2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <drm/intel_lpe_audio.h>
41 #include "i915_debugfs.h"
43 #include "intel_atomic.h"
44 #include "intel_audio.h"
45 #include "intel_connector.h"
46 #include "intel_ddi.h"
47 #include "intel_display_types.h"
49 #include "intel_dpio_phy.h"
50 #include "intel_fifo_underrun.h"
51 #include "intel_gmbus.h"
52 #include "intel_hdcp.h"
53 #include "intel_hdmi.h"
54 #include "intel_hotplug.h"
55 #include "intel_lspcon.h"
56 #include "intel_panel.h"
57 #include "intel_sdvo.h"
58 #include "intel_sideband.h"
60 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
62 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
66 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
68 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
69 struct drm_i915_private *dev_priv = to_i915(dev);
72 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
75 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
76 "HDMI port enabled, expecting disabled\n");
80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
81 enum transcoder cpu_transcoder)
83 drm_WARN(&dev_priv->drm,
84 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
85 TRANS_DDI_FUNC_ENABLE,
86 "HDMI transcoder function enabled, expecting disabled\n");
89 struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder)
91 struct intel_digital_port *dig_port =
92 container_of(&encoder->base, struct intel_digital_port,
94 return &dig_port->hdmi;
97 static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector)
99 return enc_to_intel_hdmi(intel_attached_encoder(connector));
102 static u32 g4x_infoframe_index(unsigned int type)
105 case HDMI_PACKET_TYPE_GAMUT_METADATA:
106 return VIDEO_DIP_SELECT_GAMUT;
107 case HDMI_INFOFRAME_TYPE_AVI:
108 return VIDEO_DIP_SELECT_AVI;
109 case HDMI_INFOFRAME_TYPE_SPD:
110 return VIDEO_DIP_SELECT_SPD;
111 case HDMI_INFOFRAME_TYPE_VENDOR:
112 return VIDEO_DIP_SELECT_VENDOR;
119 static u32 g4x_infoframe_enable(unsigned int type)
122 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
123 return VIDEO_DIP_ENABLE_GCP;
124 case HDMI_PACKET_TYPE_GAMUT_METADATA:
125 return VIDEO_DIP_ENABLE_GAMUT;
128 case HDMI_INFOFRAME_TYPE_AVI:
129 return VIDEO_DIP_ENABLE_AVI;
130 case HDMI_INFOFRAME_TYPE_SPD:
131 return VIDEO_DIP_ENABLE_SPD;
132 case HDMI_INFOFRAME_TYPE_VENDOR:
133 return VIDEO_DIP_ENABLE_VENDOR;
134 case HDMI_INFOFRAME_TYPE_DRM:
142 static u32 hsw_infoframe_enable(unsigned int type)
145 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
146 return VIDEO_DIP_ENABLE_GCP_HSW;
147 case HDMI_PACKET_TYPE_GAMUT_METADATA:
148 return VIDEO_DIP_ENABLE_GMP_HSW;
150 return VIDEO_DIP_ENABLE_VSC_HSW;
152 return VDIP_ENABLE_PPS;
153 case HDMI_INFOFRAME_TYPE_AVI:
154 return VIDEO_DIP_ENABLE_AVI_HSW;
155 case HDMI_INFOFRAME_TYPE_SPD:
156 return VIDEO_DIP_ENABLE_SPD_HSW;
157 case HDMI_INFOFRAME_TYPE_VENDOR:
158 return VIDEO_DIP_ENABLE_VS_HSW;
159 case HDMI_INFOFRAME_TYPE_DRM:
160 return VIDEO_DIP_ENABLE_DRM_GLK;
168 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
169 enum transcoder cpu_transcoder,
174 case HDMI_PACKET_TYPE_GAMUT_METADATA:
175 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
177 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
179 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
180 case HDMI_INFOFRAME_TYPE_AVI:
181 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
182 case HDMI_INFOFRAME_TYPE_SPD:
183 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
184 case HDMI_INFOFRAME_TYPE_VENDOR:
185 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
186 case HDMI_INFOFRAME_TYPE_DRM:
187 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
190 return INVALID_MMIO_REG;
194 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
199 return VIDEO_DIP_VSC_DATA_SIZE;
201 return VIDEO_DIP_PPS_DATA_SIZE;
202 case HDMI_PACKET_TYPE_GAMUT_METADATA:
203 if (INTEL_GEN(dev_priv) >= 11)
204 return VIDEO_DIP_GMP_DATA_SIZE;
206 return VIDEO_DIP_DATA_SIZE;
208 return VIDEO_DIP_DATA_SIZE;
212 static void g4x_write_infoframe(struct intel_encoder *encoder,
213 const struct intel_crtc_state *crtc_state,
215 const void *frame, ssize_t len)
217 const u32 *data = frame;
218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
219 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
222 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
223 "Writing DIP with CTL reg disabled\n");
225 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
226 val |= g4x_infoframe_index(type);
228 val &= ~g4x_infoframe_enable(type);
230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
232 for (i = 0; i < len; i += 4) {
233 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
236 /* Write every possible data byte to force correct ECC calculation. */
237 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
238 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
240 val |= g4x_infoframe_enable(type);
241 val &= ~VIDEO_DIP_FREQ_MASK;
242 val |= VIDEO_DIP_FREQ_VSYNC;
244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
245 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
248 static void g4x_read_infoframe(struct intel_encoder *encoder,
249 const struct intel_crtc_state *crtc_state,
251 void *frame, ssize_t len)
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
254 u32 val, *data = frame;
257 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
259 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
260 val |= g4x_infoframe_index(type);
262 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
264 for (i = 0; i < len; i += 4)
265 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
268 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
269 const struct intel_crtc_state *pipe_config)
271 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
272 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
274 if ((val & VIDEO_DIP_ENABLE) == 0)
277 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
280 return val & (VIDEO_DIP_ENABLE_AVI |
281 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
284 static void ibx_write_infoframe(struct intel_encoder *encoder,
285 const struct intel_crtc_state *crtc_state,
287 const void *frame, ssize_t len)
289 const u32 *data = frame;
290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
292 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
293 u32 val = intel_de_read(dev_priv, reg);
296 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
297 "Writing DIP with CTL reg disabled\n");
299 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
300 val |= g4x_infoframe_index(type);
302 val &= ~g4x_infoframe_enable(type);
304 intel_de_write(dev_priv, reg, val);
306 for (i = 0; i < len; i += 4) {
307 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
311 /* Write every possible data byte to force correct ECC calculation. */
312 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
313 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
315 val |= g4x_infoframe_enable(type);
316 val &= ~VIDEO_DIP_FREQ_MASK;
317 val |= VIDEO_DIP_FREQ_VSYNC;
319 intel_de_write(dev_priv, reg, val);
320 intel_de_posting_read(dev_priv, reg);
323 static void ibx_read_infoframe(struct intel_encoder *encoder,
324 const struct intel_crtc_state *crtc_state,
326 void *frame, ssize_t len)
328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
329 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
330 u32 val, *data = frame;
333 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
335 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
336 val |= g4x_infoframe_index(type);
338 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
340 for (i = 0; i < len; i += 4)
341 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
344 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
348 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
349 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
350 u32 val = intel_de_read(dev_priv, reg);
352 if ((val & VIDEO_DIP_ENABLE) == 0)
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
363 static void cpt_write_infoframe(struct intel_encoder *encoder,
364 const struct intel_crtc_state *crtc_state,
366 const void *frame, ssize_t len)
368 const u32 *data = frame;
369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
371 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
372 u32 val = intel_de_read(dev_priv, reg);
375 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
376 "Writing DIP with CTL reg disabled\n");
378 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
379 val |= g4x_infoframe_index(type);
381 /* The DIP control register spec says that we need to update the AVI
382 * infoframe without clearing its enable bit */
383 if (type != HDMI_INFOFRAME_TYPE_AVI)
384 val &= ~g4x_infoframe_enable(type);
386 intel_de_write(dev_priv, reg, val);
388 for (i = 0; i < len; i += 4) {
389 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
393 /* Write every possible data byte to force correct ECC calculation. */
394 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
395 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
397 val |= g4x_infoframe_enable(type);
398 val &= ~VIDEO_DIP_FREQ_MASK;
399 val |= VIDEO_DIP_FREQ_VSYNC;
401 intel_de_write(dev_priv, reg, val);
402 intel_de_posting_read(dev_priv, reg);
405 static void cpt_read_infoframe(struct intel_encoder *encoder,
406 const struct intel_crtc_state *crtc_state,
408 void *frame, ssize_t len)
410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
412 u32 val, *data = frame;
415 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
417 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
418 val |= g4x_infoframe_index(type);
420 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
422 for (i = 0; i < len; i += 4)
423 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
426 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
427 const struct intel_crtc_state *pipe_config)
429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
430 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
431 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
433 if ((val & VIDEO_DIP_ENABLE) == 0)
436 return val & (VIDEO_DIP_ENABLE_AVI |
437 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
438 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
441 static void vlv_write_infoframe(struct intel_encoder *encoder,
442 const struct intel_crtc_state *crtc_state,
444 const void *frame, ssize_t len)
446 const u32 *data = frame;
447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
449 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
450 u32 val = intel_de_read(dev_priv, reg);
453 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
454 "Writing DIP with CTL reg disabled\n");
456 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
457 val |= g4x_infoframe_index(type);
459 val &= ~g4x_infoframe_enable(type);
461 intel_de_write(dev_priv, reg, val);
463 for (i = 0; i < len; i += 4) {
464 intel_de_write(dev_priv,
465 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
468 /* Write every possible data byte to force correct ECC calculation. */
469 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
470 intel_de_write(dev_priv,
471 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
473 val |= g4x_infoframe_enable(type);
474 val &= ~VIDEO_DIP_FREQ_MASK;
475 val |= VIDEO_DIP_FREQ_VSYNC;
477 intel_de_write(dev_priv, reg, val);
478 intel_de_posting_read(dev_priv, reg);
481 static void vlv_read_infoframe(struct intel_encoder *encoder,
482 const struct intel_crtc_state *crtc_state,
484 void *frame, ssize_t len)
486 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
488 u32 val, *data = frame;
491 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
493 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
494 val |= g4x_infoframe_index(type);
496 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
498 for (i = 0; i < len; i += 4)
499 *data++ = intel_de_read(dev_priv,
500 VLV_TVIDEO_DIP_DATA(crtc->pipe));
503 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
504 const struct intel_crtc_state *pipe_config)
506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
507 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
508 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
510 if ((val & VIDEO_DIP_ENABLE) == 0)
513 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
516 return val & (VIDEO_DIP_ENABLE_AVI |
517 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
518 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
521 void hsw_write_infoframe(struct intel_encoder *encoder,
522 const struct intel_crtc_state *crtc_state,
524 const void *frame, ssize_t len)
526 const u32 *data = frame;
527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
529 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
532 u32 val = intel_de_read(dev_priv, ctl_reg);
534 data_size = hsw_dip_data_size(dev_priv, type);
536 drm_WARN_ON(&dev_priv->drm, len > data_size);
538 val &= ~hsw_infoframe_enable(type);
539 intel_de_write(dev_priv, ctl_reg, val);
541 for (i = 0; i < len; i += 4) {
542 intel_de_write(dev_priv,
543 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
547 /* Write every possible data byte to force correct ECC calculation. */
548 for (; i < data_size; i += 4)
549 intel_de_write(dev_priv,
550 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
553 val |= hsw_infoframe_enable(type);
554 intel_de_write(dev_priv, ctl_reg, val);
555 intel_de_posting_read(dev_priv, ctl_reg);
558 void hsw_read_infoframe(struct intel_encoder *encoder,
559 const struct intel_crtc_state *crtc_state,
560 unsigned int type, void *frame, ssize_t len)
562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
563 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
564 u32 val, *data = frame;
567 val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder));
569 for (i = 0; i < len; i += 4)
570 *data++ = intel_de_read(dev_priv,
571 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
574 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
575 const struct intel_crtc_state *pipe_config)
577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
578 u32 val = intel_de_read(dev_priv,
579 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
582 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
583 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
584 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
586 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
587 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
592 static const u8 infoframe_type_to_idx[] = {
593 HDMI_PACKET_TYPE_GENERAL_CONTROL,
594 HDMI_PACKET_TYPE_GAMUT_METADATA,
596 HDMI_INFOFRAME_TYPE_AVI,
597 HDMI_INFOFRAME_TYPE_SPD,
598 HDMI_INFOFRAME_TYPE_VENDOR,
599 HDMI_INFOFRAME_TYPE_DRM,
602 u32 intel_hdmi_infoframe_enable(unsigned int type)
606 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
607 if (infoframe_type_to_idx[i] == type)
614 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
615 const struct intel_crtc_state *crtc_state)
617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
618 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
622 val = dig_port->infoframes_enabled(encoder, crtc_state);
624 /* map from hardware bits to dip idx */
625 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
626 unsigned int type = infoframe_type_to_idx[i];
628 if (HAS_DDI(dev_priv)) {
629 if (val & hsw_infoframe_enable(type))
632 if (val & g4x_infoframe_enable(type))
641 * The data we write to the DIP data buffer registers is 1 byte bigger than the
642 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
643 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
644 * used for both technologies.
646 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
647 * DW1: DB3 | DB2 | DB1 | DB0
648 * DW2: DB7 | DB6 | DB5 | DB4
651 * (HB is Header Byte, DB is Data Byte)
653 * The hdmi pack() functions don't know about that hardware specific hole so we
654 * trick them by giving an offset into the buffer and moving back the header
657 static void intel_write_infoframe(struct intel_encoder *encoder,
658 const struct intel_crtc_state *crtc_state,
659 enum hdmi_infoframe_type type,
660 const union hdmi_infoframe *frame)
662 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
663 u8 buffer[VIDEO_DIP_DATA_SIZE];
666 if ((crtc_state->infoframes.enable &
667 intel_hdmi_infoframe_enable(type)) == 0)
670 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
673 /* see comment above for the reason for this offset */
674 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
675 if (drm_WARN_ON(encoder->base.dev, len < 0))
678 /* Insert the 'hole' (see big comment above) at position 3 */
679 memmove(&buffer[0], &buffer[1], 3);
683 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
686 void intel_read_infoframe(struct intel_encoder *encoder,
687 const struct intel_crtc_state *crtc_state,
688 enum hdmi_infoframe_type type,
689 union hdmi_infoframe *frame)
691 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
692 u8 buffer[VIDEO_DIP_DATA_SIZE];
695 if ((crtc_state->infoframes.enable &
696 intel_hdmi_infoframe_enable(type)) == 0)
699 dig_port->read_infoframe(encoder, crtc_state,
700 type, buffer, sizeof(buffer));
702 /* Fill the 'hole' (see big comment above) at position 3 */
703 memmove(&buffer[1], &buffer[0], 3);
705 /* see comment above for the reason for this offset */
706 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
708 drm_dbg_kms(encoder->base.dev,
709 "Failed to unpack infoframe type 0x%02x\n", type);
713 if (frame->any.type != type)
714 drm_dbg_kms(encoder->base.dev,
715 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
716 frame->any.type, type);
720 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
721 struct intel_crtc_state *crtc_state,
722 struct drm_connector_state *conn_state)
724 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
725 const struct drm_display_mode *adjusted_mode =
726 &crtc_state->hw.adjusted_mode;
727 struct drm_connector *connector = conn_state->connector;
730 if (!crtc_state->has_infoframe)
733 crtc_state->infoframes.enable |=
734 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
736 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
741 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
742 frame->colorspace = HDMI_COLORSPACE_YUV420;
743 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
744 frame->colorspace = HDMI_COLORSPACE_YUV444;
746 frame->colorspace = HDMI_COLORSPACE_RGB;
748 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
750 /* nonsense combination */
751 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
752 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
754 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
755 drm_hdmi_avi_infoframe_quant_range(frame, connector,
757 crtc_state->limited_color_range ?
758 HDMI_QUANTIZATION_RANGE_LIMITED :
759 HDMI_QUANTIZATION_RANGE_FULL);
761 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
762 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
765 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
767 /* TODO: handle pixel repetition for YCBCR420 outputs */
769 ret = hdmi_avi_infoframe_check(frame);
770 if (drm_WARN_ON(encoder->base.dev, ret))
777 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
778 struct intel_crtc_state *crtc_state,
779 struct drm_connector_state *conn_state)
781 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
784 if (!crtc_state->has_infoframe)
787 crtc_state->infoframes.enable |=
788 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
790 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
791 if (drm_WARN_ON(encoder->base.dev, ret))
794 frame->sdi = HDMI_SPD_SDI_PC;
796 ret = hdmi_spd_infoframe_check(frame);
797 if (drm_WARN_ON(encoder->base.dev, ret))
804 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
805 struct intel_crtc_state *crtc_state,
806 struct drm_connector_state *conn_state)
808 struct hdmi_vendor_infoframe *frame =
809 &crtc_state->infoframes.hdmi.vendor.hdmi;
810 const struct drm_display_info *info =
811 &conn_state->connector->display_info;
814 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
817 crtc_state->infoframes.enable |=
818 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
820 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
821 conn_state->connector,
822 &crtc_state->hw.adjusted_mode);
823 if (drm_WARN_ON(encoder->base.dev, ret))
826 ret = hdmi_vendor_infoframe_check(frame);
827 if (drm_WARN_ON(encoder->base.dev, ret))
834 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
835 struct intel_crtc_state *crtc_state,
836 struct drm_connector_state *conn_state)
838 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
839 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
842 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
845 if (!crtc_state->has_infoframe)
848 if (!conn_state->hdr_output_metadata)
851 crtc_state->infoframes.enable |=
852 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
854 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
856 drm_dbg_kms(&dev_priv->drm,
857 "couldn't set HDR metadata in infoframe\n");
861 ret = hdmi_drm_infoframe_check(frame);
862 if (drm_WARN_ON(&dev_priv->drm, ret))
868 static void g4x_set_infoframes(struct intel_encoder *encoder,
870 const struct intel_crtc_state *crtc_state,
871 const struct drm_connector_state *conn_state)
873 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
874 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
875 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
876 i915_reg_t reg = VIDEO_DIP_CTL;
877 u32 val = intel_de_read(dev_priv, reg);
878 u32 port = VIDEO_DIP_PORT(encoder->port);
880 assert_hdmi_port_disabled(intel_hdmi);
882 /* If the registers were not initialized yet, they might be zeroes,
883 * which means we're selecting the AVI DIP and we're setting its
884 * frequency to once. This seems to really confuse the HW and make
885 * things stop working (the register spec says the AVI always needs to
886 * be sent every VSync). So here we avoid writing to the register more
887 * than we need and also explicitly select the AVI DIP and explicitly
888 * set its frequency to every VSync. Avoiding to write it twice seems to
889 * be enough to solve the problem, but being defensive shouldn't hurt us
891 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
894 if (!(val & VIDEO_DIP_ENABLE))
896 if (port != (val & VIDEO_DIP_PORT_MASK)) {
897 drm_dbg_kms(&dev_priv->drm,
898 "video DIP still enabled on port %c\n",
899 (val & VIDEO_DIP_PORT_MASK) >> 29);
902 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
903 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
904 intel_de_write(dev_priv, reg, val);
905 intel_de_posting_read(dev_priv, reg);
909 if (port != (val & VIDEO_DIP_PORT_MASK)) {
910 if (val & VIDEO_DIP_ENABLE) {
911 drm_dbg_kms(&dev_priv->drm,
912 "video DIP already enabled on port %c\n",
913 (val & VIDEO_DIP_PORT_MASK) >> 29);
916 val &= ~VIDEO_DIP_PORT_MASK;
920 val |= VIDEO_DIP_ENABLE;
921 val &= ~(VIDEO_DIP_ENABLE_AVI |
922 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
924 intel_de_write(dev_priv, reg, val);
925 intel_de_posting_read(dev_priv, reg);
927 intel_write_infoframe(encoder, crtc_state,
928 HDMI_INFOFRAME_TYPE_AVI,
929 &crtc_state->infoframes.avi);
930 intel_write_infoframe(encoder, crtc_state,
931 HDMI_INFOFRAME_TYPE_SPD,
932 &crtc_state->infoframes.spd);
933 intel_write_infoframe(encoder, crtc_state,
934 HDMI_INFOFRAME_TYPE_VENDOR,
935 &crtc_state->infoframes.hdmi);
939 * Determine if default_phase=1 can be indicated in the GCP infoframe.
941 * From HDMI specification 1.4a:
942 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
943 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
944 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
945 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
948 static bool gcp_default_phase_possible(int pipe_bpp,
949 const struct drm_display_mode *mode)
951 unsigned int pixels_per_group;
955 /* 4 pixels in 5 clocks */
956 pixels_per_group = 4;
959 /* 2 pixels in 3 clocks */
960 pixels_per_group = 2;
963 /* 1 pixel in 2 clocks */
964 pixels_per_group = 1;
967 /* phase information not relevant for 8bpc */
971 return mode->crtc_hdisplay % pixels_per_group == 0 &&
972 mode->crtc_htotal % pixels_per_group == 0 &&
973 mode->crtc_hblank_start % pixels_per_group == 0 &&
974 mode->crtc_hblank_end % pixels_per_group == 0 &&
975 mode->crtc_hsync_start % pixels_per_group == 0 &&
976 mode->crtc_hsync_end % pixels_per_group == 0 &&
977 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
978 mode->crtc_htotal/2 % pixels_per_group == 0);
981 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
982 const struct intel_crtc_state *crtc_state,
983 const struct drm_connector_state *conn_state)
985 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
986 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
989 if ((crtc_state->infoframes.enable &
990 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
993 if (HAS_DDI(dev_priv))
994 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
995 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
996 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
997 else if (HAS_PCH_SPLIT(dev_priv))
998 reg = TVIDEO_DIP_GCP(crtc->pipe);
1002 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
1007 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
1008 struct intel_crtc_state *crtc_state)
1010 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1011 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1014 if ((crtc_state->infoframes.enable &
1015 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1018 if (HAS_DDI(dev_priv))
1019 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1020 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1021 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1022 else if (HAS_PCH_SPLIT(dev_priv))
1023 reg = TVIDEO_DIP_GCP(crtc->pipe);
1027 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1030 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1031 struct intel_crtc_state *crtc_state,
1032 struct drm_connector_state *conn_state)
1034 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1036 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1039 crtc_state->infoframes.enable |=
1040 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1042 /* Indicate color indication for deep color mode */
1043 if (crtc_state->pipe_bpp > 24)
1044 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1046 /* Enable default_phase whenever the display mode is suitably aligned */
1047 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1048 &crtc_state->hw.adjusted_mode))
1049 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1052 static void ibx_set_infoframes(struct intel_encoder *encoder,
1054 const struct intel_crtc_state *crtc_state,
1055 const struct drm_connector_state *conn_state)
1057 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1059 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1060 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1061 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1062 u32 val = intel_de_read(dev_priv, reg);
1063 u32 port = VIDEO_DIP_PORT(encoder->port);
1065 assert_hdmi_port_disabled(intel_hdmi);
1067 /* See the big comment in g4x_set_infoframes() */
1068 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1071 if (!(val & VIDEO_DIP_ENABLE))
1073 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1074 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1075 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1076 intel_de_write(dev_priv, reg, val);
1077 intel_de_posting_read(dev_priv, reg);
1081 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1082 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1083 "DIP already enabled on port %c\n",
1084 (val & VIDEO_DIP_PORT_MASK) >> 29);
1085 val &= ~VIDEO_DIP_PORT_MASK;
1089 val |= VIDEO_DIP_ENABLE;
1090 val &= ~(VIDEO_DIP_ENABLE_AVI |
1091 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1092 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1094 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1095 val |= VIDEO_DIP_ENABLE_GCP;
1097 intel_de_write(dev_priv, reg, val);
1098 intel_de_posting_read(dev_priv, reg);
1100 intel_write_infoframe(encoder, crtc_state,
1101 HDMI_INFOFRAME_TYPE_AVI,
1102 &crtc_state->infoframes.avi);
1103 intel_write_infoframe(encoder, crtc_state,
1104 HDMI_INFOFRAME_TYPE_SPD,
1105 &crtc_state->infoframes.spd);
1106 intel_write_infoframe(encoder, crtc_state,
1107 HDMI_INFOFRAME_TYPE_VENDOR,
1108 &crtc_state->infoframes.hdmi);
1111 static void cpt_set_infoframes(struct intel_encoder *encoder,
1113 const struct intel_crtc_state *crtc_state,
1114 const struct drm_connector_state *conn_state)
1116 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1118 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1119 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1120 u32 val = intel_de_read(dev_priv, reg);
1122 assert_hdmi_port_disabled(intel_hdmi);
1124 /* See the big comment in g4x_set_infoframes() */
1125 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1128 if (!(val & VIDEO_DIP_ENABLE))
1130 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1131 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1132 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1133 intel_de_write(dev_priv, reg, val);
1134 intel_de_posting_read(dev_priv, reg);
1138 /* Set both together, unset both together: see the spec. */
1139 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1140 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1141 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1143 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1144 val |= VIDEO_DIP_ENABLE_GCP;
1146 intel_de_write(dev_priv, reg, val);
1147 intel_de_posting_read(dev_priv, reg);
1149 intel_write_infoframe(encoder, crtc_state,
1150 HDMI_INFOFRAME_TYPE_AVI,
1151 &crtc_state->infoframes.avi);
1152 intel_write_infoframe(encoder, crtc_state,
1153 HDMI_INFOFRAME_TYPE_SPD,
1154 &crtc_state->infoframes.spd);
1155 intel_write_infoframe(encoder, crtc_state,
1156 HDMI_INFOFRAME_TYPE_VENDOR,
1157 &crtc_state->infoframes.hdmi);
1160 static void vlv_set_infoframes(struct intel_encoder *encoder,
1162 const struct intel_crtc_state *crtc_state,
1163 const struct drm_connector_state *conn_state)
1165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1167 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1168 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1169 u32 val = intel_de_read(dev_priv, reg);
1170 u32 port = VIDEO_DIP_PORT(encoder->port);
1172 assert_hdmi_port_disabled(intel_hdmi);
1174 /* See the big comment in g4x_set_infoframes() */
1175 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1178 if (!(val & VIDEO_DIP_ENABLE))
1180 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1181 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1182 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1183 intel_de_write(dev_priv, reg, val);
1184 intel_de_posting_read(dev_priv, reg);
1188 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1189 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1190 "DIP already enabled on port %c\n",
1191 (val & VIDEO_DIP_PORT_MASK) >> 29);
1192 val &= ~VIDEO_DIP_PORT_MASK;
1196 val |= VIDEO_DIP_ENABLE;
1197 val &= ~(VIDEO_DIP_ENABLE_AVI |
1198 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1199 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1201 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1202 val |= VIDEO_DIP_ENABLE_GCP;
1204 intel_de_write(dev_priv, reg, val);
1205 intel_de_posting_read(dev_priv, reg);
1207 intel_write_infoframe(encoder, crtc_state,
1208 HDMI_INFOFRAME_TYPE_AVI,
1209 &crtc_state->infoframes.avi);
1210 intel_write_infoframe(encoder, crtc_state,
1211 HDMI_INFOFRAME_TYPE_SPD,
1212 &crtc_state->infoframes.spd);
1213 intel_write_infoframe(encoder, crtc_state,
1214 HDMI_INFOFRAME_TYPE_VENDOR,
1215 &crtc_state->infoframes.hdmi);
1218 static void hsw_set_infoframes(struct intel_encoder *encoder,
1220 const struct intel_crtc_state *crtc_state,
1221 const struct drm_connector_state *conn_state)
1223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1224 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1225 u32 val = intel_de_read(dev_priv, reg);
1227 assert_hdmi_transcoder_func_disabled(dev_priv,
1228 crtc_state->cpu_transcoder);
1230 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1231 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1232 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1233 VIDEO_DIP_ENABLE_DRM_GLK);
1236 intel_de_write(dev_priv, reg, val);
1237 intel_de_posting_read(dev_priv, reg);
1241 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1242 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1244 intel_de_write(dev_priv, reg, val);
1245 intel_de_posting_read(dev_priv, reg);
1247 intel_write_infoframe(encoder, crtc_state,
1248 HDMI_INFOFRAME_TYPE_AVI,
1249 &crtc_state->infoframes.avi);
1250 intel_write_infoframe(encoder, crtc_state,
1251 HDMI_INFOFRAME_TYPE_SPD,
1252 &crtc_state->infoframes.spd);
1253 intel_write_infoframe(encoder, crtc_state,
1254 HDMI_INFOFRAME_TYPE_VENDOR,
1255 &crtc_state->infoframes.hdmi);
1256 intel_write_infoframe(encoder, crtc_state,
1257 HDMI_INFOFRAME_TYPE_DRM,
1258 &crtc_state->infoframes.drm);
1261 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1263 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1264 struct i2c_adapter *adapter =
1265 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1267 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1270 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1271 enable ? "Enabling" : "Disabling");
1273 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1277 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1278 unsigned int offset, void *buffer, size_t size)
1280 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1281 struct intel_hdmi *hdmi = &dig_port->hdmi;
1282 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1285 u8 start = offset & 0xff;
1286 struct i2c_msg msgs[] = {
1288 .addr = DRM_HDCP_DDC_ADDR,
1294 .addr = DRM_HDCP_DDC_ADDR,
1300 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1301 if (ret == ARRAY_SIZE(msgs))
1303 return ret >= 0 ? -EIO : ret;
1306 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1307 unsigned int offset, void *buffer, size_t size)
1309 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1310 struct intel_hdmi *hdmi = &dig_port->hdmi;
1311 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1317 write_buf = kzalloc(size + 1, GFP_KERNEL);
1321 write_buf[0] = offset & 0xff;
1322 memcpy(&write_buf[1], buffer, size);
1324 msg.addr = DRM_HDCP_DDC_ADDR;
1327 msg.buf = write_buf;
1329 ret = i2c_transfer(adapter, &msg, 1);
1340 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1343 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1344 struct intel_hdmi *hdmi = &dig_port->hdmi;
1345 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1349 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1352 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1357 ret = intel_gmbus_output_aksv(adapter);
1359 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1365 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1368 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1371 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1374 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1380 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1383 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1387 bstatus, DRM_HDCP_BSTATUS_LEN);
1389 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1395 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1396 bool *repeater_present)
1398 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1402 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1404 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1408 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1413 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1416 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1420 ri_prime, DRM_HDCP_RI_LEN);
1422 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1428 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1431 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1437 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1441 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1446 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1447 int num_downstream, u8 *ksv_fifo)
1449 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1451 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1452 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1454 drm_dbg_kms(&i915->drm,
1455 "Read ksv fifo over DDC failed (%d)\n", ret);
1462 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1465 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1468 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1471 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1472 part, DRM_HDCP_V_PRIME_PART_LEN);
1474 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1479 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1480 enum transcoder cpu_transcoder)
1482 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1483 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1484 struct drm_crtc *crtc = connector->base.state->crtc;
1485 struct intel_crtc *intel_crtc = container_of(crtc,
1486 struct intel_crtc, base);
1491 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe));
1492 if (scanline > 100 && scanline < 200)
1494 usleep_range(25, 50);
1497 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
1500 drm_err(&dev_priv->drm,
1501 "Disable HDCP signalling failed (%d)\n", ret);
1504 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
1507 drm_err(&dev_priv->drm,
1508 "Enable HDCP signalling failed (%d)\n", ret);
1516 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1517 enum transcoder cpu_transcoder,
1520 struct intel_hdmi *hdmi = &dig_port->hdmi;
1521 struct intel_connector *connector = hdmi->attached_connector;
1522 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1526 usleep_range(6, 60); /* Bspec says >= 6us */
1528 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
1531 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1532 enable ? "Enable" : "Disable", ret);
1537 * WA: To fix incorrect positioning of the window of
1538 * opportunity and enc_en signalling in KABYLAKE.
1540 if (IS_KABYLAKE(dev_priv) && enable)
1541 return kbl_repositioning_enc_en_signal(connector,
1548 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1549 struct intel_connector *connector)
1551 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1552 enum port port = dig_port->base.port;
1553 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1557 u8 shim[DRM_HDCP_RI_LEN];
1560 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1564 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1566 /* Wait for Ri prime match */
1567 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1568 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1569 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1570 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1571 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1579 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1580 struct intel_connector *connector)
1582 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1585 for (retry = 0; retry < 3; retry++)
1586 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1589 drm_err(&i915->drm, "Link check failed\n");
1593 struct hdcp2_hdmi_msg_timeout {
1598 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1599 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1600 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1601 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1602 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1603 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1607 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1610 return intel_hdmi_hdcp_read(dig_port,
1611 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1613 HDCP_2_2_HDMI_RXSTATUS_LEN);
1616 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1620 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1622 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1624 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1627 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1628 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1629 return hdcp2_msg_timeout[i].timeout;
1636 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1637 u8 msg_id, bool *msg_ready,
1640 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1641 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1644 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1646 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1651 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1654 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1655 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1658 *msg_ready = *msg_sz;
1664 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1665 u8 msg_id, bool paired)
1667 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1668 bool msg_ready = false;
1672 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1676 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1679 !ret && msg_ready && msg_sz, timeout * 1000,
1682 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1683 msg_id, ret, timeout);
1685 return ret ? ret : msg_sz;
1689 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1690 void *buf, size_t size)
1692 unsigned int offset;
1694 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1695 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1699 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1700 u8 msg_id, void *buf, size_t size)
1702 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1703 struct intel_hdmi *hdmi = &dig_port->hdmi;
1704 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1705 unsigned int offset;
1708 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1714 * Available msg size should be equal to or lesser than the
1718 drm_dbg_kms(&i915->drm,
1719 "msg_sz(%zd) is more than exp size(%zu)\n",
1724 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1725 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1727 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1734 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
1736 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1739 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1744 * Re-auth request and Link Integrity Failures are represented by
1745 * same bit. i.e reauth_req.
1747 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1748 ret = HDCP_REAUTH_REQUEST;
1749 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1750 ret = HDCP_TOPOLOGY_CHANGE;
1756 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1763 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1764 &hdcp2_version, sizeof(hdcp2_version));
1765 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1771 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1772 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1773 .read_bksv = intel_hdmi_hdcp_read_bksv,
1774 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1775 .repeater_present = intel_hdmi_hdcp_repeater_present,
1776 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1777 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1778 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1779 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1780 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1781 .check_link = intel_hdmi_hdcp_check_link,
1782 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1783 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1784 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1785 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1786 .protocol = HDCP_PROTOCOL_HDMI,
1789 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1790 const struct intel_crtc_state *crtc_state)
1792 struct drm_device *dev = encoder->base.dev;
1793 struct drm_i915_private *dev_priv = to_i915(dev);
1794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1795 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1796 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1799 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1801 hdmi_val = SDVO_ENCODING_HDMI;
1802 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1803 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1804 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1805 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1806 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1807 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1809 if (crtc_state->pipe_bpp > 24)
1810 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1812 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1814 if (crtc_state->has_hdmi_sink)
1815 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1817 if (HAS_PCH_CPT(dev_priv))
1818 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1819 else if (IS_CHERRYVIEW(dev_priv))
1820 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1822 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1824 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
1825 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1828 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1831 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1832 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1833 intel_wakeref_t wakeref;
1836 wakeref = intel_display_power_get_if_enabled(dev_priv,
1837 encoder->power_domain);
1841 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1843 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1848 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1849 struct intel_crtc_state *pipe_config)
1851 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1852 struct drm_device *dev = encoder->base.dev;
1853 struct drm_i915_private *dev_priv = to_i915(dev);
1857 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1859 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1861 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1862 flags |= DRM_MODE_FLAG_PHSYNC;
1864 flags |= DRM_MODE_FLAG_NHSYNC;
1866 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1867 flags |= DRM_MODE_FLAG_PVSYNC;
1869 flags |= DRM_MODE_FLAG_NVSYNC;
1871 if (tmp & HDMI_MODE_SELECT_HDMI)
1872 pipe_config->has_hdmi_sink = true;
1874 pipe_config->infoframes.enable |=
1875 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1877 if (pipe_config->infoframes.enable)
1878 pipe_config->has_infoframe = true;
1880 if (tmp & HDMI_AUDIO_ENABLE)
1881 pipe_config->has_audio = true;
1883 if (!HAS_PCH_SPLIT(dev_priv) &&
1884 tmp & HDMI_COLOR_RANGE_16_235)
1885 pipe_config->limited_color_range = true;
1887 pipe_config->hw.adjusted_mode.flags |= flags;
1889 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1890 dotclock = pipe_config->port_clock * 2 / 3;
1892 dotclock = pipe_config->port_clock;
1894 if (pipe_config->pixel_multiplier)
1895 dotclock /= pipe_config->pixel_multiplier;
1897 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1899 pipe_config->lane_count = 4;
1901 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1903 intel_read_infoframe(encoder, pipe_config,
1904 HDMI_INFOFRAME_TYPE_AVI,
1905 &pipe_config->infoframes.avi);
1906 intel_read_infoframe(encoder, pipe_config,
1907 HDMI_INFOFRAME_TYPE_SPD,
1908 &pipe_config->infoframes.spd);
1909 intel_read_infoframe(encoder, pipe_config,
1910 HDMI_INFOFRAME_TYPE_VENDOR,
1911 &pipe_config->infoframes.hdmi);
1914 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1915 const struct intel_crtc_state *pipe_config,
1916 const struct drm_connector_state *conn_state)
1918 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1919 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1921 drm_WARN_ON(&i915->drm, !pipe_config->has_hdmi_sink);
1922 drm_dbg_kms(&i915->drm, "Enabling HDMI audio on pipe %c\n",
1923 pipe_name(crtc->pipe));
1924 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1927 static void g4x_enable_hdmi(struct intel_atomic_state *state,
1928 struct intel_encoder *encoder,
1929 const struct intel_crtc_state *pipe_config,
1930 const struct drm_connector_state *conn_state)
1932 struct drm_device *dev = encoder->base.dev;
1933 struct drm_i915_private *dev_priv = to_i915(dev);
1934 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1937 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1939 temp |= SDVO_ENABLE;
1940 if (pipe_config->has_audio)
1941 temp |= HDMI_AUDIO_ENABLE;
1943 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1944 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1946 if (pipe_config->has_audio)
1947 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1950 static void ibx_enable_hdmi(struct intel_atomic_state *state,
1951 struct intel_encoder *encoder,
1952 const struct intel_crtc_state *pipe_config,
1953 const struct drm_connector_state *conn_state)
1955 struct drm_device *dev = encoder->base.dev;
1956 struct drm_i915_private *dev_priv = to_i915(dev);
1957 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1960 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1962 temp |= SDVO_ENABLE;
1963 if (pipe_config->has_audio)
1964 temp |= HDMI_AUDIO_ENABLE;
1967 * HW workaround, need to write this twice for issue
1968 * that may result in first write getting masked.
1970 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1971 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1972 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1973 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1976 * HW workaround, need to toggle enable bit off and on
1977 * for 12bpc with pixel repeat.
1979 * FIXME: BSpec says this should be done at the end of
1980 * of the modeset sequence, so not sure if this isn't too soon.
1982 if (pipe_config->pipe_bpp > 24 &&
1983 pipe_config->pixel_multiplier > 1) {
1984 intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
1985 temp & ~SDVO_ENABLE);
1986 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1989 * HW workaround, need to write this twice for issue
1990 * that may result in first write getting masked.
1992 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1993 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1994 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1995 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1998 if (pipe_config->has_audio)
1999 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
2002 static void cpt_enable_hdmi(struct intel_atomic_state *state,
2003 struct intel_encoder *encoder,
2004 const struct intel_crtc_state *pipe_config,
2005 const struct drm_connector_state *conn_state)
2007 struct drm_device *dev = encoder->base.dev;
2008 struct drm_i915_private *dev_priv = to_i915(dev);
2009 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2010 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2011 enum pipe pipe = crtc->pipe;
2014 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
2016 temp |= SDVO_ENABLE;
2017 if (pipe_config->has_audio)
2018 temp |= HDMI_AUDIO_ENABLE;
2021 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
2023 * The procedure for 12bpc is as follows:
2024 * 1. disable HDMI clock gating
2025 * 2. enable HDMI with 8bpc
2026 * 3. enable HDMI with 12bpc
2027 * 4. enable HDMI clock gating
2030 if (pipe_config->pipe_bpp > 24) {
2031 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
2032 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
2034 temp &= ~SDVO_COLOR_FORMAT_MASK;
2035 temp |= SDVO_COLOR_FORMAT_8bpc;
2038 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2039 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2041 if (pipe_config->pipe_bpp > 24) {
2042 temp &= ~SDVO_COLOR_FORMAT_MASK;
2043 temp |= HDMI_COLOR_FORMAT_12bpc;
2045 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2046 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2048 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
2049 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
2052 if (pipe_config->has_audio)
2053 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
2056 static void vlv_enable_hdmi(struct intel_atomic_state *state,
2057 struct intel_encoder *encoder,
2058 const struct intel_crtc_state *pipe_config,
2059 const struct drm_connector_state *conn_state)
2063 static void intel_disable_hdmi(struct intel_atomic_state *state,
2064 struct intel_encoder *encoder,
2065 const struct intel_crtc_state *old_crtc_state,
2066 const struct drm_connector_state *old_conn_state)
2068 struct drm_device *dev = encoder->base.dev;
2069 struct drm_i915_private *dev_priv = to_i915(dev);
2070 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2071 struct intel_digital_port *dig_port =
2072 hdmi_to_dig_port(intel_hdmi);
2073 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2076 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
2078 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2079 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2080 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2083 * HW workaround for IBX, we need to move the port
2084 * to transcoder A after disabling it to allow the
2085 * matching DP port to be enabled on transcoder A.
2087 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2089 * We get CPU/PCH FIFO underruns on the other pipe when
2090 * doing the workaround. Sweep them under the rug.
2092 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2093 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2095 temp &= ~SDVO_PIPE_SEL_MASK;
2096 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2098 * HW workaround, need to write this twice for issue
2099 * that may result in first write getting masked.
2101 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2102 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2103 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2104 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2106 temp &= ~SDVO_ENABLE;
2107 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2108 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2110 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2111 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2112 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2115 dig_port->set_infoframes(encoder,
2117 old_crtc_state, old_conn_state);
2119 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2122 static void g4x_disable_hdmi(struct intel_atomic_state *state,
2123 struct intel_encoder *encoder,
2124 const struct intel_crtc_state *old_crtc_state,
2125 const struct drm_connector_state *old_conn_state)
2127 if (old_crtc_state->has_audio)
2128 intel_audio_codec_disable(encoder,
2129 old_crtc_state, old_conn_state);
2131 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
2134 static void pch_disable_hdmi(struct intel_atomic_state *state,
2135 struct intel_encoder *encoder,
2136 const struct intel_crtc_state *old_crtc_state,
2137 const struct drm_connector_state *old_conn_state)
2139 if (old_crtc_state->has_audio)
2140 intel_audio_codec_disable(encoder,
2141 old_crtc_state, old_conn_state);
2144 static void pch_post_disable_hdmi(struct intel_atomic_state *state,
2145 struct intel_encoder *encoder,
2146 const struct intel_crtc_state *old_crtc_state,
2147 const struct drm_connector_state *old_conn_state)
2149 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
2152 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2155 int max_tmds_clock, vbt_max_tmds_clock;
2157 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2158 max_tmds_clock = 594000;
2159 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2160 max_tmds_clock = 300000;
2161 else if (INTEL_GEN(dev_priv) >= 5)
2162 max_tmds_clock = 225000;
2164 max_tmds_clock = 165000;
2166 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
2167 if (vbt_max_tmds_clock)
2168 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
2170 return max_tmds_clock;
2173 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
2174 const struct drm_connector_state *conn_state)
2176 return hdmi->has_hdmi_sink &&
2177 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
2180 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2181 bool respect_downstream_limits,
2184 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2185 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2187 if (respect_downstream_limits) {
2188 struct intel_connector *connector = hdmi->attached_connector;
2189 const struct drm_display_info *info = &connector->base.display_info;
2191 if (hdmi->dp_dual_mode.max_tmds_clock)
2192 max_tmds_clock = min(max_tmds_clock,
2193 hdmi->dp_dual_mode.max_tmds_clock);
2195 if (info->max_tmds_clock)
2196 max_tmds_clock = min(max_tmds_clock,
2197 info->max_tmds_clock);
2198 else if (!has_hdmi_sink)
2199 max_tmds_clock = min(max_tmds_clock, 165000);
2202 return max_tmds_clock;
2205 static enum drm_mode_status
2206 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2207 int clock, bool respect_downstream_limits,
2210 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2213 return MODE_CLOCK_LOW;
2214 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
2216 return MODE_CLOCK_HIGH;
2218 /* BXT DPLL can't generate 223-240 MHz */
2219 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2220 return MODE_CLOCK_RANGE;
2222 /* CHV DPLL can't generate 216-240 MHz */
2223 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2224 return MODE_CLOCK_RANGE;
2229 static enum drm_mode_status
2230 intel_hdmi_mode_valid(struct drm_connector *connector,
2231 struct drm_display_mode *mode)
2233 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2234 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2235 struct drm_i915_private *dev_priv = to_i915(dev);
2236 enum drm_mode_status status;
2237 int clock = mode->clock;
2238 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2239 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
2241 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2242 return MODE_NO_DBLESCAN;
2244 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2247 if (clock > max_dotclk)
2248 return MODE_CLOCK_HIGH;
2250 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2252 return MODE_CLOCK_LOW;
2256 if (drm_mode_is_420_only(&connector->display_info, mode))
2259 /* check if we can do 8bpc */
2260 status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink);
2262 if (has_hdmi_sink) {
2263 /* if we can't do 8bpc we may still be able to do 12bpc */
2264 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2265 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2266 true, has_hdmi_sink);
2268 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2269 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2270 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2271 true, has_hdmi_sink);
2273 if (status != MODE_OK)
2276 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2279 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2280 int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2282 struct drm_atomic_state *state = crtc_state->uapi.state;
2283 struct drm_connector_state *connector_state;
2284 struct drm_connector *connector;
2287 if (crtc_state->pipe_bpp < bpc * 3)
2293 for_each_new_connector_in_state(state, connector, connector_state, i) {
2294 const struct drm_display_info *info = &connector->display_info;
2296 if (connector_state->crtc != crtc_state->uapi.crtc)
2299 if (ycbcr420_output) {
2300 const struct drm_hdmi_info *hdmi = &info->hdmi;
2302 if (bpc == 12 && !(hdmi->y420_dc_modes &
2303 DRM_EDID_YCBCR420_DC_36))
2305 else if (bpc == 10 && !(hdmi->y420_dc_modes &
2306 DRM_EDID_YCBCR420_DC_30))
2309 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2310 DRM_EDID_HDMI_DC_36))
2312 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2313 DRM_EDID_HDMI_DC_30))
2321 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2324 struct drm_i915_private *dev_priv =
2325 to_i915(crtc_state->uapi.crtc->dev);
2326 const struct drm_display_mode *adjusted_mode =
2327 &crtc_state->hw.adjusted_mode;
2329 if (HAS_GMCH(dev_priv))
2332 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2336 * HDMI deep color affects the clocks, so it's only possible
2337 * when not cloning with other encoder types.
2339 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2342 /* Display Wa_1405510057:icl,ehl */
2343 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2344 bpc == 10 && IS_GEN(dev_priv, 11) &&
2345 (adjusted_mode->crtc_hblank_end -
2346 adjusted_mode->crtc_hblank_start) % 8 == 2)
2349 return intel_hdmi_deep_color_possible(crtc_state, bpc,
2350 crtc_state->has_hdmi_sink,
2351 crtc_state->output_format ==
2352 INTEL_OUTPUT_FORMAT_YCBCR420);
2356 intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
2357 const struct drm_connector_state *conn_state)
2359 struct drm_connector *connector = conn_state->connector;
2360 struct drm_i915_private *i915 = to_i915(connector->dev);
2361 const struct drm_display_mode *adjusted_mode =
2362 &crtc_state->hw.adjusted_mode;
2364 if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode))
2367 if (!connector->ycbcr_420_allowed) {
2369 "Platform doesn't support YCBCR420 output\n");
2373 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2375 return intel_pch_panel_fitting(crtc_state, conn_state);
2378 static int intel_hdmi_port_clock(int clock, int bpc)
2381 * Need to adjust the port link by:
2385 return clock * bpc / 8;
2388 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2389 struct intel_crtc_state *crtc_state,
2392 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2395 for (bpc = 12; bpc >= 10; bpc -= 2) {
2396 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2397 hdmi_port_clock_valid(intel_hdmi,
2398 intel_hdmi_port_clock(clock, bpc),
2399 true, crtc_state->has_hdmi_sink) == MODE_OK)
2406 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2407 struct intel_crtc_state *crtc_state)
2409 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2410 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2411 const struct drm_display_mode *adjusted_mode =
2412 &crtc_state->hw.adjusted_mode;
2413 int bpc, clock = adjusted_mode->crtc_clock;
2415 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2418 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2419 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2422 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2424 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2427 * pipe_bpp could already be below 8bpc due to
2428 * FDI bandwidth constraints. We shouldn't bump it
2429 * back up to 8bpc in that case.
2431 if (crtc_state->pipe_bpp > bpc * 3)
2432 crtc_state->pipe_bpp = bpc * 3;
2434 drm_dbg_kms(&i915->drm,
2435 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2436 bpc, crtc_state->pipe_bpp);
2438 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2439 false, crtc_state->has_hdmi_sink) != MODE_OK) {
2440 drm_dbg_kms(&i915->drm,
2441 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2442 crtc_state->port_clock);
2449 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2450 const struct drm_connector_state *conn_state)
2452 const struct intel_digital_connector_state *intel_conn_state =
2453 to_intel_digital_connector_state(conn_state);
2454 const struct drm_display_mode *adjusted_mode =
2455 &crtc_state->hw.adjusted_mode;
2458 * Our YCbCr output is always limited range.
2459 * crtc_state->limited_color_range only applies to RGB,
2460 * and it must never be set for YCbCr or we risk setting
2461 * some conflicting bits in PIPECONF which will mess up
2462 * the colors on the monitor.
2464 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2467 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2468 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2469 return crtc_state->has_hdmi_sink &&
2470 drm_default_rgb_quant_range(adjusted_mode) ==
2471 HDMI_QUANTIZATION_RANGE_LIMITED;
2473 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2477 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2478 const struct intel_crtc_state *crtc_state,
2479 const struct drm_connector_state *conn_state)
2481 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2482 const struct intel_digital_connector_state *intel_conn_state =
2483 to_intel_digital_connector_state(conn_state);
2485 if (!crtc_state->has_hdmi_sink)
2488 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2489 return intel_hdmi->has_audio;
2491 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2494 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2495 struct intel_crtc_state *pipe_config,
2496 struct drm_connector_state *conn_state)
2498 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2500 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2501 struct drm_connector *connector = conn_state->connector;
2502 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2505 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2508 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2509 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2512 if (pipe_config->has_hdmi_sink)
2513 pipe_config->has_infoframe = true;
2515 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2516 pipe_config->pixel_multiplier = 2;
2518 ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state);
2522 pipe_config->limited_color_range =
2523 intel_hdmi_limited_color_range(pipe_config, conn_state);
2525 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2526 pipe_config->has_pch_encoder = true;
2528 pipe_config->has_audio =
2529 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2531 ret = intel_hdmi_compute_clock(encoder, pipe_config);
2535 if (conn_state->picture_aspect_ratio)
2536 adjusted_mode->picture_aspect_ratio =
2537 conn_state->picture_aspect_ratio;
2539 pipe_config->lane_count = 4;
2541 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2542 IS_GEMINILAKE(dev_priv))) {
2543 if (scdc->scrambling.low_rates)
2544 pipe_config->hdmi_scrambling = true;
2546 if (pipe_config->port_clock > 340000) {
2547 pipe_config->hdmi_scrambling = true;
2548 pipe_config->hdmi_high_tmds_clock_ratio = true;
2552 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2555 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2556 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2560 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2561 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2565 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2566 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2570 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2571 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2579 intel_hdmi_unset_edid(struct drm_connector *connector)
2581 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2583 intel_hdmi->has_hdmi_sink = false;
2584 intel_hdmi->has_audio = false;
2586 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2587 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2589 kfree(to_intel_connector(connector)->detect_edid);
2590 to_intel_connector(connector)->detect_edid = NULL;
2594 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2596 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2597 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2598 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2599 struct i2c_adapter *adapter =
2600 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2601 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2604 * Type 1 DVI adaptors are not required to implement any
2605 * registers, so we can't always detect their presence.
2606 * Ideally we should be able to check the state of the
2607 * CONFIG1 pin, but no such luck on our hardware.
2609 * The only method left to us is to check the VBT to see
2610 * if the port is a dual mode capable DP port. But let's
2611 * only do that when we sucesfully read the EDID, to avoid
2612 * confusing log messages about DP dual mode adaptors when
2613 * there's nothing connected to the port.
2615 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2616 /* An overridden EDID imply that we want this port for testing.
2617 * Make sure not to set limits for that port.
2619 if (has_edid && !connector->override_edid &&
2620 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2621 drm_dbg_kms(&dev_priv->drm,
2622 "Assuming DP dual mode adaptor presence based on VBT\n");
2623 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2625 type = DRM_DP_DUAL_MODE_NONE;
2629 if (type == DRM_DP_DUAL_MODE_NONE)
2632 hdmi->dp_dual_mode.type = type;
2633 hdmi->dp_dual_mode.max_tmds_clock =
2634 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2636 drm_dbg_kms(&dev_priv->drm,
2637 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2638 drm_dp_get_dual_mode_type_name(type),
2639 hdmi->dp_dual_mode.max_tmds_clock);
2643 intel_hdmi_set_edid(struct drm_connector *connector)
2645 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2646 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2647 intel_wakeref_t wakeref;
2649 bool connected = false;
2650 struct i2c_adapter *i2c;
2652 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2654 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2656 edid = drm_get_edid(connector, i2c);
2658 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2659 drm_dbg_kms(&dev_priv->drm,
2660 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2661 intel_gmbus_force_bit(i2c, true);
2662 edid = drm_get_edid(connector, i2c);
2663 intel_gmbus_force_bit(i2c, false);
2666 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2668 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2670 to_intel_connector(connector)->detect_edid = edid;
2671 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2672 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2673 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2678 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2683 static enum drm_connector_status
2684 intel_hdmi_detect(struct drm_connector *connector, bool force)
2686 enum drm_connector_status status = connector_status_disconnected;
2687 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2688 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2689 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2690 intel_wakeref_t wakeref;
2692 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2693 connector->base.id, connector->name);
2695 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2696 return connector_status_disconnected;
2698 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2700 if (INTEL_GEN(dev_priv) >= 11 &&
2701 !intel_digital_port_connected(encoder))
2704 intel_hdmi_unset_edid(connector);
2706 if (intel_hdmi_set_edid(connector))
2707 status = connector_status_connected;
2710 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2712 if (status != connector_status_connected)
2713 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2716 * Make sure the refs for power wells enabled during detect are
2717 * dropped to avoid a new detect cycle triggered by HPD polling.
2719 intel_display_power_flush_work(dev_priv);
2725 intel_hdmi_force(struct drm_connector *connector)
2727 struct drm_i915_private *i915 = to_i915(connector->dev);
2729 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2730 connector->base.id, connector->name);
2732 intel_hdmi_unset_edid(connector);
2734 if (connector->status != connector_status_connected)
2737 intel_hdmi_set_edid(connector);
2740 static int intel_hdmi_get_modes(struct drm_connector *connector)
2744 edid = to_intel_connector(connector)->detect_edid;
2748 return intel_connector_update_modes(connector, edid);
2751 static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
2752 struct intel_encoder *encoder,
2753 const struct intel_crtc_state *pipe_config,
2754 const struct drm_connector_state *conn_state)
2756 struct intel_digital_port *dig_port =
2757 enc_to_dig_port(encoder);
2759 intel_hdmi_prepare(encoder, pipe_config);
2761 dig_port->set_infoframes(encoder,
2762 pipe_config->has_infoframe,
2763 pipe_config, conn_state);
2766 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
2767 struct intel_encoder *encoder,
2768 const struct intel_crtc_state *pipe_config,
2769 const struct drm_connector_state *conn_state)
2771 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2772 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2774 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2777 vlv_set_phy_signal_level(encoder, pipe_config,
2778 0x2b245f5f, 0x00002000,
2779 0x5578b83a, 0x2b247878);
2781 dig_port->set_infoframes(encoder,
2782 pipe_config->has_infoframe,
2783 pipe_config, conn_state);
2785 g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
2787 vlv_wait_port_ready(dev_priv, dig_port, 0x0);
2790 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
2791 struct intel_encoder *encoder,
2792 const struct intel_crtc_state *pipe_config,
2793 const struct drm_connector_state *conn_state)
2795 intel_hdmi_prepare(encoder, pipe_config);
2797 vlv_phy_pre_pll_enable(encoder, pipe_config);
2800 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
2801 struct intel_encoder *encoder,
2802 const struct intel_crtc_state *pipe_config,
2803 const struct drm_connector_state *conn_state)
2805 intel_hdmi_prepare(encoder, pipe_config);
2807 chv_phy_pre_pll_enable(encoder, pipe_config);
2810 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
2811 struct intel_encoder *encoder,
2812 const struct intel_crtc_state *old_crtc_state,
2813 const struct drm_connector_state *old_conn_state)
2815 chv_phy_post_pll_disable(encoder, old_crtc_state);
2818 static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
2819 struct intel_encoder *encoder,
2820 const struct intel_crtc_state *old_crtc_state,
2821 const struct drm_connector_state *old_conn_state)
2823 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2824 vlv_phy_reset_lanes(encoder, old_crtc_state);
2827 static void chv_hdmi_post_disable(struct intel_atomic_state *state,
2828 struct intel_encoder *encoder,
2829 const struct intel_crtc_state *old_crtc_state,
2830 const struct drm_connector_state *old_conn_state)
2832 struct drm_device *dev = encoder->base.dev;
2833 struct drm_i915_private *dev_priv = to_i915(dev);
2835 vlv_dpio_get(dev_priv);
2837 /* Assert data lane reset */
2838 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2840 vlv_dpio_put(dev_priv);
2843 static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
2844 struct intel_encoder *encoder,
2845 const struct intel_crtc_state *pipe_config,
2846 const struct drm_connector_state *conn_state)
2848 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2849 struct drm_device *dev = encoder->base.dev;
2850 struct drm_i915_private *dev_priv = to_i915(dev);
2852 chv_phy_pre_encoder_enable(encoder, pipe_config);
2854 /* FIXME: Program the support xxx V-dB */
2856 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
2858 dig_port->set_infoframes(encoder,
2859 pipe_config->has_infoframe,
2860 pipe_config, conn_state);
2862 g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
2864 vlv_wait_port_ready(dev_priv, dig_port, 0x0);
2866 /* Second common lane will stay alive on its own now */
2867 chv_phy_release_cl2_override(encoder);
2870 static struct i2c_adapter *
2871 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2873 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2874 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2876 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2879 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2881 struct drm_i915_private *i915 = to_i915(connector->dev);
2882 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2883 struct kobject *i2c_kobj = &adapter->dev.kobj;
2884 struct kobject *connector_kobj = &connector->kdev->kobj;
2887 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2889 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2892 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2894 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2895 struct kobject *i2c_kobj = &adapter->dev.kobj;
2896 struct kobject *connector_kobj = &connector->kdev->kobj;
2898 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2902 intel_hdmi_connector_register(struct drm_connector *connector)
2906 ret = intel_connector_register(connector);
2910 intel_hdmi_create_i2c_symlink(connector);
2915 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2917 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2919 cec_notifier_conn_unregister(n);
2921 intel_hdmi_remove_i2c_symlink(connector);
2922 intel_connector_unregister(connector);
2925 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2926 .detect = intel_hdmi_detect,
2927 .force = intel_hdmi_force,
2928 .fill_modes = drm_helper_probe_single_connector_modes,
2929 .atomic_get_property = intel_digital_connector_atomic_get_property,
2930 .atomic_set_property = intel_digital_connector_atomic_set_property,
2931 .late_register = intel_hdmi_connector_register,
2932 .early_unregister = intel_hdmi_connector_unregister,
2933 .destroy = intel_connector_destroy,
2934 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2935 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2938 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2939 .get_modes = intel_hdmi_get_modes,
2940 .mode_valid = intel_hdmi_mode_valid,
2941 .atomic_check = intel_digital_connector_atomic_check,
2944 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2945 .destroy = intel_encoder_destroy,
2949 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2951 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2953 intel_attach_force_audio_property(connector);
2954 intel_attach_broadcast_rgb_property(connector);
2955 intel_attach_aspect_ratio_property(connector);
2957 intel_attach_hdmi_colorspace_property(connector);
2958 drm_connector_attach_content_type_property(connector);
2960 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2961 drm_object_attach_property(&connector->base,
2962 connector->dev->mode_config.hdr_output_metadata_property, 0);
2964 if (!HAS_GMCH(dev_priv))
2965 drm_connector_attach_max_bpc_property(connector, 8, 12);
2969 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2970 * @encoder: intel_encoder
2971 * @connector: drm_connector
2972 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2973 * or reset the high tmds clock ratio for scrambling
2974 * @scrambling: bool to Indicate if the function needs to set or reset
2977 * This function handles scrambling on HDMI 2.0 capable sinks.
2978 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2979 * it enables scrambling. This should be called before enabling the HDMI
2980 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2981 * detect a scrambled clock within 100 ms.
2984 * True on success, false on failure.
2986 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2987 struct drm_connector *connector,
2988 bool high_tmds_clock_ratio,
2991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2992 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2993 struct drm_scrambling *sink_scrambling =
2994 &connector->display_info.hdmi.scdc.scrambling;
2995 struct i2c_adapter *adapter =
2996 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2998 if (!sink_scrambling->supported)
3001 drm_dbg_kms(&dev_priv->drm,
3002 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
3003 connector->base.id, connector->name,
3004 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
3006 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
3007 return drm_scdc_set_high_tmds_clock_ratio(adapter,
3008 high_tmds_clock_ratio) &&
3009 drm_scdc_set_scrambling(adapter, scrambling);
3012 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3018 ddc_pin = GMBUS_PIN_DPB;
3021 ddc_pin = GMBUS_PIN_DPC;
3024 ddc_pin = GMBUS_PIN_DPD_CHV;
3028 ddc_pin = GMBUS_PIN_DPB;
3034 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3040 ddc_pin = GMBUS_PIN_1_BXT;
3043 ddc_pin = GMBUS_PIN_2_BXT;
3047 ddc_pin = GMBUS_PIN_1_BXT;
3053 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3060 ddc_pin = GMBUS_PIN_1_BXT;
3063 ddc_pin = GMBUS_PIN_2_BXT;
3066 ddc_pin = GMBUS_PIN_4_CNP;
3069 ddc_pin = GMBUS_PIN_3_BXT;
3073 ddc_pin = GMBUS_PIN_1_BXT;
3079 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3081 enum phy phy = intel_port_to_phy(dev_priv, port);
3083 if (intel_phy_is_combo(dev_priv, phy))
3084 return GMBUS_PIN_1_BXT + port;
3085 else if (intel_phy_is_tc(dev_priv, phy))
3086 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
3088 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
3089 return GMBUS_PIN_2_BXT;
3092 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3094 enum phy phy = intel_port_to_phy(dev_priv, port);
3099 ddc_pin = GMBUS_PIN_1_BXT;
3102 ddc_pin = GMBUS_PIN_2_BXT;
3105 ddc_pin = GMBUS_PIN_9_TC1_ICP;
3109 ddc_pin = GMBUS_PIN_1_BXT;
3115 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3117 enum phy phy = intel_port_to_phy(dev_priv, port);
3119 WARN_ON(port == PORT_C);
3122 * Pin mapping for RKL depends on which PCH is present. With TGP, the
3123 * final two outputs use type-c pins, even though they're actually
3124 * combo outputs. With CMP, the traditional DDI A-D pins are used for
3127 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
3128 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
3130 return GMBUS_PIN_1_BXT + phy;
3133 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3135 return intel_port_to_phy(dev_priv, port) + 1;
3138 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3145 ddc_pin = GMBUS_PIN_DPB;
3148 ddc_pin = GMBUS_PIN_DPC;
3151 ddc_pin = GMBUS_PIN_DPD;
3155 ddc_pin = GMBUS_PIN_DPB;
3161 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
3163 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3164 enum port port = encoder->port;
3167 ddc_pin = intel_bios_alternate_ddc_pin(encoder);
3169 drm_dbg_kms(&dev_priv->drm,
3170 "Using DDC pin 0x%x for port %c (VBT)\n",
3171 ddc_pin, port_name(port));
3175 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
3176 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
3177 else if (IS_ROCKETLAKE(dev_priv))
3178 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
3179 else if (HAS_PCH_MCC(dev_priv))
3180 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3181 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3182 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3183 else if (HAS_PCH_CNP(dev_priv))
3184 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3185 else if (IS_GEN9_LP(dev_priv))
3186 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3187 else if (IS_CHERRYVIEW(dev_priv))
3188 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3190 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3192 drm_dbg_kms(&dev_priv->drm,
3193 "Using DDC pin 0x%x for port %c (platform default)\n",
3194 ddc_pin, port_name(port));
3199 void intel_infoframe_init(struct intel_digital_port *dig_port)
3201 struct drm_i915_private *dev_priv =
3202 to_i915(dig_port->base.base.dev);
3204 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3205 dig_port->write_infoframe = vlv_write_infoframe;
3206 dig_port->read_infoframe = vlv_read_infoframe;
3207 dig_port->set_infoframes = vlv_set_infoframes;
3208 dig_port->infoframes_enabled = vlv_infoframes_enabled;
3209 } else if (IS_G4X(dev_priv)) {
3210 dig_port->write_infoframe = g4x_write_infoframe;
3211 dig_port->read_infoframe = g4x_read_infoframe;
3212 dig_port->set_infoframes = g4x_set_infoframes;
3213 dig_port->infoframes_enabled = g4x_infoframes_enabled;
3214 } else if (HAS_DDI(dev_priv)) {
3215 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
3216 dig_port->write_infoframe = lspcon_write_infoframe;
3217 dig_port->read_infoframe = lspcon_read_infoframe;
3218 dig_port->set_infoframes = lspcon_set_infoframes;
3219 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3221 dig_port->write_infoframe = hsw_write_infoframe;
3222 dig_port->read_infoframe = hsw_read_infoframe;
3223 dig_port->set_infoframes = hsw_set_infoframes;
3224 dig_port->infoframes_enabled = hsw_infoframes_enabled;
3226 } else if (HAS_PCH_IBX(dev_priv)) {
3227 dig_port->write_infoframe = ibx_write_infoframe;
3228 dig_port->read_infoframe = ibx_read_infoframe;
3229 dig_port->set_infoframes = ibx_set_infoframes;
3230 dig_port->infoframes_enabled = ibx_infoframes_enabled;
3232 dig_port->write_infoframe = cpt_write_infoframe;
3233 dig_port->read_infoframe = cpt_read_infoframe;
3234 dig_port->set_infoframes = cpt_set_infoframes;
3235 dig_port->infoframes_enabled = cpt_infoframes_enabled;
3239 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
3240 struct intel_connector *intel_connector)
3242 struct drm_connector *connector = &intel_connector->base;
3243 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3244 struct intel_encoder *intel_encoder = &dig_port->base;
3245 struct drm_device *dev = intel_encoder->base.dev;
3246 struct drm_i915_private *dev_priv = to_i915(dev);
3247 struct i2c_adapter *ddc;
3248 enum port port = intel_encoder->port;
3249 struct cec_connector_info conn_info;
3251 drm_dbg_kms(&dev_priv->drm,
3252 "Adding HDMI connector on [ENCODER:%d:%s]\n",
3253 intel_encoder->base.base.id, intel_encoder->base.name);
3255 if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
3258 if (drm_WARN(dev, dig_port->max_lanes < 4,
3259 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3260 dig_port->max_lanes, intel_encoder->base.base.id,
3261 intel_encoder->base.name))
3264 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
3265 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
3267 drm_connector_init_with_ddc(dev, connector,
3268 &intel_hdmi_connector_funcs,
3269 DRM_MODE_CONNECTOR_HDMIA,
3271 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3273 connector->interlace_allowed = 1;
3274 connector->doublescan_allowed = 0;
3275 connector->stereo_allowed = 1;
3277 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3278 connector->ycbcr_420_allowed = true;
3280 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3282 if (HAS_DDI(dev_priv))
3283 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3285 intel_connector->get_hw_state = intel_connector_get_hw_state;
3287 intel_hdmi_add_properties(intel_hdmi, connector);
3289 intel_connector_attach_encoder(intel_connector, intel_encoder);
3290 intel_hdmi->attached_connector = intel_connector;
3292 if (is_hdcp_supported(dev_priv, port)) {
3293 int ret = intel_hdcp_init(intel_connector, port,
3294 &intel_hdmi_hdcp_shim);
3296 drm_dbg_kms(&dev_priv->drm,
3297 "HDCP init failed, skipping.\n");
3300 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3301 * 0xd. Failure to do so will result in spurious interrupts being
3302 * generated on the port when a cable is not attached.
3304 if (IS_G45(dev_priv)) {
3305 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
3306 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
3307 (temp & ~0xf) | 0xd);
3310 cec_fill_conn_info_from_drm(&conn_info, connector);
3312 intel_hdmi->cec_notifier =
3313 cec_notifier_conn_register(dev->dev, port_identifier(port),
3315 if (!intel_hdmi->cec_notifier)
3316 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3319 static enum intel_hotplug_state
3320 intel_hdmi_hotplug(struct intel_encoder *encoder,
3321 struct intel_connector *connector)
3323 enum intel_hotplug_state state;
3325 state = intel_encoder_hotplug(encoder, connector);
3328 * On many platforms the HDMI live state signal is known to be
3329 * unreliable, so we can't use it to detect if a sink is connected or
3330 * not. Instead we detect if it's connected based on whether we can
3331 * read the EDID or not. That in turn has a problem during disconnect,
3332 * since the HPD interrupt may be raised before the DDC lines get
3333 * disconnected (due to how the required length of DDC vs. HPD
3334 * connector pins are specified) and so we'll still be able to get a
3335 * valid EDID. To solve this schedule another detection cycle if this
3336 * time around we didn't detect any change in the sink's connection
3339 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
3340 state = INTEL_HOTPLUG_RETRY;
3345 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3346 i915_reg_t hdmi_reg, enum port port)
3348 struct intel_digital_port *dig_port;
3349 struct intel_encoder *intel_encoder;
3350 struct intel_connector *intel_connector;
3352 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
3356 intel_connector = intel_connector_alloc();
3357 if (!intel_connector) {
3362 intel_encoder = &dig_port->base;
3364 mutex_init(&dig_port->hdcp_mutex);
3366 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3367 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3368 "HDMI %c", port_name(port));
3370 intel_encoder->hotplug = intel_hdmi_hotplug;
3371 intel_encoder->compute_config = intel_hdmi_compute_config;
3372 if (HAS_PCH_SPLIT(dev_priv)) {
3373 intel_encoder->disable = pch_disable_hdmi;
3374 intel_encoder->post_disable = pch_post_disable_hdmi;
3376 intel_encoder->disable = g4x_disable_hdmi;
3378 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3379 intel_encoder->get_config = intel_hdmi_get_config;
3380 if (IS_CHERRYVIEW(dev_priv)) {
3381 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3382 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3383 intel_encoder->enable = vlv_enable_hdmi;
3384 intel_encoder->post_disable = chv_hdmi_post_disable;
3385 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3386 } else if (IS_VALLEYVIEW(dev_priv)) {
3387 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3388 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3389 intel_encoder->enable = vlv_enable_hdmi;
3390 intel_encoder->post_disable = vlv_hdmi_post_disable;
3392 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3393 if (HAS_PCH_CPT(dev_priv))
3394 intel_encoder->enable = cpt_enable_hdmi;
3395 else if (HAS_PCH_IBX(dev_priv))
3396 intel_encoder->enable = ibx_enable_hdmi;
3398 intel_encoder->enable = g4x_enable_hdmi;
3401 intel_encoder->type = INTEL_OUTPUT_HDMI;
3402 intel_encoder->power_domain = intel_port_to_power_domain(port);
3403 intel_encoder->port = port;
3404 if (IS_CHERRYVIEW(dev_priv)) {
3406 intel_encoder->pipe_mask = BIT(PIPE_C);
3408 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
3410 intel_encoder->pipe_mask = ~0;
3412 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3413 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3415 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3416 * to work on real hardware. And since g4x can send infoframes to
3417 * only one port anyway, nothing is lost by allowing it.
3419 if (IS_G4X(dev_priv))
3420 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3422 dig_port->hdmi.hdmi_reg = hdmi_reg;
3423 dig_port->dp.output_reg = INVALID_MMIO_REG;
3424 dig_port->max_lanes = 4;
3426 intel_infoframe_init(dig_port);
3428 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3429 intel_hdmi_init_connector(dig_port, intel_connector);
3433 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3434 * @vactive: Vactive of a display mode
3436 * @return: appropriate dsc slice height for a given mode.
3438 int intel_hdmi_dsc_get_slice_height(int vactive)
3443 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3444 * Select smallest slice height >=96, that results in a valid PPS and
3445 * requires minimum padding lines required for final slice.
3447 * Assumption : Vactive is even.
3449 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3450 if (vactive % slice_height == 0)
3451 return slice_height;
3457 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3458 * and dsc decoder capabilities
3460 * @crtc_state: intel crtc_state
3461 * @src_max_slices: maximum slices supported by the DSC encoder
3462 * @src_max_slice_width: maximum slice width supported by DSC encoder
3463 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3464 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3466 * @return: num of dsc slices that can be supported by the dsc encoder
3470 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3471 int src_max_slices, int src_max_slice_width,
3472 int hdmi_max_slices, int hdmi_throughput)
3474 /* Pixel rates in KPixels/sec */
3475 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000
3477 * Rates at which the source and sink are required to process pixels in each
3478 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3480 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
3481 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
3483 /* Spec limits the slice width to 2720 pixels */
3484 #define MAX_HDMI_SLICE_WIDTH 2720
3486 int adjusted_clk_khz;
3489 int max_throughput; /* max clock freq. in khz per slice */
3490 int max_slice_width;
3492 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3494 if (!hdmi_throughput)
3498 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3499 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3500 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3501 * dividing adjusted clock value by 10.
3503 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3504 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3510 * As per spec, the rate at which the source and the sink process
3511 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3512 * This depends upon the pixel clock rate and output formats
3514 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3515 * at max 340MHz, otherwise they can be processed at max 400MHz.
3518 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3520 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3521 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3523 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3526 * Taking into account the sink's capability for maximum
3527 * clock per slice (in MHz) as read from HF-VSDB.
3529 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3531 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3532 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3535 * Keep on increasing the num of slices/line, starting from min_slices
3536 * per line till we get such a number, for which the slice_width is
3537 * just less than max_slice_width. The slices/line selected should be
3538 * less than or equal to the max horizontal slices that the combination
3539 * of PCON encoder and HDMI decoder can support.
3541 slice_width = max_slice_width;
3544 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3546 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3548 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3550 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3552 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3554 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3559 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3560 if (slice_width >= max_slice_width)
3561 min_slices = target_slices + 1;
3562 } while (slice_width >= max_slice_width);
3564 return target_slices;
3568 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3569 * source and sink capabilities.
3571 * @src_fraction_bpp: fractional bpp supported by the source
3572 * @slice_width: dsc slice width supported by the source and sink
3573 * @num_slices: num of slices supported by the source and sink
3574 * @output_format: video output format
3575 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3576 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3578 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3581 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3582 int output_format, bool hdmi_all_bpp,
3583 int hdmi_max_chunk_bytes)
3585 int max_dsc_bpp, min_dsc_bpp;
3587 bool bpp_found = false;
3588 int bpp_decrement_x16;
3593 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3594 * Start with the max bpp and keep on decrementing with
3595 * fractional bpp, if supported by PCON DSC encoder
3597 * for each bpp we check if no of bytes can be supported by HDMI sink
3600 /* Assuming: bpc as 8*/
3601 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3603 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3604 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3605 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3607 max_dsc_bpp = 3 * 8; /* 3*bpc */
3609 /* Assuming 4:2:2 encoding */
3611 max_dsc_bpp = 2 * 8; /* 2*bpc */
3615 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3616 * Section 7.7.34 : Source shall not enable compressed Video
3617 * Transport with bpp_target settings above 12 bpp unless
3618 * DSC_all_bpp is set to 1.
3621 max_dsc_bpp = min(max_dsc_bpp, 12);
3624 * The Sink has a limit of compressed data in bytes for a scanline,
3625 * as described in max_chunk_bytes field in HFVSDB block of edid.
3626 * The no. of bytes depend on the target bits per pixel that the
3627 * source configures. So we start with the max_bpp and calculate
3628 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3629 * till we get the target_chunk_bytes just less than what the sink's
3630 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3632 * The decrement is according to the fractional support from PCON DSC
3633 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3635 * bpp_target_x16 = bpp_target * 16
3636 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3637 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3640 bpp_target = max_dsc_bpp;
3642 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3643 if (!src_fractional_bpp)
3644 src_fractional_bpp = 1;
3645 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3646 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3648 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3651 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3652 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3653 if (target_bytes <= hdmi_max_chunk_bytes) {
3657 bpp_target_x16 -= bpp_decrement_x16;
3660 return bpp_target_x16;