drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_hdcp_helper.h>
  36 #include <drm/display/drm_hdmi_helper.h>
  37 #include <drm/display/drm_scdc_helper.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_crtc.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/intel_lpe_audio.h>
  42
  43 #include "i915_debugfs.h"
  44 #include "i915_drv.h"
  45 #include "i915_reg.h"
  46 #include "intel_atomic.h"
  47 #include "intel_connector.h"
  48 #include "intel_ddi.h"
  49 #include "intel_de.h"
  50 #include "intel_display_types.h"
  51 #include "intel_dp.h"
  52 #include "intel_gmbus.h"
  53 #include "intel_hdcp.h"
  54 #include "intel_hdcp_regs.h"
  55 #include "intel_hdmi.h"
  56 #include "intel_lspcon.h"
  57 #include "intel_panel.h"
  58 #include "intel_snps_phy.h"
  59
  60 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
  61 {
  62         return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
  63 }
  64
  65 static void
  66 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  67 {
  68         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
  69         u32 enabled_bits;
  70
  71         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  72
  73         drm_WARN(&dev_priv->drm,
  74                  intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
  75                  "HDMI port enabled, expecting disabled\n");
  76 }
  77
  78 static void
  79 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  80                                      enum transcoder cpu_transcoder)
  81 {
  82         drm_WARN(&dev_priv->drm,
  83                  intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  84                  TRANS_DDI_FUNC_ENABLE,
  85                  "HDMI transcoder function enabled, expecting disabled\n");
  86 }
  87
  88 static u32 g4x_infoframe_index(unsigned int type)
  89 {
  90         switch (type) {
  91         case HDMI_PACKET_TYPE_GAMUT_METADATA:
  92                 return VIDEO_DIP_SELECT_GAMUT;
  93         case HDMI_INFOFRAME_TYPE_AVI:
  94                 return VIDEO_DIP_SELECT_AVI;
  95         case HDMI_INFOFRAME_TYPE_SPD:
  96                 return VIDEO_DIP_SELECT_SPD;
  97         case HDMI_INFOFRAME_TYPE_VENDOR:
  98                 return VIDEO_DIP_SELECT_VENDOR;
  99         default:
 100                 MISSING_CASE(type);
 101                 return 0;
 102         }
 103 }
 104
 105 static u32 g4x_infoframe_enable(unsigned int type)
 106 {
 107         switch (type) {
 108         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 109                 return VIDEO_DIP_ENABLE_GCP;
 110         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 111                 return VIDEO_DIP_ENABLE_GAMUT;
 112         case DP_SDP_VSC:
 113                 return 0;
 114         case HDMI_INFOFRAME_TYPE_AVI:
 115                 return VIDEO_DIP_ENABLE_AVI;
 116         case HDMI_INFOFRAME_TYPE_SPD:
 117                 return VIDEO_DIP_ENABLE_SPD;
 118         case HDMI_INFOFRAME_TYPE_VENDOR:
 119                 return VIDEO_DIP_ENABLE_VENDOR;
 120         case HDMI_INFOFRAME_TYPE_DRM:
 121                 return 0;
 122         default:
 123                 MISSING_CASE(type);
 124                 return 0;
 125         }
 126 }
 127
 128 static u32 hsw_infoframe_enable(unsigned int type)
 129 {
 130         switch (type) {
 131         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 132                 return VIDEO_DIP_ENABLE_GCP_HSW;
 133         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 134                 return VIDEO_DIP_ENABLE_GMP_HSW;
 135         case DP_SDP_VSC:
 136                 return VIDEO_DIP_ENABLE_VSC_HSW;
 137         case DP_SDP_PPS:
 138                 return VDIP_ENABLE_PPS;
 139         case HDMI_INFOFRAME_TYPE_AVI:
 140                 return VIDEO_DIP_ENABLE_AVI_HSW;
 141         case HDMI_INFOFRAME_TYPE_SPD:
 142                 return VIDEO_DIP_ENABLE_SPD_HSW;
 143         case HDMI_INFOFRAME_TYPE_VENDOR:
 144                 return VIDEO_DIP_ENABLE_VS_HSW;
 145         case HDMI_INFOFRAME_TYPE_DRM:
 146                 return VIDEO_DIP_ENABLE_DRM_GLK;
 147         default:
 148                 MISSING_CASE(type);
 149                 return 0;
 150         }
 151 }
 152
 153 static i915_reg_t
 154 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 155                  enum transcoder cpu_transcoder,
 156                  unsigned int type,
 157                  int i)
 158 {
 159         switch (type) {
 160         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 161                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 162         case DP_SDP_VSC:
 163                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 164         case DP_SDP_PPS:
 165                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 166         case HDMI_INFOFRAME_TYPE_AVI:
 167                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 168         case HDMI_INFOFRAME_TYPE_SPD:
 169                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 170         case HDMI_INFOFRAME_TYPE_VENDOR:
 171                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 172         case HDMI_INFOFRAME_TYPE_DRM:
 173                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 174         default:
 175                 MISSING_CASE(type);
 176                 return INVALID_MMIO_REG;
 177         }
 178 }
 179
 180 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
 181                              unsigned int type)
 182 {
 183         switch (type) {
 184         case DP_SDP_VSC:
 185                 return VIDEO_DIP_VSC_DATA_SIZE;
 186         case DP_SDP_PPS:
 187                 return VIDEO_DIP_PPS_DATA_SIZE;
 188         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 189                 if (DISPLAY_VER(dev_priv) >= 11)
 190                         return VIDEO_DIP_GMP_DATA_SIZE;
 191                 else
 192                         return VIDEO_DIP_DATA_SIZE;
 193         default:
 194                 return VIDEO_DIP_DATA_SIZE;
 195         }
 196 }
 197
 198 static void g4x_write_infoframe(struct intel_encoder *encoder,
 199                                 const struct intel_crtc_state *crtc_state,
 200                                 unsigned int type,
 201                                 const void *frame, ssize_t len)
 202 {
 203         const u32 *data = frame;
 204         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 205         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 206         int i;
 207
 208         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 209                  "Writing DIP with CTL reg disabled\n");
 210
 211         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 212         val |= g4x_infoframe_index(type);
 213
 214         val &= ~g4x_infoframe_enable(type);
 215
 216         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 217
 218         for (i = 0; i < len; i += 4) {
 219                 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
 220                 data++;
 221         }
 222         /* Write every possible data byte to force correct ECC calculation. */
 223         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 224                 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
 225
 226         val |= g4x_infoframe_enable(type);
 227         val &= ~VIDEO_DIP_FREQ_MASK;
 228         val |= VIDEO_DIP_FREQ_VSYNC;
 229
 230         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 231         intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
 232 }
 233
 234 static void g4x_read_infoframe(struct intel_encoder *encoder,
 235                                const struct intel_crtc_state *crtc_state,
 236                                unsigned int type,
 237                                void *frame, ssize_t len)
 238 {
 239         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 240         u32 val, *data = frame;
 241         int i;
 242
 243         val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 244
 245         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 246         val |= g4x_infoframe_index(type);
 247
 248         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 249
 250         for (i = 0; i < len; i += 4)
 251                 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
 252 }
 253
 254 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 255                                   const struct intel_crtc_state *pipe_config)
 256 {
 257         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 258         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 259
 260         if ((val & VIDEO_DIP_ENABLE) == 0)
 261                 return 0;
 262
 263         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 264                 return 0;
 265
 266         return val & (VIDEO_DIP_ENABLE_AVI |
 267                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 268 }
 269
 270 static void ibx_write_infoframe(struct intel_encoder *encoder,
 271                                 const struct intel_crtc_state *crtc_state,
 272                                 unsigned int type,
 273                                 const void *frame, ssize_t len)
 274 {
 275         const u32 *data = frame;
 276         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 277         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 278         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 279         u32 val = intel_de_read(dev_priv, reg);
 280         int i;
 281
 282         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 283                  "Writing DIP with CTL reg disabled\n");
 284
 285         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 286         val |= g4x_infoframe_index(type);
 287
 288         val &= ~g4x_infoframe_enable(type);
 289
 290         intel_de_write(dev_priv, reg, val);
 291
 292         for (i = 0; i < len; i += 4) {
 293                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 294                                *data);
 295                 data++;
 296         }
 297         /* Write every possible data byte to force correct ECC calculation. */
 298         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 299                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 300
 301         val |= g4x_infoframe_enable(type);
 302         val &= ~VIDEO_DIP_FREQ_MASK;
 303         val |= VIDEO_DIP_FREQ_VSYNC;
 304
 305         intel_de_write(dev_priv, reg, val);
 306         intel_de_posting_read(dev_priv, reg);
 307 }
 308
 309 static void ibx_read_infoframe(struct intel_encoder *encoder,
 310                                const struct intel_crtc_state *crtc_state,
 311                                unsigned int type,
 312                                void *frame, ssize_t len)
 313 {
 314         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 315         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 316         u32 val, *data = frame;
 317         int i;
 318
 319         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 320
 321         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 322         val |= g4x_infoframe_index(type);
 323
 324         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 325
 326         for (i = 0; i < len; i += 4)
 327                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 328 }
 329
 330 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 331                                   const struct intel_crtc_state *pipe_config)
 332 {
 333         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 334         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 335         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 336         u32 val = intel_de_read(dev_priv, reg);
 337
 338         if ((val & VIDEO_DIP_ENABLE) == 0)
 339                 return 0;
 340
 341         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 342                 return 0;
 343
 344         return val & (VIDEO_DIP_ENABLE_AVI |
 345                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 346                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 347 }
 348
 349 static void cpt_write_infoframe(struct intel_encoder *encoder,
 350                                 const struct intel_crtc_state *crtc_state,
 351                                 unsigned int type,
 352                                 const void *frame, ssize_t len)
 353 {
 354         const u32 *data = frame;
 355         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 356         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 357         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 358         u32 val = intel_de_read(dev_priv, reg);
 359         int i;
 360
 361         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 362                  "Writing DIP with CTL reg disabled\n");
 363
 364         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 365         val |= g4x_infoframe_index(type);
 366
 367         /* The DIP control register spec says that we need to update the AVI
 368          * infoframe without clearing its enable bit */
 369         if (type != HDMI_INFOFRAME_TYPE_AVI)
 370                 val &= ~g4x_infoframe_enable(type);
 371
 372         intel_de_write(dev_priv, reg, val);
 373
 374         for (i = 0; i < len; i += 4) {
 375                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 376                                *data);
 377                 data++;
 378         }
 379         /* Write every possible data byte to force correct ECC calculation. */
 380         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 381                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 382
 383         val |= g4x_infoframe_enable(type);
 384         val &= ~VIDEO_DIP_FREQ_MASK;
 385         val |= VIDEO_DIP_FREQ_VSYNC;
 386
 387         intel_de_write(dev_priv, reg, val);
 388         intel_de_posting_read(dev_priv, reg);
 389 }
 390
 391 static void cpt_read_infoframe(struct intel_encoder *encoder,
 392                                const struct intel_crtc_state *crtc_state,
 393                                unsigned int type,
 394                                void *frame, ssize_t len)
 395 {
 396         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 397         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 398         u32 val, *data = frame;
 399         int i;
 400
 401         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 402
 403         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 404         val |= g4x_infoframe_index(type);
 405
 406         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 407
 408         for (i = 0; i < len; i += 4)
 409                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 410 }
 411
 412 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 413                                   const struct intel_crtc_state *pipe_config)
 414 {
 415         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 416         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 417         u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
 418
 419         if ((val & VIDEO_DIP_ENABLE) == 0)
 420                 return 0;
 421
 422         return val & (VIDEO_DIP_ENABLE_AVI |
 423                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 424                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 425 }
 426
 427 static void vlv_write_infoframe(struct intel_encoder *encoder,
 428                                 const struct intel_crtc_state *crtc_state,
 429                                 unsigned int type,
 430                                 const void *frame, ssize_t len)
 431 {
 432         const u32 *data = frame;
 433         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 434         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 435         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 436         u32 val = intel_de_read(dev_priv, reg);
 437         int i;
 438
 439         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 440                  "Writing DIP with CTL reg disabled\n");
 441
 442         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 443         val |= g4x_infoframe_index(type);
 444
 445         val &= ~g4x_infoframe_enable(type);
 446
 447         intel_de_write(dev_priv, reg, val);
 448
 449         for (i = 0; i < len; i += 4) {
 450                 intel_de_write(dev_priv,
 451                                VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
 452                 data++;
 453         }
 454         /* Write every possible data byte to force correct ECC calculation. */
 455         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 456                 intel_de_write(dev_priv,
 457                                VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
 458
 459         val |= g4x_infoframe_enable(type);
 460         val &= ~VIDEO_DIP_FREQ_MASK;
 461         val |= VIDEO_DIP_FREQ_VSYNC;
 462
 463         intel_de_write(dev_priv, reg, val);
 464         intel_de_posting_read(dev_priv, reg);
 465 }
 466
 467 static void vlv_read_infoframe(struct intel_encoder *encoder,
 468                                const struct intel_crtc_state *crtc_state,
 469                                unsigned int type,
 470                                void *frame, ssize_t len)
 471 {
 472         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 473         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 474         u32 val, *data = frame;
 475         int i;
 476
 477         val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
 478
 479         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 480         val |= g4x_infoframe_index(type);
 481
 482         intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 483
 484         for (i = 0; i < len; i += 4)
 485                 *data++ = intel_de_read(dev_priv,
 486                                         VLV_TVIDEO_DIP_DATA(crtc->pipe));
 487 }
 488
 489 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 490                                   const struct intel_crtc_state *pipe_config)
 491 {
 492         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 493         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 494         u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
 495
 496         if ((val & VIDEO_DIP_ENABLE) == 0)
 497                 return 0;
 498
 499         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 500                 return 0;
 501
 502         return val & (VIDEO_DIP_ENABLE_AVI |
 503                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 504                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 505 }
 506
 507 void hsw_write_infoframe(struct intel_encoder *encoder,
 508                          const struct intel_crtc_state *crtc_state,
 509                          unsigned int type,
 510                          const void *frame, ssize_t len)
 511 {
 512         const u32 *data = frame;
 513         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 514         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 515         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 516         int data_size;
 517         int i;
 518         u32 val = intel_de_read(dev_priv, ctl_reg);
 519
 520         data_size = hsw_dip_data_size(dev_priv, type);
 521
 522         drm_WARN_ON(&dev_priv->drm, len > data_size);
 523
 524         val &= ~hsw_infoframe_enable(type);
 525         intel_de_write(dev_priv, ctl_reg, val);
 526
 527         for (i = 0; i < len; i += 4) {
 528                 intel_de_write(dev_priv,
 529                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 530                                *data);
 531                 data++;
 532         }
 533         /* Write every possible data byte to force correct ECC calculation. */
 534         for (; i < data_size; i += 4)
 535                 intel_de_write(dev_priv,
 536                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 537                                0);
 538
 539         /* Wa_14013475917 */
 540         if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
 541             type == DP_SDP_VSC)
 542                 return;
 543
 544         val |= hsw_infoframe_enable(type);
 545         intel_de_write(dev_priv, ctl_reg, val);
 546         intel_de_posting_read(dev_priv, ctl_reg);
 547 }
 548
 549 void hsw_read_infoframe(struct intel_encoder *encoder,
 550                         const struct intel_crtc_state *crtc_state,
 551                         unsigned int type, void *frame, ssize_t len)
 552 {
 553         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 554         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 555         u32 *data = frame;
 556         int i;
 557
 558         for (i = 0; i < len; i += 4)
 559                 *data++ = intel_de_read(dev_priv,
 560                                         hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
 561 }
 562
 563 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 564                                   const struct intel_crtc_state *pipe_config)
 565 {
 566         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 567         u32 val = intel_de_read(dev_priv,
 568                                 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 569         u32 mask;
 570
 571         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 572                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 573                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 574
 575         if (DISPLAY_VER(dev_priv) >= 10)
 576                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 577
 578         return val & mask;
 579 }
 580
 581 static const u8 infoframe_type_to_idx[] = {
 582         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 583         HDMI_PACKET_TYPE_GAMUT_METADATA,
 584         DP_SDP_VSC,
 585         HDMI_INFOFRAME_TYPE_AVI,
 586         HDMI_INFOFRAME_TYPE_SPD,
 587         HDMI_INFOFRAME_TYPE_VENDOR,
 588         HDMI_INFOFRAME_TYPE_DRM,
 589 };
 590
 591 u32 intel_hdmi_infoframe_enable(unsigned int type)
 592 {
 593         int i;
 594
 595         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 596                 if (infoframe_type_to_idx[i] == type)
 597                         return BIT(i);
 598         }
 599
 600         return 0;
 601 }
 602
 603 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 604                                   const struct intel_crtc_state *crtc_state)
 605 {
 606         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 607         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 608         u32 val, ret = 0;
 609         int i;
 610
 611         val = dig_port->infoframes_enabled(encoder, crtc_state);
 612
 613         /* map from hardware bits to dip idx */
 614         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 615                 unsigned int type = infoframe_type_to_idx[i];
 616
 617                 if (HAS_DDI(dev_priv)) {
 618                         if (val & hsw_infoframe_enable(type))
 619                                 ret |= BIT(i);
 620                 } else {
 621                         if (val & g4x_infoframe_enable(type))
 622                                 ret |= BIT(i);
 623                 }
 624         }
 625
 626         return ret;
 627 }
 628
 629 /*
 630  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 631  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 632  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 633  * used for both technologies.
 634  *
 635  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 636  * DW1:       DB3       | DB2 | DB1 | DB0
 637  * DW2:       DB7       | DB6 | DB5 | DB4
 638  * DW3: ...
 639  *
 640  * (HB is Header Byte, DB is Data Byte)
 641  *
 642  * The hdmi pack() functions don't know about that hardware specific hole so we
 643  * trick them by giving an offset into the buffer and moving back the header
 644  * bytes by one.
 645  */
 646 static void intel_write_infoframe(struct intel_encoder *encoder,
 647                                   const struct intel_crtc_state *crtc_state,
 648                                   enum hdmi_infoframe_type type,
 649                                   const union hdmi_infoframe *frame)
 650 {
 651         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 652         u8 buffer[VIDEO_DIP_DATA_SIZE];
 653         ssize_t len;
 654
 655         if ((crtc_state->infoframes.enable &
 656              intel_hdmi_infoframe_enable(type)) == 0)
 657                 return;
 658
 659         if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
 660                 return;
 661
 662         /* see comment above for the reason for this offset */
 663         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 664         if (drm_WARN_ON(encoder->base.dev, len < 0))
 665                 return;
 666
 667         /* Insert the 'hole' (see big comment above) at position 3 */
 668         memmove(&buffer[0], &buffer[1], 3);
 669         buffer[3] = 0;
 670         len++;
 671
 672         dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 673 }
 674
 675 void intel_read_infoframe(struct intel_encoder *encoder,
 676                           const struct intel_crtc_state *crtc_state,
 677                           enum hdmi_infoframe_type type,
 678                           union hdmi_infoframe *frame)
 679 {
 680         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 681         u8 buffer[VIDEO_DIP_DATA_SIZE];
 682         int ret;
 683
 684         if ((crtc_state->infoframes.enable &
 685              intel_hdmi_infoframe_enable(type)) == 0)
 686                 return;
 687
 688         dig_port->read_infoframe(encoder, crtc_state,
 689                                        type, buffer, sizeof(buffer));
 690
 691         /* Fill the 'hole' (see big comment above) at position 3 */
 692         memmove(&buffer[1], &buffer[0], 3);
 693
 694         /* see comment above for the reason for this offset */
 695         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 696         if (ret) {
 697                 drm_dbg_kms(encoder->base.dev,
 698                             "Failed to unpack infoframe type 0x%02x\n", type);
 699                 return;
 700         }
 701
 702         if (frame->any.type != type)
 703                 drm_dbg_kms(encoder->base.dev,
 704                             "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 705                             frame->any.type, type);
 706 }
 707
 708 static bool
 709 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 710                                  struct intel_crtc_state *crtc_state,
 711                                  struct drm_connector_state *conn_state)
 712 {
 713         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 714         const struct drm_display_mode *adjusted_mode =
 715                 &crtc_state->hw.adjusted_mode;
 716         struct drm_connector *connector = conn_state->connector;
 717         int ret;
 718
 719         if (!crtc_state->has_infoframe)
 720                 return true;
 721
 722         crtc_state->infoframes.enable |=
 723                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 724
 725         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 726                                                        adjusted_mode);
 727         if (ret)
 728                 return false;
 729
 730         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 731                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 732         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 733                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 734         else
 735                 frame->colorspace = HDMI_COLORSPACE_RGB;
 736
 737         drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
 738
 739         /* nonsense combination */
 740         drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
 741                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 742
 743         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 744                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 745                                                    adjusted_mode,
 746                                                    crtc_state->limited_color_range ?
 747                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 748                                                    HDMI_QUANTIZATION_RANGE_FULL);
 749         } else {
 750                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 751                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 752         }
 753
 754         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 755
 756         /* TODO: handle pixel repetition for YCBCR420 outputs */
 757
 758         ret = hdmi_avi_infoframe_check(frame);
 759         if (drm_WARN_ON(encoder->base.dev, ret))
 760                 return false;
 761
 762         return true;
 763 }
 764
 765 static bool
 766 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 767                                  struct intel_crtc_state *crtc_state,
 768                                  struct drm_connector_state *conn_state)
 769 {
 770         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 771         int ret;
 772
 773         if (!crtc_state->has_infoframe)
 774                 return true;
 775
 776         crtc_state->infoframes.enable |=
 777                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 778
 779         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 780         if (drm_WARN_ON(encoder->base.dev, ret))
 781                 return false;
 782
 783         frame->sdi = HDMI_SPD_SDI_PC;
 784
 785         ret = hdmi_spd_infoframe_check(frame);
 786         if (drm_WARN_ON(encoder->base.dev, ret))
 787                 return false;
 788
 789         return true;
 790 }
 791
 792 static bool
 793 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 794                                   struct intel_crtc_state *crtc_state,
 795                                   struct drm_connector_state *conn_state)
 796 {
 797         struct hdmi_vendor_infoframe *frame =
 798                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 799         const struct drm_display_info *info =
 800                 &conn_state->connector->display_info;
 801         int ret;
 802
 803         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 804                 return true;
 805
 806         crtc_state->infoframes.enable |=
 807                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 808
 809         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 810                                                           conn_state->connector,
 811                                                           &crtc_state->hw.adjusted_mode);
 812         if (drm_WARN_ON(encoder->base.dev, ret))
 813                 return false;
 814
 815         ret = hdmi_vendor_infoframe_check(frame);
 816         if (drm_WARN_ON(encoder->base.dev, ret))
 817                 return false;
 818
 819         return true;
 820 }
 821
 822 static bool
 823 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 824                                  struct intel_crtc_state *crtc_state,
 825                                  struct drm_connector_state *conn_state)
 826 {
 827         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 828         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 829         int ret;
 830
 831         if (DISPLAY_VER(dev_priv) < 10)
 832                 return true;
 833
 834         if (!crtc_state->has_infoframe)
 835                 return true;
 836
 837         if (!conn_state->hdr_output_metadata)
 838                 return true;
 839
 840         crtc_state->infoframes.enable |=
 841                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 842
 843         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 844         if (ret < 0) {
 845                 drm_dbg_kms(&dev_priv->drm,
 846                             "couldn't set HDR metadata in infoframe\n");
 847                 return false;
 848         }
 849
 850         ret = hdmi_drm_infoframe_check(frame);
 851         if (drm_WARN_ON(&dev_priv->drm, ret))
 852                 return false;
 853
 854         return true;
 855 }
 856
 857 static void g4x_set_infoframes(struct intel_encoder *encoder,
 858                                bool enable,
 859                                const struct intel_crtc_state *crtc_state,
 860                                const struct drm_connector_state *conn_state)
 861 {
 862         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 863         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 864         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 865         i915_reg_t reg = VIDEO_DIP_CTL;
 866         u32 val = intel_de_read(dev_priv, reg);
 867         u32 port = VIDEO_DIP_PORT(encoder->port);
 868
 869         assert_hdmi_port_disabled(intel_hdmi);
 870
 871         /* If the registers were not initialized yet, they might be zeroes,
 872          * which means we're selecting the AVI DIP and we're setting its
 873          * frequency to once. This seems to really confuse the HW and make
 874          * things stop working (the register spec says the AVI always needs to
 875          * be sent every VSync). So here we avoid writing to the register more
 876          * than we need and also explicitly select the AVI DIP and explicitly
 877          * set its frequency to every VSync. Avoiding to write it twice seems to
 878          * be enough to solve the problem, but being defensive shouldn't hurt us
 879          * either. */
 880         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 881
 882         if (!enable) {
 883                 if (!(val & VIDEO_DIP_ENABLE))
 884                         return;
 885                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 886                         drm_dbg_kms(&dev_priv->drm,
 887                                     "video DIP still enabled on port %c\n",
 888                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 889                         return;
 890                 }
 891                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 892                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 893                 intel_de_write(dev_priv, reg, val);
 894                 intel_de_posting_read(dev_priv, reg);
 895                 return;
 896         }
 897
 898         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 899                 if (val & VIDEO_DIP_ENABLE) {
 900                         drm_dbg_kms(&dev_priv->drm,
 901                                     "video DIP already enabled on port %c\n",
 902                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 903                         return;
 904                 }
 905                 val &= ~VIDEO_DIP_PORT_MASK;
 906                 val |= port;
 907         }
 908
 909         val |= VIDEO_DIP_ENABLE;
 910         val &= ~(VIDEO_DIP_ENABLE_AVI |
 911                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 912
 913         intel_de_write(dev_priv, reg, val);
 914         intel_de_posting_read(dev_priv, reg);
 915
 916         intel_write_infoframe(encoder, crtc_state,
 917                               HDMI_INFOFRAME_TYPE_AVI,
 918                               &crtc_state->infoframes.avi);
 919         intel_write_infoframe(encoder, crtc_state,
 920                               HDMI_INFOFRAME_TYPE_SPD,
 921                               &crtc_state->infoframes.spd);
 922         intel_write_infoframe(encoder, crtc_state,
 923                               HDMI_INFOFRAME_TYPE_VENDOR,
 924                               &crtc_state->infoframes.hdmi);
 925 }
 926
 927 /*
 928  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 929  *
 930  * From HDMI specification 1.4a:
 931  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 932  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 933  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 934  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 935  *   phase of 0
 936  */
 937 static bool gcp_default_phase_possible(int pipe_bpp,
 938                                        const struct drm_display_mode *mode)
 939 {
 940         unsigned int pixels_per_group;
 941
 942         switch (pipe_bpp) {
 943         case 30:
 944                 /* 4 pixels in 5 clocks */
 945                 pixels_per_group = 4;
 946                 break;
 947         case 36:
 948                 /* 2 pixels in 3 clocks */
 949                 pixels_per_group = 2;
 950                 break;
 951         case 48:
 952                 /* 1 pixel in 2 clocks */
 953                 pixels_per_group = 1;
 954                 break;
 955         default:
 956                 /* phase information not relevant for 8bpc */
 957                 return false;
 958         }
 959
 960         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 961                 mode->crtc_htotal % pixels_per_group == 0 &&
 962                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 963                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 964                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 965                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 966                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 967                  mode->crtc_htotal/2 % pixels_per_group == 0);
 968 }
 969
 970 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 971                                          const struct intel_crtc_state *crtc_state,
 972                                          const struct drm_connector_state *conn_state)
 973 {
 974         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 975         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 976         i915_reg_t reg;
 977
 978         if ((crtc_state->infoframes.enable &
 979              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 980                 return false;
 981
 982         if (HAS_DDI(dev_priv))
 983                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 984         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 985                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 986         else if (HAS_PCH_SPLIT(dev_priv))
 987                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 988         else
 989                 return false;
 990
 991         intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
 992
 993         return true;
 994 }
 995
 996 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 997                                    struct intel_crtc_state *crtc_state)
 998 {
 999         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1000         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1001         i915_reg_t reg;
1002
1003         if ((crtc_state->infoframes.enable &
1004              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1005                 return;
1006
1007         if (HAS_DDI(dev_priv))
1008                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1009         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1010                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1011         else if (HAS_PCH_SPLIT(dev_priv))
1012                 reg = TVIDEO_DIP_GCP(crtc->pipe);
1013         else
1014                 return;
1015
1016         crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1017 }
1018
1019 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1020                                              struct intel_crtc_state *crtc_state,
1021                                              struct drm_connector_state *conn_state)
1022 {
1023         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1024
1025         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1026                 return;
1027
1028         crtc_state->infoframes.enable |=
1029                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1030
1031         /* Indicate color indication for deep color mode */
1032         if (crtc_state->pipe_bpp > 24)
1033                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1034
1035         /* Enable default_phase whenever the display mode is suitably aligned */
1036         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1037                                        &crtc_state->hw.adjusted_mode))
1038                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1039 }
1040
1041 static void ibx_set_infoframes(struct intel_encoder *encoder,
1042                                bool enable,
1043                                const struct intel_crtc_state *crtc_state,
1044                                const struct drm_connector_state *conn_state)
1045 {
1046         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1047         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1048         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1049         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1050         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1051         u32 val = intel_de_read(dev_priv, reg);
1052         u32 port = VIDEO_DIP_PORT(encoder->port);
1053
1054         assert_hdmi_port_disabled(intel_hdmi);
1055
1056         /* See the big comment in g4x_set_infoframes() */
1057         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1058
1059         if (!enable) {
1060                 if (!(val & VIDEO_DIP_ENABLE))
1061                         return;
1062                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1063                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1064                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1065                 intel_de_write(dev_priv, reg, val);
1066                 intel_de_posting_read(dev_priv, reg);
1067                 return;
1068         }
1069
1070         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1071                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1072                          "DIP already enabled on port %c\n",
1073                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1074                 val &= ~VIDEO_DIP_PORT_MASK;
1075                 val |= port;
1076         }
1077
1078         val |= VIDEO_DIP_ENABLE;
1079         val &= ~(VIDEO_DIP_ENABLE_AVI |
1080                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1081                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1082
1083         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1084                 val |= VIDEO_DIP_ENABLE_GCP;
1085
1086         intel_de_write(dev_priv, reg, val);
1087         intel_de_posting_read(dev_priv, reg);
1088
1089         intel_write_infoframe(encoder, crtc_state,
1090                               HDMI_INFOFRAME_TYPE_AVI,
1091                               &crtc_state->infoframes.avi);
1092         intel_write_infoframe(encoder, crtc_state,
1093                               HDMI_INFOFRAME_TYPE_SPD,
1094                               &crtc_state->infoframes.spd);
1095         intel_write_infoframe(encoder, crtc_state,
1096                               HDMI_INFOFRAME_TYPE_VENDOR,
1097                               &crtc_state->infoframes.hdmi);
1098 }
1099
1100 static void cpt_set_infoframes(struct intel_encoder *encoder,
1101                                bool enable,
1102                                const struct intel_crtc_state *crtc_state,
1103                                const struct drm_connector_state *conn_state)
1104 {
1105         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1106         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1107         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1108         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1109         u32 val = intel_de_read(dev_priv, reg);
1110
1111         assert_hdmi_port_disabled(intel_hdmi);
1112
1113         /* See the big comment in g4x_set_infoframes() */
1114         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1115
1116         if (!enable) {
1117                 if (!(val & VIDEO_DIP_ENABLE))
1118                         return;
1119                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1120                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1121                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1122                 intel_de_write(dev_priv, reg, val);
1123                 intel_de_posting_read(dev_priv, reg);
1124                 return;
1125         }
1126
1127         /* Set both together, unset both together: see the spec. */
1128         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1129         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1130                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1131
1132         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1133                 val |= VIDEO_DIP_ENABLE_GCP;
1134
1135         intel_de_write(dev_priv, reg, val);
1136         intel_de_posting_read(dev_priv, reg);
1137
1138         intel_write_infoframe(encoder, crtc_state,
1139                               HDMI_INFOFRAME_TYPE_AVI,
1140                               &crtc_state->infoframes.avi);
1141         intel_write_infoframe(encoder, crtc_state,
1142                               HDMI_INFOFRAME_TYPE_SPD,
1143                               &crtc_state->infoframes.spd);
1144         intel_write_infoframe(encoder, crtc_state,
1145                               HDMI_INFOFRAME_TYPE_VENDOR,
1146                               &crtc_state->infoframes.hdmi);
1147 }
1148
1149 static void vlv_set_infoframes(struct intel_encoder *encoder,
1150                                bool enable,
1151                                const struct intel_crtc_state *crtc_state,
1152                                const struct drm_connector_state *conn_state)
1153 {
1154         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1155         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1156         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1157         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1158         u32 val = intel_de_read(dev_priv, reg);
1159         u32 port = VIDEO_DIP_PORT(encoder->port);
1160
1161         assert_hdmi_port_disabled(intel_hdmi);
1162
1163         /* See the big comment in g4x_set_infoframes() */
1164         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1165
1166         if (!enable) {
1167                 if (!(val & VIDEO_DIP_ENABLE))
1168                         return;
1169                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1170                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1171                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1172                 intel_de_write(dev_priv, reg, val);
1173                 intel_de_posting_read(dev_priv, reg);
1174                 return;
1175         }
1176
1177         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1178                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1179                          "DIP already enabled on port %c\n",
1180                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1181                 val &= ~VIDEO_DIP_PORT_MASK;
1182                 val |= port;
1183         }
1184
1185         val |= VIDEO_DIP_ENABLE;
1186         val &= ~(VIDEO_DIP_ENABLE_AVI |
1187                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1188                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1189
1190         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1191                 val |= VIDEO_DIP_ENABLE_GCP;
1192
1193         intel_de_write(dev_priv, reg, val);
1194         intel_de_posting_read(dev_priv, reg);
1195
1196         intel_write_infoframe(encoder, crtc_state,
1197                               HDMI_INFOFRAME_TYPE_AVI,
1198                               &crtc_state->infoframes.avi);
1199         intel_write_infoframe(encoder, crtc_state,
1200                               HDMI_INFOFRAME_TYPE_SPD,
1201                               &crtc_state->infoframes.spd);
1202         intel_write_infoframe(encoder, crtc_state,
1203                               HDMI_INFOFRAME_TYPE_VENDOR,
1204                               &crtc_state->infoframes.hdmi);
1205 }
1206
1207 static void hsw_set_infoframes(struct intel_encoder *encoder,
1208                                bool enable,
1209                                const struct intel_crtc_state *crtc_state,
1210                                const struct drm_connector_state *conn_state)
1211 {
1212         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1213         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1214         u32 val = intel_de_read(dev_priv, reg);
1215
1216         assert_hdmi_transcoder_func_disabled(dev_priv,
1217                                              crtc_state->cpu_transcoder);
1218
1219         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1220                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1221                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1222                  VIDEO_DIP_ENABLE_DRM_GLK);
1223
1224         if (!enable) {
1225                 intel_de_write(dev_priv, reg, val);
1226                 intel_de_posting_read(dev_priv, reg);
1227                 return;
1228         }
1229
1230         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1231                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1232
1233         intel_de_write(dev_priv, reg, val);
1234         intel_de_posting_read(dev_priv, reg);
1235
1236         intel_write_infoframe(encoder, crtc_state,
1237                               HDMI_INFOFRAME_TYPE_AVI,
1238                               &crtc_state->infoframes.avi);
1239         intel_write_infoframe(encoder, crtc_state,
1240                               HDMI_INFOFRAME_TYPE_SPD,
1241                               &crtc_state->infoframes.spd);
1242         intel_write_infoframe(encoder, crtc_state,
1243                               HDMI_INFOFRAME_TYPE_VENDOR,
1244                               &crtc_state->infoframes.hdmi);
1245         intel_write_infoframe(encoder, crtc_state,
1246                               HDMI_INFOFRAME_TYPE_DRM,
1247                               &crtc_state->infoframes.drm);
1248 }
1249
1250 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1251 {
1252         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1253         struct i2c_adapter *adapter;
1254
1255         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1256                 return;
1257
1258         adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1259
1260         drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1261                     enable ? "Enabling" : "Disabling");
1262
1263         drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1264 }
1265
1266 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1267                                 unsigned int offset, void *buffer, size_t size)
1268 {
1269         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1270         struct intel_hdmi *hdmi = &dig_port->hdmi;
1271         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1272                                                               hdmi->ddc_bus);
1273         int ret;
1274         u8 start = offset & 0xff;
1275         struct i2c_msg msgs[] = {
1276                 {
1277                         .addr = DRM_HDCP_DDC_ADDR,
1278                         .flags = 0,
1279                         .len = 1,
1280                         .buf = &start,
1281                 },
1282                 {
1283                         .addr = DRM_HDCP_DDC_ADDR,
1284                         .flags = I2C_M_RD,
1285                         .len = size,
1286                         .buf = buffer
1287                 }
1288         };
1289         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1290         if (ret == ARRAY_SIZE(msgs))
1291                 return 0;
1292         return ret >= 0 ? -EIO : ret;
1293 }
1294
1295 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1296                                  unsigned int offset, void *buffer, size_t size)
1297 {
1298         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1299         struct intel_hdmi *hdmi = &dig_port->hdmi;
1300         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1301                                                               hdmi->ddc_bus);
1302         int ret;
1303         u8 *write_buf;
1304         struct i2c_msg msg;
1305
1306         write_buf = kzalloc(size + 1, GFP_KERNEL);
1307         if (!write_buf)
1308                 return -ENOMEM;
1309
1310         write_buf[0] = offset & 0xff;
1311         memcpy(&write_buf[1], buffer, size);
1312
1313         msg.addr = DRM_HDCP_DDC_ADDR;
1314         msg.flags = 0,
1315         msg.len = size + 1,
1316         msg.buf = write_buf;
1317
1318         ret = i2c_transfer(adapter, &msg, 1);
1319         if (ret == 1)
1320                 ret = 0;
1321         else if (ret >= 0)
1322                 ret = -EIO;
1323
1324         kfree(write_buf);
1325         return ret;
1326 }
1327
1328 static
1329 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1330                                   u8 *an)
1331 {
1332         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1333         struct intel_hdmi *hdmi = &dig_port->hdmi;
1334         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1335                                                               hdmi->ddc_bus);
1336         int ret;
1337
1338         ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1339                                     DRM_HDCP_AN_LEN);
1340         if (ret) {
1341                 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1342                             ret);
1343                 return ret;
1344         }
1345
1346         ret = intel_gmbus_output_aksv(adapter);
1347         if (ret < 0) {
1348                 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1349                 return ret;
1350         }
1351         return 0;
1352 }
1353
1354 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1355                                      u8 *bksv)
1356 {
1357         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1358
1359         int ret;
1360         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1361                                    DRM_HDCP_KSV_LEN);
1362         if (ret)
1363                 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1364                             ret);
1365         return ret;
1366 }
1367
1368 static
1369 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1370                                  u8 *bstatus)
1371 {
1372         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1373
1374         int ret;
1375         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1376                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1377         if (ret)
1378                 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1379                             ret);
1380         return ret;
1381 }
1382
1383 static
1384 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1385                                      bool *repeater_present)
1386 {
1387         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1388         int ret;
1389         u8 val;
1390
1391         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1392         if (ret) {
1393                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1394                             ret);
1395                 return ret;
1396         }
1397         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1398         return 0;
1399 }
1400
1401 static
1402 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1403                                   u8 *ri_prime)
1404 {
1405         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1406
1407         int ret;
1408         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1409                                    ri_prime, DRM_HDCP_RI_LEN);
1410         if (ret)
1411                 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1412                             ret);
1413         return ret;
1414 }
1415
1416 static
1417 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1418                                    bool *ksv_ready)
1419 {
1420         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1421         int ret;
1422         u8 val;
1423
1424         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1425         if (ret) {
1426                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1427                             ret);
1428                 return ret;
1429         }
1430         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1431         return 0;
1432 }
1433
1434 static
1435 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1436                                   int num_downstream, u8 *ksv_fifo)
1437 {
1438         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1439         int ret;
1440         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1441                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1442         if (ret) {
1443                 drm_dbg_kms(&i915->drm,
1444                             "Read ksv fifo over DDC failed (%d)\n", ret);
1445                 return ret;
1446         }
1447         return 0;
1448 }
1449
1450 static
1451 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1452                                       int i, u32 *part)
1453 {
1454         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1455         int ret;
1456
1457         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1458                 return -EINVAL;
1459
1460         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1461                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1462         if (ret)
1463                 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1464                             i, ret);
1465         return ret;
1466 }
1467
1468 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1469                                            enum transcoder cpu_transcoder)
1470 {
1471         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1472         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1473         struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1474         u32 scanline;
1475         int ret;
1476
1477         for (;;) {
1478                 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1479                 if (scanline > 100 && scanline < 200)
1480                         break;
1481                 usleep_range(25, 50);
1482         }
1483
1484         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1485                                          false, TRANS_DDI_HDCP_SIGNALLING);
1486         if (ret) {
1487                 drm_err(&dev_priv->drm,
1488                         "Disable HDCP signalling failed (%d)\n", ret);
1489                 return ret;
1490         }
1491
1492         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1493                                          true, TRANS_DDI_HDCP_SIGNALLING);
1494         if (ret) {
1495                 drm_err(&dev_priv->drm,
1496                         "Enable HDCP signalling failed (%d)\n", ret);
1497                 return ret;
1498         }
1499
1500         return 0;
1501 }
1502
1503 static
1504 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1505                                       enum transcoder cpu_transcoder,
1506                                       bool enable)
1507 {
1508         struct intel_hdmi *hdmi = &dig_port->hdmi;
1509         struct intel_connector *connector = hdmi->attached_connector;
1510         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1511         int ret;
1512
1513         if (!enable)
1514                 usleep_range(6, 60); /* Bspec says >= 6us */
1515
1516         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1517                                          cpu_transcoder, enable,
1518                                          TRANS_DDI_HDCP_SIGNALLING);
1519         if (ret) {
1520                 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1521                         enable ? "Enable" : "Disable", ret);
1522                 return ret;
1523         }
1524
1525         /*
1526          * WA: To fix incorrect positioning of the window of
1527          * opportunity and enc_en signalling in KABYLAKE.
1528          */
1529         if (IS_KABYLAKE(dev_priv) && enable)
1530                 return kbl_repositioning_enc_en_signal(connector,
1531                                                        cpu_transcoder);
1532
1533         return 0;
1534 }
1535
1536 static
1537 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1538                                      struct intel_connector *connector)
1539 {
1540         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1541         enum port port = dig_port->base.port;
1542         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1543         int ret;
1544         union {
1545                 u32 reg;
1546                 u8 shim[DRM_HDCP_RI_LEN];
1547         } ri;
1548
1549         ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1550         if (ret)
1551                 return false;
1552
1553         intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1554
1555         /* Wait for Ri prime match */
1556         if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1557                       (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1558                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1559                 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1560                         intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1561                                                         port)));
1562                 return false;
1563         }
1564         return true;
1565 }
1566
1567 static
1568 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1569                                 struct intel_connector *connector)
1570 {
1571         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1572         int retry;
1573
1574         for (retry = 0; retry < 3; retry++)
1575                 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1576                         return true;
1577
1578         drm_err(&i915->drm, "Link check failed\n");
1579         return false;
1580 }
1581
1582 struct hdcp2_hdmi_msg_timeout {
1583         u8 msg_id;
1584         u16 timeout;
1585 };
1586
1587 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1588         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1589         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1590         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1591         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1592         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1593 };
1594
1595 static
1596 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1597                                     u8 *rx_status)
1598 {
1599         return intel_hdmi_hdcp_read(dig_port,
1600                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1601                                     rx_status,
1602                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1603 }
1604
1605 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1606 {
1607         int i;
1608
1609         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1610                 if (is_paired)
1611                         return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1612                 else
1613                         return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1614         }
1615
1616         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1617                 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1618                         return hdcp2_msg_timeout[i].timeout;
1619         }
1620
1621         return -EINVAL;
1622 }
1623
1624 static int
1625 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1626                               u8 msg_id, bool *msg_ready,
1627                               ssize_t *msg_sz)
1628 {
1629         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1630         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1631         int ret;
1632
1633         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1634         if (ret < 0) {
1635                 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1636                             ret);
1637                 return ret;
1638         }
1639
1640         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1641                   rx_status[0]);
1642
1643         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1644                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1645                              *msg_sz);
1646         else
1647                 *msg_ready = *msg_sz;
1648
1649         return 0;
1650 }
1651
1652 static ssize_t
1653 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1654                               u8 msg_id, bool paired)
1655 {
1656         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1657         bool msg_ready = false;
1658         int timeout, ret;
1659         ssize_t msg_sz = 0;
1660
1661         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1662         if (timeout < 0)
1663                 return timeout;
1664
1665         ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1666                                                              msg_id, &msg_ready,
1667                                                              &msg_sz),
1668                          !ret && msg_ready && msg_sz, timeout * 1000,
1669                          1000, 5 * 1000);
1670         if (ret)
1671                 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1672                             msg_id, ret, timeout);
1673
1674         return ret ? ret : msg_sz;
1675 }
1676
1677 static
1678 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1679                                void *buf, size_t size)
1680 {
1681         unsigned int offset;
1682
1683         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1684         return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1685 }
1686
1687 static
1688 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1689                               u8 msg_id, void *buf, size_t size)
1690 {
1691         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1692         struct intel_hdmi *hdmi = &dig_port->hdmi;
1693         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1694         unsigned int offset;
1695         ssize_t ret;
1696
1697         ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1698                                             hdcp->is_paired);
1699         if (ret < 0)
1700                 return ret;
1701
1702         /*
1703          * Available msg size should be equal to or lesser than the
1704          * available buffer.
1705          */
1706         if (ret > size) {
1707                 drm_dbg_kms(&i915->drm,
1708                             "msg_sz(%zd) is more than exp size(%zu)\n",
1709                             ret, size);
1710                 return -EINVAL;
1711         }
1712
1713         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1714         ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1715         if (ret)
1716                 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1717                             msg_id, ret);
1718
1719         return ret;
1720 }
1721
1722 static
1723 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1724                                 struct intel_connector *connector)
1725 {
1726         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1727         int ret;
1728
1729         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1730         if (ret)
1731                 return ret;
1732
1733         /*
1734          * Re-auth request and Link Integrity Failures are represented by
1735          * same bit. i.e reauth_req.
1736          */
1737         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1738                 ret = HDCP_REAUTH_REQUEST;
1739         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1740                 ret = HDCP_TOPOLOGY_CHANGE;
1741
1742         return ret;
1743 }
1744
1745 static
1746 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1747                              bool *capable)
1748 {
1749         u8 hdcp2_version;
1750         int ret;
1751
1752         *capable = false;
1753         ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1754                                    &hdcp2_version, sizeof(hdcp2_version));
1755         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1756                 *capable = true;
1757
1758         return ret;
1759 }
1760
1761 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1762         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1763         .read_bksv = intel_hdmi_hdcp_read_bksv,
1764         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1765         .repeater_present = intel_hdmi_hdcp_repeater_present,
1766         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1767         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1768         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1769         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1770         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1771         .check_link = intel_hdmi_hdcp_check_link,
1772         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1773         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1774         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1775         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1776         .protocol = HDCP_PROTOCOL_HDMI,
1777 };
1778
1779 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1780 {
1781         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1782         int max_tmds_clock, vbt_max_tmds_clock;
1783
1784         if (DISPLAY_VER(dev_priv) >= 10)
1785                 max_tmds_clock = 594000;
1786         else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1787                 max_tmds_clock = 300000;
1788         else if (DISPLAY_VER(dev_priv) >= 5)
1789                 max_tmds_clock = 225000;
1790         else
1791                 max_tmds_clock = 165000;
1792
1793         vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1794         if (vbt_max_tmds_clock)
1795                 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1796
1797         return max_tmds_clock;
1798 }
1799
1800 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1801                                 const struct drm_connector_state *conn_state)
1802 {
1803         return hdmi->has_hdmi_sink &&
1804                 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1805 }
1806
1807 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1808 {
1809         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1810 }
1811
1812 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1813                                  bool respect_downstream_limits,
1814                                  bool has_hdmi_sink)
1815 {
1816         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1817         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1818
1819         if (respect_downstream_limits) {
1820                 struct intel_connector *connector = hdmi->attached_connector;
1821                 const struct drm_display_info *info = &connector->base.display_info;
1822
1823                 if (hdmi->dp_dual_mode.max_tmds_clock)
1824                         max_tmds_clock = min(max_tmds_clock,
1825                                              hdmi->dp_dual_mode.max_tmds_clock);
1826
1827                 if (info->max_tmds_clock)
1828                         max_tmds_clock = min(max_tmds_clock,
1829                                              info->max_tmds_clock);
1830                 else if (!has_hdmi_sink)
1831                         max_tmds_clock = min(max_tmds_clock, 165000);
1832         }
1833
1834         return max_tmds_clock;
1835 }
1836
1837 static enum drm_mode_status
1838 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1839                       int clock, bool respect_downstream_limits,
1840                       bool has_hdmi_sink)
1841 {
1842         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1843         enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1844
1845         if (clock < 25000)
1846                 return MODE_CLOCK_LOW;
1847         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1848                                           has_hdmi_sink))
1849                 return MODE_CLOCK_HIGH;
1850
1851         /* GLK DPLL can't generate 446-480 MHz */
1852         if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1853                 return MODE_CLOCK_RANGE;
1854
1855         /* BXT/GLK DPLL can't generate 223-240 MHz */
1856         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1857             clock > 223333 && clock < 240000)
1858                 return MODE_CLOCK_RANGE;
1859
1860         /* CHV DPLL can't generate 216-240 MHz */
1861         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1862                 return MODE_CLOCK_RANGE;
1863
1864         /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1865         if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1866                 return MODE_CLOCK_RANGE;
1867
1868         /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1869         if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1870                 return MODE_CLOCK_RANGE;
1871
1872         /*
1873          * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1874          * set of link rates.
1875          *
1876          * FIXME: We will hopefully get an algorithmic way of programming
1877          * the MPLLB for HDMI in the future.
1878          */
1879         if (IS_DG2(dev_priv))
1880                 return intel_snps_phy_check_hdmi_link_rate(clock);
1881
1882         return MODE_OK;
1883 }
1884
1885 int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
1886 {
1887         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1888         if (ycbcr420_output)
1889                 clock /= 2;
1890
1891         /*
1892          * Need to adjust the port link by:
1893          *  1.5x for 12bpc
1894          *  1.25x for 10bpc
1895          */
1896         return DIV_ROUND_CLOSEST(clock * bpc, 8);
1897 }
1898
1899 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1900 {
1901         switch (bpc) {
1902         case 12:
1903                 return !HAS_GMCH(i915);
1904         case 10:
1905                 return DISPLAY_VER(i915) >= 11;
1906         case 8:
1907                 return true;
1908         default:
1909                 MISSING_CASE(bpc);
1910                 return false;
1911         }
1912 }
1913
1914 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1915                                          int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1916 {
1917         const struct drm_display_info *info = &connector->display_info;
1918         const struct drm_hdmi_info *hdmi = &info->hdmi;
1919
1920         switch (bpc) {
1921         case 12:
1922                 if (!has_hdmi_sink)
1923                         return false;
1924
1925                 if (ycbcr420_output)
1926                         return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1927                 else
1928                         return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1929         case 10:
1930                 if (!has_hdmi_sink)
1931                         return false;
1932
1933                 if (ycbcr420_output)
1934                         return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1935                 else
1936                         return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1937         case 8:
1938                 return true;
1939         default:
1940                 MISSING_CASE(bpc);
1941                 return false;
1942         }
1943 }
1944
1945 static enum drm_mode_status
1946 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1947                             bool has_hdmi_sink, bool ycbcr420_output)
1948 {
1949         struct drm_i915_private *i915 = to_i915(connector->dev);
1950         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1951         enum drm_mode_status status = MODE_OK;
1952         int bpc;
1953
1954         /*
1955          * Try all color depths since valid port clock range
1956          * can have holes. Any mode that can be used with at
1957          * least one color depth is accepted.
1958          */
1959         for (bpc = 12; bpc >= 8; bpc -= 2) {
1960                 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
1961
1962                 if (!intel_hdmi_source_bpc_possible(i915, bpc))
1963                         continue;
1964
1965                 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1966                         continue;
1967
1968                 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1969                 if (status == MODE_OK)
1970                         return MODE_OK;
1971         }
1972
1973         /* can never happen */
1974         drm_WARN_ON(&i915->drm, status == MODE_OK);
1975
1976         return status;
1977 }
1978
1979 static enum drm_mode_status
1980 intel_hdmi_mode_valid(struct drm_connector *connector,
1981                       struct drm_display_mode *mode)
1982 {
1983         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1984         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1985         enum drm_mode_status status;
1986         int clock = mode->clock;
1987         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1988         bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1989         bool ycbcr_420_only;
1990
1991         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1992                 return MODE_NO_DBLESCAN;
1993
1994         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1995                 clock *= 2;
1996
1997         if (clock > max_dotclk)
1998                 return MODE_CLOCK_HIGH;
1999
2000         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2001                 if (!has_hdmi_sink)
2002                         return MODE_CLOCK_LOW;
2003                 clock *= 2;
2004         }
2005
2006         /*
2007          * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2008          * enumerated only if FRL is supported. Current platforms do not support
2009          * FRL so prune the higher resolution modes that require doctclock more
2010          * than 600MHz.
2011          */
2012         if (clock > 600000)
2013                 return MODE_CLOCK_HIGH;
2014
2015         ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2016
2017         status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
2018         if (status != MODE_OK) {
2019                 if (ycbcr_420_only ||
2020                     !connector->ycbcr_420_allowed ||
2021                     !drm_mode_is_420_also(&connector->display_info, mode))
2022                         return status;
2023
2024                 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
2025                 if (status != MODE_OK)
2026                         return status;
2027         }
2028
2029         return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2030 }
2031
2032 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2033                              int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2034 {
2035         struct drm_atomic_state *state = crtc_state->uapi.state;
2036         struct drm_connector_state *connector_state;
2037         struct drm_connector *connector;
2038         int i;
2039
2040         for_each_new_connector_in_state(state, connector, connector_state, i) {
2041                 if (connector_state->crtc != crtc_state->uapi.crtc)
2042                         continue;
2043
2044                 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2045                         return false;
2046         }
2047
2048         return true;
2049 }
2050
2051 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2052 {
2053         struct drm_i915_private *dev_priv =
2054                 to_i915(crtc_state->uapi.crtc->dev);
2055         const struct drm_display_mode *adjusted_mode =
2056                 &crtc_state->hw.adjusted_mode;
2057
2058         if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2059                 return false;
2060
2061         /*
2062          * HDMI deep color affects the clocks, so it's only possible
2063          * when not cloning with other encoder types.
2064          */
2065         if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2066                 return false;
2067
2068         /* Display Wa_1405510057:icl,ehl */
2069         if (intel_hdmi_is_ycbcr420(crtc_state) &&
2070             bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2071             (adjusted_mode->crtc_hblank_end -
2072              adjusted_mode->crtc_hblank_start) % 8 == 2)
2073                 return false;
2074
2075         return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
2076                                        intel_hdmi_is_ycbcr420(crtc_state));
2077 }
2078
2079 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2080                                   struct intel_crtc_state *crtc_state,
2081                                   int clock, bool respect_downstream_limits)
2082 {
2083         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2084         bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
2085         int bpc;
2086
2087         /*
2088          * pipe_bpp could already be below 8bpc due to FDI
2089          * bandwidth constraints. HDMI minimum is 8bpc however.
2090          */
2091         bpc = max(crtc_state->pipe_bpp / 3, 8);
2092
2093         /*
2094          * We will never exceed downstream TMDS clock limits while
2095          * attempting deep color. If the user insists on forcing an
2096          * out of spec mode they will have to be satisfied with 8bpc.
2097          */
2098         if (!respect_downstream_limits)
2099                 bpc = 8;
2100
2101         for (; bpc >= 8; bpc -= 2) {
2102                 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
2103
2104                 if (hdmi_bpc_possible(crtc_state, bpc) &&
2105                     hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2106                                           respect_downstream_limits,
2107                                           crtc_state->has_hdmi_sink) == MODE_OK)
2108                         return bpc;
2109         }
2110
2111         return -EINVAL;
2112 }
2113
2114 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2115                                     struct intel_crtc_state *crtc_state,
2116                                     bool respect_downstream_limits)
2117 {
2118         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2119         const struct drm_display_mode *adjusted_mode =
2120                 &crtc_state->hw.adjusted_mode;
2121         int bpc, clock = adjusted_mode->crtc_clock;
2122
2123         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2124                 clock *= 2;
2125
2126         bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2127                                      respect_downstream_limits);
2128         if (bpc < 0)
2129                 return bpc;
2130
2131         crtc_state->port_clock =
2132                 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
2133
2134         /*
2135          * pipe_bpp could already be below 8bpc due to
2136          * FDI bandwidth constraints. We shouldn't bump it
2137          * back up to the HDMI minimum 8bpc in that case.
2138          */
2139         crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2140
2141         drm_dbg_kms(&i915->drm,
2142                     "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2143                     bpc, crtc_state->pipe_bpp);
2144
2145         return 0;
2146 }
2147
2148 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2149                                     const struct drm_connector_state *conn_state)
2150 {
2151         const struct intel_digital_connector_state *intel_conn_state =
2152                 to_intel_digital_connector_state(conn_state);
2153         const struct drm_display_mode *adjusted_mode =
2154                 &crtc_state->hw.adjusted_mode;
2155
2156         /*
2157          * Our YCbCr output is always limited range.
2158          * crtc_state->limited_color_range only applies to RGB,
2159          * and it must never be set for YCbCr or we risk setting
2160          * some conflicting bits in PIPECONF which will mess up
2161          * the colors on the monitor.
2162          */
2163         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2164                 return false;
2165
2166         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2167                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2168                 return crtc_state->has_hdmi_sink &&
2169                         drm_default_rgb_quant_range(adjusted_mode) ==
2170                         HDMI_QUANTIZATION_RANGE_LIMITED;
2171         } else {
2172                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2173         }
2174 }
2175
2176 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2177                                  const struct intel_crtc_state *crtc_state,
2178                                  const struct drm_connector_state *conn_state)
2179 {
2180         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2181         const struct intel_digital_connector_state *intel_conn_state =
2182                 to_intel_digital_connector_state(conn_state);
2183
2184         if (!crtc_state->has_hdmi_sink)
2185                 return false;
2186
2187         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2188                 return intel_hdmi->has_audio;
2189         else
2190                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2191 }
2192
2193 static enum intel_output_format
2194 intel_hdmi_output_format(struct intel_connector *connector,
2195                          bool ycbcr_420_output)
2196 {
2197         if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2198                 return INTEL_OUTPUT_FORMAT_YCBCR420;
2199         else
2200                 return INTEL_OUTPUT_FORMAT_RGB;
2201 }
2202
2203 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2204                                             struct intel_crtc_state *crtc_state,
2205                                             const struct drm_connector_state *conn_state,
2206                                             bool respect_downstream_limits)
2207 {
2208         struct intel_connector *connector = to_intel_connector(conn_state->connector);
2209         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2210         const struct drm_display_info *info = &connector->base.display_info;
2211         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2212         bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2213         int ret;
2214
2215         crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only);
2216
2217         if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
2218                 drm_dbg_kms(&i915->drm,
2219                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2220                 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2221         }
2222
2223         ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2224         if (ret) {
2225                 if (intel_hdmi_is_ycbcr420(crtc_state) ||
2226                     !connector->base.ycbcr_420_allowed ||
2227                     !drm_mode_is_420_also(info, adjusted_mode))
2228                         return ret;
2229
2230                 crtc_state->output_format = intel_hdmi_output_format(connector, true);
2231                 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2232         }
2233
2234         return ret;
2235 }
2236
2237 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2238                               struct intel_crtc_state *pipe_config,
2239                               struct drm_connector_state *conn_state)
2240 {
2241         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2242         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2243         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2244         struct drm_connector *connector = conn_state->connector;
2245         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2246         int ret;
2247
2248         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2249                 return -EINVAL;
2250
2251         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2252         pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2253                                                          conn_state);
2254
2255         if (pipe_config->has_hdmi_sink)
2256                 pipe_config->has_infoframe = true;
2257
2258         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2259                 pipe_config->pixel_multiplier = 2;
2260
2261         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2262                 pipe_config->has_pch_encoder = true;
2263
2264         pipe_config->has_audio =
2265                 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2266
2267         /*
2268          * Try to respect downstream TMDS clock limits first, if
2269          * that fails assume the user might know something we don't.
2270          */
2271         ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2272         if (ret)
2273                 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2274         if (ret) {
2275                 drm_dbg_kms(&dev_priv->drm,
2276                             "unsupported HDMI clock (%d kHz), rejecting mode\n",
2277                             pipe_config->hw.adjusted_mode.crtc_clock);
2278                 return ret;
2279         }
2280
2281         if (intel_hdmi_is_ycbcr420(pipe_config)) {
2282                 ret = intel_panel_fitting(pipe_config, conn_state);
2283                 if (ret)
2284                         return ret;
2285         }
2286
2287         pipe_config->limited_color_range =
2288                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2289
2290         if (conn_state->picture_aspect_ratio)
2291                 adjusted_mode->picture_aspect_ratio =
2292                         conn_state->picture_aspect_ratio;
2293
2294         pipe_config->lane_count = 4;
2295
2296         if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2297                 if (scdc->scrambling.low_rates)
2298                         pipe_config->hdmi_scrambling = true;
2299
2300                 if (pipe_config->port_clock > 340000) {
2301                         pipe_config->hdmi_scrambling = true;
2302                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2303                 }
2304         }
2305
2306         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2307                                          conn_state);
2308
2309         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2310                 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2311                 return -EINVAL;
2312         }
2313
2314         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2315                 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2316                 return -EINVAL;
2317         }
2318
2319         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2320                 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2321                 return -EINVAL;
2322         }
2323
2324         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2325                 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2326                 return -EINVAL;
2327         }
2328
2329         return 0;
2330 }
2331
2332 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2333 {
2334         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2335
2336         /*
2337          * Give a hand to buggy BIOSen which forget to turn
2338          * the TMDS output buffers back on after a reboot.
2339          */
2340         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2341 }
2342
2343 static void
2344 intel_hdmi_unset_edid(struct drm_connector *connector)
2345 {
2346         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2347
2348         intel_hdmi->has_hdmi_sink = false;
2349         intel_hdmi->has_audio = false;
2350
2351         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2352         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2353
2354         kfree(to_intel_connector(connector)->detect_edid);
2355         to_intel_connector(connector)->detect_edid = NULL;
2356 }
2357
2358 static void
2359 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2360 {
2361         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2362         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2363         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2364         struct i2c_adapter *adapter =
2365                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2366         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2367
2368         /*
2369          * Type 1 DVI adaptors are not required to implement any
2370          * registers, so we can't always detect their presence.
2371          * Ideally we should be able to check the state of the
2372          * CONFIG1 pin, but no such luck on our hardware.
2373          *
2374          * The only method left to us is to check the VBT to see
2375          * if the port is a dual mode capable DP port.
2376          */
2377         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2378                 if (!connector->force &&
2379                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2380                         drm_dbg_kms(&dev_priv->drm,
2381                                     "Assuming DP dual mode adaptor presence based on VBT\n");
2382                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2383                 } else {
2384                         type = DRM_DP_DUAL_MODE_NONE;
2385                 }
2386         }
2387
2388         if (type == DRM_DP_DUAL_MODE_NONE)
2389                 return;
2390
2391         hdmi->dp_dual_mode.type = type;
2392         hdmi->dp_dual_mode.max_tmds_clock =
2393                 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2394
2395         drm_dbg_kms(&dev_priv->drm,
2396                     "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2397                     drm_dp_get_dual_mode_type_name(type),
2398                     hdmi->dp_dual_mode.max_tmds_clock);
2399
2400         /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2401         if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2402             !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2403                 drm_dbg_kms(&dev_priv->drm,
2404                             "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2405                 hdmi->dp_dual_mode.max_tmds_clock = 0;
2406         }
2407 }
2408
2409 static bool
2410 intel_hdmi_set_edid(struct drm_connector *connector)
2411 {
2412         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2413         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2414         intel_wakeref_t wakeref;
2415         struct edid *edid;
2416         bool connected = false;
2417         struct i2c_adapter *i2c;
2418
2419         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2420
2421         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2422
2423         edid = drm_get_edid(connector, i2c);
2424
2425         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2426                 drm_dbg_kms(&dev_priv->drm,
2427                             "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2428                 intel_gmbus_force_bit(i2c, true);
2429                 edid = drm_get_edid(connector, i2c);
2430                 intel_gmbus_force_bit(i2c, false);
2431         }
2432
2433         to_intel_connector(connector)->detect_edid = edid;
2434         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2435                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2436                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2437
2438                 intel_hdmi_dp_dual_mode_detect(connector);
2439
2440                 connected = true;
2441         }
2442
2443         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2444
2445         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2446
2447         return connected;
2448 }
2449
2450 static enum drm_connector_status
2451 intel_hdmi_detect(struct drm_connector *connector, bool force)
2452 {
2453         enum drm_connector_status status = connector_status_disconnected;
2454         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2455         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2456         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2457         intel_wakeref_t wakeref;
2458
2459         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2460                     connector->base.id, connector->name);
2461
2462         if (!INTEL_DISPLAY_ENABLED(dev_priv))
2463                 return connector_status_disconnected;
2464
2465         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2466
2467         if (DISPLAY_VER(dev_priv) >= 11 &&
2468             !intel_digital_port_connected(encoder))
2469                 goto out;
2470
2471         intel_hdmi_unset_edid(connector);
2472
2473         if (intel_hdmi_set_edid(connector))
2474                 status = connector_status_connected;
2475
2476 out:
2477         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2478
2479         if (status != connector_status_connected)
2480                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2481
2482         /*
2483          * Make sure the refs for power wells enabled during detect are
2484          * dropped to avoid a new detect cycle triggered by HPD polling.
2485          */
2486         intel_display_power_flush_work(dev_priv);
2487
2488         return status;
2489 }
2490
2491 static void
2492 intel_hdmi_force(struct drm_connector *connector)
2493 {
2494         struct drm_i915_private *i915 = to_i915(connector->dev);
2495
2496         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2497                     connector->base.id, connector->name);
2498
2499         intel_hdmi_unset_edid(connector);
2500
2501         if (connector->status != connector_status_connected)
2502                 return;
2503
2504         intel_hdmi_set_edid(connector);
2505 }
2506
2507 static int intel_hdmi_get_modes(struct drm_connector *connector)
2508 {
2509         struct edid *edid;
2510
2511         edid = to_intel_connector(connector)->detect_edid;
2512         if (edid == NULL)
2513                 return 0;
2514
2515         return intel_connector_update_modes(connector, edid);
2516 }
2517
2518 static struct i2c_adapter *
2519 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2520 {
2521         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2522         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2523
2524         return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2525 }
2526
2527 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2528 {
2529         struct drm_i915_private *i915 = to_i915(connector->dev);
2530         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2531         struct kobject *i2c_kobj = &adapter->dev.kobj;
2532         struct kobject *connector_kobj = &connector->kdev->kobj;
2533         int ret;
2534
2535         ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2536         if (ret)
2537                 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2538 }
2539
2540 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2541 {
2542         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2543         struct kobject *i2c_kobj = &adapter->dev.kobj;
2544         struct kobject *connector_kobj = &connector->kdev->kobj;
2545
2546         sysfs_remove_link(connector_kobj, i2c_kobj->name);
2547 }
2548
2549 static int
2550 intel_hdmi_connector_register(struct drm_connector *connector)
2551 {
2552         int ret;
2553
2554         ret = intel_connector_register(connector);
2555         if (ret)
2556                 return ret;
2557
2558         intel_hdmi_create_i2c_symlink(connector);
2559
2560         return ret;
2561 }
2562
2563 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2564 {
2565         struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2566
2567         cec_notifier_conn_unregister(n);
2568
2569         intel_hdmi_remove_i2c_symlink(connector);
2570         intel_connector_unregister(connector);
2571 }
2572
2573 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2574         .detect = intel_hdmi_detect,
2575         .force = intel_hdmi_force,
2576         .fill_modes = drm_helper_probe_single_connector_modes,
2577         .atomic_get_property = intel_digital_connector_atomic_get_property,
2578         .atomic_set_property = intel_digital_connector_atomic_set_property,
2579         .late_register = intel_hdmi_connector_register,
2580         .early_unregister = intel_hdmi_connector_unregister,
2581         .destroy = intel_connector_destroy,
2582         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2583         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2584 };
2585
2586 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2587         .get_modes = intel_hdmi_get_modes,
2588         .mode_valid = intel_hdmi_mode_valid,
2589         .atomic_check = intel_digital_connector_atomic_check,
2590 };
2591
2592 static void
2593 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2594 {
2595         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2596
2597         intel_attach_force_audio_property(connector);
2598         intel_attach_broadcast_rgb_property(connector);
2599         intel_attach_aspect_ratio_property(connector);
2600
2601         intel_attach_hdmi_colorspace_property(connector);
2602         drm_connector_attach_content_type_property(connector);
2603
2604         if (DISPLAY_VER(dev_priv) >= 10)
2605                 drm_connector_attach_hdr_output_metadata_property(connector);
2606
2607         if (!HAS_GMCH(dev_priv))
2608                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2609 }
2610
2611 /*
2612  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2613  * @encoder: intel_encoder
2614  * @connector: drm_connector
2615  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2616  *  or reset the high tmds clock ratio for scrambling
2617  * @scrambling: bool to Indicate if the function needs to set or reset
2618  *  sink scrambling
2619  *
2620  * This function handles scrambling on HDMI 2.0 capable sinks.
2621  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2622  * it enables scrambling. This should be called before enabling the HDMI
2623  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2624  * detect a scrambled clock within 100 ms.
2625  *
2626  * Returns:
2627  * True on success, false on failure.
2628  */
2629 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2630                                        struct drm_connector *connector,
2631                                        bool high_tmds_clock_ratio,
2632                                        bool scrambling)
2633 {
2634         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2635         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2636         struct drm_scrambling *sink_scrambling =
2637                 &connector->display_info.hdmi.scdc.scrambling;
2638         struct i2c_adapter *adapter =
2639                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2640
2641         if (!sink_scrambling->supported)
2642                 return true;
2643
2644         drm_dbg_kms(&dev_priv->drm,
2645                     "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2646                     connector->base.id, connector->name,
2647                     str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2648
2649         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2650         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2651                                                   high_tmds_clock_ratio) &&
2652                 drm_scdc_set_scrambling(adapter, scrambling);
2653 }
2654
2655 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2656 {
2657         u8 ddc_pin;
2658
2659         switch (port) {
2660         case PORT_B:
2661                 ddc_pin = GMBUS_PIN_DPB;
2662                 break;
2663         case PORT_C:
2664                 ddc_pin = GMBUS_PIN_DPC;
2665                 break;
2666         case PORT_D:
2667                 ddc_pin = GMBUS_PIN_DPD_CHV;
2668                 break;
2669         default:
2670                 MISSING_CASE(port);
2671                 ddc_pin = GMBUS_PIN_DPB;
2672                 break;
2673         }
2674         return ddc_pin;
2675 }
2676
2677 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2678 {
2679         u8 ddc_pin;
2680
2681         switch (port) {
2682         case PORT_B:
2683                 ddc_pin = GMBUS_PIN_1_BXT;
2684                 break;
2685         case PORT_C:
2686                 ddc_pin = GMBUS_PIN_2_BXT;
2687                 break;
2688         default:
2689                 MISSING_CASE(port);
2690                 ddc_pin = GMBUS_PIN_1_BXT;
2691                 break;
2692         }
2693         return ddc_pin;
2694 }
2695
2696 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2697                               enum port port)
2698 {
2699         u8 ddc_pin;
2700
2701         switch (port) {
2702         case PORT_B:
2703                 ddc_pin = GMBUS_PIN_1_BXT;
2704                 break;
2705         case PORT_C:
2706                 ddc_pin = GMBUS_PIN_2_BXT;
2707                 break;
2708         case PORT_D:
2709                 ddc_pin = GMBUS_PIN_4_CNP;
2710                 break;
2711         case PORT_F:
2712                 ddc_pin = GMBUS_PIN_3_BXT;
2713                 break;
2714         default:
2715                 MISSING_CASE(port);
2716                 ddc_pin = GMBUS_PIN_1_BXT;
2717                 break;
2718         }
2719         return ddc_pin;
2720 }
2721
2722 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2723 {
2724         enum phy phy = intel_port_to_phy(dev_priv, port);
2725
2726         if (intel_phy_is_combo(dev_priv, phy))
2727                 return GMBUS_PIN_1_BXT + port;
2728         else if (intel_phy_is_tc(dev_priv, phy))
2729                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2730
2731         drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2732         return GMBUS_PIN_2_BXT;
2733 }
2734
2735 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2736 {
2737         enum phy phy = intel_port_to_phy(dev_priv, port);
2738         u8 ddc_pin;
2739
2740         switch (phy) {
2741         case PHY_A:
2742                 ddc_pin = GMBUS_PIN_1_BXT;
2743                 break;
2744         case PHY_B:
2745                 ddc_pin = GMBUS_PIN_2_BXT;
2746                 break;
2747         case PHY_C:
2748                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2749                 break;
2750         default:
2751                 MISSING_CASE(phy);
2752                 ddc_pin = GMBUS_PIN_1_BXT;
2753                 break;
2754         }
2755         return ddc_pin;
2756 }
2757
2758 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2759 {
2760         enum phy phy = intel_port_to_phy(dev_priv, port);
2761
2762         WARN_ON(port == PORT_C);
2763
2764         /*
2765          * Pin mapping for RKL depends on which PCH is present.  With TGP, the
2766          * final two outputs use type-c pins, even though they're actually
2767          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2768          * all outputs.
2769          */
2770         if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2771                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2772
2773         return GMBUS_PIN_1_BXT + phy;
2774 }
2775
2776 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2777 {
2778         enum phy phy = intel_port_to_phy(i915, port);
2779
2780         drm_WARN_ON(&i915->drm, port == PORT_A);
2781
2782         /*
2783          * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
2784          * final two outputs use type-c pins, even though they're actually
2785          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2786          * all outputs.
2787          */
2788         if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2789                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2790
2791         return GMBUS_PIN_1_BXT + phy;
2792 }
2793
2794 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2795 {
2796         return intel_port_to_phy(dev_priv, port) + 1;
2797 }
2798
2799 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2800 {
2801         enum phy phy = intel_port_to_phy(dev_priv, port);
2802
2803         WARN_ON(port == PORT_B || port == PORT_C);
2804
2805         /*
2806          * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2807          * except first combo output.
2808          */
2809         if (phy == PHY_A)
2810                 return GMBUS_PIN_1_BXT;
2811
2812         return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2813 }
2814
2815 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2816                               enum port port)
2817 {
2818         u8 ddc_pin;
2819
2820         switch (port) {
2821         case PORT_B:
2822                 ddc_pin = GMBUS_PIN_DPB;
2823                 break;
2824         case PORT_C:
2825                 ddc_pin = GMBUS_PIN_DPC;
2826                 break;
2827         case PORT_D:
2828                 ddc_pin = GMBUS_PIN_DPD;
2829                 break;
2830         default:
2831                 MISSING_CASE(port);
2832                 ddc_pin = GMBUS_PIN_DPB;
2833                 break;
2834         }
2835         return ddc_pin;
2836 }
2837
2838 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2839 {
2840         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2841         enum port port = encoder->port;
2842         u8 ddc_pin;
2843
2844         ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2845         if (ddc_pin) {
2846                 drm_dbg_kms(&dev_priv->drm,
2847                             "Using DDC pin 0x%x for port %c (VBT)\n",
2848                             ddc_pin, port_name(port));
2849                 return ddc_pin;
2850         }
2851
2852         if (IS_ALDERLAKE_S(dev_priv))
2853                 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2854         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2855                 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2856         else if (IS_ROCKETLAKE(dev_priv))
2857                 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2858         else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2859                 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2860         else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
2861                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2862         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2863                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2864         else if (HAS_PCH_CNP(dev_priv))
2865                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2866         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2867                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2868         else if (IS_CHERRYVIEW(dev_priv))
2869                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2870         else
2871                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2872
2873         drm_dbg_kms(&dev_priv->drm,
2874                     "Using DDC pin 0x%x for port %c (platform default)\n",
2875                     ddc_pin, port_name(port));
2876
2877         return ddc_pin;
2878 }
2879
2880 void intel_infoframe_init(struct intel_digital_port *dig_port)
2881 {
2882         struct drm_i915_private *dev_priv =
2883                 to_i915(dig_port->base.base.dev);
2884
2885         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2886                 dig_port->write_infoframe = vlv_write_infoframe;
2887                 dig_port->read_infoframe = vlv_read_infoframe;
2888                 dig_port->set_infoframes = vlv_set_infoframes;
2889                 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2890         } else if (IS_G4X(dev_priv)) {
2891                 dig_port->write_infoframe = g4x_write_infoframe;
2892                 dig_port->read_infoframe = g4x_read_infoframe;
2893                 dig_port->set_infoframes = g4x_set_infoframes;
2894                 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2895         } else if (HAS_DDI(dev_priv)) {
2896                 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2897                         dig_port->write_infoframe = lspcon_write_infoframe;
2898                         dig_port->read_infoframe = lspcon_read_infoframe;
2899                         dig_port->set_infoframes = lspcon_set_infoframes;
2900                         dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2901                 } else {
2902                         dig_port->write_infoframe = hsw_write_infoframe;
2903                         dig_port->read_infoframe = hsw_read_infoframe;
2904                         dig_port->set_infoframes = hsw_set_infoframes;
2905                         dig_port->infoframes_enabled = hsw_infoframes_enabled;
2906                 }
2907         } else if (HAS_PCH_IBX(dev_priv)) {
2908                 dig_port->write_infoframe = ibx_write_infoframe;
2909                 dig_port->read_infoframe = ibx_read_infoframe;
2910                 dig_port->set_infoframes = ibx_set_infoframes;
2911                 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2912         } else {
2913                 dig_port->write_infoframe = cpt_write_infoframe;
2914                 dig_port->read_infoframe = cpt_read_infoframe;
2915                 dig_port->set_infoframes = cpt_set_infoframes;
2916                 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2917         }
2918 }
2919
2920 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2921                                struct intel_connector *intel_connector)
2922 {
2923         struct drm_connector *connector = &intel_connector->base;
2924         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2925         struct intel_encoder *intel_encoder = &dig_port->base;
2926         struct drm_device *dev = intel_encoder->base.dev;
2927         struct drm_i915_private *dev_priv = to_i915(dev);
2928         struct i2c_adapter *ddc;
2929         enum port port = intel_encoder->port;
2930         struct cec_connector_info conn_info;
2931
2932         drm_dbg_kms(&dev_priv->drm,
2933                     "Adding HDMI connector on [ENCODER:%d:%s]\n",
2934                     intel_encoder->base.base.id, intel_encoder->base.name);
2935
2936         if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2937                 return;
2938
2939         if (drm_WARN(dev, dig_port->max_lanes < 4,
2940                      "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2941                      dig_port->max_lanes, intel_encoder->base.base.id,
2942                      intel_encoder->base.name))
2943                 return;
2944
2945         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2946         ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2947
2948         drm_connector_init_with_ddc(dev, connector,
2949                                     &intel_hdmi_connector_funcs,
2950                                     DRM_MODE_CONNECTOR_HDMIA,
2951                                     ddc);
2952         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2953
2954         connector->interlace_allowed = true;
2955         connector->stereo_allowed = true;
2956
2957         if (DISPLAY_VER(dev_priv) >= 10)
2958                 connector->ycbcr_420_allowed = true;
2959
2960         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2961
2962         if (HAS_DDI(dev_priv))
2963                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2964         else
2965                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2966
2967         intel_hdmi_add_properties(intel_hdmi, connector);
2968
2969         intel_connector_attach_encoder(intel_connector, intel_encoder);
2970         intel_hdmi->attached_connector = intel_connector;
2971
2972         if (is_hdcp_supported(dev_priv, port)) {
2973                 int ret = intel_hdcp_init(intel_connector, dig_port,
2974                                           &intel_hdmi_hdcp_shim);
2975                 if (ret)
2976                         drm_dbg_kms(&dev_priv->drm,
2977                                     "HDCP init failed, skipping.\n");
2978         }
2979
2980         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2981          * 0xd.  Failure to do so will result in spurious interrupts being
2982          * generated on the port when a cable is not attached.
2983          */
2984         if (IS_G45(dev_priv)) {
2985                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2986                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2987                                (temp & ~0xf) | 0xd);
2988         }
2989
2990         cec_fill_conn_info_from_drm(&conn_info, connector);
2991
2992         intel_hdmi->cec_notifier =
2993                 cec_notifier_conn_register(dev->dev, port_identifier(port),
2994                                            &conn_info);
2995         if (!intel_hdmi->cec_notifier)
2996                 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
2997 }
2998
2999 /*
3000  * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3001  * @vactive: Vactive of a display mode
3002  *
3003  * @return: appropriate dsc slice height for a given mode.
3004  */
3005 int intel_hdmi_dsc_get_slice_height(int vactive)
3006 {
3007         int slice_height;
3008
3009         /*
3010          * Slice Height determination : HDMI2.1 Section 7.7.5.2
3011          * Select smallest slice height >=96, that results in a valid PPS and
3012          * requires minimum padding lines required for final slice.
3013          *
3014          * Assumption : Vactive is even.
3015          */
3016         for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3017                 if (vactive % slice_height == 0)
3018                         return slice_height;
3019
3020         return 0;
3021 }
3022
3023 /*
3024  * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3025  * and dsc decoder capabilities
3026  *
3027  * @crtc_state: intel crtc_state
3028  * @src_max_slices: maximum slices supported by the DSC encoder
3029  * @src_max_slice_width: maximum slice width supported by DSC encoder
3030  * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3031  * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3032  *
3033  * @return: num of dsc slices that can be supported by the dsc encoder
3034  * and decoder.
3035  */
3036 int
3037 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3038                               int src_max_slices, int src_max_slice_width,
3039                               int hdmi_max_slices, int hdmi_throughput)
3040 {
3041 /* Pixel rates in KPixels/sec */
3042 #define HDMI_DSC_PEAK_PIXEL_RATE                2720000
3043 /*
3044  * Rates at which the source and sink are required to process pixels in each
3045  * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3046  */
3047 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0           340000
3048 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1           400000
3049
3050 /* Spec limits the slice width to 2720 pixels */
3051 #define MAX_HDMI_SLICE_WIDTH                    2720
3052         int kslice_adjust;
3053         int adjusted_clk_khz;
3054         int min_slices;
3055         int target_slices;
3056         int max_throughput; /* max clock freq. in khz per slice */
3057         int max_slice_width;
3058         int slice_width;
3059         int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3060
3061         if (!hdmi_throughput)
3062                 return 0;
3063
3064         /*
3065          * Slice Width determination : HDMI2.1 Section 7.7.5.1
3066          * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3067          * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3068          * dividing adjusted clock value by 10.
3069          */
3070         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3071             crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3072                 kslice_adjust = 10;
3073         else
3074                 kslice_adjust = 5;
3075
3076         /*
3077          * As per spec, the rate at which the source and the sink process
3078          * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3079          * This depends upon the pixel clock rate and output formats
3080          * (kslice adjust).
3081          * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3082          * at max 340MHz, otherwise they can be processed at max 400MHz.
3083          */
3084
3085         adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3086
3087         if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3088                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3089         else
3090                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3091
3092         /*
3093          * Taking into account the sink's capability for maximum
3094          * clock per slice (in MHz) as read from HF-VSDB.
3095          */
3096         max_throughput = min(max_throughput, hdmi_throughput * 1000);
3097
3098         min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3099         max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3100
3101         /*
3102          * Keep on increasing the num of slices/line, starting from min_slices
3103          * per line till we get such a number, for which the slice_width is
3104          * just less than max_slice_width. The slices/line selected should be
3105          * less than or equal to the max horizontal slices that the combination
3106          * of PCON encoder and HDMI decoder can support.
3107          */
3108         slice_width = max_slice_width;
3109
3110         do {
3111                 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3112                         target_slices = 1;
3113                 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3114                         target_slices = 2;
3115                 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3116                         target_slices = 4;
3117                 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3118                         target_slices = 8;
3119                 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3120                         target_slices = 12;
3121                 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3122                         target_slices = 16;
3123                 else
3124                         return 0;
3125
3126                 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3127                 if (slice_width >= max_slice_width)
3128                         min_slices = target_slices + 1;
3129         } while (slice_width >= max_slice_width);
3130
3131         return target_slices;
3132 }
3133
3134 /*
3135  * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3136  * source and sink capabilities.
3137  *
3138  * @src_fraction_bpp: fractional bpp supported by the source
3139  * @slice_width: dsc slice width supported by the source and sink
3140  * @num_slices: num of slices supported by the source and sink
3141  * @output_format: video output format
3142  * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3143  * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3144  *
3145  * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3146  */
3147 int
3148 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3149                        int output_format, bool hdmi_all_bpp,
3150                        int hdmi_max_chunk_bytes)
3151 {
3152         int max_dsc_bpp, min_dsc_bpp;
3153         int target_bytes;
3154         bool bpp_found = false;
3155         int bpp_decrement_x16;
3156         int bpp_target;
3157         int bpp_target_x16;
3158
3159         /*
3160          * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3161          * Start with the max bpp and keep on decrementing with
3162          * fractional bpp, if supported by PCON DSC encoder
3163          *
3164          * for each bpp we check if no of bytes can be supported by HDMI sink
3165          */
3166
3167         /* Assuming: bpc as 8*/
3168         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3169                 min_dsc_bpp = 6;
3170                 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3171         } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3172                    output_format == INTEL_OUTPUT_FORMAT_RGB) {
3173                 min_dsc_bpp = 8;
3174                 max_dsc_bpp = 3 * 8; /* 3*bpc */
3175         } else {
3176                 /* Assuming 4:2:2 encoding */
3177                 min_dsc_bpp = 7;
3178                 max_dsc_bpp = 2 * 8; /* 2*bpc */
3179         }
3180
3181         /*
3182          * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3183          * Section 7.7.34 : Source shall not enable compressed Video
3184          * Transport with bpp_target settings above 12 bpp unless
3185          * DSC_all_bpp is set to 1.
3186          */
3187         if (!hdmi_all_bpp)
3188                 max_dsc_bpp = min(max_dsc_bpp, 12);
3189
3190         /*
3191          * The Sink has a limit of compressed data in bytes for a scanline,
3192          * as described in max_chunk_bytes field in HFVSDB block of edid.
3193          * The no. of bytes depend on the target bits per pixel that the
3194          * source configures. So we start with the max_bpp and calculate
3195          * the target_chunk_bytes. We keep on decrementing the target_bpp,
3196          * till we get the target_chunk_bytes just less than what the sink's
3197          * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3198          *
3199          * The decrement is according to the fractional support from PCON DSC
3200          * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3201          *
3202          * bpp_target_x16 = bpp_target * 16
3203          * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3204          * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3205          */
3206
3207         bpp_target = max_dsc_bpp;
3208
3209         /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3210         if (!src_fractional_bpp)
3211                 src_fractional_bpp = 1;
3212         bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3213         bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3214
3215         while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3216                 int bpp;
3217
3218                 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3219                 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3220                 if (target_bytes <= hdmi_max_chunk_bytes) {
3221                         bpp_found = true;
3222                         break;
3223                 }
3224                 bpp_target_x16 -= bpp_decrement_x16;
3225         }
3226         if (bpp_found)
3227                 return bpp_target_x16;
3228
3229         return 0;
3230 }