drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "intel_atomic.h"
  45 #include "intel_audio.h"
  46 #include "intel_connector.h"
  47 #include "intel_ddi.h"
  48 #include "intel_display_types.h"
  49 #include "intel_dp.h"
  50 #include "intel_dpio_phy.h"
  51 #include "intel_fifo_underrun.h"
  52 #include "intel_gmbus.h"
  53 #include "intel_hdcp.h"
  54 #include "intel_hdmi.h"
  55 #include "intel_hotplug.h"
  56 #include "intel_lspcon.h"
  57 #include "intel_panel.h"
  58 #include "intel_sdvo.h"
  59 #include "intel_sideband.h"
  60
  61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  62 {
  63         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  64 }
  65
  66 static void
  67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  68 {
  69         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  70         struct drm_i915_private *dev_priv = to_i915(dev);
  71         u32 enabled_bits;
  72
  73         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  74
  75         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  76              "HDMI port enabled, expecting disabled\n");
  77 }
  78
  79 static void
  80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  81                                      enum transcoder cpu_transcoder)
  82 {
  83         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  84              TRANS_DDI_FUNC_ENABLE,
  85              "HDMI transcoder function enabled, expecting disabled\n");
  86 }
  87
  88 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  89 {
  90         struct intel_digital_port *intel_dig_port =
  91                 container_of(encoder, struct intel_digital_port, base.base);
  92         return &intel_dig_port->hdmi;
  93 }
  94
  95 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  96 {
  97         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  98 }
  99
 100 static u32 g4x_infoframe_index(unsigned int type)
 101 {
 102         switch (type) {
 103         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 104                 return VIDEO_DIP_SELECT_GAMUT;
 105         case HDMI_INFOFRAME_TYPE_AVI:
 106                 return VIDEO_DIP_SELECT_AVI;
 107         case HDMI_INFOFRAME_TYPE_SPD:
 108                 return VIDEO_DIP_SELECT_SPD;
 109         case HDMI_INFOFRAME_TYPE_VENDOR:
 110                 return VIDEO_DIP_SELECT_VENDOR;
 111         default:
 112                 MISSING_CASE(type);
 113                 return 0;
 114         }
 115 }
 116
 117 static u32 g4x_infoframe_enable(unsigned int type)
 118 {
 119         switch (type) {
 120         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 121                 return VIDEO_DIP_ENABLE_GCP;
 122         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 123                 return VIDEO_DIP_ENABLE_GAMUT;
 124         case DP_SDP_VSC:
 125                 return 0;
 126         case HDMI_INFOFRAME_TYPE_AVI:
 127                 return VIDEO_DIP_ENABLE_AVI;
 128         case HDMI_INFOFRAME_TYPE_SPD:
 129                 return VIDEO_DIP_ENABLE_SPD;
 130         case HDMI_INFOFRAME_TYPE_VENDOR:
 131                 return VIDEO_DIP_ENABLE_VENDOR;
 132         case HDMI_INFOFRAME_TYPE_DRM:
 133                 return 0;
 134         default:
 135                 MISSING_CASE(type);
 136                 return 0;
 137         }
 138 }
 139
 140 static u32 hsw_infoframe_enable(unsigned int type)
 141 {
 142         switch (type) {
 143         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 144                 return VIDEO_DIP_ENABLE_GCP_HSW;
 145         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 146                 return VIDEO_DIP_ENABLE_GMP_HSW;
 147         case DP_SDP_VSC:
 148                 return VIDEO_DIP_ENABLE_VSC_HSW;
 149         case DP_SDP_PPS:
 150                 return VDIP_ENABLE_PPS;
 151         case HDMI_INFOFRAME_TYPE_AVI:
 152                 return VIDEO_DIP_ENABLE_AVI_HSW;
 153         case HDMI_INFOFRAME_TYPE_SPD:
 154                 return VIDEO_DIP_ENABLE_SPD_HSW;
 155         case HDMI_INFOFRAME_TYPE_VENDOR:
 156                 return VIDEO_DIP_ENABLE_VS_HSW;
 157         case HDMI_INFOFRAME_TYPE_DRM:
 158                 return VIDEO_DIP_ENABLE_DRM_GLK;
 159         default:
 160                 MISSING_CASE(type);
 161                 return 0;
 162         }
 163 }
 164
 165 static i915_reg_t
 166 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 167                  enum transcoder cpu_transcoder,
 168                  unsigned int type,
 169                  int i)
 170 {
 171         switch (type) {
 172         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 173                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 174         case DP_SDP_VSC:
 175                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 176         case DP_SDP_PPS:
 177                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 178         case HDMI_INFOFRAME_TYPE_AVI:
 179                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 180         case HDMI_INFOFRAME_TYPE_SPD:
 181                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 182         case HDMI_INFOFRAME_TYPE_VENDOR:
 183                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 184         case HDMI_INFOFRAME_TYPE_DRM:
 185                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 186         default:
 187                 MISSING_CASE(type);
 188                 return INVALID_MMIO_REG;
 189         }
 190 }
 191
 192 static int hsw_dip_data_size(unsigned int type)
 193 {
 194         switch (type) {
 195         case DP_SDP_VSC:
 196                 return VIDEO_DIP_VSC_DATA_SIZE;
 197         case DP_SDP_PPS:
 198                 return VIDEO_DIP_PPS_DATA_SIZE;
 199         default:
 200                 return VIDEO_DIP_DATA_SIZE;
 201         }
 202 }
 203
 204 static void g4x_write_infoframe(struct intel_encoder *encoder,
 205                                 const struct intel_crtc_state *crtc_state,
 206                                 unsigned int type,
 207                                 const void *frame, ssize_t len)
 208 {
 209         const u32 *data = frame;
 210         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 211         u32 val = I915_READ(VIDEO_DIP_CTL);
 212         int i;
 213
 214         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 215
 216         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 217         val |= g4x_infoframe_index(type);
 218
 219         val &= ~g4x_infoframe_enable(type);
 220
 221         I915_WRITE(VIDEO_DIP_CTL, val);
 222
 223         for (i = 0; i < len; i += 4) {
 224                 I915_WRITE(VIDEO_DIP_DATA, *data);
 225                 data++;
 226         }
 227         /* Write every possible data byte to force correct ECC calculation. */
 228         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 229                 I915_WRITE(VIDEO_DIP_DATA, 0);
 230
 231         val |= g4x_infoframe_enable(type);
 232         val &= ~VIDEO_DIP_FREQ_MASK;
 233         val |= VIDEO_DIP_FREQ_VSYNC;
 234
 235         I915_WRITE(VIDEO_DIP_CTL, val);
 236         POSTING_READ(VIDEO_DIP_CTL);
 237 }
 238
 239 static void g4x_read_infoframe(struct intel_encoder *encoder,
 240                                const struct intel_crtc_state *crtc_state,
 241                                unsigned int type,
 242                                void *frame, ssize_t len)
 243 {
 244         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 245         u32 val, *data = frame;
 246         int i;
 247
 248         val = I915_READ(VIDEO_DIP_CTL);
 249
 250         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 251         val |= g4x_infoframe_index(type);
 252
 253         I915_WRITE(VIDEO_DIP_CTL, val);
 254
 255         for (i = 0; i < len; i += 4)
 256                 *data++ = I915_READ(VIDEO_DIP_DATA);
 257 }
 258
 259 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 260                                   const struct intel_crtc_state *pipe_config)
 261 {
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263         u32 val = I915_READ(VIDEO_DIP_CTL);
 264
 265         if ((val & VIDEO_DIP_ENABLE) == 0)
 266                 return 0;
 267
 268         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 269                 return 0;
 270
 271         return val & (VIDEO_DIP_ENABLE_AVI |
 272                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 273 }
 274
 275 static void ibx_write_infoframe(struct intel_encoder *encoder,
 276                                 const struct intel_crtc_state *crtc_state,
 277                                 unsigned int type,
 278                                 const void *frame, ssize_t len)
 279 {
 280         const u32 *data = frame;
 281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 283         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 284         u32 val = I915_READ(reg);
 285         int i;
 286
 287         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 288
 289         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 290         val |= g4x_infoframe_index(type);
 291
 292         val &= ~g4x_infoframe_enable(type);
 293
 294         I915_WRITE(reg, val);
 295
 296         for (i = 0; i < len; i += 4) {
 297                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 298                 data++;
 299         }
 300         /* Write every possible data byte to force correct ECC calculation. */
 301         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 302                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 303
 304         val |= g4x_infoframe_enable(type);
 305         val &= ~VIDEO_DIP_FREQ_MASK;
 306         val |= VIDEO_DIP_FREQ_VSYNC;
 307
 308         I915_WRITE(reg, val);
 309         POSTING_READ(reg);
 310 }
 311
 312 static void ibx_read_infoframe(struct intel_encoder *encoder,
 313                                const struct intel_crtc_state *crtc_state,
 314                                unsigned int type,
 315                                void *frame, ssize_t len)
 316 {
 317         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 318         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 319         u32 val, *data = frame;
 320         int i;
 321
 322         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 323
 324         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 325         val |= g4x_infoframe_index(type);
 326
 327         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 328
 329         for (i = 0; i < len; i += 4)
 330                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 331 }
 332
 333 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 334                                   const struct intel_crtc_state *pipe_config)
 335 {
 336         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 337         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 338         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 339         u32 val = I915_READ(reg);
 340
 341         if ((val & VIDEO_DIP_ENABLE) == 0)
 342                 return 0;
 343
 344         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 345                 return 0;
 346
 347         return val & (VIDEO_DIP_ENABLE_AVI |
 348                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 349                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 350 }
 351
 352 static void cpt_write_infoframe(struct intel_encoder *encoder,
 353                                 const struct intel_crtc_state *crtc_state,
 354                                 unsigned int type,
 355                                 const void *frame, ssize_t len)
 356 {
 357         const u32 *data = frame;
 358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 359         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 360         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 361         u32 val = I915_READ(reg);
 362         int i;
 363
 364         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 365
 366         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 367         val |= g4x_infoframe_index(type);
 368
 369         /* The DIP control register spec says that we need to update the AVI
 370          * infoframe without clearing its enable bit */
 371         if (type != HDMI_INFOFRAME_TYPE_AVI)
 372                 val &= ~g4x_infoframe_enable(type);
 373
 374         I915_WRITE(reg, val);
 375
 376         for (i = 0; i < len; i += 4) {
 377                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 378                 data++;
 379         }
 380         /* Write every possible data byte to force correct ECC calculation. */
 381         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 382                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 383
 384         val |= g4x_infoframe_enable(type);
 385         val &= ~VIDEO_DIP_FREQ_MASK;
 386         val |= VIDEO_DIP_FREQ_VSYNC;
 387
 388         I915_WRITE(reg, val);
 389         POSTING_READ(reg);
 390 }
 391
 392 static void cpt_read_infoframe(struct intel_encoder *encoder,
 393                                const struct intel_crtc_state *crtc_state,
 394                                unsigned int type,
 395                                void *frame, ssize_t len)
 396 {
 397         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 398         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 399         u32 val, *data = frame;
 400         int i;
 401
 402         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 403
 404         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 405         val |= g4x_infoframe_index(type);
 406
 407         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 408
 409         for (i = 0; i < len; i += 4)
 410                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 411 }
 412
 413 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 414                                   const struct intel_crtc_state *pipe_config)
 415 {
 416         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 417         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 418         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 419
 420         if ((val & VIDEO_DIP_ENABLE) == 0)
 421                 return 0;
 422
 423         return val & (VIDEO_DIP_ENABLE_AVI |
 424                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 425                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 426 }
 427
 428 static void vlv_write_infoframe(struct intel_encoder *encoder,
 429                                 const struct intel_crtc_state *crtc_state,
 430                                 unsigned int type,
 431                                 const void *frame, ssize_t len)
 432 {
 433         const u32 *data = frame;
 434         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 436         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 437         u32 val = I915_READ(reg);
 438         int i;
 439
 440         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 441
 442         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 443         val |= g4x_infoframe_index(type);
 444
 445         val &= ~g4x_infoframe_enable(type);
 446
 447         I915_WRITE(reg, val);
 448
 449         for (i = 0; i < len; i += 4) {
 450                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 451                 data++;
 452         }
 453         /* Write every possible data byte to force correct ECC calculation. */
 454         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 455                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 456
 457         val |= g4x_infoframe_enable(type);
 458         val &= ~VIDEO_DIP_FREQ_MASK;
 459         val |= VIDEO_DIP_FREQ_VSYNC;
 460
 461         I915_WRITE(reg, val);
 462         POSTING_READ(reg);
 463 }
 464
 465 static void vlv_read_infoframe(struct intel_encoder *encoder,
 466                                const struct intel_crtc_state *crtc_state,
 467                                unsigned int type,
 468                                void *frame, ssize_t len)
 469 {
 470         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 471         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 472         u32 val, *data = frame;
 473         int i;
 474
 475         val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
 476
 477         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 478         val |= g4x_infoframe_index(type);
 479
 480         I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 481
 482         for (i = 0; i < len; i += 4)
 483                 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
 484 }
 485
 486 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 487                                   const struct intel_crtc_state *pipe_config)
 488 {
 489         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 490         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 491         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 492
 493         if ((val & VIDEO_DIP_ENABLE) == 0)
 494                 return 0;
 495
 496         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 497                 return 0;
 498
 499         return val & (VIDEO_DIP_ENABLE_AVI |
 500                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 501                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 502 }
 503
 504 static void hsw_write_infoframe(struct intel_encoder *encoder,
 505                                 const struct intel_crtc_state *crtc_state,
 506                                 unsigned int type,
 507                                 const void *frame, ssize_t len)
 508 {
 509         const u32 *data = frame;
 510         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 511         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 512         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 513         int data_size;
 514         int i;
 515         u32 val = I915_READ(ctl_reg);
 516
 517         data_size = hsw_dip_data_size(type);
 518
 519         val &= ~hsw_infoframe_enable(type);
 520         I915_WRITE(ctl_reg, val);
 521
 522         for (i = 0; i < len; i += 4) {
 523                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 524                                             type, i >> 2), *data);
 525                 data++;
 526         }
 527         /* Write every possible data byte to force correct ECC calculation. */
 528         for (; i < data_size; i += 4)
 529                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 530                                             type, i >> 2), 0);
 531
 532         val |= hsw_infoframe_enable(type);
 533         I915_WRITE(ctl_reg, val);
 534         POSTING_READ(ctl_reg);
 535 }
 536
 537 static void hsw_read_infoframe(struct intel_encoder *encoder,
 538                                const struct intel_crtc_state *crtc_state,
 539                                unsigned int type,
 540                                void *frame, ssize_t len)
 541 {
 542         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 543         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 544         u32 val, *data = frame;
 545         int i;
 546
 547         val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
 548
 549         for (i = 0; i < len; i += 4)
 550                 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 551                                                      type, i >> 2));
 552 }
 553
 554 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 555                                   const struct intel_crtc_state *pipe_config)
 556 {
 557         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 558         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 559         u32 mask;
 560
 561         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 562                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 563                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 564
 565         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 566                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 567
 568         return val & mask;
 569 }
 570
 571 static const u8 infoframe_type_to_idx[] = {
 572         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 573         HDMI_PACKET_TYPE_GAMUT_METADATA,
 574         DP_SDP_VSC,
 575         HDMI_INFOFRAME_TYPE_AVI,
 576         HDMI_INFOFRAME_TYPE_SPD,
 577         HDMI_INFOFRAME_TYPE_VENDOR,
 578         HDMI_INFOFRAME_TYPE_DRM,
 579 };
 580
 581 u32 intel_hdmi_infoframe_enable(unsigned int type)
 582 {
 583         int i;
 584
 585         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 586                 if (infoframe_type_to_idx[i] == type)
 587                         return BIT(i);
 588         }
 589
 590         return 0;
 591 }
 592
 593 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 594                                   const struct intel_crtc_state *crtc_state)
 595 {
 596         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 597         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 598         u32 val, ret = 0;
 599         int i;
 600
 601         val = dig_port->infoframes_enabled(encoder, crtc_state);
 602
 603         /* map from hardware bits to dip idx */
 604         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 605                 unsigned int type = infoframe_type_to_idx[i];
 606
 607                 if (HAS_DDI(dev_priv)) {
 608                         if (val & hsw_infoframe_enable(type))
 609                                 ret |= BIT(i);
 610                 } else {
 611                         if (val & g4x_infoframe_enable(type))
 612                                 ret |= BIT(i);
 613                 }
 614         }
 615
 616         return ret;
 617 }
 618
 619 /*
 620  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 621  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 622  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 623  * used for both technologies.
 624  *
 625  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 626  * DW1:       DB3       | DB2 | DB1 | DB0
 627  * DW2:       DB7       | DB6 | DB5 | DB4
 628  * DW3: ...
 629  *
 630  * (HB is Header Byte, DB is Data Byte)
 631  *
 632  * The hdmi pack() functions don't know about that hardware specific hole so we
 633  * trick them by giving an offset into the buffer and moving back the header
 634  * bytes by one.
 635  */
 636 static void intel_write_infoframe(struct intel_encoder *encoder,
 637                                   const struct intel_crtc_state *crtc_state,
 638                                   enum hdmi_infoframe_type type,
 639                                   const union hdmi_infoframe *frame)
 640 {
 641         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 642         u8 buffer[VIDEO_DIP_DATA_SIZE];
 643         ssize_t len;
 644
 645         if ((crtc_state->infoframes.enable &
 646              intel_hdmi_infoframe_enable(type)) == 0)
 647                 return;
 648
 649         if (WARN_ON(frame->any.type != type))
 650                 return;
 651
 652         /* see comment above for the reason for this offset */
 653         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 654         if (WARN_ON(len < 0))
 655                 return;
 656
 657         /* Insert the 'hole' (see big comment above) at position 3 */
 658         memmove(&buffer[0], &buffer[1], 3);
 659         buffer[3] = 0;
 660         len++;
 661
 662         intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 663 }
 664
 665 void intel_read_infoframe(struct intel_encoder *encoder,
 666                           const struct intel_crtc_state *crtc_state,
 667                           enum hdmi_infoframe_type type,
 668                           union hdmi_infoframe *frame)
 669 {
 670         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 671         u8 buffer[VIDEO_DIP_DATA_SIZE];
 672         int ret;
 673
 674         if ((crtc_state->infoframes.enable &
 675              intel_hdmi_infoframe_enable(type)) == 0)
 676                 return;
 677
 678         intel_dig_port->read_infoframe(encoder, crtc_state,
 679                                        type, buffer, sizeof(buffer));
 680
 681         /* Fill the 'hole' (see big comment above) at position 3 */
 682         memmove(&buffer[1], &buffer[0], 3);
 683
 684         /* see comment above for the reason for this offset */
 685         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 686         if (ret) {
 687                 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
 688                 return;
 689         }
 690
 691         if (frame->any.type != type)
 692                 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 693                               frame->any.type, type);
 694 }
 695
 696 static bool
 697 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 698                                  struct intel_crtc_state *crtc_state,
 699                                  struct drm_connector_state *conn_state)
 700 {
 701         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 702         const struct drm_display_mode *adjusted_mode =
 703                 &crtc_state->base.adjusted_mode;
 704         struct drm_connector *connector = conn_state->connector;
 705         int ret;
 706
 707         if (!crtc_state->has_infoframe)
 708                 return true;
 709
 710         crtc_state->infoframes.enable |=
 711                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 712
 713         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 714                                                        adjusted_mode);
 715         if (ret)
 716                 return false;
 717
 718         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 719                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 720         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 721                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 722         else
 723                 frame->colorspace = HDMI_COLORSPACE_RGB;
 724
 725         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 726
 727         /* nonsense combination */
 728         WARN_ON(crtc_state->limited_color_range &&
 729                 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 730
 731         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 732                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 733                                                    adjusted_mode,
 734                                                    crtc_state->limited_color_range ?
 735                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 736                                                    HDMI_QUANTIZATION_RANGE_FULL);
 737         } else {
 738                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 739                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 740         }
 741
 742         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 743
 744         /* TODO: handle pixel repetition for YCBCR420 outputs */
 745
 746         ret = hdmi_avi_infoframe_check(frame);
 747         if (WARN_ON(ret))
 748                 return false;
 749
 750         return true;
 751 }
 752
 753 static bool
 754 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 755                                  struct intel_crtc_state *crtc_state,
 756                                  struct drm_connector_state *conn_state)
 757 {
 758         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 759         int ret;
 760
 761         if (!crtc_state->has_infoframe)
 762                 return true;
 763
 764         crtc_state->infoframes.enable |=
 765                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 766
 767         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 768         if (WARN_ON(ret))
 769                 return false;
 770
 771         frame->sdi = HDMI_SPD_SDI_PC;
 772
 773         ret = hdmi_spd_infoframe_check(frame);
 774         if (WARN_ON(ret))
 775                 return false;
 776
 777         return true;
 778 }
 779
 780 static bool
 781 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 782                                   struct intel_crtc_state *crtc_state,
 783                                   struct drm_connector_state *conn_state)
 784 {
 785         struct hdmi_vendor_infoframe *frame =
 786                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 787         const struct drm_display_info *info =
 788                 &conn_state->connector->display_info;
 789         int ret;
 790
 791         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 792                 return true;
 793
 794         crtc_state->infoframes.enable |=
 795                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 796
 797         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 798                                                           conn_state->connector,
 799                                                           &crtc_state->base.adjusted_mode);
 800         if (WARN_ON(ret))
 801                 return false;
 802
 803         ret = hdmi_vendor_infoframe_check(frame);
 804         if (WARN_ON(ret))
 805                 return false;
 806
 807         return true;
 808 }
 809
 810 static bool
 811 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 812                                  struct intel_crtc_state *crtc_state,
 813                                  struct drm_connector_state *conn_state)
 814 {
 815         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 816         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 817         int ret;
 818
 819         if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
 820                 return true;
 821
 822         if (!crtc_state->has_infoframe)
 823                 return true;
 824
 825         if (!conn_state->hdr_output_metadata)
 826                 return true;
 827
 828         crtc_state->infoframes.enable |=
 829                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 830
 831         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 832         if (ret < 0) {
 833                 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
 834                 return false;
 835         }
 836
 837         ret = hdmi_drm_infoframe_check(frame);
 838         if (WARN_ON(ret))
 839                 return false;
 840
 841         return true;
 842 }
 843
 844 static void g4x_set_infoframes(struct intel_encoder *encoder,
 845                                bool enable,
 846                                const struct intel_crtc_state *crtc_state,
 847                                const struct drm_connector_state *conn_state)
 848 {
 849         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 850         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 851         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 852         i915_reg_t reg = VIDEO_DIP_CTL;
 853         u32 val = I915_READ(reg);
 854         u32 port = VIDEO_DIP_PORT(encoder->port);
 855
 856         assert_hdmi_port_disabled(intel_hdmi);
 857
 858         /* If the registers were not initialized yet, they might be zeroes,
 859          * which means we're selecting the AVI DIP and we're setting its
 860          * frequency to once. This seems to really confuse the HW and make
 861          * things stop working (the register spec says the AVI always needs to
 862          * be sent every VSync). So here we avoid writing to the register more
 863          * than we need and also explicitly select the AVI DIP and explicitly
 864          * set its frequency to every VSync. Avoiding to write it twice seems to
 865          * be enough to solve the problem, but being defensive shouldn't hurt us
 866          * either. */
 867         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 868
 869         if (!enable) {
 870                 if (!(val & VIDEO_DIP_ENABLE))
 871                         return;
 872                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 873                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 874                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 875                         return;
 876                 }
 877                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 878                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 879                 I915_WRITE(reg, val);
 880                 POSTING_READ(reg);
 881                 return;
 882         }
 883
 884         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 885                 if (val & VIDEO_DIP_ENABLE) {
 886                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 887                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 888                         return;
 889                 }
 890                 val &= ~VIDEO_DIP_PORT_MASK;
 891                 val |= port;
 892         }
 893
 894         val |= VIDEO_DIP_ENABLE;
 895         val &= ~(VIDEO_DIP_ENABLE_AVI |
 896                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 897
 898         I915_WRITE(reg, val);
 899         POSTING_READ(reg);
 900
 901         intel_write_infoframe(encoder, crtc_state,
 902                               HDMI_INFOFRAME_TYPE_AVI,
 903                               &crtc_state->infoframes.avi);
 904         intel_write_infoframe(encoder, crtc_state,
 905                               HDMI_INFOFRAME_TYPE_SPD,
 906                               &crtc_state->infoframes.spd);
 907         intel_write_infoframe(encoder, crtc_state,
 908                               HDMI_INFOFRAME_TYPE_VENDOR,
 909                               &crtc_state->infoframes.hdmi);
 910 }
 911
 912 /*
 913  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 914  *
 915  * From HDMI specification 1.4a:
 916  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 917  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 918  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 919  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 920  *   phase of 0
 921  */
 922 static bool gcp_default_phase_possible(int pipe_bpp,
 923                                        const struct drm_display_mode *mode)
 924 {
 925         unsigned int pixels_per_group;
 926
 927         switch (pipe_bpp) {
 928         case 30:
 929                 /* 4 pixels in 5 clocks */
 930                 pixels_per_group = 4;
 931                 break;
 932         case 36:
 933                 /* 2 pixels in 3 clocks */
 934                 pixels_per_group = 2;
 935                 break;
 936         case 48:
 937                 /* 1 pixel in 2 clocks */
 938                 pixels_per_group = 1;
 939                 break;
 940         default:
 941                 /* phase information not relevant for 8bpc */
 942                 return false;
 943         }
 944
 945         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 946                 mode->crtc_htotal % pixels_per_group == 0 &&
 947                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 948                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 949                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 950                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 951                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 952                  mode->crtc_htotal/2 % pixels_per_group == 0);
 953 }
 954
 955 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 956                                          const struct intel_crtc_state *crtc_state,
 957                                          const struct drm_connector_state *conn_state)
 958 {
 959         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 960         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 961         i915_reg_t reg;
 962
 963         if ((crtc_state->infoframes.enable &
 964              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 965                 return false;
 966
 967         if (HAS_DDI(dev_priv))
 968                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 969         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 970                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 971         else if (HAS_PCH_SPLIT(dev_priv))
 972                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 973         else
 974                 return false;
 975
 976         I915_WRITE(reg, crtc_state->infoframes.gcp);
 977
 978         return true;
 979 }
 980
 981 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 982                                    struct intel_crtc_state *crtc_state)
 983 {
 984         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 986         i915_reg_t reg;
 987
 988         if ((crtc_state->infoframes.enable &
 989              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 990                 return;
 991
 992         if (HAS_DDI(dev_priv))
 993                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 994         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 995                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 996         else if (HAS_PCH_SPLIT(dev_priv))
 997                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 998         else
 999                 return;
1000
1001         crtc_state->infoframes.gcp = I915_READ(reg);
1002 }
1003
1004 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1005                                              struct intel_crtc_state *crtc_state,
1006                                              struct drm_connector_state *conn_state)
1007 {
1008         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1009
1010         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1011                 return;
1012
1013         crtc_state->infoframes.enable |=
1014                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1015
1016         /* Indicate color indication for deep color mode */
1017         if (crtc_state->pipe_bpp > 24)
1018                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1019
1020         /* Enable default_phase whenever the display mode is suitably aligned */
1021         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1022                                        &crtc_state->base.adjusted_mode))
1023                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1024 }
1025
1026 static void ibx_set_infoframes(struct intel_encoder *encoder,
1027                                bool enable,
1028                                const struct intel_crtc_state *crtc_state,
1029                                const struct drm_connector_state *conn_state)
1030 {
1031         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1033         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1034         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1035         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1036         u32 val = I915_READ(reg);
1037         u32 port = VIDEO_DIP_PORT(encoder->port);
1038
1039         assert_hdmi_port_disabled(intel_hdmi);
1040
1041         /* See the big comment in g4x_set_infoframes() */
1042         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1043
1044         if (!enable) {
1045                 if (!(val & VIDEO_DIP_ENABLE))
1046                         return;
1047                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1048                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1049                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1050                 I915_WRITE(reg, val);
1051                 POSTING_READ(reg);
1052                 return;
1053         }
1054
1055         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1056                 WARN(val & VIDEO_DIP_ENABLE,
1057                      "DIP already enabled on port %c\n",
1058                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1059                 val &= ~VIDEO_DIP_PORT_MASK;
1060                 val |= port;
1061         }
1062
1063         val |= VIDEO_DIP_ENABLE;
1064         val &= ~(VIDEO_DIP_ENABLE_AVI |
1065                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1066                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1067
1068         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1069                 val |= VIDEO_DIP_ENABLE_GCP;
1070
1071         I915_WRITE(reg, val);
1072         POSTING_READ(reg);
1073
1074         intel_write_infoframe(encoder, crtc_state,
1075                               HDMI_INFOFRAME_TYPE_AVI,
1076                               &crtc_state->infoframes.avi);
1077         intel_write_infoframe(encoder, crtc_state,
1078                               HDMI_INFOFRAME_TYPE_SPD,
1079                               &crtc_state->infoframes.spd);
1080         intel_write_infoframe(encoder, crtc_state,
1081                               HDMI_INFOFRAME_TYPE_VENDOR,
1082                               &crtc_state->infoframes.hdmi);
1083 }
1084
1085 static void cpt_set_infoframes(struct intel_encoder *encoder,
1086                                bool enable,
1087                                const struct intel_crtc_state *crtc_state,
1088                                const struct drm_connector_state *conn_state)
1089 {
1090         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1092         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1093         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1094         u32 val = I915_READ(reg);
1095
1096         assert_hdmi_port_disabled(intel_hdmi);
1097
1098         /* See the big comment in g4x_set_infoframes() */
1099         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1100
1101         if (!enable) {
1102                 if (!(val & VIDEO_DIP_ENABLE))
1103                         return;
1104                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1105                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1106                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1107                 I915_WRITE(reg, val);
1108                 POSTING_READ(reg);
1109                 return;
1110         }
1111
1112         /* Set both together, unset both together: see the spec. */
1113         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1114         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1115                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1116
1117         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1118                 val |= VIDEO_DIP_ENABLE_GCP;
1119
1120         I915_WRITE(reg, val);
1121         POSTING_READ(reg);
1122
1123         intel_write_infoframe(encoder, crtc_state,
1124                               HDMI_INFOFRAME_TYPE_AVI,
1125                               &crtc_state->infoframes.avi);
1126         intel_write_infoframe(encoder, crtc_state,
1127                               HDMI_INFOFRAME_TYPE_SPD,
1128                               &crtc_state->infoframes.spd);
1129         intel_write_infoframe(encoder, crtc_state,
1130                               HDMI_INFOFRAME_TYPE_VENDOR,
1131                               &crtc_state->infoframes.hdmi);
1132 }
1133
1134 static void vlv_set_infoframes(struct intel_encoder *encoder,
1135                                bool enable,
1136                                const struct intel_crtc_state *crtc_state,
1137                                const struct drm_connector_state *conn_state)
1138 {
1139         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1141         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1142         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1143         u32 val = I915_READ(reg);
1144         u32 port = VIDEO_DIP_PORT(encoder->port);
1145
1146         assert_hdmi_port_disabled(intel_hdmi);
1147
1148         /* See the big comment in g4x_set_infoframes() */
1149         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1150
1151         if (!enable) {
1152                 if (!(val & VIDEO_DIP_ENABLE))
1153                         return;
1154                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1155                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1156                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1157                 I915_WRITE(reg, val);
1158                 POSTING_READ(reg);
1159                 return;
1160         }
1161
1162         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1163                 WARN(val & VIDEO_DIP_ENABLE,
1164                      "DIP already enabled on port %c\n",
1165                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1166                 val &= ~VIDEO_DIP_PORT_MASK;
1167                 val |= port;
1168         }
1169
1170         val |= VIDEO_DIP_ENABLE;
1171         val &= ~(VIDEO_DIP_ENABLE_AVI |
1172                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1173                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1174
1175         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1176                 val |= VIDEO_DIP_ENABLE_GCP;
1177
1178         I915_WRITE(reg, val);
1179         POSTING_READ(reg);
1180
1181         intel_write_infoframe(encoder, crtc_state,
1182                               HDMI_INFOFRAME_TYPE_AVI,
1183                               &crtc_state->infoframes.avi);
1184         intel_write_infoframe(encoder, crtc_state,
1185                               HDMI_INFOFRAME_TYPE_SPD,
1186                               &crtc_state->infoframes.spd);
1187         intel_write_infoframe(encoder, crtc_state,
1188                               HDMI_INFOFRAME_TYPE_VENDOR,
1189                               &crtc_state->infoframes.hdmi);
1190 }
1191
1192 static void hsw_set_infoframes(struct intel_encoder *encoder,
1193                                bool enable,
1194                                const struct intel_crtc_state *crtc_state,
1195                                const struct drm_connector_state *conn_state)
1196 {
1197         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1198         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1199         u32 val = I915_READ(reg);
1200
1201         assert_hdmi_transcoder_func_disabled(dev_priv,
1202                                              crtc_state->cpu_transcoder);
1203
1204         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1205                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1206                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1207                  VIDEO_DIP_ENABLE_DRM_GLK);
1208
1209         if (!enable) {
1210                 I915_WRITE(reg, val);
1211                 POSTING_READ(reg);
1212                 return;
1213         }
1214
1215         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1216                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1217
1218         I915_WRITE(reg, val);
1219         POSTING_READ(reg);
1220
1221         intel_write_infoframe(encoder, crtc_state,
1222                               HDMI_INFOFRAME_TYPE_AVI,
1223                               &crtc_state->infoframes.avi);
1224         intel_write_infoframe(encoder, crtc_state,
1225                               HDMI_INFOFRAME_TYPE_SPD,
1226                               &crtc_state->infoframes.spd);
1227         intel_write_infoframe(encoder, crtc_state,
1228                               HDMI_INFOFRAME_TYPE_VENDOR,
1229                               &crtc_state->infoframes.hdmi);
1230         intel_write_infoframe(encoder, crtc_state,
1231                               HDMI_INFOFRAME_TYPE_DRM,
1232                               &crtc_state->infoframes.drm);
1233 }
1234
1235 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1236 {
1237         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1238         struct i2c_adapter *adapter =
1239                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1240
1241         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1242                 return;
1243
1244         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1245                       enable ? "Enabling" : "Disabling");
1246
1247         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1248                                          adapter, enable);
1249 }
1250
1251 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1252                                 unsigned int offset, void *buffer, size_t size)
1253 {
1254         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1255         struct drm_i915_private *dev_priv =
1256                 intel_dig_port->base.base.dev->dev_private;
1257         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1258                                                               hdmi->ddc_bus);
1259         int ret;
1260         u8 start = offset & 0xff;
1261         struct i2c_msg msgs[] = {
1262                 {
1263                         .addr = DRM_HDCP_DDC_ADDR,
1264                         .flags = 0,
1265                         .len = 1,
1266                         .buf = &start,
1267                 },
1268                 {
1269                         .addr = DRM_HDCP_DDC_ADDR,
1270                         .flags = I2C_M_RD,
1271                         .len = size,
1272                         .buf = buffer
1273                 }
1274         };
1275         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1276         if (ret == ARRAY_SIZE(msgs))
1277                 return 0;
1278         return ret >= 0 ? -EIO : ret;
1279 }
1280
1281 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1282                                  unsigned int offset, void *buffer, size_t size)
1283 {
1284         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1285         struct drm_i915_private *dev_priv =
1286                 intel_dig_port->base.base.dev->dev_private;
1287         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1288                                                               hdmi->ddc_bus);
1289         int ret;
1290         u8 *write_buf;
1291         struct i2c_msg msg;
1292
1293         write_buf = kzalloc(size + 1, GFP_KERNEL);
1294         if (!write_buf)
1295                 return -ENOMEM;
1296
1297         write_buf[0] = offset & 0xff;
1298         memcpy(&write_buf[1], buffer, size);
1299
1300         msg.addr = DRM_HDCP_DDC_ADDR;
1301         msg.flags = 0,
1302         msg.len = size + 1,
1303         msg.buf = write_buf;
1304
1305         ret = i2c_transfer(adapter, &msg, 1);
1306         if (ret == 1)
1307                 ret = 0;
1308         else if (ret >= 0)
1309                 ret = -EIO;
1310
1311         kfree(write_buf);
1312         return ret;
1313 }
1314
1315 static
1316 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1317                                   u8 *an)
1318 {
1319         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1320         struct drm_i915_private *dev_priv =
1321                 intel_dig_port->base.base.dev->dev_private;
1322         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1323                                                               hdmi->ddc_bus);
1324         int ret;
1325
1326         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1327                                     DRM_HDCP_AN_LEN);
1328         if (ret) {
1329                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1330                 return ret;
1331         }
1332
1333         ret = intel_gmbus_output_aksv(adapter);
1334         if (ret < 0) {
1335                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1336                 return ret;
1337         }
1338         return 0;
1339 }
1340
1341 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1342                                      u8 *bksv)
1343 {
1344         int ret;
1345         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1346                                    DRM_HDCP_KSV_LEN);
1347         if (ret)
1348                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1349         return ret;
1350 }
1351
1352 static
1353 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1354                                  u8 *bstatus)
1355 {
1356         int ret;
1357         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1358                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1359         if (ret)
1360                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1361         return ret;
1362 }
1363
1364 static
1365 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1366                                      bool *repeater_present)
1367 {
1368         int ret;
1369         u8 val;
1370
1371         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1372         if (ret) {
1373                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1374                 return ret;
1375         }
1376         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1377         return 0;
1378 }
1379
1380 static
1381 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1382                                   u8 *ri_prime)
1383 {
1384         int ret;
1385         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1386                                    ri_prime, DRM_HDCP_RI_LEN);
1387         if (ret)
1388                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1389         return ret;
1390 }
1391
1392 static
1393 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1394                                    bool *ksv_ready)
1395 {
1396         int ret;
1397         u8 val;
1398
1399         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1400         if (ret) {
1401                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1402                 return ret;
1403         }
1404         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1405         return 0;
1406 }
1407
1408 static
1409 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1410                                   int num_downstream, u8 *ksv_fifo)
1411 {
1412         int ret;
1413         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1414                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1415         if (ret) {
1416                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1417                 return ret;
1418         }
1419         return 0;
1420 }
1421
1422 static
1423 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1424                                       int i, u32 *part)
1425 {
1426         int ret;
1427
1428         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1429                 return -EINVAL;
1430
1431         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1432                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1433         if (ret)
1434                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1435         return ret;
1436 }
1437
1438 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1439 {
1440         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1441         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1442         struct drm_crtc *crtc = connector->base.state->crtc;
1443         struct intel_crtc *intel_crtc = container_of(crtc,
1444                                                      struct intel_crtc, base);
1445         u32 scanline;
1446         int ret;
1447
1448         for (;;) {
1449                 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1450                 if (scanline > 100 && scanline < 200)
1451                         break;
1452                 usleep_range(25, 50);
1453         }
1454
1455         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1456         if (ret) {
1457                 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1458                 return ret;
1459         }
1460         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1461         if (ret) {
1462                 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1463                 return ret;
1464         }
1465
1466         return 0;
1467 }
1468
1469 static
1470 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1471                                       bool enable)
1472 {
1473         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1474         struct intel_connector *connector = hdmi->attached_connector;
1475         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1476         int ret;
1477
1478         if (!enable)
1479                 usleep_range(6, 60); /* Bspec says >= 6us */
1480
1481         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1482         if (ret) {
1483                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1484                           enable ? "Enable" : "Disable", ret);
1485                 return ret;
1486         }
1487
1488         /*
1489          * WA: To fix incorrect positioning of the window of
1490          * opportunity and enc_en signalling in KABYLAKE.
1491          */
1492         if (IS_KABYLAKE(dev_priv) && enable)
1493                 return kbl_repositioning_enc_en_signal(connector);
1494
1495         return 0;
1496 }
1497
1498 static
1499 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1500 {
1501         struct drm_i915_private *dev_priv =
1502                 intel_dig_port->base.base.dev->dev_private;
1503         struct intel_connector *connector =
1504                 intel_dig_port->hdmi.attached_connector;
1505         enum port port = intel_dig_port->base.port;
1506         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1507         int ret;
1508         union {
1509                 u32 reg;
1510                 u8 shim[DRM_HDCP_RI_LEN];
1511         } ri;
1512
1513         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1514         if (ret)
1515                 return false;
1516
1517         I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
1518
1519         /* Wait for Ri prime match */
1520         if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
1521                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1522                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1523                           I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
1524                                                 port)));
1525                 return false;
1526         }
1527         return true;
1528 }
1529
1530 struct hdcp2_hdmi_msg_data {
1531         u8 msg_id;
1532         u32 timeout;
1533         u32 timeout2;
1534 };
1535
1536 static const struct hdcp2_hdmi_msg_data hdcp2_msg_data[] = {
1537         { HDCP_2_2_AKE_INIT, 0, 0 },
1538         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
1539         { HDCP_2_2_AKE_NO_STORED_KM, 0, 0 },
1540         { HDCP_2_2_AKE_STORED_KM, 0, 0 },
1541         { HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1542           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
1543         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
1544         { HDCP_2_2_LC_INIT, 0, 0 },
1545         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0 },
1546         { HDCP_2_2_SKE_SEND_EKS, 0, 0 },
1547         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
1548         { HDCP_2_2_REP_SEND_ACK, 0, 0 },
1549         { HDCP_2_2_REP_STREAM_MANAGE, 0, 0 },
1550         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
1551 };
1552
1553 static
1554 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1555                                     u8 *rx_status)
1556 {
1557         return intel_hdmi_hdcp_read(intel_dig_port,
1558                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1559                                     rx_status,
1560                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1561 }
1562
1563 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1564 {
1565         int i;
1566
1567         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1568                 if (hdcp2_msg_data[i].msg_id == msg_id &&
1569                     (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1570                         return hdcp2_msg_data[i].timeout;
1571                 else if (hdcp2_msg_data[i].msg_id == msg_id)
1572                         return hdcp2_msg_data[i].timeout2;
1573
1574         return -EINVAL;
1575 }
1576
1577 static inline
1578 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1579                                   u8 msg_id, bool *msg_ready,
1580                                   ssize_t *msg_sz)
1581 {
1582         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1583         int ret;
1584
1585         ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1586         if (ret < 0) {
1587                 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1588                 return ret;
1589         }
1590
1591         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1592                   rx_status[0]);
1593
1594         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1595                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1596                              *msg_sz);
1597         else
1598                 *msg_ready = *msg_sz;
1599
1600         return 0;
1601 }
1602
1603 static ssize_t
1604 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1605                               u8 msg_id, bool paired)
1606 {
1607         bool msg_ready = false;
1608         int timeout, ret;
1609         ssize_t msg_sz = 0;
1610
1611         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1612         if (timeout < 0)
1613                 return timeout;
1614
1615         ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1616                                                              msg_id, &msg_ready,
1617                                                              &msg_sz),
1618                          !ret && msg_ready && msg_sz, timeout * 1000,
1619                          1000, 5 * 1000);
1620         if (ret)
1621                 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1622                               msg_id, ret, timeout);
1623
1624         return ret ? ret : msg_sz;
1625 }
1626
1627 static
1628 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1629                                void *buf, size_t size)
1630 {
1631         unsigned int offset;
1632
1633         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1634         return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1635 }
1636
1637 static
1638 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1639                               u8 msg_id, void *buf, size_t size)
1640 {
1641         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1642         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1643         unsigned int offset;
1644         ssize_t ret;
1645
1646         ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1647                                             hdcp->is_paired);
1648         if (ret < 0)
1649                 return ret;
1650
1651         /*
1652          * Available msg size should be equal to or lesser than the
1653          * available buffer.
1654          */
1655         if (ret > size) {
1656                 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1657                               ret, size);
1658                 return -1;
1659         }
1660
1661         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1662         ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1663         if (ret)
1664                 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1665
1666         return ret;
1667 }
1668
1669 static
1670 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1671 {
1672         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1673         int ret;
1674
1675         ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1676         if (ret)
1677                 return ret;
1678
1679         /*
1680          * Re-auth request and Link Integrity Failures are represented by
1681          * same bit. i.e reauth_req.
1682          */
1683         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1684                 ret = HDCP_REAUTH_REQUEST;
1685         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1686                 ret = HDCP_TOPOLOGY_CHANGE;
1687
1688         return ret;
1689 }
1690
1691 static
1692 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1693                              bool *capable)
1694 {
1695         u8 hdcp2_version;
1696         int ret;
1697
1698         *capable = false;
1699         ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1700                                    &hdcp2_version, sizeof(hdcp2_version));
1701         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1702                 *capable = true;
1703
1704         return ret;
1705 }
1706
1707 static inline
1708 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1709 {
1710         return HDCP_PROTOCOL_HDMI;
1711 }
1712
1713 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1714         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1715         .read_bksv = intel_hdmi_hdcp_read_bksv,
1716         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1717         .repeater_present = intel_hdmi_hdcp_repeater_present,
1718         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1719         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1720         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1721         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1722         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1723         .check_link = intel_hdmi_hdcp_check_link,
1724         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1725         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1726         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1727         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1728         .protocol = HDCP_PROTOCOL_HDMI,
1729 };
1730
1731 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1732                                const struct intel_crtc_state *crtc_state)
1733 {
1734         struct drm_device *dev = encoder->base.dev;
1735         struct drm_i915_private *dev_priv = to_i915(dev);
1736         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1737         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1738         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1739         u32 hdmi_val;
1740
1741         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1742
1743         hdmi_val = SDVO_ENCODING_HDMI;
1744         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1745                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1746         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1747                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1748         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1749                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1750
1751         if (crtc_state->pipe_bpp > 24)
1752                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1753         else
1754                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1755
1756         if (crtc_state->has_hdmi_sink)
1757                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1758
1759         if (HAS_PCH_CPT(dev_priv))
1760                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1761         else if (IS_CHERRYVIEW(dev_priv))
1762                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1763         else
1764                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1765
1766         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1767         POSTING_READ(intel_hdmi->hdmi_reg);
1768 }
1769
1770 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1771                                     enum pipe *pipe)
1772 {
1773         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1774         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1775         intel_wakeref_t wakeref;
1776         bool ret;
1777
1778         wakeref = intel_display_power_get_if_enabled(dev_priv,
1779                                                      encoder->power_domain);
1780         if (!wakeref)
1781                 return false;
1782
1783         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1784
1785         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1786
1787         return ret;
1788 }
1789
1790 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1791                                   struct intel_crtc_state *pipe_config)
1792 {
1793         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1794         struct drm_device *dev = encoder->base.dev;
1795         struct drm_i915_private *dev_priv = to_i915(dev);
1796         u32 tmp, flags = 0;
1797         int dotclock;
1798
1799         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1800
1801         tmp = I915_READ(intel_hdmi->hdmi_reg);
1802
1803         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1804                 flags |= DRM_MODE_FLAG_PHSYNC;
1805         else
1806                 flags |= DRM_MODE_FLAG_NHSYNC;
1807
1808         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1809                 flags |= DRM_MODE_FLAG_PVSYNC;
1810         else
1811                 flags |= DRM_MODE_FLAG_NVSYNC;
1812
1813         if (tmp & HDMI_MODE_SELECT_HDMI)
1814                 pipe_config->has_hdmi_sink = true;
1815
1816         pipe_config->infoframes.enable |=
1817                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1818
1819         if (pipe_config->infoframes.enable)
1820                 pipe_config->has_infoframe = true;
1821
1822         if (tmp & HDMI_AUDIO_ENABLE)
1823                 pipe_config->has_audio = true;
1824
1825         if (!HAS_PCH_SPLIT(dev_priv) &&
1826             tmp & HDMI_COLOR_RANGE_16_235)
1827                 pipe_config->limited_color_range = true;
1828
1829         pipe_config->base.adjusted_mode.flags |= flags;
1830
1831         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1832                 dotclock = pipe_config->port_clock * 2 / 3;
1833         else
1834                 dotclock = pipe_config->port_clock;
1835
1836         if (pipe_config->pixel_multiplier)
1837                 dotclock /= pipe_config->pixel_multiplier;
1838
1839         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1840
1841         pipe_config->lane_count = 4;
1842
1843         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1844
1845         intel_read_infoframe(encoder, pipe_config,
1846                              HDMI_INFOFRAME_TYPE_AVI,
1847                              &pipe_config->infoframes.avi);
1848         intel_read_infoframe(encoder, pipe_config,
1849                              HDMI_INFOFRAME_TYPE_SPD,
1850                              &pipe_config->infoframes.spd);
1851         intel_read_infoframe(encoder, pipe_config,
1852                              HDMI_INFOFRAME_TYPE_VENDOR,
1853                              &pipe_config->infoframes.hdmi);
1854 }
1855
1856 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1857                                     const struct intel_crtc_state *pipe_config,
1858                                     const struct drm_connector_state *conn_state)
1859 {
1860         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1861
1862         WARN_ON(!pipe_config->has_hdmi_sink);
1863         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1864                          pipe_name(crtc->pipe));
1865         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1866 }
1867
1868 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1869                             const struct intel_crtc_state *pipe_config,
1870                             const struct drm_connector_state *conn_state)
1871 {
1872         struct drm_device *dev = encoder->base.dev;
1873         struct drm_i915_private *dev_priv = to_i915(dev);
1874         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1875         u32 temp;
1876
1877         temp = I915_READ(intel_hdmi->hdmi_reg);
1878
1879         temp |= SDVO_ENABLE;
1880         if (pipe_config->has_audio)
1881                 temp |= HDMI_AUDIO_ENABLE;
1882
1883         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1884         POSTING_READ(intel_hdmi->hdmi_reg);
1885
1886         if (pipe_config->has_audio)
1887                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1888 }
1889
1890 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1891                             const struct intel_crtc_state *pipe_config,
1892                             const struct drm_connector_state *conn_state)
1893 {
1894         struct drm_device *dev = encoder->base.dev;
1895         struct drm_i915_private *dev_priv = to_i915(dev);
1896         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1897         u32 temp;
1898
1899         temp = I915_READ(intel_hdmi->hdmi_reg);
1900
1901         temp |= SDVO_ENABLE;
1902         if (pipe_config->has_audio)
1903                 temp |= HDMI_AUDIO_ENABLE;
1904
1905         /*
1906          * HW workaround, need to write this twice for issue
1907          * that may result in first write getting masked.
1908          */
1909         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1910         POSTING_READ(intel_hdmi->hdmi_reg);
1911         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1912         POSTING_READ(intel_hdmi->hdmi_reg);
1913
1914         /*
1915          * HW workaround, need to toggle enable bit off and on
1916          * for 12bpc with pixel repeat.
1917          *
1918          * FIXME: BSpec says this should be done at the end of
1919          * of the modeset sequence, so not sure if this isn't too soon.
1920          */
1921         if (pipe_config->pipe_bpp > 24 &&
1922             pipe_config->pixel_multiplier > 1) {
1923                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1924                 POSTING_READ(intel_hdmi->hdmi_reg);
1925
1926                 /*
1927                  * HW workaround, need to write this twice for issue
1928                  * that may result in first write getting masked.
1929                  */
1930                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1931                 POSTING_READ(intel_hdmi->hdmi_reg);
1932                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1933                 POSTING_READ(intel_hdmi->hdmi_reg);
1934         }
1935
1936         if (pipe_config->has_audio)
1937                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1938 }
1939
1940 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1941                             const struct intel_crtc_state *pipe_config,
1942                             const struct drm_connector_state *conn_state)
1943 {
1944         struct drm_device *dev = encoder->base.dev;
1945         struct drm_i915_private *dev_priv = to_i915(dev);
1946         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1947         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1948         enum pipe pipe = crtc->pipe;
1949         u32 temp;
1950
1951         temp = I915_READ(intel_hdmi->hdmi_reg);
1952
1953         temp |= SDVO_ENABLE;
1954         if (pipe_config->has_audio)
1955                 temp |= HDMI_AUDIO_ENABLE;
1956
1957         /*
1958          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1959          *
1960          * The procedure for 12bpc is as follows:
1961          * 1. disable HDMI clock gating
1962          * 2. enable HDMI with 8bpc
1963          * 3. enable HDMI with 12bpc
1964          * 4. enable HDMI clock gating
1965          */
1966
1967         if (pipe_config->pipe_bpp > 24) {
1968                 I915_WRITE(TRANS_CHICKEN1(pipe),
1969                            I915_READ(TRANS_CHICKEN1(pipe)) |
1970                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1971
1972                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1973                 temp |= SDVO_COLOR_FORMAT_8bpc;
1974         }
1975
1976         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1977         POSTING_READ(intel_hdmi->hdmi_reg);
1978
1979         if (pipe_config->pipe_bpp > 24) {
1980                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1981                 temp |= HDMI_COLOR_FORMAT_12bpc;
1982
1983                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1984                 POSTING_READ(intel_hdmi->hdmi_reg);
1985
1986                 I915_WRITE(TRANS_CHICKEN1(pipe),
1987                            I915_READ(TRANS_CHICKEN1(pipe)) &
1988                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1989         }
1990
1991         if (pipe_config->has_audio)
1992                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1993 }
1994
1995 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1996                             const struct intel_crtc_state *pipe_config,
1997                             const struct drm_connector_state *conn_state)
1998 {
1999 }
2000
2001 static void intel_disable_hdmi(struct intel_encoder *encoder,
2002                                const struct intel_crtc_state *old_crtc_state,
2003                                const struct drm_connector_state *old_conn_state)
2004 {
2005         struct drm_device *dev = encoder->base.dev;
2006         struct drm_i915_private *dev_priv = to_i915(dev);
2007         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2008         struct intel_digital_port *intel_dig_port =
2009                 hdmi_to_dig_port(intel_hdmi);
2010         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2011         u32 temp;
2012
2013         temp = I915_READ(intel_hdmi->hdmi_reg);
2014
2015         temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2016         I915_WRITE(intel_hdmi->hdmi_reg, temp);
2017         POSTING_READ(intel_hdmi->hdmi_reg);
2018
2019         /*
2020          * HW workaround for IBX, we need to move the port
2021          * to transcoder A after disabling it to allow the
2022          * matching DP port to be enabled on transcoder A.
2023          */
2024         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2025                 /*
2026                  * We get CPU/PCH FIFO underruns on the other pipe when
2027                  * doing the workaround. Sweep them under the rug.
2028                  */
2029                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2030                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2031
2032                 temp &= ~SDVO_PIPE_SEL_MASK;
2033                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2034                 /*
2035                  * HW workaround, need to write this twice for issue
2036                  * that may result in first write getting masked.
2037                  */
2038                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2039                 POSTING_READ(intel_hdmi->hdmi_reg);
2040                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2041                 POSTING_READ(intel_hdmi->hdmi_reg);
2042
2043                 temp &= ~SDVO_ENABLE;
2044                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2045                 POSTING_READ(intel_hdmi->hdmi_reg);
2046
2047                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2048                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2049                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2050         }
2051
2052         intel_dig_port->set_infoframes(encoder,
2053                                        false,
2054                                        old_crtc_state, old_conn_state);
2055
2056         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2057 }
2058
2059 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2060                              const struct intel_crtc_state *old_crtc_state,
2061                              const struct drm_connector_state *old_conn_state)
2062 {
2063         if (old_crtc_state->has_audio)
2064                 intel_audio_codec_disable(encoder,
2065                                           old_crtc_state, old_conn_state);
2066
2067         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2068 }
2069
2070 static void pch_disable_hdmi(struct intel_encoder *encoder,
2071                              const struct intel_crtc_state *old_crtc_state,
2072                              const struct drm_connector_state *old_conn_state)
2073 {
2074         if (old_crtc_state->has_audio)
2075                 intel_audio_codec_disable(encoder,
2076                                           old_crtc_state, old_conn_state);
2077 }
2078
2079 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2080                                   const struct intel_crtc_state *old_crtc_state,
2081                                   const struct drm_connector_state *old_conn_state)
2082 {
2083         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2084 }
2085
2086 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2087 {
2088         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2089         const struct ddi_vbt_port_info *info =
2090                 &dev_priv->vbt.ddi_port_info[encoder->port];
2091         int max_tmds_clock;
2092
2093         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2094                 max_tmds_clock = 594000;
2095         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2096                 max_tmds_clock = 300000;
2097         else if (INTEL_GEN(dev_priv) >= 5)
2098                 max_tmds_clock = 225000;
2099         else
2100                 max_tmds_clock = 165000;
2101
2102         if (info->max_tmds_clock)
2103                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2104
2105         return max_tmds_clock;
2106 }
2107
2108 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2109                                  bool respect_downstream_limits,
2110                                  bool force_dvi)
2111 {
2112         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2113         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2114
2115         if (respect_downstream_limits) {
2116                 struct intel_connector *connector = hdmi->attached_connector;
2117                 const struct drm_display_info *info = &connector->base.display_info;
2118
2119                 if (hdmi->dp_dual_mode.max_tmds_clock)
2120                         max_tmds_clock = min(max_tmds_clock,
2121                                              hdmi->dp_dual_mode.max_tmds_clock);
2122
2123                 if (info->max_tmds_clock)
2124                         max_tmds_clock = min(max_tmds_clock,
2125                                              info->max_tmds_clock);
2126                 else if (!hdmi->has_hdmi_sink || force_dvi)
2127                         max_tmds_clock = min(max_tmds_clock, 165000);
2128         }
2129
2130         return max_tmds_clock;
2131 }
2132
2133 static enum drm_mode_status
2134 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2135                       int clock, bool respect_downstream_limits,
2136                       bool force_dvi)
2137 {
2138         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2139
2140         if (clock < 25000)
2141                 return MODE_CLOCK_LOW;
2142         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2143                 return MODE_CLOCK_HIGH;
2144
2145         /* BXT DPLL can't generate 223-240 MHz */
2146         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2147                 return MODE_CLOCK_RANGE;
2148
2149         /* CHV DPLL can't generate 216-240 MHz */
2150         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2151                 return MODE_CLOCK_RANGE;
2152
2153         return MODE_OK;
2154 }
2155
2156 static enum drm_mode_status
2157 intel_hdmi_mode_valid(struct drm_connector *connector,
2158                       struct drm_display_mode *mode)
2159 {
2160         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2161         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2162         struct drm_i915_private *dev_priv = to_i915(dev);
2163         enum drm_mode_status status;
2164         int clock;
2165         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2166         bool force_dvi =
2167                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2168
2169         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2170                 return MODE_NO_DBLESCAN;
2171
2172         clock = mode->clock;
2173
2174         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2175                 clock *= 2;
2176
2177         if (clock > max_dotclk)
2178                 return MODE_CLOCK_HIGH;
2179
2180         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2181                 clock *= 2;
2182
2183         if (drm_mode_is_420_only(&connector->display_info, mode))
2184                 clock /= 2;
2185
2186         /* check if we can do 8bpc */
2187         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2188
2189         if (hdmi->has_hdmi_sink && !force_dvi) {
2190                 /* if we can't do 8bpc we may still be able to do 12bpc */
2191                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2192                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2193                                                        true, force_dvi);
2194
2195                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2196                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2197                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2198                                                        true, force_dvi);
2199         }
2200         if (status != MODE_OK)
2201                 return status;
2202
2203         return intel_mode_valid_max_plane_size(dev_priv, mode);
2204 }
2205
2206 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2207                                      int bpc)
2208 {
2209         struct drm_i915_private *dev_priv =
2210                 to_i915(crtc_state->base.crtc->dev);
2211         struct drm_atomic_state *state = crtc_state->base.state;
2212         struct drm_connector_state *connector_state;
2213         struct drm_connector *connector;
2214         const struct drm_display_mode *adjusted_mode =
2215                 &crtc_state->base.adjusted_mode;
2216         int i;
2217
2218         if (HAS_GMCH(dev_priv))
2219                 return false;
2220
2221         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2222                 return false;
2223
2224         if (crtc_state->pipe_bpp < bpc * 3)
2225                 return false;
2226
2227         if (!crtc_state->has_hdmi_sink)
2228                 return false;
2229
2230         /*
2231          * HDMI deep color affects the clocks, so it's only possible
2232          * when not cloning with other encoder types.
2233          */
2234         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2235                 return false;
2236
2237         for_each_new_connector_in_state(state, connector, connector_state, i) {
2238                 const struct drm_display_info *info = &connector->display_info;
2239
2240                 if (connector_state->crtc != crtc_state->base.crtc)
2241                         continue;
2242
2243                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2244                         const struct drm_hdmi_info *hdmi = &info->hdmi;
2245
2246                         if (bpc == 12 && !(hdmi->y420_dc_modes &
2247                                            DRM_EDID_YCBCR420_DC_36))
2248                                 return false;
2249                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
2250                                                 DRM_EDID_YCBCR420_DC_30))
2251                                 return false;
2252                 } else {
2253                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2254                                            DRM_EDID_HDMI_DC_36))
2255                                 return false;
2256                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2257                                                 DRM_EDID_HDMI_DC_30))
2258                                 return false;
2259                 }
2260         }
2261
2262         /* Display WA #1139: glk */
2263         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2264             adjusted_mode->htotal > 5460)
2265                 return false;
2266
2267         /* Display Wa_1405510057:icl */
2268         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2269             bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2270             (adjusted_mode->crtc_hblank_end -
2271              adjusted_mode->crtc_hblank_start) % 8 == 2)
2272                 return false;
2273
2274         return true;
2275 }
2276
2277 static bool
2278 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2279                            struct intel_crtc_state *config)
2280 {
2281         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2282
2283         if (!connector->ycbcr_420_allowed) {
2284                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2285                 return false;
2286         }
2287
2288         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2289
2290         /* YCBCR 420 output conversion needs a scaler */
2291         if (skl_update_scaler_crtc(config)) {
2292                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2293                 return false;
2294         }
2295
2296         intel_pch_panel_fitting(intel_crtc, config,
2297                                 DRM_MODE_SCALE_FULLSCREEN);
2298
2299         return true;
2300 }
2301
2302 static int intel_hdmi_port_clock(int clock, int bpc)
2303 {
2304         /*
2305          * Need to adjust the port link by:
2306          *  1.5x for 12bpc
2307          *  1.25x for 10bpc
2308          */
2309         return clock * bpc / 8;
2310 }
2311
2312 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2313                                   struct intel_crtc_state *crtc_state,
2314                                   int clock, bool force_dvi)
2315 {
2316         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2317         int bpc;
2318
2319         for (bpc = 12; bpc >= 10; bpc -= 2) {
2320                 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2321                     hdmi_port_clock_valid(intel_hdmi,
2322                                           intel_hdmi_port_clock(clock, bpc),
2323                                           true, force_dvi) == MODE_OK)
2324                         return bpc;
2325         }
2326
2327         return 8;
2328 }
2329
2330 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2331                                     struct intel_crtc_state *crtc_state,
2332                                     bool force_dvi)
2333 {
2334         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2335         const struct drm_display_mode *adjusted_mode =
2336                 &crtc_state->base.adjusted_mode;
2337         int bpc, clock = adjusted_mode->crtc_clock;
2338
2339         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2340                 clock *= 2;
2341
2342         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2343         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2344                 clock /= 2;
2345
2346         bpc = intel_hdmi_compute_bpc(encoder, crtc_state,
2347                                      clock, force_dvi);
2348
2349         crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2350
2351         /*
2352          * pipe_bpp could already be below 8bpc due to
2353          * FDI bandwidth constraints. We shouldn't bump it
2354          * back up to 8bpc in that case.
2355          */
2356         if (crtc_state->pipe_bpp > bpc * 3)
2357                 crtc_state->pipe_bpp = bpc * 3;
2358
2359         DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
2360                       bpc, crtc_state->pipe_bpp);
2361
2362         if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2363                                   false, force_dvi) != MODE_OK) {
2364                 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
2365                               crtc_state->port_clock);
2366                 return -EINVAL;
2367         }
2368
2369         return 0;
2370 }
2371
2372 static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2373                                            const struct drm_connector_state *conn_state)
2374 {
2375         const struct intel_digital_connector_state *intel_conn_state =
2376                 to_intel_digital_connector_state(conn_state);
2377         const struct drm_display_mode *adjusted_mode =
2378                 &crtc_state->base.adjusted_mode;
2379
2380         /*
2381          * Our YCbCr output is always limited range.
2382          * crtc_state->limited_color_range only applies to RGB,
2383          * and it must never be set for YCbCr or we risk setting
2384          * some conflicting bits in PIPECONF which will mess up
2385          * the colors on the monitor.
2386          */
2387         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2388                 return false;
2389
2390         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2391                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2392                 return crtc_state->has_hdmi_sink &&
2393                         drm_default_rgb_quant_range(adjusted_mode) ==
2394                         HDMI_QUANTIZATION_RANGE_LIMITED;
2395         } else {
2396                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2397         }
2398 }
2399
2400 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2401                               struct intel_crtc_state *pipe_config,
2402                               struct drm_connector_state *conn_state)
2403 {
2404         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2405         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2406         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2407         struct drm_connector *connector = conn_state->connector;
2408         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2409         struct intel_digital_connector_state *intel_conn_state =
2410                 to_intel_digital_connector_state(conn_state);
2411         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2412         int ret;
2413
2414         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2415                 return -EINVAL;
2416
2417         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2418         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2419
2420         if (pipe_config->has_hdmi_sink)
2421                 pipe_config->has_infoframe = true;
2422
2423         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2424                 pipe_config->pixel_multiplier = 2;
2425
2426         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2427                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
2428                         DRM_ERROR("Can't support YCBCR420 output\n");
2429                         return -EINVAL;
2430                 }
2431         }
2432
2433         pipe_config->limited_color_range =
2434                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2435
2436         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2437                 pipe_config->has_pch_encoder = true;
2438
2439         if (pipe_config->has_hdmi_sink) {
2440                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2441                         pipe_config->has_audio = intel_hdmi->has_audio;
2442                 else
2443                         pipe_config->has_audio =
2444                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2445         }
2446
2447         ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi);
2448         if (ret)
2449                 return ret;
2450
2451         /* Set user selected PAR to incoming mode's member */
2452         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2453
2454         pipe_config->lane_count = 4;
2455
2456         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2457                                            IS_GEMINILAKE(dev_priv))) {
2458                 if (scdc->scrambling.low_rates)
2459                         pipe_config->hdmi_scrambling = true;
2460
2461                 if (pipe_config->port_clock > 340000) {
2462                         pipe_config->hdmi_scrambling = true;
2463                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2464                 }
2465         }
2466
2467         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2468
2469         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2470                 DRM_DEBUG_KMS("bad AVI infoframe\n");
2471                 return -EINVAL;
2472         }
2473
2474         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2475                 DRM_DEBUG_KMS("bad SPD infoframe\n");
2476                 return -EINVAL;
2477         }
2478
2479         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2480                 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2481                 return -EINVAL;
2482         }
2483
2484         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2485                 DRM_DEBUG_KMS("bad DRM infoframe\n");
2486                 return -EINVAL;
2487         }
2488
2489         intel_hdcp_transcoder_config(intel_hdmi->attached_connector,
2490                                      pipe_config->cpu_transcoder);
2491
2492         return 0;
2493 }
2494
2495 static void
2496 intel_hdmi_unset_edid(struct drm_connector *connector)
2497 {
2498         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2499
2500         intel_hdmi->has_hdmi_sink = false;
2501         intel_hdmi->has_audio = false;
2502
2503         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2504         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2505
2506         kfree(to_intel_connector(connector)->detect_edid);
2507         to_intel_connector(connector)->detect_edid = NULL;
2508 }
2509
2510 static void
2511 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2512 {
2513         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2514         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2515         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2516         struct i2c_adapter *adapter =
2517                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2518         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2519
2520         /*
2521          * Type 1 DVI adaptors are not required to implement any
2522          * registers, so we can't always detect their presence.
2523          * Ideally we should be able to check the state of the
2524          * CONFIG1 pin, but no such luck on our hardware.
2525          *
2526          * The only method left to us is to check the VBT to see
2527          * if the port is a dual mode capable DP port. But let's
2528          * only do that when we sucesfully read the EDID, to avoid
2529          * confusing log messages about DP dual mode adaptors when
2530          * there's nothing connected to the port.
2531          */
2532         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2533                 /* An overridden EDID imply that we want this port for testing.
2534                  * Make sure not to set limits for that port.
2535                  */
2536                 if (has_edid && !connector->override_edid &&
2537                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2538                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2539                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2540                 } else {
2541                         type = DRM_DP_DUAL_MODE_NONE;
2542                 }
2543         }
2544
2545         if (type == DRM_DP_DUAL_MODE_NONE)
2546                 return;
2547
2548         hdmi->dp_dual_mode.type = type;
2549         hdmi->dp_dual_mode.max_tmds_clock =
2550                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2551
2552         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2553                       drm_dp_get_dual_mode_type_name(type),
2554                       hdmi->dp_dual_mode.max_tmds_clock);
2555 }
2556
2557 static bool
2558 intel_hdmi_set_edid(struct drm_connector *connector)
2559 {
2560         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2561         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2562         intel_wakeref_t wakeref;
2563         struct edid *edid;
2564         bool connected = false;
2565         struct i2c_adapter *i2c;
2566
2567         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2568
2569         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2570
2571         edid = drm_get_edid(connector, i2c);
2572
2573         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2574                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2575                 intel_gmbus_force_bit(i2c, true);
2576                 edid = drm_get_edid(connector, i2c);
2577                 intel_gmbus_force_bit(i2c, false);
2578         }
2579
2580         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2581
2582         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2583
2584         to_intel_connector(connector)->detect_edid = edid;
2585         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2586                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2587                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2588
2589                 connected = true;
2590         }
2591
2592         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2593
2594         return connected;
2595 }
2596
2597 static enum drm_connector_status
2598 intel_hdmi_detect(struct drm_connector *connector, bool force)
2599 {
2600         enum drm_connector_status status = connector_status_disconnected;
2601         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2602         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2603         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2604         intel_wakeref_t wakeref;
2605
2606         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2607                       connector->base.id, connector->name);
2608
2609         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2610
2611         if (INTEL_GEN(dev_priv) >= 11 &&
2612             !intel_digital_port_connected(encoder))
2613                 goto out;
2614
2615         intel_hdmi_unset_edid(connector);
2616
2617         if (intel_hdmi_set_edid(connector))
2618                 status = connector_status_connected;
2619
2620 out:
2621         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2622
2623         if (status != connector_status_connected)
2624                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2625
2626         return status;
2627 }
2628
2629 static void
2630 intel_hdmi_force(struct drm_connector *connector)
2631 {
2632         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2633                       connector->base.id, connector->name);
2634
2635         intel_hdmi_unset_edid(connector);
2636
2637         if (connector->status != connector_status_connected)
2638                 return;
2639
2640         intel_hdmi_set_edid(connector);
2641 }
2642
2643 static int intel_hdmi_get_modes(struct drm_connector *connector)
2644 {
2645         struct edid *edid;
2646
2647         edid = to_intel_connector(connector)->detect_edid;
2648         if (edid == NULL)
2649                 return 0;
2650
2651         return intel_connector_update_modes(connector, edid);
2652 }
2653
2654 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2655                                   const struct intel_crtc_state *pipe_config,
2656                                   const struct drm_connector_state *conn_state)
2657 {
2658         struct intel_digital_port *intel_dig_port =
2659                 enc_to_dig_port(&encoder->base);
2660
2661         intel_hdmi_prepare(encoder, pipe_config);
2662
2663         intel_dig_port->set_infoframes(encoder,
2664                                        pipe_config->has_infoframe,
2665                                        pipe_config, conn_state);
2666 }
2667
2668 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2669                                 const struct intel_crtc_state *pipe_config,
2670                                 const struct drm_connector_state *conn_state)
2671 {
2672         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2673         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2674
2675         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2676
2677         /* HDMI 1.0V-2dB */
2678         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2679                                  0x2b247878);
2680
2681         dport->set_infoframes(encoder,
2682                               pipe_config->has_infoframe,
2683                               pipe_config, conn_state);
2684
2685         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2686
2687         vlv_wait_port_ready(dev_priv, dport, 0x0);
2688 }
2689
2690 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2691                                     const struct intel_crtc_state *pipe_config,
2692                                     const struct drm_connector_state *conn_state)
2693 {
2694         intel_hdmi_prepare(encoder, pipe_config);
2695
2696         vlv_phy_pre_pll_enable(encoder, pipe_config);
2697 }
2698
2699 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2700                                     const struct intel_crtc_state *pipe_config,
2701                                     const struct drm_connector_state *conn_state)
2702 {
2703         intel_hdmi_prepare(encoder, pipe_config);
2704
2705         chv_phy_pre_pll_enable(encoder, pipe_config);
2706 }
2707
2708 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2709                                       const struct intel_crtc_state *old_crtc_state,
2710                                       const struct drm_connector_state *old_conn_state)
2711 {
2712         chv_phy_post_pll_disable(encoder, old_crtc_state);
2713 }
2714
2715 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2716                                   const struct intel_crtc_state *old_crtc_state,
2717                                   const struct drm_connector_state *old_conn_state)
2718 {
2719         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2720         vlv_phy_reset_lanes(encoder, old_crtc_state);
2721 }
2722
2723 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2724                                   const struct intel_crtc_state *old_crtc_state,
2725                                   const struct drm_connector_state *old_conn_state)
2726 {
2727         struct drm_device *dev = encoder->base.dev;
2728         struct drm_i915_private *dev_priv = to_i915(dev);
2729
2730         vlv_dpio_get(dev_priv);
2731
2732         /* Assert data lane reset */
2733         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2734
2735         vlv_dpio_put(dev_priv);
2736 }
2737
2738 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2739                                 const struct intel_crtc_state *pipe_config,
2740                                 const struct drm_connector_state *conn_state)
2741 {
2742         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2743         struct drm_device *dev = encoder->base.dev;
2744         struct drm_i915_private *dev_priv = to_i915(dev);
2745
2746         chv_phy_pre_encoder_enable(encoder, pipe_config);
2747
2748         /* FIXME: Program the support xxx V-dB */
2749         /* Use 800mV-0dB */
2750         chv_set_phy_signal_level(encoder, 128, 102, false);
2751
2752         dport->set_infoframes(encoder,
2753                               pipe_config->has_infoframe,
2754                               pipe_config, conn_state);
2755
2756         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2757
2758         vlv_wait_port_ready(dev_priv, dport, 0x0);
2759
2760         /* Second common lane will stay alive on its own now */
2761         chv_phy_release_cl2_override(encoder);
2762 }
2763
2764 static struct i2c_adapter *
2765 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2766 {
2767         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2768         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2769
2770         return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2771 }
2772
2773 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2774 {
2775         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2776         struct kobject *i2c_kobj = &adapter->dev.kobj;
2777         struct kobject *connector_kobj = &connector->kdev->kobj;
2778         int ret;
2779
2780         ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2781         if (ret)
2782                 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret);
2783 }
2784
2785 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2786 {
2787         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2788         struct kobject *i2c_kobj = &adapter->dev.kobj;
2789         struct kobject *connector_kobj = &connector->kdev->kobj;
2790
2791         sysfs_remove_link(connector_kobj, i2c_kobj->name);
2792 }
2793
2794 static int
2795 intel_hdmi_connector_register(struct drm_connector *connector)
2796 {
2797         int ret;
2798
2799         ret = intel_connector_register(connector);
2800         if (ret)
2801                 return ret;
2802
2803         i915_debugfs_connector_add(connector);
2804
2805         intel_hdmi_create_i2c_symlink(connector);
2806
2807         return ret;
2808 }
2809
2810 static void intel_hdmi_destroy(struct drm_connector *connector)
2811 {
2812         struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier;
2813
2814         cec_notifier_conn_unregister(n);
2815
2816         intel_connector_destroy(connector);
2817 }
2818
2819 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2820 {
2821         intel_hdmi_remove_i2c_symlink(connector);
2822
2823         intel_connector_unregister(connector);
2824 }
2825
2826 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2827         .detect = intel_hdmi_detect,
2828         .force = intel_hdmi_force,
2829         .fill_modes = drm_helper_probe_single_connector_modes,
2830         .atomic_get_property = intel_digital_connector_atomic_get_property,
2831         .atomic_set_property = intel_digital_connector_atomic_set_property,
2832         .late_register = intel_hdmi_connector_register,
2833         .early_unregister = intel_hdmi_connector_unregister,
2834         .destroy = intel_hdmi_destroy,
2835         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2836         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2837 };
2838
2839 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2840         .get_modes = intel_hdmi_get_modes,
2841         .mode_valid = intel_hdmi_mode_valid,
2842         .atomic_check = intel_digital_connector_atomic_check,
2843 };
2844
2845 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2846         .destroy = intel_encoder_destroy,
2847 };
2848
2849 static void
2850 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2851 {
2852         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2853         struct intel_digital_port *intel_dig_port =
2854                                 hdmi_to_dig_port(intel_hdmi);
2855
2856         intel_attach_force_audio_property(connector);
2857         intel_attach_broadcast_rgb_property(connector);
2858         intel_attach_aspect_ratio_property(connector);
2859
2860         /*
2861          * Attach Colorspace property for Non LSPCON based device
2862          * ToDo: This needs to be extended for LSPCON implementation
2863          * as well. Will be implemented separately.
2864          */
2865         if (!intel_dig_port->lspcon.active)
2866                 intel_attach_colorspace_property(connector);
2867
2868         drm_connector_attach_content_type_property(connector);
2869         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2870
2871         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2872                 drm_object_attach_property(&connector->base,
2873                         connector->dev->mode_config.hdr_output_metadata_property, 0);
2874
2875         if (!HAS_GMCH(dev_priv))
2876                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2877 }
2878
2879 /*
2880  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2881  * @encoder: intel_encoder
2882  * @connector: drm_connector
2883  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2884  *  or reset the high tmds clock ratio for scrambling
2885  * @scrambling: bool to Indicate if the function needs to set or reset
2886  *  sink scrambling
2887  *
2888  * This function handles scrambling on HDMI 2.0 capable sinks.
2889  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2890  * it enables scrambling. This should be called before enabling the HDMI
2891  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2892  * detect a scrambled clock within 100 ms.
2893  *
2894  * Returns:
2895  * True on success, false on failure.
2896  */
2897 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2898                                        struct drm_connector *connector,
2899                                        bool high_tmds_clock_ratio,
2900                                        bool scrambling)
2901 {
2902         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2903         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2904         struct drm_scrambling *sink_scrambling =
2905                 &connector->display_info.hdmi.scdc.scrambling;
2906         struct i2c_adapter *adapter =
2907                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2908
2909         if (!sink_scrambling->supported)
2910                 return true;
2911
2912         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2913                       connector->base.id, connector->name,
2914                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2915
2916         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2917         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2918                                                   high_tmds_clock_ratio) &&
2919                 drm_scdc_set_scrambling(adapter, scrambling);
2920 }
2921
2922 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2923 {
2924         u8 ddc_pin;
2925
2926         switch (port) {
2927         case PORT_B:
2928                 ddc_pin = GMBUS_PIN_DPB;
2929                 break;
2930         case PORT_C:
2931                 ddc_pin = GMBUS_PIN_DPC;
2932                 break;
2933         case PORT_D:
2934                 ddc_pin = GMBUS_PIN_DPD_CHV;
2935                 break;
2936         default:
2937                 MISSING_CASE(port);
2938                 ddc_pin = GMBUS_PIN_DPB;
2939                 break;
2940         }
2941         return ddc_pin;
2942 }
2943
2944 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2945 {
2946         u8 ddc_pin;
2947
2948         switch (port) {
2949         case PORT_B:
2950                 ddc_pin = GMBUS_PIN_1_BXT;
2951                 break;
2952         case PORT_C:
2953                 ddc_pin = GMBUS_PIN_2_BXT;
2954                 break;
2955         default:
2956                 MISSING_CASE(port);
2957                 ddc_pin = GMBUS_PIN_1_BXT;
2958                 break;
2959         }
2960         return ddc_pin;
2961 }
2962
2963 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2964                               enum port port)
2965 {
2966         u8 ddc_pin;
2967
2968         switch (port) {
2969         case PORT_B:
2970                 ddc_pin = GMBUS_PIN_1_BXT;
2971                 break;
2972         case PORT_C:
2973                 ddc_pin = GMBUS_PIN_2_BXT;
2974                 break;
2975         case PORT_D:
2976                 ddc_pin = GMBUS_PIN_4_CNP;
2977                 break;
2978         case PORT_F:
2979                 ddc_pin = GMBUS_PIN_3_BXT;
2980                 break;
2981         default:
2982                 MISSING_CASE(port);
2983                 ddc_pin = GMBUS_PIN_1_BXT;
2984                 break;
2985         }
2986         return ddc_pin;
2987 }
2988
2989 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2990 {
2991         enum phy phy = intel_port_to_phy(dev_priv, port);
2992
2993         if (intel_phy_is_combo(dev_priv, phy))
2994                 return GMBUS_PIN_1_BXT + port;
2995         else if (intel_phy_is_tc(dev_priv, phy))
2996                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2997
2998         WARN(1, "Unknown port:%c\n", port_name(port));
2999         return GMBUS_PIN_2_BXT;
3000 }
3001
3002 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3003 {
3004         enum phy phy = intel_port_to_phy(dev_priv, port);
3005         u8 ddc_pin;
3006
3007         switch (phy) {
3008         case PHY_A:
3009                 ddc_pin = GMBUS_PIN_1_BXT;
3010                 break;
3011         case PHY_B:
3012                 ddc_pin = GMBUS_PIN_2_BXT;
3013                 break;
3014         case PHY_C:
3015                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
3016                 break;
3017         default:
3018                 MISSING_CASE(phy);
3019                 ddc_pin = GMBUS_PIN_1_BXT;
3020                 break;
3021         }
3022         return ddc_pin;
3023 }
3024
3025 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3026                               enum port port)
3027 {
3028         u8 ddc_pin;
3029
3030         switch (port) {
3031         case PORT_B:
3032                 ddc_pin = GMBUS_PIN_DPB;
3033                 break;
3034         case PORT_C:
3035                 ddc_pin = GMBUS_PIN_DPC;
3036                 break;
3037         case PORT_D:
3038                 ddc_pin = GMBUS_PIN_DPD;
3039                 break;
3040         default:
3041                 MISSING_CASE(port);
3042                 ddc_pin = GMBUS_PIN_DPB;
3043                 break;
3044         }
3045         return ddc_pin;
3046 }
3047
3048 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
3049                              enum port port)
3050 {
3051         const struct ddi_vbt_port_info *info =
3052                 &dev_priv->vbt.ddi_port_info[port];
3053         u8 ddc_pin;
3054
3055         if (info->alternate_ddc_pin) {
3056                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
3057                               info->alternate_ddc_pin, port_name(port));
3058                 return info->alternate_ddc_pin;
3059         }
3060
3061         if (HAS_PCH_MCC(dev_priv))
3062                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3063         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3064                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3065         else if (HAS_PCH_CNP(dev_priv))
3066                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3067         else if (IS_GEN9_LP(dev_priv))
3068                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3069         else if (IS_CHERRYVIEW(dev_priv))
3070                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3071         else
3072                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3073
3074         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
3075                       ddc_pin, port_name(port));
3076
3077         return ddc_pin;
3078 }
3079
3080 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
3081 {
3082         struct drm_i915_private *dev_priv =
3083                 to_i915(intel_dig_port->base.base.dev);
3084
3085         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3086                 intel_dig_port->write_infoframe = vlv_write_infoframe;
3087                 intel_dig_port->read_infoframe = vlv_read_infoframe;
3088                 intel_dig_port->set_infoframes = vlv_set_infoframes;
3089                 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
3090         } else if (IS_G4X(dev_priv)) {
3091                 intel_dig_port->write_infoframe = g4x_write_infoframe;
3092                 intel_dig_port->read_infoframe = g4x_read_infoframe;
3093                 intel_dig_port->set_infoframes = g4x_set_infoframes;
3094                 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
3095         } else if (HAS_DDI(dev_priv)) {
3096                 if (intel_dig_port->lspcon.active) {
3097                         intel_dig_port->write_infoframe = lspcon_write_infoframe;
3098                         intel_dig_port->read_infoframe = lspcon_read_infoframe;
3099                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
3100                         intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3101                 } else {
3102                         intel_dig_port->write_infoframe = hsw_write_infoframe;
3103                         intel_dig_port->read_infoframe = hsw_read_infoframe;
3104                         intel_dig_port->set_infoframes = hsw_set_infoframes;
3105                         intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
3106                 }
3107         } else if (HAS_PCH_IBX(dev_priv)) {
3108                 intel_dig_port->write_infoframe = ibx_write_infoframe;
3109                 intel_dig_port->read_infoframe = ibx_read_infoframe;
3110                 intel_dig_port->set_infoframes = ibx_set_infoframes;
3111                 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
3112         } else {
3113                 intel_dig_port->write_infoframe = cpt_write_infoframe;
3114                 intel_dig_port->read_infoframe = cpt_read_infoframe;
3115                 intel_dig_port->set_infoframes = cpt_set_infoframes;
3116                 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
3117         }
3118 }
3119
3120 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
3121                                struct intel_connector *intel_connector)
3122 {
3123         struct drm_connector *connector = &intel_connector->base;
3124         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3125         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3126         struct drm_device *dev = intel_encoder->base.dev;
3127         struct drm_i915_private *dev_priv = to_i915(dev);
3128         enum port port = intel_encoder->port;
3129         struct cec_connector_info conn_info;
3130
3131         DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n",
3132                       intel_encoder->base.base.id, intel_encoder->base.name);
3133
3134         if (WARN(intel_dig_port->max_lanes < 4,
3135                  "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3136                  intel_dig_port->max_lanes, intel_encoder->base.base.id,
3137                  intel_encoder->base.name))
3138                 return;
3139
3140         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
3141                            DRM_MODE_CONNECTOR_HDMIA);
3142         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3143
3144         connector->interlace_allowed = 1;
3145         connector->doublescan_allowed = 0;
3146         connector->stereo_allowed = 1;
3147
3148         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3149                 connector->ycbcr_420_allowed = true;
3150
3151         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
3152
3153         if (WARN_ON(port == PORT_A))
3154                 return;
3155         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3156
3157         if (HAS_DDI(dev_priv))
3158                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3159         else
3160                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3161
3162         intel_hdmi_add_properties(intel_hdmi, connector);
3163
3164         intel_connector_attach_encoder(intel_connector, intel_encoder);
3165         intel_hdmi->attached_connector = intel_connector;
3166
3167         if (is_hdcp_supported(dev_priv, port)) {
3168                 int ret = intel_hdcp_init(intel_connector,
3169                                           &intel_hdmi_hdcp_shim);
3170                 if (ret)
3171                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3172         }
3173
3174         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3175          * 0xd.  Failure to do so will result in spurious interrupts being
3176          * generated on the port when a cable is not attached.
3177          */
3178         if (IS_G45(dev_priv)) {
3179                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3180                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3181         }
3182
3183         cec_fill_conn_info_from_drm(&conn_info, connector);
3184
3185         intel_hdmi->cec_notifier =
3186                 cec_notifier_conn_register(dev->dev, port_identifier(port),
3187                                            &conn_info);
3188         if (!intel_hdmi->cec_notifier)
3189                 DRM_DEBUG_KMS("CEC notifier get failed\n");
3190 }
3191
3192 static enum intel_hotplug_state
3193 intel_hdmi_hotplug(struct intel_encoder *encoder,
3194                    struct intel_connector *connector, bool irq_received)
3195 {
3196         enum intel_hotplug_state state;
3197
3198         state = intel_encoder_hotplug(encoder, connector, irq_received);
3199
3200         /*
3201          * On many platforms the HDMI live state signal is known to be
3202          * unreliable, so we can't use it to detect if a sink is connected or
3203          * not. Instead we detect if it's connected based on whether we can
3204          * read the EDID or not. That in turn has a problem during disconnect,
3205          * since the HPD interrupt may be raised before the DDC lines get
3206          * disconnected (due to how the required length of DDC vs. HPD
3207          * connector pins are specified) and so we'll still be able to get a
3208          * valid EDID. To solve this schedule another detection cycle if this
3209          * time around we didn't detect any change in the sink's connection
3210          * status.
3211          */
3212         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
3213                 state = INTEL_HOTPLUG_RETRY;
3214
3215         return state;
3216 }
3217
3218 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3219                      i915_reg_t hdmi_reg, enum port port)
3220 {
3221         struct intel_digital_port *intel_dig_port;
3222         struct intel_encoder *intel_encoder;
3223         struct intel_connector *intel_connector;
3224
3225         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3226         if (!intel_dig_port)
3227                 return;
3228
3229         intel_connector = intel_connector_alloc();
3230         if (!intel_connector) {
3231                 kfree(intel_dig_port);
3232                 return;
3233         }
3234
3235         intel_encoder = &intel_dig_port->base;
3236
3237         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3238                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3239                          "HDMI %c", port_name(port));
3240
3241         intel_encoder->hotplug = intel_hdmi_hotplug;
3242         intel_encoder->compute_config = intel_hdmi_compute_config;
3243         if (HAS_PCH_SPLIT(dev_priv)) {
3244                 intel_encoder->disable = pch_disable_hdmi;
3245                 intel_encoder->post_disable = pch_post_disable_hdmi;
3246         } else {
3247                 intel_encoder->disable = g4x_disable_hdmi;
3248         }
3249         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3250         intel_encoder->get_config = intel_hdmi_get_config;
3251         if (IS_CHERRYVIEW(dev_priv)) {
3252                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3253                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3254                 intel_encoder->enable = vlv_enable_hdmi;
3255                 intel_encoder->post_disable = chv_hdmi_post_disable;
3256                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3257         } else if (IS_VALLEYVIEW(dev_priv)) {
3258                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3259                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3260                 intel_encoder->enable = vlv_enable_hdmi;
3261                 intel_encoder->post_disable = vlv_hdmi_post_disable;
3262         } else {
3263                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3264                 if (HAS_PCH_CPT(dev_priv))
3265                         intel_encoder->enable = cpt_enable_hdmi;
3266                 else if (HAS_PCH_IBX(dev_priv))
3267                         intel_encoder->enable = ibx_enable_hdmi;
3268                 else
3269                         intel_encoder->enable = g4x_enable_hdmi;
3270         }
3271
3272         intel_encoder->type = INTEL_OUTPUT_HDMI;
3273         intel_encoder->power_domain = intel_port_to_power_domain(port);
3274         intel_encoder->port = port;
3275         if (IS_CHERRYVIEW(dev_priv)) {
3276                 if (port == PORT_D)
3277                         intel_encoder->crtc_mask = BIT(PIPE_C);
3278                 else
3279                         intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B);
3280         } else {
3281                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
3282         }
3283         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3284         /*
3285          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3286          * to work on real hardware. And since g4x can send infoframes to
3287          * only one port anyway, nothing is lost by allowing it.
3288          */
3289         if (IS_G4X(dev_priv))
3290                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3291
3292         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3293         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3294         intel_dig_port->max_lanes = 4;
3295
3296         intel_infoframe_init(intel_dig_port);
3297
3298         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3299         intel_hdmi_init_connector(intel_dig_port, intel_connector);
3300 }