1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include "intel_atomic.h"
9 #include "intel_display_types.h"
10 #include "intel_fdi.h"
11 #include "intel_sideband.h"
14 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
16 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
17 return crtc_state->fdi_lanes;
22 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
23 struct intel_crtc_state *pipe_config)
25 struct drm_i915_private *dev_priv = to_i915(dev);
26 struct drm_atomic_state *state = pipe_config->uapi.state;
27 struct intel_crtc *other_crtc;
28 struct intel_crtc_state *other_crtc_state;
30 drm_dbg_kms(&dev_priv->drm,
31 "checking fdi config on pipe %c, lanes %i\n",
32 pipe_name(pipe), pipe_config->fdi_lanes);
33 if (pipe_config->fdi_lanes > 4) {
34 drm_dbg_kms(&dev_priv->drm,
35 "invalid fdi lane config on pipe %c: %i lanes\n",
36 pipe_name(pipe), pipe_config->fdi_lanes);
40 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
41 if (pipe_config->fdi_lanes > 2) {
42 drm_dbg_kms(&dev_priv->drm,
43 "only 2 lanes on haswell, required: %i lanes\n",
44 pipe_config->fdi_lanes);
51 if (INTEL_NUM_PIPES(dev_priv) == 2)
54 /* Ivybridge 3 pipe is really complicated */
59 if (pipe_config->fdi_lanes <= 2)
62 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
64 intel_atomic_get_crtc_state(state, other_crtc);
65 if (IS_ERR(other_crtc_state))
66 return PTR_ERR(other_crtc_state);
68 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
69 drm_dbg_kms(&dev_priv->drm,
70 "invalid shared fdi lane config on pipe %c: %i lanes\n",
71 pipe_name(pipe), pipe_config->fdi_lanes);
76 if (pipe_config->fdi_lanes > 2) {
77 drm_dbg_kms(&dev_priv->drm,
78 "only 2 lanes on pipe %c: required %i lanes\n",
79 pipe_name(pipe), pipe_config->fdi_lanes);
83 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
85 intel_atomic_get_crtc_state(state, other_crtc);
86 if (IS_ERR(other_crtc_state))
87 return PTR_ERR(other_crtc_state);
89 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
90 drm_dbg_kms(&dev_priv->drm,
91 "fdi link B uses too many lanes to enable link C\n");
101 void intel_fdi_pll_freq_update(struct drm_i915_private *i915)
103 if (IS_IRONLAKE(i915)) {
105 intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
107 i915->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
108 } else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) {
109 i915->fdi_pll_freq = 270000;
114 drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq);
117 int intel_fdi_link_freq(struct drm_i915_private *i915,
118 const struct intel_crtc_state *pipe_config)
121 return pipe_config->port_clock; /* SPLL */
123 return i915->fdi_pll_freq;
126 int ilk_fdi_compute_config(struct intel_crtc *crtc,
127 struct intel_crtc_state *pipe_config)
129 struct drm_device *dev = crtc->base.dev;
130 struct drm_i915_private *i915 = to_i915(dev);
131 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
132 int lane, link_bw, fdi_dotclock, ret;
133 bool needs_recompute = false;
136 /* FDI is a binary signal running at ~2.7GHz, encoding
137 * each output octet as 10 bits. The actual frequency
138 * is stored as a divider into a 100MHz clock, and the
139 * mode pixel clock is stored in units of 1KHz.
140 * Hence the bw of each lane in terms of the mode signal
143 link_bw = intel_fdi_link_freq(i915, pipe_config);
145 fdi_dotclock = adjusted_mode->crtc_clock;
147 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
148 pipe_config->pipe_bpp);
150 pipe_config->fdi_lanes = lane;
152 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
153 link_bw, &pipe_config->fdi_m_n, false, false);
155 ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
159 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
160 pipe_config->pipe_bpp -= 2*3;
161 drm_dbg_kms(&i915->drm,
162 "fdi link bw constraint, reducing pipe bpp to %i\n",
163 pipe_config->pipe_bpp);
164 needs_recompute = true;
165 pipe_config->bw_constrained = true;
171 return I915_DISPLAY_CONFIG_RETRY;
176 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
180 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
181 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
184 drm_WARN_ON(&dev_priv->drm,
185 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
187 drm_WARN_ON(&dev_priv->drm,
188 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
191 temp &= ~FDI_BC_BIFURCATION_SELECT;
193 temp |= FDI_BC_BIFURCATION_SELECT;
195 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
196 enable ? "en" : "dis");
197 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
198 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
201 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
203 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
204 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
206 switch (crtc->pipe) {
210 if (crtc_state->fdi_lanes > 2)
211 cpt_set_fdi_bc_bifurcation(dev_priv, false);
213 cpt_set_fdi_bc_bifurcation(dev_priv, true);
217 cpt_set_fdi_bc_bifurcation(dev_priv, true);
221 MISSING_CASE(crtc->pipe);
225 void intel_fdi_normal_train(struct intel_crtc *crtc)
227 struct drm_device *dev = crtc->base.dev;
228 struct drm_i915_private *dev_priv = to_i915(dev);
229 enum pipe pipe = crtc->pipe;
233 /* enable normal train */
234 reg = FDI_TX_CTL(pipe);
235 temp = intel_de_read(dev_priv, reg);
236 if (IS_IVYBRIDGE(dev_priv)) {
237 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
238 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
240 temp &= ~FDI_LINK_TRAIN_NONE;
241 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
243 intel_de_write(dev_priv, reg, temp);
245 reg = FDI_RX_CTL(pipe);
246 temp = intel_de_read(dev_priv, reg);
247 if (HAS_PCH_CPT(dev_priv)) {
248 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
249 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
251 temp &= ~FDI_LINK_TRAIN_NONE;
252 temp |= FDI_LINK_TRAIN_NONE;
254 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
256 /* wait one idle pattern time */
257 intel_de_posting_read(dev_priv, reg);
260 /* IVB wants error correction enabled */
261 if (IS_IVYBRIDGE(dev_priv))
262 intel_de_write(dev_priv, reg,
263 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
266 /* The FDI link training functions for ILK/Ibexpeak. */
267 static void ilk_fdi_link_train(struct intel_crtc *crtc,
268 const struct intel_crtc_state *crtc_state)
270 struct drm_device *dev = crtc->base.dev;
271 struct drm_i915_private *dev_priv = to_i915(dev);
272 enum pipe pipe = crtc->pipe;
277 * Write the TU size bits before fdi link training, so that error
280 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
281 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
283 /* FDI needs bits from pipe first */
284 assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);
286 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
288 reg = FDI_RX_IMR(pipe);
289 temp = intel_de_read(dev_priv, reg);
290 temp &= ~FDI_RX_SYMBOL_LOCK;
291 temp &= ~FDI_RX_BIT_LOCK;
292 intel_de_write(dev_priv, reg, temp);
293 intel_de_read(dev_priv, reg);
296 /* enable CPU FDI TX and PCH FDI RX */
297 reg = FDI_TX_CTL(pipe);
298 temp = intel_de_read(dev_priv, reg);
299 temp &= ~FDI_DP_PORT_WIDTH_MASK;
300 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
301 temp &= ~FDI_LINK_TRAIN_NONE;
302 temp |= FDI_LINK_TRAIN_PATTERN_1;
303 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
305 reg = FDI_RX_CTL(pipe);
306 temp = intel_de_read(dev_priv, reg);
307 temp &= ~FDI_LINK_TRAIN_NONE;
308 temp |= FDI_LINK_TRAIN_PATTERN_1;
309 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
311 intel_de_posting_read(dev_priv, reg);
314 /* Ironlake workaround, enable clock pointer after FDI enable*/
315 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
316 FDI_RX_PHASE_SYNC_POINTER_OVR);
317 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
318 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
320 reg = FDI_RX_IIR(pipe);
321 for (tries = 0; tries < 5; tries++) {
322 temp = intel_de_read(dev_priv, reg);
323 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
325 if ((temp & FDI_RX_BIT_LOCK)) {
326 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
327 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
332 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
335 reg = FDI_TX_CTL(pipe);
336 temp = intel_de_read(dev_priv, reg);
337 temp &= ~FDI_LINK_TRAIN_NONE;
338 temp |= FDI_LINK_TRAIN_PATTERN_2;
339 intel_de_write(dev_priv, reg, temp);
341 reg = FDI_RX_CTL(pipe);
342 temp = intel_de_read(dev_priv, reg);
343 temp &= ~FDI_LINK_TRAIN_NONE;
344 temp |= FDI_LINK_TRAIN_PATTERN_2;
345 intel_de_write(dev_priv, reg, temp);
347 intel_de_posting_read(dev_priv, reg);
350 reg = FDI_RX_IIR(pipe);
351 for (tries = 0; tries < 5; tries++) {
352 temp = intel_de_read(dev_priv, reg);
353 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
355 if (temp & FDI_RX_SYMBOL_LOCK) {
356 intel_de_write(dev_priv, reg,
357 temp | FDI_RX_SYMBOL_LOCK);
358 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
363 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
365 drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
369 static const int snb_b_fdi_train_param[] = {
370 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
371 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
372 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
373 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
376 /* The FDI link training functions for SNB/Cougarpoint. */
377 static void gen6_fdi_link_train(struct intel_crtc *crtc,
378 const struct intel_crtc_state *crtc_state)
380 struct drm_device *dev = crtc->base.dev;
381 struct drm_i915_private *dev_priv = to_i915(dev);
382 enum pipe pipe = crtc->pipe;
387 * Write the TU size bits before fdi link training, so that error
390 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
391 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
393 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
395 reg = FDI_RX_IMR(pipe);
396 temp = intel_de_read(dev_priv, reg);
397 temp &= ~FDI_RX_SYMBOL_LOCK;
398 temp &= ~FDI_RX_BIT_LOCK;
399 intel_de_write(dev_priv, reg, temp);
401 intel_de_posting_read(dev_priv, reg);
404 /* enable CPU FDI TX and PCH FDI RX */
405 reg = FDI_TX_CTL(pipe);
406 temp = intel_de_read(dev_priv, reg);
407 temp &= ~FDI_DP_PORT_WIDTH_MASK;
408 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
409 temp &= ~FDI_LINK_TRAIN_NONE;
410 temp |= FDI_LINK_TRAIN_PATTERN_1;
411 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
413 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
414 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
416 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
417 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
419 reg = FDI_RX_CTL(pipe);
420 temp = intel_de_read(dev_priv, reg);
421 if (HAS_PCH_CPT(dev_priv)) {
422 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
423 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
425 temp &= ~FDI_LINK_TRAIN_NONE;
426 temp |= FDI_LINK_TRAIN_PATTERN_1;
428 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
430 intel_de_posting_read(dev_priv, reg);
433 for (i = 0; i < 4; i++) {
434 reg = FDI_TX_CTL(pipe);
435 temp = intel_de_read(dev_priv, reg);
436 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
437 temp |= snb_b_fdi_train_param[i];
438 intel_de_write(dev_priv, reg, temp);
440 intel_de_posting_read(dev_priv, reg);
443 for (retry = 0; retry < 5; retry++) {
444 reg = FDI_RX_IIR(pipe);
445 temp = intel_de_read(dev_priv, reg);
446 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
447 if (temp & FDI_RX_BIT_LOCK) {
448 intel_de_write(dev_priv, reg,
449 temp | FDI_RX_BIT_LOCK);
450 drm_dbg_kms(&dev_priv->drm,
451 "FDI train 1 done.\n");
460 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
463 reg = FDI_TX_CTL(pipe);
464 temp = intel_de_read(dev_priv, reg);
465 temp &= ~FDI_LINK_TRAIN_NONE;
466 temp |= FDI_LINK_TRAIN_PATTERN_2;
467 if (IS_SANDYBRIDGE(dev_priv)) {
468 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
470 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
472 intel_de_write(dev_priv, reg, temp);
474 reg = FDI_RX_CTL(pipe);
475 temp = intel_de_read(dev_priv, reg);
476 if (HAS_PCH_CPT(dev_priv)) {
477 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
478 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
480 temp &= ~FDI_LINK_TRAIN_NONE;
481 temp |= FDI_LINK_TRAIN_PATTERN_2;
483 intel_de_write(dev_priv, reg, temp);
485 intel_de_posting_read(dev_priv, reg);
488 for (i = 0; i < 4; i++) {
489 reg = FDI_TX_CTL(pipe);
490 temp = intel_de_read(dev_priv, reg);
491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
492 temp |= snb_b_fdi_train_param[i];
493 intel_de_write(dev_priv, reg, temp);
495 intel_de_posting_read(dev_priv, reg);
498 for (retry = 0; retry < 5; retry++) {
499 reg = FDI_RX_IIR(pipe);
500 temp = intel_de_read(dev_priv, reg);
501 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
502 if (temp & FDI_RX_SYMBOL_LOCK) {
503 intel_de_write(dev_priv, reg,
504 temp | FDI_RX_SYMBOL_LOCK);
505 drm_dbg_kms(&dev_priv->drm,
506 "FDI train 2 done.\n");
515 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
517 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
520 /* Manual link training for Ivy Bridge A0 parts */
521 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
522 const struct intel_crtc_state *crtc_state)
524 struct drm_device *dev = crtc->base.dev;
525 struct drm_i915_private *dev_priv = to_i915(dev);
526 enum pipe pipe = crtc->pipe;
530 ivb_update_fdi_bc_bifurcation(crtc_state);
533 * Write the TU size bits before fdi link training, so that error
536 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
537 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
539 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
541 reg = FDI_RX_IMR(pipe);
542 temp = intel_de_read(dev_priv, reg);
543 temp &= ~FDI_RX_SYMBOL_LOCK;
544 temp &= ~FDI_RX_BIT_LOCK;
545 intel_de_write(dev_priv, reg, temp);
547 intel_de_posting_read(dev_priv, reg);
550 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
551 intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
553 /* Try each vswing and preemphasis setting twice before moving on */
554 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
555 /* disable first in case we need to retry */
556 reg = FDI_TX_CTL(pipe);
557 temp = intel_de_read(dev_priv, reg);
558 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
559 temp &= ~FDI_TX_ENABLE;
560 intel_de_write(dev_priv, reg, temp);
562 reg = FDI_RX_CTL(pipe);
563 temp = intel_de_read(dev_priv, reg);
564 temp &= ~FDI_LINK_TRAIN_AUTO;
565 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
566 temp &= ~FDI_RX_ENABLE;
567 intel_de_write(dev_priv, reg, temp);
569 /* enable CPU FDI TX and PCH FDI RX */
570 reg = FDI_TX_CTL(pipe);
571 temp = intel_de_read(dev_priv, reg);
572 temp &= ~FDI_DP_PORT_WIDTH_MASK;
573 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
574 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
576 temp |= snb_b_fdi_train_param[j/2];
577 temp |= FDI_COMPOSITE_SYNC;
578 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
580 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
581 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
583 reg = FDI_RX_CTL(pipe);
584 temp = intel_de_read(dev_priv, reg);
585 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
586 temp |= FDI_COMPOSITE_SYNC;
587 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
589 intel_de_posting_read(dev_priv, reg);
590 udelay(1); /* should be 0.5us */
592 for (i = 0; i < 4; i++) {
593 reg = FDI_RX_IIR(pipe);
594 temp = intel_de_read(dev_priv, reg);
595 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
597 if (temp & FDI_RX_BIT_LOCK ||
598 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
599 intel_de_write(dev_priv, reg,
600 temp | FDI_RX_BIT_LOCK);
601 drm_dbg_kms(&dev_priv->drm,
602 "FDI train 1 done, level %i.\n",
606 udelay(1); /* should be 0.5us */
609 drm_dbg_kms(&dev_priv->drm,
610 "FDI train 1 fail on vswing %d\n", j / 2);
615 reg = FDI_TX_CTL(pipe);
616 temp = intel_de_read(dev_priv, reg);
617 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
618 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
619 intel_de_write(dev_priv, reg, temp);
621 reg = FDI_RX_CTL(pipe);
622 temp = intel_de_read(dev_priv, reg);
623 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
624 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
625 intel_de_write(dev_priv, reg, temp);
627 intel_de_posting_read(dev_priv, reg);
628 udelay(2); /* should be 1.5us */
630 for (i = 0; i < 4; i++) {
631 reg = FDI_RX_IIR(pipe);
632 temp = intel_de_read(dev_priv, reg);
633 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
635 if (temp & FDI_RX_SYMBOL_LOCK ||
636 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
637 intel_de_write(dev_priv, reg,
638 temp | FDI_RX_SYMBOL_LOCK);
639 drm_dbg_kms(&dev_priv->drm,
640 "FDI train 2 done, level %i.\n",
644 udelay(2); /* should be 1.5us */
647 drm_dbg_kms(&dev_priv->drm,
648 "FDI train 2 fail on vswing %d\n", j / 2);
652 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
655 /* Starting with Haswell, different DDI ports can work in FDI mode for
656 * connection to the PCH-located connectors. For this, it is necessary to train
657 * both the DDI port and PCH receiver for the desired DDI buffer settings.
659 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
660 * please note that when FDI mode is active on DDI E, it shares 2 lines with
661 * DDI A (which is used for eDP)
663 void hsw_fdi_link_train(struct intel_encoder *encoder,
664 const struct intel_crtc_state *crtc_state)
666 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
667 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
668 u32 temp, i, rx_ctl_val;
671 encoder->get_buf_trans(encoder, crtc_state, &n_entries);
673 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
675 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
676 * mode set "sequence for CRT port" document:
677 * - TP1 to TP2 time with the default value
680 * WaFDIAutoLinkSetTimingOverrride:hsw
682 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
683 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
685 /* Enable the PCH Receiver FDI PLL */
686 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
688 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
689 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
690 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
693 /* Switch from Rawclk to PCDclk */
694 rx_ctl_val |= FDI_PCDCLK;
695 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
697 /* Configure Port Clock Select */
698 drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
699 intel_ddi_enable_clock(encoder, crtc_state);
701 /* Start the training iterating through available voltages and emphasis,
702 * testing each value twice. */
703 for (i = 0; i < n_entries * 2; i++) {
704 /* Configure DP_TP_CTL with auto-training */
705 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
706 DP_TP_CTL_FDI_AUTOTRAIN |
707 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
708 DP_TP_CTL_LINK_TRAIN_PAT1 |
711 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
712 * DDI E does not support port reversal, the functionality is
713 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
714 * port reversal bit */
715 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
716 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
717 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
721 /* Program PCH FDI Receiver TU */
722 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
724 /* Enable PCH FDI Receiver with auto-training */
725 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
726 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
727 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
729 /* Wait for FDI receiver lane calibration */
732 /* Unset FDI_RX_MISC pwrdn lanes */
733 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
734 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
735 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
736 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
738 /* Wait for FDI auto training time */
741 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
742 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
743 drm_dbg_kms(&dev_priv->drm,
744 "FDI link training done on step %d\n", i);
749 * Leave things enabled even if we failed to train FDI.
750 * Results in less fireworks from the state checker.
752 if (i == n_entries * 2 - 1) {
753 drm_err(&dev_priv->drm, "FDI link training failed!\n");
757 rx_ctl_val &= ~FDI_RX_ENABLE;
758 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
759 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
761 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
762 temp &= ~DDI_BUF_CTL_ENABLE;
763 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
764 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
766 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
767 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
768 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
769 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
770 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
771 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
773 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
775 /* Reset FDI_RX_MISC pwrdn lanes */
776 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
777 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
778 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
779 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
780 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
783 /* Enable normal pixel sending for FDI */
784 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
785 DP_TP_CTL_FDI_AUTOTRAIN |
786 DP_TP_CTL_LINK_TRAIN_NORMAL |
787 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
791 void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
793 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
794 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
795 enum pipe pipe = crtc->pipe;
799 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
800 reg = FDI_RX_CTL(pipe);
801 temp = intel_de_read(dev_priv, reg);
802 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
803 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
804 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
805 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
807 intel_de_posting_read(dev_priv, reg);
810 /* Switch from Rawclk to PCDclk */
811 temp = intel_de_read(dev_priv, reg);
812 intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
814 intel_de_posting_read(dev_priv, reg);
817 /* Enable CPU FDI TX PLL, always on for Ironlake */
818 reg = FDI_TX_CTL(pipe);
819 temp = intel_de_read(dev_priv, reg);
820 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
821 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
823 intel_de_posting_read(dev_priv, reg);
828 void ilk_fdi_pll_disable(struct intel_crtc *crtc)
830 struct drm_device *dev = crtc->base.dev;
831 struct drm_i915_private *dev_priv = to_i915(dev);
832 enum pipe pipe = crtc->pipe;
836 /* Switch from PCDclk to Rawclk */
837 reg = FDI_RX_CTL(pipe);
838 temp = intel_de_read(dev_priv, reg);
839 intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
841 /* Disable CPU FDI TX PLL */
842 reg = FDI_TX_CTL(pipe);
843 temp = intel_de_read(dev_priv, reg);
844 intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
846 intel_de_posting_read(dev_priv, reg);
849 reg = FDI_RX_CTL(pipe);
850 temp = intel_de_read(dev_priv, reg);
851 intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
853 /* Wait for the clocks to turn off. */
854 intel_de_posting_read(dev_priv, reg);
858 void ilk_fdi_disable(struct intel_crtc *crtc)
860 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
861 enum pipe pipe = crtc->pipe;
865 /* disable CPU FDI tx and PCH FDI rx */
866 reg = FDI_TX_CTL(pipe);
867 temp = intel_de_read(dev_priv, reg);
868 intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
869 intel_de_posting_read(dev_priv, reg);
871 reg = FDI_RX_CTL(pipe);
872 temp = intel_de_read(dev_priv, reg);
873 temp &= ~(0x7 << 16);
874 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
875 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
877 intel_de_posting_read(dev_priv, reg);
880 /* Ironlake workaround, disable clock pointer after downing FDI */
881 if (HAS_PCH_IBX(dev_priv))
882 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
883 FDI_RX_PHASE_SYNC_POINTER_OVR);
885 /* still set train pattern 1 */
886 reg = FDI_TX_CTL(pipe);
887 temp = intel_de_read(dev_priv, reg);
888 temp &= ~FDI_LINK_TRAIN_NONE;
889 temp |= FDI_LINK_TRAIN_PATTERN_1;
890 intel_de_write(dev_priv, reg, temp);
892 reg = FDI_RX_CTL(pipe);
893 temp = intel_de_read(dev_priv, reg);
894 if (HAS_PCH_CPT(dev_priv)) {
895 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
896 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
898 temp &= ~FDI_LINK_TRAIN_NONE;
899 temp |= FDI_LINK_TRAIN_PATTERN_1;
901 /* BPC in FDI rx is consistent with that in PIPECONF */
902 temp &= ~(0x07 << 16);
903 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
904 intel_de_write(dev_priv, reg, temp);
906 intel_de_posting_read(dev_priv, reg);
910 static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
914 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
915 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
916 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
918 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
919 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
920 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
922 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
923 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
924 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
926 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
927 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
928 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
931 /* WaMPhyProgramming:hsw */
932 void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
936 lpt_fdi_reset_mphy(dev_priv);
938 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
939 tmp &= ~(0xFF << 24);
941 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
943 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
945 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
947 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
949 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
951 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
952 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
953 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
955 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
956 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
957 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
959 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
962 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
964 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
967 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
969 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
972 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
974 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
977 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
979 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
980 tmp &= ~(0xFF << 16);
982 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
984 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
985 tmp &= ~(0xFF << 16);
987 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
989 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
991 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
993 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
995 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
997 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
1000 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
1002 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
1003 tmp &= ~(0xF << 28);
1005 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
1009 intel_fdi_init_hook(struct drm_i915_private *dev_priv)
1011 if (IS_IRONLAKE(dev_priv)) {
1012 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
1013 } else if (IS_SANDYBRIDGE(dev_priv)) {
1014 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
1015 } else if (IS_IVYBRIDGE(dev_priv)) {
1016 /* FIXME: detect B0+ stepping and use auto training */
1017 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;