drivers/gpu/drm/i915/display/intel_dpll.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5 #include <linux/kernel.h>
   6 #include "intel_display_types.h"
   7 #include "intel_display.h"
   8 #include "intel_dpll.h"
   9 #include "intel_lvds.h"
  10 #include "intel_panel.h"
  11
  12 struct intel_limit {
  13         struct {
  14                 int min, max;
  15         } dot, vco, n, m, m1, m2, p, p1;
  16
  17         struct {
  18                 int dot_limit;
  19                 int p2_slow, p2_fast;
  20         } p2;
  21 };
  22 static const struct intel_limit intel_limits_i8xx_dac = {
  23         .dot = { .min = 25000, .max = 350000 },
  24         .vco = { .min = 908000, .max = 1512000 },
  25         .n = { .min = 2, .max = 16 },
  26         .m = { .min = 96, .max = 140 },
  27         .m1 = { .min = 18, .max = 26 },
  28         .m2 = { .min = 6, .max = 16 },
  29         .p = { .min = 4, .max = 128 },
  30         .p1 = { .min = 2, .max = 33 },
  31         .p2 = { .dot_limit = 165000,
  32                 .p2_slow = 4, .p2_fast = 2 },
  33 };
  34
  35 static const struct intel_limit intel_limits_i8xx_dvo = {
  36         .dot = { .min = 25000, .max = 350000 },
  37         .vco = { .min = 908000, .max = 1512000 },
  38         .n = { .min = 2, .max = 16 },
  39         .m = { .min = 96, .max = 140 },
  40         .m1 = { .min = 18, .max = 26 },
  41         .m2 = { .min = 6, .max = 16 },
  42         .p = { .min = 4, .max = 128 },
  43         .p1 = { .min = 2, .max = 33 },
  44         .p2 = { .dot_limit = 165000,
  45                 .p2_slow = 4, .p2_fast = 4 },
  46 };
  47
  48 static const struct intel_limit intel_limits_i8xx_lvds = {
  49         .dot = { .min = 25000, .max = 350000 },
  50         .vco = { .min = 908000, .max = 1512000 },
  51         .n = { .min = 2, .max = 16 },
  52         .m = { .min = 96, .max = 140 },
  53         .m1 = { .min = 18, .max = 26 },
  54         .m2 = { .min = 6, .max = 16 },
  55         .p = { .min = 4, .max = 128 },
  56         .p1 = { .min = 1, .max = 6 },
  57         .p2 = { .dot_limit = 165000,
  58                 .p2_slow = 14, .p2_fast = 7 },
  59 };
  60
  61 static const struct intel_limit intel_limits_i9xx_sdvo = {
  62         .dot = { .min = 20000, .max = 400000 },
  63         .vco = { .min = 1400000, .max = 2800000 },
  64         .n = { .min = 1, .max = 6 },
  65         .m = { .min = 70, .max = 120 },
  66         .m1 = { .min = 8, .max = 18 },
  67         .m2 = { .min = 3, .max = 7 },
  68         .p = { .min = 5, .max = 80 },
  69         .p1 = { .min = 1, .max = 8 },
  70         .p2 = { .dot_limit = 200000,
  71                 .p2_slow = 10, .p2_fast = 5 },
  72 };
  73
  74 static const struct intel_limit intel_limits_i9xx_lvds = {
  75         .dot = { .min = 20000, .max = 400000 },
  76         .vco = { .min = 1400000, .max = 2800000 },
  77         .n = { .min = 1, .max = 6 },
  78         .m = { .min = 70, .max = 120 },
  79         .m1 = { .min = 8, .max = 18 },
  80         .m2 = { .min = 3, .max = 7 },
  81         .p = { .min = 7, .max = 98 },
  82         .p1 = { .min = 1, .max = 8 },
  83         .p2 = { .dot_limit = 112000,
  84                 .p2_slow = 14, .p2_fast = 7 },
  85 };
  86
  87
  88 static const struct intel_limit intel_limits_g4x_sdvo = {
  89         .dot = { .min = 25000, .max = 270000 },
  90         .vco = { .min = 1750000, .max = 3500000},
  91         .n = { .min = 1, .max = 4 },
  92         .m = { .min = 104, .max = 138 },
  93         .m1 = { .min = 17, .max = 23 },
  94         .m2 = { .min = 5, .max = 11 },
  95         .p = { .min = 10, .max = 30 },
  96         .p1 = { .min = 1, .max = 3},
  97         .p2 = { .dot_limit = 270000,
  98                 .p2_slow = 10,
  99                 .p2_fast = 10
 100         },
 101 };
 102
 103 static const struct intel_limit intel_limits_g4x_hdmi = {
 104         .dot = { .min = 22000, .max = 400000 },
 105         .vco = { .min = 1750000, .max = 3500000},
 106         .n = { .min = 1, .max = 4 },
 107         .m = { .min = 104, .max = 138 },
 108         .m1 = { .min = 16, .max = 23 },
 109         .m2 = { .min = 5, .max = 11 },
 110         .p = { .min = 5, .max = 80 },
 111         .p1 = { .min = 1, .max = 8},
 112         .p2 = { .dot_limit = 165000,
 113                 .p2_slow = 10, .p2_fast = 5 },
 114 };
 115
 116 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 117         .dot = { .min = 20000, .max = 115000 },
 118         .vco = { .min = 1750000, .max = 3500000 },
 119         .n = { .min = 1, .max = 3 },
 120         .m = { .min = 104, .max = 138 },
 121         .m1 = { .min = 17, .max = 23 },
 122         .m2 = { .min = 5, .max = 11 },
 123         .p = { .min = 28, .max = 112 },
 124         .p1 = { .min = 2, .max = 8 },
 125         .p2 = { .dot_limit = 0,
 126                 .p2_slow = 14, .p2_fast = 14
 127         },
 128 };
 129
 130 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 131         .dot = { .min = 80000, .max = 224000 },
 132         .vco = { .min = 1750000, .max = 3500000 },
 133         .n = { .min = 1, .max = 3 },
 134         .m = { .min = 104, .max = 138 },
 135         .m1 = { .min = 17, .max = 23 },
 136         .m2 = { .min = 5, .max = 11 },
 137         .p = { .min = 14, .max = 42 },
 138         .p1 = { .min = 2, .max = 6 },
 139         .p2 = { .dot_limit = 0,
 140                 .p2_slow = 7, .p2_fast = 7
 141         },
 142 };
 143
 144 static const struct intel_limit pnv_limits_sdvo = {
 145         .dot = { .min = 20000, .max = 400000},
 146         .vco = { .min = 1700000, .max = 3500000 },
 147         /* Pineview's Ncounter is a ring counter */
 148         .n = { .min = 3, .max = 6 },
 149         .m = { .min = 2, .max = 256 },
 150         /* Pineview only has one combined m divider, which we treat as m2. */
 151         .m1 = { .min = 0, .max = 0 },
 152         .m2 = { .min = 0, .max = 254 },
 153         .p = { .min = 5, .max = 80 },
 154         .p1 = { .min = 1, .max = 8 },
 155         .p2 = { .dot_limit = 200000,
 156                 .p2_slow = 10, .p2_fast = 5 },
 157 };
 158
 159 static const struct intel_limit pnv_limits_lvds = {
 160         .dot = { .min = 20000, .max = 400000 },
 161         .vco = { .min = 1700000, .max = 3500000 },
 162         .n = { .min = 3, .max = 6 },
 163         .m = { .min = 2, .max = 256 },
 164         .m1 = { .min = 0, .max = 0 },
 165         .m2 = { .min = 0, .max = 254 },
 166         .p = { .min = 7, .max = 112 },
 167         .p1 = { .min = 1, .max = 8 },
 168         .p2 = { .dot_limit = 112000,
 169                 .p2_slow = 14, .p2_fast = 14 },
 170 };
 171
 172 /* Ironlake / Sandybridge
 173  *
 174  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 175  * the range value for them is (actual_value - 2).
 176  */
 177 static const struct intel_limit ilk_limits_dac = {
 178         .dot = { .min = 25000, .max = 350000 },
 179         .vco = { .min = 1760000, .max = 3510000 },
 180         .n = { .min = 1, .max = 5 },
 181         .m = { .min = 79, .max = 127 },
 182         .m1 = { .min = 12, .max = 22 },
 183         .m2 = { .min = 5, .max = 9 },
 184         .p = { .min = 5, .max = 80 },
 185         .p1 = { .min = 1, .max = 8 },
 186         .p2 = { .dot_limit = 225000,
 187                 .p2_slow = 10, .p2_fast = 5 },
 188 };
 189
 190 static const struct intel_limit ilk_limits_single_lvds = {
 191         .dot = { .min = 25000, .max = 350000 },
 192         .vco = { .min = 1760000, .max = 3510000 },
 193         .n = { .min = 1, .max = 3 },
 194         .m = { .min = 79, .max = 118 },
 195         .m1 = { .min = 12, .max = 22 },
 196         .m2 = { .min = 5, .max = 9 },
 197         .p = { .min = 28, .max = 112 },
 198         .p1 = { .min = 2, .max = 8 },
 199         .p2 = { .dot_limit = 225000,
 200                 .p2_slow = 14, .p2_fast = 14 },
 201 };
 202
 203 static const struct intel_limit ilk_limits_dual_lvds = {
 204         .dot = { .min = 25000, .max = 350000 },
 205         .vco = { .min = 1760000, .max = 3510000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 79, .max = 127 },
 208         .m1 = { .min = 12, .max = 22 },
 209         .m2 = { .min = 5, .max = 9 },
 210         .p = { .min = 14, .max = 56 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 225000,
 213                 .p2_slow = 7, .p2_fast = 7 },
 214 };
 215
 216 /* LVDS 100mhz refclk limits. */
 217 static const struct intel_limit ilk_limits_single_lvds_100m = {
 218         .dot = { .min = 25000, .max = 350000 },
 219         .vco = { .min = 1760000, .max = 3510000 },
 220         .n = { .min = 1, .max = 2 },
 221         .m = { .min = 79, .max = 126 },
 222         .m1 = { .min = 12, .max = 22 },
 223         .m2 = { .min = 5, .max = 9 },
 224         .p = { .min = 28, .max = 112 },
 225         .p1 = { .min = 2, .max = 8 },
 226         .p2 = { .dot_limit = 225000,
 227                 .p2_slow = 14, .p2_fast = 14 },
 228 };
 229
 230 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 231         .dot = { .min = 25000, .max = 350000 },
 232         .vco = { .min = 1760000, .max = 3510000 },
 233         .n = { .min = 1, .max = 3 },
 234         .m = { .min = 79, .max = 126 },
 235         .m1 = { .min = 12, .max = 22 },
 236         .m2 = { .min = 5, .max = 9 },
 237         .p = { .min = 14, .max = 42 },
 238         .p1 = { .min = 2, .max = 6 },
 239         .p2 = { .dot_limit = 225000,
 240                 .p2_slow = 7, .p2_fast = 7 },
 241 };
 242
 243 static const struct intel_limit intel_limits_vlv = {
 244          /*
 245           * These are the data rate limits (measured in fast clocks)
 246           * since those are the strictest limits we have. The fast
 247           * clock and actual rate limits are more relaxed, so checking
 248           * them would make no difference.
 249           */
 250         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 251         .vco = { .min = 4000000, .max = 6000000 },
 252         .n = { .min = 1, .max = 7 },
 253         .m1 = { .min = 2, .max = 3 },
 254         .m2 = { .min = 11, .max = 156 },
 255         .p1 = { .min = 2, .max = 3 },
 256         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 257 };
 258
 259 static const struct intel_limit intel_limits_chv = {
 260         /*
 261          * These are the data rate limits (measured in fast clocks)
 262          * since those are the strictest limits we have.  The fast
 263          * clock and actual rate limits are more relaxed, so checking
 264          * them would make no difference.
 265          */
 266         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 267         .vco = { .min = 4800000, .max = 6480000 },
 268         .n = { .min = 1, .max = 1 },
 269         .m1 = { .min = 2, .max = 2 },
 270         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 271         .p1 = { .min = 2, .max = 4 },
 272         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 273 };
 274
 275 static const struct intel_limit intel_limits_bxt = {
 276         /* FIXME: find real dot limits */
 277         .dot = { .min = 0, .max = INT_MAX },
 278         .vco = { .min = 4800000, .max = 6700000 },
 279         .n = { .min = 1, .max = 1 },
 280         .m1 = { .min = 2, .max = 2 },
 281         /* FIXME: find real m2 limits */
 282         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 283         .p1 = { .min = 2, .max = 4 },
 284         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 285 };
 286
 287 /*
 288  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 289  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 290  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 291  * The helpers' return value is the rate of the clock that is fed to the
 292  * display engine's pipe which can be the above fast dot clock rate or a
 293  * divided-down version of it.
 294  */
 295 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 296 int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 297 {
 298         clock->m = clock->m2 + 2;
 299         clock->p = clock->p1 * clock->p2;
 300         if (WARN_ON(clock->n == 0 || clock->p == 0))
 301                 return 0;
 302         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 303         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 304
 305         return clock->dot;
 306 }
 307
 308 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 309 {
 310         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 311 }
 312
 313 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 314 {
 315         clock->m = i9xx_dpll_compute_m(clock);
 316         clock->p = clock->p1 * clock->p2;
 317         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 318                 return 0;
 319         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 320         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 321
 322         return clock->dot;
 323 }
 324
 325 int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 326 {
 327         clock->m = clock->m1 * clock->m2;
 328         clock->p = clock->p1 * clock->p2;
 329         if (WARN_ON(clock->n == 0 || clock->p == 0))
 330                 return 0;
 331         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 332         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 333
 334         return clock->dot / 5;
 335 }
 336
 337 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 338 {
 339         clock->m = clock->m1 * clock->m2;
 340         clock->p = clock->p1 * clock->p2;
 341         if (WARN_ON(clock->n == 0 || clock->p == 0))
 342                 return 0;
 343         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 344                                            clock->n << 22);
 345         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 346
 347         return clock->dot / 5;
 348 }
 349
 350 /*
 351  * Returns whether the given set of divisors are valid for a given refclk with
 352  * the given connectors.
 353  */
 354 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 355                                const struct intel_limit *limit,
 356                                const struct dpll *clock)
 357 {
 358         if (clock->n < limit->n.min || limit->n.max < clock->n)
 359                 return false;
 360         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 361                 return false;
 362         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 363                 return false;
 364         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 365                 return false;
 366
 367         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 368             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 369                 if (clock->m1 <= clock->m2)
 370                         return false;
 371
 372         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 373             !IS_GEN9_LP(dev_priv)) {
 374                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 375                         return false;
 376                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 377                         return false;
 378         }
 379
 380         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 381                 return false;
 382         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 383          * connector, etc., rather than just a single range.
 384          */
 385         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 386                 return false;
 387
 388         return true;
 389 }
 390
 391 static int
 392 i9xx_select_p2_div(const struct intel_limit *limit,
 393                    const struct intel_crtc_state *crtc_state,
 394                    int target)
 395 {
 396         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 397
 398         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 399                 /*
 400                  * For LVDS just rely on its current settings for dual-channel.
 401                  * We haven't figured out how to reliably set up different
 402                  * single/dual channel state, if we even can.
 403                  */
 404                 if (intel_is_dual_link_lvds(dev_priv))
 405                         return limit->p2.p2_fast;
 406                 else
 407                         return limit->p2.p2_slow;
 408         } else {
 409                 if (target < limit->p2.dot_limit)
 410                         return limit->p2.p2_slow;
 411                 else
 412                         return limit->p2.p2_fast;
 413         }
 414 }
 415
 416 /*
 417  * Returns a set of divisors for the desired target clock with the given
 418  * refclk, or FALSE.  The returned values represent the clock equation:
 419  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 420  *
 421  * Target and reference clocks are specified in kHz.
 422  *
 423  * If match_clock is provided, then best_clock P divider must match the P
 424  * divider from @match_clock used for LVDS downclocking.
 425  */
 426 static bool
 427 i9xx_find_best_dpll(const struct intel_limit *limit,
 428                     struct intel_crtc_state *crtc_state,
 429                     int target, int refclk, struct dpll *match_clock,
 430                     struct dpll *best_clock)
 431 {
 432         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 433         struct dpll clock;
 434         int err = target;
 435
 436         memset(best_clock, 0, sizeof(*best_clock));
 437
 438         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 439
 440         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 441              clock.m1++) {
 442                 for (clock.m2 = limit->m2.min;
 443                      clock.m2 <= limit->m2.max; clock.m2++) {
 444                         if (clock.m2 >= clock.m1)
 445                                 break;
 446                         for (clock.n = limit->n.min;
 447                              clock.n <= limit->n.max; clock.n++) {
 448                                 for (clock.p1 = limit->p1.min;
 449                                         clock.p1 <= limit->p1.max; clock.p1++) {
 450                                         int this_err;
 451
 452                                         i9xx_calc_dpll_params(refclk, &clock);
 453                                         if (!intel_pll_is_valid(to_i915(dev),
 454                                                                 limit,
 455                                                                 &clock))
 456                                                 continue;
 457                                         if (match_clock &&
 458                                             clock.p != match_clock->p)
 459                                                 continue;
 460
 461                                         this_err = abs(clock.dot - target);
 462                                         if (this_err < err) {
 463                                                 *best_clock = clock;
 464                                                 err = this_err;
 465                                         }
 466                                 }
 467                         }
 468                 }
 469         }
 470
 471         return (err != target);
 472 }
 473
 474 /*
 475  * Returns a set of divisors for the desired target clock with the given
 476  * refclk, or FALSE.  The returned values represent the clock equation:
 477  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 478  *
 479  * Target and reference clocks are specified in kHz.
 480  *
 481  * If match_clock is provided, then best_clock P divider must match the P
 482  * divider from @match_clock used for LVDS downclocking.
 483  */
 484 static bool
 485 pnv_find_best_dpll(const struct intel_limit *limit,
 486                    struct intel_crtc_state *crtc_state,
 487                    int target, int refclk, struct dpll *match_clock,
 488                    struct dpll *best_clock)
 489 {
 490         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 491         struct dpll clock;
 492         int err = target;
 493
 494         memset(best_clock, 0, sizeof(*best_clock));
 495
 496         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 497
 498         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 499              clock.m1++) {
 500                 for (clock.m2 = limit->m2.min;
 501                      clock.m2 <= limit->m2.max; clock.m2++) {
 502                         for (clock.n = limit->n.min;
 503                              clock.n <= limit->n.max; clock.n++) {
 504                                 for (clock.p1 = limit->p1.min;
 505                                         clock.p1 <= limit->p1.max; clock.p1++) {
 506                                         int this_err;
 507
 508                                         pnv_calc_dpll_params(refclk, &clock);
 509                                         if (!intel_pll_is_valid(to_i915(dev),
 510                                                                 limit,
 511                                                                 &clock))
 512                                                 continue;
 513                                         if (match_clock &&
 514                                             clock.p != match_clock->p)
 515                                                 continue;
 516
 517                                         this_err = abs(clock.dot - target);
 518                                         if (this_err < err) {
 519                                                 *best_clock = clock;
 520                                                 err = this_err;
 521                                         }
 522                                 }
 523                         }
 524                 }
 525         }
 526
 527         return (err != target);
 528 }
 529
 530 /*
 531  * Returns a set of divisors for the desired target clock with the given
 532  * refclk, or FALSE.  The returned values represent the clock equation:
 533  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 534  *
 535  * Target and reference clocks are specified in kHz.
 536  *
 537  * If match_clock is provided, then best_clock P divider must match the P
 538  * divider from @match_clock used for LVDS downclocking.
 539  */
 540 static bool
 541 g4x_find_best_dpll(const struct intel_limit *limit,
 542                    struct intel_crtc_state *crtc_state,
 543                    int target, int refclk, struct dpll *match_clock,
 544                    struct dpll *best_clock)
 545 {
 546         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 547         struct dpll clock;
 548         int max_n;
 549         bool found = false;
 550         /* approximately equals target * 0.00585 */
 551         int err_most = (target >> 8) + (target >> 9);
 552
 553         memset(best_clock, 0, sizeof(*best_clock));
 554
 555         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 556
 557         max_n = limit->n.max;
 558         /* based on hardware requirement, prefer smaller n to precision */
 559         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 560                 /* based on hardware requirement, prefere larger m1,m2 */
 561                 for (clock.m1 = limit->m1.max;
 562                      clock.m1 >= limit->m1.min; clock.m1--) {
 563                         for (clock.m2 = limit->m2.max;
 564                              clock.m2 >= limit->m2.min; clock.m2--) {
 565                                 for (clock.p1 = limit->p1.max;
 566                                      clock.p1 >= limit->p1.min; clock.p1--) {
 567                                         int this_err;
 568
 569                                         i9xx_calc_dpll_params(refclk, &clock);
 570                                         if (!intel_pll_is_valid(to_i915(dev),
 571                                                                 limit,
 572                                                                 &clock))
 573                                                 continue;
 574
 575                                         this_err = abs(clock.dot - target);
 576                                         if (this_err < err_most) {
 577                                                 *best_clock = clock;
 578                                                 err_most = this_err;
 579                                                 max_n = clock.n;
 580                                                 found = true;
 581                                         }
 582                                 }
 583                         }
 584                 }
 585         }
 586         return found;
 587 }
 588
 589 /*
 590  * Check if the calculated PLL configuration is more optimal compared to the
 591  * best configuration and error found so far. Return the calculated error.
 592  */
 593 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 594                                const struct dpll *calculated_clock,
 595                                const struct dpll *best_clock,
 596                                unsigned int best_error_ppm,
 597                                unsigned int *error_ppm)
 598 {
 599         /*
 600          * For CHV ignore the error and consider only the P value.
 601          * Prefer a bigger P value based on HW requirements.
 602          */
 603         if (IS_CHERRYVIEW(to_i915(dev))) {
 604                 *error_ppm = 0;
 605
 606                 return calculated_clock->p > best_clock->p;
 607         }
 608
 609         if (drm_WARN_ON_ONCE(dev, !target_freq))
 610                 return false;
 611
 612         *error_ppm = div_u64(1000000ULL *
 613                                 abs(target_freq - calculated_clock->dot),
 614                              target_freq);
 615         /*
 616          * Prefer a better P value over a better (smaller) error if the error
 617          * is small. Ensure this preference for future configurations too by
 618          * setting the error to 0.
 619          */
 620         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 621                 *error_ppm = 0;
 622
 623                 return true;
 624         }
 625
 626         return *error_ppm + 10 < best_error_ppm;
 627 }
 628
 629 /*
 630  * Returns a set of divisors for the desired target clock with the given
 631  * refclk, or FALSE.  The returned values represent the clock equation:
 632  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 633  */
 634 static bool
 635 vlv_find_best_dpll(const struct intel_limit *limit,
 636                    struct intel_crtc_state *crtc_state,
 637                    int target, int refclk, struct dpll *match_clock,
 638                    struct dpll *best_clock)
 639 {
 640         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 641         struct drm_device *dev = crtc->base.dev;
 642         struct dpll clock;
 643         unsigned int bestppm = 1000000;
 644         /* min update 19.2 MHz */
 645         int max_n = min(limit->n.max, refclk / 19200);
 646         bool found = false;
 647
 648         target *= 5; /* fast clock */
 649
 650         memset(best_clock, 0, sizeof(*best_clock));
 651
 652         /* based on hardware requirement, prefer smaller n to precision */
 653         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 654                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 655                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 656                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 657                                 clock.p = clock.p1 * clock.p2;
 658                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 659                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 660                                         unsigned int ppm;
 661
 662                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 663                                                                      refclk * clock.m1);
 664
 665                                         vlv_calc_dpll_params(refclk, &clock);
 666
 667                                         if (!intel_pll_is_valid(to_i915(dev),
 668                                                                 limit,
 669                                                                 &clock))
 670                                                 continue;
 671
 672                                         if (!vlv_PLL_is_optimal(dev, target,
 673                                                                 &clock,
 674                                                                 best_clock,
 675                                                                 bestppm, &ppm))
 676                                                 continue;
 677
 678                                         *best_clock = clock;
 679                                         bestppm = ppm;
 680                                         found = true;
 681                                 }
 682                         }
 683                 }
 684         }
 685
 686         return found;
 687 }
 688
 689 /*
 690  * Returns a set of divisors for the desired target clock with the given
 691  * refclk, or FALSE.  The returned values represent the clock equation:
 692  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 693  */
 694 static bool
 695 chv_find_best_dpll(const struct intel_limit *limit,
 696                    struct intel_crtc_state *crtc_state,
 697                    int target, int refclk, struct dpll *match_clock,
 698                    struct dpll *best_clock)
 699 {
 700         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 701         struct drm_device *dev = crtc->base.dev;
 702         unsigned int best_error_ppm;
 703         struct dpll clock;
 704         u64 m2;
 705         int found = false;
 706
 707         memset(best_clock, 0, sizeof(*best_clock));
 708         best_error_ppm = 1000000;
 709
 710         /*
 711          * Based on hardware doc, the n always set to 1, and m1 always
 712          * set to 2.  If requires to support 200Mhz refclk, we need to
 713          * revisit this because n may not 1 anymore.
 714          */
 715         clock.n = 1;
 716         clock.m1 = 2;
 717         target *= 5;    /* fast clock */
 718
 719         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 720                 for (clock.p2 = limit->p2.p2_fast;
 721                                 clock.p2 >= limit->p2.p2_slow;
 722                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 723                         unsigned int error_ppm;
 724
 725                         clock.p = clock.p1 * clock.p2;
 726
 727                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
 728                                                    refclk * clock.m1);
 729
 730                         if (m2 > INT_MAX/clock.m1)
 731                                 continue;
 732
 733                         clock.m2 = m2;
 734
 735                         chv_calc_dpll_params(refclk, &clock);
 736
 737                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
 738                                 continue;
 739
 740                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 741                                                 best_error_ppm, &error_ppm))
 742                                 continue;
 743
 744                         *best_clock = clock;
 745                         best_error_ppm = error_ppm;
 746                         found = true;
 747                 }
 748         }
 749
 750         return found;
 751 }
 752
 753 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 754                         struct dpll *best_clock)
 755 {
 756         int refclk = 100000;
 757         const struct intel_limit *limit = &intel_limits_bxt;
 758
 759         return chv_find_best_dpll(limit, crtc_state,
 760                                   crtc_state->port_clock, refclk,
 761                                   NULL, best_clock);
 762 }
 763
 764 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
 765 {
 766         return (1 << dpll->n) << 16 | dpll->m2;
 767 }
 768
 769 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 770                                      struct intel_crtc_state *crtc_state,
 771                                      struct dpll *reduced_clock)
 772 {
 773         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 774         u32 fp, fp2 = 0;
 775
 776         if (IS_PINEVIEW(dev_priv)) {
 777                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
 778                 if (reduced_clock)
 779                         fp2 = pnv_dpll_compute_fp(reduced_clock);
 780         } else {
 781                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
 782                 if (reduced_clock)
 783                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
 784         }
 785
 786         crtc_state->dpll_hw_state.fp0 = fp;
 787
 788         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 789             reduced_clock) {
 790                 crtc_state->dpll_hw_state.fp1 = fp2;
 791         } else {
 792                 crtc_state->dpll_hw_state.fp1 = fp;
 793         }
 794 }
 795
 796 static void i9xx_compute_dpll(struct intel_crtc *crtc,
 797                               struct intel_crtc_state *crtc_state,
 798                               struct dpll *reduced_clock)
 799 {
 800         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 801         u32 dpll;
 802         struct dpll *clock = &crtc_state->dpll;
 803
 804         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 805
 806         dpll = DPLL_VGA_MODE_DIS;
 807
 808         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
 809                 dpll |= DPLLB_MODE_LVDS;
 810         else
 811                 dpll |= DPLLB_MODE_DAC_SERIAL;
 812
 813         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 814             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
 815                 dpll |= (crtc_state->pixel_multiplier - 1)
 816                         << SDVO_MULTIPLIER_SHIFT_HIRES;
 817         }
 818
 819         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
 820             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 821                 dpll |= DPLL_SDVO_HIGH_SPEED;
 822
 823         if (intel_crtc_has_dp_encoder(crtc_state))
 824                 dpll |= DPLL_SDVO_HIGH_SPEED;
 825
 826         /* compute bitmask from p1 value */
 827         if (IS_PINEVIEW(dev_priv))
 828                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
 829         else {
 830                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 831                 if (IS_G4X(dev_priv) && reduced_clock)
 832                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 833         }
 834         switch (clock->p2) {
 835         case 5:
 836                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 837                 break;
 838         case 7:
 839                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
 840                 break;
 841         case 10:
 842                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
 843                 break;
 844         case 14:
 845                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 846                 break;
 847         }
 848         if (INTEL_GEN(dev_priv) >= 4)
 849                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 850
 851         if (crtc_state->sdvo_tv_clock)
 852                 dpll |= PLL_REF_INPUT_TVCLKINBC;
 853         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 854                  intel_panel_use_ssc(dev_priv))
 855                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 856         else
 857                 dpll |= PLL_REF_INPUT_DREFCLK;
 858
 859         dpll |= DPLL_VCO_ENABLE;
 860         crtc_state->dpll_hw_state.dpll = dpll;
 861
 862         if (INTEL_GEN(dev_priv) >= 4) {
 863                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
 864                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 865                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
 866         }
 867 }
 868
 869 static void i8xx_compute_dpll(struct intel_crtc *crtc,
 870                               struct intel_crtc_state *crtc_state,
 871                               struct dpll *reduced_clock)
 872 {
 873         struct drm_device *dev = crtc->base.dev;
 874         struct drm_i915_private *dev_priv = to_i915(dev);
 875         u32 dpll;
 876         struct dpll *clock = &crtc_state->dpll;
 877
 878         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 879
 880         dpll = DPLL_VGA_MODE_DIS;
 881
 882         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 883                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 884         } else {
 885                 if (clock->p1 == 2)
 886                         dpll |= PLL_P1_DIVIDE_BY_TWO;
 887                 else
 888                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 889                 if (clock->p2 == 4)
 890                         dpll |= PLL_P2_DIVIDE_BY_4;
 891         }
 892
 893         /*
 894          * Bspec:
 895          * "[Almador Errata}: For the correct operation of the muxed DVO pins
 896          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
 897          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
 898          *  Enable) must be set to “1” in both the DPLL A Control Register
 899          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
 900          *
 901          * For simplicity We simply keep both bits always enabled in
 902          * both DPLLS. The spec says we should disable the DVO 2X clock
 903          * when not needed, but this seems to work fine in practice.
 904          */
 905         if (IS_I830(dev_priv) ||
 906             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
 907                 dpll |= DPLL_DVO_2X_MODE;
 908
 909         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 910             intel_panel_use_ssc(dev_priv))
 911                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 912         else
 913                 dpll |= PLL_REF_INPUT_DREFCLK;
 914
 915         dpll |= DPLL_VCO_ENABLE;
 916         crtc_state->dpll_hw_state.dpll = dpll;
 917 }
 918
 919 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
 920                                   struct intel_crtc_state *crtc_state)
 921 {
 922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 923         struct intel_atomic_state *state =
 924                 to_intel_atomic_state(crtc_state->uapi.state);
 925
 926         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
 927             INTEL_GEN(dev_priv) >= 11) {
 928                 struct intel_encoder *encoder =
 929                         intel_get_crtc_new_encoder(state, crtc_state);
 930
 931                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
 932                         drm_dbg_kms(&dev_priv->drm,
 933                                     "failed to find PLL for pipe %c\n",
 934                                     pipe_name(crtc->pipe));
 935                         return -EINVAL;
 936                 }
 937         }
 938
 939         return 0;
 940 }
 941
 942 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
 943 {
 944         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
 945 }
 946
 947
 948 static void ilk_compute_dpll(struct intel_crtc *crtc,
 949                              struct intel_crtc_state *crtc_state,
 950                              struct dpll *reduced_clock)
 951 {
 952         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 953         u32 dpll, fp, fp2;
 954         int factor;
 955
 956         /* Enable autotuning of the PLL clock (if permissible) */
 957         factor = 21;
 958         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 959                 if ((intel_panel_use_ssc(dev_priv) &&
 960                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
 961                     (HAS_PCH_IBX(dev_priv) &&
 962                      intel_is_dual_link_lvds(dev_priv)))
 963                         factor = 25;
 964         } else if (crtc_state->sdvo_tv_clock) {
 965                 factor = 20;
 966         }
 967
 968         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
 969
 970         if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
 971                 fp |= FP_CB_TUNE;
 972
 973         if (reduced_clock) {
 974                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
 975
 976                 if (reduced_clock->m < factor * reduced_clock->n)
 977                         fp2 |= FP_CB_TUNE;
 978         } else {
 979                 fp2 = fp;
 980         }
 981
 982         dpll = 0;
 983
 984         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
 985                 dpll |= DPLLB_MODE_LVDS;
 986         else
 987                 dpll |= DPLLB_MODE_DAC_SERIAL;
 988
 989         dpll |= (crtc_state->pixel_multiplier - 1)
 990                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
 991
 992         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
 993             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 994                 dpll |= DPLL_SDVO_HIGH_SPEED;
 995
 996         if (intel_crtc_has_dp_encoder(crtc_state))
 997                 dpll |= DPLL_SDVO_HIGH_SPEED;
 998
 999         /*
1000          * The high speed IO clock is only really required for
1001          * SDVO/HDMI/DP, but we also enable it for CRT to make it
1002          * possible to share the DPLL between CRT and HDMI. Enabling
1003          * the clock needlessly does no real harm, except use up a
1004          * bit of power potentially.
1005          *
1006          * We'll limit this to IVB with 3 pipes, since it has only two
1007          * DPLLs and so DPLL sharing is the only way to get three pipes
1008          * driving PCH ports at the same time. On SNB we could do this,
1009          * and potentially avoid enabling the second DPLL, but it's not
1010          * clear if it''s a win or loss power wise. No point in doing
1011          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
1012          */
1013         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
1014             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1015                 dpll |= DPLL_SDVO_HIGH_SPEED;
1016
1017         /* compute bitmask from p1 value */
1018         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1019         /* also FPA1 */
1020         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1021
1022         switch (crtc_state->dpll.p2) {
1023         case 5:
1024                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1025                 break;
1026         case 7:
1027                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1028                 break;
1029         case 10:
1030                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1031                 break;
1032         case 14:
1033                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1034                 break;
1035         }
1036
1037         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1038             intel_panel_use_ssc(dev_priv))
1039                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1040         else
1041                 dpll |= PLL_REF_INPUT_DREFCLK;
1042
1043         dpll |= DPLL_VCO_ENABLE;
1044
1045         crtc_state->dpll_hw_state.dpll = dpll;
1046         crtc_state->dpll_hw_state.fp0 = fp;
1047         crtc_state->dpll_hw_state.fp1 = fp2;
1048 }
1049
1050 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
1051                                   struct intel_crtc_state *crtc_state)
1052 {
1053         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1054         struct intel_atomic_state *state =
1055                 to_intel_atomic_state(crtc_state->uapi.state);
1056         const struct intel_limit *limit;
1057         int refclk = 120000;
1058
1059         memset(&crtc_state->dpll_hw_state, 0,
1060                sizeof(crtc_state->dpll_hw_state));
1061
1062         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1063         if (!crtc_state->has_pch_encoder)
1064                 return 0;
1065
1066         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1067                 if (intel_panel_use_ssc(dev_priv)) {
1068                         drm_dbg_kms(&dev_priv->drm,
1069                                     "using SSC reference clock of %d kHz\n",
1070                                     dev_priv->vbt.lvds_ssc_freq);
1071                         refclk = dev_priv->vbt.lvds_ssc_freq;
1072                 }
1073
1074                 if (intel_is_dual_link_lvds(dev_priv)) {
1075                         if (refclk == 100000)
1076                                 limit = &ilk_limits_dual_lvds_100m;
1077                         else
1078                                 limit = &ilk_limits_dual_lvds;
1079                 } else {
1080                         if (refclk == 100000)
1081                                 limit = &ilk_limits_single_lvds_100m;
1082                         else
1083                                 limit = &ilk_limits_single_lvds;
1084                 }
1085         } else {
1086                 limit = &ilk_limits_dac;
1087         }
1088
1089         if (!crtc_state->clock_set &&
1090             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1091                                 refclk, NULL, &crtc_state->dpll)) {
1092                 drm_err(&dev_priv->drm,
1093                         "Couldn't find PLL settings for mode!\n");
1094                 return -EINVAL;
1095         }
1096
1097         ilk_compute_dpll(crtc, crtc_state, NULL);
1098
1099         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
1100                 drm_dbg_kms(&dev_priv->drm,
1101                             "failed to find PLL for pipe %c\n",
1102                             pipe_name(crtc->pipe));
1103                 return -EINVAL;
1104         }
1105
1106         return 0;
1107 }
1108
1109 void vlv_compute_dpll(struct intel_crtc *crtc,
1110                       struct intel_crtc_state *pipe_config)
1111 {
1112         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
1113                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1114         if (crtc->pipe != PIPE_A)
1115                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1116
1117         /* DPLL not used with DSI, but still need the rest set up */
1118         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
1119                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
1120                         DPLL_EXT_BUFFER_ENABLE_VLV;
1121
1122         pipe_config->dpll_hw_state.dpll_md =
1123                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1124 }
1125
1126 void chv_compute_dpll(struct intel_crtc *crtc,
1127                       struct intel_crtc_state *pipe_config)
1128 {
1129         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
1130                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1131         if (crtc->pipe != PIPE_A)
1132                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1133
1134         /* DPLL not used with DSI, but still need the rest set up */
1135         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
1136                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
1137
1138         pipe_config->dpll_hw_state.dpll_md =
1139                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1140 }
1141
1142 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
1143                                   struct intel_crtc_state *crtc_state)
1144 {
1145         int refclk = 100000;
1146         const struct intel_limit *limit = &intel_limits_chv;
1147         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1148
1149         memset(&crtc_state->dpll_hw_state, 0,
1150                sizeof(crtc_state->dpll_hw_state));
1151
1152         if (!crtc_state->clock_set &&
1153             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1154                                 refclk, NULL, &crtc_state->dpll)) {
1155                 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
1156                 return -EINVAL;
1157         }
1158
1159         chv_compute_dpll(crtc, crtc_state);
1160
1161         return 0;
1162 }
1163
1164 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
1165                                   struct intel_crtc_state *crtc_state)
1166 {
1167         int refclk = 100000;
1168         const struct intel_limit *limit = &intel_limits_vlv;
1169         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1170
1171         memset(&crtc_state->dpll_hw_state, 0,
1172                sizeof(crtc_state->dpll_hw_state));
1173
1174         if (!crtc_state->clock_set &&
1175             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1176                                 refclk, NULL, &crtc_state->dpll)) {
1177                 drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
1178                 return -EINVAL;
1179         }
1180
1181         vlv_compute_dpll(crtc, crtc_state);
1182
1183         return 0;
1184 }
1185
1186 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
1187                                   struct intel_crtc_state *crtc_state)
1188 {
1189         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1190         const struct intel_limit *limit;
1191         int refclk = 96000;
1192
1193         memset(&crtc_state->dpll_hw_state, 0,
1194                sizeof(crtc_state->dpll_hw_state));
1195
1196         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1197                 if (intel_panel_use_ssc(dev_priv)) {
1198                         refclk = dev_priv->vbt.lvds_ssc_freq;
1199                         drm_dbg_kms(&dev_priv->drm,
1200                                     "using SSC reference clock of %d kHz\n",
1201                                     refclk);
1202                 }
1203
1204                 if (intel_is_dual_link_lvds(dev_priv))
1205                         limit = &intel_limits_g4x_dual_channel_lvds;
1206                 else
1207                         limit = &intel_limits_g4x_single_channel_lvds;
1208         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
1209                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1210                 limit = &intel_limits_g4x_hdmi;
1211         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
1212                 limit = &intel_limits_g4x_sdvo;
1213         } else {
1214                 /* The option is for other outputs */
1215                 limit = &intel_limits_i9xx_sdvo;
1216         }
1217
1218         if (!crtc_state->clock_set &&
1219             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1220                                 refclk, NULL, &crtc_state->dpll)) {
1221                 drm_err(&dev_priv->drm,
1222                         "Couldn't find PLL settings for mode!\n");
1223                 return -EINVAL;
1224         }
1225
1226         i9xx_compute_dpll(crtc, crtc_state, NULL);
1227
1228         return 0;
1229 }
1230
1231 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
1232                                   struct intel_crtc_state *crtc_state)
1233 {
1234         struct drm_device *dev = crtc->base.dev;
1235         struct drm_i915_private *dev_priv = to_i915(dev);
1236         const struct intel_limit *limit;
1237         int refclk = 96000;
1238
1239         memset(&crtc_state->dpll_hw_state, 0,
1240                sizeof(crtc_state->dpll_hw_state));
1241
1242         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1243                 if (intel_panel_use_ssc(dev_priv)) {
1244                         refclk = dev_priv->vbt.lvds_ssc_freq;
1245                         drm_dbg_kms(&dev_priv->drm,
1246                                     "using SSC reference clock of %d kHz\n",
1247                                     refclk);
1248                 }
1249
1250                 limit = &pnv_limits_lvds;
1251         } else {
1252                 limit = &pnv_limits_sdvo;
1253         }
1254
1255         if (!crtc_state->clock_set &&
1256             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1257                                 refclk, NULL, &crtc_state->dpll)) {
1258                 drm_err(&dev_priv->drm,
1259                         "Couldn't find PLL settings for mode!\n");
1260                 return -EINVAL;
1261         }
1262
1263         i9xx_compute_dpll(crtc, crtc_state, NULL);
1264
1265         return 0;
1266 }
1267
1268 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
1269                                    struct intel_crtc_state *crtc_state)
1270 {
1271         struct drm_device *dev = crtc->base.dev;
1272         struct drm_i915_private *dev_priv = to_i915(dev);
1273         const struct intel_limit *limit;
1274         int refclk = 96000;
1275
1276         memset(&crtc_state->dpll_hw_state, 0,
1277                sizeof(crtc_state->dpll_hw_state));
1278
1279         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1280                 if (intel_panel_use_ssc(dev_priv)) {
1281                         refclk = dev_priv->vbt.lvds_ssc_freq;
1282                         drm_dbg_kms(&dev_priv->drm,
1283                                     "using SSC reference clock of %d kHz\n",
1284                                     refclk);
1285                 }
1286
1287                 limit = &intel_limits_i9xx_lvds;
1288         } else {
1289                 limit = &intel_limits_i9xx_sdvo;
1290         }
1291
1292         if (!crtc_state->clock_set &&
1293             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1294                                  refclk, NULL, &crtc_state->dpll)) {
1295                 drm_err(&dev_priv->drm,
1296                         "Couldn't find PLL settings for mode!\n");
1297                 return -EINVAL;
1298         }
1299
1300         i9xx_compute_dpll(crtc, crtc_state, NULL);
1301
1302         return 0;
1303 }
1304
1305 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
1306                                    struct intel_crtc_state *crtc_state)
1307 {
1308         struct drm_device *dev = crtc->base.dev;
1309         struct drm_i915_private *dev_priv = to_i915(dev);
1310         const struct intel_limit *limit;
1311         int refclk = 48000;
1312
1313         memset(&crtc_state->dpll_hw_state, 0,
1314                sizeof(crtc_state->dpll_hw_state));
1315
1316         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1317                 if (intel_panel_use_ssc(dev_priv)) {
1318                         refclk = dev_priv->vbt.lvds_ssc_freq;
1319                         drm_dbg_kms(&dev_priv->drm,
1320                                     "using SSC reference clock of %d kHz\n",
1321                                     refclk);
1322                 }
1323
1324                 limit = &intel_limits_i8xx_lvds;
1325         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
1326                 limit = &intel_limits_i8xx_dvo;
1327         } else {
1328                 limit = &intel_limits_i8xx_dac;
1329         }
1330
1331         if (!crtc_state->clock_set &&
1332             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1333                                  refclk, NULL, &crtc_state->dpll)) {
1334                 drm_err(&dev_priv->drm,
1335                         "Couldn't find PLL settings for mode!\n");
1336                 return -EINVAL;
1337         }
1338
1339         i8xx_compute_dpll(crtc, crtc_state, NULL);
1340
1341         return 0;
1342 }
1343
1344 void
1345 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
1346 {
1347         if (INTEL_GEN(dev_priv) >= 9 || HAS_DDI(dev_priv))
1348                 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
1349         else if (HAS_PCH_SPLIT(dev_priv))
1350                 dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
1351         else if (IS_CHERRYVIEW(dev_priv))
1352                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
1353         else if (IS_VALLEYVIEW(dev_priv))
1354                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
1355         else if (IS_G4X(dev_priv))
1356                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
1357         else if (IS_PINEVIEW(dev_priv))
1358                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
1359         else if (!IS_GEN(dev_priv, 2))
1360                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
1361         else
1362                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
1363 }