drivers/gpu/drm/i915/display/intel_dpll.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5 #include <linux/kernel.h>
   6 #include "intel_crtc.h"
   7 #include "intel_de.h"
   8 #include "intel_display_types.h"
   9 #include "intel_display.h"
  10 #include "intel_dpll.h"
  11 #include "intel_lvds.h"
  12 #include "intel_panel.h"
  13 #include "intel_sideband.h"
  14 #include "display/intel_snps_phy.h"
  15
  16 struct intel_limit {
  17         struct {
  18                 int min, max;
  19         } dot, vco, n, m, m1, m2, p, p1;
  20
  21         struct {
  22                 int dot_limit;
  23                 int p2_slow, p2_fast;
  24         } p2;
  25 };
  26 static const struct intel_limit intel_limits_i8xx_dac = {
  27         .dot = { .min = 25000, .max = 350000 },
  28         .vco = { .min = 908000, .max = 1512000 },
  29         .n = { .min = 2, .max = 16 },
  30         .m = { .min = 96, .max = 140 },
  31         .m1 = { .min = 18, .max = 26 },
  32         .m2 = { .min = 6, .max = 16 },
  33         .p = { .min = 4, .max = 128 },
  34         .p1 = { .min = 2, .max = 33 },
  35         .p2 = { .dot_limit = 165000,
  36                 .p2_slow = 4, .p2_fast = 2 },
  37 };
  38
  39 static const struct intel_limit intel_limits_i8xx_dvo = {
  40         .dot = { .min = 25000, .max = 350000 },
  41         .vco = { .min = 908000, .max = 1512000 },
  42         .n = { .min = 2, .max = 16 },
  43         .m = { .min = 96, .max = 140 },
  44         .m1 = { .min = 18, .max = 26 },
  45         .m2 = { .min = 6, .max = 16 },
  46         .p = { .min = 4, .max = 128 },
  47         .p1 = { .min = 2, .max = 33 },
  48         .p2 = { .dot_limit = 165000,
  49                 .p2_slow = 4, .p2_fast = 4 },
  50 };
  51
  52 static const struct intel_limit intel_limits_i8xx_lvds = {
  53         .dot = { .min = 25000, .max = 350000 },
  54         .vco = { .min = 908000, .max = 1512000 },
  55         .n = { .min = 2, .max = 16 },
  56         .m = { .min = 96, .max = 140 },
  57         .m1 = { .min = 18, .max = 26 },
  58         .m2 = { .min = 6, .max = 16 },
  59         .p = { .min = 4, .max = 128 },
  60         .p1 = { .min = 1, .max = 6 },
  61         .p2 = { .dot_limit = 165000,
  62                 .p2_slow = 14, .p2_fast = 7 },
  63 };
  64
  65 static const struct intel_limit intel_limits_i9xx_sdvo = {
  66         .dot = { .min = 20000, .max = 400000 },
  67         .vco = { .min = 1400000, .max = 2800000 },
  68         .n = { .min = 1, .max = 6 },
  69         .m = { .min = 70, .max = 120 },
  70         .m1 = { .min = 8, .max = 18 },
  71         .m2 = { .min = 3, .max = 7 },
  72         .p = { .min = 5, .max = 80 },
  73         .p1 = { .min = 1, .max = 8 },
  74         .p2 = { .dot_limit = 200000,
  75                 .p2_slow = 10, .p2_fast = 5 },
  76 };
  77
  78 static const struct intel_limit intel_limits_i9xx_lvds = {
  79         .dot = { .min = 20000, .max = 400000 },
  80         .vco = { .min = 1400000, .max = 2800000 },
  81         .n = { .min = 1, .max = 6 },
  82         .m = { .min = 70, .max = 120 },
  83         .m1 = { .min = 8, .max = 18 },
  84         .m2 = { .min = 3, .max = 7 },
  85         .p = { .min = 7, .max = 98 },
  86         .p1 = { .min = 1, .max = 8 },
  87         .p2 = { .dot_limit = 112000,
  88                 .p2_slow = 14, .p2_fast = 7 },
  89 };
  90
  91
  92 static const struct intel_limit intel_limits_g4x_sdvo = {
  93         .dot = { .min = 25000, .max = 270000 },
  94         .vco = { .min = 1750000, .max = 3500000},
  95         .n = { .min = 1, .max = 4 },
  96         .m = { .min = 104, .max = 138 },
  97         .m1 = { .min = 17, .max = 23 },
  98         .m2 = { .min = 5, .max = 11 },
  99         .p = { .min = 10, .max = 30 },
 100         .p1 = { .min = 1, .max = 3},
 101         .p2 = { .dot_limit = 270000,
 102                 .p2_slow = 10,
 103                 .p2_fast = 10
 104         },
 105 };
 106
 107 static const struct intel_limit intel_limits_g4x_hdmi = {
 108         .dot = { .min = 22000, .max = 400000 },
 109         .vco = { .min = 1750000, .max = 3500000},
 110         .n = { .min = 1, .max = 4 },
 111         .m = { .min = 104, .max = 138 },
 112         .m1 = { .min = 16, .max = 23 },
 113         .m2 = { .min = 5, .max = 11 },
 114         .p = { .min = 5, .max = 80 },
 115         .p1 = { .min = 1, .max = 8},
 116         .p2 = { .dot_limit = 165000,
 117                 .p2_slow = 10, .p2_fast = 5 },
 118 };
 119
 120 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 121         .dot = { .min = 20000, .max = 115000 },
 122         .vco = { .min = 1750000, .max = 3500000 },
 123         .n = { .min = 1, .max = 3 },
 124         .m = { .min = 104, .max = 138 },
 125         .m1 = { .min = 17, .max = 23 },
 126         .m2 = { .min = 5, .max = 11 },
 127         .p = { .min = 28, .max = 112 },
 128         .p1 = { .min = 2, .max = 8 },
 129         .p2 = { .dot_limit = 0,
 130                 .p2_slow = 14, .p2_fast = 14
 131         },
 132 };
 133
 134 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 135         .dot = { .min = 80000, .max = 224000 },
 136         .vco = { .min = 1750000, .max = 3500000 },
 137         .n = { .min = 1, .max = 3 },
 138         .m = { .min = 104, .max = 138 },
 139         .m1 = { .min = 17, .max = 23 },
 140         .m2 = { .min = 5, .max = 11 },
 141         .p = { .min = 14, .max = 42 },
 142         .p1 = { .min = 2, .max = 6 },
 143         .p2 = { .dot_limit = 0,
 144                 .p2_slow = 7, .p2_fast = 7
 145         },
 146 };
 147
 148 static const struct intel_limit pnv_limits_sdvo = {
 149         .dot = { .min = 20000, .max = 400000},
 150         .vco = { .min = 1700000, .max = 3500000 },
 151         /* Pineview's Ncounter is a ring counter */
 152         .n = { .min = 3, .max = 6 },
 153         .m = { .min = 2, .max = 256 },
 154         /* Pineview only has one combined m divider, which we treat as m2. */
 155         .m1 = { .min = 0, .max = 0 },
 156         .m2 = { .min = 0, .max = 254 },
 157         .p = { .min = 5, .max = 80 },
 158         .p1 = { .min = 1, .max = 8 },
 159         .p2 = { .dot_limit = 200000,
 160                 .p2_slow = 10, .p2_fast = 5 },
 161 };
 162
 163 static const struct intel_limit pnv_limits_lvds = {
 164         .dot = { .min = 20000, .max = 400000 },
 165         .vco = { .min = 1700000, .max = 3500000 },
 166         .n = { .min = 3, .max = 6 },
 167         .m = { .min = 2, .max = 256 },
 168         .m1 = { .min = 0, .max = 0 },
 169         .m2 = { .min = 0, .max = 254 },
 170         .p = { .min = 7, .max = 112 },
 171         .p1 = { .min = 1, .max = 8 },
 172         .p2 = { .dot_limit = 112000,
 173                 .p2_slow = 14, .p2_fast = 14 },
 174 };
 175
 176 /* Ironlake / Sandybridge
 177  *
 178  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 179  * the range value for them is (actual_value - 2).
 180  */
 181 static const struct intel_limit ilk_limits_dac = {
 182         .dot = { .min = 25000, .max = 350000 },
 183         .vco = { .min = 1760000, .max = 3510000 },
 184         .n = { .min = 1, .max = 5 },
 185         .m = { .min = 79, .max = 127 },
 186         .m1 = { .min = 12, .max = 22 },
 187         .m2 = { .min = 5, .max = 9 },
 188         .p = { .min = 5, .max = 80 },
 189         .p1 = { .min = 1, .max = 8 },
 190         .p2 = { .dot_limit = 225000,
 191                 .p2_slow = 10, .p2_fast = 5 },
 192 };
 193
 194 static const struct intel_limit ilk_limits_single_lvds = {
 195         .dot = { .min = 25000, .max = 350000 },
 196         .vco = { .min = 1760000, .max = 3510000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 79, .max = 118 },
 199         .m1 = { .min = 12, .max = 22 },
 200         .m2 = { .min = 5, .max = 9 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 225000,
 204                 .p2_slow = 14, .p2_fast = 14 },
 205 };
 206
 207 static const struct intel_limit ilk_limits_dual_lvds = {
 208         .dot = { .min = 25000, .max = 350000 },
 209         .vco = { .min = 1760000, .max = 3510000 },
 210         .n = { .min = 1, .max = 3 },
 211         .m = { .min = 79, .max = 127 },
 212         .m1 = { .min = 12, .max = 22 },
 213         .m2 = { .min = 5, .max = 9 },
 214         .p = { .min = 14, .max = 56 },
 215         .p1 = { .min = 2, .max = 8 },
 216         .p2 = { .dot_limit = 225000,
 217                 .p2_slow = 7, .p2_fast = 7 },
 218 };
 219
 220 /* LVDS 100mhz refclk limits. */
 221 static const struct intel_limit ilk_limits_single_lvds_100m = {
 222         .dot = { .min = 25000, .max = 350000 },
 223         .vco = { .min = 1760000, .max = 3510000 },
 224         .n = { .min = 1, .max = 2 },
 225         .m = { .min = 79, .max = 126 },
 226         .m1 = { .min = 12, .max = 22 },
 227         .m2 = { .min = 5, .max = 9 },
 228         .p = { .min = 28, .max = 112 },
 229         .p1 = { .min = 2, .max = 8 },
 230         .p2 = { .dot_limit = 225000,
 231                 .p2_slow = 14, .p2_fast = 14 },
 232 };
 233
 234 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 235         .dot = { .min = 25000, .max = 350000 },
 236         .vco = { .min = 1760000, .max = 3510000 },
 237         .n = { .min = 1, .max = 3 },
 238         .m = { .min = 79, .max = 126 },
 239         .m1 = { .min = 12, .max = 22 },
 240         .m2 = { .min = 5, .max = 9 },
 241         .p = { .min = 14, .max = 42 },
 242         .p1 = { .min = 2, .max = 6 },
 243         .p2 = { .dot_limit = 225000,
 244                 .p2_slow = 7, .p2_fast = 7 },
 245 };
 246
 247 static const struct intel_limit intel_limits_vlv = {
 248          /*
 249           * These are the data rate limits (measured in fast clocks)
 250           * since those are the strictest limits we have. The fast
 251           * clock and actual rate limits are more relaxed, so checking
 252           * them would make no difference.
 253           */
 254         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 255         .vco = { .min = 4000000, .max = 6000000 },
 256         .n = { .min = 1, .max = 7 },
 257         .m1 = { .min = 2, .max = 3 },
 258         .m2 = { .min = 11, .max = 156 },
 259         .p1 = { .min = 2, .max = 3 },
 260         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 261 };
 262
 263 static const struct intel_limit intel_limits_chv = {
 264         /*
 265          * These are the data rate limits (measured in fast clocks)
 266          * since those are the strictest limits we have.  The fast
 267          * clock and actual rate limits are more relaxed, so checking
 268          * them would make no difference.
 269          */
 270         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 271         .vco = { .min = 4800000, .max = 6480000 },
 272         .n = { .min = 1, .max = 1 },
 273         .m1 = { .min = 2, .max = 2 },
 274         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 275         .p1 = { .min = 2, .max = 4 },
 276         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 277 };
 278
 279 static const struct intel_limit intel_limits_bxt = {
 280         /* FIXME: find real dot limits */
 281         .dot = { .min = 0, .max = INT_MAX },
 282         .vco = { .min = 4800000, .max = 6700000 },
 283         .n = { .min = 1, .max = 1 },
 284         .m1 = { .min = 2, .max = 2 },
 285         /* FIXME: find real m2 limits */
 286         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 287         .p1 = { .min = 2, .max = 4 },
 288         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 289 };
 290
 291 /*
 292  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 293  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 294  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 295  * The helpers' return value is the rate of the clock that is fed to the
 296  * display engine's pipe which can be the above fast dot clock rate or a
 297  * divided-down version of it.
 298  */
 299 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 300 int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 301 {
 302         clock->m = clock->m2 + 2;
 303         clock->p = clock->p1 * clock->p2;
 304         if (WARN_ON(clock->n == 0 || clock->p == 0))
 305                 return 0;
 306         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 307         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 308
 309         return clock->dot;
 310 }
 311
 312 static u32 i9xx_dpll_compute_m(const struct dpll *dpll)
 313 {
 314         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 315 }
 316
 317 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 318 {
 319         clock->m = i9xx_dpll_compute_m(clock);
 320         clock->p = clock->p1 * clock->p2;
 321         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 322                 return 0;
 323         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 324         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 325
 326         return clock->dot;
 327 }
 328
 329 int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 330 {
 331         clock->m = clock->m1 * clock->m2;
 332         clock->p = clock->p1 * clock->p2;
 333         if (WARN_ON(clock->n == 0 || clock->p == 0))
 334                 return 0;
 335         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 336         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 337
 338         return clock->dot / 5;
 339 }
 340
 341 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 342 {
 343         clock->m = clock->m1 * clock->m2;
 344         clock->p = clock->p1 * clock->p2;
 345         if (WARN_ON(clock->n == 0 || clock->p == 0))
 346                 return 0;
 347         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 348                                            clock->n << 22);
 349         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 350
 351         return clock->dot / 5;
 352 }
 353
 354 /*
 355  * Returns whether the given set of divisors are valid for a given refclk with
 356  * the given connectors.
 357  */
 358 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 359                                const struct intel_limit *limit,
 360                                const struct dpll *clock)
 361 {
 362         if (clock->n < limit->n.min || limit->n.max < clock->n)
 363                 return false;
 364         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 365                 return false;
 366         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 367                 return false;
 368         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 369                 return false;
 370
 371         if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv))
 372                 if (clock->m1 <= clock->m2)
 373                         return false;
 374
 375         if (!IS_LP(dev_priv)) {
 376                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 377                         return false;
 378                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 379                         return false;
 380         }
 381
 382         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 383                 return false;
 384         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 385          * connector, etc., rather than just a single range.
 386          */
 387         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 388                 return false;
 389
 390         return true;
 391 }
 392
 393 static int
 394 i9xx_select_p2_div(const struct intel_limit *limit,
 395                    const struct intel_crtc_state *crtc_state,
 396                    int target)
 397 {
 398         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 399
 400         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 401                 /*
 402                  * For LVDS just rely on its current settings for dual-channel.
 403                  * We haven't figured out how to reliably set up different
 404                  * single/dual channel state, if we even can.
 405                  */
 406                 if (intel_is_dual_link_lvds(dev_priv))
 407                         return limit->p2.p2_fast;
 408                 else
 409                         return limit->p2.p2_slow;
 410         } else {
 411                 if (target < limit->p2.dot_limit)
 412                         return limit->p2.p2_slow;
 413                 else
 414                         return limit->p2.p2_fast;
 415         }
 416 }
 417
 418 /*
 419  * Returns a set of divisors for the desired target clock with the given
 420  * refclk, or FALSE.  The returned values represent the clock equation:
 421  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 422  *
 423  * Target and reference clocks are specified in kHz.
 424  *
 425  * If match_clock is provided, then best_clock P divider must match the P
 426  * divider from @match_clock used for LVDS downclocking.
 427  */
 428 static bool
 429 i9xx_find_best_dpll(const struct intel_limit *limit,
 430                     struct intel_crtc_state *crtc_state,
 431                     int target, int refclk,
 432                     const struct dpll *match_clock,
 433                     struct dpll *best_clock)
 434 {
 435         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 436         struct dpll clock;
 437         int err = target;
 438
 439         memset(best_clock, 0, sizeof(*best_clock));
 440
 441         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 442
 443         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 444              clock.m1++) {
 445                 for (clock.m2 = limit->m2.min;
 446                      clock.m2 <= limit->m2.max; clock.m2++) {
 447                         if (clock.m2 >= clock.m1)
 448                                 break;
 449                         for (clock.n = limit->n.min;
 450                              clock.n <= limit->n.max; clock.n++) {
 451                                 for (clock.p1 = limit->p1.min;
 452                                         clock.p1 <= limit->p1.max; clock.p1++) {
 453                                         int this_err;
 454
 455                                         i9xx_calc_dpll_params(refclk, &clock);
 456                                         if (!intel_pll_is_valid(to_i915(dev),
 457                                                                 limit,
 458                                                                 &clock))
 459                                                 continue;
 460                                         if (match_clock &&
 461                                             clock.p != match_clock->p)
 462                                                 continue;
 463
 464                                         this_err = abs(clock.dot - target);
 465                                         if (this_err < err) {
 466                                                 *best_clock = clock;
 467                                                 err = this_err;
 468                                         }
 469                                 }
 470                         }
 471                 }
 472         }
 473
 474         return (err != target);
 475 }
 476
 477 /*
 478  * Returns a set of divisors for the desired target clock with the given
 479  * refclk, or FALSE.  The returned values represent the clock equation:
 480  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 481  *
 482  * Target and reference clocks are specified in kHz.
 483  *
 484  * If match_clock is provided, then best_clock P divider must match the P
 485  * divider from @match_clock used for LVDS downclocking.
 486  */
 487 static bool
 488 pnv_find_best_dpll(const struct intel_limit *limit,
 489                    struct intel_crtc_state *crtc_state,
 490                    int target, int refclk,
 491                    const struct dpll *match_clock,
 492                    struct dpll *best_clock)
 493 {
 494         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 495         struct dpll clock;
 496         int err = target;
 497
 498         memset(best_clock, 0, sizeof(*best_clock));
 499
 500         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 501
 502         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 503              clock.m1++) {
 504                 for (clock.m2 = limit->m2.min;
 505                      clock.m2 <= limit->m2.max; clock.m2++) {
 506                         for (clock.n = limit->n.min;
 507                              clock.n <= limit->n.max; clock.n++) {
 508                                 for (clock.p1 = limit->p1.min;
 509                                         clock.p1 <= limit->p1.max; clock.p1++) {
 510                                         int this_err;
 511
 512                                         pnv_calc_dpll_params(refclk, &clock);
 513                                         if (!intel_pll_is_valid(to_i915(dev),
 514                                                                 limit,
 515                                                                 &clock))
 516                                                 continue;
 517                                         if (match_clock &&
 518                                             clock.p != match_clock->p)
 519                                                 continue;
 520
 521                                         this_err = abs(clock.dot - target);
 522                                         if (this_err < err) {
 523                                                 *best_clock = clock;
 524                                                 err = this_err;
 525                                         }
 526                                 }
 527                         }
 528                 }
 529         }
 530
 531         return (err != target);
 532 }
 533
 534 /*
 535  * Returns a set of divisors for the desired target clock with the given
 536  * refclk, or FALSE.  The returned values represent the clock equation:
 537  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 538  *
 539  * Target and reference clocks are specified in kHz.
 540  *
 541  * If match_clock is provided, then best_clock P divider must match the P
 542  * divider from @match_clock used for LVDS downclocking.
 543  */
 544 static bool
 545 g4x_find_best_dpll(const struct intel_limit *limit,
 546                    struct intel_crtc_state *crtc_state,
 547                    int target, int refclk,
 548                    const struct dpll *match_clock,
 549                    struct dpll *best_clock)
 550 {
 551         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 552         struct dpll clock;
 553         int max_n;
 554         bool found = false;
 555         /* approximately equals target * 0.00585 */
 556         int err_most = (target >> 8) + (target >> 9);
 557
 558         memset(best_clock, 0, sizeof(*best_clock));
 559
 560         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 561
 562         max_n = limit->n.max;
 563         /* based on hardware requirement, prefer smaller n to precision */
 564         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 565                 /* based on hardware requirement, prefere larger m1,m2 */
 566                 for (clock.m1 = limit->m1.max;
 567                      clock.m1 >= limit->m1.min; clock.m1--) {
 568                         for (clock.m2 = limit->m2.max;
 569                              clock.m2 >= limit->m2.min; clock.m2--) {
 570                                 for (clock.p1 = limit->p1.max;
 571                                      clock.p1 >= limit->p1.min; clock.p1--) {
 572                                         int this_err;
 573
 574                                         i9xx_calc_dpll_params(refclk, &clock);
 575                                         if (!intel_pll_is_valid(to_i915(dev),
 576                                                                 limit,
 577                                                                 &clock))
 578                                                 continue;
 579
 580                                         this_err = abs(clock.dot - target);
 581                                         if (this_err < err_most) {
 582                                                 *best_clock = clock;
 583                                                 err_most = this_err;
 584                                                 max_n = clock.n;
 585                                                 found = true;
 586                                         }
 587                                 }
 588                         }
 589                 }
 590         }
 591         return found;
 592 }
 593
 594 /*
 595  * Check if the calculated PLL configuration is more optimal compared to the
 596  * best configuration and error found so far. Return the calculated error.
 597  */
 598 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 599                                const struct dpll *calculated_clock,
 600                                const struct dpll *best_clock,
 601                                unsigned int best_error_ppm,
 602                                unsigned int *error_ppm)
 603 {
 604         /*
 605          * For CHV ignore the error and consider only the P value.
 606          * Prefer a bigger P value based on HW requirements.
 607          */
 608         if (IS_CHERRYVIEW(to_i915(dev))) {
 609                 *error_ppm = 0;
 610
 611                 return calculated_clock->p > best_clock->p;
 612         }
 613
 614         if (drm_WARN_ON_ONCE(dev, !target_freq))
 615                 return false;
 616
 617         *error_ppm = div_u64(1000000ULL *
 618                                 abs(target_freq - calculated_clock->dot),
 619                              target_freq);
 620         /*
 621          * Prefer a better P value over a better (smaller) error if the error
 622          * is small. Ensure this preference for future configurations too by
 623          * setting the error to 0.
 624          */
 625         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 626                 *error_ppm = 0;
 627
 628                 return true;
 629         }
 630
 631         return *error_ppm + 10 < best_error_ppm;
 632 }
 633
 634 /*
 635  * Returns a set of divisors for the desired target clock with the given
 636  * refclk, or FALSE.  The returned values represent the clock equation:
 637  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 638  */
 639 static bool
 640 vlv_find_best_dpll(const struct intel_limit *limit,
 641                    struct intel_crtc_state *crtc_state,
 642                    int target, int refclk,
 643                    const struct dpll *match_clock,
 644                    struct dpll *best_clock)
 645 {
 646         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 647         struct drm_device *dev = crtc->base.dev;
 648         struct dpll clock;
 649         unsigned int bestppm = 1000000;
 650         /* min update 19.2 MHz */
 651         int max_n = min(limit->n.max, refclk / 19200);
 652         bool found = false;
 653
 654         target *= 5; /* fast clock */
 655
 656         memset(best_clock, 0, sizeof(*best_clock));
 657
 658         /* based on hardware requirement, prefer smaller n to precision */
 659         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 660                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 661                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 662                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 663                                 clock.p = clock.p1 * clock.p2;
 664                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 665                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 666                                         unsigned int ppm;
 667
 668                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 669                                                                      refclk * clock.m1);
 670
 671                                         vlv_calc_dpll_params(refclk, &clock);
 672
 673                                         if (!intel_pll_is_valid(to_i915(dev),
 674                                                                 limit,
 675                                                                 &clock))
 676                                                 continue;
 677
 678                                         if (!vlv_PLL_is_optimal(dev, target,
 679                                                                 &clock,
 680                                                                 best_clock,
 681                                                                 bestppm, &ppm))
 682                                                 continue;
 683
 684                                         *best_clock = clock;
 685                                         bestppm = ppm;
 686                                         found = true;
 687                                 }
 688                         }
 689                 }
 690         }
 691
 692         return found;
 693 }
 694
 695 /*
 696  * Returns a set of divisors for the desired target clock with the given
 697  * refclk, or FALSE.  The returned values represent the clock equation:
 698  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 699  */
 700 static bool
 701 chv_find_best_dpll(const struct intel_limit *limit,
 702                    struct intel_crtc_state *crtc_state,
 703                    int target, int refclk,
 704                    const struct dpll *match_clock,
 705                    struct dpll *best_clock)
 706 {
 707         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 708         struct drm_device *dev = crtc->base.dev;
 709         unsigned int best_error_ppm;
 710         struct dpll clock;
 711         u64 m2;
 712         int found = false;
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715         best_error_ppm = 1000000;
 716
 717         /*
 718          * Based on hardware doc, the n always set to 1, and m1 always
 719          * set to 2.  If requires to support 200Mhz refclk, we need to
 720          * revisit this because n may not 1 anymore.
 721          */
 722         clock.n = 1;
 723         clock.m1 = 2;
 724         target *= 5;    /* fast clock */
 725
 726         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 727                 for (clock.p2 = limit->p2.p2_fast;
 728                                 clock.p2 >= limit->p2.p2_slow;
 729                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 730                         unsigned int error_ppm;
 731
 732                         clock.p = clock.p1 * clock.p2;
 733
 734                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
 735                                                    refclk * clock.m1);
 736
 737                         if (m2 > INT_MAX/clock.m1)
 738                                 continue;
 739
 740                         clock.m2 = m2;
 741
 742                         chv_calc_dpll_params(refclk, &clock);
 743
 744                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
 745                                 continue;
 746
 747                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 748                                                 best_error_ppm, &error_ppm))
 749                                 continue;
 750
 751                         *best_clock = clock;
 752                         best_error_ppm = error_ppm;
 753                         found = true;
 754                 }
 755         }
 756
 757         return found;
 758 }
 759
 760 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 761                         struct dpll *best_clock)
 762 {
 763         int refclk = 100000;
 764         const struct intel_limit *limit = &intel_limits_bxt;
 765
 766         return chv_find_best_dpll(limit, crtc_state,
 767                                   crtc_state->port_clock, refclk,
 768                                   NULL, best_clock);
 769 }
 770
 771 u32 i9xx_dpll_compute_fp(const struct dpll *dpll)
 772 {
 773         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
 774 }
 775
 776 static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
 777 {
 778         return (1 << dpll->n) << 16 | dpll->m2;
 779 }
 780
 781 static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state,
 782                                      const struct dpll *clock,
 783                                      const struct dpll *reduced_clock)
 784 {
 785         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 786         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 787         u32 fp, fp2;
 788
 789         if (IS_PINEVIEW(dev_priv)) {
 790                 fp = pnv_dpll_compute_fp(clock);
 791                 fp2 = pnv_dpll_compute_fp(reduced_clock);
 792         } else {
 793                 fp = i9xx_dpll_compute_fp(clock);
 794                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
 795         }
 796
 797         crtc_state->dpll_hw_state.fp0 = fp;
 798         crtc_state->dpll_hw_state.fp1 = fp2;
 799 }
 800
 801 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
 802                               const struct dpll *clock,
 803                               const struct dpll *reduced_clock)
 804 {
 805         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 806         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 807         u32 dpll;
 808
 809         i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
 810
 811         dpll = DPLL_VGA_MODE_DIS;
 812
 813         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
 814                 dpll |= DPLLB_MODE_LVDS;
 815         else
 816                 dpll |= DPLLB_MODE_DAC_SERIAL;
 817
 818         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 819             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
 820                 dpll |= (crtc_state->pixel_multiplier - 1)
 821                         << SDVO_MULTIPLIER_SHIFT_HIRES;
 822         }
 823
 824         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
 825             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 826                 dpll |= DPLL_SDVO_HIGH_SPEED;
 827
 828         if (intel_crtc_has_dp_encoder(crtc_state))
 829                 dpll |= DPLL_SDVO_HIGH_SPEED;
 830
 831         /* compute bitmask from p1 value */
 832         if (IS_G4X(dev_priv)) {
 833                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 834                 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 835         } else if (IS_PINEVIEW(dev_priv)) {
 836                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
 837                 WARN_ON(reduced_clock->p1 != clock->p1);
 838         } else {
 839                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 840                 WARN_ON(reduced_clock->p1 != clock->p1);
 841         }
 842
 843         switch (clock->p2) {
 844         case 5:
 845                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 846                 break;
 847         case 7:
 848                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
 849                 break;
 850         case 10:
 851                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
 852                 break;
 853         case 14:
 854                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 855                 break;
 856         }
 857         WARN_ON(reduced_clock->p2 != clock->p2);
 858
 859         if (DISPLAY_VER(dev_priv) >= 4)
 860                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 861
 862         if (crtc_state->sdvo_tv_clock)
 863                 dpll |= PLL_REF_INPUT_TVCLKINBC;
 864         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 865                  intel_panel_use_ssc(dev_priv))
 866                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 867         else
 868                 dpll |= PLL_REF_INPUT_DREFCLK;
 869
 870         dpll |= DPLL_VCO_ENABLE;
 871         crtc_state->dpll_hw_state.dpll = dpll;
 872
 873         if (DISPLAY_VER(dev_priv) >= 4) {
 874                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
 875                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 876                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
 877         }
 878 }
 879
 880 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
 881                               const struct dpll *clock,
 882                               const struct dpll *reduced_clock)
 883 {
 884         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 885         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 886         u32 dpll;
 887
 888         i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
 889
 890         dpll = DPLL_VGA_MODE_DIS;
 891
 892         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 893                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 894         } else {
 895                 if (clock->p1 == 2)
 896                         dpll |= PLL_P1_DIVIDE_BY_TWO;
 897                 else
 898                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 899                 if (clock->p2 == 4)
 900                         dpll |= PLL_P2_DIVIDE_BY_4;
 901         }
 902         WARN_ON(reduced_clock->p1 != clock->p1);
 903         WARN_ON(reduced_clock->p2 != clock->p2);
 904
 905         /*
 906          * Bspec:
 907          * "[Almador Errata}: For the correct operation of the muxed DVO pins
 908          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
 909          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
 910          *  Enable) must be set to “1” in both the DPLL A Control Register
 911          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
 912          *
 913          * For simplicity We simply keep both bits always enabled in
 914          * both DPLLS. The spec says we should disable the DVO 2X clock
 915          * when not needed, but this seems to work fine in practice.
 916          */
 917         if (IS_I830(dev_priv) ||
 918             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
 919                 dpll |= DPLL_DVO_2X_MODE;
 920
 921         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 922             intel_panel_use_ssc(dev_priv))
 923                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 924         else
 925                 dpll |= PLL_REF_INPUT_DREFCLK;
 926
 927         dpll |= DPLL_VCO_ENABLE;
 928         crtc_state->dpll_hw_state.dpll = dpll;
 929 }
 930
 931 static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state)
 932 {
 933         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 934         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 935         struct intel_atomic_state *state =
 936                 to_intel_atomic_state(crtc_state->uapi.state);
 937         struct intel_encoder *encoder =
 938                 intel_get_crtc_new_encoder(state, crtc_state);
 939
 940         if (IS_DG2(dev_priv))
 941                 return intel_mpllb_calc_state(crtc_state, encoder);
 942
 943         if (DISPLAY_VER(dev_priv) < 11 &&
 944             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 945                 return 0;
 946
 947         if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
 948                 drm_dbg_kms(&dev_priv->drm,
 949                             "failed to find PLL for pipe %c\n",
 950                             pipe_name(crtc->pipe));
 951                 return -EINVAL;
 952         }
 953
 954         return 0;
 955 }
 956
 957 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
 958 {
 959         return dpll->m < factor * dpll->n;
 960 }
 961
 962 static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
 963                                     const struct dpll *clock,
 964                                     const struct dpll *reduced_clock)
 965 {
 966         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 967         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 968         u32 fp, fp2;
 969         int factor;
 970
 971         /* Enable autotuning of the PLL clock (if permissible) */
 972         factor = 21;
 973         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 974                 if ((intel_panel_use_ssc(dev_priv) &&
 975                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
 976                     (HAS_PCH_IBX(dev_priv) &&
 977                      intel_is_dual_link_lvds(dev_priv)))
 978                         factor = 25;
 979         } else if (crtc_state->sdvo_tv_clock) {
 980                 factor = 20;
 981         }
 982
 983         fp = i9xx_dpll_compute_fp(clock);
 984         if (ilk_needs_fb_cb_tune(clock, factor))
 985                 fp |= FP_CB_TUNE;
 986
 987         fp2 = i9xx_dpll_compute_fp(reduced_clock);
 988         if (ilk_needs_fb_cb_tune(reduced_clock, factor))
 989                 fp2 |= FP_CB_TUNE;
 990
 991         crtc_state->dpll_hw_state.fp0 = fp;
 992         crtc_state->dpll_hw_state.fp1 = fp2;
 993 }
 994
 995 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
 996                              const struct dpll *clock,
 997                              const struct dpll *reduced_clock)
 998 {
 999         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1000         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1001         u32 dpll;
1002
1003         ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
1004
1005         dpll = 0;
1006
1007         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
1008                 dpll |= DPLLB_MODE_LVDS;
1009         else
1010                 dpll |= DPLLB_MODE_DAC_SERIAL;
1011
1012         dpll |= (crtc_state->pixel_multiplier - 1)
1013                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1014
1015         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
1016             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1017                 dpll |= DPLL_SDVO_HIGH_SPEED;
1018
1019         if (intel_crtc_has_dp_encoder(crtc_state))
1020                 dpll |= DPLL_SDVO_HIGH_SPEED;
1021
1022         /*
1023          * The high speed IO clock is only really required for
1024          * SDVO/HDMI/DP, but we also enable it for CRT to make it
1025          * possible to share the DPLL between CRT and HDMI. Enabling
1026          * the clock needlessly does no real harm, except use up a
1027          * bit of power potentially.
1028          *
1029          * We'll limit this to IVB with 3 pipes, since it has only two
1030          * DPLLs and so DPLL sharing is the only way to get three pipes
1031          * driving PCH ports at the same time. On SNB we could do this,
1032          * and potentially avoid enabling the second DPLL, but it's not
1033          * clear if it''s a win or loss power wise. No point in doing
1034          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
1035          */
1036         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
1037             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1038                 dpll |= DPLL_SDVO_HIGH_SPEED;
1039
1040         /* compute bitmask from p1 value */
1041         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1042         /* also FPA1 */
1043         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1044
1045         switch (clock->p2) {
1046         case 5:
1047                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1048                 break;
1049         case 7:
1050                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1051                 break;
1052         case 10:
1053                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1054                 break;
1055         case 14:
1056                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1057                 break;
1058         }
1059         WARN_ON(reduced_clock->p2 != clock->p2);
1060
1061         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1062             intel_panel_use_ssc(dev_priv))
1063                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1064         else
1065                 dpll |= PLL_REF_INPUT_DREFCLK;
1066
1067         dpll |= DPLL_VCO_ENABLE;
1068
1069         crtc_state->dpll_hw_state.dpll = dpll;
1070 }
1071
1072 static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state)
1073 {
1074         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1075         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1076         struct intel_atomic_state *state =
1077                 to_intel_atomic_state(crtc_state->uapi.state);
1078         const struct intel_limit *limit;
1079         int refclk = 120000;
1080
1081         memset(&crtc_state->dpll_hw_state, 0,
1082                sizeof(crtc_state->dpll_hw_state));
1083
1084         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1085         if (!crtc_state->has_pch_encoder)
1086                 return 0;
1087
1088         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1089                 if (intel_panel_use_ssc(dev_priv)) {
1090                         drm_dbg_kms(&dev_priv->drm,
1091                                     "using SSC reference clock of %d kHz\n",
1092                                     dev_priv->vbt.lvds_ssc_freq);
1093                         refclk = dev_priv->vbt.lvds_ssc_freq;
1094                 }
1095
1096                 if (intel_is_dual_link_lvds(dev_priv)) {
1097                         if (refclk == 100000)
1098                                 limit = &ilk_limits_dual_lvds_100m;
1099                         else
1100                                 limit = &ilk_limits_dual_lvds;
1101                 } else {
1102                         if (refclk == 100000)
1103                                 limit = &ilk_limits_single_lvds_100m;
1104                         else
1105                                 limit = &ilk_limits_single_lvds;
1106                 }
1107         } else {
1108                 limit = &ilk_limits_dac;
1109         }
1110
1111         if (!crtc_state->clock_set &&
1112             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1113                                 refclk, NULL, &crtc_state->dpll)) {
1114                 drm_err(&dev_priv->drm,
1115                         "Couldn't find PLL settings for mode!\n");
1116                 return -EINVAL;
1117         }
1118
1119         ilk_compute_dpll(crtc_state, &crtc_state->dpll,
1120                          &crtc_state->dpll);
1121
1122         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
1123                 drm_dbg_kms(&dev_priv->drm,
1124                             "failed to find PLL for pipe %c\n",
1125                             pipe_name(crtc->pipe));
1126                 return -EINVAL;
1127         }
1128
1129         return 0;
1130 }
1131
1132 void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
1133 {
1134         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1135
1136         crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
1137                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1138         if (crtc->pipe != PIPE_A)
1139                 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1140
1141         /* DPLL not used with DSI, but still need the rest set up */
1142         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1143                 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
1144                         DPLL_EXT_BUFFER_ENABLE_VLV;
1145
1146         crtc_state->dpll_hw_state.dpll_md =
1147                 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1148 }
1149
1150 void chv_compute_dpll(struct intel_crtc_state *crtc_state)
1151 {
1152         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1153
1154         crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
1155                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1156         if (crtc->pipe != PIPE_A)
1157                 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1158
1159         /* DPLL not used with DSI, but still need the rest set up */
1160         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1161                 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
1162
1163         crtc_state->dpll_hw_state.dpll_md =
1164                 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1165 }
1166
1167 static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
1168 {
1169         int refclk = 100000;
1170         const struct intel_limit *limit = &intel_limits_chv;
1171         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1172
1173         memset(&crtc_state->dpll_hw_state, 0,
1174                sizeof(crtc_state->dpll_hw_state));
1175
1176         if (!crtc_state->clock_set &&
1177             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1178                                 refclk, NULL, &crtc_state->dpll)) {
1179                 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
1180                 return -EINVAL;
1181         }
1182
1183         chv_compute_dpll(crtc_state);
1184
1185         return 0;
1186 }
1187
1188 static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
1189 {
1190         int refclk = 100000;
1191         const struct intel_limit *limit = &intel_limits_vlv;
1192         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1193
1194         memset(&crtc_state->dpll_hw_state, 0,
1195                sizeof(crtc_state->dpll_hw_state));
1196
1197         if (!crtc_state->clock_set &&
1198             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1199                                 refclk, NULL, &crtc_state->dpll)) {
1200                 drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
1201                 return -EINVAL;
1202         }
1203
1204         vlv_compute_dpll(crtc_state);
1205
1206         return 0;
1207 }
1208
1209 static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state)
1210 {
1211         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1212         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1213         const struct intel_limit *limit;
1214         int refclk = 96000;
1215
1216         memset(&crtc_state->dpll_hw_state, 0,
1217                sizeof(crtc_state->dpll_hw_state));
1218
1219         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1220                 if (intel_panel_use_ssc(dev_priv)) {
1221                         refclk = dev_priv->vbt.lvds_ssc_freq;
1222                         drm_dbg_kms(&dev_priv->drm,
1223                                     "using SSC reference clock of %d kHz\n",
1224                                     refclk);
1225                 }
1226
1227                 if (intel_is_dual_link_lvds(dev_priv))
1228                         limit = &intel_limits_g4x_dual_channel_lvds;
1229                 else
1230                         limit = &intel_limits_g4x_single_channel_lvds;
1231         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
1232                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1233                 limit = &intel_limits_g4x_hdmi;
1234         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
1235                 limit = &intel_limits_g4x_sdvo;
1236         } else {
1237                 /* The option is for other outputs */
1238                 limit = &intel_limits_i9xx_sdvo;
1239         }
1240
1241         if (!crtc_state->clock_set &&
1242             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1243                                 refclk, NULL, &crtc_state->dpll)) {
1244                 drm_err(&dev_priv->drm,
1245                         "Couldn't find PLL settings for mode!\n");
1246                 return -EINVAL;
1247         }
1248
1249         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1250                           &crtc_state->dpll);
1251
1252         return 0;
1253 }
1254
1255 static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state)
1256 {
1257         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1258         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1259         const struct intel_limit *limit;
1260         int refclk = 96000;
1261
1262         memset(&crtc_state->dpll_hw_state, 0,
1263                sizeof(crtc_state->dpll_hw_state));
1264
1265         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1266                 if (intel_panel_use_ssc(dev_priv)) {
1267                         refclk = dev_priv->vbt.lvds_ssc_freq;
1268                         drm_dbg_kms(&dev_priv->drm,
1269                                     "using SSC reference clock of %d kHz\n",
1270                                     refclk);
1271                 }
1272
1273                 limit = &pnv_limits_lvds;
1274         } else {
1275                 limit = &pnv_limits_sdvo;
1276         }
1277
1278         if (!crtc_state->clock_set &&
1279             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1280                                 refclk, NULL, &crtc_state->dpll)) {
1281                 drm_err(&dev_priv->drm,
1282                         "Couldn't find PLL settings for mode!\n");
1283                 return -EINVAL;
1284         }
1285
1286         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1287                           &crtc_state->dpll);
1288
1289         return 0;
1290 }
1291
1292 static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
1293 {
1294         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1295         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1296         const struct intel_limit *limit;
1297         int refclk = 96000;
1298
1299         memset(&crtc_state->dpll_hw_state, 0,
1300                sizeof(crtc_state->dpll_hw_state));
1301
1302         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1303                 if (intel_panel_use_ssc(dev_priv)) {
1304                         refclk = dev_priv->vbt.lvds_ssc_freq;
1305                         drm_dbg_kms(&dev_priv->drm,
1306                                     "using SSC reference clock of %d kHz\n",
1307                                     refclk);
1308                 }
1309
1310                 limit = &intel_limits_i9xx_lvds;
1311         } else {
1312                 limit = &intel_limits_i9xx_sdvo;
1313         }
1314
1315         if (!crtc_state->clock_set &&
1316             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1317                                  refclk, NULL, &crtc_state->dpll)) {
1318                 drm_err(&dev_priv->drm,
1319                         "Couldn't find PLL settings for mode!\n");
1320                 return -EINVAL;
1321         }
1322
1323         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1324                           &crtc_state->dpll);
1325
1326         return 0;
1327 }
1328
1329 static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
1330 {
1331         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1332         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1333         const struct intel_limit *limit;
1334         int refclk = 48000;
1335
1336         memset(&crtc_state->dpll_hw_state, 0,
1337                sizeof(crtc_state->dpll_hw_state));
1338
1339         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1340                 if (intel_panel_use_ssc(dev_priv)) {
1341                         refclk = dev_priv->vbt.lvds_ssc_freq;
1342                         drm_dbg_kms(&dev_priv->drm,
1343                                     "using SSC reference clock of %d kHz\n",
1344                                     refclk);
1345                 }
1346
1347                 limit = &intel_limits_i8xx_lvds;
1348         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
1349                 limit = &intel_limits_i8xx_dvo;
1350         } else {
1351                 limit = &intel_limits_i8xx_dac;
1352         }
1353
1354         if (!crtc_state->clock_set &&
1355             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1356                                  refclk, NULL, &crtc_state->dpll)) {
1357                 drm_err(&dev_priv->drm,
1358                         "Couldn't find PLL settings for mode!\n");
1359                 return -EINVAL;
1360         }
1361
1362         i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
1363                           &crtc_state->dpll);
1364
1365         return 0;
1366 }
1367
1368 static const struct intel_dpll_funcs hsw_dpll_funcs = {
1369         .crtc_compute_clock = hsw_crtc_compute_clock,
1370 };
1371
1372 static const struct intel_dpll_funcs ilk_dpll_funcs = {
1373         .crtc_compute_clock = ilk_crtc_compute_clock,
1374 };
1375
1376 static const struct intel_dpll_funcs chv_dpll_funcs = {
1377         .crtc_compute_clock = chv_crtc_compute_clock,
1378 };
1379
1380 static const struct intel_dpll_funcs vlv_dpll_funcs = {
1381         .crtc_compute_clock = vlv_crtc_compute_clock,
1382 };
1383
1384 static const struct intel_dpll_funcs g4x_dpll_funcs = {
1385         .crtc_compute_clock = g4x_crtc_compute_clock,
1386 };
1387
1388 static const struct intel_dpll_funcs pnv_dpll_funcs = {
1389         .crtc_compute_clock = pnv_crtc_compute_clock,
1390 };
1391
1392 static const struct intel_dpll_funcs i9xx_dpll_funcs = {
1393         .crtc_compute_clock = i9xx_crtc_compute_clock,
1394 };
1395
1396 static const struct intel_dpll_funcs i8xx_dpll_funcs = {
1397         .crtc_compute_clock = i8xx_crtc_compute_clock,
1398 };
1399
1400 void
1401 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
1402 {
1403         if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
1404                 dev_priv->dpll_funcs = &hsw_dpll_funcs;
1405         else if (HAS_PCH_SPLIT(dev_priv))
1406                 dev_priv->dpll_funcs = &ilk_dpll_funcs;
1407         else if (IS_CHERRYVIEW(dev_priv))
1408                 dev_priv->dpll_funcs = &chv_dpll_funcs;
1409         else if (IS_VALLEYVIEW(dev_priv))
1410                 dev_priv->dpll_funcs = &vlv_dpll_funcs;
1411         else if (IS_G4X(dev_priv))
1412                 dev_priv->dpll_funcs = &g4x_dpll_funcs;
1413         else if (IS_PINEVIEW(dev_priv))
1414                 dev_priv->dpll_funcs = &pnv_dpll_funcs;
1415         else if (DISPLAY_VER(dev_priv) != 2)
1416                 dev_priv->dpll_funcs = &i9xx_dpll_funcs;
1417         else
1418                 dev_priv->dpll_funcs = &i8xx_dpll_funcs;
1419 }
1420
1421 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1422 {
1423         if (IS_I830(dev_priv))
1424                 return false;
1425
1426         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1427 }
1428
1429 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
1430 {
1431         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1432         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1433         u32 dpll = crtc_state->dpll_hw_state.dpll;
1434         enum pipe pipe = crtc->pipe;
1435         int i;
1436
1437         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1438
1439         /* PLL is protected by panel, make sure we can write it */
1440         if (i9xx_has_pps(dev_priv))
1441                 assert_panel_unlocked(dev_priv, pipe);
1442
1443         intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
1444         intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
1445
1446         /*
1447          * Apparently we need to have VGA mode enabled prior to changing
1448          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1449          * dividers, even though the register value does change.
1450          */
1451         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
1452         intel_de_write(dev_priv, DPLL(pipe), dpll);
1453
1454         /* Wait for the clocks to stabilize. */
1455         intel_de_posting_read(dev_priv, DPLL(pipe));
1456         udelay(150);
1457
1458         if (DISPLAY_VER(dev_priv) >= 4) {
1459                 intel_de_write(dev_priv, DPLL_MD(pipe),
1460                                crtc_state->dpll_hw_state.dpll_md);
1461         } else {
1462                 /* The pixel multiplier can only be updated once the
1463                  * DPLL is enabled and the clocks are stable.
1464                  *
1465                  * So write it again.
1466                  */
1467                 intel_de_write(dev_priv, DPLL(pipe), dpll);
1468         }
1469
1470         /* We do this three times for luck */
1471         for (i = 0; i < 3; i++) {
1472                 intel_de_write(dev_priv, DPLL(pipe), dpll);
1473                 intel_de_posting_read(dev_priv, DPLL(pipe));
1474                 udelay(150); /* wait for warmup */
1475         }
1476 }
1477
1478 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
1479                                  enum pipe pipe)
1480 {
1481         u32 reg_val;
1482
1483         /*
1484          * PLLB opamp always calibrates to max value of 0x3f, force enable it
1485          * and set it to a reasonable value instead.
1486          */
1487         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
1488         reg_val &= 0xffffff00;
1489         reg_val |= 0x00000030;
1490         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
1491
1492         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
1493         reg_val &= 0x00ffffff;
1494         reg_val |= 0x8c000000;
1495         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
1496
1497         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
1498         reg_val &= 0xffffff00;
1499         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
1500
1501         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
1502         reg_val &= 0x00ffffff;
1503         reg_val |= 0xb0000000;
1504         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
1505 }
1506
1507 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
1508 {
1509         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1510         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1511         enum pipe pipe = crtc->pipe;
1512         u32 mdiv;
1513         u32 bestn, bestm1, bestm2, bestp1, bestp2;
1514         u32 coreclk, reg_val;
1515
1516         vlv_dpio_get(dev_priv);
1517
1518         bestn = crtc_state->dpll.n;
1519         bestm1 = crtc_state->dpll.m1;
1520         bestm2 = crtc_state->dpll.m2;
1521         bestp1 = crtc_state->dpll.p1;
1522         bestp2 = crtc_state->dpll.p2;
1523
1524         /* See eDP HDMI DPIO driver vbios notes doc */
1525
1526         /* PLL B needs special handling */
1527         if (pipe == PIPE_B)
1528                 vlv_pllb_recal_opamp(dev_priv, pipe);
1529
1530         /* Set up Tx target for periodic Rcomp update */
1531         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
1532
1533         /* Disable target IRef on PLL */
1534         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
1535         reg_val &= 0x00ffffff;
1536         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
1537
1538         /* Disable fast lock */
1539         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
1540
1541         /* Set idtafcrecal before PLL is enabled */
1542         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
1543         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
1544         mdiv |= ((bestn << DPIO_N_SHIFT));
1545         mdiv |= (1 << DPIO_K_SHIFT);
1546
1547         /*
1548          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
1549          * but we don't support that).
1550          * Note: don't use the DAC post divider as it seems unstable.
1551          */
1552         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
1553         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
1554
1555         mdiv |= DPIO_ENABLE_CALIBRATION;
1556         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
1557
1558         /* Set HBR and RBR LPF coefficients */
1559         if (crtc_state->port_clock == 162000 ||
1560             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
1561             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1562                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
1563                                  0x009f0003);
1564         else
1565                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
1566                                  0x00d0000f);
1567
1568         if (intel_crtc_has_dp_encoder(crtc_state)) {
1569                 /* Use SSC source */
1570                 if (pipe == PIPE_A)
1571                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1572                                          0x0df40000);
1573                 else
1574                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1575                                          0x0df70000);
1576         } else { /* HDMI or VGA */
1577                 /* Use bend source */
1578                 if (pipe == PIPE_A)
1579                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1580                                          0x0df70000);
1581                 else
1582                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1583                                          0x0df40000);
1584         }
1585
1586         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
1587         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
1588         if (intel_crtc_has_dp_encoder(crtc_state))
1589                 coreclk |= 0x01000000;
1590         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
1591
1592         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
1593
1594         vlv_dpio_put(dev_priv);
1595 }
1596
1597 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1598 {
1599         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1600         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1601         enum pipe pipe = crtc->pipe;
1602
1603         intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);
1604         intel_de_posting_read(dev_priv, DPLL(pipe));
1605         udelay(150);
1606
1607         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1608                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1609 }
1610
1611 void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1612 {
1613         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1614         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1615         enum pipe pipe = crtc->pipe;
1616
1617         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1618
1619         /* PLL is protected by panel, make sure we can write it */
1620         assert_panel_unlocked(dev_priv, pipe);
1621
1622         /* Enable Refclk */
1623         intel_de_write(dev_priv, DPLL(pipe),
1624                        crtc_state->dpll_hw_state.dpll &
1625                        ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
1626
1627         if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {
1628                 vlv_prepare_pll(crtc_state);
1629                 _vlv_enable_pll(crtc_state);
1630         }
1631
1632         intel_de_write(dev_priv, DPLL_MD(pipe),
1633                        crtc_state->dpll_hw_state.dpll_md);
1634         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1635 }
1636
1637 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
1638 {
1639         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1640         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1641         enum pipe pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 loopfilter, tribuf_calcntr;
1644         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
1645         u32 dpio_val;
1646         int vco;
1647
1648         bestn = crtc_state->dpll.n;
1649         bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;
1650         bestm1 = crtc_state->dpll.m1;
1651         bestm2 = crtc_state->dpll.m2 >> 22;
1652         bestp1 = crtc_state->dpll.p1;
1653         bestp2 = crtc_state->dpll.p2;
1654         vco = crtc_state->dpll.vco;
1655         dpio_val = 0;
1656         loopfilter = 0;
1657
1658         vlv_dpio_get(dev_priv);
1659
1660         /* p1 and p2 divider */
1661         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
1662                         5 << DPIO_CHV_S1_DIV_SHIFT |
1663                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
1664                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
1665                         1 << DPIO_CHV_K_DIV_SHIFT);
1666
1667         /* Feedback post-divider - m2 */
1668         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
1669
1670         /* Feedback refclk divider - n and m1 */
1671         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
1672                         DPIO_CHV_M1_DIV_BY_2 |
1673                         1 << DPIO_CHV_N_DIV_SHIFT);
1674
1675         /* M2 fraction division */
1676         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
1677
1678         /* M2 fraction division enable */
1679         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
1680         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
1681         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
1682         if (bestm2_frac)
1683                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
1684         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
1685
1686         /* Program digital lock detect threshold */
1687         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
1688         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
1689                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
1690         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
1691         if (!bestm2_frac)
1692                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
1693         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
1694
1695         /* Loop filter */
1696         if (vco == 5400000) {
1697                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
1698                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
1699                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
1700                 tribuf_calcntr = 0x9;
1701         } else if (vco <= 6200000) {
1702                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
1703                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
1704                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1705                 tribuf_calcntr = 0x9;
1706         } else if (vco <= 6480000) {
1707                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
1708                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
1709                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1710                 tribuf_calcntr = 0x8;
1711         } else {
1712                 /* Not supported. Apply the same limits as in the max case */
1713                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
1714                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
1715                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1716                 tribuf_calcntr = 0;
1717         }
1718         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
1719
1720         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
1721         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
1722         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
1723         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
1724
1725         /* AFC Recal */
1726         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
1727                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
1728                         DPIO_AFC_RECAL);
1729
1730         vlv_dpio_put(dev_priv);
1731 }
1732
1733 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
1734 {
1735         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1736         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1737         enum pipe pipe = crtc->pipe;
1738         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1739         u32 tmp;
1740
1741         vlv_dpio_get(dev_priv);
1742
1743         /* Enable back the 10bit clock to display controller */
1744         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1745         tmp |= DPIO_DCLKP_EN;
1746         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1747
1748         vlv_dpio_put(dev_priv);
1749
1750         /*
1751          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1752          */
1753         udelay(1);
1754
1755         /* Enable PLL */
1756         intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);
1757
1758         /* Check PLL is locked */
1759         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1760                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1761 }
1762
1763 void chv_enable_pll(const struct intel_crtc_state *crtc_state)
1764 {
1765         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1766         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1767         enum pipe pipe = crtc->pipe;
1768
1769         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1770
1771         /* PLL is protected by panel, make sure we can write it */
1772         assert_panel_unlocked(dev_priv, pipe);
1773
1774         /* Enable Refclk and SSC */
1775         intel_de_write(dev_priv, DPLL(pipe),
1776                        crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
1777
1778         if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {
1779                 chv_prepare_pll(crtc_state);
1780                 _chv_enable_pll(crtc_state);
1781         }
1782
1783         if (pipe != PIPE_A) {
1784                 /*
1785                  * WaPixelRepeatModeFixForC0:chv
1786                  *
1787                  * DPLLCMD is AWOL. Use chicken bits to propagate
1788                  * the value from DPLLBMD to either pipe B or C.
1789                  */
1790                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1791                 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1792                                crtc_state->dpll_hw_state.dpll_md);
1793                 intel_de_write(dev_priv, CBR4_VLV, 0);
1794                 dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
1795
1796                 /*
1797                  * DPLLB VGA mode also seems to cause problems.
1798                  * We should always have it disabled.
1799                  */
1800                 drm_WARN_ON(&dev_priv->drm,
1801                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1802                              DPLL_VGA_MODE_DIS) == 0);
1803         } else {
1804                 intel_de_write(dev_priv, DPLL_MD(pipe),
1805                                crtc_state->dpll_hw_state.dpll_md);
1806                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1807         }
1808 }
1809
1810 /**
1811  * vlv_force_pll_on - forcibly enable just the PLL
1812  * @dev_priv: i915 private structure
1813  * @pipe: pipe PLL to enable
1814  * @dpll: PLL configuration
1815  *
1816  * Enable the PLL for @pipe using the supplied @dpll config. To be used
1817  * in cases where we need the PLL enabled even when @pipe is not going to
1818  * be enabled.
1819  */
1820 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1821                      const struct dpll *dpll)
1822 {
1823         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1824         struct intel_crtc_state *crtc_state;
1825
1826         crtc_state = intel_crtc_state_alloc(crtc);
1827         if (!crtc_state)
1828                 return -ENOMEM;
1829
1830         crtc_state->cpu_transcoder = (enum transcoder)pipe;
1831         crtc_state->pixel_multiplier = 1;
1832         crtc_state->dpll = *dpll;
1833         crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);
1834
1835         if (IS_CHERRYVIEW(dev_priv)) {
1836                 chv_compute_dpll(crtc_state);
1837                 chv_enable_pll(crtc_state);
1838         } else {
1839                 vlv_compute_dpll(crtc_state);
1840                 vlv_enable_pll(crtc_state);
1841         }
1842
1843         kfree(crtc_state);
1844
1845         return 0;
1846 }
1847
1848 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1849 {
1850         u32 val;
1851
1852         /* Make sure the pipe isn't still relying on us */
1853         assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
1854
1855         val = DPLL_INTEGRATED_REF_CLK_VLV |
1856                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1857         if (pipe != PIPE_A)
1858                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1859
1860         intel_de_write(dev_priv, DPLL(pipe), val);
1861         intel_de_posting_read(dev_priv, DPLL(pipe));
1862 }
1863
1864 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1865 {
1866         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1867         u32 val;
1868
1869         /* Make sure the pipe isn't still relying on us */
1870         assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
1871
1872         val = DPLL_SSC_REF_CLK_CHV |
1873                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1874         if (pipe != PIPE_A)
1875                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1876
1877         intel_de_write(dev_priv, DPLL(pipe), val);
1878         intel_de_posting_read(dev_priv, DPLL(pipe));
1879
1880         vlv_dpio_get(dev_priv);
1881
1882         /* Disable 10bit clock to display controller */
1883         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1884         val &= ~DPIO_DCLKP_EN;
1885         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1886
1887         vlv_dpio_put(dev_priv);
1888 }
1889
1890 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1891 {
1892         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1893         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1894         enum pipe pipe = crtc->pipe;
1895
1896         /* Don't disable pipe or pipe PLLs if needed */
1897         if (IS_I830(dev_priv))
1898                 return;
1899
1900         /* Make sure the pipe isn't still relying on us */
1901         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1902
1903         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1904         intel_de_posting_read(dev_priv, DPLL(pipe));
1905 }
1906
1907
1908 /**
1909  * vlv_force_pll_off - forcibly disable just the PLL
1910  * @dev_priv: i915 private structure
1911  * @pipe: pipe PLL to disable
1912  *
1913  * Disable the PLL for @pipe. To be used in cases where we need
1914  * the PLL enabled even when @pipe is not going to be enabled.
1915  */
1916 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
1917 {
1918         if (IS_CHERRYVIEW(dev_priv))
1919                 chv_disable_pll(dev_priv, pipe);
1920         else
1921                 vlv_disable_pll(dev_priv, pipe);
1922 }