2 * Copyright © 2008 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <drm/drm_atomic.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_edid.h>
29 #include <drm/drm_probe_helper.h>
33 #include "intel_atomic.h"
34 #include "intel_audio.h"
35 #include "intel_connector.h"
36 #include "intel_crtc.h"
37 #include "intel_ddi.h"
39 #include "intel_display_types.h"
41 #include "intel_dp_hdcp.h"
42 #include "intel_dp_mst.h"
43 #include "intel_dpio_phy.h"
44 #include "intel_hdcp.h"
45 #include "intel_hotplug.h"
46 #include "skl_scaler.h"
48 static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
49 const struct drm_display_mode *adjusted_mode,
50 struct intel_crtc_state *crtc_state,
53 if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) {
55 /* DisplayPort 2 128b/132b, bits per lane is always 32 */
56 int symbol_clock = crtc_state->port_clock / 32;
58 if (output_bpp * adjusted_mode->crtc_clock >=
60 drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n",
61 output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);
69 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
70 struct intel_crtc_state *crtc_state,
73 struct link_config_limits *limits,
74 struct drm_connector_state *conn_state,
78 struct drm_atomic_state *state = crtc_state->uapi.state;
79 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
80 struct intel_dp *intel_dp = &intel_mst->primary->dp;
81 struct drm_dp_mst_topology_state *mst_state;
82 struct intel_connector *connector =
83 to_intel_connector(conn_state->connector);
84 struct drm_i915_private *i915 = to_i915(connector->base.dev);
85 const struct drm_display_mode *adjusted_mode =
86 &crtc_state->hw.adjusted_mode;
87 int bpp, slots = -EINVAL;
90 mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
91 if (IS_ERR(mst_state))
92 return PTR_ERR(mst_state);
94 crtc_state->lane_count = limits->max_lane_count;
95 crtc_state->port_clock = limits->max_rate;
97 // TODO: Handle pbn_div changes by adding a new MST helper
98 if (!mst_state->pbn_div) {
99 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
100 crtc_state->port_clock,
101 crtc_state->lane_count);
104 for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
105 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
107 ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
111 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
112 dsc ? bpp << 4 : bpp,
115 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
118 if (slots == -EDEADLK)
122 ret = drm_dp_mst_atomic_check(state);
124 * If we got slots >= 0 and we can fit those based on check
125 * then we can exit the loop. Otherwise keep trying.
132 /* We failed to find a proper bpp/timeslots, return error */
137 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
141 crtc_state->pipe_bpp = bpp;
143 crtc_state->dsc.compressed_bpp = bpp;
144 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
150 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
151 struct intel_crtc_state *crtc_state,
152 struct drm_connector_state *conn_state,
153 struct link_config_limits *limits)
155 const struct drm_display_mode *adjusted_mode =
156 &crtc_state->hw.adjusted_mode;
159 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
160 limits->min_bpp, limits,
161 conn_state, 2 * 3, false);
166 intel_link_compute_m_n(crtc_state->pipe_bpp,
167 crtc_state->lane_count,
168 adjusted_mode->crtc_clock,
169 crtc_state->port_clock,
171 crtc_state->fec_enable);
172 crtc_state->dp_m_n.tu = slots;
177 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
178 struct intel_crtc_state *crtc_state,
179 struct drm_connector_state *conn_state,
180 struct link_config_limits *limits)
182 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
183 struct intel_dp *intel_dp = &intel_mst->primary->dp;
184 struct intel_connector *connector =
185 to_intel_connector(conn_state->connector);
186 struct drm_i915_private *i915 = to_i915(connector->base.dev);
187 const struct drm_display_mode *adjusted_mode =
188 &crtc_state->hw.adjusted_mode;
192 int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
194 bool need_timeslot_recalc = false;
195 u32 last_compressed_bpp;
197 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
198 if (DISPLAY_VER(i915) >= 12)
199 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
201 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
203 max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
204 min_bpp = limits->min_bpp;
206 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
209 drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
212 sink_max_bpp = dsc_bpc[0] * 3;
213 sink_min_bpp = sink_max_bpp;
215 for (i = 1; i < num_bpc; i++) {
216 if (sink_min_bpp > dsc_bpc[i] * 3)
217 sink_min_bpp = dsc_bpc[i] * 3;
218 if (sink_max_bpp < dsc_bpc[i] * 3)
219 sink_max_bpp = dsc_bpc[i] * 3;
222 drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
223 sink_min_bpp, sink_max_bpp);
225 if (min_bpp < sink_min_bpp)
226 min_bpp = sink_min_bpp;
228 if (max_bpp > sink_max_bpp)
229 max_bpp = sink_max_bpp;
231 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
233 conn_state, 2 * 3, true);
238 last_compressed_bpp = crtc_state->dsc.compressed_bpp;
240 crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
242 crtc_state->pipe_bpp);
244 if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
245 need_timeslot_recalc = true;
248 * Apparently some MST hubs dislike if vcpi slots are not matching precisely
249 * the actual compressed bpp we use.
251 if (need_timeslot_recalc) {
252 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
253 crtc_state->dsc.compressed_bpp,
254 crtc_state->dsc.compressed_bpp,
255 limits, conn_state, 2 * 3, true);
260 intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
261 crtc_state->lane_count,
262 adjusted_mode->crtc_clock,
263 crtc_state->port_clock,
265 crtc_state->fec_enable);
266 crtc_state->dp_m_n.tu = slots;
270 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
271 struct intel_crtc_state *crtc_state,
272 struct drm_connector_state *conn_state)
274 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
275 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
276 struct intel_dp *intel_dp = &intel_mst->primary->dp;
277 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
278 struct drm_dp_mst_topology_state *topology_state;
279 u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
280 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
282 topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
283 if (IS_ERR(topology_state)) {
284 drm_dbg_kms(&i915->drm, "slot update failed\n");
285 return PTR_ERR(topology_state);
288 drm_dp_mst_update_slots(topology_state, link_coding_cap);
293 static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
295 const struct intel_digital_connector_state *intel_conn_state =
296 to_intel_digital_connector_state(conn_state);
297 struct intel_connector *connector =
298 to_intel_connector(conn_state->connector);
300 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
301 return connector->base.display_info.has_audio;
303 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
306 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
307 struct intel_crtc_state *pipe_config,
308 struct drm_connector_state *conn_state)
310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
311 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
312 struct intel_dp *intel_dp = &intel_mst->primary->dp;
313 const struct drm_display_mode *adjusted_mode =
314 &pipe_config->hw.adjusted_mode;
315 struct link_config_limits limits;
318 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
321 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
322 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
323 pipe_config->has_pch_encoder = false;
325 pipe_config->has_audio =
326 intel_dp_mst_has_audio(conn_state) &&
327 intel_audio_compute_config(encoder, pipe_config, conn_state);
330 * for MST we always configure max link bw - the spec doesn't
331 * seem to suggest we should do otherwise.
334 limits.max_rate = intel_dp_max_link_rate(intel_dp);
336 limits.min_lane_count =
337 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
339 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
341 * FIXME: If all the streams can't fit into the link with
342 * their current pipe_bpp we should reduce pipe_bpp across
343 * the board until things start to fit. Until then we
344 * limit to <= 8bpc since that's what was hardcoded for all
345 * MST streams previously. This hack should be removed once
346 * we have the proper retry logic in place.
348 limits.max_bpp = min(pipe_config->pipe_bpp, 24);
350 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
352 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
353 conn_state, &limits);
358 /* enable compression if the mode doesn't fit available BW */
359 drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
360 if (ret || intel_dp->force_dsc_en) {
362 * Try to get at least some timeslots and then see, if
363 * we can fit there with DSC.
365 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
367 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
368 conn_state, &limits);
372 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
374 pipe_config->dp_m_n.tu, false);
380 ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
384 pipe_config->limited_color_range =
385 intel_dp_limited_color_range(pipe_config, conn_state);
387 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
388 pipe_config->lane_lat_optim_mask =
389 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
391 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
397 * Iterate over all connectors and return a mask of
398 * all CPU transcoders streaming over the same DP link.
401 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
402 struct intel_dp *mst_port)
404 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
405 const struct intel_digital_connector_state *conn_state;
406 struct intel_connector *connector;
410 if (DISPLAY_VER(dev_priv) < 12)
413 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
414 const struct intel_crtc_state *crtc_state;
415 struct intel_crtc *crtc;
417 if (connector->mst_port != mst_port || !conn_state->base.crtc)
420 crtc = to_intel_crtc(conn_state->base.crtc);
421 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
423 if (!crtc_state->hw.active)
426 transcoders |= BIT(crtc_state->cpu_transcoder);
432 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
433 struct intel_crtc_state *crtc_state,
434 struct drm_connector_state *conn_state)
436 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
437 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
438 struct intel_dp *intel_dp = &intel_mst->primary->dp;
440 /* lowest numbered transcoder will be designated master */
441 crtc_state->mst_master_transcoder =
442 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
448 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
449 * that shares the same MST stream as mode changed,
450 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
451 * a fastset when possible.
454 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
455 struct intel_atomic_state *state)
457 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
458 struct drm_connector_list_iter connector_list_iter;
459 struct intel_connector *connector_iter;
462 if (DISPLAY_VER(dev_priv) < 12)
465 if (!intel_connector_needs_modeset(state, &connector->base))
468 drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
469 for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
470 struct intel_digital_connector_state *conn_iter_state;
471 struct intel_crtc_state *crtc_state;
472 struct intel_crtc *crtc;
474 if (connector_iter->mst_port != connector->mst_port ||
475 connector_iter == connector)
478 conn_iter_state = intel_atomic_get_digital_connector_state(state,
480 if (IS_ERR(conn_iter_state)) {
481 ret = PTR_ERR(conn_iter_state);
485 if (!conn_iter_state->base.crtc)
488 crtc = to_intel_crtc(conn_iter_state->base.crtc);
489 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
490 if (IS_ERR(crtc_state)) {
491 ret = PTR_ERR(crtc_state);
495 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
498 crtc_state->uapi.mode_changed = true;
500 drm_connector_list_iter_end(&connector_list_iter);
506 intel_dp_mst_atomic_check(struct drm_connector *connector,
507 struct drm_atomic_state *_state)
509 struct intel_atomic_state *state = to_intel_atomic_state(_state);
510 struct intel_connector *intel_connector =
511 to_intel_connector(connector);
514 ret = intel_digital_connector_atomic_check(connector, &state->base);
518 ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state);
522 return drm_dp_atomic_release_time_slots(&state->base,
523 &intel_connector->mst_port->mst_mgr,
524 intel_connector->port);
527 static void clear_act_sent(struct intel_encoder *encoder,
528 const struct intel_crtc_state *crtc_state)
530 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
532 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
533 DP_TP_STATUS_ACT_SENT);
536 static void wait_for_act_sent(struct intel_encoder *encoder,
537 const struct intel_crtc_state *crtc_state)
539 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
540 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
541 struct intel_dp *intel_dp = &intel_mst->primary->dp;
543 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
544 DP_TP_STATUS_ACT_SENT, 1))
545 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
547 drm_dp_check_act_status(&intel_dp->mst_mgr);
550 static void intel_mst_disable_dp(struct intel_atomic_state *state,
551 struct intel_encoder *encoder,
552 const struct intel_crtc_state *old_crtc_state,
553 const struct drm_connector_state *old_conn_state)
555 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
556 struct intel_digital_port *dig_port = intel_mst->primary;
557 struct intel_dp *intel_dp = &dig_port->dp;
558 struct intel_connector *connector =
559 to_intel_connector(old_conn_state->connector);
560 struct drm_dp_mst_topology_state *old_mst_state =
561 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
562 struct drm_dp_mst_topology_state *new_mst_state =
563 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
564 const struct drm_dp_mst_atomic_payload *old_payload =
565 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
566 struct drm_dp_mst_atomic_payload *new_payload =
567 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
568 struct drm_i915_private *i915 = to_i915(connector->base.dev);
570 drm_dbg_kms(&i915->drm, "active links %d\n",
571 intel_dp->active_mst_links);
573 intel_hdcp_disable(intel_mst->connector);
575 drm_dp_remove_payload(&intel_dp->mst_mgr, new_mst_state,
576 old_payload, new_payload);
578 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
581 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
582 struct intel_encoder *encoder,
583 const struct intel_crtc_state *old_crtc_state,
584 const struct drm_connector_state *old_conn_state)
586 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
587 struct intel_digital_port *dig_port = intel_mst->primary;
588 struct intel_dp *intel_dp = &dig_port->dp;
589 struct intel_connector *connector =
590 to_intel_connector(old_conn_state->connector);
591 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
592 bool last_mst_stream;
594 intel_dp->active_mst_links--;
595 last_mst_stream = intel_dp->active_mst_links == 0;
596 drm_WARN_ON(&dev_priv->drm,
597 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
598 !intel_dp_mst_is_master_trans(old_crtc_state));
600 intel_crtc_vblank_off(old_crtc_state);
602 intel_disable_transcoder(old_crtc_state);
604 clear_act_sent(encoder, old_crtc_state);
606 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
607 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
609 wait_for_act_sent(encoder, old_crtc_state);
611 intel_ddi_disable_transcoder_func(old_crtc_state);
613 if (DISPLAY_VER(dev_priv) >= 9)
614 skl_scaler_disable(old_crtc_state);
616 ilk_pfit_disable(old_crtc_state);
619 * Power down mst path before disabling the port, otherwise we end
620 * up getting interrupts from the sink upon detecting link loss.
622 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
626 * BSpec 4287: disable DIP after the transcoder is disabled and before
627 * the transcoder clock select is set to none.
630 intel_dp_set_infoframes(&dig_port->base, false,
631 old_crtc_state, NULL);
633 * From TGL spec: "If multi-stream slave transcoder: Configure
634 * Transcoder Clock Select to direct no clock to the transcoder"
636 * From older GENs spec: "Configure Transcoder Clock Select to direct
637 * no clock to the transcoder"
639 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
640 intel_ddi_disable_transcoder_clock(old_crtc_state);
643 intel_mst->connector = NULL;
645 dig_port->base.post_disable(state, &dig_port->base,
646 old_crtc_state, NULL);
648 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
649 intel_dp->active_mst_links);
652 static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state,
653 struct intel_encoder *encoder,
654 const struct intel_crtc_state *old_crtc_state,
655 const struct drm_connector_state *old_conn_state)
657 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
658 struct intel_digital_port *dig_port = intel_mst->primary;
659 struct intel_dp *intel_dp = &dig_port->dp;
661 if (intel_dp->active_mst_links == 0 &&
662 dig_port->base.post_pll_disable)
663 dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);
666 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
667 struct intel_encoder *encoder,
668 const struct intel_crtc_state *pipe_config,
669 const struct drm_connector_state *conn_state)
671 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
672 struct intel_digital_port *dig_port = intel_mst->primary;
673 struct intel_dp *intel_dp = &dig_port->dp;
675 if (intel_dp->active_mst_links == 0)
676 dig_port->base.pre_pll_enable(state, &dig_port->base,
680 * The port PLL state needs to get updated for secondary
681 * streams as for the primary stream.
683 intel_ddi_update_active_dpll(state, &dig_port->base,
684 to_intel_crtc(pipe_config->uapi.crtc));
687 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
688 struct intel_encoder *encoder,
689 const struct intel_crtc_state *pipe_config,
690 const struct drm_connector_state *conn_state)
692 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
693 struct intel_digital_port *dig_port = intel_mst->primary;
694 struct intel_dp *intel_dp = &dig_port->dp;
695 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
696 struct intel_connector *connector =
697 to_intel_connector(conn_state->connector);
698 struct drm_dp_mst_topology_state *mst_state =
699 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
701 bool first_mst_stream;
703 /* MST encoders are bound to a crtc, not to a connector,
704 * force the mapping here for get_hw_state.
706 connector->encoder = encoder;
707 intel_mst->connector = connector;
708 first_mst_stream = intel_dp->active_mst_links == 0;
709 drm_WARN_ON(&dev_priv->drm,
710 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
711 !intel_dp_mst_is_master_trans(pipe_config));
713 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
714 intel_dp->active_mst_links);
716 if (first_mst_stream)
717 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
719 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
721 if (first_mst_stream)
722 dig_port->base.pre_enable(state, &dig_port->base,
725 intel_dp->active_mst_links++;
727 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
728 drm_atomic_get_mst_payload_state(mst_state, connector->port));
730 drm_err(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
731 connector->base.name, ret);
734 * Before Gen 12 this is not done as part of
735 * dig_port->base.pre_enable() and should be done here. For
736 * Gen 12+ the step in which this should be done is different for the
737 * first MST stream, so it's done on the DDI for the first stream and
738 * here for the following ones.
740 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
741 intel_ddi_enable_transcoder_clock(encoder, pipe_config);
743 intel_ddi_set_dp_msa(pipe_config, conn_state);
746 static void intel_mst_enable_dp(struct intel_atomic_state *state,
747 struct intel_encoder *encoder,
748 const struct intel_crtc_state *pipe_config,
749 const struct drm_connector_state *conn_state)
751 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
752 struct intel_digital_port *dig_port = intel_mst->primary;
753 struct intel_dp *intel_dp = &dig_port->dp;
754 struct intel_connector *connector = to_intel_connector(conn_state->connector);
755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
756 struct drm_dp_mst_topology_state *mst_state =
757 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
758 enum transcoder trans = pipe_config->cpu_transcoder;
760 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
762 clear_act_sent(encoder, pipe_config);
764 if (intel_dp_is_uhbr(pipe_config)) {
765 const struct drm_display_mode *adjusted_mode =
766 &pipe_config->hw.adjusted_mode;
767 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
769 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
770 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
771 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
772 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
775 intel_ddi_enable_transcoder_func(encoder, pipe_config);
777 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
778 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
780 drm_dbg_kms(&dev_priv->drm, "active links %d\n",
781 intel_dp->active_mst_links);
783 wait_for_act_sent(encoder, pipe_config);
785 drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
786 drm_atomic_get_mst_payload_state(mst_state, connector->port));
788 if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
789 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
790 FECSTALL_DIS_DPTSTREAM_DPTTG);
791 else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
792 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
793 FECSTALL_DIS_DPTSTREAM_DPTTG);
795 intel_enable_transcoder(pipe_config);
797 intel_crtc_vblank_on(pipe_config);
799 intel_audio_codec_enable(encoder, pipe_config, conn_state);
801 /* Enable hdcp if it's desired */
802 if (conn_state->content_protection ==
803 DRM_MODE_CONTENT_PROTECTION_DESIRED)
804 intel_hdcp_enable(state, encoder, pipe_config, conn_state);
807 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
810 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
811 *pipe = intel_mst->pipe;
812 if (intel_mst->connector)
817 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
818 struct intel_crtc_state *pipe_config)
820 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
821 struct intel_digital_port *dig_port = intel_mst->primary;
823 dig_port->base.get_config(&dig_port->base, pipe_config);
826 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
827 struct intel_crtc_state *crtc_state)
829 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
830 struct intel_digital_port *dig_port = intel_mst->primary;
832 return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
835 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
837 struct intel_connector *intel_connector = to_intel_connector(connector);
838 struct intel_dp *intel_dp = intel_connector->mst_port;
839 const struct drm_edid *drm_edid;
842 if (drm_connector_is_unregistered(connector))
843 return intel_connector_update_modes(connector, NULL);
845 drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);
847 ret = intel_connector_update_modes(connector, drm_edid);
849 drm_edid_free(drm_edid);
855 intel_dp_mst_connector_late_register(struct drm_connector *connector)
857 struct intel_connector *intel_connector = to_intel_connector(connector);
860 ret = drm_dp_mst_connector_late_register(connector,
861 intel_connector->port);
865 ret = intel_connector_register(connector);
867 drm_dp_mst_connector_early_unregister(connector,
868 intel_connector->port);
874 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
876 struct intel_connector *intel_connector = to_intel_connector(connector);
878 intel_connector_unregister(connector);
879 drm_dp_mst_connector_early_unregister(connector,
880 intel_connector->port);
883 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
884 .fill_modes = drm_helper_probe_single_connector_modes,
885 .atomic_get_property = intel_digital_connector_atomic_get_property,
886 .atomic_set_property = intel_digital_connector_atomic_set_property,
887 .late_register = intel_dp_mst_connector_late_register,
888 .early_unregister = intel_dp_mst_connector_early_unregister,
889 .destroy = intel_connector_destroy,
890 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
891 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
894 static int intel_dp_mst_get_modes(struct drm_connector *connector)
896 return intel_dp_mst_get_ddc_modes(connector);
900 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
901 struct drm_display_mode *mode,
902 struct drm_modeset_acquire_ctx *ctx,
903 enum drm_mode_status *status)
905 struct drm_i915_private *dev_priv = to_i915(connector->dev);
906 struct intel_connector *intel_connector = to_intel_connector(connector);
907 struct intel_dp *intel_dp = intel_connector->mst_port;
908 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
909 struct drm_dp_mst_port *port = intel_connector->port;
910 const int min_bpp = 18;
911 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
912 int max_rate, mode_rate, max_lanes, max_link_clock;
914 bool dsc = false, bigjoiner = false;
915 u16 dsc_max_output_bpp = 0;
916 u8 dsc_slice_count = 0;
917 int target_clock = mode->clock;
919 if (drm_connector_is_unregistered(connector)) {
920 *status = MODE_ERROR;
924 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
925 *status = MODE_NO_DBLESCAN;
929 max_link_clock = intel_dp_max_link_rate(intel_dp);
930 max_lanes = intel_dp_max_lane_count(intel_dp);
932 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
933 mode_rate = intel_dp_link_required(mode->clock, min_bpp);
935 ret = drm_modeset_lock(&mgr->base.lock, ctx);
939 if (mode_rate > max_rate || mode->clock > max_dotclk ||
940 drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
941 *status = MODE_CLOCK_HIGH;
945 if (mode->clock < 10000) {
946 *status = MODE_CLOCK_LOW;
950 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
951 *status = MODE_H_ILLEGAL;
955 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
960 if (DISPLAY_VER(dev_priv) >= 10 &&
961 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
963 * TBD pass the connector BPC,
964 * for now U8_MAX so that max BPC on that platform would be picked
966 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
968 if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
970 intel_dp_dsc_get_output_bpp(dev_priv,
978 intel_dp_dsc_get_slice_count(intel_dp,
984 dsc = dsc_max_output_bpp && dsc_slice_count;
988 * Big joiner configuration needs DSC for TGL which is not true for
989 * XE_LPD where uncompressed joiner is supported.
991 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
992 return MODE_CLOCK_HIGH;
994 if (mode_rate > max_rate && !dsc)
995 return MODE_CLOCK_HIGH;
997 *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
1001 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
1002 struct drm_atomic_state *state)
1004 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1006 struct intel_connector *intel_connector = to_intel_connector(connector);
1007 struct intel_dp *intel_dp = intel_connector->mst_port;
1008 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
1010 return &intel_dp->mst_encoders[crtc->pipe]->base.base;
1014 intel_dp_mst_detect(struct drm_connector *connector,
1015 struct drm_modeset_acquire_ctx *ctx, bool force)
1017 struct drm_i915_private *i915 = to_i915(connector->dev);
1018 struct intel_connector *intel_connector = to_intel_connector(connector);
1019 struct intel_dp *intel_dp = intel_connector->mst_port;
1021 if (!INTEL_DISPLAY_ENABLED(i915))
1022 return connector_status_disconnected;
1024 if (drm_connector_is_unregistered(connector))
1025 return connector_status_disconnected;
1027 return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
1028 intel_connector->port);
1031 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
1032 .get_modes = intel_dp_mst_get_modes,
1033 .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
1034 .atomic_best_encoder = intel_mst_atomic_best_encoder,
1035 .atomic_check = intel_dp_mst_atomic_check,
1036 .detect_ctx = intel_dp_mst_detect,
1039 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
1041 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
1043 drm_encoder_cleanup(encoder);
1047 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
1048 .destroy = intel_dp_mst_encoder_destroy,
1051 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
1053 if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1055 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1062 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1063 struct drm_connector *connector,
1064 const char *pathprop)
1066 struct drm_i915_private *i915 = to_i915(connector->dev);
1068 drm_object_attach_property(&connector->base,
1069 i915->drm.mode_config.path_property, 0);
1070 drm_object_attach_property(&connector->base,
1071 i915->drm.mode_config.tile_property, 0);
1073 intel_attach_force_audio_property(connector);
1074 intel_attach_broadcast_rgb_property(connector);
1077 * Reuse the prop from the SST connector because we're
1078 * not allowed to create new props after device registration.
1080 connector->max_bpc_property =
1081 intel_dp->attached_connector->base.max_bpc_property;
1082 if (connector->max_bpc_property)
1083 drm_connector_attach_max_bpc_property(connector, 6, 12);
1085 return drm_connector_set_path_property(connector, pathprop);
1088 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1089 struct drm_dp_mst_port *port,
1090 const char *pathprop)
1092 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1093 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1094 struct drm_device *dev = dig_port->base.base.dev;
1095 struct drm_i915_private *dev_priv = to_i915(dev);
1096 struct intel_connector *intel_connector;
1097 struct drm_connector *connector;
1101 intel_connector = intel_connector_alloc();
1102 if (!intel_connector)
1105 intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1106 intel_connector->mst_port = intel_dp;
1107 intel_connector->port = port;
1108 drm_dp_mst_get_port_malloc(port);
1110 connector = &intel_connector->base;
1111 ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1112 DRM_MODE_CONNECTOR_DisplayPort);
1114 drm_dp_mst_put_port_malloc(port);
1115 intel_connector_free(intel_connector);
1119 drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1121 for_each_pipe(dev_priv, pipe) {
1122 struct drm_encoder *enc =
1123 &intel_dp->mst_encoders[pipe]->base.base;
1125 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1130 ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1134 ret = intel_dp_hdcp_init(dig_port, intel_connector);
1136 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1137 connector->name, connector->base.id);
1142 drm_connector_cleanup(connector);
1147 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1149 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1151 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1154 static const struct drm_dp_mst_topology_cbs mst_cbs = {
1155 .add_connector = intel_dp_add_mst_connector,
1156 .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1159 static struct intel_dp_mst_encoder *
1160 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1162 struct intel_dp_mst_encoder *intel_mst;
1163 struct intel_encoder *intel_encoder;
1164 struct drm_device *dev = dig_port->base.base.dev;
1166 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1171 intel_mst->pipe = pipe;
1172 intel_encoder = &intel_mst->base;
1173 intel_mst->primary = dig_port;
1175 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1176 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1178 intel_encoder->type = INTEL_OUTPUT_DP_MST;
1179 intel_encoder->power_domain = dig_port->base.power_domain;
1180 intel_encoder->port = dig_port->base.port;
1181 intel_encoder->cloneable = 0;
1183 * This is wrong, but broken userspace uses the intersection
1184 * of possible_crtcs of all the encoders of a given connector
1185 * to figure out which crtcs can drive said connector. What
1186 * should be used instead is the union of possible_crtcs.
1187 * To keep such userspace functioning we must misconfigure
1188 * this to make sure the intersection is not empty :(
1190 intel_encoder->pipe_mask = ~0;
1192 intel_encoder->compute_config = intel_dp_mst_compute_config;
1193 intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1194 intel_encoder->disable = intel_mst_disable_dp;
1195 intel_encoder->post_disable = intel_mst_post_disable_dp;
1196 intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
1197 intel_encoder->update_pipe = intel_ddi_update_pipe;
1198 intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1199 intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1200 intel_encoder->enable = intel_mst_enable_dp;
1201 intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1202 intel_encoder->get_config = intel_dp_mst_enc_get_config;
1203 intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1210 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1212 struct intel_dp *intel_dp = &dig_port->dp;
1213 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1216 for_each_pipe(dev_priv, pipe)
1217 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1222 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1224 return dig_port->dp.active_mst_links;
1228 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1230 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1231 struct intel_dp *intel_dp = &dig_port->dp;
1232 enum port port = dig_port->base.port;
1235 if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1238 if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1241 if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1244 intel_dp->mst_mgr.cbs = &mst_cbs;
1246 /* create encoders */
1247 intel_dp_create_fake_mst_encoders(dig_port);
1248 ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1249 &intel_dp->aux, 16, 3, conn_base_id);
1251 intel_dp->mst_mgr.cbs = NULL;
1258 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1260 return intel_dp->mst_mgr.cbs;
1264 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1266 struct intel_dp *intel_dp = &dig_port->dp;
1268 if (!intel_dp_mst_source_support(intel_dp))
1271 drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1272 /* encoders will get killed by normal cleanup */
1274 intel_dp->mst_mgr.cbs = NULL;
1277 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1279 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1282 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1284 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1285 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1289 * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1290 * @state: atomic state
1291 * @connector: connector to add the state for
1292 * @crtc: the CRTC @connector is attached to
1294 * Add the MST topology state for @connector to @state.
1296 * Returns 0 on success, negative error code on failure.
1299 intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1300 struct intel_connector *connector,
1301 struct intel_crtc *crtc)
1303 struct drm_dp_mst_topology_state *mst_state;
1305 if (!connector->mst_port)
1308 mst_state = drm_atomic_get_mst_topology_state(&state->base,
1309 &connector->mst_port->mst_mgr);
1310 if (IS_ERR(mst_state))
1311 return PTR_ERR(mst_state);
1313 mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1319 * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1320 * @state: atomic state
1321 * @crtc: CRTC to add the state for
1323 * Add the MST topology state for @crtc to @state.
1325 * Returns 0 on success, negative error code on failure.
1327 int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1328 struct intel_crtc *crtc)
1330 struct drm_connector *_connector;
1331 struct drm_connector_state *conn_state;
1334 for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1335 struct intel_connector *connector = to_intel_connector(_connector);
1338 if (conn_state->crtc != &crtc->base)
1341 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);