drivers/gpu/drm/i915/display/intel_dp_mst.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *             2014 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_probe_helper.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_reg.h"
  33 #include "intel_atomic.h"
  34 #include "intel_audio.h"
  35 #include "intel_connector.h"
  36 #include "intel_crtc.h"
  37 #include "intel_ddi.h"
  38 #include "intel_de.h"
  39 #include "intel_display_types.h"
  40 #include "intel_dp.h"
  41 #include "intel_dp_hdcp.h"
  42 #include "intel_dp_mst.h"
  43 #include "intel_dpio_phy.h"
  44 #include "intel_hdcp.h"
  45 #include "intel_hotplug.h"
  46 #include "skl_scaler.h"
  47
  48 static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
  49                                           const struct drm_display_mode *adjusted_mode,
  50                                           struct intel_crtc_state *crtc_state,
  51                                           bool dsc)
  52 {
  53         if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) {
  54                 int output_bpp = bpp;
  55                 /* DisplayPort 2 128b/132b, bits per lane is always 32 */
  56                 int symbol_clock = crtc_state->port_clock / 32;
  57
  58                 if (output_bpp * adjusted_mode->crtc_clock >=
  59                     symbol_clock * 72) {
  60                         drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n",
  61                                     output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);
  62                         return -EINVAL;
  63                 }
  64         }
  65
  66         return 0;
  67 }
  68
  69 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
  70                                                 struct intel_crtc_state *crtc_state,
  71                                                 int max_bpp,
  72                                                 int min_bpp,
  73                                                 struct link_config_limits *limits,
  74                                                 struct drm_connector_state *conn_state,
  75                                                 int step,
  76                                                 bool dsc)
  77 {
  78         struct drm_atomic_state *state = crtc_state->uapi.state;
  79         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
  80         struct intel_dp *intel_dp = &intel_mst->primary->dp;
  81         struct drm_dp_mst_topology_state *mst_state;
  82         struct intel_connector *connector =
  83                 to_intel_connector(conn_state->connector);
  84         struct drm_i915_private *i915 = to_i915(connector->base.dev);
  85         const struct drm_display_mode *adjusted_mode =
  86                 &crtc_state->hw.adjusted_mode;
  87         int bpp, slots = -EINVAL;
  88         int ret = 0;
  89
  90         mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
  91         if (IS_ERR(mst_state))
  92                 return PTR_ERR(mst_state);
  93
  94         crtc_state->lane_count = limits->max_lane_count;
  95         crtc_state->port_clock = limits->max_rate;
  96
  97         // TODO: Handle pbn_div changes by adding a new MST helper
  98         if (!mst_state->pbn_div) {
  99                 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
 100                                                               crtc_state->port_clock,
 101                                                               crtc_state->lane_count);
 102         }
 103
 104         for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
 105                 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
 106
 107                 ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
 108                 if (ret)
 109                         continue;
 110
 111                 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
 112                                                        dsc ? bpp << 4 : bpp,
 113                                                        dsc);
 114
 115                 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
 116                                                       connector->port,
 117                                                       crtc_state->pbn);
 118                 if (slots == -EDEADLK)
 119                         return slots;
 120
 121                 if (slots >= 0) {
 122                         ret = drm_dp_mst_atomic_check(state);
 123                         /*
 124                          * If we got slots >= 0 and we can fit those based on check
 125                          * then we can exit the loop. Otherwise keep trying.
 126                          */
 127                         if (!ret)
 128                                 break;
 129                 }
 130         }
 131
 132         /* We failed to find a proper bpp/timeslots, return error */
 133         if (ret)
 134                 slots = ret;
 135
 136         if (slots < 0) {
 137                 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
 138                             slots);
 139         } else {
 140                 if (!dsc)
 141                         crtc_state->pipe_bpp = bpp;
 142                 else
 143                         crtc_state->dsc.compressed_bpp = bpp;
 144                 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 145         }
 146
 147         return slots;
 148 }
 149
 150 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 151                                             struct intel_crtc_state *crtc_state,
 152                                             struct drm_connector_state *conn_state,
 153                                             struct link_config_limits *limits)
 154 {
 155         const struct drm_display_mode *adjusted_mode =
 156                 &crtc_state->hw.adjusted_mode;
 157         int slots = -EINVAL;
 158
 159         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
 160                                                      limits->min_bpp, limits,
 161                                                      conn_state, 2 * 3, false);
 162
 163         if (slots < 0)
 164                 return slots;
 165
 166         intel_link_compute_m_n(crtc_state->pipe_bpp,
 167                                crtc_state->lane_count,
 168                                adjusted_mode->crtc_clock,
 169                                crtc_state->port_clock,
 170                                &crtc_state->dp_m_n,
 171                                crtc_state->fec_enable);
 172         crtc_state->dp_m_n.tu = slots;
 173
 174         return 0;
 175 }
 176
 177 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 178                                                 struct intel_crtc_state *crtc_state,
 179                                                 struct drm_connector_state *conn_state,
 180                                                 struct link_config_limits *limits)
 181 {
 182         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 183         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 184         struct intel_connector *connector =
 185                 to_intel_connector(conn_state->connector);
 186         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 187         const struct drm_display_mode *adjusted_mode =
 188                 &crtc_state->hw.adjusted_mode;
 189         int slots = -EINVAL;
 190         int i, num_bpc;
 191         u8 dsc_bpc[3] = {0};
 192         int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
 193         u8 dsc_max_bpc;
 194         bool need_timeslot_recalc = false;
 195         u32 last_compressed_bpp;
 196
 197         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
 198         if (DISPLAY_VER(i915) >= 12)
 199                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
 200         else
 201                 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
 202
 203         max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
 204         min_bpp = limits->min_bpp;
 205
 206         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
 207                                                        dsc_bpc);
 208
 209         drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
 210                     min_bpp, max_bpp);
 211
 212         sink_max_bpp = dsc_bpc[0] * 3;
 213         sink_min_bpp = sink_max_bpp;
 214
 215         for (i = 1; i < num_bpc; i++) {
 216                 if (sink_min_bpp > dsc_bpc[i] * 3)
 217                         sink_min_bpp = dsc_bpc[i] * 3;
 218                 if (sink_max_bpp < dsc_bpc[i] * 3)
 219                         sink_max_bpp = dsc_bpc[i] * 3;
 220         }
 221
 222         drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
 223                     sink_min_bpp, sink_max_bpp);
 224
 225         if (min_bpp < sink_min_bpp)
 226                 min_bpp = sink_min_bpp;
 227
 228         if (max_bpp > sink_max_bpp)
 229                 max_bpp = sink_max_bpp;
 230
 231         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
 232                                                      min_bpp, limits,
 233                                                      conn_state, 2 * 3, true);
 234
 235         if (slots < 0)
 236                 return slots;
 237
 238         last_compressed_bpp = crtc_state->dsc.compressed_bpp;
 239
 240         crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
 241                                                                         last_compressed_bpp,
 242                                                                         crtc_state->pipe_bpp);
 243
 244         if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
 245                 need_timeslot_recalc = true;
 246
 247         /*
 248          * Apparently some MST hubs dislike if vcpi slots are not matching precisely
 249          * the actual compressed bpp we use.
 250          */
 251         if (need_timeslot_recalc) {
 252                 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
 253                                                              crtc_state->dsc.compressed_bpp,
 254                                                              crtc_state->dsc.compressed_bpp,
 255                                                              limits, conn_state, 2 * 3, true);
 256                 if (slots < 0)
 257                         return slots;
 258         }
 259
 260         intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
 261                                crtc_state->lane_count,
 262                                adjusted_mode->crtc_clock,
 263                                crtc_state->port_clock,
 264                                &crtc_state->dp_m_n,
 265                                crtc_state->fec_enable);
 266         crtc_state->dp_m_n.tu = slots;
 267
 268         return 0;
 269 }
 270 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
 271                                      struct intel_crtc_state *crtc_state,
 272                                      struct drm_connector_state *conn_state)
 273 {
 274         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 275         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 276         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 277         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 278         struct drm_dp_mst_topology_state *topology_state;
 279         u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
 280                 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
 281
 282         topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
 283         if (IS_ERR(topology_state)) {
 284                 drm_dbg_kms(&i915->drm, "slot update failed\n");
 285                 return PTR_ERR(topology_state);
 286         }
 287
 288         drm_dp_mst_update_slots(topology_state, link_coding_cap);
 289
 290         return 0;
 291 }
 292
 293 static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
 294 {
 295         const struct intel_digital_connector_state *intel_conn_state =
 296                 to_intel_digital_connector_state(conn_state);
 297         struct intel_connector *connector =
 298                 to_intel_connector(conn_state->connector);
 299
 300         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
 301                 return connector->base.display_info.has_audio;
 302         else
 303                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
 304 }
 305
 306 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 307                                        struct intel_crtc_state *pipe_config,
 308                                        struct drm_connector_state *conn_state)
 309 {
 310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 311         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 312         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 313         const struct drm_display_mode *adjusted_mode =
 314                 &pipe_config->hw.adjusted_mode;
 315         struct link_config_limits limits;
 316         int ret;
 317
 318         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 319                 return -EINVAL;
 320
 321         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 322         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 323         pipe_config->has_pch_encoder = false;
 324
 325         pipe_config->has_audio =
 326                 intel_dp_mst_has_audio(conn_state) &&
 327                 intel_audio_compute_config(encoder, pipe_config, conn_state);
 328
 329         /*
 330          * for MST we always configure max link bw - the spec doesn't
 331          * seem to suggest we should do otherwise.
 332          */
 333         limits.min_rate =
 334         limits.max_rate = intel_dp_max_link_rate(intel_dp);
 335
 336         limits.min_lane_count =
 337         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 338
 339         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
 340         /*
 341          * FIXME: If all the streams can't fit into the link with
 342          * their current pipe_bpp we should reduce pipe_bpp across
 343          * the board until things start to fit. Until then we
 344          * limit to <= 8bpc since that's what was hardcoded for all
 345          * MST streams previously. This hack should be removed once
 346          * we have the proper retry logic in place.
 347          */
 348         limits.max_bpp = min(pipe_config->pipe_bpp, 24);
 349
 350         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
 351
 352         ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
 353                                                conn_state, &limits);
 354
 355         if (ret == -EDEADLK)
 356                 return ret;
 357
 358         /* enable compression if the mode doesn't fit available BW */
 359         drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
 360         if (ret || intel_dp->force_dsc_en) {
 361                 /*
 362                  * Try to get at least some timeslots and then see, if
 363                  * we can fit there with DSC.
 364                  */
 365                 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
 366
 367                 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
 368                                                            conn_state, &limits);
 369                 if (ret < 0)
 370                         return ret;
 371
 372                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
 373                                                   conn_state, &limits,
 374                                                   pipe_config->dp_m_n.tu, false);
 375         }
 376
 377         if (ret)
 378                 return ret;
 379
 380         ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
 381         if (ret)
 382                 return ret;
 383
 384         pipe_config->limited_color_range =
 385                 intel_dp_limited_color_range(pipe_config, conn_state);
 386
 387         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 388                 pipe_config->lane_lat_optim_mask =
 389                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 390
 391         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 392
 393         return 0;
 394 }
 395
 396 /*
 397  * Iterate over all connectors and return a mask of
 398  * all CPU transcoders streaming over the same DP link.
 399  */
 400 static unsigned int
 401 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
 402                              struct intel_dp *mst_port)
 403 {
 404         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 405         const struct intel_digital_connector_state *conn_state;
 406         struct intel_connector *connector;
 407         u8 transcoders = 0;
 408         int i;
 409
 410         if (DISPLAY_VER(dev_priv) < 12)
 411                 return 0;
 412
 413         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 414                 const struct intel_crtc_state *crtc_state;
 415                 struct intel_crtc *crtc;
 416
 417                 if (connector->mst_port != mst_port || !conn_state->base.crtc)
 418                         continue;
 419
 420                 crtc = to_intel_crtc(conn_state->base.crtc);
 421                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 422
 423                 if (!crtc_state->hw.active)
 424                         continue;
 425
 426                 transcoders |= BIT(crtc_state->cpu_transcoder);
 427         }
 428
 429         return transcoders;
 430 }
 431
 432 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
 433                                             struct intel_crtc_state *crtc_state,
 434                                             struct drm_connector_state *conn_state)
 435 {
 436         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 437         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 438         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 439
 440         /* lowest numbered transcoder will be designated master */
 441         crtc_state->mst_master_transcoder =
 442                 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
 443
 444         return 0;
 445 }
 446
 447 /*
 448  * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
 449  * that shares the same MST stream as mode changed,
 450  * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
 451  * a fastset when possible.
 452  */
 453 static int
 454 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
 455                                        struct intel_atomic_state *state)
 456 {
 457         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 458         struct drm_connector_list_iter connector_list_iter;
 459         struct intel_connector *connector_iter;
 460         int ret = 0;
 461
 462         if (DISPLAY_VER(dev_priv) < 12)
 463                 return  0;
 464
 465         if (!intel_connector_needs_modeset(state, &connector->base))
 466                 return 0;
 467
 468         drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
 469         for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
 470                 struct intel_digital_connector_state *conn_iter_state;
 471                 struct intel_crtc_state *crtc_state;
 472                 struct intel_crtc *crtc;
 473
 474                 if (connector_iter->mst_port != connector->mst_port ||
 475                     connector_iter == connector)
 476                         continue;
 477
 478                 conn_iter_state = intel_atomic_get_digital_connector_state(state,
 479                                                                            connector_iter);
 480                 if (IS_ERR(conn_iter_state)) {
 481                         ret = PTR_ERR(conn_iter_state);
 482                         break;
 483                 }
 484
 485                 if (!conn_iter_state->base.crtc)
 486                         continue;
 487
 488                 crtc = to_intel_crtc(conn_iter_state->base.crtc);
 489                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
 490                 if (IS_ERR(crtc_state)) {
 491                         ret = PTR_ERR(crtc_state);
 492                         break;
 493                 }
 494
 495                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
 496                 if (ret)
 497                         break;
 498                 crtc_state->uapi.mode_changed = true;
 499         }
 500         drm_connector_list_iter_end(&connector_list_iter);
 501
 502         return ret;
 503 }
 504
 505 static int
 506 intel_dp_mst_atomic_check(struct drm_connector *connector,
 507                           struct drm_atomic_state *_state)
 508 {
 509         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 510         struct intel_connector *intel_connector =
 511                 to_intel_connector(connector);
 512         int ret;
 513
 514         ret = intel_digital_connector_atomic_check(connector, &state->base);
 515         if (ret)
 516                 return ret;
 517
 518         ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state);
 519         if (ret)
 520                 return ret;
 521
 522         return drm_dp_atomic_release_time_slots(&state->base,
 523                                                 &intel_connector->mst_port->mst_mgr,
 524                                                 intel_connector->port);
 525 }
 526
 527 static void clear_act_sent(struct intel_encoder *encoder,
 528                            const struct intel_crtc_state *crtc_state)
 529 {
 530         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 531
 532         intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
 533                        DP_TP_STATUS_ACT_SENT);
 534 }
 535
 536 static void wait_for_act_sent(struct intel_encoder *encoder,
 537                               const struct intel_crtc_state *crtc_state)
 538 {
 539         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 540         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 541         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 542
 543         if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
 544                                   DP_TP_STATUS_ACT_SENT, 1))
 545                 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
 546
 547         drm_dp_check_act_status(&intel_dp->mst_mgr);
 548 }
 549
 550 static void intel_mst_disable_dp(struct intel_atomic_state *state,
 551                                  struct intel_encoder *encoder,
 552                                  const struct intel_crtc_state *old_crtc_state,
 553                                  const struct drm_connector_state *old_conn_state)
 554 {
 555         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 556         struct intel_digital_port *dig_port = intel_mst->primary;
 557         struct intel_dp *intel_dp = &dig_port->dp;
 558         struct intel_connector *connector =
 559                 to_intel_connector(old_conn_state->connector);
 560         struct drm_dp_mst_topology_state *old_mst_state =
 561                 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 562         struct drm_dp_mst_topology_state *new_mst_state =
 563                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 564         const struct drm_dp_mst_atomic_payload *old_payload =
 565                 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
 566         struct drm_dp_mst_atomic_payload *new_payload =
 567                 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
 568         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 569
 570         drm_dbg_kms(&i915->drm, "active links %d\n",
 571                     intel_dp->active_mst_links);
 572
 573         intel_hdcp_disable(intel_mst->connector);
 574
 575         drm_dp_remove_payload(&intel_dp->mst_mgr, new_mst_state,
 576                               old_payload, new_payload);
 577
 578         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
 579 }
 580
 581 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 582                                       struct intel_encoder *encoder,
 583                                       const struct intel_crtc_state *old_crtc_state,
 584                                       const struct drm_connector_state *old_conn_state)
 585 {
 586         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 587         struct intel_digital_port *dig_port = intel_mst->primary;
 588         struct intel_dp *intel_dp = &dig_port->dp;
 589         struct intel_connector *connector =
 590                 to_intel_connector(old_conn_state->connector);
 591         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 592         bool last_mst_stream;
 593
 594         intel_dp->active_mst_links--;
 595         last_mst_stream = intel_dp->active_mst_links == 0;
 596         drm_WARN_ON(&dev_priv->drm,
 597                     DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
 598                     !intel_dp_mst_is_master_trans(old_crtc_state));
 599
 600         intel_crtc_vblank_off(old_crtc_state);
 601
 602         intel_disable_transcoder(old_crtc_state);
 603
 604         clear_act_sent(encoder, old_crtc_state);
 605
 606         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
 607                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
 608
 609         wait_for_act_sent(encoder, old_crtc_state);
 610
 611         intel_ddi_disable_transcoder_func(old_crtc_state);
 612
 613         if (DISPLAY_VER(dev_priv) >= 9)
 614                 skl_scaler_disable(old_crtc_state);
 615         else
 616                 ilk_pfit_disable(old_crtc_state);
 617
 618         /*
 619          * Power down mst path before disabling the port, otherwise we end
 620          * up getting interrupts from the sink upon detecting link loss.
 621          */
 622         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
 623                                      false);
 624
 625         /*
 626          * BSpec 4287: disable DIP after the transcoder is disabled and before
 627          * the transcoder clock select is set to none.
 628          */
 629         if (last_mst_stream)
 630                 intel_dp_set_infoframes(&dig_port->base, false,
 631                                         old_crtc_state, NULL);
 632         /*
 633          * From TGL spec: "If multi-stream slave transcoder: Configure
 634          * Transcoder Clock Select to direct no clock to the transcoder"
 635          *
 636          * From older GENs spec: "Configure Transcoder Clock Select to direct
 637          * no clock to the transcoder"
 638          */
 639         if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
 640                 intel_ddi_disable_transcoder_clock(old_crtc_state);
 641
 642
 643         intel_mst->connector = NULL;
 644         if (last_mst_stream)
 645                 dig_port->base.post_disable(state, &dig_port->base,
 646                                                   old_crtc_state, NULL);
 647
 648         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 649                     intel_dp->active_mst_links);
 650 }
 651
 652 static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state,
 653                                           struct intel_encoder *encoder,
 654                                           const struct intel_crtc_state *old_crtc_state,
 655                                           const struct drm_connector_state *old_conn_state)
 656 {
 657         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 658         struct intel_digital_port *dig_port = intel_mst->primary;
 659         struct intel_dp *intel_dp = &dig_port->dp;
 660
 661         if (intel_dp->active_mst_links == 0 &&
 662             dig_port->base.post_pll_disable)
 663                 dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);
 664 }
 665
 666 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
 667                                         struct intel_encoder *encoder,
 668                                         const struct intel_crtc_state *pipe_config,
 669                                         const struct drm_connector_state *conn_state)
 670 {
 671         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 672         struct intel_digital_port *dig_port = intel_mst->primary;
 673         struct intel_dp *intel_dp = &dig_port->dp;
 674
 675         if (intel_dp->active_mst_links == 0)
 676                 dig_port->base.pre_pll_enable(state, &dig_port->base,
 677                                                     pipe_config, NULL);
 678         else
 679                 /*
 680                  * The port PLL state needs to get updated for secondary
 681                  * streams as for the primary stream.
 682                  */
 683                 intel_ddi_update_active_dpll(state, &dig_port->base,
 684                                              to_intel_crtc(pipe_config->uapi.crtc));
 685 }
 686
 687 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 688                                     struct intel_encoder *encoder,
 689                                     const struct intel_crtc_state *pipe_config,
 690                                     const struct drm_connector_state *conn_state)
 691 {
 692         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 693         struct intel_digital_port *dig_port = intel_mst->primary;
 694         struct intel_dp *intel_dp = &dig_port->dp;
 695         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 696         struct intel_connector *connector =
 697                 to_intel_connector(conn_state->connector);
 698         struct drm_dp_mst_topology_state *mst_state =
 699                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 700         int ret;
 701         bool first_mst_stream;
 702
 703         /* MST encoders are bound to a crtc, not to a connector,
 704          * force the mapping here for get_hw_state.
 705          */
 706         connector->encoder = encoder;
 707         intel_mst->connector = connector;
 708         first_mst_stream = intel_dp->active_mst_links == 0;
 709         drm_WARN_ON(&dev_priv->drm,
 710                     DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
 711                     !intel_dp_mst_is_master_trans(pipe_config));
 712
 713         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 714                     intel_dp->active_mst_links);
 715
 716         if (first_mst_stream)
 717                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 718
 719         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 720
 721         if (first_mst_stream)
 722                 dig_port->base.pre_enable(state, &dig_port->base,
 723                                                 pipe_config, NULL);
 724
 725         intel_dp->active_mst_links++;
 726
 727         ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
 728                                        drm_atomic_get_mst_payload_state(mst_state, connector->port));
 729         if (ret < 0)
 730                 drm_err(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
 731                         connector->base.name, ret);
 732
 733         /*
 734          * Before Gen 12 this is not done as part of
 735          * dig_port->base.pre_enable() and should be done here. For
 736          * Gen 12+ the step in which this should be done is different for the
 737          * first MST stream, so it's done on the DDI for the first stream and
 738          * here for the following ones.
 739          */
 740         if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
 741                 intel_ddi_enable_transcoder_clock(encoder, pipe_config);
 742
 743         intel_ddi_set_dp_msa(pipe_config, conn_state);
 744 }
 745
 746 static void intel_mst_enable_dp(struct intel_atomic_state *state,
 747                                 struct intel_encoder *encoder,
 748                                 const struct intel_crtc_state *pipe_config,
 749                                 const struct drm_connector_state *conn_state)
 750 {
 751         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 752         struct intel_digital_port *dig_port = intel_mst->primary;
 753         struct intel_dp *intel_dp = &dig_port->dp;
 754         struct intel_connector *connector = to_intel_connector(conn_state->connector);
 755         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 756         struct drm_dp_mst_topology_state *mst_state =
 757                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 758         enum transcoder trans = pipe_config->cpu_transcoder;
 759
 760         drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
 761
 762         clear_act_sent(encoder, pipe_config);
 763
 764         if (intel_dp_is_uhbr(pipe_config)) {
 765                 const struct drm_display_mode *adjusted_mode =
 766                         &pipe_config->hw.adjusted_mode;
 767                 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
 768
 769                 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
 770                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
 771                 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
 772                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
 773         }
 774
 775         intel_ddi_enable_transcoder_func(encoder, pipe_config);
 776
 777         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
 778                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 779
 780         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 781                     intel_dp->active_mst_links);
 782
 783         wait_for_act_sent(encoder, pipe_config);
 784
 785         drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
 786                                  drm_atomic_get_mst_payload_state(mst_state, connector->port));
 787
 788         if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
 789                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
 790                              FECSTALL_DIS_DPTSTREAM_DPTTG);
 791         else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
 792                 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
 793                              FECSTALL_DIS_DPTSTREAM_DPTTG);
 794
 795         intel_enable_transcoder(pipe_config);
 796
 797         intel_crtc_vblank_on(pipe_config);
 798
 799         intel_audio_codec_enable(encoder, pipe_config, conn_state);
 800
 801         /* Enable hdcp if it's desired */
 802         if (conn_state->content_protection ==
 803             DRM_MODE_CONTENT_PROTECTION_DESIRED)
 804                 intel_hdcp_enable(state, encoder, pipe_config, conn_state);
 805 }
 806
 807 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
 808                                       enum pipe *pipe)
 809 {
 810         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 811         *pipe = intel_mst->pipe;
 812         if (intel_mst->connector)
 813                 return true;
 814         return false;
 815 }
 816
 817 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
 818                                         struct intel_crtc_state *pipe_config)
 819 {
 820         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 821         struct intel_digital_port *dig_port = intel_mst->primary;
 822
 823         dig_port->base.get_config(&dig_port->base, pipe_config);
 824 }
 825
 826 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
 827                                                struct intel_crtc_state *crtc_state)
 828 {
 829         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 830         struct intel_digital_port *dig_port = intel_mst->primary;
 831
 832         return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
 833 }
 834
 835 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
 836 {
 837         struct intel_connector *intel_connector = to_intel_connector(connector);
 838         struct intel_dp *intel_dp = intel_connector->mst_port;
 839         struct edid *edid;
 840         int ret;
 841
 842         if (drm_connector_is_unregistered(connector))
 843                 return intel_connector_update_modes(connector, NULL);
 844
 845         edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
 846         ret = intel_connector_update_modes(connector, edid);
 847         kfree(edid);
 848
 849         return ret;
 850 }
 851
 852 static int
 853 intel_dp_mst_connector_late_register(struct drm_connector *connector)
 854 {
 855         struct intel_connector *intel_connector = to_intel_connector(connector);
 856         int ret;
 857
 858         ret = drm_dp_mst_connector_late_register(connector,
 859                                                  intel_connector->port);
 860         if (ret < 0)
 861                 return ret;
 862
 863         ret = intel_connector_register(connector);
 864         if (ret < 0)
 865                 drm_dp_mst_connector_early_unregister(connector,
 866                                                       intel_connector->port);
 867
 868         return ret;
 869 }
 870
 871 static void
 872 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
 873 {
 874         struct intel_connector *intel_connector = to_intel_connector(connector);
 875
 876         intel_connector_unregister(connector);
 877         drm_dp_mst_connector_early_unregister(connector,
 878                                               intel_connector->port);
 879 }
 880
 881 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
 882         .fill_modes = drm_helper_probe_single_connector_modes,
 883         .atomic_get_property = intel_digital_connector_atomic_get_property,
 884         .atomic_set_property = intel_digital_connector_atomic_set_property,
 885         .late_register = intel_dp_mst_connector_late_register,
 886         .early_unregister = intel_dp_mst_connector_early_unregister,
 887         .destroy = intel_connector_destroy,
 888         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 889         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 890 };
 891
 892 static int intel_dp_mst_get_modes(struct drm_connector *connector)
 893 {
 894         return intel_dp_mst_get_ddc_modes(connector);
 895 }
 896
 897 static int
 898 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 899                             struct drm_display_mode *mode,
 900                             struct drm_modeset_acquire_ctx *ctx,
 901                             enum drm_mode_status *status)
 902 {
 903         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 904         struct intel_connector *intel_connector = to_intel_connector(connector);
 905         struct intel_dp *intel_dp = intel_connector->mst_port;
 906         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 907         struct drm_dp_mst_port *port = intel_connector->port;
 908         const int min_bpp = 18;
 909         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 910         int max_rate, mode_rate, max_lanes, max_link_clock;
 911         int ret;
 912         bool dsc = false, bigjoiner = false;
 913         u16 dsc_max_output_bpp = 0;
 914         u8 dsc_slice_count = 0;
 915         int target_clock = mode->clock;
 916
 917         if (drm_connector_is_unregistered(connector)) {
 918                 *status = MODE_ERROR;
 919                 return 0;
 920         }
 921
 922         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 923                 *status = MODE_NO_DBLESCAN;
 924                 return 0;
 925         }
 926
 927         max_link_clock = intel_dp_max_link_rate(intel_dp);
 928         max_lanes = intel_dp_max_lane_count(intel_dp);
 929
 930         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 931         mode_rate = intel_dp_link_required(mode->clock, min_bpp);
 932
 933         ret = drm_modeset_lock(&mgr->base.lock, ctx);
 934         if (ret)
 935                 return ret;
 936
 937         if (mode_rate > max_rate || mode->clock > max_dotclk ||
 938             drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
 939                 *status = MODE_CLOCK_HIGH;
 940                 return 0;
 941         }
 942
 943         if (mode->clock < 10000) {
 944                 *status = MODE_CLOCK_LOW;
 945                 return 0;
 946         }
 947
 948         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
 949                 *status = MODE_H_ILLEGAL;
 950                 return 0;
 951         }
 952
 953         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
 954                 bigjoiner = true;
 955                 max_dotclk *= 2;
 956         }
 957
 958         if (DISPLAY_VER(dev_priv) >= 10 &&
 959             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 960                 /*
 961                  * TBD pass the connector BPC,
 962                  * for now U8_MAX so that max BPC on that platform would be picked
 963                  */
 964                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
 965
 966                 if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 967                         dsc_max_output_bpp =
 968                                 intel_dp_dsc_get_output_bpp(dev_priv,
 969                                                             max_link_clock,
 970                                                             max_lanes,
 971                                                             target_clock,
 972                                                             mode->hdisplay,
 973                                                             bigjoiner,
 974                                                             pipe_bpp, 64) >> 4;
 975                         dsc_slice_count =
 976                                 intel_dp_dsc_get_slice_count(intel_dp,
 977                                                              target_clock,
 978                                                              mode->hdisplay,
 979                                                              bigjoiner);
 980                 }
 981
 982                 dsc = dsc_max_output_bpp && dsc_slice_count;
 983         }
 984
 985         /*
 986          * Big joiner configuration needs DSC for TGL which is not true for
 987          * XE_LPD where uncompressed joiner is supported.
 988          */
 989         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
 990                 return MODE_CLOCK_HIGH;
 991
 992         if (mode_rate > max_rate && !dsc)
 993                 return MODE_CLOCK_HIGH;
 994
 995         *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
 996         return 0;
 997 }
 998
 999 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
1000                                                          struct drm_atomic_state *state)
1001 {
1002         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1003                                                                                          connector);
1004         struct intel_connector *intel_connector = to_intel_connector(connector);
1005         struct intel_dp *intel_dp = intel_connector->mst_port;
1006         struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
1007
1008         return &intel_dp->mst_encoders[crtc->pipe]->base.base;
1009 }
1010
1011 static int
1012 intel_dp_mst_detect(struct drm_connector *connector,
1013                     struct drm_modeset_acquire_ctx *ctx, bool force)
1014 {
1015         struct drm_i915_private *i915 = to_i915(connector->dev);
1016         struct intel_connector *intel_connector = to_intel_connector(connector);
1017         struct intel_dp *intel_dp = intel_connector->mst_port;
1018
1019         if (!INTEL_DISPLAY_ENABLED(i915))
1020                 return connector_status_disconnected;
1021
1022         if (drm_connector_is_unregistered(connector))
1023                 return connector_status_disconnected;
1024
1025         return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
1026                                       intel_connector->port);
1027 }
1028
1029 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
1030         .get_modes = intel_dp_mst_get_modes,
1031         .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
1032         .atomic_best_encoder = intel_mst_atomic_best_encoder,
1033         .atomic_check = intel_dp_mst_atomic_check,
1034         .detect_ctx = intel_dp_mst_detect,
1035 };
1036
1037 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
1038 {
1039         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
1040
1041         drm_encoder_cleanup(encoder);
1042         kfree(intel_mst);
1043 }
1044
1045 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
1046         .destroy = intel_dp_mst_encoder_destroy,
1047 };
1048
1049 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
1050 {
1051         if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1052                 enum pipe pipe;
1053                 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1054                         return false;
1055                 return true;
1056         }
1057         return false;
1058 }
1059
1060 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1061                                        struct drm_connector *connector,
1062                                        const char *pathprop)
1063 {
1064         struct drm_i915_private *i915 = to_i915(connector->dev);
1065
1066         drm_object_attach_property(&connector->base,
1067                                    i915->drm.mode_config.path_property, 0);
1068         drm_object_attach_property(&connector->base,
1069                                    i915->drm.mode_config.tile_property, 0);
1070
1071         intel_attach_force_audio_property(connector);
1072         intel_attach_broadcast_rgb_property(connector);
1073
1074         /*
1075          * Reuse the prop from the SST connector because we're
1076          * not allowed to create new props after device registration.
1077          */
1078         connector->max_bpc_property =
1079                 intel_dp->attached_connector->base.max_bpc_property;
1080         if (connector->max_bpc_property)
1081                 drm_connector_attach_max_bpc_property(connector, 6, 12);
1082
1083         return drm_connector_set_path_property(connector, pathprop);
1084 }
1085
1086 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1087                                                         struct drm_dp_mst_port *port,
1088                                                         const char *pathprop)
1089 {
1090         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1091         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1092         struct drm_device *dev = dig_port->base.base.dev;
1093         struct drm_i915_private *dev_priv = to_i915(dev);
1094         struct intel_connector *intel_connector;
1095         struct drm_connector *connector;
1096         enum pipe pipe;
1097         int ret;
1098
1099         intel_connector = intel_connector_alloc();
1100         if (!intel_connector)
1101                 return NULL;
1102
1103         intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1104         intel_connector->mst_port = intel_dp;
1105         intel_connector->port = port;
1106         drm_dp_mst_get_port_malloc(port);
1107
1108         connector = &intel_connector->base;
1109         ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1110                                  DRM_MODE_CONNECTOR_DisplayPort);
1111         if (ret) {
1112                 drm_dp_mst_put_port_malloc(port);
1113                 intel_connector_free(intel_connector);
1114                 return NULL;
1115         }
1116
1117         drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1118
1119         for_each_pipe(dev_priv, pipe) {
1120                 struct drm_encoder *enc =
1121                         &intel_dp->mst_encoders[pipe]->base.base;
1122
1123                 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1124                 if (ret)
1125                         goto err;
1126         }
1127
1128         ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1129         if (ret)
1130                 goto err;
1131
1132         ret = intel_dp_hdcp_init(dig_port, intel_connector);
1133         if (ret)
1134                 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1135                             connector->name, connector->base.id);
1136
1137         return connector;
1138
1139 err:
1140         drm_connector_cleanup(connector);
1141         return NULL;
1142 }
1143
1144 static void
1145 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1146 {
1147         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1148
1149         intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1150 }
1151
1152 static const struct drm_dp_mst_topology_cbs mst_cbs = {
1153         .add_connector = intel_dp_add_mst_connector,
1154         .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1155 };
1156
1157 static struct intel_dp_mst_encoder *
1158 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1159 {
1160         struct intel_dp_mst_encoder *intel_mst;
1161         struct intel_encoder *intel_encoder;
1162         struct drm_device *dev = dig_port->base.base.dev;
1163
1164         intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1165
1166         if (!intel_mst)
1167                 return NULL;
1168
1169         intel_mst->pipe = pipe;
1170         intel_encoder = &intel_mst->base;
1171         intel_mst->primary = dig_port;
1172
1173         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1174                          DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1175
1176         intel_encoder->type = INTEL_OUTPUT_DP_MST;
1177         intel_encoder->power_domain = dig_port->base.power_domain;
1178         intel_encoder->port = dig_port->base.port;
1179         intel_encoder->cloneable = 0;
1180         /*
1181          * This is wrong, but broken userspace uses the intersection
1182          * of possible_crtcs of all the encoders of a given connector
1183          * to figure out which crtcs can drive said connector. What
1184          * should be used instead is the union of possible_crtcs.
1185          * To keep such userspace functioning we must misconfigure
1186          * this to make sure the intersection is not empty :(
1187          */
1188         intel_encoder->pipe_mask = ~0;
1189
1190         intel_encoder->compute_config = intel_dp_mst_compute_config;
1191         intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1192         intel_encoder->disable = intel_mst_disable_dp;
1193         intel_encoder->post_disable = intel_mst_post_disable_dp;
1194         intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
1195         intel_encoder->update_pipe = intel_ddi_update_pipe;
1196         intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1197         intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1198         intel_encoder->enable = intel_mst_enable_dp;
1199         intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1200         intel_encoder->get_config = intel_dp_mst_enc_get_config;
1201         intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1202
1203         return intel_mst;
1204
1205 }
1206
1207 static bool
1208 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1209 {
1210         struct intel_dp *intel_dp = &dig_port->dp;
1211         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1212         enum pipe pipe;
1213
1214         for_each_pipe(dev_priv, pipe)
1215                 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1216         return true;
1217 }
1218
1219 int
1220 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1221 {
1222         return dig_port->dp.active_mst_links;
1223 }
1224
1225 int
1226 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1227 {
1228         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1229         struct intel_dp *intel_dp = &dig_port->dp;
1230         enum port port = dig_port->base.port;
1231         int ret;
1232
1233         if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1234                 return 0;
1235
1236         if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1237                 return 0;
1238
1239         if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1240                 return 0;
1241
1242         intel_dp->mst_mgr.cbs = &mst_cbs;
1243
1244         /* create encoders */
1245         intel_dp_create_fake_mst_encoders(dig_port);
1246         ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1247                                            &intel_dp->aux, 16, 3, conn_base_id);
1248         if (ret) {
1249                 intel_dp->mst_mgr.cbs = NULL;
1250                 return ret;
1251         }
1252
1253         return 0;
1254 }
1255
1256 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1257 {
1258         return intel_dp->mst_mgr.cbs;
1259 }
1260
1261 void
1262 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1263 {
1264         struct intel_dp *intel_dp = &dig_port->dp;
1265
1266         if (!intel_dp_mst_source_support(intel_dp))
1267                 return;
1268
1269         drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1270         /* encoders will get killed by normal cleanup */
1271
1272         intel_dp->mst_mgr.cbs = NULL;
1273 }
1274
1275 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1276 {
1277         return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1278 }
1279
1280 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1281 {
1282         return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1283                crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1284 }
1285
1286 /**
1287  * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1288  * @state: atomic state
1289  * @connector: connector to add the state for
1290  * @crtc: the CRTC @connector is attached to
1291  *
1292  * Add the MST topology state for @connector to @state.
1293  *
1294  * Returns 0 on success, negative error code on failure.
1295  */
1296 static int
1297 intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1298                                               struct intel_connector *connector,
1299                                               struct intel_crtc *crtc)
1300 {
1301         struct drm_dp_mst_topology_state *mst_state;
1302
1303         if (!connector->mst_port)
1304                 return 0;
1305
1306         mst_state = drm_atomic_get_mst_topology_state(&state->base,
1307                                                       &connector->mst_port->mst_mgr);
1308         if (IS_ERR(mst_state))
1309                 return PTR_ERR(mst_state);
1310
1311         mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1312
1313         return 0;
1314 }
1315
1316 /**
1317  * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1318  * @state: atomic state
1319  * @crtc: CRTC to add the state for
1320  *
1321  * Add the MST topology state for @crtc to @state.
1322  *
1323  * Returns 0 on success, negative error code on failure.
1324  */
1325 int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1326                                              struct intel_crtc *crtc)
1327 {
1328         struct drm_connector *_connector;
1329         struct drm_connector_state *conn_state;
1330         int i;
1331
1332         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1333                 struct intel_connector *connector = to_intel_connector(_connector);
1334                 int ret;
1335
1336                 if (conn_state->crtc != &crtc->base)
1337                         continue;
1338
1339                 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);
1340                 if (ret)
1341                         return ret;
1342         }
1343
1344         return 0;
1345 }