drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43
  44 #include "i915_debugfs.h"
  45 #include "i915_drv.h"
  46 #include "i915_trace.h"
  47 #include "intel_atomic.h"
  48 #include "intel_audio.h"
  49 #include "intel_connector.h"
  50 #include "intel_ddi.h"
  51 #include "intel_display_debugfs.h"
  52 #include "intel_display_types.h"
  53 #include "intel_dp.h"
  54 #include "intel_dp_link_training.h"
  55 #include "intel_dp_mst.h"
  56 #include "intel_dpio_phy.h"
  57 #include "intel_fifo_underrun.h"
  58 #include "intel_hdcp.h"
  59 #include "intel_hdmi.h"
  60 #include "intel_hotplug.h"
  61 #include "intel_lspcon.h"
  62 #include "intel_lvds.h"
  63 #include "intel_panel.h"
  64 #include "intel_psr.h"
  65 #include "intel_sideband.h"
  66 #include "intel_tc.h"
  67 #include "intel_vdsc.h"
  68
  69 #define DP_DPRX_ESI_LEN 14
  70
  71 /* DP DSC throughput values used for slice count calculations KPixels/s */
  72 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  73 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  74 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  75
  76 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  77 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  78
  79 /* Compliance test status bits  */
  80 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  81 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  82 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  83 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  84
  85 struct dp_link_dpll {
  86         int clock;
  87         struct dpll dpll;
  88 };
  89
  90 static const struct dp_link_dpll g4x_dpll[] = {
  91         { 162000,
  92                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  93         { 270000,
  94                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  95 };
  96
  97 static const struct dp_link_dpll pch_dpll[] = {
  98         { 162000,
  99                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 100         { 270000,
 101                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 102 };
 103
 104 static const struct dp_link_dpll vlv_dpll[] = {
 105         { 162000,
 106                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 107         { 270000,
 108                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 109 };
 110
 111 /*
 112  * CHV supports eDP 1.4 that have  more link rates.
 113  * Below only provides the fixed rate but exclude variable rate.
 114  */
 115 static const struct dp_link_dpll chv_dpll[] = {
 116         /*
 117          * CHV requires to program fractional division for m2.
 118          * m2 is stored in fixed point format using formula below
 119          * (m2_int << 22) | m2_fraction
 120          */
 121         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 122                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 123         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 124                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 125 };
 126
 127 /* Constants for DP DSC configurations */
 128 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 129
 130 /* With Single pipe configuration, HW is capable of supporting maximum
 131  * of 4 slices per line.
 132  */
 133 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 134
 135 /**
 136  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 137  * @intel_dp: DP struct
 138  *
 139  * If a CPU or PCH DP output is attached to an eDP panel, this function
 140  * will return true, and false otherwise.
 141  */
 142 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 143 {
 144         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 145
 146         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 147 }
 148
 149 static void intel_dp_link_down(struct intel_encoder *encoder,
 150                                const struct intel_crtc_state *old_crtc_state);
 151 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 152 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 153 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 154                                            const struct intel_crtc_state *crtc_state);
 155 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 156                                       enum pipe pipe);
 157 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 158
 159 /* update sink rates from dpcd */
 160 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 161 {
 162         static const int dp_rates[] = {
 163                 162000, 270000, 540000, 810000
 164         };
 165         int i, max_rate;
 166
 167         if (drm_dp_has_quirk(&intel_dp->desc, 0,
 168                              DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 169                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 170                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 171
 172                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 173                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 174
 175                 return;
 176         }
 177
 178         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 179
 180         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 181                 if (dp_rates[i] > max_rate)
 182                         break;
 183                 intel_dp->sink_rates[i] = dp_rates[i];
 184         }
 185
 186         intel_dp->num_sink_rates = i;
 187 }
 188
 189 /* Get length of rates array potentially limited by max_rate. */
 190 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 191 {
 192         int i;
 193
 194         /* Limit results by potentially reduced max rate */
 195         for (i = 0; i < len; i++) {
 196                 if (rates[len - i - 1] <= max_rate)
 197                         return len - i;
 198         }
 199
 200         return 0;
 201 }
 202
 203 /* Get length of common rates array potentially limited by max_rate. */
 204 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 205                                           int max_rate)
 206 {
 207         return intel_dp_rate_limit_len(intel_dp->common_rates,
 208                                        intel_dp->num_common_rates, max_rate);
 209 }
 210
 211 /* Theoretical max between source and sink */
 212 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 213 {
 214         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 215 }
 216
 217 /* Theoretical max between source and sink */
 218 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 219 {
 220         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 221         int source_max = intel_dig_port->max_lanes;
 222         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 223         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 224
 225         return min3(source_max, sink_max, fia_max);
 226 }
 227
 228 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 229 {
 230         return intel_dp->max_link_lane_count;
 231 }
 232
 233 int
 234 intel_dp_link_required(int pixel_clock, int bpp)
 235 {
 236         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 237         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 238 }
 239
 240 int
 241 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 242 {
 243         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 244          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 245          * is transmitted every LS_Clk per lane, there is no need to account for
 246          * the channel encoding that is done in the PHY layer here.
 247          */
 248
 249         return max_link_clock * max_lanes;
 250 }
 251
 252 static int
 253 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 254 {
 255         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 256         struct intel_encoder *encoder = &intel_dig_port->base;
 257         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 258         int max_dotclk = dev_priv->max_dotclk_freq;
 259         int ds_max_dotclk;
 260
 261         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 262
 263         if (type != DP_DS_PORT_TYPE_VGA)
 264                 return max_dotclk;
 265
 266         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 267                                                     intel_dp->downstream_ports);
 268
 269         if (ds_max_dotclk != 0)
 270                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 271
 272         return max_dotclk;
 273 }
 274
 275 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 276 {
 277         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 278         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 279         enum port port = dig_port->base.port;
 280
 281         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 282
 283         /* Low voltage SKUs are limited to max of 5.4G */
 284         if (voltage == VOLTAGE_INFO_0_85V)
 285                 return 540000;
 286
 287         /* For this SKU 8.1G is supported in all ports */
 288         if (IS_CNL_WITH_PORT_F(dev_priv))
 289                 return 810000;
 290
 291         /* For other SKUs, max rate on ports A and D is 5.4G */
 292         if (port == PORT_A || port == PORT_D)
 293                 return 540000;
 294
 295         return 810000;
 296 }
 297
 298 static int icl_max_source_rate(struct intel_dp *intel_dp)
 299 {
 300         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 301         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 302         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 303
 304         if (intel_phy_is_combo(dev_priv, phy) &&
 305             !IS_ELKHARTLAKE(dev_priv) &&
 306             !intel_dp_is_edp(intel_dp))
 307                 return 540000;
 308
 309         return 810000;
 310 }
 311
 312 static void
 313 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 314 {
 315         /* The values must be in increasing order */
 316         static const int cnl_rates[] = {
 317                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 318         };
 319         static const int bxt_rates[] = {
 320                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 321         };
 322         static const int skl_rates[] = {
 323                 162000, 216000, 270000, 324000, 432000, 540000
 324         };
 325         static const int hsw_rates[] = {
 326                 162000, 270000, 540000
 327         };
 328         static const int g4x_rates[] = {
 329                 162000, 270000
 330         };
 331         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 332         struct intel_encoder *encoder = &dig_port->base;
 333         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 334         const int *source_rates;
 335         int size, max_rate = 0, vbt_max_rate;
 336
 337         /* This should only be done once */
 338         drm_WARN_ON(&dev_priv->drm,
 339                     intel_dp->source_rates || intel_dp->num_source_rates);
 340
 341         if (INTEL_GEN(dev_priv) >= 10) {
 342                 source_rates = cnl_rates;
 343                 size = ARRAY_SIZE(cnl_rates);
 344                 if (IS_GEN(dev_priv, 10))
 345                         max_rate = cnl_max_source_rate(intel_dp);
 346                 else
 347                         max_rate = icl_max_source_rate(intel_dp);
 348         } else if (IS_GEN9_LP(dev_priv)) {
 349                 source_rates = bxt_rates;
 350                 size = ARRAY_SIZE(bxt_rates);
 351         } else if (IS_GEN9_BC(dev_priv)) {
 352                 source_rates = skl_rates;
 353                 size = ARRAY_SIZE(skl_rates);
 354         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 355                    IS_BROADWELL(dev_priv)) {
 356                 source_rates = hsw_rates;
 357                 size = ARRAY_SIZE(hsw_rates);
 358         } else {
 359                 source_rates = g4x_rates;
 360                 size = ARRAY_SIZE(g4x_rates);
 361         }
 362
 363         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 364         if (max_rate && vbt_max_rate)
 365                 max_rate = min(max_rate, vbt_max_rate);
 366         else if (vbt_max_rate)
 367                 max_rate = vbt_max_rate;
 368
 369         if (max_rate)
 370                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 371
 372         intel_dp->source_rates = source_rates;
 373         intel_dp->num_source_rates = size;
 374 }
 375
 376 static int intersect_rates(const int *source_rates, int source_len,
 377                            const int *sink_rates, int sink_len,
 378                            int *common_rates)
 379 {
 380         int i = 0, j = 0, k = 0;
 381
 382         while (i < source_len && j < sink_len) {
 383                 if (source_rates[i] == sink_rates[j]) {
 384                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 385                                 return k;
 386                         common_rates[k] = source_rates[i];
 387                         ++k;
 388                         ++i;
 389                         ++j;
 390                 } else if (source_rates[i] < sink_rates[j]) {
 391                         ++i;
 392                 } else {
 393                         ++j;
 394                 }
 395         }
 396         return k;
 397 }
 398
 399 /* return index of rate in rates array, or -1 if not found */
 400 static int intel_dp_rate_index(const int *rates, int len, int rate)
 401 {
 402         int i;
 403
 404         for (i = 0; i < len; i++)
 405                 if (rate == rates[i])
 406                         return i;
 407
 408         return -1;
 409 }
 410
 411 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 412 {
 413         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 414
 415         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 416                                                      intel_dp->num_source_rates,
 417                                                      intel_dp->sink_rates,
 418                                                      intel_dp->num_sink_rates,
 419                                                      intel_dp->common_rates);
 420
 421         /* Paranoia, there should always be something in common. */
 422         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 423                 intel_dp->common_rates[0] = 162000;
 424                 intel_dp->num_common_rates = 1;
 425         }
 426 }
 427
 428 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 429                                        u8 lane_count)
 430 {
 431         /*
 432          * FIXME: we need to synchronize the current link parameters with
 433          * hardware readout. Currently fast link training doesn't work on
 434          * boot-up.
 435          */
 436         if (link_rate == 0 ||
 437             link_rate > intel_dp->max_link_rate)
 438                 return false;
 439
 440         if (lane_count == 0 ||
 441             lane_count > intel_dp_max_lane_count(intel_dp))
 442                 return false;
 443
 444         return true;
 445 }
 446
 447 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 448                                                      int link_rate,
 449                                                      u8 lane_count)
 450 {
 451         const struct drm_display_mode *fixed_mode =
 452                 intel_dp->attached_connector->panel.fixed_mode;
 453         int mode_rate, max_rate;
 454
 455         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 456         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 457         if (mode_rate > max_rate)
 458                 return false;
 459
 460         return true;
 461 }
 462
 463 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 464                                             int link_rate, u8 lane_count)
 465 {
 466         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 467         int index;
 468
 469         index = intel_dp_rate_index(intel_dp->common_rates,
 470                                     intel_dp->num_common_rates,
 471                                     link_rate);
 472         if (index > 0) {
 473                 if (intel_dp_is_edp(intel_dp) &&
 474                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 475                                                               intel_dp->common_rates[index - 1],
 476                                                               lane_count)) {
 477                         drm_dbg_kms(&i915->drm,
 478                                     "Retrying Link training for eDP with same parameters\n");
 479                         return 0;
 480                 }
 481                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 482                 intel_dp->max_link_lane_count = lane_count;
 483         } else if (lane_count > 1) {
 484                 if (intel_dp_is_edp(intel_dp) &&
 485                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 486                                                               intel_dp_max_common_rate(intel_dp),
 487                                                               lane_count >> 1)) {
 488                         drm_dbg_kms(&i915->drm,
 489                                     "Retrying Link training for eDP with same parameters\n");
 490                         return 0;
 491                 }
 492                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 493                 intel_dp->max_link_lane_count = lane_count >> 1;
 494         } else {
 495                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 496                 return -1;
 497         }
 498
 499         return 0;
 500 }
 501
 502 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 503 {
 504         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 505                        DP_DSC_FEC_OVERHEAD_FACTOR);
 506 }
 507
 508 static int
 509 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 510 {
 511         if (INTEL_GEN(i915) >= 11)
 512                 return 7680 * 8;
 513         else
 514                 return 6144 * 8;
 515 }
 516
 517 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 518                                        u32 link_clock, u32 lane_count,
 519                                        u32 mode_clock, u32 mode_hdisplay)
 520 {
 521         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 522         int i;
 523
 524         /*
 525          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 526          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 527          * for SST -> TimeSlotsPerMTP is 1,
 528          * for MST -> TimeSlotsPerMTP has to be calculated
 529          */
 530         bits_per_pixel = (link_clock * lane_count * 8) /
 531                          intel_dp_mode_to_fec_clock(mode_clock);
 532         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 533
 534         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 535         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 536                 mode_hdisplay;
 537         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 538                     max_bpp_small_joiner_ram);
 539
 540         /*
 541          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 542          * check, output bpp from small joiner RAM check)
 543          */
 544         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 545
 546         /* Error out if the max bpp is less than smallest allowed valid bpp */
 547         if (bits_per_pixel < valid_dsc_bpp[0]) {
 548                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 549                             bits_per_pixel, valid_dsc_bpp[0]);
 550                 return 0;
 551         }
 552
 553         /* Find the nearest match in the array of known BPPs from VESA */
 554         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 555                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 556                         break;
 557         }
 558         bits_per_pixel = valid_dsc_bpp[i];
 559
 560         /*
 561          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 562          * fractional part is 0
 563          */
 564         return bits_per_pixel << 4;
 565 }
 566
 567 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 568                                        int mode_clock, int mode_hdisplay)
 569 {
 570         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 571         u8 min_slice_count, i;
 572         int max_slice_width;
 573
 574         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 575                 min_slice_count = DIV_ROUND_UP(mode_clock,
 576                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 577         else
 578                 min_slice_count = DIV_ROUND_UP(mode_clock,
 579                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 580
 581         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 582         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 583                 drm_dbg_kms(&i915->drm,
 584                             "Unsupported slice width %d by DP DSC Sink device\n",
 585                             max_slice_width);
 586                 return 0;
 587         }
 588         /* Also take into account max slice width */
 589         min_slice_count = min_t(u8, min_slice_count,
 590                                 DIV_ROUND_UP(mode_hdisplay,
 591                                              max_slice_width));
 592
 593         /* Find the closest match to the valid slice count values */
 594         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 595                 if (valid_dsc_slicecount[i] >
 596                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 597                                                     false))
 598                         break;
 599                 if (min_slice_count  <= valid_dsc_slicecount[i])
 600                         return valid_dsc_slicecount[i];
 601         }
 602
 603         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 604                     min_slice_count);
 605         return 0;
 606 }
 607
 608 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 609                                   int hdisplay)
 610 {
 611         /*
 612          * Older platforms don't like hdisplay==4096 with DP.
 613          *
 614          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 615          * and frame counter increment), but we don't get vblank interrupts,
 616          * and the pipe underruns immediately. The link also doesn't seem
 617          * to get trained properly.
 618          *
 619          * On CHV the vblank interrupts don't seem to disappear but
 620          * otherwise the symptoms are similar.
 621          *
 622          * TODO: confirm the behaviour on HSW+
 623          */
 624         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 625 }
 626
 627 static enum drm_mode_status
 628 intel_dp_mode_valid(struct drm_connector *connector,
 629                     struct drm_display_mode *mode)
 630 {
 631         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 632         struct intel_connector *intel_connector = to_intel_connector(connector);
 633         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 634         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 635         int target_clock = mode->clock;
 636         int max_rate, mode_rate, max_lanes, max_link_clock;
 637         int max_dotclk;
 638         u16 dsc_max_output_bpp = 0;
 639         u8 dsc_slice_count = 0;
 640
 641         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 642                 return MODE_NO_DBLESCAN;
 643
 644         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 645
 646         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 647                 if (mode->hdisplay > fixed_mode->hdisplay)
 648                         return MODE_PANEL;
 649
 650                 if (mode->vdisplay > fixed_mode->vdisplay)
 651                         return MODE_PANEL;
 652
 653                 target_clock = fixed_mode->clock;
 654         }
 655
 656         max_link_clock = intel_dp_max_link_rate(intel_dp);
 657         max_lanes = intel_dp_max_lane_count(intel_dp);
 658
 659         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 660         mode_rate = intel_dp_link_required(target_clock, 18);
 661
 662         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 663                 return MODE_H_ILLEGAL;
 664
 665         /*
 666          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 667          * integer value since we support only integer values of bpp.
 668          */
 669         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 670             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 671                 if (intel_dp_is_edp(intel_dp)) {
 672                         dsc_max_output_bpp =
 673                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 674                         dsc_slice_count =
 675                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 676                                                                 true);
 677                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 678                         dsc_max_output_bpp =
 679                                 intel_dp_dsc_get_output_bpp(dev_priv,
 680                                                             max_link_clock,
 681                                                             max_lanes,
 682                                                             target_clock,
 683                                                             mode->hdisplay) >> 4;
 684                         dsc_slice_count =
 685                                 intel_dp_dsc_get_slice_count(intel_dp,
 686                                                              target_clock,
 687                                                              mode->hdisplay);
 688                 }
 689         }
 690
 691         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 692             target_clock > max_dotclk)
 693                 return MODE_CLOCK_HIGH;
 694
 695         if (mode->clock < 10000)
 696                 return MODE_CLOCK_LOW;
 697
 698         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 699                 return MODE_H_ILLEGAL;
 700
 701         return intel_mode_valid_max_plane_size(dev_priv, mode);
 702 }
 703
 704 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 705 {
 706         int i;
 707         u32 v = 0;
 708
 709         if (src_bytes > 4)
 710                 src_bytes = 4;
 711         for (i = 0; i < src_bytes; i++)
 712                 v |= ((u32)src[i]) << ((3 - i) * 8);
 713         return v;
 714 }
 715
 716 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 717 {
 718         int i;
 719         if (dst_bytes > 4)
 720                 dst_bytes = 4;
 721         for (i = 0; i < dst_bytes; i++)
 722                 dst[i] = src >> ((3-i) * 8);
 723 }
 724
 725 static void
 726 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 727 static void
 728 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 729                                               bool force_disable_vdd);
 730 static void
 731 intel_dp_pps_init(struct intel_dp *intel_dp);
 732
 733 static intel_wakeref_t
 734 pps_lock(struct intel_dp *intel_dp)
 735 {
 736         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 737         intel_wakeref_t wakeref;
 738
 739         /*
 740          * See intel_power_sequencer_reset() why we need
 741          * a power domain reference here.
 742          */
 743         wakeref = intel_display_power_get(dev_priv,
 744                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 745
 746         mutex_lock(&dev_priv->pps_mutex);
 747
 748         return wakeref;
 749 }
 750
 751 static intel_wakeref_t
 752 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 753 {
 754         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 755
 756         mutex_unlock(&dev_priv->pps_mutex);
 757         intel_display_power_put(dev_priv,
 758                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 759                                 wakeref);
 760         return 0;
 761 }
 762
 763 #define with_pps_lock(dp, wf) \
 764         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 765
 766 static void
 767 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 768 {
 769         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 770         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 771         enum pipe pipe = intel_dp->pps_pipe;
 772         bool pll_enabled, release_cl_override = false;
 773         enum dpio_phy phy = DPIO_PHY(pipe);
 774         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 775         u32 DP;
 776
 777         if (drm_WARN(&dev_priv->drm,
 778                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 779                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 780                      pipe_name(pipe), intel_dig_port->base.base.base.id,
 781                      intel_dig_port->base.base.name))
 782                 return;
 783
 784         drm_dbg_kms(&dev_priv->drm,
 785                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 786                     pipe_name(pipe), intel_dig_port->base.base.base.id,
 787                     intel_dig_port->base.base.name);
 788
 789         /* Preserve the BIOS-computed detected bit. This is
 790          * supposed to be read-only.
 791          */
 792         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 793         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 794         DP |= DP_PORT_WIDTH(1);
 795         DP |= DP_LINK_TRAIN_PAT_1;
 796
 797         if (IS_CHERRYVIEW(dev_priv))
 798                 DP |= DP_PIPE_SEL_CHV(pipe);
 799         else
 800                 DP |= DP_PIPE_SEL(pipe);
 801
 802         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 803
 804         /*
 805          * The DPLL for the pipe must be enabled for this to work.
 806          * So enable temporarily it if it's not already enabled.
 807          */
 808         if (!pll_enabled) {
 809                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 810                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 811
 812                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 813                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 814                         drm_err(&dev_priv->drm,
 815                                 "Failed to force on pll for pipe %c!\n",
 816                                 pipe_name(pipe));
 817                         return;
 818                 }
 819         }
 820
 821         /*
 822          * Similar magic as in intel_dp_enable_port().
 823          * We _must_ do this port enable + disable trick
 824          * to make this power sequencer lock onto the port.
 825          * Otherwise even VDD force bit won't work.
 826          */
 827         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 828         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 829
 830         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 831         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 832
 833         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 834         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 835
 836         if (!pll_enabled) {
 837                 vlv_force_pll_off(dev_priv, pipe);
 838
 839                 if (release_cl_override)
 840                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 841         }
 842 }
 843
 844 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 845 {
 846         struct intel_encoder *encoder;
 847         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 848
 849         /*
 850          * We don't have power sequencer currently.
 851          * Pick one that's not used by other ports.
 852          */
 853         for_each_intel_dp(&dev_priv->drm, encoder) {
 854                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 855
 856                 if (encoder->type == INTEL_OUTPUT_EDP) {
 857                         drm_WARN_ON(&dev_priv->drm,
 858                                     intel_dp->active_pipe != INVALID_PIPE &&
 859                                     intel_dp->active_pipe !=
 860                                     intel_dp->pps_pipe);
 861
 862                         if (intel_dp->pps_pipe != INVALID_PIPE)
 863                                 pipes &= ~(1 << intel_dp->pps_pipe);
 864                 } else {
 865                         drm_WARN_ON(&dev_priv->drm,
 866                                     intel_dp->pps_pipe != INVALID_PIPE);
 867
 868                         if (intel_dp->active_pipe != INVALID_PIPE)
 869                                 pipes &= ~(1 << intel_dp->active_pipe);
 870                 }
 871         }
 872
 873         if (pipes == 0)
 874                 return INVALID_PIPE;
 875
 876         return ffs(pipes) - 1;
 877 }
 878
 879 static enum pipe
 880 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 881 {
 882         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 883         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 884         enum pipe pipe;
 885
 886         lockdep_assert_held(&dev_priv->pps_mutex);
 887
 888         /* We should never land here with regular DP ports */
 889         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 890
 891         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
 892                     intel_dp->active_pipe != intel_dp->pps_pipe);
 893
 894         if (intel_dp->pps_pipe != INVALID_PIPE)
 895                 return intel_dp->pps_pipe;
 896
 897         pipe = vlv_find_free_pps(dev_priv);
 898
 899         /*
 900          * Didn't find one. This should not happen since there
 901          * are two power sequencers and up to two eDP ports.
 902          */
 903         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
 904                 pipe = PIPE_A;
 905
 906         vlv_steal_power_sequencer(dev_priv, pipe);
 907         intel_dp->pps_pipe = pipe;
 908
 909         drm_dbg_kms(&dev_priv->drm,
 910                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 911                     pipe_name(intel_dp->pps_pipe),
 912                     intel_dig_port->base.base.base.id,
 913                     intel_dig_port->base.base.name);
 914
 915         /* init power sequencer on this pipe and port */
 916         intel_dp_init_panel_power_sequencer(intel_dp);
 917         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 918
 919         /*
 920          * Even vdd force doesn't work until we've made
 921          * the power sequencer lock in on the port.
 922          */
 923         vlv_power_sequencer_kick(intel_dp);
 924
 925         return intel_dp->pps_pipe;
 926 }
 927
 928 static int
 929 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 930 {
 931         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 932         int backlight_controller = dev_priv->vbt.backlight.controller;
 933
 934         lockdep_assert_held(&dev_priv->pps_mutex);
 935
 936         /* We should never land here with regular DP ports */
 937         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
 938
 939         if (!intel_dp->pps_reset)
 940                 return backlight_controller;
 941
 942         intel_dp->pps_reset = false;
 943
 944         /*
 945          * Only the HW needs to be reprogrammed, the SW state is fixed and
 946          * has been setup during connector init.
 947          */
 948         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 949
 950         return backlight_controller;
 951 }
 952
 953 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 954                                enum pipe pipe);
 955
 956 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 957                                enum pipe pipe)
 958 {
 959         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
 960 }
 961
 962 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 963                                 enum pipe pipe)
 964 {
 965         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 966 }
 967
 968 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 969                          enum pipe pipe)
 970 {
 971         return true;
 972 }
 973
 974 static enum pipe
 975 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 976                      enum port port,
 977                      vlv_pipe_check pipe_check)
 978 {
 979         enum pipe pipe;
 980
 981         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 982                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
 983                         PANEL_PORT_SELECT_MASK;
 984
 985                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 986                         continue;
 987
 988                 if (!pipe_check(dev_priv, pipe))
 989                         continue;
 990
 991                 return pipe;
 992         }
 993
 994         return INVALID_PIPE;
 995 }
 996
 997 static void
 998 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 999 {
1000         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1001         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1002         enum port port = intel_dig_port->base.port;
1003
1004         lockdep_assert_held(&dev_priv->pps_mutex);
1005
1006         /* try to find a pipe with this port selected */
1007         /* first pick one where the panel is on */
1008         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1009                                                   vlv_pipe_has_pp_on);
1010         /* didn't find one? pick one where vdd is on */
1011         if (intel_dp->pps_pipe == INVALID_PIPE)
1012                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1013                                                           vlv_pipe_has_vdd_on);
1014         /* didn't find one? pick one with just the correct port */
1015         if (intel_dp->pps_pipe == INVALID_PIPE)
1016                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1017                                                           vlv_pipe_any);
1018
1019         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1020         if (intel_dp->pps_pipe == INVALID_PIPE) {
1021                 drm_dbg_kms(&dev_priv->drm,
1022                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1023                             intel_dig_port->base.base.base.id,
1024                             intel_dig_port->base.base.name);
1025                 return;
1026         }
1027
1028         drm_dbg_kms(&dev_priv->drm,
1029                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1030                     intel_dig_port->base.base.base.id,
1031                     intel_dig_port->base.base.name,
1032                     pipe_name(intel_dp->pps_pipe));
1033
1034         intel_dp_init_panel_power_sequencer(intel_dp);
1035         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1036 }
1037
1038 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1039 {
1040         struct intel_encoder *encoder;
1041
1042         if (drm_WARN_ON(&dev_priv->drm,
1043                         !(IS_VALLEYVIEW(dev_priv) ||
1044                           IS_CHERRYVIEW(dev_priv) ||
1045                           IS_GEN9_LP(dev_priv))))
1046                 return;
1047
1048         /*
1049          * We can't grab pps_mutex here due to deadlock with power_domain
1050          * mutex when power_domain functions are called while holding pps_mutex.
1051          * That also means that in order to use pps_pipe the code needs to
1052          * hold both a power domain reference and pps_mutex, and the power domain
1053          * reference get/put must be done while _not_ holding pps_mutex.
1054          * pps_{lock,unlock}() do these steps in the correct order, so one
1055          * should use them always.
1056          */
1057
1058         for_each_intel_dp(&dev_priv->drm, encoder) {
1059                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1060
1061                 drm_WARN_ON(&dev_priv->drm,
1062                             intel_dp->active_pipe != INVALID_PIPE);
1063
1064                 if (encoder->type != INTEL_OUTPUT_EDP)
1065                         continue;
1066
1067                 if (IS_GEN9_LP(dev_priv))
1068                         intel_dp->pps_reset = true;
1069                 else
1070                         intel_dp->pps_pipe = INVALID_PIPE;
1071         }
1072 }
1073
1074 struct pps_registers {
1075         i915_reg_t pp_ctrl;
1076         i915_reg_t pp_stat;
1077         i915_reg_t pp_on;
1078         i915_reg_t pp_off;
1079         i915_reg_t pp_div;
1080 };
1081
1082 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1083                                     struct pps_registers *regs)
1084 {
1085         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1086         int pps_idx = 0;
1087
1088         memset(regs, 0, sizeof(*regs));
1089
1090         if (IS_GEN9_LP(dev_priv))
1091                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1092         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1093                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1094
1095         regs->pp_ctrl = PP_CONTROL(pps_idx);
1096         regs->pp_stat = PP_STATUS(pps_idx);
1097         regs->pp_on = PP_ON_DELAYS(pps_idx);
1098         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1099
1100         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1101         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1102                 regs->pp_div = INVALID_MMIO_REG;
1103         else
1104                 regs->pp_div = PP_DIVISOR(pps_idx);
1105 }
1106
1107 static i915_reg_t
1108 _pp_ctrl_reg(struct intel_dp *intel_dp)
1109 {
1110         struct pps_registers regs;
1111
1112         intel_pps_get_registers(intel_dp, &regs);
1113
1114         return regs.pp_ctrl;
1115 }
1116
1117 static i915_reg_t
1118 _pp_stat_reg(struct intel_dp *intel_dp)
1119 {
1120         struct pps_registers regs;
1121
1122         intel_pps_get_registers(intel_dp, &regs);
1123
1124         return regs.pp_stat;
1125 }
1126
1127 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1128    This function only applicable when panel PM state is not to be tracked */
1129 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1130                               void *unused)
1131 {
1132         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1133                                                  edp_notifier);
1134         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1135         intel_wakeref_t wakeref;
1136
1137         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1138                 return 0;
1139
1140         with_pps_lock(intel_dp, wakeref) {
1141                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1142                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1143                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1144                         u32 pp_div;
1145
1146                         pp_ctrl_reg = PP_CONTROL(pipe);
1147                         pp_div_reg  = PP_DIVISOR(pipe);
1148                         pp_div = intel_de_read(dev_priv, pp_div_reg);
1149                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1150
1151                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1152                         intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
1153                         intel_de_write(dev_priv, pp_ctrl_reg,
1154                                        PANEL_UNLOCK_REGS);
1155                         msleep(intel_dp->panel_power_cycle_delay);
1156                 }
1157         }
1158
1159         return 0;
1160 }
1161
1162 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1163 {
1164         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1165
1166         lockdep_assert_held(&dev_priv->pps_mutex);
1167
1168         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1169             intel_dp->pps_pipe == INVALID_PIPE)
1170                 return false;
1171
1172         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1173 }
1174
1175 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1176 {
1177         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1178
1179         lockdep_assert_held(&dev_priv->pps_mutex);
1180
1181         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1182             intel_dp->pps_pipe == INVALID_PIPE)
1183                 return false;
1184
1185         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1186 }
1187
1188 static void
1189 intel_dp_check_edp(struct intel_dp *intel_dp)
1190 {
1191         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1192
1193         if (!intel_dp_is_edp(intel_dp))
1194                 return;
1195
1196         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1197                 drm_WARN(&dev_priv->drm, 1,
1198                          "eDP powered off while attempting aux channel communication.\n");
1199                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1200                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1201                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1202         }
1203 }
1204
1205 static u32
1206 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1207 {
1208         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1209         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1210         const unsigned int timeout_ms = 10;
1211         u32 status;
1212         bool done;
1213
1214 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1215         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1216                                   msecs_to_jiffies_timeout(timeout_ms));
1217
1218         /* just trace the final value */
1219         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1220
1221         if (!done)
1222                 drm_err(&i915->drm,
1223                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1224                         intel_dp->aux.name, timeout_ms, status);
1225 #undef C
1226
1227         return status;
1228 }
1229
1230 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1231 {
1232         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1233
1234         if (index)
1235                 return 0;
1236
1237         /*
1238          * The clock divider is based off the hrawclk, and would like to run at
1239          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1240          */
1241         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1242 }
1243
1244 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1245 {
1246         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1247         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1248         u32 freq;
1249
1250         if (index)
1251                 return 0;
1252
1253         /*
1254          * The clock divider is based off the cdclk or PCH rawclk, and would
1255          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1256          * divide by 2000 and use that
1257          */
1258         if (dig_port->aux_ch == AUX_CH_A)
1259                 freq = dev_priv->cdclk.hw.cdclk;
1260         else
1261                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1262         return DIV_ROUND_CLOSEST(freq, 2000);
1263 }
1264
1265 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1266 {
1267         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1268         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1269
1270         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1271                 /* Workaround for non-ULT HSW */
1272                 switch (index) {
1273                 case 0: return 63;
1274                 case 1: return 72;
1275                 default: return 0;
1276                 }
1277         }
1278
1279         return ilk_get_aux_clock_divider(intel_dp, index);
1280 }
1281
1282 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1283 {
1284         /*
1285          * SKL doesn't need us to program the AUX clock divider (Hardware will
1286          * derive the clock from CDCLK automatically). We still implement the
1287          * get_aux_clock_divider vfunc to plug-in into the existing code.
1288          */
1289         return index ? 0 : 1;
1290 }
1291
1292 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1293                                 int send_bytes,
1294                                 u32 aux_clock_divider)
1295 {
1296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1297         struct drm_i915_private *dev_priv =
1298                         to_i915(intel_dig_port->base.base.dev);
1299         u32 precharge, timeout;
1300
1301         if (IS_GEN(dev_priv, 6))
1302                 precharge = 3;
1303         else
1304                 precharge = 5;
1305
1306         if (IS_BROADWELL(dev_priv))
1307                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1308         else
1309                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1310
1311         return DP_AUX_CH_CTL_SEND_BUSY |
1312                DP_AUX_CH_CTL_DONE |
1313                DP_AUX_CH_CTL_INTERRUPT |
1314                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1315                timeout |
1316                DP_AUX_CH_CTL_RECEIVE_ERROR |
1317                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1318                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1319                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1320 }
1321
1322 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1323                                 int send_bytes,
1324                                 u32 unused)
1325 {
1326         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1327         struct drm_i915_private *i915 =
1328                         to_i915(intel_dig_port->base.base.dev);
1329         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1330         u32 ret;
1331
1332         ret = DP_AUX_CH_CTL_SEND_BUSY |
1333               DP_AUX_CH_CTL_DONE |
1334               DP_AUX_CH_CTL_INTERRUPT |
1335               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1336               DP_AUX_CH_CTL_TIME_OUT_MAX |
1337               DP_AUX_CH_CTL_RECEIVE_ERROR |
1338               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1339               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1340               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1341
1342         if (intel_phy_is_tc(i915, phy) &&
1343             intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1344                 ret |= DP_AUX_CH_CTL_TBT_IO;
1345
1346         return ret;
1347 }
1348
1349 static int
1350 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1351                   const u8 *send, int send_bytes,
1352                   u8 *recv, int recv_size,
1353                   u32 aux_send_ctl_flags)
1354 {
1355         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1356         struct drm_i915_private *i915 =
1357                         to_i915(intel_dig_port->base.base.dev);
1358         struct intel_uncore *uncore = &i915->uncore;
1359         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1360         bool is_tc_port = intel_phy_is_tc(i915, phy);
1361         i915_reg_t ch_ctl, ch_data[5];
1362         u32 aux_clock_divider;
1363         enum intel_display_power_domain aux_domain =
1364                 intel_aux_power_domain(intel_dig_port);
1365         intel_wakeref_t aux_wakeref;
1366         intel_wakeref_t pps_wakeref;
1367         int i, ret, recv_bytes;
1368         int try, clock = 0;
1369         u32 status;
1370         bool vdd;
1371
1372         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1373         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1374                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1375
1376         if (is_tc_port)
1377                 intel_tc_port_lock(intel_dig_port);
1378
1379         aux_wakeref = intel_display_power_get(i915, aux_domain);
1380         pps_wakeref = pps_lock(intel_dp);
1381
1382         /*
1383          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1384          * In such cases we want to leave VDD enabled and it's up to upper layers
1385          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1386          * ourselves.
1387          */
1388         vdd = edp_panel_vdd_on(intel_dp);
1389
1390         /* dp aux is extremely sensitive to irq latency, hence request the
1391          * lowest possible wakeup latency and so prevent the cpu from going into
1392          * deep sleep states.
1393          */
1394         cpu_latency_qos_update_request(&i915->pm_qos, 0);
1395
1396         intel_dp_check_edp(intel_dp);
1397
1398         /* Try to wait for any previous AUX channel activity */
1399         for (try = 0; try < 3; try++) {
1400                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1401                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1402                         break;
1403                 msleep(1);
1404         }
1405         /* just trace the final value */
1406         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1407
1408         if (try == 3) {
1409                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1410
1411                 if (status != intel_dp->aux_busy_last_status) {
1412                         drm_WARN(&i915->drm, 1,
1413                                  "%s: not started (status 0x%08x)\n",
1414                                  intel_dp->aux.name, status);
1415                         intel_dp->aux_busy_last_status = status;
1416                 }
1417
1418                 ret = -EBUSY;
1419                 goto out;
1420         }
1421
1422         /* Only 5 data registers! */
1423         if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1424                 ret = -E2BIG;
1425                 goto out;
1426         }
1427
1428         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1429                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1430                                                           send_bytes,
1431                                                           aux_clock_divider);
1432
1433                 send_ctl |= aux_send_ctl_flags;
1434
1435                 /* Must try at least 3 times according to DP spec */
1436                 for (try = 0; try < 5; try++) {
1437                         /* Load the send data into the aux channel data registers */
1438                         for (i = 0; i < send_bytes; i += 4)
1439                                 intel_uncore_write(uncore,
1440                                                    ch_data[i >> 2],
1441                                                    intel_dp_pack_aux(send + i,
1442                                                                      send_bytes - i));
1443
1444                         /* Send the command and wait for it to complete */
1445                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1446
1447                         status = intel_dp_aux_wait_done(intel_dp);
1448
1449                         /* Clear done status and any errors */
1450                         intel_uncore_write(uncore,
1451                                            ch_ctl,
1452                                            status |
1453                                            DP_AUX_CH_CTL_DONE |
1454                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1455                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1456
1457                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1458                          *   400us delay required for errors and timeouts
1459                          *   Timeout errors from the HW already meet this
1460                          *   requirement so skip to next iteration
1461                          */
1462                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1463                                 continue;
1464
1465                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1466                                 usleep_range(400, 500);
1467                                 continue;
1468                         }
1469                         if (status & DP_AUX_CH_CTL_DONE)
1470                                 goto done;
1471                 }
1472         }
1473
1474         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1475                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1476                         intel_dp->aux.name, status);
1477                 ret = -EBUSY;
1478                 goto out;
1479         }
1480
1481 done:
1482         /* Check for timeout or receive error.
1483          * Timeouts occur when the sink is not connected
1484          */
1485         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1486                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1487                         intel_dp->aux.name, status);
1488                 ret = -EIO;
1489                 goto out;
1490         }
1491
1492         /* Timeouts occur when the device isn't connected, so they're
1493          * "normal" -- don't fill the kernel log with these */
1494         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1495                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1496                             intel_dp->aux.name, status);
1497                 ret = -ETIMEDOUT;
1498                 goto out;
1499         }
1500
1501         /* Unload any bytes sent back from the other side */
1502         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1503                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1504
1505         /*
1506          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1507          * We have no idea of what happened so we return -EBUSY so
1508          * drm layer takes care for the necessary retries.
1509          */
1510         if (recv_bytes == 0 || recv_bytes > 20) {
1511                 drm_dbg_kms(&i915->drm,
1512                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1513                             intel_dp->aux.name, recv_bytes);
1514                 ret = -EBUSY;
1515                 goto out;
1516         }
1517
1518         if (recv_bytes > recv_size)
1519                 recv_bytes = recv_size;
1520
1521         for (i = 0; i < recv_bytes; i += 4)
1522                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1523                                     recv + i, recv_bytes - i);
1524
1525         ret = recv_bytes;
1526 out:
1527         cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1528
1529         if (vdd)
1530                 edp_panel_vdd_off(intel_dp, false);
1531
1532         pps_unlock(intel_dp, pps_wakeref);
1533         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1534
1535         if (is_tc_port)
1536                 intel_tc_port_unlock(intel_dig_port);
1537
1538         return ret;
1539 }
1540
1541 #define BARE_ADDRESS_SIZE       3
1542 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1543
1544 static void
1545 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1546                     const struct drm_dp_aux_msg *msg)
1547 {
1548         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1549         txbuf[1] = (msg->address >> 8) & 0xff;
1550         txbuf[2] = msg->address & 0xff;
1551         txbuf[3] = msg->size - 1;
1552 }
1553
1554 static ssize_t
1555 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1556 {
1557         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1558         u8 txbuf[20], rxbuf[20];
1559         size_t txsize, rxsize;
1560         int ret;
1561
1562         intel_dp_aux_header(txbuf, msg);
1563
1564         switch (msg->request & ~DP_AUX_I2C_MOT) {
1565         case DP_AUX_NATIVE_WRITE:
1566         case DP_AUX_I2C_WRITE:
1567         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1568                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1569                 rxsize = 2; /* 0 or 1 data bytes */
1570
1571                 if (WARN_ON(txsize > 20))
1572                         return -E2BIG;
1573
1574                 WARN_ON(!msg->buffer != !msg->size);
1575
1576                 if (msg->buffer)
1577                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1578
1579                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1580                                         rxbuf, rxsize, 0);
1581                 if (ret > 0) {
1582                         msg->reply = rxbuf[0] >> 4;
1583
1584                         if (ret > 1) {
1585                                 /* Number of bytes written in a short write. */
1586                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1587                         } else {
1588                                 /* Return payload size. */
1589                                 ret = msg->size;
1590                         }
1591                 }
1592                 break;
1593
1594         case DP_AUX_NATIVE_READ:
1595         case DP_AUX_I2C_READ:
1596                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1597                 rxsize = msg->size + 1;
1598
1599                 if (WARN_ON(rxsize > 20))
1600                         return -E2BIG;
1601
1602                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1603                                         rxbuf, rxsize, 0);
1604                 if (ret > 0) {
1605                         msg->reply = rxbuf[0] >> 4;
1606                         /*
1607                          * Assume happy day, and copy the data. The caller is
1608                          * expected to check msg->reply before touching it.
1609                          *
1610                          * Return payload size.
1611                          */
1612                         ret--;
1613                         memcpy(msg->buffer, rxbuf + 1, ret);
1614                 }
1615                 break;
1616
1617         default:
1618                 ret = -EINVAL;
1619                 break;
1620         }
1621
1622         return ret;
1623 }
1624
1625
1626 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1627 {
1628         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1629         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1630         enum aux_ch aux_ch = dig_port->aux_ch;
1631
1632         switch (aux_ch) {
1633         case AUX_CH_B:
1634         case AUX_CH_C:
1635         case AUX_CH_D:
1636                 return DP_AUX_CH_CTL(aux_ch);
1637         default:
1638                 MISSING_CASE(aux_ch);
1639                 return DP_AUX_CH_CTL(AUX_CH_B);
1640         }
1641 }
1642
1643 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1644 {
1645         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1646         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1647         enum aux_ch aux_ch = dig_port->aux_ch;
1648
1649         switch (aux_ch) {
1650         case AUX_CH_B:
1651         case AUX_CH_C:
1652         case AUX_CH_D:
1653                 return DP_AUX_CH_DATA(aux_ch, index);
1654         default:
1655                 MISSING_CASE(aux_ch);
1656                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1657         }
1658 }
1659
1660 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1661 {
1662         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1663         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1664         enum aux_ch aux_ch = dig_port->aux_ch;
1665
1666         switch (aux_ch) {
1667         case AUX_CH_A:
1668                 return DP_AUX_CH_CTL(aux_ch);
1669         case AUX_CH_B:
1670         case AUX_CH_C:
1671         case AUX_CH_D:
1672                 return PCH_DP_AUX_CH_CTL(aux_ch);
1673         default:
1674                 MISSING_CASE(aux_ch);
1675                 return DP_AUX_CH_CTL(AUX_CH_A);
1676         }
1677 }
1678
1679 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1680 {
1681         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1682         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1683         enum aux_ch aux_ch = dig_port->aux_ch;
1684
1685         switch (aux_ch) {
1686         case AUX_CH_A:
1687                 return DP_AUX_CH_DATA(aux_ch, index);
1688         case AUX_CH_B:
1689         case AUX_CH_C:
1690         case AUX_CH_D:
1691                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1692         default:
1693                 MISSING_CASE(aux_ch);
1694                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1695         }
1696 }
1697
1698 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1699 {
1700         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1701         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1702         enum aux_ch aux_ch = dig_port->aux_ch;
1703
1704         switch (aux_ch) {
1705         case AUX_CH_A:
1706         case AUX_CH_B:
1707         case AUX_CH_C:
1708         case AUX_CH_D:
1709         case AUX_CH_E:
1710         case AUX_CH_F:
1711         case AUX_CH_G:
1712                 return DP_AUX_CH_CTL(aux_ch);
1713         default:
1714                 MISSING_CASE(aux_ch);
1715                 return DP_AUX_CH_CTL(AUX_CH_A);
1716         }
1717 }
1718
1719 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1720 {
1721         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1722         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1723         enum aux_ch aux_ch = dig_port->aux_ch;
1724
1725         switch (aux_ch) {
1726         case AUX_CH_A:
1727         case AUX_CH_B:
1728         case AUX_CH_C:
1729         case AUX_CH_D:
1730         case AUX_CH_E:
1731         case AUX_CH_F:
1732         case AUX_CH_G:
1733                 return DP_AUX_CH_DATA(aux_ch, index);
1734         default:
1735                 MISSING_CASE(aux_ch);
1736                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1737         }
1738 }
1739
1740 static void
1741 intel_dp_aux_fini(struct intel_dp *intel_dp)
1742 {
1743         kfree(intel_dp->aux.name);
1744 }
1745
1746 static void
1747 intel_dp_aux_init(struct intel_dp *intel_dp)
1748 {
1749         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1750         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1751         struct intel_encoder *encoder = &dig_port->base;
1752
1753         if (INTEL_GEN(dev_priv) >= 9) {
1754                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1755                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1756         } else if (HAS_PCH_SPLIT(dev_priv)) {
1757                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1758                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1759         } else {
1760                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1761                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1762         }
1763
1764         if (INTEL_GEN(dev_priv) >= 9)
1765                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1766         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1767                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1768         else if (HAS_PCH_SPLIT(dev_priv))
1769                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1770         else
1771                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1772
1773         if (INTEL_GEN(dev_priv) >= 9)
1774                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1775         else
1776                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1777
1778         drm_dp_aux_init(&intel_dp->aux);
1779
1780         /* Failure to allocate our preferred name is not critical */
1781         intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
1782                                        aux_ch_name(dig_port->aux_ch),
1783                                        port_name(encoder->port));
1784         intel_dp->aux.transfer = intel_dp_aux_transfer;
1785 }
1786
1787 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1788 {
1789         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1790
1791         return max_rate >= 540000;
1792 }
1793
1794 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1795 {
1796         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1797
1798         return max_rate >= 810000;
1799 }
1800
1801 static void
1802 intel_dp_set_clock(struct intel_encoder *encoder,
1803                    struct intel_crtc_state *pipe_config)
1804 {
1805         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1806         const struct dp_link_dpll *divisor = NULL;
1807         int i, count = 0;
1808
1809         if (IS_G4X(dev_priv)) {
1810                 divisor = g4x_dpll;
1811                 count = ARRAY_SIZE(g4x_dpll);
1812         } else if (HAS_PCH_SPLIT(dev_priv)) {
1813                 divisor = pch_dpll;
1814                 count = ARRAY_SIZE(pch_dpll);
1815         } else if (IS_CHERRYVIEW(dev_priv)) {
1816                 divisor = chv_dpll;
1817                 count = ARRAY_SIZE(chv_dpll);
1818         } else if (IS_VALLEYVIEW(dev_priv)) {
1819                 divisor = vlv_dpll;
1820                 count = ARRAY_SIZE(vlv_dpll);
1821         }
1822
1823         if (divisor && count) {
1824                 for (i = 0; i < count; i++) {
1825                         if (pipe_config->port_clock == divisor[i].clock) {
1826                                 pipe_config->dpll = divisor[i].dpll;
1827                                 pipe_config->clock_set = true;
1828                                 break;
1829                         }
1830                 }
1831         }
1832 }
1833
1834 static void snprintf_int_array(char *str, size_t len,
1835                                const int *array, int nelem)
1836 {
1837         int i;
1838
1839         str[0] = '\0';
1840
1841         for (i = 0; i < nelem; i++) {
1842                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1843                 if (r >= len)
1844                         return;
1845                 str += r;
1846                 len -= r;
1847         }
1848 }
1849
1850 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1851 {
1852         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1853         char str[128]; /* FIXME: too big for stack? */
1854
1855         if (!drm_debug_enabled(DRM_UT_KMS))
1856                 return;
1857
1858         snprintf_int_array(str, sizeof(str),
1859                            intel_dp->source_rates, intel_dp->num_source_rates);
1860         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1861
1862         snprintf_int_array(str, sizeof(str),
1863                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1864         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1865
1866         snprintf_int_array(str, sizeof(str),
1867                            intel_dp->common_rates, intel_dp->num_common_rates);
1868         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1869 }
1870
1871 int
1872 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1873 {
1874         int len;
1875
1876         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1877         if (WARN_ON(len <= 0))
1878                 return 162000;
1879
1880         return intel_dp->common_rates[len - 1];
1881 }
1882
1883 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1884 {
1885         int i = intel_dp_rate_index(intel_dp->sink_rates,
1886                                     intel_dp->num_sink_rates, rate);
1887
1888         if (WARN_ON(i < 0))
1889                 i = 0;
1890
1891         return i;
1892 }
1893
1894 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1895                            u8 *link_bw, u8 *rate_select)
1896 {
1897         /* eDP 1.4 rate select method. */
1898         if (intel_dp->use_rate_select) {
1899                 *link_bw = 0;
1900                 *rate_select =
1901                         intel_dp_rate_select(intel_dp, port_clock);
1902         } else {
1903                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1904                 *rate_select = 0;
1905         }
1906 }
1907
1908 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1909                                          const struct intel_crtc_state *pipe_config)
1910 {
1911         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1912
1913         /* On TGL, FEC is supported on all Pipes */
1914         if (INTEL_GEN(dev_priv) >= 12)
1915                 return true;
1916
1917         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1918                 return true;
1919
1920         return false;
1921 }
1922
1923 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1924                                   const struct intel_crtc_state *pipe_config)
1925 {
1926         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1927                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1928 }
1929
1930 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1931                                   const struct intel_crtc_state *crtc_state)
1932 {
1933         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1934
1935         if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1936                 return false;
1937
1938         return intel_dsc_source_support(encoder, crtc_state) &&
1939                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1940 }
1941
1942 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1943                                 struct intel_crtc_state *pipe_config)
1944 {
1945         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1946         struct intel_connector *intel_connector = intel_dp->attached_connector;
1947         int bpp, bpc;
1948
1949         bpp = pipe_config->pipe_bpp;
1950         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1951
1952         if (bpc > 0)
1953                 bpp = min(bpp, 3*bpc);
1954
1955         if (intel_dp_is_edp(intel_dp)) {
1956                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1957                 if (intel_connector->base.display_info.bpc == 0 &&
1958                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1959                         drm_dbg_kms(&dev_priv->drm,
1960                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1961                                     dev_priv->vbt.edp.bpp);
1962                         bpp = dev_priv->vbt.edp.bpp;
1963                 }
1964         }
1965
1966         return bpp;
1967 }
1968
1969 /* Adjust link config limits based on compliance test requests. */
1970 void
1971 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1972                                   struct intel_crtc_state *pipe_config,
1973                                   struct link_config_limits *limits)
1974 {
1975         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1976
1977         /* For DP Compliance we override the computed bpp for the pipe */
1978         if (intel_dp->compliance.test_data.bpc != 0) {
1979                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1980
1981                 limits->min_bpp = limits->max_bpp = bpp;
1982                 pipe_config->dither_force_disable = bpp == 6 * 3;
1983
1984                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1985         }
1986
1987         /* Use values requested by Compliance Test Request */
1988         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1989                 int index;
1990
1991                 /* Validate the compliance test data since max values
1992                  * might have changed due to link train fallback.
1993                  */
1994                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1995                                                intel_dp->compliance.test_lane_count)) {
1996                         index = intel_dp_rate_index(intel_dp->common_rates,
1997                                                     intel_dp->num_common_rates,
1998                                                     intel_dp->compliance.test_link_rate);
1999                         if (index >= 0)
2000                                 limits->min_clock = limits->max_clock = index;
2001                         limits->min_lane_count = limits->max_lane_count =
2002                                 intel_dp->compliance.test_lane_count;
2003                 }
2004         }
2005 }
2006
2007 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
2008 {
2009         /*
2010          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
2011          * format of the number of bytes per pixel will be half the number
2012          * of bytes of RGB pixel.
2013          */
2014         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2015                 bpp /= 2;
2016
2017         return bpp;
2018 }
2019
2020 /* Optimize link config in order: max bpp, min clock, min lanes */
2021 static int
2022 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2023                                   struct intel_crtc_state *pipe_config,
2024                                   const struct link_config_limits *limits)
2025 {
2026         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2027         int bpp, clock, lane_count;
2028         int mode_rate, link_clock, link_avail;
2029
2030         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2031                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2032
2033                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2034                                                    output_bpp);
2035
2036                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2037                         for (lane_count = limits->min_lane_count;
2038                              lane_count <= limits->max_lane_count;
2039                              lane_count <<= 1) {
2040                                 link_clock = intel_dp->common_rates[clock];
2041                                 link_avail = intel_dp_max_data_rate(link_clock,
2042                                                                     lane_count);
2043
2044                                 if (mode_rate <= link_avail) {
2045                                         pipe_config->lane_count = lane_count;
2046                                         pipe_config->pipe_bpp = bpp;
2047                                         pipe_config->port_clock = link_clock;
2048
2049                                         return 0;
2050                                 }
2051                         }
2052                 }
2053         }
2054
2055         return -EINVAL;
2056 }
2057
2058 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2059 {
2060         int i, num_bpc;
2061         u8 dsc_bpc[3] = {0};
2062
2063         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2064                                                        dsc_bpc);
2065         for (i = 0; i < num_bpc; i++) {
2066                 if (dsc_max_bpc >= dsc_bpc[i])
2067                         return dsc_bpc[i] * 3;
2068         }
2069
2070         return 0;
2071 }
2072
2073 #define DSC_SUPPORTED_VERSION_MIN               1
2074
2075 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2076                                        struct intel_crtc_state *crtc_state)
2077 {
2078         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2079         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2080         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2081         u8 line_buf_depth;
2082         int ret;
2083
2084         ret = intel_dsc_compute_params(encoder, crtc_state);
2085         if (ret)
2086                 return ret;
2087
2088         /*
2089          * Slice Height of 8 works for all currently available panels. So start
2090          * with that if pic_height is an integral multiple of 8. Eventually add
2091          * logic to try multiple slice heights.
2092          */
2093         if (vdsc_cfg->pic_height % 8 == 0)
2094                 vdsc_cfg->slice_height = 8;
2095         else if (vdsc_cfg->pic_height % 4 == 0)
2096                 vdsc_cfg->slice_height = 4;
2097         else
2098                 vdsc_cfg->slice_height = 2;
2099
2100         vdsc_cfg->dsc_version_major =
2101                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2102                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2103         vdsc_cfg->dsc_version_minor =
2104                 min(DSC_SUPPORTED_VERSION_MIN,
2105                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2106                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2107
2108         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2109                 DP_DSC_RGB;
2110
2111         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2112         if (!line_buf_depth) {
2113                 drm_dbg_kms(&i915->drm,
2114                             "DSC Sink Line Buffer Depth invalid\n");
2115                 return -EINVAL;
2116         }
2117
2118         if (vdsc_cfg->dsc_version_minor == 2)
2119                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2120                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2121         else
2122                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2123                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2124
2125         vdsc_cfg->block_pred_enable =
2126                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2127                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2128
2129         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2130 }
2131
2132 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2133                                        struct intel_crtc_state *pipe_config,
2134                                        struct drm_connector_state *conn_state,
2135                                        struct link_config_limits *limits)
2136 {
2137         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2138         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2139         const struct drm_display_mode *adjusted_mode =
2140                 &pipe_config->hw.adjusted_mode;
2141         u8 dsc_max_bpc;
2142         int pipe_bpp;
2143         int ret;
2144
2145         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2146                 intel_dp_supports_fec(intel_dp, pipe_config);
2147
2148         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2149                 return -EINVAL;
2150
2151         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2152         if (INTEL_GEN(dev_priv) >= 12)
2153                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2154         else
2155                 dsc_max_bpc = min_t(u8, 10,
2156                                     conn_state->max_requested_bpc);
2157
2158         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2159
2160         /* Min Input BPC for ICL+ is 8 */
2161         if (pipe_bpp < 8 * 3) {
2162                 drm_dbg_kms(&dev_priv->drm,
2163                             "No DSC support for less than 8bpc\n");
2164                 return -EINVAL;
2165         }
2166
2167         /*
2168          * For now enable DSC for max bpp, max link rate, max lane count.
2169          * Optimize this later for the minimum possible link rate/lane count
2170          * with DSC enabled for the requested mode.
2171          */
2172         pipe_config->pipe_bpp = pipe_bpp;
2173         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2174         pipe_config->lane_count = limits->max_lane_count;
2175
2176         if (intel_dp_is_edp(intel_dp)) {
2177                 pipe_config->dsc.compressed_bpp =
2178                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2179                               pipe_config->pipe_bpp);
2180                 pipe_config->dsc.slice_count =
2181                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2182                                                         true);
2183         } else {
2184                 u16 dsc_max_output_bpp;
2185                 u8 dsc_dp_slice_count;
2186
2187                 dsc_max_output_bpp =
2188                         intel_dp_dsc_get_output_bpp(dev_priv,
2189                                                     pipe_config->port_clock,
2190                                                     pipe_config->lane_count,
2191                                                     adjusted_mode->crtc_clock,
2192                                                     adjusted_mode->crtc_hdisplay);
2193                 dsc_dp_slice_count =
2194                         intel_dp_dsc_get_slice_count(intel_dp,
2195                                                      adjusted_mode->crtc_clock,
2196                                                      adjusted_mode->crtc_hdisplay);
2197                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2198                         drm_dbg_kms(&dev_priv->drm,
2199                                     "Compressed BPP/Slice Count not supported\n");
2200                         return -EINVAL;
2201                 }
2202                 pipe_config->dsc.compressed_bpp = min_t(u16,
2203                                                                dsc_max_output_bpp >> 4,
2204                                                                pipe_config->pipe_bpp);
2205                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2206         }
2207         /*
2208          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2209          * is greater than the maximum Cdclock and if slice count is even
2210          * then we need to use 2 VDSC instances.
2211          */
2212         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2213                 if (pipe_config->dsc.slice_count > 1) {
2214                         pipe_config->dsc.dsc_split = true;
2215                 } else {
2216                         drm_dbg_kms(&dev_priv->drm,
2217                                     "Cannot split stream to use 2 VDSC instances\n");
2218                         return -EINVAL;
2219                 }
2220         }
2221
2222         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2223         if (ret < 0) {
2224                 drm_dbg_kms(&dev_priv->drm,
2225                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2226                             "Compressed BPP = %d\n",
2227                             pipe_config->pipe_bpp,
2228                             pipe_config->dsc.compressed_bpp);
2229                 return ret;
2230         }
2231
2232         pipe_config->dsc.compression_enable = true;
2233         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2234                     "Compressed Bpp = %d Slice Count = %d\n",
2235                     pipe_config->pipe_bpp,
2236                     pipe_config->dsc.compressed_bpp,
2237                     pipe_config->dsc.slice_count);
2238
2239         return 0;
2240 }
2241
2242 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2243 {
2244         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2245                 return 6 * 3;
2246         else
2247                 return 8 * 3;
2248 }
2249
2250 static int
2251 intel_dp_compute_link_config(struct intel_encoder *encoder,
2252                              struct intel_crtc_state *pipe_config,
2253                              struct drm_connector_state *conn_state)
2254 {
2255         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2256         const struct drm_display_mode *adjusted_mode =
2257                 &pipe_config->hw.adjusted_mode;
2258         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2259         struct link_config_limits limits;
2260         int common_len;
2261         int ret;
2262
2263         common_len = intel_dp_common_len_rate_limit(intel_dp,
2264                                                     intel_dp->max_link_rate);
2265
2266         /* No common link rates between source and sink */
2267         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2268
2269         limits.min_clock = 0;
2270         limits.max_clock = common_len - 1;
2271
2272         limits.min_lane_count = 1;
2273         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2274
2275         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2276         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2277
2278         if (intel_dp_is_edp(intel_dp)) {
2279                 /*
2280                  * Use the maximum clock and number of lanes the eDP panel
2281                  * advertizes being capable of. The panels are generally
2282                  * designed to support only a single clock and lane
2283                  * configuration, and typically these values correspond to the
2284                  * native resolution of the panel.
2285                  */
2286                 limits.min_lane_count = limits.max_lane_count;
2287                 limits.min_clock = limits.max_clock;
2288         }
2289
2290         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2291
2292         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2293                     "max rate %d max bpp %d pixel clock %iKHz\n",
2294                     limits.max_lane_count,
2295                     intel_dp->common_rates[limits.max_clock],
2296                     limits.max_bpp, adjusted_mode->crtc_clock);
2297
2298         /*
2299          * Optimize for slow and wide. This is the place to add alternative
2300          * optimization policy.
2301          */
2302         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2303
2304         /* enable compression if the mode doesn't fit available BW */
2305         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2306         if (ret || intel_dp->force_dsc_en) {
2307                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2308                                                   conn_state, &limits);
2309                 if (ret < 0)
2310                         return ret;
2311         }
2312
2313         if (pipe_config->dsc.compression_enable) {
2314                 drm_dbg_kms(&i915->drm,
2315                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2316                             pipe_config->lane_count, pipe_config->port_clock,
2317                             pipe_config->pipe_bpp,
2318                             pipe_config->dsc.compressed_bpp);
2319
2320                 drm_dbg_kms(&i915->drm,
2321                             "DP link rate required %i available %i\n",
2322                             intel_dp_link_required(adjusted_mode->crtc_clock,
2323                                                    pipe_config->dsc.compressed_bpp),
2324                             intel_dp_max_data_rate(pipe_config->port_clock,
2325                                                    pipe_config->lane_count));
2326         } else {
2327                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2328                             pipe_config->lane_count, pipe_config->port_clock,
2329                             pipe_config->pipe_bpp);
2330
2331                 drm_dbg_kms(&i915->drm,
2332                             "DP link rate required %i available %i\n",
2333                             intel_dp_link_required(adjusted_mode->crtc_clock,
2334                                                    pipe_config->pipe_bpp),
2335                             intel_dp_max_data_rate(pipe_config->port_clock,
2336                                                    pipe_config->lane_count));
2337         }
2338         return 0;
2339 }
2340
2341 static int
2342 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2343                          struct drm_connector *connector,
2344                          struct intel_crtc_state *crtc_state)
2345 {
2346         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2347         const struct drm_display_info *info = &connector->display_info;
2348         const struct drm_display_mode *adjusted_mode =
2349                 &crtc_state->hw.adjusted_mode;
2350         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2351         int ret;
2352
2353         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2354             !intel_dp_get_colorimetry_status(intel_dp) ||
2355             !connector->ycbcr_420_allowed)
2356                 return 0;
2357
2358         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2359
2360         /* YCBCR 420 output conversion needs a scaler */
2361         ret = skl_update_scaler_crtc(crtc_state);
2362         if (ret) {
2363                 drm_dbg_kms(&i915->drm,
2364                             "Scaler allocation for output failed\n");
2365                 return ret;
2366         }
2367
2368         intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2369
2370         return 0;
2371 }
2372
2373 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2374                                   const struct drm_connector_state *conn_state)
2375 {
2376         const struct intel_digital_connector_state *intel_conn_state =
2377                 to_intel_digital_connector_state(conn_state);
2378         const struct drm_display_mode *adjusted_mode =
2379                 &crtc_state->hw.adjusted_mode;
2380
2381         /*
2382          * Our YCbCr output is always limited range.
2383          * crtc_state->limited_color_range only applies to RGB,
2384          * and it must never be set for YCbCr or we risk setting
2385          * some conflicting bits in PIPECONF which will mess up
2386          * the colors on the monitor.
2387          */
2388         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2389                 return false;
2390
2391         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2392                 /*
2393                  * See:
2394                  * CEA-861-E - 5.1 Default Encoding Parameters
2395                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2396                  */
2397                 return crtc_state->pipe_bpp != 18 &&
2398                         drm_default_rgb_quant_range(adjusted_mode) ==
2399                         HDMI_QUANTIZATION_RANGE_LIMITED;
2400         } else {
2401                 return intel_conn_state->broadcast_rgb ==
2402                         INTEL_BROADCAST_RGB_LIMITED;
2403         }
2404 }
2405
2406 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2407                                     enum port port)
2408 {
2409         if (IS_G4X(dev_priv))
2410                 return false;
2411         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2412                 return false;
2413
2414         return true;
2415 }
2416
2417 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2418                                              const struct drm_connector_state *conn_state,
2419                                              struct drm_dp_vsc_sdp *vsc)
2420 {
2421         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2423
2424         /*
2425          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2426          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2427          * Colorimetry Format indication.
2428          */
2429         vsc->revision = 0x5;
2430         vsc->length = 0x13;
2431
2432         /* DP 1.4a spec, Table 2-120 */
2433         switch (crtc_state->output_format) {
2434         case INTEL_OUTPUT_FORMAT_YCBCR444:
2435                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2436                 break;
2437         case INTEL_OUTPUT_FORMAT_YCBCR420:
2438                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2439                 break;
2440         case INTEL_OUTPUT_FORMAT_RGB:
2441         default:
2442                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2443         }
2444
2445         switch (conn_state->colorspace) {
2446         case DRM_MODE_COLORIMETRY_BT709_YCC:
2447                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2448                 break;
2449         case DRM_MODE_COLORIMETRY_XVYCC_601:
2450                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2451                 break;
2452         case DRM_MODE_COLORIMETRY_XVYCC_709:
2453                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2454                 break;
2455         case DRM_MODE_COLORIMETRY_SYCC_601:
2456                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2457                 break;
2458         case DRM_MODE_COLORIMETRY_OPYCC_601:
2459                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2460                 break;
2461         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2462                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2463                 break;
2464         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2465                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2466                 break;
2467         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2468                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2469                 break;
2470         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2471         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2472                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2473                 break;
2474         default:
2475                 /*
2476                  * RGB->YCBCR color conversion uses the BT.709
2477                  * color space.
2478                  */
2479                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2480                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2481                 else
2482                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2483                 break;
2484         }
2485
2486         vsc->bpc = crtc_state->pipe_bpp / 3;
2487
2488         /* only RGB pixelformat supports 6 bpc */
2489         drm_WARN_ON(&dev_priv->drm,
2490                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2491
2492         /* all YCbCr are always limited range */
2493         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2494         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2495 }
2496
2497 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2498                                      struct intel_crtc_state *crtc_state,
2499                                      const struct drm_connector_state *conn_state)
2500 {
2501         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2502
2503         /* When PSR is enabled, VSC SDP is handled by PSR routine */
2504         if (intel_psr_enabled(intel_dp))
2505                 return;
2506
2507         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2508                 return;
2509
2510         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2511         vsc->sdp_type = DP_SDP_VSC;
2512         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2513                                          &crtc_state->infoframes.vsc);
2514 }
2515
2516 static void
2517 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2518                                             struct intel_crtc_state *crtc_state,
2519                                             const struct drm_connector_state *conn_state)
2520 {
2521         int ret;
2522         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2523         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2524
2525         if (!conn_state->hdr_output_metadata)
2526                 return;
2527
2528         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2529
2530         if (ret) {
2531                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2532                 return;
2533         }
2534
2535         crtc_state->infoframes.enable |=
2536                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2537 }
2538
2539 int
2540 intel_dp_compute_config(struct intel_encoder *encoder,
2541                         struct intel_crtc_state *pipe_config,
2542                         struct drm_connector_state *conn_state)
2543 {
2544         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2545         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2546         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2547         struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2548         enum port port = encoder->port;
2549         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
2550         struct intel_connector *intel_connector = intel_dp->attached_connector;
2551         struct intel_digital_connector_state *intel_conn_state =
2552                 to_intel_digital_connector_state(conn_state);
2553         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2554                                            DP_DPCD_QUIRK_CONSTANT_N);
2555         int ret = 0, output_bpp;
2556
2557         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2558                 pipe_config->has_pch_encoder = true;
2559
2560         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2561
2562         if (lspcon->active)
2563                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2564         else
2565                 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2566                                                pipe_config);
2567
2568         if (ret)
2569                 return ret;
2570
2571         pipe_config->has_drrs = false;
2572         if (!intel_dp_port_has_audio(dev_priv, port))
2573                 pipe_config->has_audio = false;
2574         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2575                 pipe_config->has_audio = intel_dp->has_audio;
2576         else
2577                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2578
2579         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2580                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2581                                        adjusted_mode);
2582
2583                 if (INTEL_GEN(dev_priv) >= 9) {
2584                         ret = skl_update_scaler_crtc(pipe_config);
2585                         if (ret)
2586                                 return ret;
2587                 }
2588
2589                 if (HAS_GMCH(dev_priv))
2590                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2591                                                  conn_state->scaling_mode);
2592                 else
2593                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2594                                                 conn_state->scaling_mode);
2595         }
2596
2597         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2598                 return -EINVAL;
2599
2600         if (HAS_GMCH(dev_priv) &&
2601             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2602                 return -EINVAL;
2603
2604         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2605                 return -EINVAL;
2606
2607         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2608                 return -EINVAL;
2609
2610         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2611         if (ret < 0)
2612                 return ret;
2613
2614         pipe_config->limited_color_range =
2615                 intel_dp_limited_color_range(pipe_config, conn_state);
2616
2617         if (pipe_config->dsc.compression_enable)
2618                 output_bpp = pipe_config->dsc.compressed_bpp;
2619         else
2620                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2621
2622         intel_link_compute_m_n(output_bpp,
2623                                pipe_config->lane_count,
2624                                adjusted_mode->crtc_clock,
2625                                pipe_config->port_clock,
2626                                &pipe_config->dp_m_n,
2627                                constant_n, pipe_config->fec_enable);
2628
2629         if (intel_connector->panel.downclock_mode != NULL &&
2630                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2631                         pipe_config->has_drrs = true;
2632                         intel_link_compute_m_n(output_bpp,
2633                                                pipe_config->lane_count,
2634                                                intel_connector->panel.downclock_mode->clock,
2635                                                pipe_config->port_clock,
2636                                                &pipe_config->dp_m2_n2,
2637                                                constant_n, pipe_config->fec_enable);
2638         }
2639
2640         if (!HAS_DDI(dev_priv))
2641                 intel_dp_set_clock(encoder, pipe_config);
2642
2643         intel_psr_compute_config(intel_dp, pipe_config);
2644         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2645         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2646
2647         return 0;
2648 }
2649
2650 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2651                               int link_rate, u8 lane_count,
2652                               bool link_mst)
2653 {
2654         intel_dp->link_trained = false;
2655         intel_dp->link_rate = link_rate;
2656         intel_dp->lane_count = lane_count;
2657         intel_dp->link_mst = link_mst;
2658 }
2659
2660 static void intel_dp_prepare(struct intel_encoder *encoder,
2661                              const struct intel_crtc_state *pipe_config)
2662 {
2663         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2664         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2665         enum port port = encoder->port;
2666         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2667         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2668
2669         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2670                                  pipe_config->lane_count,
2671                                  intel_crtc_has_type(pipe_config,
2672                                                      INTEL_OUTPUT_DP_MST));
2673
2674         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2675         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2676
2677         /*
2678          * There are four kinds of DP registers:
2679          *
2680          *      IBX PCH
2681          *      SNB CPU
2682          *      IVB CPU
2683          *      CPT PCH
2684          *
2685          * IBX PCH and CPU are the same for almost everything,
2686          * except that the CPU DP PLL is configured in this
2687          * register
2688          *
2689          * CPT PCH is quite different, having many bits moved
2690          * to the TRANS_DP_CTL register instead. That
2691          * configuration happens (oddly) in ilk_pch_enable
2692          */
2693
2694         /* Preserve the BIOS-computed detected bit. This is
2695          * supposed to be read-only.
2696          */
2697         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2698
2699         /* Handle DP bits in common between all three register formats */
2700         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2701         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2702
2703         /* Split out the IBX/CPU vs CPT settings */
2704
2705         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2706                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2707                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2708                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2709                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2710                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2711
2712                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2713                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2714
2715                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2716         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2717                 u32 trans_dp;
2718
2719                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2720
2721                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2722                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2723                         trans_dp |= TRANS_DP_ENH_FRAMING;
2724                 else
2725                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2726                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2727         } else {
2728                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2729                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2730
2731                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2732                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2733                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2734                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2735                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2736
2737                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2738                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2739
2740                 if (IS_CHERRYVIEW(dev_priv))
2741                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2742                 else
2743                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2744         }
2745 }
2746
2747 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2748 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2749
2750 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2751 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2752
2753 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2754 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2755
2756 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2757
2758 static void wait_panel_status(struct intel_dp *intel_dp,
2759                                        u32 mask,
2760                                        u32 value)
2761 {
2762         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2763         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2764
2765         lockdep_assert_held(&dev_priv->pps_mutex);
2766
2767         intel_pps_verify_state(intel_dp);
2768
2769         pp_stat_reg = _pp_stat_reg(intel_dp);
2770         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2771
2772         drm_dbg_kms(&dev_priv->drm,
2773                     "mask %08x value %08x status %08x control %08x\n",
2774                     mask, value,
2775                     intel_de_read(dev_priv, pp_stat_reg),
2776                     intel_de_read(dev_priv, pp_ctrl_reg));
2777
2778         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2779                                        mask, value, 5000))
2780                 drm_err(&dev_priv->drm,
2781                         "Panel status timeout: status %08x control %08x\n",
2782                         intel_de_read(dev_priv, pp_stat_reg),
2783                         intel_de_read(dev_priv, pp_ctrl_reg));
2784
2785         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
2786 }
2787
2788 static void wait_panel_on(struct intel_dp *intel_dp)
2789 {
2790         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2791
2792         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
2793         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2794 }
2795
2796 static void wait_panel_off(struct intel_dp *intel_dp)
2797 {
2798         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2799
2800         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
2801         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2802 }
2803
2804 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2805 {
2806         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2807         ktime_t panel_power_on_time;
2808         s64 panel_power_off_duration;
2809
2810         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
2811
2812         /* take the difference of currrent time and panel power off time
2813          * and then make panel wait for t11_t12 if needed. */
2814         panel_power_on_time = ktime_get_boottime();
2815         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2816
2817         /* When we disable the VDD override bit last we have to do the manual
2818          * wait. */
2819         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2820                 wait_remaining_ms_from_jiffies(jiffies,
2821                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2822
2823         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2824 }
2825
2826 static void wait_backlight_on(struct intel_dp *intel_dp)
2827 {
2828         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2829                                        intel_dp->backlight_on_delay);
2830 }
2831
2832 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2833 {
2834         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2835                                        intel_dp->backlight_off_delay);
2836 }
2837
2838 /* Read the current pp_control value, unlocking the register if it
2839  * is locked
2840  */
2841
2842 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2843 {
2844         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2845         u32 control;
2846
2847         lockdep_assert_held(&dev_priv->pps_mutex);
2848
2849         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
2850         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
2851                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2852                 control &= ~PANEL_UNLOCK_MASK;
2853                 control |= PANEL_UNLOCK_REGS;
2854         }
2855         return control;
2856 }
2857
2858 /*
2859  * Must be paired with edp_panel_vdd_off().
2860  * Must hold pps_mutex around the whole on/off sequence.
2861  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2862  */
2863 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2864 {
2865         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2866         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2867         u32 pp;
2868         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2869         bool need_to_disable = !intel_dp->want_panel_vdd;
2870
2871         lockdep_assert_held(&dev_priv->pps_mutex);
2872
2873         if (!intel_dp_is_edp(intel_dp))
2874                 return false;
2875
2876         cancel_delayed_work(&intel_dp->panel_vdd_work);
2877         intel_dp->want_panel_vdd = true;
2878
2879         if (edp_have_panel_vdd(intel_dp))
2880                 return need_to_disable;
2881
2882         intel_display_power_get(dev_priv,
2883                                 intel_aux_power_domain(intel_dig_port));
2884
2885         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
2886                     intel_dig_port->base.base.base.id,
2887                     intel_dig_port->base.base.name);
2888
2889         if (!edp_have_panel_power(intel_dp))
2890                 wait_panel_power_cycle(intel_dp);
2891
2892         pp = ilk_get_pp_control(intel_dp);
2893         pp |= EDP_FORCE_VDD;
2894
2895         pp_stat_reg = _pp_stat_reg(intel_dp);
2896         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2897
2898         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2899         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2900         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2901                     intel_de_read(dev_priv, pp_stat_reg),
2902                     intel_de_read(dev_priv, pp_ctrl_reg));
2903         /*
2904          * If the panel wasn't on, delay before accessing aux channel
2905          */
2906         if (!edp_have_panel_power(intel_dp)) {
2907                 drm_dbg_kms(&dev_priv->drm,
2908                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
2909                             intel_dig_port->base.base.base.id,
2910                             intel_dig_port->base.base.name);
2911                 msleep(intel_dp->panel_power_up_delay);
2912         }
2913
2914         return need_to_disable;
2915 }
2916
2917 /*
2918  * Must be paired with intel_edp_panel_vdd_off() or
2919  * intel_edp_panel_off().
2920  * Nested calls to these functions are not allowed since
2921  * we drop the lock. Caller must use some higher level
2922  * locking to prevent nested calls from other threads.
2923  */
2924 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2925 {
2926         intel_wakeref_t wakeref;
2927         bool vdd;
2928
2929         if (!intel_dp_is_edp(intel_dp))
2930                 return;
2931
2932         vdd = false;
2933         with_pps_lock(intel_dp, wakeref)
2934                 vdd = edp_panel_vdd_on(intel_dp);
2935         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2936                         dp_to_dig_port(intel_dp)->base.base.base.id,
2937                         dp_to_dig_port(intel_dp)->base.base.name);
2938 }
2939
2940 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2941 {
2942         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2943         struct intel_digital_port *intel_dig_port =
2944                 dp_to_dig_port(intel_dp);
2945         u32 pp;
2946         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2947
2948         lockdep_assert_held(&dev_priv->pps_mutex);
2949
2950         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
2951
2952         if (!edp_have_panel_vdd(intel_dp))
2953                 return;
2954
2955         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
2956                     intel_dig_port->base.base.base.id,
2957                     intel_dig_port->base.base.name);
2958
2959         pp = ilk_get_pp_control(intel_dp);
2960         pp &= ~EDP_FORCE_VDD;
2961
2962         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2963         pp_stat_reg = _pp_stat_reg(intel_dp);
2964
2965         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2966         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2967
2968         /* Make sure sequencer is idle before allowing subsequent activity */
2969         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2970                     intel_de_read(dev_priv, pp_stat_reg),
2971                     intel_de_read(dev_priv, pp_ctrl_reg));
2972
2973         if ((pp & PANEL_POWER_ON) == 0)
2974                 intel_dp->panel_power_off_time = ktime_get_boottime();
2975
2976         intel_display_power_put_unchecked(dev_priv,
2977                                           intel_aux_power_domain(intel_dig_port));
2978 }
2979
2980 static void edp_panel_vdd_work(struct work_struct *__work)
2981 {
2982         struct intel_dp *intel_dp =
2983                 container_of(to_delayed_work(__work),
2984                              struct intel_dp, panel_vdd_work);
2985         intel_wakeref_t wakeref;
2986
2987         with_pps_lock(intel_dp, wakeref) {
2988                 if (!intel_dp->want_panel_vdd)
2989                         edp_panel_vdd_off_sync(intel_dp);
2990         }
2991 }
2992
2993 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2994 {
2995         unsigned long delay;
2996
2997         /*
2998          * Queue the timer to fire a long time from now (relative to the power
2999          * down delay) to keep the panel power up across a sequence of
3000          * operations.
3001          */
3002         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3003         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3004 }
3005
3006 /*
3007  * Must be paired with edp_panel_vdd_on().
3008  * Must hold pps_mutex around the whole on/off sequence.
3009  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3010  */
3011 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3012 {
3013         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3014
3015         lockdep_assert_held(&dev_priv->pps_mutex);
3016
3017         if (!intel_dp_is_edp(intel_dp))
3018                 return;
3019
3020         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3021                         dp_to_dig_port(intel_dp)->base.base.base.id,
3022                         dp_to_dig_port(intel_dp)->base.base.name);
3023
3024         intel_dp->want_panel_vdd = false;
3025
3026         if (sync)
3027                 edp_panel_vdd_off_sync(intel_dp);
3028         else
3029                 edp_panel_vdd_schedule_off(intel_dp);
3030 }
3031
3032 static void edp_panel_on(struct intel_dp *intel_dp)
3033 {
3034         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3035         u32 pp;
3036         i915_reg_t pp_ctrl_reg;
3037
3038         lockdep_assert_held(&dev_priv->pps_mutex);
3039
3040         if (!intel_dp_is_edp(intel_dp))
3041                 return;
3042
3043         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3044                     dp_to_dig_port(intel_dp)->base.base.base.id,
3045                     dp_to_dig_port(intel_dp)->base.base.name);
3046
3047         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3048                      "[ENCODER:%d:%s] panel power already on\n",
3049                      dp_to_dig_port(intel_dp)->base.base.base.id,
3050                      dp_to_dig_port(intel_dp)->base.base.name))
3051                 return;
3052
3053         wait_panel_power_cycle(intel_dp);
3054
3055         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3056         pp = ilk_get_pp_control(intel_dp);
3057         if (IS_GEN(dev_priv, 5)) {
3058                 /* ILK workaround: disable reset around power sequence */
3059                 pp &= ~PANEL_POWER_RESET;
3060                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3061                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3062         }
3063
3064         pp |= PANEL_POWER_ON;
3065         if (!IS_GEN(dev_priv, 5))
3066                 pp |= PANEL_POWER_RESET;
3067
3068         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3069         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3070
3071         wait_panel_on(intel_dp);
3072         intel_dp->last_power_on = jiffies;
3073
3074         if (IS_GEN(dev_priv, 5)) {
3075                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3076                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3077                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3078         }
3079 }
3080
3081 void intel_edp_panel_on(struct intel_dp *intel_dp)
3082 {
3083         intel_wakeref_t wakeref;
3084
3085         if (!intel_dp_is_edp(intel_dp))
3086                 return;
3087
3088         with_pps_lock(intel_dp, wakeref)
3089                 edp_panel_on(intel_dp);
3090 }
3091
3092
3093 static void edp_panel_off(struct intel_dp *intel_dp)
3094 {
3095         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3096         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3097         u32 pp;
3098         i915_reg_t pp_ctrl_reg;
3099
3100         lockdep_assert_held(&dev_priv->pps_mutex);
3101
3102         if (!intel_dp_is_edp(intel_dp))
3103                 return;
3104
3105         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3106                     dig_port->base.base.base.id, dig_port->base.base.name);
3107
3108         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3109                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3110                  dig_port->base.base.base.id, dig_port->base.base.name);
3111
3112         pp = ilk_get_pp_control(intel_dp);
3113         /* We need to switch off panel power _and_ force vdd, for otherwise some
3114          * panels get very unhappy and cease to work. */
3115         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3116                 EDP_BLC_ENABLE);
3117
3118         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3119
3120         intel_dp->want_panel_vdd = false;
3121
3122         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3123         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3124
3125         wait_panel_off(intel_dp);
3126         intel_dp->panel_power_off_time = ktime_get_boottime();
3127
3128         /* We got a reference when we enabled the VDD. */
3129         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3130 }
3131
3132 void intel_edp_panel_off(struct intel_dp *intel_dp)
3133 {
3134         intel_wakeref_t wakeref;
3135
3136         if (!intel_dp_is_edp(intel_dp))
3137                 return;
3138
3139         with_pps_lock(intel_dp, wakeref)
3140                 edp_panel_off(intel_dp);
3141 }
3142
3143 /* Enable backlight in the panel power control. */
3144 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3145 {
3146         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3147         intel_wakeref_t wakeref;
3148
3149         /*
3150          * If we enable the backlight right away following a panel power
3151          * on, we may see slight flicker as the panel syncs with the eDP
3152          * link.  So delay a bit to make sure the image is solid before
3153          * allowing it to appear.
3154          */
3155         wait_backlight_on(intel_dp);
3156
3157         with_pps_lock(intel_dp, wakeref) {
3158                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3159                 u32 pp;
3160
3161                 pp = ilk_get_pp_control(intel_dp);
3162                 pp |= EDP_BLC_ENABLE;
3163
3164                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3165                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3166         }
3167 }
3168
3169 /* Enable backlight PWM and backlight PP control. */
3170 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3171                             const struct drm_connector_state *conn_state)
3172 {
3173         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3174         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3175
3176         if (!intel_dp_is_edp(intel_dp))
3177                 return;
3178
3179         drm_dbg_kms(&i915->drm, "\n");
3180
3181         intel_panel_enable_backlight(crtc_state, conn_state);
3182         _intel_edp_backlight_on(intel_dp);
3183 }
3184
3185 /* Disable backlight in the panel power control. */
3186 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3187 {
3188         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3189         intel_wakeref_t wakeref;
3190
3191         if (!intel_dp_is_edp(intel_dp))
3192                 return;
3193
3194         with_pps_lock(intel_dp, wakeref) {
3195                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3196                 u32 pp;
3197
3198                 pp = ilk_get_pp_control(intel_dp);
3199                 pp &= ~EDP_BLC_ENABLE;
3200
3201                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3202                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3203         }
3204
3205         intel_dp->last_backlight_off = jiffies;
3206         edp_wait_backlight_off(intel_dp);
3207 }
3208
3209 /* Disable backlight PP control and backlight PWM. */
3210 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3211 {
3212         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3213         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3214
3215         if (!intel_dp_is_edp(intel_dp))
3216                 return;
3217
3218         drm_dbg_kms(&i915->drm, "\n");
3219
3220         _intel_edp_backlight_off(intel_dp);
3221         intel_panel_disable_backlight(old_conn_state);
3222 }
3223
3224 /*
3225  * Hook for controlling the panel power control backlight through the bl_power
3226  * sysfs attribute. Take care to handle multiple calls.
3227  */
3228 static void intel_edp_backlight_power(struct intel_connector *connector,
3229                                       bool enable)
3230 {
3231         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3232         struct intel_dp *intel_dp = intel_attached_dp(connector);
3233         intel_wakeref_t wakeref;
3234         bool is_enabled;
3235
3236         is_enabled = false;
3237         with_pps_lock(intel_dp, wakeref)
3238                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3239         if (is_enabled == enable)
3240                 return;
3241
3242         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3243                     enable ? "enable" : "disable");
3244
3245         if (enable)
3246                 _intel_edp_backlight_on(intel_dp);
3247         else
3248                 _intel_edp_backlight_off(intel_dp);
3249 }
3250
3251 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3252 {
3253         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3254         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3255         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3256
3257         I915_STATE_WARN(cur_state != state,
3258                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3259                         dig_port->base.base.base.id, dig_port->base.base.name,
3260                         onoff(state), onoff(cur_state));
3261 }
3262 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3263
3264 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3265 {
3266         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3267
3268         I915_STATE_WARN(cur_state != state,
3269                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3270                         onoff(state), onoff(cur_state));
3271 }
3272 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3273 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3274
3275 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3276                            const struct intel_crtc_state *pipe_config)
3277 {
3278         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3279         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3280
3281         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3282         assert_dp_port_disabled(intel_dp);
3283         assert_edp_pll_disabled(dev_priv);
3284
3285         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3286                     pipe_config->port_clock);
3287
3288         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3289
3290         if (pipe_config->port_clock == 162000)
3291                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3292         else
3293                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3294
3295         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3296         intel_de_posting_read(dev_priv, DP_A);
3297         udelay(500);
3298
3299         /*
3300          * [DevILK] Work around required when enabling DP PLL
3301          * while a pipe is enabled going to FDI:
3302          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3303          * 2. Program DP PLL enable
3304          */
3305         if (IS_GEN(dev_priv, 5))
3306                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3307
3308         intel_dp->DP |= DP_PLL_ENABLE;
3309
3310         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3311         intel_de_posting_read(dev_priv, DP_A);
3312         udelay(200);
3313 }
3314
3315 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3316                             const struct intel_crtc_state *old_crtc_state)
3317 {
3318         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3319         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3320
3321         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3322         assert_dp_port_disabled(intel_dp);
3323         assert_edp_pll_enabled(dev_priv);
3324
3325         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3326
3327         intel_dp->DP &= ~DP_PLL_ENABLE;
3328
3329         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3330         intel_de_posting_read(dev_priv, DP_A);
3331         udelay(200);
3332 }
3333
3334 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3335 {
3336         /*
3337          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3338          * be capable of signalling downstream hpd with a long pulse.
3339          * Whether or not that means D3 is safe to use is not clear,
3340          * but let's assume so until proven otherwise.
3341          *
3342          * FIXME should really check all downstream ports...
3343          */
3344         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3345                 drm_dp_is_branch(intel_dp->dpcd) &&
3346                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3347 }
3348
3349 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3350                                            const struct intel_crtc_state *crtc_state,
3351                                            bool enable)
3352 {
3353         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3354         int ret;
3355
3356         if (!crtc_state->dsc.compression_enable)
3357                 return;
3358
3359         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3360                                  enable ? DP_DECOMPRESSION_EN : 0);
3361         if (ret < 0)
3362                 drm_dbg_kms(&i915->drm,
3363                             "Failed to %s sink decompression state\n",
3364                             enable ? "enable" : "disable");
3365 }
3366
3367 /* If the sink supports it, try to set the power state appropriately */
3368 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3369 {
3370         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3371         int ret, i;
3372
3373         /* Should have a valid DPCD by this point */
3374         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3375                 return;
3376
3377         if (mode != DRM_MODE_DPMS_ON) {
3378                 if (downstream_hpd_needs_d0(intel_dp))
3379                         return;
3380
3381                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3382                                          DP_SET_POWER_D3);
3383         } else {
3384                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3385
3386                 /*
3387                  * When turning on, we need to retry for 1ms to give the sink
3388                  * time to wake up.
3389                  */
3390                 for (i = 0; i < 3; i++) {
3391                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3392                                                  DP_SET_POWER_D0);
3393                         if (ret == 1)
3394                                 break;
3395                         msleep(1);
3396                 }
3397
3398                 if (ret == 1 && lspcon->active)
3399                         lspcon_wait_pcon_mode(lspcon);
3400         }
3401
3402         if (ret != 1)
3403                 drm_dbg_kms(&i915->drm, "failed to %s sink power state\n",
3404                             mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3405 }
3406
3407 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3408                                  enum port port, enum pipe *pipe)
3409 {
3410         enum pipe p;
3411
3412         for_each_pipe(dev_priv, p) {
3413                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3414
3415                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3416                         *pipe = p;
3417                         return true;
3418                 }
3419         }
3420
3421         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3422                     port_name(port));
3423
3424         /* must initialize pipe to something for the asserts */
3425         *pipe = PIPE_A;
3426
3427         return false;
3428 }
3429
3430 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3431                            i915_reg_t dp_reg, enum port port,
3432                            enum pipe *pipe)
3433 {
3434         bool ret;
3435         u32 val;
3436
3437         val = intel_de_read(dev_priv, dp_reg);
3438
3439         ret = val & DP_PORT_EN;
3440
3441         /* asserts want to know the pipe even if the port is disabled */
3442         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3443                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3444         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3445                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3446         else if (IS_CHERRYVIEW(dev_priv))
3447                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3448         else
3449                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3450
3451         return ret;
3452 }
3453
3454 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3455                                   enum pipe *pipe)
3456 {
3457         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3458         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3459         intel_wakeref_t wakeref;
3460         bool ret;
3461
3462         wakeref = intel_display_power_get_if_enabled(dev_priv,
3463                                                      encoder->power_domain);
3464         if (!wakeref)
3465                 return false;
3466
3467         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3468                                     encoder->port, pipe);
3469
3470         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3471
3472         return ret;
3473 }
3474
3475 static void intel_dp_get_config(struct intel_encoder *encoder,
3476                                 struct intel_crtc_state *pipe_config)
3477 {
3478         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3479         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3480         u32 tmp, flags = 0;
3481         enum port port = encoder->port;
3482         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3483
3484         if (encoder->type == INTEL_OUTPUT_EDP)
3485                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3486         else
3487                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3488
3489         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3490
3491         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3492
3493         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3494                 u32 trans_dp = intel_de_read(dev_priv,
3495                                              TRANS_DP_CTL(crtc->pipe));
3496
3497                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3498                         flags |= DRM_MODE_FLAG_PHSYNC;
3499                 else
3500                         flags |= DRM_MODE_FLAG_NHSYNC;
3501
3502                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3503                         flags |= DRM_MODE_FLAG_PVSYNC;
3504                 else
3505                         flags |= DRM_MODE_FLAG_NVSYNC;
3506         } else {
3507                 if (tmp & DP_SYNC_HS_HIGH)
3508                         flags |= DRM_MODE_FLAG_PHSYNC;
3509                 else
3510                         flags |= DRM_MODE_FLAG_NHSYNC;
3511
3512                 if (tmp & DP_SYNC_VS_HIGH)
3513                         flags |= DRM_MODE_FLAG_PVSYNC;
3514                 else
3515                         flags |= DRM_MODE_FLAG_NVSYNC;
3516         }
3517
3518         pipe_config->hw.adjusted_mode.flags |= flags;
3519
3520         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3521                 pipe_config->limited_color_range = true;
3522
3523         pipe_config->lane_count =
3524                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3525
3526         intel_dp_get_m_n(crtc, pipe_config);
3527
3528         if (port == PORT_A) {
3529                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3530                         pipe_config->port_clock = 162000;
3531                 else
3532                         pipe_config->port_clock = 270000;
3533         }
3534
3535         pipe_config->hw.adjusted_mode.crtc_clock =
3536                 intel_dotclock_calculate(pipe_config->port_clock,
3537                                          &pipe_config->dp_m_n);
3538
3539         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3540             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3541                 /*
3542                  * This is a big fat ugly hack.
3543                  *
3544                  * Some machines in UEFI boot mode provide us a VBT that has 18
3545                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3546                  * unknown we fail to light up. Yet the same BIOS boots up with
3547                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3548                  * max, not what it tells us to use.
3549                  *
3550                  * Note: This will still be broken if the eDP panel is not lit
3551                  * up by the BIOS, and thus we can't get the mode at module
3552                  * load.
3553                  */
3554                 drm_dbg_kms(&dev_priv->drm,
3555                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3556                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3557                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3558         }
3559 }
3560
3561 static void intel_disable_dp(struct intel_atomic_state *state,
3562                              struct intel_encoder *encoder,
3563                              const struct intel_crtc_state *old_crtc_state,
3564                              const struct drm_connector_state *old_conn_state)
3565 {
3566         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3567
3568         intel_dp->link_trained = false;
3569
3570         if (old_crtc_state->has_audio)
3571                 intel_audio_codec_disable(encoder,
3572                                           old_crtc_state, old_conn_state);
3573
3574         /* Make sure the panel is off before trying to change the mode. But also
3575          * ensure that we have vdd while we switch off the panel. */
3576         intel_edp_panel_vdd_on(intel_dp);
3577         intel_edp_backlight_off(old_conn_state);
3578         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3579         intel_edp_panel_off(intel_dp);
3580 }
3581
3582 static void g4x_disable_dp(struct intel_atomic_state *state,
3583                            struct intel_encoder *encoder,
3584                            const struct intel_crtc_state *old_crtc_state,
3585                            const struct drm_connector_state *old_conn_state)
3586 {
3587         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3588 }
3589
3590 static void vlv_disable_dp(struct intel_atomic_state *state,
3591                            struct intel_encoder *encoder,
3592                            const struct intel_crtc_state *old_crtc_state,
3593                            const struct drm_connector_state *old_conn_state)
3594 {
3595         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3596 }
3597
3598 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3599                                 struct intel_encoder *encoder,
3600                                 const struct intel_crtc_state *old_crtc_state,
3601                                 const struct drm_connector_state *old_conn_state)
3602 {
3603         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3604         enum port port = encoder->port;
3605
3606         /*
3607          * Bspec does not list a specific disable sequence for g4x DP.
3608          * Follow the ilk+ sequence (disable pipe before the port) for
3609          * g4x DP as it does not suffer from underruns like the normal
3610          * g4x modeset sequence (disable pipe after the port).
3611          */
3612         intel_dp_link_down(encoder, old_crtc_state);
3613
3614         /* Only ilk+ has port A */
3615         if (port == PORT_A)
3616                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3617 }
3618
3619 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3620                                 struct intel_encoder *encoder,
3621                                 const struct intel_crtc_state *old_crtc_state,
3622                                 const struct drm_connector_state *old_conn_state)
3623 {
3624         intel_dp_link_down(encoder, old_crtc_state);
3625 }
3626
3627 static void chv_post_disable_dp(struct intel_atomic_state *state,
3628                                 struct intel_encoder *encoder,
3629                                 const struct intel_crtc_state *old_crtc_state,
3630                                 const struct drm_connector_state *old_conn_state)
3631 {
3632         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3633
3634         intel_dp_link_down(encoder, old_crtc_state);
3635
3636         vlv_dpio_get(dev_priv);
3637
3638         /* Assert data lane reset */
3639         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3640
3641         vlv_dpio_put(dev_priv);
3642 }
3643
3644 static void
3645 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3646                          u32 *DP,
3647                          u8 dp_train_pat)
3648 {
3649         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3650         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3651         enum port port = intel_dig_port->base.port;
3652         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3653
3654         if (dp_train_pat & train_pat_mask)
3655                 drm_dbg_kms(&dev_priv->drm,
3656                             "Using DP training pattern TPS%d\n",
3657                             dp_train_pat & train_pat_mask);
3658
3659         if (HAS_DDI(dev_priv)) {
3660                 u32 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3661
3662                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3663                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3664                 else
3665                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3666
3667                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3668                 switch (dp_train_pat & train_pat_mask) {
3669                 case DP_TRAINING_PATTERN_DISABLE:
3670                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3671
3672                         break;
3673                 case DP_TRAINING_PATTERN_1:
3674                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3675                         break;
3676                 case DP_TRAINING_PATTERN_2:
3677                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3678                         break;
3679                 case DP_TRAINING_PATTERN_3:
3680                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3681                         break;
3682                 case DP_TRAINING_PATTERN_4:
3683                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3684                         break;
3685                 }
3686                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
3687
3688         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3689                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3690                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3691
3692                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3693                 case DP_TRAINING_PATTERN_DISABLE:
3694                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3695                         break;
3696                 case DP_TRAINING_PATTERN_1:
3697                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3698                         break;
3699                 case DP_TRAINING_PATTERN_2:
3700                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3701                         break;
3702                 case DP_TRAINING_PATTERN_3:
3703                         drm_dbg_kms(&dev_priv->drm,
3704                                     "TPS3 not supported, using TPS2 instead\n");
3705                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3706                         break;
3707                 }
3708
3709         } else {
3710                 *DP &= ~DP_LINK_TRAIN_MASK;
3711
3712                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3713                 case DP_TRAINING_PATTERN_DISABLE:
3714                         *DP |= DP_LINK_TRAIN_OFF;
3715                         break;
3716                 case DP_TRAINING_PATTERN_1:
3717                         *DP |= DP_LINK_TRAIN_PAT_1;
3718                         break;
3719                 case DP_TRAINING_PATTERN_2:
3720                         *DP |= DP_LINK_TRAIN_PAT_2;
3721                         break;
3722                 case DP_TRAINING_PATTERN_3:
3723                         drm_dbg_kms(&dev_priv->drm,
3724                                     "TPS3 not supported, using TPS2 instead\n");
3725                         *DP |= DP_LINK_TRAIN_PAT_2;
3726                         break;
3727                 }
3728         }
3729 }
3730
3731 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3732                                  const struct intel_crtc_state *old_crtc_state)
3733 {
3734         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3735
3736         /* enable with pattern 1 (as per spec) */
3737
3738         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3739
3740         /*
3741          * Magic for VLV/CHV. We _must_ first set up the register
3742          * without actually enabling the port, and then do another
3743          * write to enable the port. Otherwise link training will
3744          * fail when the power sequencer is freshly used for this port.
3745          */
3746         intel_dp->DP |= DP_PORT_EN;
3747         if (old_crtc_state->has_audio)
3748                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3749
3750         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3751         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3752 }
3753
3754 static void intel_enable_dp(struct intel_atomic_state *state,
3755                             struct intel_encoder *encoder,
3756                             const struct intel_crtc_state *pipe_config,
3757                             const struct drm_connector_state *conn_state)
3758 {
3759         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3760         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3761         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3762         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
3763         enum pipe pipe = crtc->pipe;
3764         intel_wakeref_t wakeref;
3765
3766         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
3767                 return;
3768
3769         with_pps_lock(intel_dp, wakeref) {
3770                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3771                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3772
3773                 intel_dp_enable_port(intel_dp, pipe_config);
3774
3775                 edp_panel_vdd_on(intel_dp);
3776                 edp_panel_on(intel_dp);
3777                 edp_panel_vdd_off(intel_dp, true);
3778         }
3779
3780         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3781                 unsigned int lane_mask = 0x0;
3782
3783                 if (IS_CHERRYVIEW(dev_priv))
3784                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3785
3786                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3787                                     lane_mask);
3788         }
3789
3790         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3791         intel_dp_start_link_train(intel_dp);
3792         intel_dp_stop_link_train(intel_dp);
3793
3794         if (pipe_config->has_audio) {
3795                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
3796                         pipe_name(pipe));
3797                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3798         }
3799 }
3800
3801 static void g4x_enable_dp(struct intel_atomic_state *state,
3802                           struct intel_encoder *encoder,
3803                           const struct intel_crtc_state *pipe_config,
3804                           const struct drm_connector_state *conn_state)
3805 {
3806         intel_enable_dp(state, encoder, pipe_config, conn_state);
3807         intel_edp_backlight_on(pipe_config, conn_state);
3808 }
3809
3810 static void vlv_enable_dp(struct intel_atomic_state *state,
3811                           struct intel_encoder *encoder,
3812                           const struct intel_crtc_state *pipe_config,
3813                           const struct drm_connector_state *conn_state)
3814 {
3815         intel_edp_backlight_on(pipe_config, conn_state);
3816 }
3817
3818 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
3819                               struct intel_encoder *encoder,
3820                               const struct intel_crtc_state *pipe_config,
3821                               const struct drm_connector_state *conn_state)
3822 {
3823         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3824         enum port port = encoder->port;
3825
3826         intel_dp_prepare(encoder, pipe_config);
3827
3828         /* Only ilk+ has port A */
3829         if (port == PORT_A)
3830                 ilk_edp_pll_on(intel_dp, pipe_config);
3831 }
3832
3833 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3834 {
3835         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3836         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3837         enum pipe pipe = intel_dp->pps_pipe;
3838         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3839
3840         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3841
3842         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
3843                 return;
3844
3845         edp_panel_vdd_off_sync(intel_dp);
3846
3847         /*
3848          * VLV seems to get confused when multiple power sequencers
3849          * have the same port selected (even if only one has power/vdd
3850          * enabled). The failure manifests as vlv_wait_port_ready() failing
3851          * CHV on the other hand doesn't seem to mind having the same port
3852          * selected in multiple power sequencers, but let's clear the
3853          * port select always when logically disconnecting a power sequencer
3854          * from a port.
3855          */
3856         drm_dbg_kms(&dev_priv->drm,
3857                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3858                     pipe_name(pipe), intel_dig_port->base.base.base.id,
3859                     intel_dig_port->base.base.name);
3860         intel_de_write(dev_priv, pp_on_reg, 0);
3861         intel_de_posting_read(dev_priv, pp_on_reg);
3862
3863         intel_dp->pps_pipe = INVALID_PIPE;
3864 }
3865
3866 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3867                                       enum pipe pipe)
3868 {
3869         struct intel_encoder *encoder;
3870
3871         lockdep_assert_held(&dev_priv->pps_mutex);
3872
3873         for_each_intel_dp(&dev_priv->drm, encoder) {
3874                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3875
3876                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
3877                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3878                          pipe_name(pipe), encoder->base.base.id,
3879                          encoder->base.name);
3880
3881                 if (intel_dp->pps_pipe != pipe)
3882                         continue;
3883
3884                 drm_dbg_kms(&dev_priv->drm,
3885                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3886                             pipe_name(pipe), encoder->base.base.id,
3887                             encoder->base.name);
3888
3889                 /* make sure vdd is off before we steal it */
3890                 vlv_detach_power_sequencer(intel_dp);
3891         }
3892 }
3893
3894 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3895                                            const struct intel_crtc_state *crtc_state)
3896 {
3897         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3898         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3899         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3900
3901         lockdep_assert_held(&dev_priv->pps_mutex);
3902
3903         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
3904
3905         if (intel_dp->pps_pipe != INVALID_PIPE &&
3906             intel_dp->pps_pipe != crtc->pipe) {
3907                 /*
3908                  * If another power sequencer was being used on this
3909                  * port previously make sure to turn off vdd there while
3910                  * we still have control of it.
3911                  */
3912                 vlv_detach_power_sequencer(intel_dp);
3913         }
3914
3915         /*
3916          * We may be stealing the power
3917          * sequencer from another port.
3918          */
3919         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3920
3921         intel_dp->active_pipe = crtc->pipe;
3922
3923         if (!intel_dp_is_edp(intel_dp))
3924                 return;
3925
3926         /* now it's all ours */
3927         intel_dp->pps_pipe = crtc->pipe;
3928
3929         drm_dbg_kms(&dev_priv->drm,
3930                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3931                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3932                     encoder->base.name);
3933
3934         /* init power sequencer on this pipe and port */
3935         intel_dp_init_panel_power_sequencer(intel_dp);
3936         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3937 }
3938
3939 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
3940                               struct intel_encoder *encoder,
3941                               const struct intel_crtc_state *pipe_config,
3942                               const struct drm_connector_state *conn_state)
3943 {
3944         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3945
3946         intel_enable_dp(state, encoder, pipe_config, conn_state);
3947 }
3948
3949 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
3950                                   struct intel_encoder *encoder,
3951                                   const struct intel_crtc_state *pipe_config,
3952                                   const struct drm_connector_state *conn_state)
3953 {
3954         intel_dp_prepare(encoder, pipe_config);
3955
3956         vlv_phy_pre_pll_enable(encoder, pipe_config);
3957 }
3958
3959 static void chv_pre_enable_dp(struct intel_atomic_state *state,
3960                               struct intel_encoder *encoder,
3961                               const struct intel_crtc_state *pipe_config,
3962                               const struct drm_connector_state *conn_state)
3963 {
3964         chv_phy_pre_encoder_enable(encoder, pipe_config);
3965
3966         intel_enable_dp(state, encoder, pipe_config, conn_state);
3967
3968         /* Second common lane will stay alive on its own now */
3969         chv_phy_release_cl2_override(encoder);
3970 }
3971
3972 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
3973                                   struct intel_encoder *encoder,
3974                                   const struct intel_crtc_state *pipe_config,
3975                                   const struct drm_connector_state *conn_state)
3976 {
3977         intel_dp_prepare(encoder, pipe_config);
3978
3979         chv_phy_pre_pll_enable(encoder, pipe_config);
3980 }
3981
3982 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
3983                                     struct intel_encoder *encoder,
3984                                     const struct intel_crtc_state *old_crtc_state,
3985                                     const struct drm_connector_state *old_conn_state)
3986 {
3987         chv_phy_post_pll_disable(encoder, old_crtc_state);
3988 }
3989
3990 /*
3991  * Fetch AUX CH registers 0x202 - 0x207 which contain
3992  * link status information
3993  */
3994 bool
3995 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3996 {
3997         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3998                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3999 }
4000
4001 /* These are source-specific values. */
4002 u8
4003 intel_dp_voltage_max(struct intel_dp *intel_dp)
4004 {
4005         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4006         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4007         enum port port = encoder->port;
4008
4009         if (HAS_DDI(dev_priv))
4010                 return intel_ddi_dp_voltage_max(encoder);
4011         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4012                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4013         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
4014                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4015         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
4016                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4017         else
4018                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4019 }
4020
4021 u8
4022 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
4023 {
4024         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4025         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4026         enum port port = encoder->port;
4027
4028         if (HAS_DDI(dev_priv)) {
4029                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
4030         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4031                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4032                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4033                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
4034                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4035                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4036                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4037                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4038                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4039                 default:
4040                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4041                 }
4042         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4043                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4044                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4045                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4046                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4047                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4048                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4049                 default:
4050                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4051                 }
4052         } else {
4053                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
4054                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4055                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4056                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4057                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4058                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4059                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
4060                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4061                 default:
4062                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
4063                 }
4064         }
4065 }
4066
4067 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
4068 {
4069         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4070         unsigned long demph_reg_value, preemph_reg_value,
4071                 uniqtranscale_reg_value;
4072         u8 train_set = intel_dp->train_set[0];
4073
4074         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4075         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4076                 preemph_reg_value = 0x0004000;
4077                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4078                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4079                         demph_reg_value = 0x2B405555;
4080                         uniqtranscale_reg_value = 0x552AB83A;
4081                         break;
4082                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4083                         demph_reg_value = 0x2B404040;
4084                         uniqtranscale_reg_value = 0x5548B83A;
4085                         break;
4086                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4087                         demph_reg_value = 0x2B245555;
4088                         uniqtranscale_reg_value = 0x5560B83A;
4089                         break;
4090                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4091                         demph_reg_value = 0x2B405555;
4092                         uniqtranscale_reg_value = 0x5598DA3A;
4093                         break;
4094                 default:
4095                         return 0;
4096                 }
4097                 break;
4098         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4099                 preemph_reg_value = 0x0002000;
4100                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4101                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4102                         demph_reg_value = 0x2B404040;
4103                         uniqtranscale_reg_value = 0x5552B83A;
4104                         break;
4105                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4106                         demph_reg_value = 0x2B404848;
4107                         uniqtranscale_reg_value = 0x5580B83A;
4108                         break;
4109                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4110                         demph_reg_value = 0x2B404040;
4111                         uniqtranscale_reg_value = 0x55ADDA3A;
4112                         break;
4113                 default:
4114                         return 0;
4115                 }
4116                 break;
4117         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4118                 preemph_reg_value = 0x0000000;
4119                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4120                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4121                         demph_reg_value = 0x2B305555;
4122                         uniqtranscale_reg_value = 0x5570B83A;
4123                         break;
4124                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4125                         demph_reg_value = 0x2B2B4040;
4126                         uniqtranscale_reg_value = 0x55ADDA3A;
4127                         break;
4128                 default:
4129                         return 0;
4130                 }
4131                 break;
4132         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4133                 preemph_reg_value = 0x0006000;
4134                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4135                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4136                         demph_reg_value = 0x1B405555;
4137                         uniqtranscale_reg_value = 0x55ADDA3A;
4138                         break;
4139                 default:
4140                         return 0;
4141                 }
4142                 break;
4143         default:
4144                 return 0;
4145         }
4146
4147         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
4148                                  uniqtranscale_reg_value, 0);
4149
4150         return 0;
4151 }
4152
4153 static u32 chv_signal_levels(struct intel_dp *intel_dp)
4154 {
4155         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4156         u32 deemph_reg_value, margin_reg_value;
4157         bool uniq_trans_scale = false;
4158         u8 train_set = intel_dp->train_set[0];
4159
4160         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4161         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4162                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4163                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4164                         deemph_reg_value = 128;
4165                         margin_reg_value = 52;
4166                         break;
4167                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4168                         deemph_reg_value = 128;
4169                         margin_reg_value = 77;
4170                         break;
4171                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4172                         deemph_reg_value = 128;
4173                         margin_reg_value = 102;
4174                         break;
4175                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4176                         deemph_reg_value = 128;
4177                         margin_reg_value = 154;
4178                         uniq_trans_scale = true;
4179                         break;
4180                 default:
4181                         return 0;
4182                 }
4183                 break;
4184         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4185                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4186                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4187                         deemph_reg_value = 85;
4188                         margin_reg_value = 78;
4189                         break;
4190                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4191                         deemph_reg_value = 85;
4192                         margin_reg_value = 116;
4193                         break;
4194                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4195                         deemph_reg_value = 85;
4196                         margin_reg_value = 154;
4197                         break;
4198                 default:
4199                         return 0;
4200                 }
4201                 break;
4202         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4203                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4205                         deemph_reg_value = 64;
4206                         margin_reg_value = 104;
4207                         break;
4208                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4209                         deemph_reg_value = 64;
4210                         margin_reg_value = 154;
4211                         break;
4212                 default:
4213                         return 0;
4214                 }
4215                 break;
4216         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4217                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4218                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4219                         deemph_reg_value = 43;
4220                         margin_reg_value = 154;
4221                         break;
4222                 default:
4223                         return 0;
4224                 }
4225                 break;
4226         default:
4227                 return 0;
4228         }
4229
4230         chv_set_phy_signal_level(encoder, deemph_reg_value,
4231                                  margin_reg_value, uniq_trans_scale);
4232
4233         return 0;
4234 }
4235
4236 static u32
4237 g4x_signal_levels(u8 train_set)
4238 {
4239         u32 signal_levels = 0;
4240
4241         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4242         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4243         default:
4244                 signal_levels |= DP_VOLTAGE_0_4;
4245                 break;
4246         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4247                 signal_levels |= DP_VOLTAGE_0_6;
4248                 break;
4249         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4250                 signal_levels |= DP_VOLTAGE_0_8;
4251                 break;
4252         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4253                 signal_levels |= DP_VOLTAGE_1_2;
4254                 break;
4255         }
4256         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4257         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4258         default:
4259                 signal_levels |= DP_PRE_EMPHASIS_0;
4260                 break;
4261         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4262                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4263                 break;
4264         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4265                 signal_levels |= DP_PRE_EMPHASIS_6;
4266                 break;
4267         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4268                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4269                 break;
4270         }
4271         return signal_levels;
4272 }
4273
4274 /* SNB CPU eDP voltage swing and pre-emphasis control */
4275 static u32
4276 snb_cpu_edp_signal_levels(u8 train_set)
4277 {
4278         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4279                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4280         switch (signal_levels) {
4281         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4282         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4283                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4284         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4285                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4286         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4287         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4288                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4289         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4290         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4291                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4292         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4293         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4294                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4295         default:
4296                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4297                               "0x%x\n", signal_levels);
4298                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4299         }
4300 }
4301
4302 /* IVB CPU eDP voltage swing and pre-emphasis control */
4303 static u32
4304 ivb_cpu_edp_signal_levels(u8 train_set)
4305 {
4306         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4307                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4308         switch (signal_levels) {
4309         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4310                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4311         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4312                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4313         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4314                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4315
4316         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4317                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4318         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4319                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4320
4321         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4322                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4323         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4324                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4325
4326         default:
4327                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4328                               "0x%x\n", signal_levels);
4329                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4330         }
4331 }
4332
4333 void
4334 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4335 {
4336         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4337         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4338         enum port port = intel_dig_port->base.port;
4339         u32 signal_levels, mask = 0;
4340         u8 train_set = intel_dp->train_set[0];
4341
4342         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4343                 signal_levels = bxt_signal_levels(intel_dp);
4344         } else if (HAS_DDI(dev_priv)) {
4345                 signal_levels = ddi_signal_levels(intel_dp);
4346                 mask = DDI_BUF_EMP_MASK;
4347         } else if (IS_CHERRYVIEW(dev_priv)) {
4348                 signal_levels = chv_signal_levels(intel_dp);
4349         } else if (IS_VALLEYVIEW(dev_priv)) {
4350                 signal_levels = vlv_signal_levels(intel_dp);
4351         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4352                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4353                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4354         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4355                 signal_levels = snb_cpu_edp_signal_levels(train_set);
4356                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4357         } else {
4358                 signal_levels = g4x_signal_levels(train_set);
4359                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4360         }
4361
4362         if (mask)
4363                 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4364                             signal_levels);
4365
4366         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4367                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4368                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4369         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4370                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4371                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4372                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4373                     " (max)" : "");
4374
4375         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4376
4377         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4378         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4379 }
4380
4381 void
4382 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4383                                        u8 dp_train_pat)
4384 {
4385         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4386         struct drm_i915_private *dev_priv =
4387                 to_i915(intel_dig_port->base.base.dev);
4388
4389         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4390
4391         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4392         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4393 }
4394
4395 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4396 {
4397         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4398         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4399         enum port port = intel_dig_port->base.port;
4400         u32 val;
4401
4402         if (!HAS_DDI(dev_priv))
4403                 return;
4404
4405         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4406         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4407         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4408         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4409
4410         /*
4411          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4412          * reason we need to set idle transmission mode is to work around a HW
4413          * issue where we enable the pipe while not in idle link-training mode.
4414          * In this case there is requirement to wait for a minimum number of
4415          * idle patterns to be sent.
4416          */
4417         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4418                 return;
4419
4420         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4421                                   DP_TP_STATUS_IDLE_DONE, 1))
4422                 drm_err(&dev_priv->drm,
4423                         "Timed out waiting for DP idle patterns\n");
4424 }
4425
4426 static void
4427 intel_dp_link_down(struct intel_encoder *encoder,
4428                    const struct intel_crtc_state *old_crtc_state)
4429 {
4430         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4431         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4432         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4433         enum port port = encoder->port;
4434         u32 DP = intel_dp->DP;
4435
4436         if (drm_WARN_ON(&dev_priv->drm,
4437                         (intel_de_read(dev_priv, intel_dp->output_reg) &
4438                          DP_PORT_EN) == 0))
4439                 return;
4440
4441         drm_dbg_kms(&dev_priv->drm, "\n");
4442
4443         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4444             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4445                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4446                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4447         } else {
4448                 DP &= ~DP_LINK_TRAIN_MASK;
4449                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4450         }
4451         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4452         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4453
4454         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4455         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4456         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4457
4458         /*
4459          * HW workaround for IBX, we need to move the port
4460          * to transcoder A after disabling it to allow the
4461          * matching HDMI port to be enabled on transcoder A.
4462          */
4463         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4464                 /*
4465                  * We get CPU/PCH FIFO underruns on the other pipe when
4466                  * doing the workaround. Sweep them under the rug.
4467                  */
4468                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4469                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4470
4471                 /* always enable with pattern 1 (as per spec) */
4472                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4473                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4474                         DP_LINK_TRAIN_PAT_1;
4475                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4476                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4477
4478                 DP &= ~DP_PORT_EN;
4479                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4480                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4481
4482                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4483                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4484                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4485         }
4486
4487         msleep(intel_dp->panel_power_down_delay);
4488
4489         intel_dp->DP = DP;
4490
4491         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4492                 intel_wakeref_t wakeref;
4493
4494                 with_pps_lock(intel_dp, wakeref)
4495                         intel_dp->active_pipe = INVALID_PIPE;
4496         }
4497 }
4498
4499 static void
4500 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4501 {
4502         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4503         u8 dpcd_ext[6];
4504
4505         /*
4506          * Prior to DP1.3 the bit represented by
4507          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4508          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4509          * the true capability of the panel. The only way to check is to
4510          * then compare 0000h and 2200h.
4511          */
4512         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4513               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4514                 return;
4515
4516         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4517                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4518                 drm_err(&i915->drm,
4519                         "DPCD failed read at extended capabilities\n");
4520                 return;
4521         }
4522
4523         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4524                 drm_dbg_kms(&i915->drm,
4525                             "DPCD extended DPCD rev less than base DPCD rev\n");
4526                 return;
4527         }
4528
4529         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4530                 return;
4531
4532         drm_dbg_kms(&i915->drm, "Base DPCD: %*ph\n",
4533                     (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4534
4535         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4536 }
4537
4538 bool
4539 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4540 {
4541         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4542
4543         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4544                              sizeof(intel_dp->dpcd)) < 0)
4545                 return false; /* aux transfer failed */
4546
4547         intel_dp_extended_receiver_capabilities(intel_dp);
4548
4549         drm_dbg_kms(&i915->drm, "DPCD: %*ph\n", (int)sizeof(intel_dp->dpcd),
4550                     intel_dp->dpcd);
4551
4552         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4553 }
4554
4555 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4556 {
4557         u8 dprx = 0;
4558
4559         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4560                               &dprx) != 1)
4561                 return false;
4562         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4563 }
4564
4565 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4566 {
4567         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4568
4569         /*
4570          * Clear the cached register set to avoid using stale values
4571          * for the sinks that do not support DSC.
4572          */
4573         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4574
4575         /* Clear fec_capable to avoid using stale values */
4576         intel_dp->fec_capable = 0;
4577
4578         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4579         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4580             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4581                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4582                                      intel_dp->dsc_dpcd,
4583                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4584                         drm_err(&i915->drm,
4585                                 "Failed to read DPCD register 0x%x\n",
4586                                 DP_DSC_SUPPORT);
4587
4588                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4589                             (int)sizeof(intel_dp->dsc_dpcd),
4590                             intel_dp->dsc_dpcd);
4591
4592                 /* FEC is supported only on DP 1.4 */
4593                 if (!intel_dp_is_edp(intel_dp) &&
4594                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4595                                       &intel_dp->fec_capable) < 0)
4596                         drm_err(&i915->drm,
4597                                 "Failed to read FEC DPCD register\n");
4598
4599                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4600                             intel_dp->fec_capable);
4601         }
4602 }
4603
4604 static bool
4605 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4606 {
4607         struct drm_i915_private *dev_priv =
4608                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4609
4610         /* this function is meant to be called only once */
4611         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4612
4613         if (!intel_dp_read_dpcd(intel_dp))
4614                 return false;
4615
4616         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4617                          drm_dp_is_branch(intel_dp->dpcd));
4618
4619         /*
4620          * Read the eDP display control registers.
4621          *
4622          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4623          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4624          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4625          * method). The display control registers should read zero if they're
4626          * not supported anyway.
4627          */
4628         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4629                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4630                              sizeof(intel_dp->edp_dpcd))
4631                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4632                             (int)sizeof(intel_dp->edp_dpcd),
4633                             intel_dp->edp_dpcd);
4634
4635         /*
4636          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4637          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4638          */
4639         intel_psr_init_dpcd(intel_dp);
4640
4641         /* Read the eDP 1.4+ supported link rates. */
4642         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4643                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4644                 int i;
4645
4646                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4647                                 sink_rates, sizeof(sink_rates));
4648
4649                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4650                         int val = le16_to_cpu(sink_rates[i]);
4651
4652                         if (val == 0)
4653                                 break;
4654
4655                         /* Value read multiplied by 200kHz gives the per-lane
4656                          * link rate in kHz. The source rates are, however,
4657                          * stored in terms of LS_Clk kHz. The full conversion
4658                          * back to symbols is
4659                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4660                          */
4661                         intel_dp->sink_rates[i] = (val * 200) / 10;
4662                 }
4663                 intel_dp->num_sink_rates = i;
4664         }
4665
4666         /*
4667          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4668          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4669          */
4670         if (intel_dp->num_sink_rates)
4671                 intel_dp->use_rate_select = true;
4672         else
4673                 intel_dp_set_sink_rates(intel_dp);
4674
4675         intel_dp_set_common_rates(intel_dp);
4676
4677         /* Read the eDP DSC DPCD registers */
4678         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4679                 intel_dp_get_dsc_sink_cap(intel_dp);
4680
4681         return true;
4682 }
4683
4684
4685 static bool
4686 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4687 {
4688         if (!intel_dp_read_dpcd(intel_dp))
4689                 return false;
4690
4691         /*
4692          * Don't clobber cached eDP rates. Also skip re-reading
4693          * the OUI/ID since we know it won't change.
4694          */
4695         if (!intel_dp_is_edp(intel_dp)) {
4696                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4697                                  drm_dp_is_branch(intel_dp->dpcd));
4698
4699                 intel_dp_set_sink_rates(intel_dp);
4700                 intel_dp_set_common_rates(intel_dp);
4701         }
4702
4703         /*
4704          * Some eDP panels do not set a valid value for sink count, that is why
4705          * it don't care about read it here and in intel_edp_init_dpcd().
4706          */
4707         if (!intel_dp_is_edp(intel_dp) &&
4708             !drm_dp_has_quirk(&intel_dp->desc, 0,
4709                               DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4710                 u8 count;
4711                 ssize_t r;
4712
4713                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4714                 if (r < 1)
4715                         return false;
4716
4717                 /*
4718                  * Sink count can change between short pulse hpd hence
4719                  * a member variable in intel_dp will track any changes
4720                  * between short pulse interrupts.
4721                  */
4722                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4723
4724                 /*
4725                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4726                  * a dongle is present but no display. Unless we require to know
4727                  * if a dongle is present or not, we don't need to update
4728                  * downstream port information. So, an early return here saves
4729                  * time from performing other operations which are not required.
4730                  */
4731                 if (!intel_dp->sink_count)
4732                         return false;
4733         }
4734
4735         if (!drm_dp_is_branch(intel_dp->dpcd))
4736                 return true; /* native DP sink */
4737
4738         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4739                 return true; /* no per-port downstream info */
4740
4741         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4742                              intel_dp->downstream_ports,
4743                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4744                 return false; /* downstream port status fetch failed */
4745
4746         return true;
4747 }
4748
4749 static bool
4750 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4751 {
4752         u8 mstm_cap;
4753
4754         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4755                 return false;
4756
4757         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4758                 return false;
4759
4760         return mstm_cap & DP_MST_CAP;
4761 }
4762
4763 static bool
4764 intel_dp_can_mst(struct intel_dp *intel_dp)
4765 {
4766         return i915_modparams.enable_dp_mst &&
4767                 intel_dp->can_mst &&
4768                 intel_dp_sink_can_mst(intel_dp);
4769 }
4770
4771 static void
4772 intel_dp_configure_mst(struct intel_dp *intel_dp)
4773 {
4774         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4775         struct intel_encoder *encoder =
4776                 &dp_to_dig_port(intel_dp)->base;
4777         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4778
4779         drm_dbg_kms(&i915->drm,
4780                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4781                     encoder->base.base.id, encoder->base.name,
4782                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
4783                     yesno(i915_modparams.enable_dp_mst));
4784
4785         if (!intel_dp->can_mst)
4786                 return;
4787
4788         intel_dp->is_mst = sink_can_mst &&
4789                 i915_modparams.enable_dp_mst;
4790
4791         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4792                                         intel_dp->is_mst);
4793 }
4794
4795 static bool
4796 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4797 {
4798         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4799                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4800                 DP_DPRX_ESI_LEN;
4801 }
4802
4803 bool
4804 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4805                        const struct drm_connector_state *conn_state)
4806 {
4807         /*
4808          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4809          * of Color Encoding Format and Content Color Gamut], in order to
4810          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4811          */
4812         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4813                 return true;
4814
4815         switch (conn_state->colorspace) {
4816         case DRM_MODE_COLORIMETRY_SYCC_601:
4817         case DRM_MODE_COLORIMETRY_OPYCC_601:
4818         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4819         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4820         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4821                 return true;
4822         default:
4823                 break;
4824         }
4825
4826         return false;
4827 }
4828
4829 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
4830                                      struct dp_sdp *sdp, size_t size)
4831 {
4832         size_t length = sizeof(struct dp_sdp);
4833
4834         if (size < length)
4835                 return -ENOSPC;
4836
4837         memset(sdp, 0, size);
4838
4839         /*
4840          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
4841          * VSC SDP Header Bytes
4842          */
4843         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
4844         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
4845         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
4846         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
4847
4848         /* VSC SDP Payload for DB16 through DB18 */
4849         /* Pixel Encoding and Colorimetry Formats  */
4850         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
4851         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
4852
4853         switch (vsc->bpc) {
4854         case 6:
4855                 /* 6bpc: 0x0 */
4856                 break;
4857         case 8:
4858                 sdp->db[17] = 0x1; /* DB17[3:0] */
4859                 break;
4860         case 10:
4861                 sdp->db[17] = 0x2;
4862                 break;
4863         case 12:
4864                 sdp->db[17] = 0x3;
4865                 break;
4866         case 16:
4867                 sdp->db[17] = 0x4;
4868                 break;
4869         default:
4870                 MISSING_CASE(vsc->bpc);
4871                 break;
4872         }
4873         /* Dynamic Range and Component Bit Depth */
4874         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
4875                 sdp->db[17] |= 0x80;  /* DB17[7] */
4876
4877         /* Content Type */
4878         sdp->db[18] = vsc->content_type & 0x7;
4879
4880         return length;
4881 }
4882
4883 static ssize_t
4884 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
4885                                          struct dp_sdp *sdp,
4886                                          size_t size)
4887 {
4888         size_t length = sizeof(struct dp_sdp);
4889         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4890         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4891         ssize_t len;
4892
4893         if (size < length)
4894                 return -ENOSPC;
4895
4896         memset(sdp, 0, size);
4897
4898         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4899         if (len < 0) {
4900                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4901                 return -ENOSPC;
4902         }
4903
4904         if (len != infoframe_size) {
4905                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4906                 return -ENOSPC;
4907         }
4908
4909         /*
4910          * Set up the infoframe sdp packet for HDR static metadata.
4911          * Prepare VSC Header for SU as per DP 1.4a spec,
4912          * Table 2-100 and Table 2-101
4913          */
4914
4915         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4916         sdp->sdp_header.HB0 = 0;
4917         /*
4918          * Packet Type 80h + Non-audio INFOFRAME Type value
4919          * HDMI_INFOFRAME_TYPE_DRM: 0x87
4920          * - 80h + Non-audio INFOFRAME Type value
4921          * - InfoFrame Type: 0x07
4922          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4923          */
4924         sdp->sdp_header.HB1 = drm_infoframe->type;
4925         /*
4926          * Least Significant Eight Bits of (Data Byte Count – 1)
4927          * infoframe_size - 1
4928          */
4929         sdp->sdp_header.HB2 = 0x1D;
4930         /* INFOFRAME SDP Version Number */
4931         sdp->sdp_header.HB3 = (0x13 << 2);
4932         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4933         sdp->db[0] = drm_infoframe->version;
4934         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4935         sdp->db[1] = drm_infoframe->length;
4936         /*
4937          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4938          * HDMI_INFOFRAME_HEADER_SIZE
4939          */
4940         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4941         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4942                HDMI_DRM_INFOFRAME_SIZE);
4943
4944         /*
4945          * Size of DP infoframe sdp packet for HDR static metadata consists of
4946          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4947          * - Two Data Blocks: 2 bytes
4948          *    CTA Header Byte2 (INFOFRAME Version Number)
4949          *    CTA Header Byte3 (Length of INFOFRAME)
4950          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4951          *
4952          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4953          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4954          * will pad rest of the size.
4955          */
4956         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4957 }
4958
4959 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4960                                const struct intel_crtc_state *crtc_state,
4961                                unsigned int type)
4962 {
4963         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4964         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4965         struct dp_sdp sdp = {};
4966         ssize_t len;
4967
4968         if ((crtc_state->infoframes.enable &
4969              intel_hdmi_infoframe_enable(type)) == 0)
4970                 return;
4971
4972         switch (type) {
4973         case DP_SDP_VSC:
4974                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4975                                             sizeof(sdp));
4976                 break;
4977         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4978                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
4979                                                                &sdp, sizeof(sdp));
4980                 break;
4981         default:
4982                 MISSING_CASE(type);
4983                 return;
4984         }
4985
4986         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4987                 return;
4988
4989         intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4990 }
4991
4992 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4993                              bool enable,
4994                              const struct intel_crtc_state *crtc_state,
4995                              const struct drm_connector_state *conn_state)
4996 {
4997         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4998         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4999         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5000         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5001                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5002                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5003         u32 val = intel_de_read(dev_priv, reg);
5004
5005         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5006         /* When PSR is enabled, this routine doesn't disable VSC DIP */
5007         if (intel_psr_enabled(intel_dp))
5008                 val &= ~dip_enable;
5009         else
5010                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5011
5012         if (!enable) {
5013                 intel_de_write(dev_priv, reg, val);
5014                 intel_de_posting_read(dev_priv, reg);
5015                 return;
5016         }
5017
5018         intel_de_write(dev_priv, reg, val);
5019         intel_de_posting_read(dev_priv, reg);
5020
5021         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5022         if (!intel_psr_enabled(intel_dp))
5023                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5024
5025         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5026 }
5027
5028 static void
5029 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
5030                        const struct intel_crtc_state *crtc_state,
5031                        const struct drm_connector_state *conn_state)
5032 {
5033         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5034         struct dp_sdp vsc_sdp = {};
5035
5036         /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
5037         vsc_sdp.sdp_header.HB0 = 0;
5038         vsc_sdp.sdp_header.HB1 = 0x7;
5039
5040         /*
5041          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
5042          * Colorimetry Format indication.
5043          */
5044         vsc_sdp.sdp_header.HB2 = 0x5;
5045
5046         /*
5047          * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
5048          * Colorimetry Format indication (HB2 = 05h).
5049          */
5050         vsc_sdp.sdp_header.HB3 = 0x13;
5051
5052         /* DP 1.4a spec, Table 2-120 */
5053         switch (crtc_state->output_format) {
5054         case INTEL_OUTPUT_FORMAT_YCBCR444:
5055                 vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
5056                 break;
5057         case INTEL_OUTPUT_FORMAT_YCBCR420:
5058                 vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
5059                 break;
5060         case INTEL_OUTPUT_FORMAT_RGB:
5061         default:
5062                 /* RGB: DB16[7:4] = 0h */
5063                 break;
5064         }
5065
5066         switch (conn_state->colorspace) {
5067         case DRM_MODE_COLORIMETRY_BT709_YCC:
5068                 vsc_sdp.db[16] |= 0x1;
5069                 break;
5070         case DRM_MODE_COLORIMETRY_XVYCC_601:
5071                 vsc_sdp.db[16] |= 0x2;
5072                 break;
5073         case DRM_MODE_COLORIMETRY_XVYCC_709:
5074                 vsc_sdp.db[16] |= 0x3;
5075                 break;
5076         case DRM_MODE_COLORIMETRY_SYCC_601:
5077                 vsc_sdp.db[16] |= 0x4;
5078                 break;
5079         case DRM_MODE_COLORIMETRY_OPYCC_601:
5080                 vsc_sdp.db[16] |= 0x5;
5081                 break;
5082         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
5083         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5084                 vsc_sdp.db[16] |= 0x6;
5085                 break;
5086         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5087                 vsc_sdp.db[16] |= 0x7;
5088                 break;
5089         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
5090         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
5091                 vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
5092                 break;
5093         default:
5094                 /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
5095
5096                 /* RGB->YCBCR color conversion uses the BT.709 color space. */
5097                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5098                         vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
5099                 break;
5100         }
5101
5102         /*
5103          * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
5104          * the following Component Bit Depth values are defined:
5105          * 001b = 8bpc.
5106          * 010b = 10bpc.
5107          * 011b = 12bpc.
5108          * 100b = 16bpc.
5109          */
5110         switch (crtc_state->pipe_bpp) {
5111         case 24: /* 8bpc */
5112                 vsc_sdp.db[17] = 0x1;
5113                 break;
5114         case 30: /* 10bpc */
5115                 vsc_sdp.db[17] = 0x2;
5116                 break;
5117         case 36: /* 12bpc */
5118                 vsc_sdp.db[17] = 0x3;
5119                 break;
5120         case 48: /* 16bpc */
5121                 vsc_sdp.db[17] = 0x4;
5122                 break;
5123         default:
5124                 MISSING_CASE(crtc_state->pipe_bpp);
5125                 break;
5126         }
5127
5128         /*
5129          * Dynamic Range (Bit 7)
5130          * 0 = VESA range, 1 = CTA range.
5131          * all YCbCr are always limited range
5132          */
5133         vsc_sdp.db[17] |= 0x80;
5134
5135         /*
5136          * Content Type (Bits 2:0)
5137          * 000b = Not defined.
5138          * 001b = Graphics.
5139          * 010b = Photo.
5140          * 011b = Video.
5141          * 100b = Game
5142          * All other values are RESERVED.
5143          * Note: See CTA-861-G for the definition and expected
5144          * processing by a stream sink for the above contect types.
5145          */
5146         vsc_sdp.db[18] = 0;
5147
5148         intel_dig_port->write_infoframe(&intel_dig_port->base,
5149                         crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
5150 }
5151
5152 static void
5153 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
5154                                           const struct intel_crtc_state *crtc_state,
5155                                           const struct drm_connector_state *conn_state)
5156 {
5157         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5158         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5159         struct dp_sdp infoframe_sdp = {};
5160         struct hdmi_drm_infoframe drm_infoframe = {};
5161         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5162         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5163         ssize_t len;
5164         int ret;
5165
5166         ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
5167         if (ret) {
5168                 drm_dbg_kms(&i915->drm,
5169                             "couldn't set HDR metadata in infoframe\n");
5170                 return;
5171         }
5172
5173         len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
5174         if (len < 0) {
5175                 drm_dbg_kms(&i915->drm,
5176                             "buffer size is smaller than hdr metadata infoframe\n");
5177                 return;
5178         }
5179
5180         if (len != infoframe_size) {
5181                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
5182                 return;
5183         }
5184
5185         /*
5186          * Set up the infoframe sdp packet for HDR static metadata.
5187          * Prepare VSC Header for SU as per DP 1.4a spec,
5188          * Table 2-100 and Table 2-101
5189          */
5190
5191         /* Packet ID, 00h for non-Audio INFOFRAME */
5192         infoframe_sdp.sdp_header.HB0 = 0;
5193         /*
5194          * Packet Type 80h + Non-audio INFOFRAME Type value
5195          * HDMI_INFOFRAME_TYPE_DRM: 0x87,
5196          */
5197         infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
5198         /*
5199          * Least Significant Eight Bits of (Data Byte Count – 1)
5200          * infoframe_size - 1,
5201          */
5202         infoframe_sdp.sdp_header.HB2 = 0x1D;
5203         /* INFOFRAME SDP Version Number */
5204         infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
5205         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5206         infoframe_sdp.db[0] = drm_infoframe.version;
5207         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5208         infoframe_sdp.db[1] = drm_infoframe.length;
5209         /*
5210          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5211          * HDMI_INFOFRAME_HEADER_SIZE
5212          */
5213         BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5214         memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5215                HDMI_DRM_INFOFRAME_SIZE);
5216
5217         /*
5218          * Size of DP infoframe sdp packet for HDR static metadata is consist of
5219          * - DP SDP Header(struct dp_sdp_header): 4 bytes
5220          * - Two Data Blocks: 2 bytes
5221          *    CTA Header Byte2 (INFOFRAME Version Number)
5222          *    CTA Header Byte3 (Length of INFOFRAME)
5223          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5224          *
5225          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5226          * infoframe size. But GEN11+ has larger than that size, write_infoframe
5227          * will pad rest of the size.
5228          */
5229         intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
5230                                         HDMI_PACKET_TYPE_GAMUT_METADATA,
5231                                         &infoframe_sdp,
5232                                         sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
5233 }
5234
5235 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
5236                          const struct intel_crtc_state *crtc_state,
5237                          const struct drm_connector_state *conn_state)
5238 {
5239         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
5240                 return;
5241
5242         intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
5243 }
5244
5245 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
5246                                   const struct intel_crtc_state *crtc_state,
5247                                   const struct drm_connector_state *conn_state)
5248 {
5249         if (!conn_state->hdr_output_metadata)
5250                 return;
5251
5252         intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
5253                                                   crtc_state,
5254                                                   conn_state);
5255 }
5256
5257 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5258 {
5259         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5260         int status = 0;
5261         int test_link_rate;
5262         u8 test_lane_count, test_link_bw;
5263         /* (DP CTS 1.2)
5264          * 4.3.1.11
5265          */
5266         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5267         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5268                                    &test_lane_count);
5269
5270         if (status <= 0) {
5271                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5272                 return DP_TEST_NAK;
5273         }
5274         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5275
5276         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5277                                    &test_link_bw);
5278         if (status <= 0) {
5279                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5280                 return DP_TEST_NAK;
5281         }
5282         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5283
5284         /* Validate the requested link rate and lane count */
5285         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5286                                         test_lane_count))
5287                 return DP_TEST_NAK;
5288
5289         intel_dp->compliance.test_lane_count = test_lane_count;
5290         intel_dp->compliance.test_link_rate = test_link_rate;
5291
5292         return DP_TEST_ACK;
5293 }
5294
5295 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5296 {
5297         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5298         u8 test_pattern;
5299         u8 test_misc;
5300         __be16 h_width, v_height;
5301         int status = 0;
5302
5303         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5304         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5305                                    &test_pattern);
5306         if (status <= 0) {
5307                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5308                 return DP_TEST_NAK;
5309         }
5310         if (test_pattern != DP_COLOR_RAMP)
5311                 return DP_TEST_NAK;
5312
5313         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5314                                   &h_width, 2);
5315         if (status <= 0) {
5316                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5317                 return DP_TEST_NAK;
5318         }
5319
5320         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5321                                   &v_height, 2);
5322         if (status <= 0) {
5323                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5324                 return DP_TEST_NAK;
5325         }
5326
5327         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5328                                    &test_misc);
5329         if (status <= 0) {
5330                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5331                 return DP_TEST_NAK;
5332         }
5333         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5334                 return DP_TEST_NAK;
5335         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5336                 return DP_TEST_NAK;
5337         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5338         case DP_TEST_BIT_DEPTH_6:
5339                 intel_dp->compliance.test_data.bpc = 6;
5340                 break;
5341         case DP_TEST_BIT_DEPTH_8:
5342                 intel_dp->compliance.test_data.bpc = 8;
5343                 break;
5344         default:
5345                 return DP_TEST_NAK;
5346         }
5347
5348         intel_dp->compliance.test_data.video_pattern = test_pattern;
5349         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5350         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5351         /* Set test active flag here so userspace doesn't interrupt things */
5352         intel_dp->compliance.test_active = true;
5353
5354         return DP_TEST_ACK;
5355 }
5356
5357 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5358 {
5359         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5360         u8 test_result = DP_TEST_ACK;
5361         struct intel_connector *intel_connector = intel_dp->attached_connector;
5362         struct drm_connector *connector = &intel_connector->base;
5363
5364         if (intel_connector->detect_edid == NULL ||
5365             connector->edid_corrupt ||
5366             intel_dp->aux.i2c_defer_count > 6) {
5367                 /* Check EDID read for NACKs, DEFERs and corruption
5368                  * (DP CTS 1.2 Core r1.1)
5369                  *    4.2.2.4 : Failed EDID read, I2C_NAK
5370                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
5371                  *    4.2.2.6 : EDID corruption detected
5372                  * Use failsafe mode for all cases
5373                  */
5374                 if (intel_dp->aux.i2c_nack_count > 0 ||
5375                         intel_dp->aux.i2c_defer_count > 0)
5376                         drm_dbg_kms(&i915->drm,
5377                                     "EDID read had %d NACKs, %d DEFERs\n",
5378                                     intel_dp->aux.i2c_nack_count,
5379                                     intel_dp->aux.i2c_defer_count);
5380                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5381         } else {
5382                 struct edid *block = intel_connector->detect_edid;
5383
5384                 /* We have to write the checksum
5385                  * of the last block read
5386                  */
5387                 block += intel_connector->detect_edid->extensions;
5388
5389                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5390                                        block->checksum) <= 0)
5391                         drm_dbg_kms(&i915->drm,
5392                                     "Failed to write EDID checksum\n");
5393
5394                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5395                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5396         }
5397
5398         /* Set test active flag here so userspace doesn't interrupt things */
5399         intel_dp->compliance.test_active = true;
5400
5401         return test_result;
5402 }
5403
5404 static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
5405 {
5406         struct drm_dp_phy_test_params *data =
5407                 &intel_dp->compliance.test_data.phytest;
5408
5409         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5410                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5411                 return DP_TEST_NAK;
5412         }
5413
5414         /*
5415          * link_mst is set to false to avoid executing mst related code
5416          * during compliance testing.
5417          */
5418         intel_dp->link_mst = false;
5419
5420         return DP_TEST_ACK;
5421 }
5422
5423 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
5424 {
5425         struct drm_i915_private *dev_priv =
5426                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5427         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5428         struct drm_dp_phy_test_params *data =
5429                         &intel_dp->compliance.test_data.phytest;
5430         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5431         enum pipe pipe = crtc->pipe;
5432         u32 pattern_val;
5433
5434         switch (data->phy_pattern) {
5435         case DP_PHY_TEST_PATTERN_NONE:
5436                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5437                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5438                 break;
5439         case DP_PHY_TEST_PATTERN_D10_2:
5440                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5441                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5442                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5443                 break;
5444         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5445                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5446                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5447                                DDI_DP_COMP_CTL_ENABLE |
5448                                DDI_DP_COMP_CTL_SCRAMBLED_0);
5449                 break;
5450         case DP_PHY_TEST_PATTERN_PRBS7:
5451                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5452                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5453                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5454                 break;
5455         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5456                 /*
5457                  * FIXME: Ideally pattern should come from DPCD 0x250. As
5458                  * current firmware of DPR-100 could not set it, so hardcoding
5459                  * now for complaince test.
5460                  */
5461                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5462                 pattern_val = 0x3e0f83e0;
5463                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5464                 pattern_val = 0x0f83e0f8;
5465                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5466                 pattern_val = 0x0000f83e;
5467                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5468                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5469                                DDI_DP_COMP_CTL_ENABLE |
5470                                DDI_DP_COMP_CTL_CUSTOM80);
5471                 break;
5472         case DP_PHY_TEST_PATTERN_CP2520:
5473                 /*
5474                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
5475                  * current firmware of DPR-100 could not set it, so hardcoding
5476                  * now for complaince test.
5477                  */
5478                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5479                 pattern_val = 0xFB;
5480                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5481                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5482                                pattern_val);
5483                 break;
5484         default:
5485                 WARN(1, "Invalid Phy Test Pattern\n");
5486         }
5487 }
5488
5489 static void
5490 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
5491 {
5492         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5493         struct drm_device *dev = intel_dig_port->base.base.dev;
5494         struct drm_i915_private *dev_priv = to_i915(dev);
5495         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5496         enum pipe pipe = crtc->pipe;
5497         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5498
5499         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5500                                                  TRANS_DDI_FUNC_CTL(pipe));
5501         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5502         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5503
5504         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5505                                       TGL_TRANS_DDI_PORT_MASK);
5506         trans_conf_value &= ~PIPECONF_ENABLE;
5507         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5508
5509         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5510         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5511                        trans_ddi_func_ctl_value);
5512         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5513 }
5514
5515 static void
5516 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
5517 {
5518         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5519         struct drm_device *dev = intel_dig_port->base.base.dev;
5520         struct drm_i915_private *dev_priv = to_i915(dev);
5521         enum port port = intel_dig_port->base.port;
5522         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
5523         enum pipe pipe = crtc->pipe;
5524         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5525
5526         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5527                                                  TRANS_DDI_FUNC_CTL(pipe));
5528         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5529         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5530
5531         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5532                                     TGL_TRANS_DDI_SELECT_PORT(port);
5533         trans_conf_value |= PIPECONF_ENABLE;
5534         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5535
5536         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5537         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5538         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5539                        trans_ddi_func_ctl_value);
5540 }
5541
5542 void intel_dp_process_phy_request(struct intel_dp *intel_dp)
5543 {
5544         struct drm_dp_phy_test_params *data =
5545                 &intel_dp->compliance.test_data.phytest;
5546         u8 link_status[DP_LINK_STATUS_SIZE];
5547
5548         if (!intel_dp_get_link_status(intel_dp, link_status)) {
5549                 DRM_DEBUG_KMS("failed to get link status\n");
5550                 return;
5551         }
5552
5553         /* retrieve vswing & pre-emphasis setting */
5554         intel_dp_get_adjust_train(intel_dp, link_status);
5555
5556         intel_dp_autotest_phy_ddi_disable(intel_dp);
5557
5558         intel_dp_set_signal_levels(intel_dp);
5559
5560         intel_dp_phy_pattern_update(intel_dp);
5561
5562         intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
5563
5564         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5565                                     link_status[DP_DPCD_REV]);
5566 }
5567
5568 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5569 {
5570         u8 test_result = DP_TEST_NAK;
5571
5572         test_result = intel_dp_prepare_phytest(intel_dp);
5573         if (test_result != DP_TEST_ACK)
5574                 DRM_ERROR("Phy test preparation failed\n");
5575
5576         intel_dp_process_phy_request(intel_dp);
5577
5578         return test_result;
5579 }
5580
5581 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5582 {
5583         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5584         u8 response = DP_TEST_NAK;
5585         u8 request = 0;
5586         int status;
5587
5588         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5589         if (status <= 0) {
5590                 drm_dbg_kms(&i915->drm,
5591                             "Could not read test request from sink\n");
5592                 goto update_status;
5593         }
5594
5595         switch (request) {
5596         case DP_TEST_LINK_TRAINING:
5597                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5598                 response = intel_dp_autotest_link_training(intel_dp);
5599                 break;
5600         case DP_TEST_LINK_VIDEO_PATTERN:
5601                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5602                 response = intel_dp_autotest_video_pattern(intel_dp);
5603                 break;
5604         case DP_TEST_LINK_EDID_READ:
5605                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5606                 response = intel_dp_autotest_edid(intel_dp);
5607                 break;
5608         case DP_TEST_LINK_PHY_TEST_PATTERN:
5609                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5610                 response = intel_dp_autotest_phy_pattern(intel_dp);
5611                 break;
5612         default:
5613                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5614                             request);
5615                 break;
5616         }
5617
5618         if (response & DP_TEST_ACK)
5619                 intel_dp->compliance.test_type = request;
5620
5621 update_status:
5622         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5623         if (status <= 0)
5624                 drm_dbg_kms(&i915->drm,
5625                             "Could not write test response to sink\n");
5626 }
5627
5628 static int
5629 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5630 {
5631         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5632         bool bret;
5633
5634         if (intel_dp->is_mst) {
5635                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
5636                 int ret = 0;
5637                 int retry;
5638                 bool handled;
5639
5640                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
5641                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5642 go_again:
5643                 if (bret == true) {
5644
5645                         /* check link status - esi[10] = 0x200c */
5646                         if (intel_dp->active_mst_links > 0 &&
5647                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5648                                 drm_dbg_kms(&i915->drm,
5649                                             "channel EQ not ok, retraining\n");
5650                                 intel_dp_start_link_train(intel_dp);
5651                                 intel_dp_stop_link_train(intel_dp);
5652                         }
5653
5654                         drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5655                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5656
5657                         if (handled) {
5658                                 for (retry = 0; retry < 3; retry++) {
5659                                         int wret;
5660                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
5661                                                                  DP_SINK_COUNT_ESI+1,
5662                                                                  &esi[1], 3);
5663                                         if (wret == 3) {
5664                                                 break;
5665                                         }
5666                                 }
5667
5668                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5669                                 if (bret == true) {
5670                                         drm_dbg_kms(&i915->drm,
5671                                                     "got esi2 %3ph\n", esi);
5672                                         goto go_again;
5673                                 }
5674                         } else
5675                                 ret = 0;
5676
5677                         return ret;
5678                 } else {
5679                         drm_dbg_kms(&i915->drm,
5680                                     "failed to get ESI - device may have failed\n");
5681                         intel_dp->is_mst = false;
5682                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5683                                                         intel_dp->is_mst);
5684                 }
5685         }
5686         return -EINVAL;
5687 }
5688
5689 static bool
5690 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5691 {
5692         u8 link_status[DP_LINK_STATUS_SIZE];
5693
5694         if (!intel_dp->link_trained)
5695                 return false;
5696
5697         /*
5698          * While PSR source HW is enabled, it will control main-link sending
5699          * frames, enabling and disabling it so trying to do a retrain will fail
5700          * as the link would or not be on or it could mix training patterns
5701          * and frame data at the same time causing retrain to fail.
5702          * Also when exiting PSR, HW will retrain the link anyways fixing
5703          * any link status error.
5704          */
5705         if (intel_psr_enabled(intel_dp))
5706                 return false;
5707
5708         if (!intel_dp_get_link_status(intel_dp, link_status))
5709                 return false;
5710
5711         /*
5712          * Validate the cached values of intel_dp->link_rate and
5713          * intel_dp->lane_count before attempting to retrain.
5714          */
5715         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5716                                         intel_dp->lane_count))
5717                 return false;
5718
5719         /* Retrain if Channel EQ or CR not ok */
5720         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5721 }
5722
5723 int intel_dp_retrain_link(struct intel_encoder *encoder,
5724                           struct drm_modeset_acquire_ctx *ctx)
5725 {
5726         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5727         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5728         struct intel_connector *connector = intel_dp->attached_connector;
5729         struct drm_connector_state *conn_state;
5730         struct intel_crtc_state *crtc_state;
5731         struct intel_crtc *crtc;
5732         int ret;
5733
5734         /* FIXME handle the MST connectors as well */
5735
5736         if (!connector || connector->base.status != connector_status_connected)
5737                 return 0;
5738
5739         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5740                                ctx);
5741         if (ret)
5742                 return ret;
5743
5744         conn_state = connector->base.state;
5745
5746         crtc = to_intel_crtc(conn_state->crtc);
5747         if (!crtc)
5748                 return 0;
5749
5750         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5751         if (ret)
5752                 return ret;
5753
5754         crtc_state = to_intel_crtc_state(crtc->base.state);
5755
5756         drm_WARN_ON(&dev_priv->drm, !intel_crtc_has_dp_encoder(crtc_state));
5757
5758         if (!crtc_state->hw.active)
5759                 return 0;
5760
5761         if (conn_state->commit &&
5762             !try_wait_for_completion(&conn_state->commit->hw_done))
5763                 return 0;
5764
5765         if (!intel_dp_needs_link_retrain(intel_dp))
5766                 return 0;
5767
5768         /* Suppress underruns caused by re-training */
5769         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5770         if (crtc_state->has_pch_encoder)
5771                 intel_set_pch_fifo_underrun_reporting(dev_priv,
5772                                                       intel_crtc_pch_transcoder(crtc), false);
5773
5774         intel_dp_start_link_train(intel_dp);
5775         intel_dp_stop_link_train(intel_dp);
5776
5777         /* Keep underrun reporting disabled until things are stable */
5778         intel_wait_for_vblank(dev_priv, crtc->pipe);
5779
5780         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5781         if (crtc_state->has_pch_encoder)
5782                 intel_set_pch_fifo_underrun_reporting(dev_priv,
5783                                                       intel_crtc_pch_transcoder(crtc), true);
5784
5785         return 0;
5786 }
5787
5788 /*
5789  * If display is now connected check links status,
5790  * there has been known issues of link loss triggering
5791  * long pulse.
5792  *
5793  * Some sinks (eg. ASUS PB287Q) seem to perform some
5794  * weird HPD ping pong during modesets. So we can apparently
5795  * end up with HPD going low during a modeset, and then
5796  * going back up soon after. And once that happens we must
5797  * retrain the link to get a picture. That's in case no
5798  * userspace component reacted to intermittent HPD dip.
5799  */
5800 static enum intel_hotplug_state
5801 intel_dp_hotplug(struct intel_encoder *encoder,
5802                  struct intel_connector *connector)
5803 {
5804         struct drm_modeset_acquire_ctx ctx;
5805         enum intel_hotplug_state state;
5806         int ret;
5807
5808         state = intel_encoder_hotplug(encoder, connector);
5809
5810         drm_modeset_acquire_init(&ctx, 0);
5811
5812         for (;;) {
5813                 ret = intel_dp_retrain_link(encoder, &ctx);
5814
5815                 if (ret == -EDEADLK) {
5816                         drm_modeset_backoff(&ctx);
5817                         continue;
5818                 }
5819
5820                 break;
5821         }
5822
5823         drm_modeset_drop_locks(&ctx);
5824         drm_modeset_acquire_fini(&ctx);
5825         drm_WARN(encoder->base.dev, ret,
5826                  "Acquiring modeset locks failed with %i\n", ret);
5827
5828         /*
5829          * Keeping it consistent with intel_ddi_hotplug() and
5830          * intel_hdmi_hotplug().
5831          */
5832         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
5833                 state = INTEL_HOTPLUG_RETRY;
5834
5835         return state;
5836 }
5837
5838 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5839 {
5840         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5841         u8 val;
5842
5843         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5844                 return;
5845
5846         if (drm_dp_dpcd_readb(&intel_dp->aux,
5847                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5848                 return;
5849
5850         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5851
5852         if (val & DP_AUTOMATED_TEST_REQUEST)
5853                 intel_dp_handle_test_request(intel_dp);
5854
5855         if (val & DP_CP_IRQ)
5856                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5857
5858         if (val & DP_SINK_SPECIFIC_IRQ)
5859                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5860 }
5861
5862 /*
5863  * According to DP spec
5864  * 5.1.2:
5865  *  1. Read DPCD
5866  *  2. Configure link according to Receiver Capabilities
5867  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5868  *  4. Check link status on receipt of hot-plug interrupt
5869  *
5870  * intel_dp_short_pulse -  handles short pulse interrupts
5871  * when full detection is not required.
5872  * Returns %true if short pulse is handled and full detection
5873  * is NOT required and %false otherwise.
5874  */
5875 static bool
5876 intel_dp_short_pulse(struct intel_dp *intel_dp)
5877 {
5878         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5879         u8 old_sink_count = intel_dp->sink_count;
5880         bool ret;
5881
5882         /*
5883          * Clearing compliance test variables to allow capturing
5884          * of values for next automated test request.
5885          */
5886         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5887
5888         /*
5889          * Now read the DPCD to see if it's actually running
5890          * If the current value of sink count doesn't match with
5891          * the value that was stored earlier or dpcd read failed
5892          * we need to do full detection
5893          */
5894         ret = intel_dp_get_dpcd(intel_dp);
5895
5896         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5897                 /* No need to proceed if we are going to do full detect */
5898                 return false;
5899         }
5900
5901         intel_dp_check_service_irq(intel_dp);
5902
5903         /* Handle CEC interrupts, if any */
5904         drm_dp_cec_irq(&intel_dp->aux);
5905
5906         /* defer to the hotplug work for link retraining if needed */
5907         if (intel_dp_needs_link_retrain(intel_dp))
5908                 return false;
5909
5910         intel_psr_short_pulse(intel_dp);
5911
5912         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5913                 drm_dbg_kms(&dev_priv->drm,
5914                             "Link Training Compliance Test requested\n");
5915                 /* Send a Hotplug Uevent to userspace to start modeset */
5916                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5917         }
5918
5919         return true;
5920 }
5921
5922 /* XXX this is probably wrong for multiple downstream ports */
5923 static enum drm_connector_status
5924 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5925 {
5926         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5927         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5928         u8 *dpcd = intel_dp->dpcd;
5929         u8 type;
5930
5931         if (WARN_ON(intel_dp_is_edp(intel_dp)))
5932                 return connector_status_connected;
5933
5934         if (lspcon->active)
5935                 lspcon_resume(lspcon);
5936
5937         if (!intel_dp_get_dpcd(intel_dp))
5938                 return connector_status_disconnected;
5939
5940         /* if there's no downstream port, we're done */
5941         if (!drm_dp_is_branch(dpcd))
5942                 return connector_status_connected;
5943
5944         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5945         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5946             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5947
5948                 return intel_dp->sink_count ?
5949                 connector_status_connected : connector_status_disconnected;
5950         }
5951
5952         if (intel_dp_can_mst(intel_dp))
5953                 return connector_status_connected;
5954
5955         /* If no HPD, poke DDC gently */
5956         if (drm_probe_ddc(&intel_dp->aux.ddc))
5957                 return connector_status_connected;
5958
5959         /* Well we tried, say unknown for unreliable port types */
5960         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5961                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5962                 if (type == DP_DS_PORT_TYPE_VGA ||
5963                     type == DP_DS_PORT_TYPE_NON_EDID)
5964                         return connector_status_unknown;
5965         } else {
5966                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5967                         DP_DWN_STRM_PORT_TYPE_MASK;
5968                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5969                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5970                         return connector_status_unknown;
5971         }
5972
5973         /* Anything else is out of spec, warn and ignore */
5974         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5975         return connector_status_disconnected;
5976 }
5977
5978 static enum drm_connector_status
5979 edp_detect(struct intel_dp *intel_dp)
5980 {
5981         return connector_status_connected;
5982 }
5983
5984 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5985 {
5986         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5987         u32 bit;
5988
5989         switch (encoder->hpd_pin) {
5990         case HPD_PORT_B:
5991                 bit = SDE_PORTB_HOTPLUG;
5992                 break;
5993         case HPD_PORT_C:
5994                 bit = SDE_PORTC_HOTPLUG;
5995                 break;
5996         case HPD_PORT_D:
5997                 bit = SDE_PORTD_HOTPLUG;
5998                 break;
5999         default:
6000                 MISSING_CASE(encoder->hpd_pin);
6001                 return false;
6002         }
6003
6004         return intel_de_read(dev_priv, SDEISR) & bit;
6005 }
6006
6007 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
6008 {
6009         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6010         u32 bit;
6011
6012         switch (encoder->hpd_pin) {
6013         case HPD_PORT_B:
6014                 bit = SDE_PORTB_HOTPLUG_CPT;
6015                 break;
6016         case HPD_PORT_C:
6017                 bit = SDE_PORTC_HOTPLUG_CPT;
6018                 break;
6019         case HPD_PORT_D:
6020                 bit = SDE_PORTD_HOTPLUG_CPT;
6021                 break;
6022         default:
6023                 MISSING_CASE(encoder->hpd_pin);
6024                 return false;
6025         }
6026
6027         return intel_de_read(dev_priv, SDEISR) & bit;
6028 }
6029
6030 static bool spt_digital_port_connected(struct intel_encoder *encoder)
6031 {
6032         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6033         u32 bit;
6034
6035         switch (encoder->hpd_pin) {
6036         case HPD_PORT_A:
6037                 bit = SDE_PORTA_HOTPLUG_SPT;
6038                 break;
6039         case HPD_PORT_E:
6040                 bit = SDE_PORTE_HOTPLUG_SPT;
6041                 break;
6042         default:
6043                 return cpt_digital_port_connected(encoder);
6044         }
6045
6046         return intel_de_read(dev_priv, SDEISR) & bit;
6047 }
6048
6049 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6050 {
6051         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6052         u32 bit;
6053
6054         switch (encoder->hpd_pin) {
6055         case HPD_PORT_B:
6056                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6057                 break;
6058         case HPD_PORT_C:
6059                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6060                 break;
6061         case HPD_PORT_D:
6062                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6063                 break;
6064         default:
6065                 MISSING_CASE(encoder->hpd_pin);
6066                 return false;
6067         }
6068
6069         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6070 }
6071
6072 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6073 {
6074         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6075         u32 bit;
6076
6077         switch (encoder->hpd_pin) {
6078         case HPD_PORT_B:
6079                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6080                 break;
6081         case HPD_PORT_C:
6082                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6083                 break;
6084         case HPD_PORT_D:
6085                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6086                 break;
6087         default:
6088                 MISSING_CASE(encoder->hpd_pin);
6089                 return false;
6090         }
6091
6092         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6093 }
6094
6095 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6096 {
6097         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6098
6099         if (encoder->hpd_pin == HPD_PORT_A)
6100                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
6101         else
6102                 return ibx_digital_port_connected(encoder);
6103 }
6104
6105 static bool snb_digital_port_connected(struct intel_encoder *encoder)
6106 {
6107         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6108
6109         if (encoder->hpd_pin == HPD_PORT_A)
6110                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
6111         else
6112                 return cpt_digital_port_connected(encoder);
6113 }
6114
6115 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
6116 {
6117         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6118
6119         if (encoder->hpd_pin == HPD_PORT_A)
6120                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB;
6121         else
6122                 return cpt_digital_port_connected(encoder);
6123 }
6124
6125 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
6126 {
6127         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6128
6129         if (encoder->hpd_pin == HPD_PORT_A)
6130                 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
6131         else
6132                 return cpt_digital_port_connected(encoder);
6133 }
6134
6135 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
6136 {
6137         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6138         u32 bit;
6139
6140         switch (encoder->hpd_pin) {
6141         case HPD_PORT_A:
6142                 bit = BXT_DE_PORT_HP_DDIA;
6143                 break;
6144         case HPD_PORT_B:
6145                 bit = BXT_DE_PORT_HP_DDIB;
6146                 break;
6147         case HPD_PORT_C:
6148                 bit = BXT_DE_PORT_HP_DDIC;
6149                 break;
6150         default:
6151                 MISSING_CASE(encoder->hpd_pin);
6152                 return false;
6153         }
6154
6155         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
6156 }
6157
6158 static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
6159                                       enum phy phy)
6160 {
6161         if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
6162                 return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
6163
6164         return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
6165 }
6166
6167 static bool icp_digital_port_connected(struct intel_encoder *encoder)
6168 {
6169         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6170         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6171         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
6172
6173         if (intel_phy_is_combo(dev_priv, phy))
6174                 return intel_combo_phy_connected(dev_priv, phy);
6175         else if (intel_phy_is_tc(dev_priv, phy))
6176                 return intel_tc_port_connected(dig_port);
6177         else
6178                 MISSING_CASE(encoder->hpd_pin);
6179
6180         return false;
6181 }
6182
6183 /*
6184  * intel_digital_port_connected - is the specified port connected?
6185  * @encoder: intel_encoder
6186  *
6187  * In cases where there's a connector physically connected but it can't be used
6188  * by our hardware we also return false, since the rest of the driver should
6189  * pretty much treat the port as disconnected. This is relevant for type-C
6190  * (starting on ICL) where there's ownership involved.
6191  *
6192  * Return %true if port is connected, %false otherwise.
6193  */
6194 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
6195 {
6196         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6197
6198         if (HAS_GMCH(dev_priv)) {
6199                 if (IS_GM45(dev_priv))
6200                         return gm45_digital_port_connected(encoder);
6201                 else
6202                         return g4x_digital_port_connected(encoder);
6203         }
6204
6205         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
6206                 return icp_digital_port_connected(encoder);
6207         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
6208                 return spt_digital_port_connected(encoder);
6209         else if (IS_GEN9_LP(dev_priv))
6210                 return bxt_digital_port_connected(encoder);
6211         else if (IS_GEN(dev_priv, 8))
6212                 return bdw_digital_port_connected(encoder);
6213         else if (IS_GEN(dev_priv, 7))
6214                 return ivb_digital_port_connected(encoder);
6215         else if (IS_GEN(dev_priv, 6))
6216                 return snb_digital_port_connected(encoder);
6217         else if (IS_GEN(dev_priv, 5))
6218                 return ilk_digital_port_connected(encoder);
6219
6220         MISSING_CASE(INTEL_GEN(dev_priv));
6221         return false;
6222 }
6223
6224 bool intel_digital_port_connected(struct intel_encoder *encoder)
6225 {
6226         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6227         bool is_connected = false;
6228         intel_wakeref_t wakeref;
6229
6230         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6231                 is_connected = __intel_digital_port_connected(encoder);
6232
6233         return is_connected;
6234 }
6235
6236 static struct edid *
6237 intel_dp_get_edid(struct intel_dp *intel_dp)
6238 {
6239         struct intel_connector *intel_connector = intel_dp->attached_connector;
6240
6241         /* use cached edid if we have one */
6242         if (intel_connector->edid) {
6243                 /* invalid edid */
6244                 if (IS_ERR(intel_connector->edid))
6245                         return NULL;
6246
6247                 return drm_edid_duplicate(intel_connector->edid);
6248         } else
6249                 return drm_get_edid(&intel_connector->base,
6250                                     &intel_dp->aux.ddc);
6251 }
6252
6253 static void
6254 intel_dp_set_edid(struct intel_dp *intel_dp)
6255 {
6256         struct intel_connector *intel_connector = intel_dp->attached_connector;
6257         struct edid *edid;
6258
6259         intel_dp_unset_edid(intel_dp);
6260         edid = intel_dp_get_edid(intel_dp);
6261         intel_connector->detect_edid = edid;
6262
6263         intel_dp->has_audio = drm_detect_monitor_audio(edid);
6264         drm_dp_cec_set_edid(&intel_dp->aux, edid);
6265         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6266 }
6267
6268 static void
6269 intel_dp_unset_edid(struct intel_dp *intel_dp)
6270 {
6271         struct intel_connector *intel_connector = intel_dp->attached_connector;
6272
6273         drm_dp_cec_unset_edid(&intel_dp->aux);
6274         kfree(intel_connector->detect_edid);
6275         intel_connector->detect_edid = NULL;
6276
6277         intel_dp->has_audio = false;
6278         intel_dp->edid_quirks = 0;
6279 }
6280
6281 static int
6282 intel_dp_detect(struct drm_connector *connector,
6283                 struct drm_modeset_acquire_ctx *ctx,
6284                 bool force)
6285 {
6286         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6287         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6288         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6289         struct intel_encoder *encoder = &dig_port->base;
6290         enum drm_connector_status status;
6291
6292         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6293                     connector->base.id, connector->name);
6294         drm_WARN_ON(&dev_priv->drm,
6295                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6296
6297         /* Can't disconnect eDP */
6298         if (intel_dp_is_edp(intel_dp))
6299                 status = edp_detect(intel_dp);
6300         else if (intel_digital_port_connected(encoder))
6301                 status = intel_dp_detect_dpcd(intel_dp);
6302         else
6303                 status = connector_status_disconnected;
6304
6305         if (status == connector_status_disconnected) {
6306                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6307                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6308
6309                 if (intel_dp->is_mst) {
6310                         drm_dbg_kms(&dev_priv->drm,
6311                                     "MST device may have disappeared %d vs %d\n",
6312                                     intel_dp->is_mst,
6313                                     intel_dp->mst_mgr.mst_state);
6314                         intel_dp->is_mst = false;
6315                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6316                                                         intel_dp->is_mst);
6317                 }
6318
6319                 goto out;
6320         }
6321
6322         if (intel_dp->reset_link_params) {
6323                 /* Initial max link lane count */
6324                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6325
6326                 /* Initial max link rate */
6327                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6328
6329                 intel_dp->reset_link_params = false;
6330         }
6331
6332         intel_dp_print_rates(intel_dp);
6333
6334         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6335         if (INTEL_GEN(dev_priv) >= 11)
6336                 intel_dp_get_dsc_sink_cap(intel_dp);
6337
6338         intel_dp_configure_mst(intel_dp);
6339
6340         if (intel_dp->is_mst) {
6341                 /*
6342                  * If we are in MST mode then this connector
6343                  * won't appear connected or have anything
6344                  * with EDID on it
6345                  */
6346                 status = connector_status_disconnected;
6347                 goto out;
6348         }
6349
6350         /*
6351          * Some external monitors do not signal loss of link synchronization
6352          * with an IRQ_HPD, so force a link status check.
6353          */
6354         if (!intel_dp_is_edp(intel_dp)) {
6355                 int ret;
6356
6357                 ret = intel_dp_retrain_link(encoder, ctx);
6358                 if (ret)
6359                         return ret;
6360         }
6361
6362         /*
6363          * Clearing NACK and defer counts to get their exact values
6364          * while reading EDID which are required by Compliance tests
6365          * 4.2.2.4 and 4.2.2.5
6366          */
6367         intel_dp->aux.i2c_nack_count = 0;
6368         intel_dp->aux.i2c_defer_count = 0;
6369
6370         intel_dp_set_edid(intel_dp);
6371         if (intel_dp_is_edp(intel_dp) ||
6372             to_intel_connector(connector)->detect_edid)
6373                 status = connector_status_connected;
6374
6375         intel_dp_check_service_irq(intel_dp);
6376
6377 out:
6378         if (status != connector_status_connected && !intel_dp->is_mst)
6379                 intel_dp_unset_edid(intel_dp);
6380
6381         /*
6382          * Make sure the refs for power wells enabled during detect are
6383          * dropped to avoid a new detect cycle triggered by HPD polling.
6384          */
6385         intel_display_power_flush_work(dev_priv);
6386
6387         return status;
6388 }
6389
6390 static void
6391 intel_dp_force(struct drm_connector *connector)
6392 {
6393         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6394         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6395         struct intel_encoder *intel_encoder = &dig_port->base;
6396         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6397         enum intel_display_power_domain aux_domain =
6398                 intel_aux_power_domain(dig_port);
6399         intel_wakeref_t wakeref;
6400
6401         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6402                     connector->base.id, connector->name);
6403         intel_dp_unset_edid(intel_dp);
6404
6405         if (connector->status != connector_status_connected)
6406                 return;
6407
6408         wakeref = intel_display_power_get(dev_priv, aux_domain);
6409
6410         intel_dp_set_edid(intel_dp);
6411
6412         intel_display_power_put(dev_priv, aux_domain, wakeref);
6413 }
6414
6415 static int intel_dp_get_modes(struct drm_connector *connector)
6416 {
6417         struct intel_connector *intel_connector = to_intel_connector(connector);
6418         struct edid *edid;
6419
6420         edid = intel_connector->detect_edid;
6421         if (edid) {
6422                 int ret = intel_connector_update_modes(connector, edid);
6423                 if (ret)
6424                         return ret;
6425         }
6426
6427         /* if eDP has no EDID, fall back to fixed mode */
6428         if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
6429             intel_connector->panel.fixed_mode) {
6430                 struct drm_display_mode *mode;
6431
6432                 mode = drm_mode_duplicate(connector->dev,
6433                                           intel_connector->panel.fixed_mode);
6434                 if (mode) {
6435                         drm_mode_probed_add(connector, mode);
6436                         return 1;
6437                 }
6438         }
6439
6440         return 0;
6441 }
6442
6443 static int
6444 intel_dp_connector_register(struct drm_connector *connector)
6445 {
6446         struct drm_i915_private *i915 = to_i915(connector->dev);
6447         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6448         int ret;
6449
6450         ret = intel_connector_register(connector);
6451         if (ret)
6452                 return ret;
6453
6454         intel_connector_debugfs_add(connector);
6455
6456         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6457                     intel_dp->aux.name, connector->kdev->kobj.name);
6458
6459         intel_dp->aux.dev = connector->kdev;
6460         ret = drm_dp_aux_register(&intel_dp->aux);
6461         if (!ret)
6462                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6463         return ret;
6464 }
6465
6466 static void
6467 intel_dp_connector_unregister(struct drm_connector *connector)
6468 {
6469         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6470
6471         drm_dp_cec_unregister_connector(&intel_dp->aux);
6472         drm_dp_aux_unregister(&intel_dp->aux);
6473         intel_connector_unregister(connector);
6474 }
6475
6476 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6477 {
6478         struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6479         struct intel_dp *intel_dp = &intel_dig_port->dp;
6480
6481         intel_dp_mst_encoder_cleanup(intel_dig_port);
6482         if (intel_dp_is_edp(intel_dp)) {
6483                 intel_wakeref_t wakeref;
6484
6485                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6486                 /*
6487                  * vdd might still be enabled do to the delayed vdd off.
6488                  * Make sure vdd is actually turned off here.
6489                  */
6490                 with_pps_lock(intel_dp, wakeref)
6491                         edp_panel_vdd_off_sync(intel_dp);
6492
6493                 if (intel_dp->edp_notifier.notifier_call) {
6494                         unregister_reboot_notifier(&intel_dp->edp_notifier);
6495                         intel_dp->edp_notifier.notifier_call = NULL;
6496                 }
6497         }
6498
6499         intel_dp_aux_fini(intel_dp);
6500 }
6501
6502 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6503 {
6504         intel_dp_encoder_flush_work(encoder);
6505
6506         drm_encoder_cleanup(encoder);
6507         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6508 }
6509
6510 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6511 {
6512         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6513         intel_wakeref_t wakeref;
6514
6515         if (!intel_dp_is_edp(intel_dp))
6516                 return;
6517
6518         /*
6519          * vdd might still be enabled do to the delayed vdd off.
6520          * Make sure vdd is actually turned off here.
6521          */
6522         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6523         with_pps_lock(intel_dp, wakeref)
6524                 edp_panel_vdd_off_sync(intel_dp);
6525 }
6526
6527 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
6528 {
6529         long ret;
6530
6531 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
6532         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
6533                                                msecs_to_jiffies(timeout));
6534
6535         if (!ret)
6536                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
6537 }
6538
6539 static
6540 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
6541                                 u8 *an)
6542 {
6543         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6544         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base));
6545         static const struct drm_dp_aux_msg msg = {
6546                 .request = DP_AUX_NATIVE_WRITE,
6547                 .address = DP_AUX_HDCP_AKSV,
6548                 .size = DRM_HDCP_KSV_LEN,
6549         };
6550         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
6551         ssize_t dpcd_ret;
6552         int ret;
6553
6554         /* Output An first, that's easy */
6555         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
6556                                      an, DRM_HDCP_AN_LEN);
6557         if (dpcd_ret != DRM_HDCP_AN_LEN) {
6558                 drm_dbg_kms(&i915->drm,
6559                             "Failed to write An over DP/AUX (%zd)\n",
6560                             dpcd_ret);
6561                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
6562         }
6563
6564         /*
6565          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
6566          * order to get it on the wire, we need to create the AUX header as if
6567          * we were writing the data, and then tickle the hardware to output the
6568          * data once the header is sent out.
6569          */
6570         intel_dp_aux_header(txbuf, &msg);
6571
6572         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
6573                                 rxbuf, sizeof(rxbuf),
6574                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
6575         if (ret < 0) {
6576                 drm_dbg_kms(&i915->drm,
6577                             "Write Aksv over DP/AUX failed (%d)\n", ret);
6578                 return ret;
6579         } else if (ret == 0) {
6580                 drm_dbg_kms(&i915->drm, "Aksv write over DP/AUX was empty\n");
6581                 return -EIO;
6582         }
6583
6584         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
6585         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
6586                 drm_dbg_kms(&i915->drm,
6587                             "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
6588                             reply);
6589                 return -EIO;
6590         }
6591         return 0;
6592 }
6593
6594 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
6595                                    u8 *bksv)
6596 {
6597         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6598         ssize_t ret;
6599
6600         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
6601                                DRM_HDCP_KSV_LEN);
6602         if (ret != DRM_HDCP_KSV_LEN) {
6603                 drm_dbg_kms(&i915->drm,
6604                             "Read Bksv from DP/AUX failed (%zd)\n", ret);
6605                 return ret >= 0 ? -EIO : ret;
6606         }
6607         return 0;
6608 }
6609
6610 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
6611                                       u8 *bstatus)
6612 {
6613         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6614         ssize_t ret;
6615
6616         /*
6617          * For some reason the HDMI and DP HDCP specs call this register
6618          * definition by different names. In the HDMI spec, it's called BSTATUS,
6619          * but in DP it's called BINFO.
6620          */
6621         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
6622                                bstatus, DRM_HDCP_BSTATUS_LEN);
6623         if (ret != DRM_HDCP_BSTATUS_LEN) {
6624                 drm_dbg_kms(&i915->drm,
6625                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6626                 return ret >= 0 ? -EIO : ret;
6627         }
6628         return 0;
6629 }
6630
6631 static
6632 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
6633                              u8 *bcaps)
6634 {
6635         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6636         ssize_t ret;
6637
6638         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
6639                                bcaps, 1);
6640         if (ret != 1) {
6641                 drm_dbg_kms(&i915->drm,
6642                             "Read bcaps from DP/AUX failed (%zd)\n", ret);
6643                 return ret >= 0 ? -EIO : ret;
6644         }
6645
6646         return 0;
6647 }
6648
6649 static
6650 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
6651                                    bool *repeater_present)
6652 {
6653         ssize_t ret;
6654         u8 bcaps;
6655
6656         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6657         if (ret)
6658                 return ret;
6659
6660         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
6661         return 0;
6662 }
6663
6664 static
6665 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
6666                                 u8 *ri_prime)
6667 {
6668         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6669         ssize_t ret;
6670
6671         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
6672                                ri_prime, DRM_HDCP_RI_LEN);
6673         if (ret != DRM_HDCP_RI_LEN) {
6674                 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
6675                             ret);
6676                 return ret >= 0 ? -EIO : ret;
6677         }
6678         return 0;
6679 }
6680
6681 static
6682 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
6683                                  bool *ksv_ready)
6684 {
6685         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6686         ssize_t ret;
6687         u8 bstatus;
6688
6689         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6690                                &bstatus, 1);
6691         if (ret != 1) {
6692                 drm_dbg_kms(&i915->drm,
6693                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6694                 return ret >= 0 ? -EIO : ret;
6695         }
6696         *ksv_ready = bstatus & DP_BSTATUS_READY;
6697         return 0;
6698 }
6699
6700 static
6701 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6702                                 int num_downstream, u8 *ksv_fifo)
6703 {
6704         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6705         ssize_t ret;
6706         int i;
6707
6708         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6709         for (i = 0; i < num_downstream; i += 3) {
6710                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6711                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6712                                        DP_AUX_HDCP_KSV_FIFO,
6713                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
6714                                        len);
6715                 if (ret != len) {
6716                         drm_dbg_kms(&i915->drm,
6717                                     "Read ksv[%d] from DP/AUX failed (%zd)\n",
6718                                     i, ret);
6719                         return ret >= 0 ? -EIO : ret;
6720                 }
6721         }
6722         return 0;
6723 }
6724
6725 static
6726 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6727                                     int i, u32 *part)
6728 {
6729         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6730         ssize_t ret;
6731
6732         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6733                 return -EINVAL;
6734
6735         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6736                                DP_AUX_HDCP_V_PRIME(i), part,
6737                                DRM_HDCP_V_PRIME_PART_LEN);
6738         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6739                 drm_dbg_kms(&i915->drm,
6740                             "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6741                 return ret >= 0 ? -EIO : ret;
6742         }
6743         return 0;
6744 }
6745
6746 static
6747 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6748                                     bool enable)
6749 {
6750         /* Not used for single stream DisplayPort setups */
6751         return 0;
6752 }
6753
6754 static
6755 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6756 {
6757         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6758         ssize_t ret;
6759         u8 bstatus;
6760
6761         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6762                                &bstatus, 1);
6763         if (ret != 1) {
6764                 drm_dbg_kms(&i915->drm,
6765                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6766                 return false;
6767         }
6768
6769         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6770 }
6771
6772 static
6773 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6774                           bool *hdcp_capable)
6775 {
6776         ssize_t ret;
6777         u8 bcaps;
6778
6779         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6780         if (ret)
6781                 return ret;
6782
6783         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6784         return 0;
6785 }
6786
6787 struct hdcp2_dp_errata_stream_type {
6788         u8      msg_id;
6789         u8      stream_type;
6790 } __packed;
6791
6792 struct hdcp2_dp_msg_data {
6793         u8 msg_id;
6794         u32 offset;
6795         bool msg_detectable;
6796         u32 timeout;
6797         u32 timeout2; /* Added for non_paired situation */
6798 };
6799
6800 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6801         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6802         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6803           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6804         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6805           false, 0, 0 },
6806         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6807           false, 0, 0 },
6808         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6809           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6810           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6811         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6812           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6813           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6814         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6815         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6816           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6817         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6818           0, 0 },
6819         { HDCP_2_2_REP_SEND_RECVID_LIST,
6820           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6821           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6822         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6823           0, 0 },
6824         { HDCP_2_2_REP_STREAM_MANAGE,
6825           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6826           0, 0 },
6827         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6828           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6829 /* local define to shovel this through the write_2_2 interface */
6830 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
6831         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6832           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6833           0, 0 },
6834 };
6835
6836 static inline
6837 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6838                                   u8 *rx_status)
6839 {
6840         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6841         ssize_t ret;
6842
6843         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6844                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6845                                HDCP_2_2_DP_RXSTATUS_LEN);
6846         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6847                 drm_dbg_kms(&i915->drm,
6848                             "Read bstatus from DP/AUX failed (%zd)\n", ret);
6849                 return ret >= 0 ? -EIO : ret;
6850         }
6851
6852         return 0;
6853 }
6854
6855 static
6856 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6857                                   u8 msg_id, bool *msg_ready)
6858 {
6859         u8 rx_status;
6860         int ret;
6861
6862         *msg_ready = false;
6863         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6864         if (ret < 0)
6865                 return ret;
6866
6867         switch (msg_id) {
6868         case HDCP_2_2_AKE_SEND_HPRIME:
6869                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6870                         *msg_ready = true;
6871                 break;
6872         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6873                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6874                         *msg_ready = true;
6875                 break;
6876         case HDCP_2_2_REP_SEND_RECVID_LIST:
6877                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6878                         *msg_ready = true;
6879                 break;
6880         default:
6881                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6882                 return -EINVAL;
6883         }
6884
6885         return 0;
6886 }
6887
6888 static ssize_t
6889 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6890                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6891 {
6892         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
6893         struct intel_dp *dp = &intel_dig_port->dp;
6894         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6895         u8 msg_id = hdcp2_msg_data->msg_id;
6896         int ret, timeout;
6897         bool msg_ready = false;
6898
6899         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6900                 timeout = hdcp2_msg_data->timeout2;
6901         else
6902                 timeout = hdcp2_msg_data->timeout;
6903
6904         /*
6905          * There is no way to detect the CERT, LPRIME and STREAM_READY
6906          * availability. So Wait for timeout and read the msg.
6907          */
6908         if (!hdcp2_msg_data->msg_detectable) {
6909                 mdelay(timeout);
6910                 ret = 0;
6911         } else {
6912                 /*
6913                  * As we want to check the msg availability at timeout, Ignoring
6914                  * the timeout at wait for CP_IRQ.
6915                  */
6916                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6917                 ret = hdcp2_detect_msg_availability(intel_dig_port,
6918                                                     msg_id, &msg_ready);
6919                 if (!msg_ready)
6920                         ret = -ETIMEDOUT;
6921         }
6922
6923         if (ret)
6924                 drm_dbg_kms(&i915->drm,
6925                             "msg_id %d, ret %d, timeout(mSec): %d\n",
6926                             hdcp2_msg_data->msg_id, ret, timeout);
6927
6928         return ret;
6929 }
6930
6931 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6932 {
6933         int i;
6934
6935         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6936                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6937                         return &hdcp2_dp_msg_data[i];
6938
6939         return NULL;
6940 }
6941
6942 static
6943 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6944                              void *buf, size_t size)
6945 {
6946         struct intel_dp *dp = &intel_dig_port->dp;
6947         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6948         unsigned int offset;
6949         u8 *byte = buf;
6950         ssize_t ret, bytes_to_write, len;
6951         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6952
6953         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6954         if (!hdcp2_msg_data)
6955                 return -EINVAL;
6956
6957         offset = hdcp2_msg_data->offset;
6958
6959         /* No msg_id in DP HDCP2.2 msgs */
6960         bytes_to_write = size - 1;
6961         byte++;
6962
6963         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6964
6965         while (bytes_to_write) {
6966                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6967                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6968
6969                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6970                                         offset, (void *)byte, len);
6971                 if (ret < 0)
6972                         return ret;
6973
6974                 bytes_to_write -= ret;
6975                 byte += ret;
6976                 offset += ret;
6977         }
6978
6979         return size;
6980 }
6981
6982 static
6983 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6984 {
6985         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6986         u32 dev_cnt;
6987         ssize_t ret;
6988
6989         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6990                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6991                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6992         if (ret != HDCP_2_2_RXINFO_LEN)
6993                 return ret >= 0 ? -EIO : ret;
6994
6995         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6996                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6997
6998         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6999                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
7000
7001         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
7002                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
7003                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
7004
7005         return ret;
7006 }
7007
7008 static
7009 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
7010                             u8 msg_id, void *buf, size_t size)
7011 {
7012         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7013         unsigned int offset;
7014         u8 *byte = buf;
7015         ssize_t ret, bytes_to_recv, len;
7016         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
7017
7018         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
7019         if (!hdcp2_msg_data)
7020                 return -EINVAL;
7021         offset = hdcp2_msg_data->offset;
7022
7023         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
7024         if (ret < 0)
7025                 return ret;
7026
7027         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
7028                 ret = get_receiver_id_list_size(intel_dig_port);
7029                 if (ret < 0)
7030                         return ret;
7031
7032                 size = ret;
7033         }
7034         bytes_to_recv = size - 1;
7035
7036         /* DP adaptation msgs has no msg_id */
7037         byte++;
7038
7039         while (bytes_to_recv) {
7040                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
7041                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
7042
7043                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
7044                                        (void *)byte, len);
7045                 if (ret < 0) {
7046                         drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
7047                                     msg_id, ret);
7048                         return ret;
7049                 }
7050
7051                 bytes_to_recv -= ret;
7052                 byte += ret;
7053                 offset += ret;
7054         }
7055         byte = buf;
7056         *byte = msg_id;
7057
7058         return size;
7059 }
7060
7061 static
7062 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
7063                                       bool is_repeater, u8 content_type)
7064 {
7065         int ret;
7066         struct hdcp2_dp_errata_stream_type stream_type_msg;
7067
7068         if (is_repeater)
7069                 return 0;
7070
7071         /*
7072          * Errata for DP: As Stream type is used for encryption, Receiver
7073          * should be communicated with stream type for the decryption of the
7074          * content.
7075          * Repeater will be communicated with stream type as a part of it's
7076          * auth later in time.
7077          */
7078         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
7079         stream_type_msg.stream_type = content_type;
7080
7081         ret =  intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
7082                                         sizeof(stream_type_msg));
7083
7084         return ret < 0 ? ret : 0;
7085
7086 }
7087
7088 static
7089 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
7090 {
7091         u8 rx_status;
7092         int ret;
7093
7094         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
7095         if (ret)
7096                 return ret;
7097
7098         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
7099                 ret = HDCP_REAUTH_REQUEST;
7100         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
7101                 ret = HDCP_LINK_INTEGRITY_FAILURE;
7102         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
7103                 ret = HDCP_TOPOLOGY_CHANGE;
7104
7105         return ret;
7106 }
7107
7108 static
7109 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
7110                            bool *capable)
7111 {
7112         u8 rx_caps[3];
7113         int ret;
7114
7115         *capable = false;
7116         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
7117                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
7118                                rx_caps, HDCP_2_2_RXCAPS_LEN);
7119         if (ret != HDCP_2_2_RXCAPS_LEN)
7120                 return ret >= 0 ? -EIO : ret;
7121
7122         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
7123             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
7124                 *capable = true;
7125
7126         return 0;
7127 }
7128
7129 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
7130         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
7131         .read_bksv = intel_dp_hdcp_read_bksv,
7132         .read_bstatus = intel_dp_hdcp_read_bstatus,
7133         .repeater_present = intel_dp_hdcp_repeater_present,
7134         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
7135         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
7136         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
7137         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
7138         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
7139         .check_link = intel_dp_hdcp_check_link,
7140         .hdcp_capable = intel_dp_hdcp_capable,
7141         .write_2_2_msg = intel_dp_hdcp2_write_msg,
7142         .read_2_2_msg = intel_dp_hdcp2_read_msg,
7143         .config_stream_type = intel_dp_hdcp2_config_stream_type,
7144         .check_2_2_link = intel_dp_hdcp2_check_link,
7145         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
7146         .protocol = HDCP_PROTOCOL_DP,
7147 };
7148
7149 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
7150 {
7151         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7152         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7153
7154         lockdep_assert_held(&dev_priv->pps_mutex);
7155
7156         if (!edp_have_panel_vdd(intel_dp))
7157                 return;
7158
7159         /*
7160          * The VDD bit needs a power domain reference, so if the bit is
7161          * already enabled when we boot or resume, grab this reference and
7162          * schedule a vdd off, so we don't hold on to the reference
7163          * indefinitely.
7164          */
7165         drm_dbg_kms(&dev_priv->drm,
7166                     "VDD left on by BIOS, adjusting state tracking\n");
7167         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
7168
7169         edp_panel_vdd_schedule_off(intel_dp);
7170 }
7171
7172 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7173 {
7174         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7175         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7176         enum pipe pipe;
7177
7178         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7179                                   encoder->port, &pipe))
7180                 return pipe;
7181
7182         return INVALID_PIPE;
7183 }
7184
7185 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7186 {
7187         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7188         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7189         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
7190         intel_wakeref_t wakeref;
7191
7192         if (!HAS_DDI(dev_priv))
7193                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7194
7195         if (lspcon->active)
7196                 lspcon_resume(lspcon);
7197
7198         intel_dp->reset_link_params = true;
7199
7200         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7201             !intel_dp_is_edp(intel_dp))
7202                 return;
7203
7204         with_pps_lock(intel_dp, wakeref) {
7205                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7206                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7207
7208                 if (intel_dp_is_edp(intel_dp)) {
7209                         /*
7210                          * Reinit the power sequencer, in case BIOS did
7211                          * something nasty with it.
7212                          */
7213                         intel_dp_pps_init(intel_dp);
7214                         intel_edp_panel_vdd_sanitize(intel_dp);
7215                 }
7216         }
7217 }
7218
7219 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7220                                     int tile_group_id)
7221 {
7222         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7223         struct drm_connector_list_iter conn_iter;
7224         struct drm_connector *connector;
7225         int ret = 0;
7226
7227         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7228         drm_for_each_connector_iter(connector, &conn_iter) {
7229                 struct drm_connector_state *conn_state;
7230                 struct intel_crtc_state *crtc_state;
7231                 struct intel_crtc *crtc;
7232
7233                 if (!connector->has_tile ||
7234                     connector->tile_group->id != tile_group_id)
7235                         continue;
7236
7237                 conn_state = drm_atomic_get_connector_state(&state->base,
7238                                                             connector);
7239                 if (IS_ERR(conn_state)) {
7240                         ret = PTR_ERR(conn_state);
7241                         break;
7242                 }
7243
7244                 crtc = to_intel_crtc(conn_state->crtc);
7245
7246                 if (!crtc)
7247                         continue;
7248
7249                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7250                 crtc_state->uapi.mode_changed = true;
7251
7252                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7253                 if (ret)
7254                         break;
7255         }
7256         drm_connector_list_iter_end(&conn_iter);
7257
7258         return ret;
7259 }
7260
7261 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7262 {
7263         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7264         struct intel_crtc *crtc;
7265
7266         if (transcoders == 0)
7267                 return 0;
7268
7269         for_each_intel_crtc(&dev_priv->drm, crtc) {
7270                 struct intel_crtc_state *crtc_state;
7271                 int ret;
7272
7273                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7274                 if (IS_ERR(crtc_state))
7275                         return PTR_ERR(crtc_state);
7276
7277                 if (!crtc_state->hw.enable)
7278                         continue;
7279
7280                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7281                         continue;
7282
7283                 crtc_state->uapi.mode_changed = true;
7284
7285                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7286                 if (ret)
7287                         return ret;
7288
7289                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7290                 if (ret)
7291                         return ret;
7292
7293                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7294         }
7295
7296         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7297
7298         return 0;
7299 }
7300
7301 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7302                                       struct drm_connector *connector)
7303 {
7304         const struct drm_connector_state *old_conn_state =
7305                 drm_atomic_get_old_connector_state(&state->base, connector);
7306         const struct intel_crtc_state *old_crtc_state;
7307         struct intel_crtc *crtc;
7308         u8 transcoders;
7309
7310         crtc = to_intel_crtc(old_conn_state->crtc);
7311         if (!crtc)
7312                 return 0;
7313
7314         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7315
7316         if (!old_crtc_state->hw.active)
7317                 return 0;
7318
7319         transcoders = old_crtc_state->sync_mode_slaves_mask;
7320         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7321                 transcoders |= BIT(old_crtc_state->master_transcoder);
7322
7323         return intel_modeset_affected_transcoders(state,
7324                                                   transcoders);
7325 }
7326
7327 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7328                                            struct drm_atomic_state *_state)
7329 {
7330         struct drm_i915_private *dev_priv = to_i915(conn->dev);
7331         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7332         int ret;
7333
7334         ret = intel_digital_connector_atomic_check(conn, &state->base);
7335         if (ret)
7336                 return ret;
7337
7338         /*
7339          * We don't enable port sync on BDW due to missing w/as and
7340          * due to not having adjusted the modeset sequence appropriately.
7341          */
7342         if (INTEL_GEN(dev_priv) < 9)
7343                 return 0;
7344
7345         if (!intel_connector_needs_modeset(state, conn))
7346                 return 0;
7347
7348         if (conn->has_tile) {
7349                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7350                 if (ret)
7351                         return ret;
7352         }
7353
7354         return intel_modeset_synced_crtcs(state, conn);
7355 }
7356
7357 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7358         .force = intel_dp_force,
7359         .fill_modes = drm_helper_probe_single_connector_modes,
7360         .atomic_get_property = intel_digital_connector_atomic_get_property,
7361         .atomic_set_property = intel_digital_connector_atomic_set_property,
7362         .late_register = intel_dp_connector_register,
7363         .early_unregister = intel_dp_connector_unregister,
7364         .destroy = intel_connector_destroy,
7365         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7366         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7367 };
7368
7369 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7370         .detect_ctx = intel_dp_detect,
7371         .get_modes = intel_dp_get_modes,
7372         .mode_valid = intel_dp_mode_valid,
7373         .atomic_check = intel_dp_connector_atomic_check,
7374 };
7375
7376 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7377         .reset = intel_dp_encoder_reset,
7378         .destroy = intel_dp_encoder_destroy,
7379 };
7380
7381 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7382 {
7383         intel_wakeref_t wakeref;
7384         bool have_power = false;
7385
7386         with_pps_lock(intel_dp, wakeref) {
7387                 have_power = edp_have_panel_power(intel_dp) &&
7388                                                   edp_have_panel_vdd(intel_dp);
7389         }
7390
7391         return have_power;
7392 }
7393
7394 enum irqreturn
7395 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
7396 {
7397         struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
7398         struct intel_dp *intel_dp = &intel_dig_port->dp;
7399
7400         if (intel_dig_port->base.type == INTEL_OUTPUT_EDP &&
7401             (long_hpd || !intel_edp_have_power(intel_dp))) {
7402                 /*
7403                  * vdd off can generate a long/short pulse on eDP which
7404                  * would require vdd on to handle it, and thus we
7405                  * would end up in an endless cycle of
7406                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7407                  */
7408                 drm_dbg_kms(&i915->drm,
7409                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7410                             long_hpd ? "long" : "short",
7411                             intel_dig_port->base.base.base.id,
7412                             intel_dig_port->base.base.name);
7413                 return IRQ_HANDLED;
7414         }
7415
7416         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7417                     intel_dig_port->base.base.base.id,
7418                     intel_dig_port->base.base.name,
7419                     long_hpd ? "long" : "short");
7420
7421         if (long_hpd) {
7422                 intel_dp->reset_link_params = true;
7423                 return IRQ_NONE;
7424         }
7425
7426         if (intel_dp->is_mst) {
7427                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
7428                         /*
7429                          * If we were in MST mode, and device is not
7430                          * there, get out of MST mode
7431                          */
7432                         drm_dbg_kms(&i915->drm,
7433                                     "MST device may have disappeared %d vs %d\n",
7434                                     intel_dp->is_mst,
7435                                     intel_dp->mst_mgr.mst_state);
7436                         intel_dp->is_mst = false;
7437                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7438                                                         intel_dp->is_mst);
7439
7440                         return IRQ_NONE;
7441                 }
7442         }
7443
7444         if (!intel_dp->is_mst) {
7445                 bool handled;
7446
7447                 handled = intel_dp_short_pulse(intel_dp);
7448
7449                 if (!handled)
7450                         return IRQ_NONE;
7451         }
7452
7453         return IRQ_HANDLED;
7454 }
7455
7456 /* check the VBT to see whether the eDP is on another port */
7457 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7458 {
7459         /*
7460          * eDP not supported on g4x. so bail out early just
7461          * for a bit extra safety in case the VBT is bonkers.
7462          */
7463         if (INTEL_GEN(dev_priv) < 5)
7464                 return false;
7465
7466         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7467                 return true;
7468
7469         return intel_bios_is_port_edp(dev_priv, port);
7470 }
7471
7472 static void
7473 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7474 {
7475         struct drm_i915_private *dev_priv = to_i915(connector->dev);
7476         enum port port = dp_to_dig_port(intel_dp)->base.port;
7477
7478         if (!IS_G4X(dev_priv) && port != PORT_A)
7479                 intel_attach_force_audio_property(connector);
7480
7481         intel_attach_broadcast_rgb_property(connector);
7482         if (HAS_GMCH(dev_priv))
7483                 drm_connector_attach_max_bpc_property(connector, 6, 10);
7484         else if (INTEL_GEN(dev_priv) >= 5)
7485                 drm_connector_attach_max_bpc_property(connector, 6, 12);
7486
7487         intel_attach_colorspace_property(connector);
7488
7489         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7490                 drm_object_attach_property(&connector->base,
7491                                            connector->dev->mode_config.hdr_output_metadata_property,
7492                                            0);
7493
7494         if (intel_dp_is_edp(intel_dp)) {
7495                 u32 allowed_scalers;
7496
7497                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7498                 if (!HAS_GMCH(dev_priv))
7499                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7500
7501                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7502
7503                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7504
7505         }
7506 }
7507
7508 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7509 {
7510         intel_dp->panel_power_off_time = ktime_get_boottime();
7511         intel_dp->last_power_on = jiffies;
7512         intel_dp->last_backlight_off = jiffies;
7513 }
7514
7515 static void
7516 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7517 {
7518         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7519         u32 pp_on, pp_off, pp_ctl;
7520         struct pps_registers regs;
7521
7522         intel_pps_get_registers(intel_dp, &regs);
7523
7524         pp_ctl = ilk_get_pp_control(intel_dp);
7525
7526         /* Ensure PPS is unlocked */
7527         if (!HAS_DDI(dev_priv))
7528                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7529
7530         pp_on = intel_de_read(dev_priv, regs.pp_on);
7531         pp_off = intel_de_read(dev_priv, regs.pp_off);
7532
7533         /* Pull timing values out of registers */
7534         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7535         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7536         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7537         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7538
7539         if (i915_mmio_reg_valid(regs.pp_div)) {
7540                 u32 pp_div;
7541
7542                 pp_div = intel_de_read(dev_priv, regs.pp_div);
7543
7544                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7545         } else {
7546                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7547         }
7548 }
7549
7550 static void
7551 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7552 {
7553         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7554                       state_name,
7555                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7556 }
7557
7558 static void
7559 intel_pps_verify_state(struct intel_dp *intel_dp)
7560 {
7561         struct edp_power_seq hw;
7562         struct edp_power_seq *sw = &intel_dp->pps_delays;
7563
7564         intel_pps_readout_hw_state(intel_dp, &hw);
7565
7566         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7567             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7568                 DRM_ERROR("PPS state mismatch\n");
7569                 intel_pps_dump_state("sw", sw);
7570                 intel_pps_dump_state("hw", &hw);
7571         }
7572 }
7573
7574 static void
7575 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7576 {
7577         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7578         struct edp_power_seq cur, vbt, spec,
7579                 *final = &intel_dp->pps_delays;
7580
7581         lockdep_assert_held(&dev_priv->pps_mutex);
7582
7583         /* already initialized? */
7584         if (final->t11_t12 != 0)
7585                 return;
7586
7587         intel_pps_readout_hw_state(intel_dp, &cur);
7588
7589         intel_pps_dump_state("cur", &cur);
7590
7591         vbt = dev_priv->vbt.edp.pps;
7592         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7593          * of 500ms appears to be too short. Ocassionally the panel
7594          * just fails to power back on. Increasing the delay to 800ms
7595          * seems sufficient to avoid this problem.
7596          */
7597         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7598                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7599                 drm_dbg_kms(&dev_priv->drm,
7600                             "Increasing T12 panel delay as per the quirk to %d\n",
7601                             vbt.t11_t12);
7602         }
7603         /* T11_T12 delay is special and actually in units of 100ms, but zero
7604          * based in the hw (so we need to add 100 ms). But the sw vbt
7605          * table multiplies it with 1000 to make it in units of 100usec,
7606          * too. */
7607         vbt.t11_t12 += 100 * 10;
7608
7609         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7610          * our hw here, which are all in 100usec. */
7611         spec.t1_t3 = 210 * 10;
7612         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7613         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7614         spec.t10 = 500 * 10;
7615         /* This one is special and actually in units of 100ms, but zero
7616          * based in the hw (so we need to add 100 ms). But the sw vbt
7617          * table multiplies it with 1000 to make it in units of 100usec,
7618          * too. */
7619         spec.t11_t12 = (510 + 100) * 10;
7620
7621         intel_pps_dump_state("vbt", &vbt);
7622
7623         /* Use the max of the register settings and vbt. If both are
7624          * unset, fall back to the spec limits. */
7625 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
7626                                        spec.field : \
7627                                        max(cur.field, vbt.field))
7628         assign_final(t1_t3);
7629         assign_final(t8);
7630         assign_final(t9);
7631         assign_final(t10);
7632         assign_final(t11_t12);
7633 #undef assign_final
7634
7635 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
7636         intel_dp->panel_power_up_delay = get_delay(t1_t3);
7637         intel_dp->backlight_on_delay = get_delay(t8);
7638         intel_dp->backlight_off_delay = get_delay(t9);
7639         intel_dp->panel_power_down_delay = get_delay(t10);
7640         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7641 #undef get_delay
7642
7643         drm_dbg_kms(&dev_priv->drm,
7644                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7645                     intel_dp->panel_power_up_delay,
7646                     intel_dp->panel_power_down_delay,
7647                     intel_dp->panel_power_cycle_delay);
7648
7649         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7650                     intel_dp->backlight_on_delay,
7651                     intel_dp->backlight_off_delay);
7652
7653         /*
7654          * We override the HW backlight delays to 1 because we do manual waits
7655          * on them. For T8, even BSpec recommends doing it. For T9, if we
7656          * don't do this, we'll end up waiting for the backlight off delay
7657          * twice: once when we do the manual sleep, and once when we disable
7658          * the panel and wait for the PP_STATUS bit to become zero.
7659          */
7660         final->t8 = 1;
7661         final->t9 = 1;
7662
7663         /*
7664          * HW has only a 100msec granularity for t11_t12 so round it up
7665          * accordingly.
7666          */
7667         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7668 }
7669
7670 static void
7671 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7672                                               bool force_disable_vdd)
7673 {
7674         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7675         u32 pp_on, pp_off, port_sel = 0;
7676         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7677         struct pps_registers regs;
7678         enum port port = dp_to_dig_port(intel_dp)->base.port;
7679         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7680
7681         lockdep_assert_held(&dev_priv->pps_mutex);
7682
7683         intel_pps_get_registers(intel_dp, &regs);
7684
7685         /*
7686          * On some VLV machines the BIOS can leave the VDD
7687          * enabled even on power sequencers which aren't
7688          * hooked up to any port. This would mess up the
7689          * power domain tracking the first time we pick
7690          * one of these power sequencers for use since
7691          * edp_panel_vdd_on() would notice that the VDD was
7692          * already on and therefore wouldn't grab the power
7693          * domain reference. Disable VDD first to avoid this.
7694          * This also avoids spuriously turning the VDD on as
7695          * soon as the new power sequencer gets initialized.
7696          */
7697         if (force_disable_vdd) {
7698                 u32 pp = ilk_get_pp_control(intel_dp);
7699
7700                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7701                          "Panel power already on\n");
7702
7703                 if (pp & EDP_FORCE_VDD)
7704                         drm_dbg_kms(&dev_priv->drm,
7705                                     "VDD already on, disabling first\n");
7706
7707                 pp &= ~EDP_FORCE_VDD;
7708
7709                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7710         }
7711
7712         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7713                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7714         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7715                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7716
7717         /* Haswell doesn't have any port selection bits for the panel
7718          * power sequencer any more. */
7719         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7720                 port_sel = PANEL_PORT_SELECT_VLV(port);
7721         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7722                 switch (port) {
7723                 case PORT_A:
7724                         port_sel = PANEL_PORT_SELECT_DPA;
7725                         break;
7726                 case PORT_C:
7727                         port_sel = PANEL_PORT_SELECT_DPC;
7728                         break;
7729                 case PORT_D:
7730                         port_sel = PANEL_PORT_SELECT_DPD;
7731                         break;
7732                 default:
7733                         MISSING_CASE(port);
7734                         break;
7735                 }
7736         }
7737
7738         pp_on |= port_sel;
7739
7740         intel_de_write(dev_priv, regs.pp_on, pp_on);
7741         intel_de_write(dev_priv, regs.pp_off, pp_off);
7742
7743         /*
7744          * Compute the divisor for the pp clock, simply match the Bspec formula.
7745          */
7746         if (i915_mmio_reg_valid(regs.pp_div)) {
7747                 intel_de_write(dev_priv, regs.pp_div,
7748                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7749         } else {
7750                 u32 pp_ctl;
7751
7752                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7753                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7754                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7755                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7756         }
7757
7758         drm_dbg_kms(&dev_priv->drm,
7759                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7760                     intel_de_read(dev_priv, regs.pp_on),
7761                     intel_de_read(dev_priv, regs.pp_off),
7762                     i915_mmio_reg_valid(regs.pp_div) ?
7763                     intel_de_read(dev_priv, regs.pp_div) :
7764                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7765 }
7766
7767 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7768 {
7769         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7770
7771         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7772                 vlv_initial_power_sequencer_setup(intel_dp);
7773         } else {
7774                 intel_dp_init_panel_power_sequencer(intel_dp);
7775                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7776         }
7777 }
7778
7779 /**
7780  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7781  * @dev_priv: i915 device
7782  * @crtc_state: a pointer to the active intel_crtc_state
7783  * @refresh_rate: RR to be programmed
7784  *
7785  * This function gets called when refresh rate (RR) has to be changed from
7786  * one frequency to another. Switches can be between high and low RR
7787  * supported by the panel or to any other RR based on media playback (in
7788  * this case, RR value needs to be passed from user space).
7789  *
7790  * The caller of this function needs to take a lock on dev_priv->drrs.
7791  */
7792 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7793                                     const struct intel_crtc_state *crtc_state,
7794                                     int refresh_rate)
7795 {
7796         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7798         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7799
7800         if (refresh_rate <= 0) {
7801                 drm_dbg_kms(&dev_priv->drm,
7802                             "Refresh rate should be positive non-zero.\n");
7803                 return;
7804         }
7805
7806         if (intel_dp == NULL) {
7807                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7808                 return;
7809         }
7810
7811         if (!intel_crtc) {
7812                 drm_dbg_kms(&dev_priv->drm,
7813                             "DRRS: intel_crtc not initialized\n");
7814                 return;
7815         }
7816
7817         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7818                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7819                 return;
7820         }
7821
7822         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
7823                         refresh_rate)
7824                 index = DRRS_LOW_RR;
7825
7826         if (index == dev_priv->drrs.refresh_rate_type) {
7827                 drm_dbg_kms(&dev_priv->drm,
7828                             "DRRS requested for previously set RR...ignoring\n");
7829                 return;
7830         }
7831
7832         if (!crtc_state->hw.active) {
7833                 drm_dbg_kms(&dev_priv->drm,
7834                             "eDP encoder disabled. CRTC not Active\n");
7835                 return;
7836         }
7837
7838         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7839                 switch (index) {
7840                 case DRRS_HIGH_RR:
7841                         intel_dp_set_m_n(crtc_state, M1_N1);
7842                         break;
7843                 case DRRS_LOW_RR:
7844                         intel_dp_set_m_n(crtc_state, M2_N2);
7845                         break;
7846                 case DRRS_MAX_RR:
7847                 default:
7848                         drm_err(&dev_priv->drm,
7849                                 "Unsupported refreshrate type\n");
7850                 }
7851         } else if (INTEL_GEN(dev_priv) > 6) {
7852                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7853                 u32 val;
7854
7855                 val = intel_de_read(dev_priv, reg);
7856                 if (index > DRRS_HIGH_RR) {
7857                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7858                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7859                         else
7860                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7861                 } else {
7862                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7863                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7864                         else
7865                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7866                 }
7867                 intel_de_write(dev_priv, reg, val);
7868         }
7869
7870         dev_priv->drrs.refresh_rate_type = index;
7871
7872         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7873                     refresh_rate);
7874 }
7875
7876 /**
7877  * intel_edp_drrs_enable - init drrs struct if supported
7878  * @intel_dp: DP struct
7879  * @crtc_state: A pointer to the active crtc state.
7880  *
7881  * Initializes frontbuffer_bits and drrs.dp
7882  */
7883 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7884                            const struct intel_crtc_state *crtc_state)
7885 {
7886         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7887
7888         if (!crtc_state->has_drrs) {
7889                 drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n");
7890                 return;
7891         }
7892
7893         if (dev_priv->psr.enabled) {
7894                 drm_dbg_kms(&dev_priv->drm,
7895                             "PSR enabled. Not enabling DRRS.\n");
7896                 return;
7897         }
7898
7899         mutex_lock(&dev_priv->drrs.mutex);
7900         if (dev_priv->drrs.dp) {
7901                 drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n");
7902                 goto unlock;
7903         }
7904
7905         dev_priv->drrs.busy_frontbuffer_bits = 0;
7906
7907         dev_priv->drrs.dp = intel_dp;
7908
7909 unlock:
7910         mutex_unlock(&dev_priv->drrs.mutex);
7911 }
7912
7913 /**
7914  * intel_edp_drrs_disable - Disable DRRS
7915  * @intel_dp: DP struct
7916  * @old_crtc_state: Pointer to old crtc_state.
7917  *
7918  */
7919 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7920                             const struct intel_crtc_state *old_crtc_state)
7921 {
7922         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7923
7924         if (!old_crtc_state->has_drrs)
7925                 return;
7926
7927         mutex_lock(&dev_priv->drrs.mutex);
7928         if (!dev_priv->drrs.dp) {
7929                 mutex_unlock(&dev_priv->drrs.mutex);
7930                 return;
7931         }
7932
7933         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7934                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7935                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7936
7937         dev_priv->drrs.dp = NULL;
7938         mutex_unlock(&dev_priv->drrs.mutex);
7939
7940         cancel_delayed_work_sync(&dev_priv->drrs.work);
7941 }
7942
7943 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7944 {
7945         struct drm_i915_private *dev_priv =
7946                 container_of(work, typeof(*dev_priv), drrs.work.work);
7947         struct intel_dp *intel_dp;
7948
7949         mutex_lock(&dev_priv->drrs.mutex);
7950
7951         intel_dp = dev_priv->drrs.dp;
7952
7953         if (!intel_dp)
7954                 goto unlock;
7955
7956         /*
7957          * The delayed work can race with an invalidate hence we need to
7958          * recheck.
7959          */
7960
7961         if (dev_priv->drrs.busy_frontbuffer_bits)
7962                 goto unlock;
7963
7964         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7965                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7966
7967                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7968                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7969         }
7970
7971 unlock:
7972         mutex_unlock(&dev_priv->drrs.mutex);
7973 }
7974
7975 /**
7976  * intel_edp_drrs_invalidate - Disable Idleness DRRS
7977  * @dev_priv: i915 device
7978  * @frontbuffer_bits: frontbuffer plane tracking bits
7979  *
7980  * This function gets called everytime rendering on the given planes start.
7981  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7982  *
7983  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7984  */
7985 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7986                                unsigned int frontbuffer_bits)
7987 {
7988         struct drm_crtc *crtc;
7989         enum pipe pipe;
7990
7991         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7992                 return;
7993
7994         cancel_delayed_work(&dev_priv->drrs.work);
7995
7996         mutex_lock(&dev_priv->drrs.mutex);
7997         if (!dev_priv->drrs.dp) {
7998                 mutex_unlock(&dev_priv->drrs.mutex);
7999                 return;
8000         }
8001
8002         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
8003         pipe = to_intel_crtc(crtc)->pipe;
8004
8005         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8006         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
8007
8008         /* invalidate means busy screen hence upclock */
8009         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8010                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8011                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
8012
8013         mutex_unlock(&dev_priv->drrs.mutex);
8014 }
8015
8016 /**
8017  * intel_edp_drrs_flush - Restart Idleness DRRS
8018  * @dev_priv: i915 device
8019  * @frontbuffer_bits: frontbuffer plane tracking bits
8020  *
8021  * This function gets called every time rendering on the given planes has
8022  * completed or flip on a crtc is completed. So DRRS should be upclocked
8023  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
8024  * if no other planes are dirty.
8025  *
8026  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
8027  */
8028 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
8029                           unsigned int frontbuffer_bits)
8030 {
8031         struct drm_crtc *crtc;
8032         enum pipe pipe;
8033
8034         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
8035                 return;
8036
8037         cancel_delayed_work(&dev_priv->drrs.work);
8038
8039         mutex_lock(&dev_priv->drrs.mutex);
8040         if (!dev_priv->drrs.dp) {
8041                 mutex_unlock(&dev_priv->drrs.mutex);
8042                 return;
8043         }
8044
8045         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
8046         pipe = to_intel_crtc(crtc)->pipe;
8047
8048         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8049         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
8050
8051         /* flush means busy screen hence upclock */
8052         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8053                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8054                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
8055
8056         /*
8057          * flush also means no more activity hence schedule downclock, if all
8058          * other fbs are quiescent too
8059          */
8060         if (!dev_priv->drrs.busy_frontbuffer_bits)
8061                 schedule_delayed_work(&dev_priv->drrs.work,
8062                                 msecs_to_jiffies(1000));
8063         mutex_unlock(&dev_priv->drrs.mutex);
8064 }
8065
8066 /**
8067  * DOC: Display Refresh Rate Switching (DRRS)
8068  *
8069  * Display Refresh Rate Switching (DRRS) is a power conservation feature
8070  * which enables swtching between low and high refresh rates,
8071  * dynamically, based on the usage scenario. This feature is applicable
8072  * for internal panels.
8073  *
8074  * Indication that the panel supports DRRS is given by the panel EDID, which
8075  * would list multiple refresh rates for one resolution.
8076  *
8077  * DRRS is of 2 types - static and seamless.
8078  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
8079  * (may appear as a blink on screen) and is used in dock-undock scenario.
8080  * Seamless DRRS involves changing RR without any visual effect to the user
8081  * and can be used during normal system usage. This is done by programming
8082  * certain registers.
8083  *
8084  * Support for static/seamless DRRS may be indicated in the VBT based on
8085  * inputs from the panel spec.
8086  *
8087  * DRRS saves power by switching to low RR based on usage scenarios.
8088  *
8089  * The implementation is based on frontbuffer tracking implementation.  When
8090  * there is a disturbance on the screen triggered by user activity or a periodic
8091  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
8092  * no movement on screen, after a timeout of 1 second, a switch to low RR is
8093  * made.
8094  *
8095  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
8096  * and intel_edp_drrs_flush() are called.
8097  *
8098  * DRRS can be further extended to support other internal panels and also
8099  * the scenario of video playback wherein RR is set based on the rate
8100  * requested by userspace.
8101  */
8102
8103 /**
8104  * intel_dp_drrs_init - Init basic DRRS work and mutex.
8105  * @connector: eDP connector
8106  * @fixed_mode: preferred mode of panel
8107  *
8108  * This function is  called only once at driver load to initialize basic
8109  * DRRS stuff.
8110  *
8111  * Returns:
8112  * Downclock mode if panel supports it, else return NULL.
8113  * DRRS support is determined by the presence of downclock mode (apart
8114  * from VBT setting).
8115  */
8116 static struct drm_display_mode *
8117 intel_dp_drrs_init(struct intel_connector *connector,
8118                    struct drm_display_mode *fixed_mode)
8119 {
8120         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8121         struct drm_display_mode *downclock_mode = NULL;
8122
8123         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
8124         mutex_init(&dev_priv->drrs.mutex);
8125
8126         if (INTEL_GEN(dev_priv) <= 6) {
8127                 drm_dbg_kms(&dev_priv->drm,
8128                             "DRRS supported for Gen7 and above\n");
8129                 return NULL;
8130         }
8131
8132         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
8133                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
8134                 return NULL;
8135         }
8136
8137         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
8138         if (!downclock_mode) {
8139                 drm_dbg_kms(&dev_priv->drm,
8140                             "Downclock mode is not found. DRRS not supported\n");
8141                 return NULL;
8142         }
8143
8144         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
8145
8146         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
8147         drm_dbg_kms(&dev_priv->drm,
8148                     "seamless DRRS supported for eDP panel.\n");
8149         return downclock_mode;
8150 }
8151
8152 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
8153                                      struct intel_connector *intel_connector)
8154 {
8155         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8156         struct drm_device *dev = &dev_priv->drm;
8157         struct drm_connector *connector = &intel_connector->base;
8158         struct drm_display_mode *fixed_mode = NULL;
8159         struct drm_display_mode *downclock_mode = NULL;
8160         bool has_dpcd;
8161         enum pipe pipe = INVALID_PIPE;
8162         intel_wakeref_t wakeref;
8163         struct edid *edid;
8164
8165         if (!intel_dp_is_edp(intel_dp))
8166                 return true;
8167
8168         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8169
8170         /*
8171          * On IBX/CPT we may get here with LVDS already registered. Since the
8172          * driver uses the only internal power sequencer available for both
8173          * eDP and LVDS bail out early in this case to prevent interfering
8174          * with an already powered-on LVDS power sequencer.
8175          */
8176         if (intel_get_lvds_encoder(dev_priv)) {
8177                 drm_WARN_ON(dev,
8178                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8179                 drm_info(&dev_priv->drm,
8180                          "LVDS was detected, not registering eDP\n");
8181
8182                 return false;
8183         }
8184
8185         with_pps_lock(intel_dp, wakeref) {
8186                 intel_dp_init_panel_power_timestamps(intel_dp);
8187                 intel_dp_pps_init(intel_dp);
8188                 intel_edp_panel_vdd_sanitize(intel_dp);
8189         }
8190
8191         /* Cache DPCD and EDID for edp. */
8192         has_dpcd = intel_edp_init_dpcd(intel_dp);
8193
8194         if (!has_dpcd) {
8195                 /* if this fails, presume the device is a ghost */
8196                 drm_info(&dev_priv->drm,
8197                          "failed to retrieve link info, disabling eDP\n");
8198                 goto out_vdd_off;
8199         }
8200
8201         mutex_lock(&dev->mode_config.mutex);
8202         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8203         if (edid) {
8204                 if (drm_add_edid_modes(connector, edid)) {
8205                         drm_connector_update_edid_property(connector, edid);
8206                         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8207                 } else {
8208                         kfree(edid);
8209                         edid = ERR_PTR(-EINVAL);
8210                 }
8211         } else {
8212                 edid = ERR_PTR(-ENOENT);
8213         }
8214         intel_connector->edid = edid;
8215
8216         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8217         if (fixed_mode)
8218                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8219
8220         /* fallback to VBT if available for eDP */
8221         if (!fixed_mode)
8222                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8223         mutex_unlock(&dev->mode_config.mutex);
8224
8225         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8226                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
8227                 register_reboot_notifier(&intel_dp->edp_notifier);
8228
8229                 /*
8230                  * Figure out the current pipe for the initial backlight setup.
8231                  * If the current pipe isn't valid, try the PPS pipe, and if that
8232                  * fails just assume pipe A.
8233                  */
8234                 pipe = vlv_active_pipe(intel_dp);
8235
8236                 if (pipe != PIPE_A && pipe != PIPE_B)
8237                         pipe = intel_dp->pps_pipe;
8238
8239                 if (pipe != PIPE_A && pipe != PIPE_B)
8240                         pipe = PIPE_A;
8241
8242                 drm_dbg_kms(&dev_priv->drm,
8243                             "using pipe %c for initial backlight setup\n",
8244                             pipe_name(pipe));
8245         }
8246
8247         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8248         intel_connector->panel.backlight.power = intel_edp_backlight_power;
8249         intel_panel_setup_backlight(connector, pipe);
8250
8251         if (fixed_mode) {
8252                 drm_connector_set_panel_orientation_with_quirk(connector,
8253                                 dev_priv->vbt.orientation,
8254                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
8255         }
8256
8257         return true;
8258
8259 out_vdd_off:
8260         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8261         /*
8262          * vdd might still be enabled do to the delayed vdd off.
8263          * Make sure vdd is actually turned off here.
8264          */
8265         with_pps_lock(intel_dp, wakeref)
8266                 edp_panel_vdd_off_sync(intel_dp);
8267
8268         return false;
8269 }
8270
8271 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8272 {
8273         struct intel_connector *intel_connector;
8274         struct drm_connector *connector;
8275
8276         intel_connector = container_of(work, typeof(*intel_connector),
8277                                        modeset_retry_work);
8278         connector = &intel_connector->base;
8279         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8280                       connector->name);
8281
8282         /* Grab the locks before changing connector property*/
8283         mutex_lock(&connector->dev->mode_config.mutex);
8284         /* Set connector link status to BAD and send a Uevent to notify
8285          * userspace to do a modeset.
8286          */
8287         drm_connector_set_link_status_property(connector,
8288                                                DRM_MODE_LINK_STATUS_BAD);
8289         mutex_unlock(&connector->dev->mode_config.mutex);
8290         /* Send Hotplug uevent so userspace can reprobe */
8291         drm_kms_helper_hotplug_event(connector->dev);
8292 }
8293
8294 bool
8295 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
8296                         struct intel_connector *intel_connector)
8297 {
8298         struct drm_connector *connector = &intel_connector->base;
8299         struct intel_dp *intel_dp = &intel_dig_port->dp;
8300         struct intel_encoder *intel_encoder = &intel_dig_port->base;
8301         struct drm_device *dev = intel_encoder->base.dev;
8302         struct drm_i915_private *dev_priv = to_i915(dev);
8303         enum port port = intel_encoder->port;
8304         enum phy phy = intel_port_to_phy(dev_priv, port);
8305         int type;
8306
8307         /* Initialize the work for modeset in case of link train failure */
8308         INIT_WORK(&intel_connector->modeset_retry_work,
8309                   intel_dp_modeset_retry_work_fn);
8310
8311         if (drm_WARN(dev, intel_dig_port->max_lanes < 1,
8312                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8313                      intel_dig_port->max_lanes, intel_encoder->base.base.id,
8314                      intel_encoder->base.name))
8315                 return false;
8316
8317         intel_dp_set_source_rates(intel_dp);
8318
8319         intel_dp->reset_link_params = true;
8320         intel_dp->pps_pipe = INVALID_PIPE;
8321         intel_dp->active_pipe = INVALID_PIPE;
8322
8323         /* Preserve the current hw state. */
8324         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8325         intel_dp->attached_connector = intel_connector;
8326
8327         if (intel_dp_is_port_edp(dev_priv, port)) {
8328                 /*
8329                  * Currently we don't support eDP on TypeC ports, although in
8330                  * theory it could work on TypeC legacy ports.
8331                  */
8332                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8333                 type = DRM_MODE_CONNECTOR_eDP;
8334         } else {
8335                 type = DRM_MODE_CONNECTOR_DisplayPort;
8336         }
8337
8338         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8339                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8340
8341         /*
8342          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8343          * for DP the encoder type can be set by the caller to
8344          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8345          */
8346         if (type == DRM_MODE_CONNECTOR_eDP)
8347                 intel_encoder->type = INTEL_OUTPUT_EDP;
8348
8349         /* eDP only on port B and/or C on vlv/chv */
8350         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8351                               IS_CHERRYVIEW(dev_priv)) &&
8352                         intel_dp_is_edp(intel_dp) &&
8353                         port != PORT_B && port != PORT_C))
8354                 return false;
8355
8356         drm_dbg_kms(&dev_priv->drm,
8357                     "Adding %s connector on [ENCODER:%d:%s]\n",
8358                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8359                     intel_encoder->base.base.id, intel_encoder->base.name);
8360
8361         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8362         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8363
8364         if (!HAS_GMCH(dev_priv))
8365                 connector->interlace_allowed = true;
8366         connector->doublescan_allowed = 0;
8367
8368         if (INTEL_GEN(dev_priv) >= 11)
8369                 connector->ycbcr_420_allowed = true;
8370
8371         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8372         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8373
8374         intel_dp_aux_init(intel_dp);
8375
8376         intel_connector_attach_encoder(intel_connector, intel_encoder);
8377
8378         if (HAS_DDI(dev_priv))
8379                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8380         else
8381                 intel_connector->get_hw_state = intel_connector_get_hw_state;
8382
8383         /* init MST on ports that can support it */
8384         intel_dp_mst_encoder_init(intel_dig_port,
8385                                   intel_connector->base.base.id);
8386
8387         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8388                 intel_dp_aux_fini(intel_dp);
8389                 intel_dp_mst_encoder_cleanup(intel_dig_port);
8390                 goto fail;
8391         }
8392
8393         intel_dp_add_properties(intel_dp, connector);
8394
8395         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8396                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
8397                 if (ret)
8398                         drm_dbg_kms(&dev_priv->drm,
8399                                     "HDCP init failed, skipping.\n");
8400         }
8401
8402         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8403          * 0xd.  Failure to do so will result in spurious interrupts being
8404          * generated on the port when a cable is not attached.
8405          */
8406         if (IS_G45(dev_priv)) {
8407                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8408                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8409                                (temp & ~0xf) | 0xd);
8410         }
8411
8412         return true;
8413
8414 fail:
8415         drm_connector_cleanup(connector);
8416
8417         return false;
8418 }
8419
8420 bool intel_dp_init(struct drm_i915_private *dev_priv,
8421                    i915_reg_t output_reg,
8422                    enum port port)
8423 {
8424         struct intel_digital_port *intel_dig_port;
8425         struct intel_encoder *intel_encoder;
8426         struct drm_encoder *encoder;
8427         struct intel_connector *intel_connector;
8428
8429         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
8430         if (!intel_dig_port)
8431                 return false;
8432
8433         intel_connector = intel_connector_alloc();
8434         if (!intel_connector)
8435                 goto err_connector_alloc;
8436
8437         intel_encoder = &intel_dig_port->base;
8438         encoder = &intel_encoder->base;
8439
8440         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8441                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8442                              "DP %c", port_name(port)))
8443                 goto err_encoder_init;
8444
8445         intel_encoder->hotplug = intel_dp_hotplug;
8446         intel_encoder->compute_config = intel_dp_compute_config;
8447         intel_encoder->get_hw_state = intel_dp_get_hw_state;
8448         intel_encoder->get_config = intel_dp_get_config;
8449         intel_encoder->update_pipe = intel_panel_update_backlight;
8450         intel_encoder->suspend = intel_dp_encoder_suspend;
8451         if (IS_CHERRYVIEW(dev_priv)) {
8452                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8453                 intel_encoder->pre_enable = chv_pre_enable_dp;
8454                 intel_encoder->enable = vlv_enable_dp;
8455                 intel_encoder->disable = vlv_disable_dp;
8456                 intel_encoder->post_disable = chv_post_disable_dp;
8457                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8458         } else if (IS_VALLEYVIEW(dev_priv)) {
8459                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8460                 intel_encoder->pre_enable = vlv_pre_enable_dp;
8461                 intel_encoder->enable = vlv_enable_dp;
8462                 intel_encoder->disable = vlv_disable_dp;
8463                 intel_encoder->post_disable = vlv_post_disable_dp;
8464         } else {
8465                 intel_encoder->pre_enable = g4x_pre_enable_dp;
8466                 intel_encoder->enable = g4x_enable_dp;
8467                 intel_encoder->disable = g4x_disable_dp;
8468                 intel_encoder->post_disable = g4x_post_disable_dp;
8469         }
8470
8471         intel_dig_port->dp.output_reg = output_reg;
8472         intel_dig_port->max_lanes = 4;
8473
8474         intel_encoder->type = INTEL_OUTPUT_DP;
8475         intel_encoder->power_domain = intel_port_to_power_domain(port);
8476         if (IS_CHERRYVIEW(dev_priv)) {
8477                 if (port == PORT_D)
8478                         intel_encoder->pipe_mask = BIT(PIPE_C);
8479                 else
8480                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8481         } else {
8482                 intel_encoder->pipe_mask = ~0;
8483         }
8484         intel_encoder->cloneable = 0;
8485         intel_encoder->port = port;
8486
8487         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
8488
8489         if (port != PORT_A)
8490                 intel_infoframe_init(intel_dig_port);
8491
8492         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8493         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
8494                 goto err_init_connector;
8495
8496         return true;
8497
8498 err_init_connector:
8499         drm_encoder_cleanup(encoder);
8500 err_encoder_init:
8501         kfree(intel_connector);
8502 err_connector_alloc:
8503         kfree(intel_dig_port);
8504         return false;
8505 }
8506
8507 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8508 {
8509         struct intel_encoder *encoder;
8510
8511         for_each_intel_encoder(&dev_priv->drm, encoder) {
8512                 struct intel_dp *intel_dp;
8513
8514                 if (encoder->type != INTEL_OUTPUT_DDI)
8515                         continue;
8516
8517                 intel_dp = enc_to_intel_dp(encoder);
8518
8519                 if (!intel_dp->can_mst)
8520                         continue;
8521
8522                 if (intel_dp->is_mst)
8523                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8524         }
8525 }
8526
8527 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8528 {
8529         struct intel_encoder *encoder;
8530
8531         for_each_intel_encoder(&dev_priv->drm, encoder) {
8532                 struct intel_dp *intel_dp;
8533                 int ret;
8534
8535                 if (encoder->type != INTEL_OUTPUT_DDI)
8536                         continue;
8537
8538                 intel_dp = enc_to_intel_dp(encoder);
8539
8540                 if (!intel_dp->can_mst)
8541                         continue;
8542
8543                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8544                                                      true);
8545                 if (ret) {
8546                         intel_dp->is_mst = false;
8547                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
8548                                                         false);
8549                 }
8550         }
8551 }