drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_drv.h"
  48 #include "i915_irq.h"
  49 #include "i915_reg.h"
  50 #include "intel_atomic.h"
  51 #include "intel_audio.h"
  52 #include "intel_backlight.h"
  53 #include "intel_combo_phy_regs.h"
  54 #include "intel_connector.h"
  55 #include "intel_crtc.h"
  56 #include "intel_cx0_phy.h"
  57 #include "intel_ddi.h"
  58 #include "intel_de.h"
  59 #include "intel_display_types.h"
  60 #include "intel_dp.h"
  61 #include "intel_dp_aux.h"
  62 #include "intel_dp_hdcp.h"
  63 #include "intel_dp_link_training.h"
  64 #include "intel_dp_mst.h"
  65 #include "intel_dpio_phy.h"
  66 #include "intel_dpll.h"
  67 #include "intel_fifo_underrun.h"
  68 #include "intel_hdcp.h"
  69 #include "intel_hdmi.h"
  70 #include "intel_hotplug.h"
  71 #include "intel_hotplug_irq.h"
  72 #include "intel_lspcon.h"
  73 #include "intel_lvds.h"
  74 #include "intel_panel.h"
  75 #include "intel_pch_display.h"
  76 #include "intel_pps.h"
  77 #include "intel_psr.h"
  78 #include "intel_tc.h"
  79 #include "intel_vdsc.h"
  80 #include "intel_vrr.h"
  81 #include "intel_crtc_state_dump.h"
  82
  83 /* DP DSC throughput values used for slice count calculations KPixels/s */
  84 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  85 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  86 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  87
  88 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  89 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  90
  91 /* Compliance test status bits  */
  92 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  93 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  94 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  95 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  96
  97
  98 /* Constants for DP DSC configurations */
  99 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 100
 101 /* With Single pipe configuration, HW is capable of supporting maximum
 102  * of 4 slices per line.
 103  */
 104 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  *
 113  * This function is not safe to use prior to encoder type being set.
 114  */
 115 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 116 {
 117         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 118
 119         return dig_port->base.type == INTEL_OUTPUT_EDP;
 120 }
 121
 122 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 123
 124 /* Is link rate UHBR and thus 128b/132b? */
 125 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 126 {
 127         return crtc_state->port_clock >= 1000000;
 128 }
 129
 130 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 131 {
 132         intel_dp->sink_rates[0] = 162000;
 133         intel_dp->num_sink_rates = 1;
 134 }
 135
 136 /* update sink rates from dpcd */
 137 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 138 {
 139         static const int dp_rates[] = {
 140                 162000, 270000, 540000, 810000
 141         };
 142         int i, max_rate;
 143         int max_lttpr_rate;
 144
 145         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 146                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 147                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 148
 149                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 150                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 151
 152                 return;
 153         }
 154
 155         /*
 156          * Sink rates for 8b/10b.
 157          */
 158         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 159         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 160         if (max_lttpr_rate)
 161                 max_rate = min(max_rate, max_lttpr_rate);
 162
 163         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 164                 if (dp_rates[i] > max_rate)
 165                         break;
 166                 intel_dp->sink_rates[i] = dp_rates[i];
 167         }
 168
 169         /*
 170          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 171          * rates and 10 Gbps.
 172          */
 173         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 174                 u8 uhbr_rates = 0;
 175
 176                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 177
 178                 drm_dp_dpcd_readb(&intel_dp->aux,
 179                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 180
 181                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 182                         /* We have a repeater */
 183                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 184                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 185                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 186                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 187                                 /* Repeater supports 128b/132b, valid UHBR rates */
 188                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 189                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 190                         } else {
 191                                 /* Does not support 128b/132b */
 192                                 uhbr_rates = 0;
 193                         }
 194                 }
 195
 196                 if (uhbr_rates & DP_UHBR10)
 197                         intel_dp->sink_rates[i++] = 1000000;
 198                 if (uhbr_rates & DP_UHBR13_5)
 199                         intel_dp->sink_rates[i++] = 1350000;
 200                 if (uhbr_rates & DP_UHBR20)
 201                         intel_dp->sink_rates[i++] = 2000000;
 202         }
 203
 204         intel_dp->num_sink_rates = i;
 205 }
 206
 207 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 208 {
 209         struct intel_connector *connector = intel_dp->attached_connector;
 210         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 211         struct intel_encoder *encoder = &intel_dig_port->base;
 212
 213         intel_dp_set_dpcd_sink_rates(intel_dp);
 214
 215         if (intel_dp->num_sink_rates)
 216                 return;
 217
 218         drm_err(&dp_to_i915(intel_dp)->drm,
 219                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 220                 connector->base.base.id, connector->base.name,
 221                 encoder->base.base.id, encoder->base.name);
 222
 223         intel_dp_set_default_sink_rates(intel_dp);
 224 }
 225
 226 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 227 {
 228         intel_dp->max_sink_lane_count = 1;
 229 }
 230
 231 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 232 {
 233         struct intel_connector *connector = intel_dp->attached_connector;
 234         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 235         struct intel_encoder *encoder = &intel_dig_port->base;
 236
 237         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 238
 239         switch (intel_dp->max_sink_lane_count) {
 240         case 1:
 241         case 2:
 242         case 4:
 243                 return;
 244         }
 245
 246         drm_err(&dp_to_i915(intel_dp)->drm,
 247                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 248                 connector->base.base.id, connector->base.name,
 249                 encoder->base.base.id, encoder->base.name,
 250                 intel_dp->max_sink_lane_count);
 251
 252         intel_dp_set_default_max_sink_lane_count(intel_dp);
 253 }
 254
 255 /* Get length of rates array potentially limited by max_rate. */
 256 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 257 {
 258         int i;
 259
 260         /* Limit results by potentially reduced max rate */
 261         for (i = 0; i < len; i++) {
 262                 if (rates[len - i - 1] <= max_rate)
 263                         return len - i;
 264         }
 265
 266         return 0;
 267 }
 268
 269 /* Get length of common rates array potentially limited by max_rate. */
 270 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 271                                           int max_rate)
 272 {
 273         return intel_dp_rate_limit_len(intel_dp->common_rates,
 274                                        intel_dp->num_common_rates, max_rate);
 275 }
 276
 277 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 278 {
 279         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 280                         index < 0 || index >= intel_dp->num_common_rates))
 281                 return 162000;
 282
 283         return intel_dp->common_rates[index];
 284 }
 285
 286 /* Theoretical max between source and sink */
 287 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 288 {
 289         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 290 }
 291
 292 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 293 {
 294         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 295         int max_lanes = dig_port->max_lanes;
 296
 297         if (vbt_max_lanes)
 298                 max_lanes = min(max_lanes, vbt_max_lanes);
 299
 300         return max_lanes;
 301 }
 302
 303 /* Theoretical max between source and sink */
 304 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 305 {
 306         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 307         int source_max = intel_dp_max_source_lane_count(dig_port);
 308         int sink_max = intel_dp->max_sink_lane_count;
 309         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 310         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 311
 312         if (lttpr_max)
 313                 sink_max = min(sink_max, lttpr_max);
 314
 315         return min3(source_max, sink_max, fia_max);
 316 }
 317
 318 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 319 {
 320         switch (intel_dp->max_link_lane_count) {
 321         case 1:
 322         case 2:
 323         case 4:
 324                 return intel_dp->max_link_lane_count;
 325         default:
 326                 MISSING_CASE(intel_dp->max_link_lane_count);
 327                 return 1;
 328         }
 329 }
 330
 331 /*
 332  * The required data bandwidth for a mode with given pixel clock and bpp. This
 333  * is the required net bandwidth independent of the data bandwidth efficiency.
 334  */
 335 int
 336 intel_dp_link_required(int pixel_clock, int bpp)
 337 {
 338         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 339         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 340 }
 341
 342 /*
 343  * Given a link rate and lanes, get the data bandwidth.
 344  *
 345  * Data bandwidth is the actual payload rate, which depends on the data
 346  * bandwidth efficiency and the link rate.
 347  *
 348  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 349  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 350  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 351  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 352  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 353  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 354  *
 355  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 356  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 357  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 358  * does not match the symbol clock, the port clock (not even if you think in
 359  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 360  * rate in units of 10000 bps.
 361  */
 362 int
 363 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 364 {
 365         if (max_link_rate >= 1000000) {
 366                 /*
 367                  * UHBR rates always use 128b/132b channel encoding, and have
 368                  * 97.71% data bandwidth efficiency. Consider max_link_rate the
 369                  * link bit rate in units of 10000 bps.
 370                  */
 371                 int max_link_rate_kbps = max_link_rate * 10;
 372
 373                 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 374                 max_link_rate = max_link_rate_kbps / 8;
 375         }
 376
 377         /*
 378          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 379          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 380          * out to be a nop by coincidence, and can be skipped:
 381          *
 382          *      int max_link_rate_kbps = max_link_rate * 10;
 383          *      max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 384          *      max_link_rate = max_link_rate_kbps / 8;
 385          */
 386
 387         return max_link_rate * max_lanes;
 388 }
 389
 390 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 391 {
 392         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 393         struct intel_encoder *encoder = &intel_dig_port->base;
 394         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 395
 396         return DISPLAY_VER(dev_priv) >= 12 ||
 397                 (DISPLAY_VER(dev_priv) == 11 &&
 398                  encoder->port != PORT_A);
 399 }
 400
 401 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 402 {
 403         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 404 }
 405
 406 static int icl_max_source_rate(struct intel_dp *intel_dp)
 407 {
 408         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 409         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 410         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 411
 412         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 413                 return 540000;
 414
 415         return 810000;
 416 }
 417
 418 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 419 {
 420         if (intel_dp_is_edp(intel_dp))
 421                 return 540000;
 422
 423         return 810000;
 424 }
 425
 426 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 427 {
 428         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 429         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 430         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 431
 432         if (intel_is_c10phy(i915, phy))
 433                 return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
 434
 435         return 2000000;
 436 }
 437
 438 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 439 {
 440         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 441         int max_rate;
 442
 443         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 444
 445         if (intel_dp_is_edp(intel_dp)) {
 446                 struct intel_connector *connector = intel_dp->attached_connector;
 447                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 448
 449                 if (max_rate && edp_max_rate)
 450                         max_rate = min(max_rate, edp_max_rate);
 451                 else if (edp_max_rate)
 452                         max_rate = edp_max_rate;
 453         }
 454
 455         return max_rate;
 456 }
 457
 458 static void
 459 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 460 {
 461         /* The values must be in increasing order */
 462         static const int mtl_rates[] = {
 463                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 464                 810000, 1000000, 1350000, 2000000,
 465         };
 466         static const int icl_rates[] = {
 467                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 468                 1000000, 1350000,
 469         };
 470         static const int bxt_rates[] = {
 471                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 472         };
 473         static const int skl_rates[] = {
 474                 162000, 216000, 270000, 324000, 432000, 540000
 475         };
 476         static const int hsw_rates[] = {
 477                 162000, 270000, 540000
 478         };
 479         static const int g4x_rates[] = {
 480                 162000, 270000
 481         };
 482         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 483         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 484         const int *source_rates;
 485         int size, max_rate = 0, vbt_max_rate;
 486
 487         /* This should only be done once */
 488         drm_WARN_ON(&dev_priv->drm,
 489                     intel_dp->source_rates || intel_dp->num_source_rates);
 490
 491         if (DISPLAY_VER(dev_priv) >= 14) {
 492                 source_rates = mtl_rates;
 493                 size = ARRAY_SIZE(mtl_rates);
 494                 max_rate = mtl_max_source_rate(intel_dp);
 495         } else if (DISPLAY_VER(dev_priv) >= 11) {
 496                 source_rates = icl_rates;
 497                 size = ARRAY_SIZE(icl_rates);
 498                 if (IS_DG2(dev_priv))
 499                         max_rate = dg2_max_source_rate(intel_dp);
 500                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 501                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 502                         max_rate = 810000;
 503                 else if (IS_JSL_EHL(dev_priv))
 504                         max_rate = ehl_max_source_rate(intel_dp);
 505                 else
 506                         max_rate = icl_max_source_rate(intel_dp);
 507         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 508                 source_rates = bxt_rates;
 509                 size = ARRAY_SIZE(bxt_rates);
 510         } else if (DISPLAY_VER(dev_priv) == 9) {
 511                 source_rates = skl_rates;
 512                 size = ARRAY_SIZE(skl_rates);
 513         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 514                    IS_BROADWELL(dev_priv)) {
 515                 source_rates = hsw_rates;
 516                 size = ARRAY_SIZE(hsw_rates);
 517         } else {
 518                 source_rates = g4x_rates;
 519                 size = ARRAY_SIZE(g4x_rates);
 520         }
 521
 522         vbt_max_rate = vbt_max_link_rate(intel_dp);
 523         if (max_rate && vbt_max_rate)
 524                 max_rate = min(max_rate, vbt_max_rate);
 525         else if (vbt_max_rate)
 526                 max_rate = vbt_max_rate;
 527
 528         if (max_rate)
 529                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 530
 531         intel_dp->source_rates = source_rates;
 532         intel_dp->num_source_rates = size;
 533 }
 534
 535 static int intersect_rates(const int *source_rates, int source_len,
 536                            const int *sink_rates, int sink_len,
 537                            int *common_rates)
 538 {
 539         int i = 0, j = 0, k = 0;
 540
 541         while (i < source_len && j < sink_len) {
 542                 if (source_rates[i] == sink_rates[j]) {
 543                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 544                                 return k;
 545                         common_rates[k] = source_rates[i];
 546                         ++k;
 547                         ++i;
 548                         ++j;
 549                 } else if (source_rates[i] < sink_rates[j]) {
 550                         ++i;
 551                 } else {
 552                         ++j;
 553                 }
 554         }
 555         return k;
 556 }
 557
 558 /* return index of rate in rates array, or -1 if not found */
 559 static int intel_dp_rate_index(const int *rates, int len, int rate)
 560 {
 561         int i;
 562
 563         for (i = 0; i < len; i++)
 564                 if (rate == rates[i])
 565                         return i;
 566
 567         return -1;
 568 }
 569
 570 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 571 {
 572         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 573
 574         drm_WARN_ON(&i915->drm,
 575                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 576
 577         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 578                                                      intel_dp->num_source_rates,
 579                                                      intel_dp->sink_rates,
 580                                                      intel_dp->num_sink_rates,
 581                                                      intel_dp->common_rates);
 582
 583         /* Paranoia, there should always be something in common. */
 584         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 585                 intel_dp->common_rates[0] = 162000;
 586                 intel_dp->num_common_rates = 1;
 587         }
 588 }
 589
 590 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 591                                        u8 lane_count)
 592 {
 593         /*
 594          * FIXME: we need to synchronize the current link parameters with
 595          * hardware readout. Currently fast link training doesn't work on
 596          * boot-up.
 597          */
 598         if (link_rate == 0 ||
 599             link_rate > intel_dp->max_link_rate)
 600                 return false;
 601
 602         if (lane_count == 0 ||
 603             lane_count > intel_dp_max_lane_count(intel_dp))
 604                 return false;
 605
 606         return true;
 607 }
 608
 609 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 610                                                      int link_rate,
 611                                                      u8 lane_count)
 612 {
 613         /* FIXME figure out what we actually want here */
 614         const struct drm_display_mode *fixed_mode =
 615                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 616         int mode_rate, max_rate;
 617
 618         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 619         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 620         if (mode_rate > max_rate)
 621                 return false;
 622
 623         return true;
 624 }
 625
 626 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 627                                             int link_rate, u8 lane_count)
 628 {
 629         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 630         int index;
 631
 632         /*
 633          * TODO: Enable fallback on MST links once MST link compute can handle
 634          * the fallback params.
 635          */
 636         if (intel_dp->is_mst) {
 637                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 638                 return -1;
 639         }
 640
 641         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 642                 drm_dbg_kms(&i915->drm,
 643                             "Retrying Link training for eDP with max parameters\n");
 644                 intel_dp->use_max_params = true;
 645                 return 0;
 646         }
 647
 648         index = intel_dp_rate_index(intel_dp->common_rates,
 649                                     intel_dp->num_common_rates,
 650                                     link_rate);
 651         if (index > 0) {
 652                 if (intel_dp_is_edp(intel_dp) &&
 653                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 654                                                               intel_dp_common_rate(intel_dp, index - 1),
 655                                                               lane_count)) {
 656                         drm_dbg_kms(&i915->drm,
 657                                     "Retrying Link training for eDP with same parameters\n");
 658                         return 0;
 659                 }
 660                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 661                 intel_dp->max_link_lane_count = lane_count;
 662         } else if (lane_count > 1) {
 663                 if (intel_dp_is_edp(intel_dp) &&
 664                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 665                                                               intel_dp_max_common_rate(intel_dp),
 666                                                               lane_count >> 1)) {
 667                         drm_dbg_kms(&i915->drm,
 668                                     "Retrying Link training for eDP with same parameters\n");
 669                         return 0;
 670                 }
 671                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 672                 intel_dp->max_link_lane_count = lane_count >> 1;
 673         } else {
 674                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 675                 return -1;
 676         }
 677
 678         return 0;
 679 }
 680
 681 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 682 {
 683         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 684                        DP_DSC_FEC_OVERHEAD_FACTOR);
 685 }
 686
 687 static int
 688 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 689 {
 690         if (DISPLAY_VER(i915) >= 13)
 691                 return 17280 * 8;
 692         else if (DISPLAY_VER(i915) >= 11)
 693                 return 7680 * 8;
 694         else
 695                 return 6144 * 8;
 696 }
 697
 698 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 699 {
 700         u32 bits_per_pixel = bpp;
 701         int i;
 702
 703         /* Error out if the max bpp is less than smallest allowed valid bpp */
 704         if (bits_per_pixel < valid_dsc_bpp[0]) {
 705                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 706                             bits_per_pixel, valid_dsc_bpp[0]);
 707                 return 0;
 708         }
 709
 710         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 711         if (DISPLAY_VER(i915) >= 13) {
 712                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 713
 714                 /*
 715                  * According to BSpec, 27 is the max DSC output bpp,
 716                  * 8 is the min DSC output bpp
 717                  */
 718                 bits_per_pixel = clamp_t(u32, bits_per_pixel, 8, 27);
 719         } else {
 720                 /* Find the nearest match in the array of known BPPs from VESA */
 721                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 722                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 723                                 break;
 724                 }
 725                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 726                             bits_per_pixel, valid_dsc_bpp[i]);
 727
 728                 bits_per_pixel = valid_dsc_bpp[i];
 729         }
 730
 731         return bits_per_pixel;
 732 }
 733
 734 u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 735                                 u32 link_clock, u32 lane_count,
 736                                 u32 mode_clock, u32 mode_hdisplay,
 737                                 bool bigjoiner,
 738                                 u32 pipe_bpp,
 739                                 u32 timeslots)
 740 {
 741         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 742
 743         /*
 744          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 745          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 746          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 747          * for MST -> TimeSlots has to be calculated, based on mode requirements
 748          *
 749          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 750          * To support the given mode:
 751          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 752          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 753          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 754          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 755          *                     (ModeClock / FEC Overhead)
 756          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 757          *                     (ModeClock / FEC Overhead * 8)
 758          */
 759         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 760                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 761
 762         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 763                                 "total bw %u pixel clock %u\n",
 764                                 bits_per_pixel, timeslots,
 765                                 (link_clock * lane_count * 8),
 766                                 intel_dp_mode_to_fec_clock(mode_clock));
 767
 768         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 769         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 770                 mode_hdisplay;
 771
 772         if (bigjoiner)
 773                 max_bpp_small_joiner_ram *= 2;
 774
 775         /*
 776          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 777          * check, output bpp from small joiner RAM check)
 778          */
 779         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 780
 781         if (bigjoiner) {
 782                 u32 max_bpp_bigjoiner =
 783                         i915->display.cdclk.max_cdclk_freq * 48 /
 784                         intel_dp_mode_to_fec_clock(mode_clock);
 785
 786                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 787         }
 788
 789         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 790
 791         /*
 792          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 793          * fractional part is 0
 794          */
 795         return bits_per_pixel << 4;
 796 }
 797
 798 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 799                                 int mode_clock, int mode_hdisplay,
 800                                 bool bigjoiner)
 801 {
 802         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 803         u8 min_slice_count, i;
 804         int max_slice_width;
 805
 806         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 807                 min_slice_count = DIV_ROUND_UP(mode_clock,
 808                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 809         else
 810                 min_slice_count = DIV_ROUND_UP(mode_clock,
 811                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 812
 813         /*
 814          * Due to some DSC engine BW limitations, we need to enable second
 815          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 816          */
 817         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 818                 min_slice_count = max_t(u8, min_slice_count, 2);
 819
 820         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 821         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 822                 drm_dbg_kms(&i915->drm,
 823                             "Unsupported slice width %d by DP DSC Sink device\n",
 824                             max_slice_width);
 825                 return 0;
 826         }
 827         /* Also take into account max slice width */
 828         min_slice_count = max_t(u8, min_slice_count,
 829                                 DIV_ROUND_UP(mode_hdisplay,
 830                                              max_slice_width));
 831
 832         /* Find the closest match to the valid slice count values */
 833         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 834                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 835
 836                 if (test_slice_count >
 837                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 838                         break;
 839
 840                 /* big joiner needs small joiner to be enabled */
 841                 if (bigjoiner && test_slice_count < 4)
 842                         continue;
 843
 844                 if (min_slice_count <= test_slice_count)
 845                         return test_slice_count;
 846         }
 847
 848         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 849                     min_slice_count);
 850         return 0;
 851 }
 852
 853 static bool source_can_output(struct intel_dp *intel_dp,
 854                               enum intel_output_format format)
 855 {
 856         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 857
 858         switch (format) {
 859         case INTEL_OUTPUT_FORMAT_RGB:
 860                 return true;
 861
 862         case INTEL_OUTPUT_FORMAT_YCBCR444:
 863                 /*
 864                  * No YCbCr output support on gmch platforms.
 865                  * Also, ILK doesn't seem capable of DP YCbCr output.
 866                  * The displayed image is severly corrupted. SNB+ is fine.
 867                  */
 868                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
 869
 870         case INTEL_OUTPUT_FORMAT_YCBCR420:
 871                 /* Platform < Gen 11 cannot output YCbCr420 format */
 872                 return DISPLAY_VER(i915) >= 11;
 873
 874         default:
 875                 MISSING_CASE(format);
 876                 return false;
 877         }
 878 }
 879
 880 static bool
 881 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
 882                          enum intel_output_format sink_format)
 883 {
 884         if (!drm_dp_is_branch(intel_dp->dpcd))
 885                 return false;
 886
 887         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 888                 return intel_dp->dfp.rgb_to_ycbcr;
 889
 890         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 891                 return intel_dp->dfp.rgb_to_ycbcr &&
 892                         intel_dp->dfp.ycbcr_444_to_420;
 893
 894         return false;
 895 }
 896
 897 static bool
 898 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
 899                               enum intel_output_format sink_format)
 900 {
 901         if (!drm_dp_is_branch(intel_dp->dpcd))
 902                 return false;
 903
 904         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 905                 return intel_dp->dfp.ycbcr_444_to_420;
 906
 907         return false;
 908 }
 909
 910 static enum intel_output_format
 911 intel_dp_output_format(struct intel_connector *connector,
 912                        enum intel_output_format sink_format)
 913 {
 914         struct intel_dp *intel_dp = intel_attached_dp(connector);
 915         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 916         enum intel_output_format output_format;
 917
 918         if (intel_dp->force_dsc_output_format)
 919                 return intel_dp->force_dsc_output_format;
 920
 921         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
 922             dfp_can_convert_from_rgb(intel_dp, sink_format))
 923                 output_format = INTEL_OUTPUT_FORMAT_RGB;
 924
 925         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
 926                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
 927                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
 928
 929         else
 930                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
 931
 932         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
 933
 934         return output_format;
 935 }
 936
 937 int intel_dp_min_bpp(enum intel_output_format output_format)
 938 {
 939         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 940                 return 6 * 3;
 941         else
 942                 return 8 * 3;
 943 }
 944
 945 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 946 {
 947         /*
 948          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 949          * format of the number of bytes per pixel will be half the number
 950          * of bytes of RGB pixel.
 951          */
 952         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 953                 bpp /= 2;
 954
 955         return bpp;
 956 }
 957
 958 static enum intel_output_format
 959 intel_dp_sink_format(struct intel_connector *connector,
 960                      const struct drm_display_mode *mode)
 961 {
 962         const struct drm_display_info *info = &connector->base.display_info;
 963
 964         if (drm_mode_is_420_only(info, mode))
 965                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 966
 967         return INTEL_OUTPUT_FORMAT_RGB;
 968 }
 969
 970 static int
 971 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 972                              const struct drm_display_mode *mode)
 973 {
 974         enum intel_output_format output_format, sink_format;
 975
 976         sink_format = intel_dp_sink_format(connector, mode);
 977
 978         output_format = intel_dp_output_format(connector, sink_format);
 979
 980         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 981 }
 982
 983 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 984                                   int hdisplay)
 985 {
 986         /*
 987          * Older platforms don't like hdisplay==4096 with DP.
 988          *
 989          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 990          * and frame counter increment), but we don't get vblank interrupts,
 991          * and the pipe underruns immediately. The link also doesn't seem
 992          * to get trained properly.
 993          *
 994          * On CHV the vblank interrupts don't seem to disappear but
 995          * otherwise the symptoms are similar.
 996          *
 997          * TODO: confirm the behaviour on HSW+
 998          */
 999         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1000 }
1001
1002 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1003 {
1004         struct intel_connector *connector = intel_dp->attached_connector;
1005         const struct drm_display_info *info = &connector->base.display_info;
1006         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1007
1008         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1009         if (max_tmds_clock && info->max_tmds_clock)
1010                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1011
1012         return max_tmds_clock;
1013 }
1014
1015 static enum drm_mode_status
1016 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1017                           int clock, int bpc,
1018                           enum intel_output_format sink_format,
1019                           bool respect_downstream_limits)
1020 {
1021         int tmds_clock, min_tmds_clock, max_tmds_clock;
1022
1023         if (!respect_downstream_limits)
1024                 return MODE_OK;
1025
1026         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1027
1028         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1029         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1030
1031         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1032                 return MODE_CLOCK_LOW;
1033
1034         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1035                 return MODE_CLOCK_HIGH;
1036
1037         return MODE_OK;
1038 }
1039
1040 static enum drm_mode_status
1041 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1042                                const struct drm_display_mode *mode,
1043                                int target_clock)
1044 {
1045         struct intel_dp *intel_dp = intel_attached_dp(connector);
1046         const struct drm_display_info *info = &connector->base.display_info;
1047         enum drm_mode_status status;
1048         enum intel_output_format sink_format;
1049
1050         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1051         if (intel_dp->dfp.pcon_max_frl_bw) {
1052                 int target_bw;
1053                 int max_frl_bw;
1054                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1055
1056                 target_bw = bpp * target_clock;
1057
1058                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1059
1060                 /* converting bw from Gbps to Kbps*/
1061                 max_frl_bw = max_frl_bw * 1000000;
1062
1063                 if (target_bw > max_frl_bw)
1064                         return MODE_CLOCK_HIGH;
1065
1066                 return MODE_OK;
1067         }
1068
1069         if (intel_dp->dfp.max_dotclock &&
1070             target_clock > intel_dp->dfp.max_dotclock)
1071                 return MODE_CLOCK_HIGH;
1072
1073         sink_format = intel_dp_sink_format(connector, mode);
1074
1075         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1076         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1077                                            8, sink_format, true);
1078
1079         if (status != MODE_OK) {
1080                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1081                     !connector->base.ycbcr_420_allowed ||
1082                     !drm_mode_is_420_also(info, mode))
1083                         return status;
1084                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1085                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1086                                                    8, sink_format, true);
1087                 if (status != MODE_OK)
1088                         return status;
1089         }
1090
1091         return MODE_OK;
1092 }
1093
1094 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1095                              int hdisplay, int clock)
1096 {
1097         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1098
1099         if (!intel_dp_can_bigjoiner(intel_dp))
1100                 return false;
1101
1102         return clock > i915->max_dotclk_freq || hdisplay > 5120;
1103 }
1104
1105 static enum drm_mode_status
1106 intel_dp_mode_valid(struct drm_connector *_connector,
1107                     struct drm_display_mode *mode)
1108 {
1109         struct intel_connector *connector = to_intel_connector(_connector);
1110         struct intel_dp *intel_dp = intel_attached_dp(connector);
1111         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1112         const struct drm_display_mode *fixed_mode;
1113         int target_clock = mode->clock;
1114         int max_rate, mode_rate, max_lanes, max_link_clock;
1115         int max_dotclk = dev_priv->max_dotclk_freq;
1116         u16 dsc_max_output_bpp = 0;
1117         u8 dsc_slice_count = 0;
1118         enum drm_mode_status status;
1119         bool dsc = false, bigjoiner = false;
1120
1121         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1122                 return MODE_H_ILLEGAL;
1123
1124         fixed_mode = intel_panel_fixed_mode(connector, mode);
1125         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1126                 status = intel_panel_mode_valid(connector, mode);
1127                 if (status != MODE_OK)
1128                         return status;
1129
1130                 target_clock = fixed_mode->clock;
1131         }
1132
1133         if (mode->clock < 10000)
1134                 return MODE_CLOCK_LOW;
1135
1136         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1137                 bigjoiner = true;
1138                 max_dotclk *= 2;
1139         }
1140         if (target_clock > max_dotclk)
1141                 return MODE_CLOCK_HIGH;
1142
1143         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1144                 return MODE_H_ILLEGAL;
1145
1146         max_link_clock = intel_dp_max_link_rate(intel_dp);
1147         max_lanes = intel_dp_max_lane_count(intel_dp);
1148
1149         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1150         mode_rate = intel_dp_link_required(target_clock,
1151                                            intel_dp_mode_min_output_bpp(connector, mode));
1152
1153         if (HAS_DSC(dev_priv) &&
1154             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1155                 /*
1156                  * TBD pass the connector BPC,
1157                  * for now U8_MAX so that max BPC on that platform would be picked
1158                  */
1159                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1160
1161                 /*
1162                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1163                  * integer value since we support only integer values of bpp.
1164                  */
1165                 if (intel_dp_is_edp(intel_dp)) {
1166                         dsc_max_output_bpp =
1167                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1168                         dsc_slice_count =
1169                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1170                                                                 true);
1171                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1172                         dsc_max_output_bpp =
1173                                 intel_dp_dsc_get_output_bpp(dev_priv,
1174                                                             max_link_clock,
1175                                                             max_lanes,
1176                                                             target_clock,
1177                                                             mode->hdisplay,
1178                                                             bigjoiner,
1179                                                             pipe_bpp, 64) >> 4;
1180                         dsc_slice_count =
1181                                 intel_dp_dsc_get_slice_count(intel_dp,
1182                                                              target_clock,
1183                                                              mode->hdisplay,
1184                                                              bigjoiner);
1185                 }
1186
1187                 dsc = dsc_max_output_bpp && dsc_slice_count;
1188         }
1189
1190         /*
1191          * Big joiner configuration needs DSC for TGL which is not true for
1192          * XE_LPD where uncompressed joiner is supported.
1193          */
1194         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1195                 return MODE_CLOCK_HIGH;
1196
1197         if (mode_rate > max_rate && !dsc)
1198                 return MODE_CLOCK_HIGH;
1199
1200         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1201         if (status != MODE_OK)
1202                 return status;
1203
1204         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1205 }
1206
1207 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1208 {
1209         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1210 }
1211
1212 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1213 {
1214         return DISPLAY_VER(i915) >= 10;
1215 }
1216
1217 static void snprintf_int_array(char *str, size_t len,
1218                                const int *array, int nelem)
1219 {
1220         int i;
1221
1222         str[0] = '\0';
1223
1224         for (i = 0; i < nelem; i++) {
1225                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1226                 if (r >= len)
1227                         return;
1228                 str += r;
1229                 len -= r;
1230         }
1231 }
1232
1233 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1234 {
1235         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1236         char str[128]; /* FIXME: too big for stack? */
1237
1238         if (!drm_debug_enabled(DRM_UT_KMS))
1239                 return;
1240
1241         snprintf_int_array(str, sizeof(str),
1242                            intel_dp->source_rates, intel_dp->num_source_rates);
1243         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1244
1245         snprintf_int_array(str, sizeof(str),
1246                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1247         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1248
1249         snprintf_int_array(str, sizeof(str),
1250                            intel_dp->common_rates, intel_dp->num_common_rates);
1251         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1252 }
1253
1254 int
1255 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1256 {
1257         int len;
1258
1259         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1260
1261         return intel_dp_common_rate(intel_dp, len - 1);
1262 }
1263
1264 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1265 {
1266         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1267         int i = intel_dp_rate_index(intel_dp->sink_rates,
1268                                     intel_dp->num_sink_rates, rate);
1269
1270         if (drm_WARN_ON(&i915->drm, i < 0))
1271                 i = 0;
1272
1273         return i;
1274 }
1275
1276 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1277                            u8 *link_bw, u8 *rate_select)
1278 {
1279         /* eDP 1.4 rate select method. */
1280         if (intel_dp->use_rate_select) {
1281                 *link_bw = 0;
1282                 *rate_select =
1283                         intel_dp_rate_select(intel_dp, port_clock);
1284         } else {
1285                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1286                 *rate_select = 0;
1287         }
1288 }
1289
1290 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1291                                          const struct intel_crtc_state *pipe_config)
1292 {
1293         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1294
1295         /* On TGL, FEC is supported on all Pipes */
1296         if (DISPLAY_VER(dev_priv) >= 12)
1297                 return true;
1298
1299         if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1300                 return true;
1301
1302         return false;
1303 }
1304
1305 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1306                                   const struct intel_crtc_state *pipe_config)
1307 {
1308         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1309                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1310 }
1311
1312 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1313                                   const struct intel_crtc_state *crtc_state)
1314 {
1315         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1316                 return false;
1317
1318         return intel_dsc_source_support(crtc_state) &&
1319                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1320 }
1321
1322 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1323                                      const struct intel_crtc_state *crtc_state,
1324                                      int bpc, bool respect_downstream_limits)
1325 {
1326         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1327
1328         /*
1329          * Current bpc could already be below 8bpc due to
1330          * FDI bandwidth constraints or other limits.
1331          * HDMI minimum is 8bpc however.
1332          */
1333         bpc = max(bpc, 8);
1334
1335         /*
1336          * We will never exceed downstream TMDS clock limits while
1337          * attempting deep color. If the user insists on forcing an
1338          * out of spec mode they will have to be satisfied with 8bpc.
1339          */
1340         if (!respect_downstream_limits)
1341                 bpc = 8;
1342
1343         for (; bpc >= 8; bpc -= 2) {
1344                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1345                                             intel_dp->has_hdmi_sink) &&
1346                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1347                                               respect_downstream_limits) == MODE_OK)
1348                         return bpc;
1349         }
1350
1351         return -EINVAL;
1352 }
1353
1354 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1355                             const struct intel_crtc_state *crtc_state,
1356                             bool respect_downstream_limits)
1357 {
1358         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1359         struct intel_connector *intel_connector = intel_dp->attached_connector;
1360         int bpp, bpc;
1361
1362         bpc = crtc_state->pipe_bpp / 3;
1363
1364         if (intel_dp->dfp.max_bpc)
1365                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1366
1367         if (intel_dp->dfp.min_tmds_clock) {
1368                 int max_hdmi_bpc;
1369
1370                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1371                                                          respect_downstream_limits);
1372                 if (max_hdmi_bpc < 0)
1373                         return 0;
1374
1375                 bpc = min(bpc, max_hdmi_bpc);
1376         }
1377
1378         bpp = bpc * 3;
1379         if (intel_dp_is_edp(intel_dp)) {
1380                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1381                 if (intel_connector->base.display_info.bpc == 0 &&
1382                     intel_connector->panel.vbt.edp.bpp &&
1383                     intel_connector->panel.vbt.edp.bpp < bpp) {
1384                         drm_dbg_kms(&dev_priv->drm,
1385                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1386                                     intel_connector->panel.vbt.edp.bpp);
1387                         bpp = intel_connector->panel.vbt.edp.bpp;
1388                 }
1389         }
1390
1391         return bpp;
1392 }
1393
1394 /* Adjust link config limits based on compliance test requests. */
1395 void
1396 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1397                                   struct intel_crtc_state *pipe_config,
1398                                   struct link_config_limits *limits)
1399 {
1400         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1401
1402         /* For DP Compliance we override the computed bpp for the pipe */
1403         if (intel_dp->compliance.test_data.bpc != 0) {
1404                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1405
1406                 limits->min_bpp = limits->max_bpp = bpp;
1407                 pipe_config->dither_force_disable = bpp == 6 * 3;
1408
1409                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1410         }
1411
1412         /* Use values requested by Compliance Test Request */
1413         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1414                 int index;
1415
1416                 /* Validate the compliance test data since max values
1417                  * might have changed due to link train fallback.
1418                  */
1419                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1420                                                intel_dp->compliance.test_lane_count)) {
1421                         index = intel_dp_rate_index(intel_dp->common_rates,
1422                                                     intel_dp->num_common_rates,
1423                                                     intel_dp->compliance.test_link_rate);
1424                         if (index >= 0)
1425                                 limits->min_rate = limits->max_rate =
1426                                         intel_dp->compliance.test_link_rate;
1427                         limits->min_lane_count = limits->max_lane_count =
1428                                 intel_dp->compliance.test_lane_count;
1429                 }
1430         }
1431 }
1432
1433 static bool has_seamless_m_n(struct intel_connector *connector)
1434 {
1435         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1436
1437         /*
1438          * Seamless M/N reprogramming only implemented
1439          * for BDW+ double buffered M/N registers so far.
1440          */
1441         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1442                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1443 }
1444
1445 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1446                                const struct drm_connector_state *conn_state)
1447 {
1448         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1449         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1450
1451         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1452         if (has_seamless_m_n(connector))
1453                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1454         else
1455                 return adjusted_mode->crtc_clock;
1456 }
1457
1458 /* Optimize link config in order: max bpp, min clock, min lanes */
1459 static int
1460 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1461                                   struct intel_crtc_state *pipe_config,
1462                                   const struct drm_connector_state *conn_state,
1463                                   const struct link_config_limits *limits)
1464 {
1465         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1466         int mode_rate, link_rate, link_avail;
1467
1468         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1469                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1470
1471                 mode_rate = intel_dp_link_required(clock, output_bpp);
1472
1473                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1474                         link_rate = intel_dp_common_rate(intel_dp, i);
1475                         if (link_rate < limits->min_rate ||
1476                             link_rate > limits->max_rate)
1477                                 continue;
1478
1479                         for (lane_count = limits->min_lane_count;
1480                              lane_count <= limits->max_lane_count;
1481                              lane_count <<= 1) {
1482                                 link_avail = intel_dp_max_data_rate(link_rate,
1483                                                                     lane_count);
1484
1485                                 if (mode_rate <= link_avail) {
1486                                         pipe_config->lane_count = lane_count;
1487                                         pipe_config->pipe_bpp = bpp;
1488                                         pipe_config->port_clock = link_rate;
1489
1490                                         return 0;
1491                                 }
1492                         }
1493                 }
1494         }
1495
1496         return -EINVAL;
1497 }
1498
1499 int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1500 {
1501         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1502         int i, num_bpc;
1503         u8 dsc_bpc[3] = {0};
1504         u8 dsc_max_bpc;
1505
1506         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1507         if (DISPLAY_VER(i915) >= 12)
1508                 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1509         else
1510                 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1511
1512         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1513                                                        dsc_bpc);
1514         for (i = 0; i < num_bpc; i++) {
1515                 if (dsc_max_bpc >= dsc_bpc[i])
1516                         return dsc_bpc[i] * 3;
1517         }
1518
1519         return 0;
1520 }
1521
1522 static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
1523 {
1524         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1525
1526         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1527 }
1528
1529 static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
1530 {
1531         return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1532                 DP_DSC_MINOR_SHIFT;
1533 }
1534
1535 static int intel_dp_get_slice_height(int vactive)
1536 {
1537         int slice_height;
1538
1539         /*
1540          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1541          * lines is an optimal slice height, but any size can be used as long as
1542          * vertical active integer multiple and maximum vertical slice count
1543          * requirements are met.
1544          */
1545         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1546                 if (vactive % slice_height == 0)
1547                         return slice_height;
1548
1549         /*
1550          * Highly unlikely we reach here as most of the resolutions will end up
1551          * finding appropriate slice_height in above loop but returning
1552          * slice_height as 2 here as it should work with all resolutions.
1553          */
1554         return 2;
1555 }
1556
1557 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1558                                        struct intel_crtc_state *crtc_state)
1559 {
1560         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1561         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1562         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1563         u8 line_buf_depth;
1564         int ret;
1565
1566         /*
1567          * RC_MODEL_SIZE is currently a constant across all configurations.
1568          *
1569          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1570          * DP_DSC_RC_BUF_SIZE for this.
1571          */
1572         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1573         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1574
1575         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1576
1577         ret = intel_dsc_compute_params(crtc_state);
1578         if (ret)
1579                 return ret;
1580
1581         vdsc_cfg->dsc_version_major =
1582                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1583                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1584         vdsc_cfg->dsc_version_minor =
1585                 min(intel_dp_source_dsc_version_minor(intel_dp),
1586                     intel_dp_sink_dsc_version_minor(intel_dp));
1587         if (vdsc_cfg->convert_rgb)
1588                 vdsc_cfg->convert_rgb =
1589                         intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1590                         DP_DSC_RGB;
1591
1592         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1593         if (!line_buf_depth) {
1594                 drm_dbg_kms(&i915->drm,
1595                             "DSC Sink Line Buffer Depth invalid\n");
1596                 return -EINVAL;
1597         }
1598
1599         if (vdsc_cfg->dsc_version_minor == 2)
1600                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1601                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1602         else
1603                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1604                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1605
1606         vdsc_cfg->block_pred_enable =
1607                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1608                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1609
1610         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1611 }
1612
1613 static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
1614                                          enum intel_output_format output_format)
1615 {
1616         u8 sink_dsc_format;
1617
1618         switch (output_format) {
1619         case INTEL_OUTPUT_FORMAT_RGB:
1620                 sink_dsc_format = DP_DSC_RGB;
1621                 break;
1622         case INTEL_OUTPUT_FORMAT_YCBCR444:
1623                 sink_dsc_format = DP_DSC_YCbCr444;
1624                 break;
1625         case INTEL_OUTPUT_FORMAT_YCBCR420:
1626                 if (min(intel_dp_source_dsc_version_minor(intel_dp),
1627                         intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
1628                         return false;
1629                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1630                 break;
1631         default:
1632                 return false;
1633         }
1634
1635         return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
1636 }
1637
1638 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1639                                 struct intel_crtc_state *pipe_config,
1640                                 struct drm_connector_state *conn_state,
1641                                 struct link_config_limits *limits,
1642                                 int timeslots,
1643                                 bool compute_pipe_bpp)
1644 {
1645         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1646         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1647         const struct drm_display_mode *adjusted_mode =
1648                 &pipe_config->hw.adjusted_mode;
1649         int pipe_bpp;
1650         int ret;
1651
1652         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1653                 intel_dp_supports_fec(intel_dp, pipe_config);
1654
1655         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1656                 return -EINVAL;
1657
1658         if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
1659                 return -EINVAL;
1660
1661         if (compute_pipe_bpp)
1662                 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1663         else
1664                 pipe_bpp = pipe_config->pipe_bpp;
1665
1666         if (intel_dp->force_dsc_bpc) {
1667                 pipe_bpp = intel_dp->force_dsc_bpc * 3;
1668                 drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
1669         }
1670
1671         /* Min Input BPC for ICL+ is 8 */
1672         if (pipe_bpp < 8 * 3) {
1673                 drm_dbg_kms(&dev_priv->drm,
1674                             "No DSC support for less than 8bpc\n");
1675                 return -EINVAL;
1676         }
1677
1678         /*
1679          * For now enable DSC for max bpp, max link rate, max lane count.
1680          * Optimize this later for the minimum possible link rate/lane count
1681          * with DSC enabled for the requested mode.
1682          */
1683         pipe_config->pipe_bpp = pipe_bpp;
1684         pipe_config->port_clock = limits->max_rate;
1685         pipe_config->lane_count = limits->max_lane_count;
1686
1687         if (intel_dp_is_edp(intel_dp)) {
1688                 pipe_config->dsc.compressed_bpp =
1689                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1690                               pipe_config->pipe_bpp);
1691                 pipe_config->dsc.slice_count =
1692                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1693                                                         true);
1694                 if (!pipe_config->dsc.slice_count) {
1695                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
1696                                     pipe_config->dsc.slice_count);
1697                         return -EINVAL;
1698                 }
1699         } else {
1700                 u16 dsc_max_output_bpp = 0;
1701                 u8 dsc_dp_slice_count;
1702
1703                 if (compute_pipe_bpp) {
1704                         dsc_max_output_bpp =
1705                                 intel_dp_dsc_get_output_bpp(dev_priv,
1706                                                             pipe_config->port_clock,
1707                                                             pipe_config->lane_count,
1708                                                             adjusted_mode->crtc_clock,
1709                                                             adjusted_mode->crtc_hdisplay,
1710                                                             pipe_config->bigjoiner_pipes,
1711                                                             pipe_bpp,
1712                                                             timeslots);
1713                         /*
1714                          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
1715                          * supported PPS value can be 63.9375 and with the further
1716                          * mention that bpp should be programmed double the target bpp
1717                          * restricting our target bpp to be 31.9375 at max
1718                          */
1719                         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1720                                 dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
1721
1722                         if (!dsc_max_output_bpp) {
1723                                 drm_dbg_kms(&dev_priv->drm,
1724                                             "Compressed BPP not supported\n");
1725                                 return -EINVAL;
1726                         }
1727                 }
1728                 dsc_dp_slice_count =
1729                         intel_dp_dsc_get_slice_count(intel_dp,
1730                                                      adjusted_mode->crtc_clock,
1731                                                      adjusted_mode->crtc_hdisplay,
1732                                                      pipe_config->bigjoiner_pipes);
1733                 if (!dsc_dp_slice_count) {
1734                         drm_dbg_kms(&dev_priv->drm,
1735                                     "Compressed Slice Count not supported\n");
1736                         return -EINVAL;
1737                 }
1738
1739                 /*
1740                  * compute pipe bpp is set to false for DP MST DSC case
1741                  * and compressed_bpp is calculated same time once
1742                  * vpci timeslots are allocated, because overall bpp
1743                  * calculation procedure is bit different for MST case.
1744                  */
1745                 if (compute_pipe_bpp) {
1746                         pipe_config->dsc.compressed_bpp = min_t(u16,
1747                                                                 dsc_max_output_bpp >> 4,
1748                                                                 pipe_config->pipe_bpp);
1749                 }
1750                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1751                 drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
1752                             pipe_config->dsc.compressed_bpp,
1753                             pipe_config->dsc.slice_count);
1754         }
1755         /*
1756          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1757          * is greater than the maximum Cdclock and if slice count is even
1758          * then we need to use 2 VDSC instances.
1759          */
1760         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
1761                 pipe_config->dsc.dsc_split = true;
1762
1763         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1764         if (ret < 0) {
1765                 drm_dbg_kms(&dev_priv->drm,
1766                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1767                             "Compressed BPP = %d\n",
1768                             pipe_config->pipe_bpp,
1769                             pipe_config->dsc.compressed_bpp);
1770                 return ret;
1771         }
1772
1773         pipe_config->dsc.compression_enable = true;
1774         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1775                     "Compressed Bpp = %d Slice Count = %d\n",
1776                     pipe_config->pipe_bpp,
1777                     pipe_config->dsc.compressed_bpp,
1778                     pipe_config->dsc.slice_count);
1779
1780         return 0;
1781 }
1782
1783 static int
1784 intel_dp_compute_link_config(struct intel_encoder *encoder,
1785                              struct intel_crtc_state *pipe_config,
1786                              struct drm_connector_state *conn_state,
1787                              bool respect_downstream_limits)
1788 {
1789         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1790         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1791         const struct drm_display_mode *adjusted_mode =
1792                 &pipe_config->hw.adjusted_mode;
1793         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1794         struct link_config_limits limits;
1795         bool joiner_needs_dsc = false;
1796         int ret;
1797
1798         limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1799         limits.max_rate = intel_dp_max_link_rate(intel_dp);
1800
1801         limits.min_lane_count = 1;
1802         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1803
1804         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1805         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1806
1807         if (intel_dp->use_max_params) {
1808                 /*
1809                  * Use the maximum clock and number of lanes the eDP panel
1810                  * advertizes being capable of in case the initial fast
1811                  * optimal params failed us. The panels are generally
1812                  * designed to support only a single clock and lane
1813                  * configuration, and typically on older panels these
1814                  * values correspond to the native resolution of the panel.
1815                  */
1816                 limits.min_lane_count = limits.max_lane_count;
1817                 limits.min_rate = limits.max_rate;
1818         }
1819
1820         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1821
1822         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1823                     "max rate %d max bpp %d pixel clock %iKHz\n",
1824                     limits.max_lane_count, limits.max_rate,
1825                     limits.max_bpp, adjusted_mode->crtc_clock);
1826
1827         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1828                                     adjusted_mode->crtc_clock))
1829                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1830
1831         /*
1832          * Pipe joiner needs compression up to display 12 due to bandwidth
1833          * limitation. DG2 onwards pipe joiner can be enabled without
1834          * compression.
1835          */
1836         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1837
1838         /*
1839          * Optimize for slow and wide for everything, because there are some
1840          * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1841          */
1842         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
1843
1844         if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1845                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1846                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1847                             str_yes_no(intel_dp->force_dsc_en));
1848                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1849                                                   conn_state, &limits, 64, true);
1850                 if (ret < 0)
1851                         return ret;
1852         }
1853
1854         if (pipe_config->dsc.compression_enable) {
1855                 drm_dbg_kms(&i915->drm,
1856                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1857                             pipe_config->lane_count, pipe_config->port_clock,
1858                             pipe_config->pipe_bpp,
1859                             pipe_config->dsc.compressed_bpp);
1860
1861                 drm_dbg_kms(&i915->drm,
1862                             "DP link rate required %i available %i\n",
1863                             intel_dp_link_required(adjusted_mode->crtc_clock,
1864                                                    pipe_config->dsc.compressed_bpp),
1865                             intel_dp_max_data_rate(pipe_config->port_clock,
1866                                                    pipe_config->lane_count));
1867         } else {
1868                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1869                             pipe_config->lane_count, pipe_config->port_clock,
1870                             pipe_config->pipe_bpp);
1871
1872                 drm_dbg_kms(&i915->drm,
1873                             "DP link rate required %i available %i\n",
1874                             intel_dp_link_required(adjusted_mode->crtc_clock,
1875                                                    pipe_config->pipe_bpp),
1876                             intel_dp_max_data_rate(pipe_config->port_clock,
1877                                                    pipe_config->lane_count));
1878         }
1879         return 0;
1880 }
1881
1882 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1883                                   const struct drm_connector_state *conn_state)
1884 {
1885         const struct intel_digital_connector_state *intel_conn_state =
1886                 to_intel_digital_connector_state(conn_state);
1887         const struct drm_display_mode *adjusted_mode =
1888                 &crtc_state->hw.adjusted_mode;
1889
1890         /*
1891          * Our YCbCr output is always limited range.
1892          * crtc_state->limited_color_range only applies to RGB,
1893          * and it must never be set for YCbCr or we risk setting
1894          * some conflicting bits in TRANSCONF which will mess up
1895          * the colors on the monitor.
1896          */
1897         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1898                 return false;
1899
1900         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1901                 /*
1902                  * See:
1903                  * CEA-861-E - 5.1 Default Encoding Parameters
1904                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1905                  */
1906                 return crtc_state->pipe_bpp != 18 &&
1907                         drm_default_rgb_quant_range(adjusted_mode) ==
1908                         HDMI_QUANTIZATION_RANGE_LIMITED;
1909         } else {
1910                 return intel_conn_state->broadcast_rgb ==
1911                         INTEL_BROADCAST_RGB_LIMITED;
1912         }
1913 }
1914
1915 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1916                                     enum port port)
1917 {
1918         if (IS_G4X(dev_priv))
1919                 return false;
1920         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1921                 return false;
1922
1923         return true;
1924 }
1925
1926 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1927                                              const struct drm_connector_state *conn_state,
1928                                              struct drm_dp_vsc_sdp *vsc)
1929 {
1930         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1931         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1932
1933         /*
1934          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1935          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1936          * Colorimetry Format indication.
1937          */
1938         vsc->revision = 0x5;
1939         vsc->length = 0x13;
1940
1941         /* DP 1.4a spec, Table 2-120 */
1942         switch (crtc_state->output_format) {
1943         case INTEL_OUTPUT_FORMAT_YCBCR444:
1944                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1945                 break;
1946         case INTEL_OUTPUT_FORMAT_YCBCR420:
1947                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1948                 break;
1949         case INTEL_OUTPUT_FORMAT_RGB:
1950         default:
1951                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1952         }
1953
1954         switch (conn_state->colorspace) {
1955         case DRM_MODE_COLORIMETRY_BT709_YCC:
1956                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1957                 break;
1958         case DRM_MODE_COLORIMETRY_XVYCC_601:
1959                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1960                 break;
1961         case DRM_MODE_COLORIMETRY_XVYCC_709:
1962                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1963                 break;
1964         case DRM_MODE_COLORIMETRY_SYCC_601:
1965                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1966                 break;
1967         case DRM_MODE_COLORIMETRY_OPYCC_601:
1968                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1969                 break;
1970         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1971                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1972                 break;
1973         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1974                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1975                 break;
1976         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1977                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1978                 break;
1979         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1980         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1981                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1982                 break;
1983         default:
1984                 /*
1985                  * RGB->YCBCR color conversion uses the BT.709
1986                  * color space.
1987                  */
1988                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1989                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1990                 else
1991                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1992                 break;
1993         }
1994
1995         vsc->bpc = crtc_state->pipe_bpp / 3;
1996
1997         /* only RGB pixelformat supports 6 bpc */
1998         drm_WARN_ON(&dev_priv->drm,
1999                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2000
2001         /* all YCbCr are always limited range */
2002         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2003         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2004 }
2005
2006 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2007                                      struct intel_crtc_state *crtc_state,
2008                                      const struct drm_connector_state *conn_state)
2009 {
2010         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2011
2012         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2013         if (crtc_state->has_psr)
2014                 return;
2015
2016         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2017                 return;
2018
2019         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2020         vsc->sdp_type = DP_SDP_VSC;
2021         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2022                                          &crtc_state->infoframes.vsc);
2023 }
2024
2025 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2026                                   const struct intel_crtc_state *crtc_state,
2027                                   const struct drm_connector_state *conn_state,
2028                                   struct drm_dp_vsc_sdp *vsc)
2029 {
2030         vsc->sdp_type = DP_SDP_VSC;
2031
2032         if (crtc_state->has_psr2) {
2033                 if (intel_dp->psr.colorimetry_support &&
2034                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2035                         /* [PSR2, +Colorimetry] */
2036                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2037                                                          vsc);
2038                 } else {
2039                         /*
2040                          * [PSR2, -Colorimetry]
2041                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2042                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2043                          */
2044                         vsc->revision = 0x4;
2045                         vsc->length = 0xe;
2046                 }
2047         } else {
2048                 /*
2049                  * [PSR1]
2050                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2051                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2052                  * higher).
2053                  */
2054                 vsc->revision = 0x2;
2055                 vsc->length = 0x8;
2056         }
2057 }
2058
2059 static void
2060 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2061                                             struct intel_crtc_state *crtc_state,
2062                                             const struct drm_connector_state *conn_state)
2063 {
2064         int ret;
2065         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2066         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2067
2068         if (!conn_state->hdr_output_metadata)
2069                 return;
2070
2071         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2072
2073         if (ret) {
2074                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2075                 return;
2076         }
2077
2078         crtc_state->infoframes.enable |=
2079                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2080 }
2081
2082 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2083                                     enum transcoder cpu_transcoder)
2084 {
2085         if (HAS_DOUBLE_BUFFERED_M_N(i915))
2086                 return true;
2087
2088         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2089 }
2090
2091 static bool can_enable_drrs(struct intel_connector *connector,
2092                             const struct intel_crtc_state *pipe_config,
2093                             const struct drm_display_mode *downclock_mode)
2094 {
2095         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2096
2097         if (pipe_config->vrr.enable)
2098                 return false;
2099
2100         /*
2101          * DRRS and PSR can't be enable together, so giving preference to PSR
2102          * as it allows more power-savings by complete shutting down display,
2103          * so to guarantee this, intel_drrs_compute_config() must be called
2104          * after intel_psr_compute_config().
2105          */
2106         if (pipe_config->has_psr)
2107                 return false;
2108
2109         /* FIXME missing FDI M2/N2 etc. */
2110         if (pipe_config->has_pch_encoder)
2111                 return false;
2112
2113         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2114                 return false;
2115
2116         return downclock_mode &&
2117                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2118 }
2119
2120 static void
2121 intel_dp_drrs_compute_config(struct intel_connector *connector,
2122                              struct intel_crtc_state *pipe_config,
2123                              int output_bpp)
2124 {
2125         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2126         const struct drm_display_mode *downclock_mode =
2127                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2128         int pixel_clock;
2129
2130         if (has_seamless_m_n(connector))
2131                 pipe_config->seamless_m_n = true;
2132
2133         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2134                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2135                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2136                 return;
2137         }
2138
2139         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2140                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2141
2142         pipe_config->has_drrs = true;
2143
2144         pixel_clock = downclock_mode->clock;
2145         if (pipe_config->splitter.enable)
2146                 pixel_clock /= pipe_config->splitter.link_count;
2147
2148         intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
2149                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2150                                pipe_config->fec_enable);
2151
2152         /* FIXME: abstract this better */
2153         if (pipe_config->splitter.enable)
2154                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2155 }
2156
2157 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2158                                const struct drm_connector_state *conn_state)
2159 {
2160         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2161         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2162         struct intel_connector *connector = intel_dp->attached_connector;
2163         const struct intel_digital_connector_state *intel_conn_state =
2164                 to_intel_digital_connector_state(conn_state);
2165
2166         if (!intel_dp_port_has_audio(i915, encoder->port))
2167                 return false;
2168
2169         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2170                 return connector->base.display_info.has_audio;
2171         else
2172                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2173 }
2174
2175 static int
2176 intel_dp_compute_output_format(struct intel_encoder *encoder,
2177                                struct intel_crtc_state *crtc_state,
2178                                struct drm_connector_state *conn_state,
2179                                bool respect_downstream_limits)
2180 {
2181         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2182         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2183         struct intel_connector *connector = intel_dp->attached_connector;
2184         const struct drm_display_info *info = &connector->base.display_info;
2185         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2186         bool ycbcr_420_only;
2187         int ret;
2188
2189         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2190
2191         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2192                 drm_dbg_kms(&i915->drm,
2193                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2194                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2195         } else {
2196                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2197         }
2198
2199         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2200
2201         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2202                                            respect_downstream_limits);
2203         if (ret) {
2204                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2205                     !connector->base.ycbcr_420_allowed ||
2206                     !drm_mode_is_420_also(info, adjusted_mode))
2207                         return ret;
2208
2209                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2210                 crtc_state->output_format = intel_dp_output_format(connector,
2211                                                                    crtc_state->sink_format);
2212                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2213                                                    respect_downstream_limits);
2214         }
2215
2216         return ret;
2217 }
2218
2219 static void
2220 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2221                               struct intel_crtc_state *pipe_config,
2222                               struct drm_connector_state *conn_state)
2223 {
2224         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2225         struct drm_connector *connector = conn_state->connector;
2226
2227         pipe_config->sdp_split_enable =
2228                 intel_dp_has_audio(encoder, conn_state) &&
2229                 intel_dp_is_uhbr(pipe_config);
2230
2231         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
2232                     connector->base.id, connector->name,
2233                     str_yes_no(pipe_config->sdp_split_enable));
2234 }
2235
2236 int
2237 intel_dp_compute_config(struct intel_encoder *encoder,
2238                         struct intel_crtc_state *pipe_config,
2239                         struct drm_connector_state *conn_state)
2240 {
2241         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2242         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2243         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2244         const struct drm_display_mode *fixed_mode;
2245         struct intel_connector *connector = intel_dp->attached_connector;
2246         int ret = 0, output_bpp;
2247
2248         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2249                 pipe_config->has_pch_encoder = true;
2250
2251         pipe_config->has_audio =
2252                 intel_dp_has_audio(encoder, conn_state) &&
2253                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2254
2255         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2256         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2257                 ret = intel_panel_compute_config(connector, adjusted_mode);
2258                 if (ret)
2259                         return ret;
2260         }
2261
2262         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2263                 return -EINVAL;
2264
2265         if (!connector->base.interlace_allowed &&
2266             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2267                 return -EINVAL;
2268
2269         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2270                 return -EINVAL;
2271
2272         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2273                 return -EINVAL;
2274
2275         /*
2276          * Try to respect downstream TMDS clock limits first, if
2277          * that fails assume the user might know something we don't.
2278          */
2279         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2280         if (ret)
2281                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2282         if (ret)
2283                 return ret;
2284
2285         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2286             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2287                 ret = intel_panel_fitting(pipe_config, conn_state);
2288                 if (ret)
2289                         return ret;
2290         }
2291
2292         pipe_config->limited_color_range =
2293                 intel_dp_limited_color_range(pipe_config, conn_state);
2294
2295         if (pipe_config->dsc.compression_enable)
2296                 output_bpp = pipe_config->dsc.compressed_bpp;
2297         else
2298                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2299                                                  pipe_config->pipe_bpp);
2300
2301         if (intel_dp->mso_link_count) {
2302                 int n = intel_dp->mso_link_count;
2303                 int overlap = intel_dp->mso_pixel_overlap;
2304
2305                 pipe_config->splitter.enable = true;
2306                 pipe_config->splitter.link_count = n;
2307                 pipe_config->splitter.pixel_overlap = overlap;
2308
2309                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2310                             n, overlap);
2311
2312                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2313                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2314                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2315                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2316                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2317                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2318                 adjusted_mode->crtc_clock /= n;
2319         }
2320
2321         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2322
2323         intel_link_compute_m_n(output_bpp,
2324                                pipe_config->lane_count,
2325                                adjusted_mode->crtc_clock,
2326                                pipe_config->port_clock,
2327                                &pipe_config->dp_m_n,
2328                                pipe_config->fec_enable);
2329
2330         /* FIXME: abstract this better */
2331         if (pipe_config->splitter.enable)
2332                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2333
2334         if (!HAS_DDI(dev_priv))
2335                 g4x_dp_set_clock(encoder, pipe_config);
2336
2337         intel_vrr_compute_config(pipe_config, conn_state);
2338         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2339         intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2340         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2341         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2342
2343         return 0;
2344 }
2345
2346 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2347                               int link_rate, int lane_count)
2348 {
2349         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2350         intel_dp->link_trained = false;
2351         intel_dp->link_rate = link_rate;
2352         intel_dp->lane_count = lane_count;
2353 }
2354
2355 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2356 {
2357         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2358         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2359 }
2360
2361 /* Enable backlight PWM and backlight PP control. */
2362 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2363                             const struct drm_connector_state *conn_state)
2364 {
2365         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2366         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2367
2368         if (!intel_dp_is_edp(intel_dp))
2369                 return;
2370
2371         drm_dbg_kms(&i915->drm, "\n");
2372
2373         intel_backlight_enable(crtc_state, conn_state);
2374         intel_pps_backlight_on(intel_dp);
2375 }
2376
2377 /* Disable backlight PP control and backlight PWM. */
2378 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2379 {
2380         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2381         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2382
2383         if (!intel_dp_is_edp(intel_dp))
2384                 return;
2385
2386         drm_dbg_kms(&i915->drm, "\n");
2387
2388         intel_pps_backlight_off(intel_dp);
2389         intel_backlight_disable(old_conn_state);
2390 }
2391
2392 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2393 {
2394         /*
2395          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2396          * be capable of signalling downstream hpd with a long pulse.
2397          * Whether or not that means D3 is safe to use is not clear,
2398          * but let's assume so until proven otherwise.
2399          *
2400          * FIXME should really check all downstream ports...
2401          */
2402         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2403                 drm_dp_is_branch(intel_dp->dpcd) &&
2404                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2405 }
2406
2407 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2408                                            const struct intel_crtc_state *crtc_state,
2409                                            bool enable)
2410 {
2411         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2412         int ret;
2413
2414         if (!crtc_state->dsc.compression_enable)
2415                 return;
2416
2417         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2418                                  enable ? DP_DECOMPRESSION_EN : 0);
2419         if (ret < 0)
2420                 drm_dbg_kms(&i915->drm,
2421                             "Failed to %s sink decompression state\n",
2422                             str_enable_disable(enable));
2423 }
2424
2425 static void
2426 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2427 {
2428         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2429         u8 oui[] = { 0x00, 0xaa, 0x01 };
2430         u8 buf[3] = { 0 };
2431
2432         /*
2433          * During driver init, we want to be careful and avoid changing the source OUI if it's
2434          * already set to what we want, so as to avoid clearing any state by accident
2435          */
2436         if (careful) {
2437                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2438                         drm_err(&i915->drm, "Failed to read source OUI\n");
2439
2440                 if (memcmp(oui, buf, sizeof(oui)) == 0)
2441                         return;
2442         }
2443
2444         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2445                 drm_err(&i915->drm, "Failed to write source OUI\n");
2446
2447         intel_dp->last_oui_write = jiffies;
2448 }
2449
2450 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2451 {
2452         struct intel_connector *connector = intel_dp->attached_connector;
2453         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2454
2455         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
2456                     connector->base.base.id, connector->base.name,
2457                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2458
2459         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
2460                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2461 }
2462
2463 /* If the device supports it, try to set the power state appropriately */
2464 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2465 {
2466         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2467         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2468         int ret, i;
2469
2470         /* Should have a valid DPCD by this point */
2471         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2472                 return;
2473
2474         if (mode != DP_SET_POWER_D0) {
2475                 if (downstream_hpd_needs_d0(intel_dp))
2476                         return;
2477
2478                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2479         } else {
2480                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2481
2482                 lspcon_resume(dp_to_dig_port(intel_dp));
2483
2484                 /* Write the source OUI as early as possible */
2485                 if (intel_dp_is_edp(intel_dp))
2486                         intel_edp_init_source_oui(intel_dp, false);
2487
2488                 /*
2489                  * When turning on, we need to retry for 1ms to give the sink
2490                  * time to wake up.
2491                  */
2492                 for (i = 0; i < 3; i++) {
2493                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2494                         if (ret == 1)
2495                                 break;
2496                         msleep(1);
2497                 }
2498
2499                 if (ret == 1 && lspcon->active)
2500                         lspcon_wait_pcon_mode(lspcon);
2501         }
2502
2503         if (ret != 1)
2504                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2505                             encoder->base.base.id, encoder->base.name,
2506                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
2507 }
2508
2509 static bool
2510 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2511
2512 /**
2513  * intel_dp_sync_state - sync the encoder state during init/resume
2514  * @encoder: intel encoder to sync
2515  * @crtc_state: state for the CRTC connected to the encoder
2516  *
2517  * Sync any state stored in the encoder wrt. HW state during driver init
2518  * and system resume.
2519  */
2520 void intel_dp_sync_state(struct intel_encoder *encoder,
2521                          const struct intel_crtc_state *crtc_state)
2522 {
2523         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2524
2525         if (!crtc_state)
2526                 return;
2527
2528         /*
2529          * Don't clobber DPCD if it's been already read out during output
2530          * setup (eDP) or detect.
2531          */
2532         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2533                 intel_dp_get_dpcd(intel_dp);
2534
2535         intel_dp_reset_max_link_params(intel_dp);
2536 }
2537
2538 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2539                                     struct intel_crtc_state *crtc_state)
2540 {
2541         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2542         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2543         bool fastset = true;
2544
2545         /*
2546          * If BIOS has set an unsupported or non-standard link rate for some
2547          * reason force an encoder recompute and full modeset.
2548          */
2549         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2550                                 crtc_state->port_clock) < 0) {
2551                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
2552                             encoder->base.base.id, encoder->base.name);
2553                 crtc_state->uapi.connectors_changed = true;
2554                 fastset = false;
2555         }
2556
2557         /*
2558          * FIXME hack to force full modeset when DSC is being used.
2559          *
2560          * As long as we do not have full state readout and config comparison
2561          * of crtc_state->dsc, we have no way to ensure reliable fastset.
2562          * Remove once we have readout for DSC.
2563          */
2564         if (crtc_state->dsc.compression_enable) {
2565                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
2566                             encoder->base.base.id, encoder->base.name);
2567                 crtc_state->uapi.mode_changed = true;
2568                 fastset = false;
2569         }
2570
2571         if (CAN_PSR(intel_dp)) {
2572                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
2573                             encoder->base.base.id, encoder->base.name);
2574                 crtc_state->uapi.mode_changed = true;
2575                 fastset = false;
2576         }
2577
2578         return fastset;
2579 }
2580
2581 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2582 {
2583         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2584
2585         /* Clear the cached register set to avoid using stale values */
2586
2587         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2588
2589         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2590                              intel_dp->pcon_dsc_dpcd,
2591                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2592                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2593                         DP_PCON_DSC_ENCODER);
2594
2595         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2596                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2597 }
2598
2599 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2600 {
2601         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2602         int i;
2603
2604         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2605                 if (frl_bw_mask & (1 << i))
2606                         return bw_gbps[i];
2607         }
2608         return 0;
2609 }
2610
2611 static int intel_dp_pcon_set_frl_mask(int max_frl)
2612 {
2613         switch (max_frl) {
2614         case 48:
2615                 return DP_PCON_FRL_BW_MASK_48GBPS;
2616         case 40:
2617                 return DP_PCON_FRL_BW_MASK_40GBPS;
2618         case 32:
2619                 return DP_PCON_FRL_BW_MASK_32GBPS;
2620         case 24:
2621                 return DP_PCON_FRL_BW_MASK_24GBPS;
2622         case 18:
2623                 return DP_PCON_FRL_BW_MASK_18GBPS;
2624         case 9:
2625                 return DP_PCON_FRL_BW_MASK_9GBPS;
2626         }
2627
2628         return 0;
2629 }
2630
2631 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2632 {
2633         struct intel_connector *intel_connector = intel_dp->attached_connector;
2634         struct drm_connector *connector = &intel_connector->base;
2635         int max_frl_rate;
2636         int max_lanes, rate_per_lane;
2637         int max_dsc_lanes, dsc_rate_per_lane;
2638
2639         max_lanes = connector->display_info.hdmi.max_lanes;
2640         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2641         max_frl_rate = max_lanes * rate_per_lane;
2642
2643         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2644                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2645                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2646                 if (max_dsc_lanes && dsc_rate_per_lane)
2647                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2648         }
2649
2650         return max_frl_rate;
2651 }
2652
2653 static bool
2654 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2655                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
2656 {
2657         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2658             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2659             *frl_trained_mask >= max_frl_bw_mask)
2660                 return true;
2661
2662         return false;
2663 }
2664
2665 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2666 {
2667 #define TIMEOUT_FRL_READY_MS 500
2668 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2669
2670         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2671         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2672         u8 max_frl_bw_mask = 0, frl_trained_mask;
2673         bool is_active;
2674
2675         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2676         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2677
2678         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2679         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2680
2681         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2682
2683         if (max_frl_bw <= 0)
2684                 return -EINVAL;
2685
2686         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2687         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2688
2689         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2690                 goto frl_trained;
2691
2692         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2693         if (ret < 0)
2694                 return ret;
2695         /* Wait for PCON to be FRL Ready */
2696         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2697
2698         if (!is_active)
2699                 return -ETIMEDOUT;
2700
2701         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2702                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2703         if (ret < 0)
2704                 return ret;
2705         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2706                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2707         if (ret < 0)
2708                 return ret;
2709         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2710         if (ret < 0)
2711                 return ret;
2712         /*
2713          * Wait for FRL to be completed
2714          * Check if the HDMI Link is up and active.
2715          */
2716         wait_for(is_active =
2717                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2718                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
2719
2720         if (!is_active)
2721                 return -ETIMEDOUT;
2722
2723 frl_trained:
2724         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2725         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2726         intel_dp->frl.is_trained = true;
2727         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2728
2729         return 0;
2730 }
2731
2732 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2733 {
2734         if (drm_dp_is_branch(intel_dp->dpcd) &&
2735             intel_dp->has_hdmi_sink &&
2736             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2737                 return true;
2738
2739         return false;
2740 }
2741
2742 static
2743 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2744 {
2745         int ret;
2746         u8 buf = 0;
2747
2748         /* Set PCON source control mode */
2749         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2750
2751         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2752         if (ret < 0)
2753                 return ret;
2754
2755         /* Set HDMI LINK ENABLE */
2756         buf |= DP_PCON_ENABLE_HDMI_LINK;
2757         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2758         if (ret < 0)
2759                 return ret;
2760
2761         return 0;
2762 }
2763
2764 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2765 {
2766         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2767
2768         /*
2769          * Always go for FRL training if:
2770          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2771          * -sink is HDMI2.1
2772          */
2773         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2774             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2775             intel_dp->frl.is_trained)
2776                 return;
2777
2778         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2779                 int ret, mode;
2780
2781                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2782                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2783                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2784
2785                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2786                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2787         } else {
2788                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2789         }
2790 }
2791
2792 static int
2793 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2794 {
2795         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2796
2797         return intel_hdmi_dsc_get_slice_height(vactive);
2798 }
2799
2800 static int
2801 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2802                              const struct intel_crtc_state *crtc_state)
2803 {
2804         struct intel_connector *intel_connector = intel_dp->attached_connector;
2805         struct drm_connector *connector = &intel_connector->base;
2806         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2807         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2808         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2809         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2810
2811         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2812                                              pcon_max_slice_width,
2813                                              hdmi_max_slices, hdmi_throughput);
2814 }
2815
2816 static int
2817 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2818                           const struct intel_crtc_state *crtc_state,
2819                           int num_slices, int slice_width)
2820 {
2821         struct intel_connector *intel_connector = intel_dp->attached_connector;
2822         struct drm_connector *connector = &intel_connector->base;
2823         int output_format = crtc_state->output_format;
2824         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2825         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2826         int hdmi_max_chunk_bytes =
2827                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2828
2829         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2830                                       num_slices, output_format, hdmi_all_bpp,
2831                                       hdmi_max_chunk_bytes);
2832 }
2833
2834 void
2835 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2836                             const struct intel_crtc_state *crtc_state)
2837 {
2838         u8 pps_param[6];
2839         int slice_height;
2840         int slice_width;
2841         int num_slices;
2842         int bits_per_pixel;
2843         int ret;
2844         struct intel_connector *intel_connector = intel_dp->attached_connector;
2845         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2846         struct drm_connector *connector;
2847         bool hdmi_is_dsc_1_2;
2848
2849         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2850                 return;
2851
2852         if (!intel_connector)
2853                 return;
2854         connector = &intel_connector->base;
2855         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2856
2857         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2858             !hdmi_is_dsc_1_2)
2859                 return;
2860
2861         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2862         if (!slice_height)
2863                 return;
2864
2865         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2866         if (!num_slices)
2867                 return;
2868
2869         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2870                                    num_slices);
2871
2872         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2873                                                    num_slices, slice_width);
2874         if (!bits_per_pixel)
2875                 return;
2876
2877         pps_param[0] = slice_height & 0xFF;
2878         pps_param[1] = slice_height >> 8;
2879         pps_param[2] = slice_width & 0xFF;
2880         pps_param[3] = slice_width >> 8;
2881         pps_param[4] = bits_per_pixel & 0xFF;
2882         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2883
2884         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2885         if (ret < 0)
2886                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2887 }
2888
2889 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2890                                            const struct intel_crtc_state *crtc_state)
2891 {
2892         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2893         bool ycbcr444_to_420 = false;
2894         bool rgb_to_ycbcr = false;
2895         u8 tmp;
2896
2897         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2898                 return;
2899
2900         if (!drm_dp_is_branch(intel_dp->dpcd))
2901                 return;
2902
2903         tmp = intel_dp->has_hdmi_sink ?
2904                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2905
2906         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2907                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2908                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2909                             str_enable_disable(intel_dp->has_hdmi_sink));
2910
2911         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2912                 switch (crtc_state->output_format) {
2913                 case INTEL_OUTPUT_FORMAT_YCBCR420:
2914                         break;
2915                 case INTEL_OUTPUT_FORMAT_YCBCR444:
2916                         ycbcr444_to_420 = true;
2917                         break;
2918                 case INTEL_OUTPUT_FORMAT_RGB:
2919                         rgb_to_ycbcr = true;
2920                         ycbcr444_to_420 = true;
2921                         break;
2922                 default:
2923                         MISSING_CASE(crtc_state->output_format);
2924                         break;
2925                 }
2926         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
2927                 switch (crtc_state->output_format) {
2928                 case INTEL_OUTPUT_FORMAT_YCBCR444:
2929                         break;
2930                 case INTEL_OUTPUT_FORMAT_RGB:
2931                         rgb_to_ycbcr = true;
2932                         break;
2933                 default:
2934                         MISSING_CASE(crtc_state->output_format);
2935                         break;
2936                 }
2937         }
2938
2939         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2940
2941         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2942                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2943                 drm_dbg_kms(&i915->drm,
2944                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2945                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2946
2947         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2948
2949         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2950                 drm_dbg_kms(&i915->drm,
2951                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2952                             str_enable_disable(tmp));
2953 }
2954
2955 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2956 {
2957         u8 dprx = 0;
2958
2959         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2960                               &dprx) != 1)
2961                 return false;
2962         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2963 }
2964
2965 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2966 {
2967         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2968
2969         /*
2970          * Clear the cached register set to avoid using stale values
2971          * for the sinks that do not support DSC.
2972          */
2973         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2974
2975         /* Clear fec_capable to avoid using stale values */
2976         intel_dp->fec_capable = 0;
2977
2978         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2979         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2980             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2981                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2982                                      intel_dp->dsc_dpcd,
2983                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2984                         drm_err(&i915->drm,
2985                                 "Failed to read DPCD register 0x%x\n",
2986                                 DP_DSC_SUPPORT);
2987
2988                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2989                             (int)sizeof(intel_dp->dsc_dpcd),
2990                             intel_dp->dsc_dpcd);
2991
2992                 /* FEC is supported only on DP 1.4 */
2993                 if (!intel_dp_is_edp(intel_dp) &&
2994                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2995                                       &intel_dp->fec_capable) < 0)
2996                         drm_err(&i915->drm,
2997                                 "Failed to read FEC DPCD register\n");
2998
2999                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3000                             intel_dp->fec_capable);
3001         }
3002 }
3003
3004 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3005                                      struct drm_display_mode *mode)
3006 {
3007         struct intel_dp *intel_dp = intel_attached_dp(connector);
3008         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3009         int n = intel_dp->mso_link_count;
3010         int overlap = intel_dp->mso_pixel_overlap;
3011
3012         if (!mode || !n)
3013                 return;
3014
3015         mode->hdisplay = (mode->hdisplay - overlap) * n;
3016         mode->hsync_start = (mode->hsync_start - overlap) * n;
3017         mode->hsync_end = (mode->hsync_end - overlap) * n;
3018         mode->htotal = (mode->htotal - overlap) * n;
3019         mode->clock *= n;
3020
3021         drm_mode_set_name(mode);
3022
3023         drm_dbg_kms(&i915->drm,
3024                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3025                     connector->base.base.id, connector->base.name,
3026                     DRM_MODE_ARG(mode));
3027 }
3028
3029 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3030 {
3031         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3032         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3033         struct intel_connector *connector = intel_dp->attached_connector;
3034
3035         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3036                 /*
3037                  * This is a big fat ugly hack.
3038                  *
3039                  * Some machines in UEFI boot mode provide us a VBT that has 18
3040                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3041                  * unknown we fail to light up. Yet the same BIOS boots up with
3042                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3043                  * max, not what it tells us to use.
3044                  *
3045                  * Note: This will still be broken if the eDP panel is not lit
3046                  * up by the BIOS, and thus we can't get the mode at module
3047                  * load.
3048                  */
3049                 drm_dbg_kms(&dev_priv->drm,
3050                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3051                             pipe_bpp, connector->panel.vbt.edp.bpp);
3052                 connector->panel.vbt.edp.bpp = pipe_bpp;
3053         }
3054 }
3055
3056 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3057 {
3058         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3059         struct intel_connector *connector = intel_dp->attached_connector;
3060         struct drm_display_info *info = &connector->base.display_info;
3061         u8 mso;
3062
3063         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3064                 return;
3065
3066         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3067                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3068                 return;
3069         }
3070
3071         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3072         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3073         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3074                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3075                 mso = 0;
3076         }
3077
3078         if (mso) {
3079                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3080                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3081                             info->mso_pixel_overlap);
3082                 if (!HAS_MSO(i915)) {
3083                         drm_err(&i915->drm, "No source MSO support, disabling\n");
3084                         mso = 0;
3085                 }
3086         }
3087
3088         intel_dp->mso_link_count = mso;
3089         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3090 }
3091
3092 static bool
3093 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3094 {
3095         struct drm_i915_private *dev_priv =
3096                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3097
3098         /* this function is meant to be called only once */
3099         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3100
3101         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3102                 return false;
3103
3104         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3105                          drm_dp_is_branch(intel_dp->dpcd));
3106
3107         /*
3108          * Read the eDP display control registers.
3109          *
3110          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3111          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3112          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3113          * method). The display control registers should read zero if they're
3114          * not supported anyway.
3115          */
3116         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3117                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3118                              sizeof(intel_dp->edp_dpcd)) {
3119                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3120                             (int)sizeof(intel_dp->edp_dpcd),
3121                             intel_dp->edp_dpcd);
3122
3123                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3124         }
3125
3126         /*
3127          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3128          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3129          */
3130         intel_psr_init_dpcd(intel_dp);
3131
3132         /* Clear the default sink rates */
3133         intel_dp->num_sink_rates = 0;
3134
3135         /* Read the eDP 1.4+ supported link rates. */
3136         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3137                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3138                 int i;
3139
3140                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3141                                 sink_rates, sizeof(sink_rates));
3142
3143                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3144                         int val = le16_to_cpu(sink_rates[i]);
3145
3146                         if (val == 0)
3147                                 break;
3148
3149                         /* Value read multiplied by 200kHz gives the per-lane
3150                          * link rate in kHz. The source rates are, however,
3151                          * stored in terms of LS_Clk kHz. The full conversion
3152                          * back to symbols is
3153                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3154                          */
3155                         intel_dp->sink_rates[i] = (val * 200) / 10;
3156                 }
3157                 intel_dp->num_sink_rates = i;
3158         }
3159
3160         /*
3161          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3162          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3163          */
3164         if (intel_dp->num_sink_rates)
3165                 intel_dp->use_rate_select = true;
3166         else
3167                 intel_dp_set_sink_rates(intel_dp);
3168         intel_dp_set_max_sink_lane_count(intel_dp);
3169
3170         /* Read the eDP DSC DPCD registers */
3171         if (HAS_DSC(dev_priv))
3172                 intel_dp_get_dsc_sink_cap(intel_dp);
3173
3174         /*
3175          * If needed, program our source OUI so we can make various Intel-specific AUX services
3176          * available (such as HDR backlight controls)
3177          */
3178         intel_edp_init_source_oui(intel_dp, true);
3179
3180         return true;
3181 }
3182
3183 static bool
3184 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3185 {
3186         if (!intel_dp->attached_connector)
3187                 return false;
3188
3189         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3190                                           intel_dp->dpcd,
3191                                           &intel_dp->desc);
3192 }
3193
3194 static bool
3195 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3196 {
3197         int ret;
3198
3199         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3200                 return false;
3201
3202         /*
3203          * Don't clobber cached eDP rates. Also skip re-reading
3204          * the OUI/ID since we know it won't change.
3205          */
3206         if (!intel_dp_is_edp(intel_dp)) {
3207                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3208                                  drm_dp_is_branch(intel_dp->dpcd));
3209
3210                 intel_dp_set_sink_rates(intel_dp);
3211                 intel_dp_set_max_sink_lane_count(intel_dp);
3212                 intel_dp_set_common_rates(intel_dp);
3213         }
3214
3215         if (intel_dp_has_sink_count(intel_dp)) {
3216                 ret = drm_dp_read_sink_count(&intel_dp->aux);
3217                 if (ret < 0)
3218                         return false;
3219
3220                 /*
3221                  * Sink count can change between short pulse hpd hence
3222                  * a member variable in intel_dp will track any changes
3223                  * between short pulse interrupts.
3224                  */
3225                 intel_dp->sink_count = ret;
3226
3227                 /*
3228                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3229                  * a dongle is present but no display. Unless we require to know
3230                  * if a dongle is present or not, we don't need to update
3231                  * downstream port information. So, an early return here saves
3232                  * time from performing other operations which are not required.
3233                  */
3234                 if (!intel_dp->sink_count)
3235                         return false;
3236         }
3237
3238         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
3239                                            intel_dp->downstream_ports) == 0;
3240 }
3241
3242 static bool
3243 intel_dp_can_mst(struct intel_dp *intel_dp)
3244 {
3245         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3246
3247         return i915->params.enable_dp_mst &&
3248                 intel_dp_mst_source_support(intel_dp) &&
3249                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3250 }
3251
3252 static void
3253 intel_dp_configure_mst(struct intel_dp *intel_dp)
3254 {
3255         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3256         struct intel_encoder *encoder =
3257                 &dp_to_dig_port(intel_dp)->base;
3258         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3259
3260         drm_dbg_kms(&i915->drm,
3261                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3262                     encoder->base.base.id, encoder->base.name,
3263                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
3264                     str_yes_no(sink_can_mst),
3265                     str_yes_no(i915->params.enable_dp_mst));
3266
3267         if (!intel_dp_mst_source_support(intel_dp))
3268                 return;
3269
3270         intel_dp->is_mst = sink_can_mst &&
3271                 i915->params.enable_dp_mst;
3272
3273         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3274                                         intel_dp->is_mst);
3275 }
3276
3277 static bool
3278 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3279 {
3280         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3281 }
3282
3283 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3284 {
3285         int retry;
3286
3287         for (retry = 0; retry < 3; retry++) {
3288                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3289                                       &esi[1], 3) == 3)
3290                         return true;
3291         }
3292
3293         return false;
3294 }
3295
3296 bool
3297 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3298                        const struct drm_connector_state *conn_state)
3299 {
3300         /*
3301          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3302          * of Color Encoding Format and Content Color Gamut], in order to
3303          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3304          */
3305         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3306                 return true;
3307
3308         switch (conn_state->colorspace) {
3309         case DRM_MODE_COLORIMETRY_SYCC_601:
3310         case DRM_MODE_COLORIMETRY_OPYCC_601:
3311         case DRM_MODE_COLORIMETRY_BT2020_YCC:
3312         case DRM_MODE_COLORIMETRY_BT2020_RGB:
3313         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3314                 return true;
3315         default:
3316                 break;
3317         }
3318
3319         return false;
3320 }
3321
3322 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3323                                      struct dp_sdp *sdp, size_t size)
3324 {
3325         size_t length = sizeof(struct dp_sdp);
3326
3327         if (size < length)
3328                 return -ENOSPC;
3329
3330         memset(sdp, 0, size);
3331
3332         /*
3333          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3334          * VSC SDP Header Bytes
3335          */
3336         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3337         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3338         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3339         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3340
3341         /*
3342          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3343          * per DP 1.4a spec.
3344          */
3345         if (vsc->revision != 0x5)
3346                 goto out;
3347
3348         /* VSC SDP Payload for DB16 through DB18 */
3349         /* Pixel Encoding and Colorimetry Formats  */
3350         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3351         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3352
3353         switch (vsc->bpc) {
3354         case 6:
3355                 /* 6bpc: 0x0 */
3356                 break;
3357         case 8:
3358                 sdp->db[17] = 0x1; /* DB17[3:0] */
3359                 break;
3360         case 10:
3361                 sdp->db[17] = 0x2;
3362                 break;
3363         case 12:
3364                 sdp->db[17] = 0x3;
3365                 break;
3366         case 16:
3367                 sdp->db[17] = 0x4;
3368                 break;
3369         default:
3370                 MISSING_CASE(vsc->bpc);
3371                 break;
3372         }
3373         /* Dynamic Range and Component Bit Depth */
3374         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3375                 sdp->db[17] |= 0x80;  /* DB17[7] */
3376
3377         /* Content Type */
3378         sdp->db[18] = vsc->content_type & 0x7;
3379
3380 out:
3381         return length;
3382 }
3383
3384 static ssize_t
3385 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3386                                          const struct hdmi_drm_infoframe *drm_infoframe,
3387                                          struct dp_sdp *sdp,
3388                                          size_t size)
3389 {
3390         size_t length = sizeof(struct dp_sdp);
3391         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3392         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3393         ssize_t len;
3394
3395         if (size < length)
3396                 return -ENOSPC;
3397
3398         memset(sdp, 0, size);
3399
3400         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3401         if (len < 0) {
3402                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3403                 return -ENOSPC;
3404         }
3405
3406         if (len != infoframe_size) {
3407                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3408                 return -ENOSPC;
3409         }
3410
3411         /*
3412          * Set up the infoframe sdp packet for HDR static metadata.
3413          * Prepare VSC Header for SU as per DP 1.4a spec,
3414          * Table 2-100 and Table 2-101
3415          */
3416
3417         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3418         sdp->sdp_header.HB0 = 0;
3419         /*
3420          * Packet Type 80h + Non-audio INFOFRAME Type value
3421          * HDMI_INFOFRAME_TYPE_DRM: 0x87
3422          * - 80h + Non-audio INFOFRAME Type value
3423          * - InfoFrame Type: 0x07
3424          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3425          */
3426         sdp->sdp_header.HB1 = drm_infoframe->type;
3427         /*
3428          * Least Significant Eight Bits of (Data Byte Count – 1)
3429          * infoframe_size - 1
3430          */
3431         sdp->sdp_header.HB2 = 0x1D;
3432         /* INFOFRAME SDP Version Number */
3433         sdp->sdp_header.HB3 = (0x13 << 2);
3434         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3435         sdp->db[0] = drm_infoframe->version;
3436         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3437         sdp->db[1] = drm_infoframe->length;
3438         /*
3439          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3440          * HDMI_INFOFRAME_HEADER_SIZE
3441          */
3442         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3443         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3444                HDMI_DRM_INFOFRAME_SIZE);
3445
3446         /*
3447          * Size of DP infoframe sdp packet for HDR static metadata consists of
3448          * - DP SDP Header(struct dp_sdp_header): 4 bytes
3449          * - Two Data Blocks: 2 bytes
3450          *    CTA Header Byte2 (INFOFRAME Version Number)
3451          *    CTA Header Byte3 (Length of INFOFRAME)
3452          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3453          *
3454          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3455          * infoframe size. But GEN11+ has larger than that size, write_infoframe
3456          * will pad rest of the size.
3457          */
3458         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3459 }
3460
3461 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3462                                const struct intel_crtc_state *crtc_state,
3463                                unsigned int type)
3464 {
3465         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3466         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3467         struct dp_sdp sdp = {};
3468         ssize_t len;
3469
3470         if ((crtc_state->infoframes.enable &
3471              intel_hdmi_infoframe_enable(type)) == 0)
3472                 return;
3473
3474         switch (type) {
3475         case DP_SDP_VSC:
3476                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3477                                             sizeof(sdp));
3478                 break;
3479         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3480                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3481                                                                &crtc_state->infoframes.drm.drm,
3482                                                                &sdp, sizeof(sdp));
3483                 break;
3484         default:
3485                 MISSING_CASE(type);
3486                 return;
3487         }
3488
3489         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3490                 return;
3491
3492         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3493 }
3494
3495 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3496                             const struct intel_crtc_state *crtc_state,
3497                             const struct drm_dp_vsc_sdp *vsc)
3498 {
3499         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3500         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3501         struct dp_sdp sdp = {};
3502         ssize_t len;
3503
3504         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3505
3506         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3507                 return;
3508
3509         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3510                                         &sdp, len);
3511 }
3512
3513 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3514                              bool enable,
3515                              const struct intel_crtc_state *crtc_state,
3516                              const struct drm_connector_state *conn_state)
3517 {
3518         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3519         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3520         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3521                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3522                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3523         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3524
3525         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3526         /* When PSR is enabled, this routine doesn't disable VSC DIP */
3527         if (!crtc_state->has_psr)
3528                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3529
3530         intel_de_write(dev_priv, reg, val);
3531         intel_de_posting_read(dev_priv, reg);
3532
3533         if (!enable)
3534                 return;
3535
3536         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3537         if (!crtc_state->has_psr)
3538                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3539
3540         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3541 }
3542
3543 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3544                                    const void *buffer, size_t size)
3545 {
3546         const struct dp_sdp *sdp = buffer;
3547
3548         if (size < sizeof(struct dp_sdp))
3549                 return -EINVAL;
3550
3551         memset(vsc, 0, sizeof(*vsc));
3552
3553         if (sdp->sdp_header.HB0 != 0)
3554                 return -EINVAL;
3555
3556         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3557                 return -EINVAL;
3558
3559         vsc->sdp_type = sdp->sdp_header.HB1;
3560         vsc->revision = sdp->sdp_header.HB2;
3561         vsc->length = sdp->sdp_header.HB3;
3562
3563         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3564             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3565                 /*
3566                  * - HB2 = 0x2, HB3 = 0x8
3567                  *   VSC SDP supporting 3D stereo + PSR
3568                  * - HB2 = 0x4, HB3 = 0xe
3569                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3570                  *   first scan line of the SU region (applies to eDP v1.4b
3571                  *   and higher).
3572                  */
3573                 return 0;
3574         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3575                 /*
3576                  * - HB2 = 0x5, HB3 = 0x13
3577                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3578                  *   Format.
3579                  */
3580                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3581                 vsc->colorimetry = sdp->db[16] & 0xf;
3582                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3583
3584                 switch (sdp->db[17] & 0x7) {
3585                 case 0x0:
3586                         vsc->bpc = 6;
3587                         break;
3588                 case 0x1:
3589                         vsc->bpc = 8;
3590                         break;
3591                 case 0x2:
3592                         vsc->bpc = 10;
3593                         break;
3594                 case 0x3:
3595                         vsc->bpc = 12;
3596                         break;
3597                 case 0x4:
3598                         vsc->bpc = 16;
3599                         break;
3600                 default:
3601                         MISSING_CASE(sdp->db[17] & 0x7);
3602                         return -EINVAL;
3603                 }
3604
3605                 vsc->content_type = sdp->db[18] & 0x7;
3606         } else {
3607                 return -EINVAL;
3608         }
3609
3610         return 0;
3611 }
3612
3613 static int
3614 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3615                                            const void *buffer, size_t size)
3616 {
3617         int ret;
3618
3619         const struct dp_sdp *sdp = buffer;
3620
3621         if (size < sizeof(struct dp_sdp))
3622                 return -EINVAL;
3623
3624         if (sdp->sdp_header.HB0 != 0)
3625                 return -EINVAL;
3626
3627         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3628                 return -EINVAL;
3629
3630         /*
3631          * Least Significant Eight Bits of (Data Byte Count – 1)
3632          * 1Dh (i.e., Data Byte Count = 30 bytes).
3633          */
3634         if (sdp->sdp_header.HB2 != 0x1D)
3635                 return -EINVAL;
3636
3637         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3638         if ((sdp->sdp_header.HB3 & 0x3) != 0)
3639                 return -EINVAL;
3640
3641         /* INFOFRAME SDP Version Number */
3642         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3643                 return -EINVAL;
3644
3645         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3646         if (sdp->db[0] != 1)
3647                 return -EINVAL;
3648
3649         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3650         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3651                 return -EINVAL;
3652
3653         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3654                                              HDMI_DRM_INFOFRAME_SIZE);
3655
3656         return ret;
3657 }
3658
3659 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3660                                   struct intel_crtc_state *crtc_state,
3661                                   struct drm_dp_vsc_sdp *vsc)
3662 {
3663         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3664         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3665         unsigned int type = DP_SDP_VSC;
3666         struct dp_sdp sdp = {};
3667         int ret;
3668
3669         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3670         if (crtc_state->has_psr)
3671                 return;
3672
3673         if ((crtc_state->infoframes.enable &
3674              intel_hdmi_infoframe_enable(type)) == 0)
3675                 return;
3676
3677         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3678
3679         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3680
3681         if (ret)
3682                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3683 }
3684
3685 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3686                                                      struct intel_crtc_state *crtc_state,
3687                                                      struct hdmi_drm_infoframe *drm_infoframe)
3688 {
3689         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3690         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3691         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3692         struct dp_sdp sdp = {};
3693         int ret;
3694
3695         if ((crtc_state->infoframes.enable &
3696             intel_hdmi_infoframe_enable(type)) == 0)
3697                 return;
3698
3699         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3700                                  sizeof(sdp));
3701
3702         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3703                                                          sizeof(sdp));
3704
3705         if (ret)
3706                 drm_dbg_kms(&dev_priv->drm,
3707                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3708 }
3709
3710 void intel_read_dp_sdp(struct intel_encoder *encoder,
3711                        struct intel_crtc_state *crtc_state,
3712                        unsigned int type)
3713 {
3714         switch (type) {
3715         case DP_SDP_VSC:
3716                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3717                                       &crtc_state->infoframes.vsc);
3718                 break;
3719         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3720                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3721                                                          &crtc_state->infoframes.drm.drm);
3722                 break;
3723         default:
3724                 MISSING_CASE(type);
3725                 break;
3726         }
3727 }
3728
3729 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3730 {
3731         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3732         int status = 0;
3733         int test_link_rate;
3734         u8 test_lane_count, test_link_bw;
3735         /* (DP CTS 1.2)
3736          * 4.3.1.11
3737          */
3738         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3739         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3740                                    &test_lane_count);
3741
3742         if (status <= 0) {
3743                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3744                 return DP_TEST_NAK;
3745         }
3746         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3747
3748         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3749                                    &test_link_bw);
3750         if (status <= 0) {
3751                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3752                 return DP_TEST_NAK;
3753         }
3754         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3755
3756         /* Validate the requested link rate and lane count */
3757         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3758                                         test_lane_count))
3759                 return DP_TEST_NAK;
3760
3761         intel_dp->compliance.test_lane_count = test_lane_count;
3762         intel_dp->compliance.test_link_rate = test_link_rate;
3763
3764         return DP_TEST_ACK;
3765 }
3766
3767 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3768 {
3769         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3770         u8 test_pattern;
3771         u8 test_misc;
3772         __be16 h_width, v_height;
3773         int status = 0;
3774
3775         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3776         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3777                                    &test_pattern);
3778         if (status <= 0) {
3779                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3780                 return DP_TEST_NAK;
3781         }
3782         if (test_pattern != DP_COLOR_RAMP)
3783                 return DP_TEST_NAK;
3784
3785         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3786                                   &h_width, 2);
3787         if (status <= 0) {
3788                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3789                 return DP_TEST_NAK;
3790         }
3791
3792         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3793                                   &v_height, 2);
3794         if (status <= 0) {
3795                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3796                 return DP_TEST_NAK;
3797         }
3798
3799         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3800                                    &test_misc);
3801         if (status <= 0) {
3802                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3803                 return DP_TEST_NAK;
3804         }
3805         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3806                 return DP_TEST_NAK;
3807         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3808                 return DP_TEST_NAK;
3809         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3810         case DP_TEST_BIT_DEPTH_6:
3811                 intel_dp->compliance.test_data.bpc = 6;
3812                 break;
3813         case DP_TEST_BIT_DEPTH_8:
3814                 intel_dp->compliance.test_data.bpc = 8;
3815                 break;
3816         default:
3817                 return DP_TEST_NAK;
3818         }
3819
3820         intel_dp->compliance.test_data.video_pattern = test_pattern;
3821         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3822         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3823         /* Set test active flag here so userspace doesn't interrupt things */
3824         intel_dp->compliance.test_active = true;
3825
3826         return DP_TEST_ACK;
3827 }
3828
3829 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3830 {
3831         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3832         u8 test_result = DP_TEST_ACK;
3833         struct intel_connector *intel_connector = intel_dp->attached_connector;
3834         struct drm_connector *connector = &intel_connector->base;
3835
3836         if (intel_connector->detect_edid == NULL ||
3837             connector->edid_corrupt ||
3838             intel_dp->aux.i2c_defer_count > 6) {
3839                 /* Check EDID read for NACKs, DEFERs and corruption
3840                  * (DP CTS 1.2 Core r1.1)
3841                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3842                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3843                  *    4.2.2.6 : EDID corruption detected
3844                  * Use failsafe mode for all cases
3845                  */
3846                 if (intel_dp->aux.i2c_nack_count > 0 ||
3847                         intel_dp->aux.i2c_defer_count > 0)
3848                         drm_dbg_kms(&i915->drm,
3849                                     "EDID read had %d NACKs, %d DEFERs\n",
3850                                     intel_dp->aux.i2c_nack_count,
3851                                     intel_dp->aux.i2c_defer_count);
3852                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3853         } else {
3854                 /* FIXME: Get rid of drm_edid_raw() */
3855                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
3856
3857                 /* We have to write the checksum of the last block read */
3858                 block += block->extensions;
3859
3860                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3861                                        block->checksum) <= 0)
3862                         drm_dbg_kms(&i915->drm,
3863                                     "Failed to write EDID checksum\n");
3864
3865                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3866                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3867         }
3868
3869         /* Set test active flag here so userspace doesn't interrupt things */
3870         intel_dp->compliance.test_active = true;
3871
3872         return test_result;
3873 }
3874
3875 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3876                                         const struct intel_crtc_state *crtc_state)
3877 {
3878         struct drm_i915_private *dev_priv =
3879                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3880         struct drm_dp_phy_test_params *data =
3881                         &intel_dp->compliance.test_data.phytest;
3882         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3883         enum pipe pipe = crtc->pipe;
3884         u32 pattern_val;
3885
3886         switch (data->phy_pattern) {
3887         case DP_PHY_TEST_PATTERN_NONE:
3888                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3889                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3890                 break;
3891         case DP_PHY_TEST_PATTERN_D10_2:
3892                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3893                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3894                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3895                 break;
3896         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3897                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3898                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3899                                DDI_DP_COMP_CTL_ENABLE |
3900                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3901                 break;
3902         case DP_PHY_TEST_PATTERN_PRBS7:
3903                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3904                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3905                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3906                 break;
3907         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3908                 /*
3909                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3910                  * current firmware of DPR-100 could not set it, so hardcoding
3911                  * now for complaince test.
3912                  */
3913                 drm_dbg_kms(&dev_priv->drm,
3914                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3915                 pattern_val = 0x3e0f83e0;
3916                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3917                 pattern_val = 0x0f83e0f8;
3918                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3919                 pattern_val = 0x0000f83e;
3920                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3921                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3922                                DDI_DP_COMP_CTL_ENABLE |
3923                                DDI_DP_COMP_CTL_CUSTOM80);
3924                 break;
3925         case DP_PHY_TEST_PATTERN_CP2520:
3926                 /*
3927                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3928                  * current firmware of DPR-100 could not set it, so hardcoding
3929                  * now for complaince test.
3930                  */
3931                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3932                 pattern_val = 0xFB;
3933                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3934                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3935                                pattern_val);
3936                 break;
3937         default:
3938                 WARN(1, "Invalid Phy Test Pattern\n");
3939         }
3940 }
3941
3942 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3943                                          const struct intel_crtc_state *crtc_state)
3944 {
3945         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3946         struct drm_dp_phy_test_params *data =
3947                 &intel_dp->compliance.test_data.phytest;
3948         u8 link_status[DP_LINK_STATUS_SIZE];
3949
3950         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3951                                              link_status) < 0) {
3952                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3953                 return;
3954         }
3955
3956         /* retrieve vswing & pre-emphasis setting */
3957         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3958                                   link_status);
3959
3960         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3961
3962         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3963
3964         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3965                           intel_dp->train_set, crtc_state->lane_count);
3966
3967         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3968                                     link_status[DP_DPCD_REV]);
3969 }
3970
3971 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3972 {
3973         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3974         struct drm_dp_phy_test_params *data =
3975                 &intel_dp->compliance.test_data.phytest;
3976
3977         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3978                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3979                 return DP_TEST_NAK;
3980         }
3981
3982         /* Set test active flag here so userspace doesn't interrupt things */
3983         intel_dp->compliance.test_active = true;
3984
3985         return DP_TEST_ACK;
3986 }
3987
3988 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3989 {
3990         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3991         u8 response = DP_TEST_NAK;
3992         u8 request = 0;
3993         int status;
3994
3995         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3996         if (status <= 0) {
3997                 drm_dbg_kms(&i915->drm,
3998                             "Could not read test request from sink\n");
3999                 goto update_status;
4000         }
4001
4002         switch (request) {
4003         case DP_TEST_LINK_TRAINING:
4004                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4005                 response = intel_dp_autotest_link_training(intel_dp);
4006                 break;
4007         case DP_TEST_LINK_VIDEO_PATTERN:
4008                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4009                 response = intel_dp_autotest_video_pattern(intel_dp);
4010                 break;
4011         case DP_TEST_LINK_EDID_READ:
4012                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4013                 response = intel_dp_autotest_edid(intel_dp);
4014                 break;
4015         case DP_TEST_LINK_PHY_TEST_PATTERN:
4016                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4017                 response = intel_dp_autotest_phy_pattern(intel_dp);
4018                 break;
4019         default:
4020                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4021                             request);
4022                 break;
4023         }
4024
4025         if (response & DP_TEST_ACK)
4026                 intel_dp->compliance.test_type = request;
4027
4028 update_status:
4029         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4030         if (status <= 0)
4031                 drm_dbg_kms(&i915->drm,
4032                             "Could not write test response to sink\n");
4033 }
4034
4035 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4036                              u8 link_status[DP_LINK_STATUS_SIZE])
4037 {
4038         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4039         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4040         bool uhbr = intel_dp->link_rate >= 1000000;
4041         bool ok;
4042
4043         if (uhbr)
4044                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4045                                                           intel_dp->lane_count);
4046         else
4047                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4048
4049         if (ok)
4050                 return true;
4051
4052         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4053         drm_dbg_kms(&i915->drm,
4054                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4055                     encoder->base.base.id, encoder->base.name,
4056                     uhbr ? "128b/132b" : "8b/10b");
4057
4058         return false;
4059 }
4060
4061 static void
4062 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4063 {
4064         bool handled = false;
4065
4066         drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4067         if (handled)
4068                 ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
4069
4070         if (esi[1] & DP_CP_IRQ) {
4071                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4072                 ack[1] |= DP_CP_IRQ;
4073         }
4074 }
4075
4076 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4077 {
4078         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4079         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4080         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4081         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4082
4083         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4084                              esi_link_status_size) != esi_link_status_size) {
4085                 drm_err(&i915->drm,
4086                         "[ENCODER:%d:%s] Failed to read link status\n",
4087                         encoder->base.base.id, encoder->base.name);
4088                 return false;
4089         }
4090
4091         return intel_dp_link_ok(intel_dp, link_status);
4092 }
4093
4094 /**
4095  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4096  * @intel_dp: Intel DP struct
4097  *
4098  * Read any pending MST interrupts, call MST core to handle these and ack the
4099  * interrupts. Check if the main and AUX link state is ok.
4100  *
4101  * Returns:
4102  * - %true if pending interrupts were serviced (or no interrupts were
4103  *   pending) w/o detecting an error condition.
4104  * - %false if an error condition - like AUX failure or a loss of link - is
4105  *   detected, which needs servicing from the hotplug work.
4106  */
4107 static bool
4108 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4109 {
4110         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4111         bool link_ok = true;
4112
4113         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4114
4115         for (;;) {
4116                 u8 esi[4] = {};
4117                 u8 ack[4] = {};
4118
4119                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4120                         drm_dbg_kms(&i915->drm,
4121                                     "failed to get ESI - device may have failed\n");
4122                         link_ok = false;
4123
4124                         break;
4125                 }
4126
4127                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4128
4129                 if (intel_dp->active_mst_links > 0 && link_ok &&
4130                     esi[3] & LINK_STATUS_CHANGED) {
4131                         if (!intel_dp_mst_link_status(intel_dp))
4132                                 link_ok = false;
4133                         ack[3] |= LINK_STATUS_CHANGED;
4134                 }
4135
4136                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4137
4138                 if (!memchr_inv(ack, 0, sizeof(ack)))
4139                         break;
4140
4141                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4142                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4143         }
4144
4145         return link_ok;
4146 }
4147
4148 static void
4149 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4150 {
4151         bool is_active;
4152         u8 buf = 0;
4153
4154         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4155         if (intel_dp->frl.is_trained && !is_active) {
4156                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4157                         return;
4158
4159                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4160                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4161                         return;
4162
4163                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4164
4165                 intel_dp->frl.is_trained = false;
4166
4167                 /* Restart FRL training or fall back to TMDS mode */
4168                 intel_dp_check_frl_training(intel_dp);
4169         }
4170 }
4171
4172 static bool
4173 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4174 {
4175         u8 link_status[DP_LINK_STATUS_SIZE];
4176
4177         if (!intel_dp->link_trained)
4178                 return false;
4179
4180         /*
4181          * While PSR source HW is enabled, it will control main-link sending
4182          * frames, enabling and disabling it so trying to do a retrain will fail
4183          * as the link would or not be on or it could mix training patterns
4184          * and frame data at the same time causing retrain to fail.
4185          * Also when exiting PSR, HW will retrain the link anyways fixing
4186          * any link status error.
4187          */
4188         if (intel_psr_enabled(intel_dp))
4189                 return false;
4190
4191         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4192                                              link_status) < 0)
4193                 return false;
4194
4195         /*
4196          * Validate the cached values of intel_dp->link_rate and
4197          * intel_dp->lane_count before attempting to retrain.
4198          *
4199          * FIXME would be nice to user the crtc state here, but since
4200          * we need to call this from the short HPD handler that seems
4201          * a bit hard.
4202          */
4203         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4204                                         intel_dp->lane_count))
4205                 return false;
4206
4207         /* Retrain if link not ok */
4208         return !intel_dp_link_ok(intel_dp, link_status);
4209 }
4210
4211 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4212                                    const struct drm_connector_state *conn_state)
4213 {
4214         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4215         struct intel_encoder *encoder;
4216         enum pipe pipe;
4217
4218         if (!conn_state->best_encoder)
4219                 return false;
4220
4221         /* SST */
4222         encoder = &dp_to_dig_port(intel_dp)->base;
4223         if (conn_state->best_encoder == &encoder->base)
4224                 return true;
4225
4226         /* MST */
4227         for_each_pipe(i915, pipe) {
4228                 encoder = &intel_dp->mst_encoders[pipe]->base;
4229                 if (conn_state->best_encoder == &encoder->base)
4230                         return true;
4231         }
4232
4233         return false;
4234 }
4235
4236 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
4237                               struct drm_modeset_acquire_ctx *ctx,
4238                               u8 *pipe_mask)
4239 {
4240         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4241         struct drm_connector_list_iter conn_iter;
4242         struct intel_connector *connector;
4243         int ret = 0;
4244
4245         *pipe_mask = 0;
4246
4247         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4248         for_each_intel_connector_iter(connector, &conn_iter) {
4249                 struct drm_connector_state *conn_state =
4250                         connector->base.state;
4251                 struct intel_crtc_state *crtc_state;
4252                 struct intel_crtc *crtc;
4253
4254                 if (!intel_dp_has_connector(intel_dp, conn_state))
4255                         continue;
4256
4257                 crtc = to_intel_crtc(conn_state->crtc);
4258                 if (!crtc)
4259                         continue;
4260
4261                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4262                 if (ret)
4263                         break;
4264
4265                 crtc_state = to_intel_crtc_state(crtc->base.state);
4266
4267                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4268
4269                 if (!crtc_state->hw.active)
4270                         continue;
4271
4272                 if (conn_state->commit &&
4273                     !try_wait_for_completion(&conn_state->commit->hw_done))
4274                         continue;
4275
4276                 *pipe_mask |= BIT(crtc->pipe);
4277         }
4278         drm_connector_list_iter_end(&conn_iter);
4279
4280         return ret;
4281 }
4282
4283 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4284 {
4285         struct intel_connector *connector = intel_dp->attached_connector;
4286
4287         return connector->base.status == connector_status_connected ||
4288                 intel_dp->is_mst;
4289 }
4290
4291 int intel_dp_retrain_link(struct intel_encoder *encoder,
4292                           struct drm_modeset_acquire_ctx *ctx)
4293 {
4294         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4295         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4296         struct intel_crtc *crtc;
4297         u8 pipe_mask;
4298         int ret;
4299
4300         if (!intel_dp_is_connected(intel_dp))
4301                 return 0;
4302
4303         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4304                                ctx);
4305         if (ret)
4306                 return ret;
4307
4308         if (!intel_dp_needs_link_retrain(intel_dp))
4309                 return 0;
4310
4311         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
4312         if (ret)
4313                 return ret;
4314
4315         if (pipe_mask == 0)
4316                 return 0;
4317
4318         if (!intel_dp_needs_link_retrain(intel_dp))
4319                 return 0;
4320
4321         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4322                     encoder->base.base.id, encoder->base.name);
4323
4324         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4325                 const struct intel_crtc_state *crtc_state =
4326                         to_intel_crtc_state(crtc->base.state);
4327
4328                 /* Suppress underruns caused by re-training */
4329                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4330                 if (crtc_state->has_pch_encoder)
4331                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4332                                                               intel_crtc_pch_transcoder(crtc), false);
4333         }
4334
4335         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4336                 const struct intel_crtc_state *crtc_state =
4337                         to_intel_crtc_state(crtc->base.state);
4338
4339                 /* retrain on the MST master transcoder */
4340                 if (DISPLAY_VER(dev_priv) >= 12 &&
4341                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4342                     !intel_dp_mst_is_master_trans(crtc_state))
4343                         continue;
4344
4345                 intel_dp_check_frl_training(intel_dp);
4346                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4347                 intel_dp_start_link_train(intel_dp, crtc_state);
4348                 intel_dp_stop_link_train(intel_dp, crtc_state);
4349                 break;
4350         }
4351
4352         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4353                 const struct intel_crtc_state *crtc_state =
4354                         to_intel_crtc_state(crtc->base.state);
4355
4356                 /* Keep underrun reporting disabled until things are stable */
4357                 intel_crtc_wait_for_next_vblank(crtc);
4358
4359                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4360                 if (crtc_state->has_pch_encoder)
4361                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4362                                                               intel_crtc_pch_transcoder(crtc), true);
4363         }
4364
4365         return 0;
4366 }
4367
4368 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4369                                   struct drm_modeset_acquire_ctx *ctx,
4370                                   u8 *pipe_mask)
4371 {
4372         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4373         struct drm_connector_list_iter conn_iter;
4374         struct intel_connector *connector;
4375         int ret = 0;
4376
4377         *pipe_mask = 0;
4378
4379         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4380         for_each_intel_connector_iter(connector, &conn_iter) {
4381                 struct drm_connector_state *conn_state =
4382                         connector->base.state;
4383                 struct intel_crtc_state *crtc_state;
4384                 struct intel_crtc *crtc;
4385
4386                 if (!intel_dp_has_connector(intel_dp, conn_state))
4387                         continue;
4388
4389                 crtc = to_intel_crtc(conn_state->crtc);
4390                 if (!crtc)
4391                         continue;
4392
4393                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4394                 if (ret)
4395                         break;
4396
4397                 crtc_state = to_intel_crtc_state(crtc->base.state);
4398
4399                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4400
4401                 if (!crtc_state->hw.active)
4402                         continue;
4403
4404                 if (conn_state->commit &&
4405                     !try_wait_for_completion(&conn_state->commit->hw_done))
4406                         continue;
4407
4408                 *pipe_mask |= BIT(crtc->pipe);
4409         }
4410         drm_connector_list_iter_end(&conn_iter);
4411
4412         return ret;
4413 }
4414
4415 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4416                                 struct drm_modeset_acquire_ctx *ctx)
4417 {
4418         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4419         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4420         struct intel_crtc *crtc;
4421         u8 pipe_mask;
4422         int ret;
4423
4424         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4425                                ctx);
4426         if (ret)
4427                 return ret;
4428
4429         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4430         if (ret)
4431                 return ret;
4432
4433         if (pipe_mask == 0)
4434                 return 0;
4435
4436         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4437                     encoder->base.base.id, encoder->base.name);
4438
4439         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4440                 const struct intel_crtc_state *crtc_state =
4441                         to_intel_crtc_state(crtc->base.state);
4442
4443                 /* test on the MST master transcoder */
4444                 if (DISPLAY_VER(dev_priv) >= 12 &&
4445                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4446                     !intel_dp_mst_is_master_trans(crtc_state))
4447                         continue;
4448
4449                 intel_dp_process_phy_request(intel_dp, crtc_state);
4450                 break;
4451         }
4452
4453         return 0;
4454 }
4455
4456 void intel_dp_phy_test(struct intel_encoder *encoder)
4457 {
4458         struct drm_modeset_acquire_ctx ctx;
4459         int ret;
4460
4461         drm_modeset_acquire_init(&ctx, 0);
4462
4463         for (;;) {
4464                 ret = intel_dp_do_phy_test(encoder, &ctx);
4465
4466                 if (ret == -EDEADLK) {
4467                         drm_modeset_backoff(&ctx);
4468                         continue;
4469                 }
4470
4471                 break;
4472         }
4473
4474         drm_modeset_drop_locks(&ctx);
4475         drm_modeset_acquire_fini(&ctx);
4476         drm_WARN(encoder->base.dev, ret,
4477                  "Acquiring modeset locks failed with %i\n", ret);
4478 }
4479
4480 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4481 {
4482         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4483         u8 val;
4484
4485         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4486                 return;
4487
4488         if (drm_dp_dpcd_readb(&intel_dp->aux,
4489                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4490                 return;
4491
4492         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4493
4494         if (val & DP_AUTOMATED_TEST_REQUEST)
4495                 intel_dp_handle_test_request(intel_dp);
4496
4497         if (val & DP_CP_IRQ)
4498                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4499
4500         if (val & DP_SINK_SPECIFIC_IRQ)
4501                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4502 }
4503
4504 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4505 {
4506         u8 val;
4507
4508         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4509                 return;
4510
4511         if (drm_dp_dpcd_readb(&intel_dp->aux,
4512                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4513                 return;
4514
4515         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4516                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4517                 return;
4518
4519         if (val & HDMI_LINK_STATUS_CHANGED)
4520                 intel_dp_handle_hdmi_link_status_change(intel_dp);
4521 }
4522
4523 /*
4524  * According to DP spec
4525  * 5.1.2:
4526  *  1. Read DPCD
4527  *  2. Configure link according to Receiver Capabilities
4528  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4529  *  4. Check link status on receipt of hot-plug interrupt
4530  *
4531  * intel_dp_short_pulse -  handles short pulse interrupts
4532  * when full detection is not required.
4533  * Returns %true if short pulse is handled and full detection
4534  * is NOT required and %false otherwise.
4535  */
4536 static bool
4537 intel_dp_short_pulse(struct intel_dp *intel_dp)
4538 {
4539         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4540         u8 old_sink_count = intel_dp->sink_count;
4541         bool ret;
4542
4543         /*
4544          * Clearing compliance test variables to allow capturing
4545          * of values for next automated test request.
4546          */
4547         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4548
4549         /*
4550          * Now read the DPCD to see if it's actually running
4551          * If the current value of sink count doesn't match with
4552          * the value that was stored earlier or dpcd read failed
4553          * we need to do full detection
4554          */
4555         ret = intel_dp_get_dpcd(intel_dp);
4556
4557         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4558                 /* No need to proceed if we are going to do full detect */
4559                 return false;
4560         }
4561
4562         intel_dp_check_device_service_irq(intel_dp);
4563         intel_dp_check_link_service_irq(intel_dp);
4564
4565         /* Handle CEC interrupts, if any */
4566         drm_dp_cec_irq(&intel_dp->aux);
4567
4568         /* defer to the hotplug work for link retraining if needed */
4569         if (intel_dp_needs_link_retrain(intel_dp))
4570                 return false;
4571
4572         intel_psr_short_pulse(intel_dp);
4573
4574         switch (intel_dp->compliance.test_type) {
4575         case DP_TEST_LINK_TRAINING:
4576                 drm_dbg_kms(&dev_priv->drm,
4577                             "Link Training Compliance Test requested\n");
4578                 /* Send a Hotplug Uevent to userspace to start modeset */
4579                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4580                 break;
4581         case DP_TEST_LINK_PHY_TEST_PATTERN:
4582                 drm_dbg_kms(&dev_priv->drm,
4583                             "PHY test pattern Compliance Test requested\n");
4584                 /*
4585                  * Schedule long hpd to do the test
4586                  *
4587                  * FIXME get rid of the ad-hoc phy test modeset code
4588                  * and properly incorporate it into the normal modeset.
4589                  */
4590                 return false;
4591         }
4592
4593         return true;
4594 }
4595
4596 /* XXX this is probably wrong for multiple downstream ports */
4597 static enum drm_connector_status
4598 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4599 {
4600         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4601         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4602         u8 *dpcd = intel_dp->dpcd;
4603         u8 type;
4604
4605         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4606                 return connector_status_connected;
4607
4608         lspcon_resume(dig_port);
4609
4610         if (!intel_dp_get_dpcd(intel_dp))
4611                 return connector_status_disconnected;
4612
4613         /* if there's no downstream port, we're done */
4614         if (!drm_dp_is_branch(dpcd))
4615                 return connector_status_connected;
4616
4617         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4618         if (intel_dp_has_sink_count(intel_dp) &&
4619             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4620                 return intel_dp->sink_count ?
4621                 connector_status_connected : connector_status_disconnected;
4622         }
4623
4624         if (intel_dp_can_mst(intel_dp))
4625                 return connector_status_connected;
4626
4627         /* If no HPD, poke DDC gently */
4628         if (drm_probe_ddc(&intel_dp->aux.ddc))
4629                 return connector_status_connected;
4630
4631         /* Well we tried, say unknown for unreliable port types */
4632         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4633                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4634                 if (type == DP_DS_PORT_TYPE_VGA ||
4635                     type == DP_DS_PORT_TYPE_NON_EDID)
4636                         return connector_status_unknown;
4637         } else {
4638                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4639                         DP_DWN_STRM_PORT_TYPE_MASK;
4640                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4641                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4642                         return connector_status_unknown;
4643         }
4644
4645         /* Anything else is out of spec, warn and ignore */
4646         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4647         return connector_status_disconnected;
4648 }
4649
4650 static enum drm_connector_status
4651 edp_detect(struct intel_dp *intel_dp)
4652 {
4653         return connector_status_connected;
4654 }
4655
4656 /*
4657  * intel_digital_port_connected - is the specified port connected?
4658  * @encoder: intel_encoder
4659  *
4660  * In cases where there's a connector physically connected but it can't be used
4661  * by our hardware we also return false, since the rest of the driver should
4662  * pretty much treat the port as disconnected. This is relevant for type-C
4663  * (starting on ICL) where there's ownership involved.
4664  *
4665  * Return %true if port is connected, %false otherwise.
4666  */
4667 bool intel_digital_port_connected(struct intel_encoder *encoder)
4668 {
4669         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4670         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4671         bool is_connected = false;
4672         intel_wakeref_t wakeref;
4673
4674         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4675                 is_connected = dig_port->connected(encoder);
4676
4677         return is_connected;
4678 }
4679
4680 static const struct drm_edid *
4681 intel_dp_get_edid(struct intel_dp *intel_dp)
4682 {
4683         struct intel_connector *connector = intel_dp->attached_connector;
4684         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
4685
4686         /* Use panel fixed edid if we have one */
4687         if (fixed_edid) {
4688                 /* invalid edid */
4689                 if (IS_ERR(fixed_edid))
4690                         return NULL;
4691
4692                 return drm_edid_dup(fixed_edid);
4693         }
4694
4695         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
4696 }
4697
4698 static void
4699 intel_dp_update_dfp(struct intel_dp *intel_dp,
4700                     const struct drm_edid *drm_edid)
4701 {
4702         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4703         struct intel_connector *connector = intel_dp->attached_connector;
4704         const struct edid *edid;
4705
4706         /* FIXME: Get rid of drm_edid_raw() */
4707         edid = drm_edid_raw(drm_edid);
4708
4709         intel_dp->dfp.max_bpc =
4710                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4711                                           intel_dp->downstream_ports, edid);
4712
4713         intel_dp->dfp.max_dotclock =
4714                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4715                                                intel_dp->downstream_ports);
4716
4717         intel_dp->dfp.min_tmds_clock =
4718                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4719                                                  intel_dp->downstream_ports,
4720                                                  edid);
4721         intel_dp->dfp.max_tmds_clock =
4722                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4723                                                  intel_dp->downstream_ports,
4724                                                  edid);
4725
4726         intel_dp->dfp.pcon_max_frl_bw =
4727                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4728                                            intel_dp->downstream_ports);
4729
4730         drm_dbg_kms(&i915->drm,
4731                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4732                     connector->base.base.id, connector->base.name,
4733                     intel_dp->dfp.max_bpc,
4734                     intel_dp->dfp.max_dotclock,
4735                     intel_dp->dfp.min_tmds_clock,
4736                     intel_dp->dfp.max_tmds_clock,
4737                     intel_dp->dfp.pcon_max_frl_bw);
4738
4739         intel_dp_get_pcon_dsc_cap(intel_dp);
4740 }
4741
4742 static bool
4743 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
4744 {
4745         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
4746             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
4747                 return true;
4748
4749         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
4750             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
4751                 return true;
4752
4753         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
4754             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
4755                 return true;
4756
4757         return false;
4758 }
4759
4760 static void
4761 intel_dp_update_420(struct intel_dp *intel_dp)
4762 {
4763         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4764         struct intel_connector *connector = intel_dp->attached_connector;
4765
4766         intel_dp->dfp.ycbcr420_passthrough =
4767                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4768                                                   intel_dp->downstream_ports);
4769         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4770         intel_dp->dfp.ycbcr_444_to_420 =
4771                 dp_to_dig_port(intel_dp)->lspcon.active ||
4772                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4773                                                         intel_dp->downstream_ports);
4774         intel_dp->dfp.rgb_to_ycbcr =
4775                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4776                                                           intel_dp->downstream_ports,
4777                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4778
4779         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
4780
4781         drm_dbg_kms(&i915->drm,
4782                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4783                     connector->base.base.id, connector->base.name,
4784                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4785                     str_yes_no(connector->base.ycbcr_420_allowed),
4786                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4787 }
4788
4789 static void
4790 intel_dp_set_edid(struct intel_dp *intel_dp)
4791 {
4792         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4793         struct intel_connector *connector = intel_dp->attached_connector;
4794         const struct drm_edid *drm_edid;
4795         const struct edid *edid;
4796         bool vrr_capable;
4797
4798         intel_dp_unset_edid(intel_dp);
4799         drm_edid = intel_dp_get_edid(intel_dp);
4800         connector->detect_edid = drm_edid;
4801
4802         /* Below we depend on display info having been updated */
4803         drm_edid_connector_update(&connector->base, drm_edid);
4804
4805         vrr_capable = intel_vrr_is_capable(connector);
4806         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4807                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4808         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4809
4810         intel_dp_update_dfp(intel_dp, drm_edid);
4811         intel_dp_update_420(intel_dp);
4812
4813         /* FIXME: Get rid of drm_edid_raw() */
4814         edid = drm_edid_raw(drm_edid);
4815         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4816                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4817         }
4818
4819         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4820 }
4821
4822 static void
4823 intel_dp_unset_edid(struct intel_dp *intel_dp)
4824 {
4825         struct intel_connector *connector = intel_dp->attached_connector;
4826
4827         drm_dp_cec_unset_edid(&intel_dp->aux);
4828         drm_edid_free(connector->detect_edid);
4829         connector->detect_edid = NULL;
4830
4831         intel_dp->has_hdmi_sink = false;
4832
4833         intel_dp->dfp.max_bpc = 0;
4834         intel_dp->dfp.max_dotclock = 0;
4835         intel_dp->dfp.min_tmds_clock = 0;
4836         intel_dp->dfp.max_tmds_clock = 0;
4837
4838         intel_dp->dfp.pcon_max_frl_bw = 0;
4839
4840         intel_dp->dfp.ycbcr_444_to_420 = false;
4841         connector->base.ycbcr_420_allowed = false;
4842
4843         drm_connector_set_vrr_capable_property(&connector->base,
4844                                                false);
4845 }
4846
4847 static int
4848 intel_dp_detect(struct drm_connector *connector,
4849                 struct drm_modeset_acquire_ctx *ctx,
4850                 bool force)
4851 {
4852         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4853         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4854         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4855         struct intel_encoder *encoder = &dig_port->base;
4856         enum drm_connector_status status;
4857
4858         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4859                     connector->base.id, connector->name);
4860         drm_WARN_ON(&dev_priv->drm,
4861                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4862
4863         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4864                 return connector_status_disconnected;
4865
4866         /* Can't disconnect eDP */
4867         if (intel_dp_is_edp(intel_dp))
4868                 status = edp_detect(intel_dp);
4869         else if (intel_digital_port_connected(encoder))
4870                 status = intel_dp_detect_dpcd(intel_dp);
4871         else
4872                 status = connector_status_disconnected;
4873
4874         if (status == connector_status_disconnected) {
4875                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4876                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4877
4878                 if (intel_dp->is_mst) {
4879                         drm_dbg_kms(&dev_priv->drm,
4880                                     "MST device may have disappeared %d vs %d\n",
4881                                     intel_dp->is_mst,
4882                                     intel_dp->mst_mgr.mst_state);
4883                         intel_dp->is_mst = false;
4884                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4885                                                         intel_dp->is_mst);
4886                 }
4887
4888                 goto out;
4889         }
4890
4891         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4892         if (HAS_DSC(dev_priv))
4893                 intel_dp_get_dsc_sink_cap(intel_dp);
4894
4895         intel_dp_configure_mst(intel_dp);
4896
4897         /*
4898          * TODO: Reset link params when switching to MST mode, until MST
4899          * supports link training fallback params.
4900          */
4901         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4902                 intel_dp_reset_max_link_params(intel_dp);
4903                 intel_dp->reset_link_params = false;
4904         }
4905
4906         intel_dp_print_rates(intel_dp);
4907
4908         if (intel_dp->is_mst) {
4909                 /*
4910                  * If we are in MST mode then this connector
4911                  * won't appear connected or have anything
4912                  * with EDID on it
4913                  */
4914                 status = connector_status_disconnected;
4915                 goto out;
4916         }
4917
4918         /*
4919          * Some external monitors do not signal loss of link synchronization
4920          * with an IRQ_HPD, so force a link status check.
4921          */
4922         if (!intel_dp_is_edp(intel_dp)) {
4923                 int ret;
4924
4925                 ret = intel_dp_retrain_link(encoder, ctx);
4926                 if (ret)
4927                         return ret;
4928         }
4929
4930         /*
4931          * Clearing NACK and defer counts to get their exact values
4932          * while reading EDID which are required by Compliance tests
4933          * 4.2.2.4 and 4.2.2.5
4934          */
4935         intel_dp->aux.i2c_nack_count = 0;
4936         intel_dp->aux.i2c_defer_count = 0;
4937
4938         intel_dp_set_edid(intel_dp);
4939         if (intel_dp_is_edp(intel_dp) ||
4940             to_intel_connector(connector)->detect_edid)
4941                 status = connector_status_connected;
4942
4943         intel_dp_check_device_service_irq(intel_dp);
4944
4945 out:
4946         if (status != connector_status_connected && !intel_dp->is_mst)
4947                 intel_dp_unset_edid(intel_dp);
4948
4949         /*
4950          * Make sure the refs for power wells enabled during detect are
4951          * dropped to avoid a new detect cycle triggered by HPD polling.
4952          */
4953         intel_display_power_flush_work(dev_priv);
4954
4955         if (!intel_dp_is_edp(intel_dp))
4956                 drm_dp_set_subconnector_property(connector,
4957                                                  status,
4958                                                  intel_dp->dpcd,
4959                                                  intel_dp->downstream_ports);
4960         return status;
4961 }
4962
4963 static void
4964 intel_dp_force(struct drm_connector *connector)
4965 {
4966         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4967         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4968         struct intel_encoder *intel_encoder = &dig_port->base;
4969         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4970         enum intel_display_power_domain aux_domain =
4971                 intel_aux_power_domain(dig_port);
4972         intel_wakeref_t wakeref;
4973
4974         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4975                     connector->base.id, connector->name);
4976         intel_dp_unset_edid(intel_dp);
4977
4978         if (connector->status != connector_status_connected)
4979                 return;
4980
4981         wakeref = intel_display_power_get(dev_priv, aux_domain);
4982
4983         intel_dp_set_edid(intel_dp);
4984
4985         intel_display_power_put(dev_priv, aux_domain, wakeref);
4986 }
4987
4988 static int intel_dp_get_modes(struct drm_connector *connector)
4989 {
4990         struct intel_connector *intel_connector = to_intel_connector(connector);
4991         int num_modes;
4992
4993         /* drm_edid_connector_update() done in ->detect() or ->force() */
4994         num_modes = drm_edid_connector_add_modes(connector);
4995
4996         /* Also add fixed mode, which may or may not be present in EDID */
4997         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
4998                 num_modes += intel_panel_get_modes(intel_connector);
4999
5000         if (num_modes)
5001                 return num_modes;
5002
5003         if (!intel_connector->detect_edid) {
5004                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5005                 struct drm_display_mode *mode;
5006
5007                 mode = drm_dp_downstream_mode(connector->dev,
5008                                               intel_dp->dpcd,
5009                                               intel_dp->downstream_ports);
5010                 if (mode) {
5011                         drm_mode_probed_add(connector, mode);
5012                         num_modes++;
5013                 }
5014         }
5015
5016         return num_modes;
5017 }
5018
5019 static int
5020 intel_dp_connector_register(struct drm_connector *connector)
5021 {
5022         struct drm_i915_private *i915 = to_i915(connector->dev);
5023         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5024         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5025         struct intel_lspcon *lspcon = &dig_port->lspcon;
5026         int ret;
5027
5028         ret = intel_connector_register(connector);
5029         if (ret)
5030                 return ret;
5031
5032         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5033                     intel_dp->aux.name, connector->kdev->kobj.name);
5034
5035         intel_dp->aux.dev = connector->kdev;
5036         ret = drm_dp_aux_register(&intel_dp->aux);
5037         if (!ret)
5038                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5039
5040         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5041                 return ret;
5042
5043         /*
5044          * ToDo: Clean this up to handle lspcon init and resume more
5045          * efficiently and streamlined.
5046          */
5047         if (lspcon_init(dig_port)) {
5048                 lspcon_detect_hdr_capability(lspcon);
5049                 if (lspcon->hdr_supported)
5050                         drm_connector_attach_hdr_output_metadata_property(connector);
5051         }
5052
5053         return ret;
5054 }
5055
5056 static void
5057 intel_dp_connector_unregister(struct drm_connector *connector)
5058 {
5059         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5060
5061         drm_dp_cec_unregister_connector(&intel_dp->aux);
5062         drm_dp_aux_unregister(&intel_dp->aux);
5063         intel_connector_unregister(connector);
5064 }
5065
5066 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5067 {
5068         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5069         struct intel_dp *intel_dp = &dig_port->dp;
5070
5071         intel_dp_mst_encoder_cleanup(dig_port);
5072
5073         intel_pps_vdd_off_sync(intel_dp);
5074
5075         /*
5076          * Ensure power off delay is respected on module remove, so that we can
5077          * reduce delays at driver probe. See pps_init_timestamps().
5078          */
5079         intel_pps_wait_power_cycle(intel_dp);
5080
5081         intel_dp_aux_fini(intel_dp);
5082 }
5083
5084 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5085 {
5086         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5087
5088         intel_pps_vdd_off_sync(intel_dp);
5089 }
5090
5091 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5092 {
5093         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5094
5095         intel_pps_wait_power_cycle(intel_dp);
5096 }
5097
5098 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5099                                     int tile_group_id)
5100 {
5101         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5102         struct drm_connector_list_iter conn_iter;
5103         struct drm_connector *connector;
5104         int ret = 0;
5105
5106         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5107         drm_for_each_connector_iter(connector, &conn_iter) {
5108                 struct drm_connector_state *conn_state;
5109                 struct intel_crtc_state *crtc_state;
5110                 struct intel_crtc *crtc;
5111
5112                 if (!connector->has_tile ||
5113                     connector->tile_group->id != tile_group_id)
5114                         continue;
5115
5116                 conn_state = drm_atomic_get_connector_state(&state->base,
5117                                                             connector);
5118                 if (IS_ERR(conn_state)) {
5119                         ret = PTR_ERR(conn_state);
5120                         break;
5121                 }
5122
5123                 crtc = to_intel_crtc(conn_state->crtc);
5124
5125                 if (!crtc)
5126                         continue;
5127
5128                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5129                 crtc_state->uapi.mode_changed = true;
5130
5131                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5132                 if (ret)
5133                         break;
5134         }
5135         drm_connector_list_iter_end(&conn_iter);
5136
5137         return ret;
5138 }
5139
5140 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5141 {
5142         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5143         struct intel_crtc *crtc;
5144
5145         if (transcoders == 0)
5146                 return 0;
5147
5148         for_each_intel_crtc(&dev_priv->drm, crtc) {
5149                 struct intel_crtc_state *crtc_state;
5150                 int ret;
5151
5152                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5153                 if (IS_ERR(crtc_state))
5154                         return PTR_ERR(crtc_state);
5155
5156                 if (!crtc_state->hw.enable)
5157                         continue;
5158
5159                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5160                         continue;
5161
5162                 crtc_state->uapi.mode_changed = true;
5163
5164                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5165                 if (ret)
5166                         return ret;
5167
5168                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5169                 if (ret)
5170                         return ret;
5171
5172                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5173         }
5174
5175         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5176
5177         return 0;
5178 }
5179
5180 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5181                                       struct drm_connector *connector)
5182 {
5183         const struct drm_connector_state *old_conn_state =
5184                 drm_atomic_get_old_connector_state(&state->base, connector);
5185         const struct intel_crtc_state *old_crtc_state;
5186         struct intel_crtc *crtc;
5187         u8 transcoders;
5188
5189         crtc = to_intel_crtc(old_conn_state->crtc);
5190         if (!crtc)
5191                 return 0;
5192
5193         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5194
5195         if (!old_crtc_state->hw.active)
5196                 return 0;
5197
5198         transcoders = old_crtc_state->sync_mode_slaves_mask;
5199         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5200                 transcoders |= BIT(old_crtc_state->master_transcoder);
5201
5202         return intel_modeset_affected_transcoders(state,
5203                                                   transcoders);
5204 }
5205
5206 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5207                                            struct drm_atomic_state *_state)
5208 {
5209         struct drm_i915_private *dev_priv = to_i915(conn->dev);
5210         struct intel_atomic_state *state = to_intel_atomic_state(_state);
5211         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
5212         struct intel_connector *intel_conn = to_intel_connector(conn);
5213         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
5214         int ret;
5215
5216         ret = intel_digital_connector_atomic_check(conn, &state->base);
5217         if (ret)
5218                 return ret;
5219
5220         if (intel_dp_mst_source_support(intel_dp)) {
5221                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
5222                 if (ret)
5223                         return ret;
5224         }
5225
5226         /*
5227          * We don't enable port sync on BDW due to missing w/as and
5228          * due to not having adjusted the modeset sequence appropriately.
5229          */
5230         if (DISPLAY_VER(dev_priv) < 9)
5231                 return 0;
5232
5233         if (!intel_connector_needs_modeset(state, conn))
5234                 return 0;
5235
5236         if (conn->has_tile) {
5237                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5238                 if (ret)
5239                         return ret;
5240         }
5241
5242         return intel_modeset_synced_crtcs(state, conn);
5243 }
5244
5245 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
5246 {
5247         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5248         struct drm_i915_private *i915 = to_i915(connector->dev);
5249
5250         spin_lock_irq(&i915->irq_lock);
5251         i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
5252         spin_unlock_irq(&i915->irq_lock);
5253         queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0);
5254 }
5255
5256 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5257         .force = intel_dp_force,
5258         .fill_modes = drm_helper_probe_single_connector_modes,
5259         .atomic_get_property = intel_digital_connector_atomic_get_property,
5260         .atomic_set_property = intel_digital_connector_atomic_set_property,
5261         .late_register = intel_dp_connector_register,
5262         .early_unregister = intel_dp_connector_unregister,
5263         .destroy = intel_connector_destroy,
5264         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5265         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5266         .oob_hotplug_event = intel_dp_oob_hotplug_event,
5267 };
5268
5269 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5270         .detect_ctx = intel_dp_detect,
5271         .get_modes = intel_dp_get_modes,
5272         .mode_valid = intel_dp_mode_valid,
5273         .atomic_check = intel_dp_connector_atomic_check,
5274 };
5275
5276 enum irqreturn
5277 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5278 {
5279         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5280         struct intel_dp *intel_dp = &dig_port->dp;
5281
5282         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5283             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5284                 /*
5285                  * vdd off can generate a long/short pulse on eDP which
5286                  * would require vdd on to handle it, and thus we
5287                  * would end up in an endless cycle of
5288                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5289                  */
5290                 drm_dbg_kms(&i915->drm,
5291                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5292                             long_hpd ? "long" : "short",
5293                             dig_port->base.base.base.id,
5294                             dig_port->base.base.name);
5295                 return IRQ_HANDLED;
5296         }
5297
5298         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5299                     dig_port->base.base.base.id,
5300                     dig_port->base.base.name,
5301                     long_hpd ? "long" : "short");
5302
5303         if (long_hpd) {
5304                 intel_dp->reset_link_params = true;
5305                 return IRQ_NONE;
5306         }
5307
5308         if (intel_dp->is_mst) {
5309                 if (!intel_dp_check_mst_status(intel_dp))
5310                         return IRQ_NONE;
5311         } else if (!intel_dp_short_pulse(intel_dp)) {
5312                 return IRQ_NONE;
5313         }
5314
5315         return IRQ_HANDLED;
5316 }
5317
5318 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
5319                                   const struct intel_bios_encoder_data *devdata,
5320                                   enum port port)
5321 {
5322         /*
5323          * eDP not supported on g4x. so bail out early just
5324          * for a bit extra safety in case the VBT is bonkers.
5325          */
5326         if (DISPLAY_VER(dev_priv) < 5)
5327                 return false;
5328
5329         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5330                 return true;
5331
5332         return devdata && intel_bios_encoder_supports_edp(devdata);
5333 }
5334
5335 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
5336 {
5337         const struct intel_bios_encoder_data *devdata =
5338                 intel_bios_encoder_data_lookup(i915, port);
5339
5340         return _intel_dp_is_port_edp(i915, devdata, port);
5341 }
5342
5343 static bool
5344 has_gamut_metadata_dip(struct intel_encoder *encoder)
5345 {
5346         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
5347         enum port port = encoder->port;
5348
5349         if (intel_bios_encoder_is_lspcon(encoder->devdata))
5350                 return false;
5351
5352         if (DISPLAY_VER(i915) >= 11)
5353                 return true;
5354
5355         if (port == PORT_A)
5356                 return false;
5357
5358         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5359             DISPLAY_VER(i915) >= 9)
5360                 return true;
5361
5362         return false;
5363 }
5364
5365 static void
5366 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5367 {
5368         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5369         enum port port = dp_to_dig_port(intel_dp)->base.port;
5370
5371         if (!intel_dp_is_edp(intel_dp))
5372                 drm_connector_attach_dp_subconnector_property(connector);
5373
5374         if (!IS_G4X(dev_priv) && port != PORT_A)
5375                 intel_attach_force_audio_property(connector);
5376
5377         intel_attach_broadcast_rgb_property(connector);
5378         if (HAS_GMCH(dev_priv))
5379                 drm_connector_attach_max_bpc_property(connector, 6, 10);
5380         else if (DISPLAY_VER(dev_priv) >= 5)
5381                 drm_connector_attach_max_bpc_property(connector, 6, 12);
5382
5383         /* Register HDMI colorspace for case of lspcon */
5384         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
5385                 drm_connector_attach_content_type_property(connector);
5386                 intel_attach_hdmi_colorspace_property(connector);
5387         } else {
5388                 intel_attach_dp_colorspace_property(connector);
5389         }
5390
5391         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
5392                 drm_connector_attach_hdr_output_metadata_property(connector);
5393
5394         if (HAS_VRR(dev_priv))
5395                 drm_connector_attach_vrr_capable_property(connector);
5396 }
5397
5398 static void
5399 intel_edp_add_properties(struct intel_dp *intel_dp)
5400 {
5401         struct intel_connector *connector = intel_dp->attached_connector;
5402         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5403         const struct drm_display_mode *fixed_mode =
5404                 intel_panel_preferred_fixed_mode(connector);
5405
5406         intel_attach_scaling_mode_property(&connector->base);
5407
5408         drm_connector_set_panel_orientation_with_quirk(&connector->base,
5409                                                        i915->display.vbt.orientation,
5410                                                        fixed_mode->hdisplay,
5411                                                        fixed_mode->vdisplay);
5412 }
5413
5414 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
5415                                       struct intel_connector *connector)
5416 {
5417         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5418         enum pipe pipe = INVALID_PIPE;
5419
5420         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
5421                 /*
5422                  * Figure out the current pipe for the initial backlight setup.
5423                  * If the current pipe isn't valid, try the PPS pipe, and if that
5424                  * fails just assume pipe A.
5425                  */
5426                 pipe = vlv_active_pipe(intel_dp);
5427
5428                 if (pipe != PIPE_A && pipe != PIPE_B)
5429                         pipe = intel_dp->pps.pps_pipe;
5430
5431                 if (pipe != PIPE_A && pipe != PIPE_B)
5432                         pipe = PIPE_A;
5433         }
5434
5435         intel_backlight_setup(connector, pipe);
5436 }
5437
5438 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5439                                      struct intel_connector *intel_connector)
5440 {
5441         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5442         struct drm_connector *connector = &intel_connector->base;
5443         struct drm_display_mode *fixed_mode;
5444         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5445         bool has_dpcd;
5446         const struct drm_edid *drm_edid;
5447
5448         if (!intel_dp_is_edp(intel_dp))
5449                 return true;
5450
5451         /*
5452          * On IBX/CPT we may get here with LVDS already registered. Since the
5453          * driver uses the only internal power sequencer available for both
5454          * eDP and LVDS bail out early in this case to prevent interfering
5455          * with an already powered-on LVDS power sequencer.
5456          */
5457         if (intel_get_lvds_encoder(dev_priv)) {
5458                 drm_WARN_ON(&dev_priv->drm,
5459                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5460                 drm_info(&dev_priv->drm,
5461                          "LVDS was detected, not registering eDP\n");
5462
5463                 return false;
5464         }
5465
5466         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
5467                                     encoder->devdata);
5468
5469         if (!intel_pps_init(intel_dp)) {
5470                 drm_info(&dev_priv->drm,
5471                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
5472                          encoder->base.base.id, encoder->base.name);
5473                 /*
5474                  * The BIOS may have still enabled VDD on the PPS even
5475                  * though it's unusable. Make sure we turn it back off
5476                  * and to release the power domain references/etc.
5477                  */
5478                 goto out_vdd_off;
5479         }
5480
5481         /*
5482          * Enable HPD sense for live status check.
5483          * intel_hpd_irq_setup() will turn it off again
5484          * if it's no longer needed later.
5485          *
5486          * The DPCD probe below will make sure VDD is on.
5487          */
5488         intel_hpd_enable_detection(encoder);
5489
5490         /* Cache DPCD and EDID for edp. */
5491         has_dpcd = intel_edp_init_dpcd(intel_dp);
5492
5493         if (!has_dpcd) {
5494                 /* if this fails, presume the device is a ghost */
5495                 drm_info(&dev_priv->drm,
5496                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
5497                          encoder->base.base.id, encoder->base.name);
5498                 goto out_vdd_off;
5499         }
5500
5501         /*
5502          * VBT and straps are liars. Also check HPD as that seems
5503          * to be the most reliable piece of information available.
5504          */
5505         if (!intel_digital_port_connected(encoder)) {
5506                 /*
5507                  * If this fails, presume the DPCD answer came
5508                  * from some other port using the same AUX CH.
5509                  *
5510                  * FIXME maybe cleaner to check this before the
5511                  * DPCD read? Would need sort out the VDD handling...
5512                  */
5513                 drm_info(&dev_priv->drm,
5514                          "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
5515                          encoder->base.base.id, encoder->base.name);
5516                 goto out_vdd_off;
5517         }
5518
5519         mutex_lock(&dev_priv->drm.mode_config.mutex);
5520         drm_edid = drm_edid_read_ddc(connector, &intel_dp->aux.ddc);
5521         if (!drm_edid) {
5522                 /* Fallback to EDID from ACPI OpRegion, if any */
5523                 drm_edid = intel_opregion_get_edid(intel_connector);
5524                 if (drm_edid)
5525                         drm_dbg_kms(&dev_priv->drm,
5526                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5527                                     connector->base.id, connector->name);
5528         }
5529         if (drm_edid) {
5530                 if (drm_edid_connector_update(connector, drm_edid) ||
5531                     !drm_edid_connector_add_modes(connector)) {
5532                         drm_edid_connector_update(connector, NULL);
5533                         drm_edid_free(drm_edid);
5534                         drm_edid = ERR_PTR(-EINVAL);
5535                 }
5536         } else {
5537                 drm_edid = ERR_PTR(-ENOENT);
5538         }
5539
5540         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
5541                                    IS_ERR(drm_edid) ? NULL : drm_edid);
5542
5543         intel_panel_add_edid_fixed_modes(intel_connector, true);
5544
5545         /* MSO requires information from the EDID */
5546         intel_edp_mso_init(intel_dp);
5547
5548         /* multiply the mode clock and horizontal timings for MSO */
5549         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5550                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5551
5552         /* fallback to VBT if available for eDP */
5553         if (!intel_panel_preferred_fixed_mode(intel_connector))
5554                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5555
5556         mutex_unlock(&dev_priv->drm.mode_config.mutex);
5557
5558         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
5559                 drm_info(&dev_priv->drm,
5560                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
5561                          encoder->base.base.id, encoder->base.name);
5562                 goto out_vdd_off;
5563         }
5564
5565         intel_panel_init(intel_connector, drm_edid);
5566
5567         intel_edp_backlight_setup(intel_dp, intel_connector);
5568
5569         intel_edp_add_properties(intel_dp);
5570
5571         intel_pps_init_late(intel_dp);
5572
5573         return true;
5574
5575 out_vdd_off:
5576         intel_pps_vdd_off_sync(intel_dp);
5577
5578         return false;
5579 }
5580
5581 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5582 {
5583         struct intel_connector *intel_connector;
5584         struct drm_connector *connector;
5585
5586         intel_connector = container_of(work, typeof(*intel_connector),
5587                                        modeset_retry_work);
5588         connector = &intel_connector->base;
5589         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5590                     connector->name);
5591
5592         /* Grab the locks before changing connector property*/
5593         mutex_lock(&connector->dev->mode_config.mutex);
5594         /* Set connector link status to BAD and send a Uevent to notify
5595          * userspace to do a modeset.
5596          */
5597         drm_connector_set_link_status_property(connector,
5598                                                DRM_MODE_LINK_STATUS_BAD);
5599         mutex_unlock(&connector->dev->mode_config.mutex);
5600         /* Send Hotplug uevent so userspace can reprobe */
5601         drm_kms_helper_connector_hotplug_event(connector);
5602 }
5603
5604 bool
5605 intel_dp_init_connector(struct intel_digital_port *dig_port,
5606                         struct intel_connector *intel_connector)
5607 {
5608         struct drm_connector *connector = &intel_connector->base;
5609         struct intel_dp *intel_dp = &dig_port->dp;
5610         struct intel_encoder *intel_encoder = &dig_port->base;
5611         struct drm_device *dev = intel_encoder->base.dev;
5612         struct drm_i915_private *dev_priv = to_i915(dev);
5613         enum port port = intel_encoder->port;
5614         enum phy phy = intel_port_to_phy(dev_priv, port);
5615         int type;
5616
5617         /* Initialize the work for modeset in case of link train failure */
5618         INIT_WORK(&intel_connector->modeset_retry_work,
5619                   intel_dp_modeset_retry_work_fn);
5620
5621         if (drm_WARN(dev, dig_port->max_lanes < 1,
5622                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5623                      dig_port->max_lanes, intel_encoder->base.base.id,
5624                      intel_encoder->base.name))
5625                 return false;
5626
5627         intel_dp->reset_link_params = true;
5628         intel_dp->pps.pps_pipe = INVALID_PIPE;
5629         intel_dp->pps.active_pipe = INVALID_PIPE;
5630
5631         /* Preserve the current hw state. */
5632         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5633         intel_dp->attached_connector = intel_connector;
5634
5635         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
5636                 /*
5637                  * Currently we don't support eDP on TypeC ports, although in
5638                  * theory it could work on TypeC legacy ports.
5639                  */
5640                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5641                 type = DRM_MODE_CONNECTOR_eDP;
5642                 intel_encoder->type = INTEL_OUTPUT_EDP;
5643
5644                 /* eDP only on port B and/or C on vlv/chv */
5645                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5646                                       IS_CHERRYVIEW(dev_priv)) &&
5647                                 port != PORT_B && port != PORT_C))
5648                         return false;
5649         } else {
5650                 type = DRM_MODE_CONNECTOR_DisplayPort;
5651         }
5652
5653         intel_dp_set_default_sink_rates(intel_dp);
5654         intel_dp_set_default_max_sink_lane_count(intel_dp);
5655
5656         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5657                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5658
5659         drm_dbg_kms(&dev_priv->drm,
5660                     "Adding %s connector on [ENCODER:%d:%s]\n",
5661                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5662                     intel_encoder->base.base.id, intel_encoder->base.name);
5663
5664         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5665         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5666
5667         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
5668                 connector->interlace_allowed = true;
5669
5670         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5671
5672         intel_dp_aux_init(intel_dp);
5673
5674         intel_connector_attach_encoder(intel_connector, intel_encoder);
5675
5676         if (HAS_DDI(dev_priv))
5677                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5678         else
5679                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5680
5681         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5682                 intel_dp_aux_fini(intel_dp);
5683                 goto fail;
5684         }
5685
5686         intel_dp_set_source_rates(intel_dp);
5687         intel_dp_set_common_rates(intel_dp);
5688         intel_dp_reset_max_link_params(intel_dp);
5689
5690         /* init MST on ports that can support it */
5691         intel_dp_mst_encoder_init(dig_port,
5692                                   intel_connector->base.base.id);
5693
5694         intel_dp_add_properties(intel_dp, connector);
5695
5696         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5697                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5698                 if (ret)
5699                         drm_dbg_kms(&dev_priv->drm,
5700                                     "HDCP init failed, skipping.\n");
5701         }
5702
5703         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5704          * 0xd.  Failure to do so will result in spurious interrupts being
5705          * generated on the port when a cable is not attached.
5706          */
5707         if (IS_G45(dev_priv)) {
5708                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5709                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5710                                (temp & ~0xf) | 0xd);
5711         }
5712
5713         intel_dp->frl.is_trained = false;
5714         intel_dp->frl.trained_rate_gbps = 0;
5715
5716         intel_psr_init(intel_dp);
5717
5718         return true;
5719
5720 fail:
5721         drm_connector_cleanup(connector);
5722
5723         return false;
5724 }
5725
5726 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5727 {
5728         struct intel_encoder *encoder;
5729
5730         if (!HAS_DISPLAY(dev_priv))
5731                 return;
5732
5733         for_each_intel_encoder(&dev_priv->drm, encoder) {
5734                 struct intel_dp *intel_dp;
5735
5736                 if (encoder->type != INTEL_OUTPUT_DDI)
5737                         continue;
5738
5739                 intel_dp = enc_to_intel_dp(encoder);
5740
5741                 if (!intel_dp_mst_source_support(intel_dp))
5742                         continue;
5743
5744                 if (intel_dp->is_mst)
5745                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5746         }
5747 }
5748
5749 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5750 {
5751         struct intel_encoder *encoder;
5752
5753         if (!HAS_DISPLAY(dev_priv))
5754                 return;
5755
5756         for_each_intel_encoder(&dev_priv->drm, encoder) {
5757                 struct intel_dp *intel_dp;
5758                 int ret;
5759
5760                 if (encoder->type != INTEL_OUTPUT_DDI)
5761                         continue;
5762
5763                 intel_dp = enc_to_intel_dp(encoder);
5764
5765                 if (!intel_dp_mst_source_support(intel_dp))
5766                         continue;
5767
5768                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5769                                                      true);
5770                 if (ret) {
5771                         intel_dp->is_mst = false;
5772                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5773                                                         false);
5774                 }
5775         }
5776 }