drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "intel_atomic.h"
  46 #include "intel_audio.h"
  47 #include "intel_connector.h"
  48 #include "intel_ddi.h"
  49 #include "intel_display_types.h"
  50 #include "intel_dp.h"
  51 #include "intel_dp_link_training.h"
  52 #include "intel_dp_mst.h"
  53 #include "intel_dpio_phy.h"
  54 #include "intel_fifo_underrun.h"
  55 #include "intel_hdcp.h"
  56 #include "intel_hdmi.h"
  57 #include "intel_hotplug.h"
  58 #include "intel_lspcon.h"
  59 #include "intel_lvds.h"
  60 #include "intel_panel.h"
  61 #include "intel_psr.h"
  62 #include "intel_sideband.h"
  63 #include "intel_tc.h"
  64 #include "intel_vdsc.h"
  65
  66 #define DP_DPRX_ESI_LEN 14
  67
  68 /* DP DSC throughput values used for slice count calculations KPixels/s */
  69 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  70 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  71 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  72
  73 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  74 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  75
  76 /* Compliance test status bits  */
  77 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  78 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  79 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  80 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  81
  82 struct dp_link_dpll {
  83         int clock;
  84         struct dpll dpll;
  85 };
  86
  87 static const struct dp_link_dpll g4x_dpll[] = {
  88         { 162000,
  89                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  90         { 270000,
  91                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  92 };
  93
  94 static const struct dp_link_dpll pch_dpll[] = {
  95         { 162000,
  96                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  97         { 270000,
  98                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  99 };
 100
 101 static const struct dp_link_dpll vlv_dpll[] = {
 102         { 162000,
 103                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 104         { 270000,
 105                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 106 };
 107
 108 /*
 109  * CHV supports eDP 1.4 that have  more link rates.
 110  * Below only provides the fixed rate but exclude variable rate.
 111  */
 112 static const struct dp_link_dpll chv_dpll[] = {
 113         /*
 114          * CHV requires to program fractional division for m2.
 115          * m2 is stored in fixed point format using formula below
 116          * (m2_int << 22) | m2_fraction
 117          */
 118         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 119                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 120         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 121                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 122 };
 123
 124 /* Constants for DP DSC configurations */
 125 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 126
 127 /* With Single pipe configuration, HW is capable of supporting maximum
 128  * of 4 slices per line.
 129  */
 130 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 131
 132 /**
 133  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 134  * @intel_dp: DP struct
 135  *
 136  * If a CPU or PCH DP output is attached to an eDP panel, this function
 137  * will return true, and false otherwise.
 138  */
 139 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 140 {
 141         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 142
 143         return dig_port->base.type == INTEL_OUTPUT_EDP;
 144 }
 145
 146 static void intel_dp_link_down(struct intel_encoder *encoder,
 147                                const struct intel_crtc_state *old_crtc_state);
 148 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 149 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 150 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 151                                            const struct intel_crtc_state *crtc_state);
 152 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 153                                       enum pipe pipe);
 154 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 155
 156 /* update sink rates from dpcd */
 157 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 158 {
 159         static const int dp_rates[] = {
 160                 162000, 270000, 540000, 810000
 161         };
 162         int i, max_rate;
 163         int max_lttpr_rate;
 164
 165         if (drm_dp_has_quirk(&intel_dp->desc, 0,
 166                              DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 167                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 168                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 169
 170                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 171                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 172
 173                 return;
 174         }
 175
 176         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 177         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 178         if (max_lttpr_rate)
 179                 max_rate = min(max_rate, max_lttpr_rate);
 180
 181         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 182                 if (dp_rates[i] > max_rate)
 183                         break;
 184                 intel_dp->sink_rates[i] = dp_rates[i];
 185         }
 186
 187         intel_dp->num_sink_rates = i;
 188 }
 189
 190 /* Get length of rates array potentially limited by max_rate. */
 191 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 192 {
 193         int i;
 194
 195         /* Limit results by potentially reduced max rate */
 196         for (i = 0; i < len; i++) {
 197                 if (rates[len - i - 1] <= max_rate)
 198                         return len - i;
 199         }
 200
 201         return 0;
 202 }
 203
 204 /* Get length of common rates array potentially limited by max_rate. */
 205 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 206                                           int max_rate)
 207 {
 208         return intel_dp_rate_limit_len(intel_dp->common_rates,
 209                                        intel_dp->num_common_rates, max_rate);
 210 }
 211
 212 /* Theoretical max between source and sink */
 213 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 216 }
 217
 218 /* Theoretical max between source and sink */
 219 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 220 {
 221         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 222         int source_max = dig_port->max_lanes;
 223         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 224         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 225         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 226
 227         if (lttpr_max)
 228                 sink_max = min(sink_max, lttpr_max);
 229
 230         return min3(source_max, sink_max, fia_max);
 231 }
 232
 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 234 {
 235         return intel_dp->max_link_lane_count;
 236 }
 237
 238 int
 239 intel_dp_link_required(int pixel_clock, int bpp)
 240 {
 241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 243 }
 244
 245 int
 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 247 {
 248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 250          * is transmitted every LS_Clk per lane, there is no need to account for
 251          * the channel encoding that is done in the PHY layer here.
 252          */
 253
 254         return max_link_clock * max_lanes;
 255 }
 256
 257 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 258 {
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct intel_encoder *encoder = &intel_dig_port->base;
 261         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 262
 263         return INTEL_GEN(dev_priv) >= 12 ||
 264                 (INTEL_GEN(dev_priv) == 11 &&
 265                  encoder->port != PORT_A);
 266 }
 267
 268 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 271         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 272         enum port port = dig_port->base.port;
 273
 274         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 275
 276         /* Low voltage SKUs are limited to max of 5.4G */
 277         if (voltage == VOLTAGE_INFO_0_85V)
 278                 return 540000;
 279
 280         /* For this SKU 8.1G is supported in all ports */
 281         if (IS_CNL_WITH_PORT_F(dev_priv))
 282                 return 810000;
 283
 284         /* For other SKUs, max rate on ports A and D is 5.4G */
 285         if (port == PORT_A || port == PORT_D)
 286                 return 540000;
 287
 288         return 810000;
 289 }
 290
 291 static int icl_max_source_rate(struct intel_dp *intel_dp)
 292 {
 293         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 294         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 295         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 296
 297         if (intel_phy_is_combo(dev_priv, phy) &&
 298             !intel_dp_is_edp(intel_dp))
 299                 return 540000;
 300
 301         return 810000;
 302 }
 303
 304 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 305 {
 306         if (intel_dp_is_edp(intel_dp))
 307                 return 540000;
 308
 309         return 810000;
 310 }
 311
 312 static void
 313 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 314 {
 315         /* The values must be in increasing order */
 316         static const int cnl_rates[] = {
 317                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 318         };
 319         static const int bxt_rates[] = {
 320                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 321         };
 322         static const int skl_rates[] = {
 323                 162000, 216000, 270000, 324000, 432000, 540000
 324         };
 325         static const int hsw_rates[] = {
 326                 162000, 270000, 540000
 327         };
 328         static const int g4x_rates[] = {
 329                 162000, 270000
 330         };
 331         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 332         struct intel_encoder *encoder = &dig_port->base;
 333         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 334         const int *source_rates;
 335         int size, max_rate = 0, vbt_max_rate;
 336
 337         /* This should only be done once */
 338         drm_WARN_ON(&dev_priv->drm,
 339                     intel_dp->source_rates || intel_dp->num_source_rates);
 340
 341         if (INTEL_GEN(dev_priv) >= 10) {
 342                 source_rates = cnl_rates;
 343                 size = ARRAY_SIZE(cnl_rates);
 344                 if (IS_GEN(dev_priv, 10))
 345                         max_rate = cnl_max_source_rate(intel_dp);
 346                 else if (IS_JSL_EHL(dev_priv))
 347                         max_rate = ehl_max_source_rate(intel_dp);
 348                 else
 349                         max_rate = icl_max_source_rate(intel_dp);
 350         } else if (IS_GEN9_LP(dev_priv)) {
 351                 source_rates = bxt_rates;
 352                 size = ARRAY_SIZE(bxt_rates);
 353         } else if (IS_GEN9_BC(dev_priv)) {
 354                 source_rates = skl_rates;
 355                 size = ARRAY_SIZE(skl_rates);
 356         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 357                    IS_BROADWELL(dev_priv)) {
 358                 source_rates = hsw_rates;
 359                 size = ARRAY_SIZE(hsw_rates);
 360         } else {
 361                 source_rates = g4x_rates;
 362                 size = ARRAY_SIZE(g4x_rates);
 363         }
 364
 365         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 366         if (max_rate && vbt_max_rate)
 367                 max_rate = min(max_rate, vbt_max_rate);
 368         else if (vbt_max_rate)
 369                 max_rate = vbt_max_rate;
 370
 371         if (max_rate)
 372                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 373
 374         intel_dp->source_rates = source_rates;
 375         intel_dp->num_source_rates = size;
 376 }
 377
 378 static int intersect_rates(const int *source_rates, int source_len,
 379                            const int *sink_rates, int sink_len,
 380                            int *common_rates)
 381 {
 382         int i = 0, j = 0, k = 0;
 383
 384         while (i < source_len && j < sink_len) {
 385                 if (source_rates[i] == sink_rates[j]) {
 386                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 387                                 return k;
 388                         common_rates[k] = source_rates[i];
 389                         ++k;
 390                         ++i;
 391                         ++j;
 392                 } else if (source_rates[i] < sink_rates[j]) {
 393                         ++i;
 394                 } else {
 395                         ++j;
 396                 }
 397         }
 398         return k;
 399 }
 400
 401 /* return index of rate in rates array, or -1 if not found */
 402 static int intel_dp_rate_index(const int *rates, int len, int rate)
 403 {
 404         int i;
 405
 406         for (i = 0; i < len; i++)
 407                 if (rate == rates[i])
 408                         return i;
 409
 410         return -1;
 411 }
 412
 413 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 414 {
 415         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 416
 417         drm_WARN_ON(&i915->drm,
 418                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 419
 420         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 421                                                      intel_dp->num_source_rates,
 422                                                      intel_dp->sink_rates,
 423                                                      intel_dp->num_sink_rates,
 424                                                      intel_dp->common_rates);
 425
 426         /* Paranoia, there should always be something in common. */
 427         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 428                 intel_dp->common_rates[0] = 162000;
 429                 intel_dp->num_common_rates = 1;
 430         }
 431 }
 432
 433 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 434                                        u8 lane_count)
 435 {
 436         /*
 437          * FIXME: we need to synchronize the current link parameters with
 438          * hardware readout. Currently fast link training doesn't work on
 439          * boot-up.
 440          */
 441         if (link_rate == 0 ||
 442             link_rate > intel_dp->max_link_rate)
 443                 return false;
 444
 445         if (lane_count == 0 ||
 446             lane_count > intel_dp_max_lane_count(intel_dp))
 447                 return false;
 448
 449         return true;
 450 }
 451
 452 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 453                                                      int link_rate,
 454                                                      u8 lane_count)
 455 {
 456         const struct drm_display_mode *fixed_mode =
 457                 intel_dp->attached_connector->panel.fixed_mode;
 458         int mode_rate, max_rate;
 459
 460         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 461         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 462         if (mode_rate > max_rate)
 463                 return false;
 464
 465         return true;
 466 }
 467
 468 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 469                                             int link_rate, u8 lane_count)
 470 {
 471         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 472         int index;
 473
 474         /*
 475          * TODO: Enable fallback on MST links once MST link compute can handle
 476          * the fallback params.
 477          */
 478         if (intel_dp->is_mst) {
 479                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 480                 return -1;
 481         }
 482
 483         index = intel_dp_rate_index(intel_dp->common_rates,
 484                                     intel_dp->num_common_rates,
 485                                     link_rate);
 486         if (index > 0) {
 487                 if (intel_dp_is_edp(intel_dp) &&
 488                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 489                                                               intel_dp->common_rates[index - 1],
 490                                                               lane_count)) {
 491                         drm_dbg_kms(&i915->drm,
 492                                     "Retrying Link training for eDP with same parameters\n");
 493                         return 0;
 494                 }
 495                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 496                 intel_dp->max_link_lane_count = lane_count;
 497         } else if (lane_count > 1) {
 498                 if (intel_dp_is_edp(intel_dp) &&
 499                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 500                                                               intel_dp_max_common_rate(intel_dp),
 501                                                               lane_count >> 1)) {
 502                         drm_dbg_kms(&i915->drm,
 503                                     "Retrying Link training for eDP with same parameters\n");
 504                         return 0;
 505                 }
 506                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 507                 intel_dp->max_link_lane_count = lane_count >> 1;
 508         } else {
 509                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 510                 return -1;
 511         }
 512
 513         return 0;
 514 }
 515
 516 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 517 {
 518         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 519                        DP_DSC_FEC_OVERHEAD_FACTOR);
 520 }
 521
 522 static int
 523 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 524 {
 525         if (INTEL_GEN(i915) >= 11)
 526                 return 7680 * 8;
 527         else
 528                 return 6144 * 8;
 529 }
 530
 531 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 532                                        u32 link_clock, u32 lane_count,
 533                                        u32 mode_clock, u32 mode_hdisplay,
 534                                        bool bigjoiner)
 535 {
 536         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 537         int i;
 538
 539         /*
 540          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 541          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 542          * for SST -> TimeSlotsPerMTP is 1,
 543          * for MST -> TimeSlotsPerMTP has to be calculated
 544          */
 545         bits_per_pixel = (link_clock * lane_count * 8) /
 546                          intel_dp_mode_to_fec_clock(mode_clock);
 547         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 548
 549         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 550         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 551                 mode_hdisplay;
 552
 553         if (bigjoiner)
 554                 max_bpp_small_joiner_ram *= 2;
 555
 556         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 557                     max_bpp_small_joiner_ram);
 558
 559         /*
 560          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 561          * check, output bpp from small joiner RAM check)
 562          */
 563         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 564
 565         if (bigjoiner) {
 566                 u32 max_bpp_bigjoiner =
 567                         i915->max_cdclk_freq * 48 /
 568                         intel_dp_mode_to_fec_clock(mode_clock);
 569
 570                 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 571                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 572         }
 573
 574         /* Error out if the max bpp is less than smallest allowed valid bpp */
 575         if (bits_per_pixel < valid_dsc_bpp[0]) {
 576                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 577                             bits_per_pixel, valid_dsc_bpp[0]);
 578                 return 0;
 579         }
 580
 581         /* Find the nearest match in the array of known BPPs from VESA */
 582         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 583                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 584                         break;
 585         }
 586         bits_per_pixel = valid_dsc_bpp[i];
 587
 588         /*
 589          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 590          * fractional part is 0
 591          */
 592         return bits_per_pixel << 4;
 593 }
 594
 595 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 596                                        int mode_clock, int mode_hdisplay,
 597                                        bool bigjoiner)
 598 {
 599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 600         u8 min_slice_count, i;
 601         int max_slice_width;
 602
 603         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 604                 min_slice_count = DIV_ROUND_UP(mode_clock,
 605                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 606         else
 607                 min_slice_count = DIV_ROUND_UP(mode_clock,
 608                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 609
 610         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 611         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 612                 drm_dbg_kms(&i915->drm,
 613                             "Unsupported slice width %d by DP DSC Sink device\n",
 614                             max_slice_width);
 615                 return 0;
 616         }
 617         /* Also take into account max slice width */
 618         min_slice_count = max_t(u8, min_slice_count,
 619                                 DIV_ROUND_UP(mode_hdisplay,
 620                                              max_slice_width));
 621
 622         /* Find the closest match to the valid slice count values */
 623         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 624                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 625
 626                 if (test_slice_count >
 627                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 628                         break;
 629
 630                 /* big joiner needs small joiner to be enabled */
 631                 if (bigjoiner && test_slice_count < 4)
 632                         continue;
 633
 634                 if (min_slice_count <= test_slice_count)
 635                         return test_slice_count;
 636         }
 637
 638         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 639                     min_slice_count);
 640         return 0;
 641 }
 642
 643 static enum intel_output_format
 644 intel_dp_output_format(struct drm_connector *connector,
 645                        const struct drm_display_mode *mode)
 646 {
 647         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 648         const struct drm_display_info *info = &connector->display_info;
 649
 650         if (!connector->ycbcr_420_allowed ||
 651             !drm_mode_is_420_only(info, mode))
 652                 return INTEL_OUTPUT_FORMAT_RGB;
 653
 654         if (intel_dp->dfp.rgb_to_ycbcr &&
 655             intel_dp->dfp.ycbcr_444_to_420)
 656                 return INTEL_OUTPUT_FORMAT_RGB;
 657
 658         if (intel_dp->dfp.ycbcr_444_to_420)
 659                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 660         else
 661                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 662 }
 663
 664 int intel_dp_min_bpp(enum intel_output_format output_format)
 665 {
 666         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 667                 return 6 * 3;
 668         else
 669                 return 8 * 3;
 670 }
 671
 672 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 673 {
 674         /*
 675          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 676          * format of the number of bytes per pixel will be half the number
 677          * of bytes of RGB pixel.
 678          */
 679         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 680                 bpp /= 2;
 681
 682         return bpp;
 683 }
 684
 685 static int
 686 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 687                              const struct drm_display_mode *mode)
 688 {
 689         enum intel_output_format output_format =
 690                 intel_dp_output_format(connector, mode);
 691
 692         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 693 }
 694
 695 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 696                                   int hdisplay)
 697 {
 698         /*
 699          * Older platforms don't like hdisplay==4096 with DP.
 700          *
 701          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 702          * and frame counter increment), but we don't get vblank interrupts,
 703          * and the pipe underruns immediately. The link also doesn't seem
 704          * to get trained properly.
 705          *
 706          * On CHV the vblank interrupts don't seem to disappear but
 707          * otherwise the symptoms are similar.
 708          *
 709          * TODO: confirm the behaviour on HSW+
 710          */
 711         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 712 }
 713
 714 static enum drm_mode_status
 715 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 716                                const struct drm_display_mode *mode,
 717                                int target_clock)
 718 {
 719         struct intel_dp *intel_dp = intel_attached_dp(connector);
 720         const struct drm_display_info *info = &connector->base.display_info;
 721         int tmds_clock;
 722
 723         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 724         if (intel_dp->dfp.pcon_max_frl_bw) {
 725                 int target_bw;
 726                 int max_frl_bw;
 727                 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
 728
 729                 target_bw = bpp * target_clock;
 730
 731                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 732
 733                 /* converting bw from Gbps to Kbps*/
 734                 max_frl_bw = max_frl_bw * 1000000;
 735
 736                 if (target_bw > max_frl_bw)
 737                         return MODE_CLOCK_HIGH;
 738
 739                 return MODE_OK;
 740         }
 741
 742         if (intel_dp->dfp.max_dotclock &&
 743             target_clock > intel_dp->dfp.max_dotclock)
 744                 return MODE_CLOCK_HIGH;
 745
 746         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 747         tmds_clock = target_clock;
 748         if (drm_mode_is_420_only(info, mode))
 749                 tmds_clock /= 2;
 750
 751         if (intel_dp->dfp.min_tmds_clock &&
 752             tmds_clock < intel_dp->dfp.min_tmds_clock)
 753                 return MODE_CLOCK_LOW;
 754         if (intel_dp->dfp.max_tmds_clock &&
 755             tmds_clock > intel_dp->dfp.max_tmds_clock)
 756                 return MODE_CLOCK_HIGH;
 757
 758         return MODE_OK;
 759 }
 760
 761 static enum drm_mode_status
 762 intel_dp_mode_valid(struct drm_connector *connector,
 763                     struct drm_display_mode *mode)
 764 {
 765         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 766         struct intel_connector *intel_connector = to_intel_connector(connector);
 767         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 768         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 769         int target_clock = mode->clock;
 770         int max_rate, mode_rate, max_lanes, max_link_clock;
 771         int max_dotclk = dev_priv->max_dotclk_freq;
 772         u16 dsc_max_output_bpp = 0;
 773         u8 dsc_slice_count = 0;
 774         enum drm_mode_status status;
 775         bool dsc = false, bigjoiner = false;
 776
 777         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 778                 return MODE_NO_DBLESCAN;
 779
 780         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 781                 return MODE_H_ILLEGAL;
 782
 783         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 784                 if (mode->hdisplay > fixed_mode->hdisplay)
 785                         return MODE_PANEL;
 786
 787                 if (mode->vdisplay > fixed_mode->vdisplay)
 788                         return MODE_PANEL;
 789
 790                 target_clock = fixed_mode->clock;
 791         }
 792
 793         if (mode->clock < 10000)
 794                 return MODE_CLOCK_LOW;
 795
 796         if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 797             intel_dp_can_bigjoiner(intel_dp)) {
 798                 bigjoiner = true;
 799                 max_dotclk *= 2;
 800         }
 801         if (target_clock > max_dotclk)
 802                 return MODE_CLOCK_HIGH;
 803
 804         max_link_clock = intel_dp_max_link_rate(intel_dp);
 805         max_lanes = intel_dp_max_lane_count(intel_dp);
 806
 807         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 808         mode_rate = intel_dp_link_required(target_clock,
 809                                            intel_dp_mode_min_output_bpp(connector, mode));
 810
 811         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 812                 return MODE_H_ILLEGAL;
 813
 814         /*
 815          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 816          * integer value since we support only integer values of bpp.
 817          */
 818         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 819             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 820                 if (intel_dp_is_edp(intel_dp)) {
 821                         dsc_max_output_bpp =
 822                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 823                         dsc_slice_count =
 824                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 825                                                                 true);
 826                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 827                         dsc_max_output_bpp =
 828                                 intel_dp_dsc_get_output_bpp(dev_priv,
 829                                                             max_link_clock,
 830                                                             max_lanes,
 831                                                             target_clock,
 832                                                             mode->hdisplay,
 833                                                             bigjoiner) >> 4;
 834                         dsc_slice_count =
 835                                 intel_dp_dsc_get_slice_count(intel_dp,
 836                                                              target_clock,
 837                                                              mode->hdisplay,
 838                                                              bigjoiner);
 839                 }
 840
 841                 dsc = dsc_max_output_bpp && dsc_slice_count;
 842         }
 843
 844         /* big joiner configuration needs DSC */
 845         if (bigjoiner && !dsc)
 846                 return MODE_CLOCK_HIGH;
 847
 848         if (mode_rate > max_rate && !dsc)
 849                 return MODE_CLOCK_HIGH;
 850
 851         status = intel_dp_mode_valid_downstream(intel_connector,
 852                                                 mode, target_clock);
 853         if (status != MODE_OK)
 854                 return status;
 855
 856         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 857 }
 858
 859 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 860 {
 861         int i;
 862         u32 v = 0;
 863
 864         if (src_bytes > 4)
 865                 src_bytes = 4;
 866         for (i = 0; i < src_bytes; i++)
 867                 v |= ((u32)src[i]) << ((3 - i) * 8);
 868         return v;
 869 }
 870
 871 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 872 {
 873         int i;
 874         if (dst_bytes > 4)
 875                 dst_bytes = 4;
 876         for (i = 0; i < dst_bytes; i++)
 877                 dst[i] = src >> ((3-i) * 8);
 878 }
 879
 880 static void
 881 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 882 static void
 883 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 884                                               bool force_disable_vdd);
 885 static void
 886 intel_dp_pps_init(struct intel_dp *intel_dp);
 887
 888 static intel_wakeref_t
 889 pps_lock(struct intel_dp *intel_dp)
 890 {
 891         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 892         intel_wakeref_t wakeref;
 893
 894         /*
 895          * See intel_power_sequencer_reset() why we need
 896          * a power domain reference here.
 897          */
 898         wakeref = intel_display_power_get(dev_priv,
 899                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 900
 901         mutex_lock(&dev_priv->pps_mutex);
 902
 903         return wakeref;
 904 }
 905
 906 static intel_wakeref_t
 907 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 908 {
 909         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 910
 911         mutex_unlock(&dev_priv->pps_mutex);
 912         intel_display_power_put(dev_priv,
 913                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 914                                 wakeref);
 915         return 0;
 916 }
 917
 918 #define with_pps_lock(dp, wf) \
 919         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 920
 921 static void
 922 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 923 {
 924         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 925         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 926         enum pipe pipe = intel_dp->pps_pipe;
 927         bool pll_enabled, release_cl_override = false;
 928         enum dpio_phy phy = DPIO_PHY(pipe);
 929         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 930         u32 DP;
 931
 932         if (drm_WARN(&dev_priv->drm,
 933                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 934                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 935                      pipe_name(pipe), dig_port->base.base.base.id,
 936                      dig_port->base.base.name))
 937                 return;
 938
 939         drm_dbg_kms(&dev_priv->drm,
 940                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 941                     pipe_name(pipe), dig_port->base.base.base.id,
 942                     dig_port->base.base.name);
 943
 944         /* Preserve the BIOS-computed detected bit. This is
 945          * supposed to be read-only.
 946          */
 947         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 948         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 949         DP |= DP_PORT_WIDTH(1);
 950         DP |= DP_LINK_TRAIN_PAT_1;
 951
 952         if (IS_CHERRYVIEW(dev_priv))
 953                 DP |= DP_PIPE_SEL_CHV(pipe);
 954         else
 955                 DP |= DP_PIPE_SEL(pipe);
 956
 957         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 958
 959         /*
 960          * The DPLL for the pipe must be enabled for this to work.
 961          * So enable temporarily it if it's not already enabled.
 962          */
 963         if (!pll_enabled) {
 964                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 965                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 966
 967                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 968                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 969                         drm_err(&dev_priv->drm,
 970                                 "Failed to force on pll for pipe %c!\n",
 971                                 pipe_name(pipe));
 972                         return;
 973                 }
 974         }
 975
 976         /*
 977          * Similar magic as in intel_dp_enable_port().
 978          * We _must_ do this port enable + disable trick
 979          * to make this power sequencer lock onto the port.
 980          * Otherwise even VDD force bit won't work.
 981          */
 982         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 983         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 984
 985         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 986         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 987
 988         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 989         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 990
 991         if (!pll_enabled) {
 992                 vlv_force_pll_off(dev_priv, pipe);
 993
 994                 if (release_cl_override)
 995                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 996         }
 997 }
 998
 999 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
1000 {
1001         struct intel_encoder *encoder;
1002         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
1003
1004         /*
1005          * We don't have power sequencer currently.
1006          * Pick one that's not used by other ports.
1007          */
1008         for_each_intel_dp(&dev_priv->drm, encoder) {
1009                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1010
1011                 if (encoder->type == INTEL_OUTPUT_EDP) {
1012                         drm_WARN_ON(&dev_priv->drm,
1013                                     intel_dp->active_pipe != INVALID_PIPE &&
1014                                     intel_dp->active_pipe !=
1015                                     intel_dp->pps_pipe);
1016
1017                         if (intel_dp->pps_pipe != INVALID_PIPE)
1018                                 pipes &= ~(1 << intel_dp->pps_pipe);
1019                 } else {
1020                         drm_WARN_ON(&dev_priv->drm,
1021                                     intel_dp->pps_pipe != INVALID_PIPE);
1022
1023                         if (intel_dp->active_pipe != INVALID_PIPE)
1024                                 pipes &= ~(1 << intel_dp->active_pipe);
1025                 }
1026         }
1027
1028         if (pipes == 0)
1029                 return INVALID_PIPE;
1030
1031         return ffs(pipes) - 1;
1032 }
1033
1034 static enum pipe
1035 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
1036 {
1037         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1038         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1039         enum pipe pipe;
1040
1041         lockdep_assert_held(&dev_priv->pps_mutex);
1042
1043         /* We should never land here with regular DP ports */
1044         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1045
1046         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
1047                     intel_dp->active_pipe != intel_dp->pps_pipe);
1048
1049         if (intel_dp->pps_pipe != INVALID_PIPE)
1050                 return intel_dp->pps_pipe;
1051
1052         pipe = vlv_find_free_pps(dev_priv);
1053
1054         /*
1055          * Didn't find one. This should not happen since there
1056          * are two power sequencers and up to two eDP ports.
1057          */
1058         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
1059                 pipe = PIPE_A;
1060
1061         vlv_steal_power_sequencer(dev_priv, pipe);
1062         intel_dp->pps_pipe = pipe;
1063
1064         drm_dbg_kms(&dev_priv->drm,
1065                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
1066                     pipe_name(intel_dp->pps_pipe),
1067                     dig_port->base.base.base.id,
1068                     dig_port->base.base.name);
1069
1070         /* init power sequencer on this pipe and port */
1071         intel_dp_init_panel_power_sequencer(intel_dp);
1072         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
1073
1074         /*
1075          * Even vdd force doesn't work until we've made
1076          * the power sequencer lock in on the port.
1077          */
1078         vlv_power_sequencer_kick(intel_dp);
1079
1080         return intel_dp->pps_pipe;
1081 }
1082
1083 static int
1084 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
1085 {
1086         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1087         int backlight_controller = dev_priv->vbt.backlight.controller;
1088
1089         lockdep_assert_held(&dev_priv->pps_mutex);
1090
1091         /* We should never land here with regular DP ports */
1092         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1093
1094         if (!intel_dp->pps_reset)
1095                 return backlight_controller;
1096
1097         intel_dp->pps_reset = false;
1098
1099         /*
1100          * Only the HW needs to be reprogrammed, the SW state is fixed and
1101          * has been setup during connector init.
1102          */
1103         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1104
1105         return backlight_controller;
1106 }
1107
1108 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
1109                                enum pipe pipe);
1110
1111 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
1112                                enum pipe pipe)
1113 {
1114         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
1115 }
1116
1117 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
1118                                 enum pipe pipe)
1119 {
1120         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
1121 }
1122
1123 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
1124                          enum pipe pipe)
1125 {
1126         return true;
1127 }
1128
1129 static enum pipe
1130 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
1131                      enum port port,
1132                      vlv_pipe_check pipe_check)
1133 {
1134         enum pipe pipe;
1135
1136         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
1137                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
1138                         PANEL_PORT_SELECT_MASK;
1139
1140                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
1141                         continue;
1142
1143                 if (!pipe_check(dev_priv, pipe))
1144                         continue;
1145
1146                 return pipe;
1147         }
1148
1149         return INVALID_PIPE;
1150 }
1151
1152 static void
1153 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
1154 {
1155         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1156         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1157         enum port port = dig_port->base.port;
1158
1159         lockdep_assert_held(&dev_priv->pps_mutex);
1160
1161         /* try to find a pipe with this port selected */
1162         /* first pick one where the panel is on */
1163         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1164                                                   vlv_pipe_has_pp_on);
1165         /* didn't find one? pick one where vdd is on */
1166         if (intel_dp->pps_pipe == INVALID_PIPE)
1167                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1168                                                           vlv_pipe_has_vdd_on);
1169         /* didn't find one? pick one with just the correct port */
1170         if (intel_dp->pps_pipe == INVALID_PIPE)
1171                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1172                                                           vlv_pipe_any);
1173
1174         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1175         if (intel_dp->pps_pipe == INVALID_PIPE) {
1176                 drm_dbg_kms(&dev_priv->drm,
1177                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1178                             dig_port->base.base.base.id,
1179                             dig_port->base.base.name);
1180                 return;
1181         }
1182
1183         drm_dbg_kms(&dev_priv->drm,
1184                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1185                     dig_port->base.base.base.id,
1186                     dig_port->base.base.name,
1187                     pipe_name(intel_dp->pps_pipe));
1188
1189         intel_dp_init_panel_power_sequencer(intel_dp);
1190         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1191 }
1192
1193 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1194 {
1195         struct intel_encoder *encoder;
1196
1197         if (drm_WARN_ON(&dev_priv->drm,
1198                         !(IS_VALLEYVIEW(dev_priv) ||
1199                           IS_CHERRYVIEW(dev_priv) ||
1200                           IS_GEN9_LP(dev_priv))))
1201                 return;
1202
1203         /*
1204          * We can't grab pps_mutex here due to deadlock with power_domain
1205          * mutex when power_domain functions are called while holding pps_mutex.
1206          * That also means that in order to use pps_pipe the code needs to
1207          * hold both a power domain reference and pps_mutex, and the power domain
1208          * reference get/put must be done while _not_ holding pps_mutex.
1209          * pps_{lock,unlock}() do these steps in the correct order, so one
1210          * should use them always.
1211          */
1212
1213         for_each_intel_dp(&dev_priv->drm, encoder) {
1214                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1215
1216                 drm_WARN_ON(&dev_priv->drm,
1217                             intel_dp->active_pipe != INVALID_PIPE);
1218
1219                 if (encoder->type != INTEL_OUTPUT_EDP)
1220                         continue;
1221
1222                 if (IS_GEN9_LP(dev_priv))
1223                         intel_dp->pps_reset = true;
1224                 else
1225                         intel_dp->pps_pipe = INVALID_PIPE;
1226         }
1227 }
1228
1229 struct pps_registers {
1230         i915_reg_t pp_ctrl;
1231         i915_reg_t pp_stat;
1232         i915_reg_t pp_on;
1233         i915_reg_t pp_off;
1234         i915_reg_t pp_div;
1235 };
1236
1237 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1238                                     struct pps_registers *regs)
1239 {
1240         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1241         int pps_idx = 0;
1242
1243         memset(regs, 0, sizeof(*regs));
1244
1245         if (IS_GEN9_LP(dev_priv))
1246                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1247         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1248                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1249
1250         regs->pp_ctrl = PP_CONTROL(pps_idx);
1251         regs->pp_stat = PP_STATUS(pps_idx);
1252         regs->pp_on = PP_ON_DELAYS(pps_idx);
1253         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1254
1255         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1256         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1257                 regs->pp_div = INVALID_MMIO_REG;
1258         else
1259                 regs->pp_div = PP_DIVISOR(pps_idx);
1260 }
1261
1262 static i915_reg_t
1263 _pp_ctrl_reg(struct intel_dp *intel_dp)
1264 {
1265         struct pps_registers regs;
1266
1267         intel_pps_get_registers(intel_dp, &regs);
1268
1269         return regs.pp_ctrl;
1270 }
1271
1272 static i915_reg_t
1273 _pp_stat_reg(struct intel_dp *intel_dp)
1274 {
1275         struct pps_registers regs;
1276
1277         intel_pps_get_registers(intel_dp, &regs);
1278
1279         return regs.pp_stat;
1280 }
1281
1282 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1283 {
1284         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1285
1286         lockdep_assert_held(&dev_priv->pps_mutex);
1287
1288         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1289             intel_dp->pps_pipe == INVALID_PIPE)
1290                 return false;
1291
1292         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1293 }
1294
1295 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1296 {
1297         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1298
1299         lockdep_assert_held(&dev_priv->pps_mutex);
1300
1301         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1302             intel_dp->pps_pipe == INVALID_PIPE)
1303                 return false;
1304
1305         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1306 }
1307
1308 static void
1309 intel_dp_check_edp(struct intel_dp *intel_dp)
1310 {
1311         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1312
1313         if (!intel_dp_is_edp(intel_dp))
1314                 return;
1315
1316         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1317                 drm_WARN(&dev_priv->drm, 1,
1318                          "eDP powered off while attempting aux channel communication.\n");
1319                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1320                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1321                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1322         }
1323 }
1324
1325 static u32
1326 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1327 {
1328         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1329         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1330         const unsigned int timeout_ms = 10;
1331         u32 status;
1332         bool done;
1333
1334 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1335         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1336                                   msecs_to_jiffies_timeout(timeout_ms));
1337
1338         /* just trace the final value */
1339         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1340
1341         if (!done)
1342                 drm_err(&i915->drm,
1343                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1344                         intel_dp->aux.name, timeout_ms, status);
1345 #undef C
1346
1347         return status;
1348 }
1349
1350 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1351 {
1352         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1353
1354         if (index)
1355                 return 0;
1356
1357         /*
1358          * The clock divider is based off the hrawclk, and would like to run at
1359          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1360          */
1361         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1362 }
1363
1364 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1365 {
1366         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1367         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1368         u32 freq;
1369
1370         if (index)
1371                 return 0;
1372
1373         /*
1374          * The clock divider is based off the cdclk or PCH rawclk, and would
1375          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1376          * divide by 2000 and use that
1377          */
1378         if (dig_port->aux_ch == AUX_CH_A)
1379                 freq = dev_priv->cdclk.hw.cdclk;
1380         else
1381                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1382         return DIV_ROUND_CLOSEST(freq, 2000);
1383 }
1384
1385 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1386 {
1387         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1388         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1389
1390         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1391                 /* Workaround for non-ULT HSW */
1392                 switch (index) {
1393                 case 0: return 63;
1394                 case 1: return 72;
1395                 default: return 0;
1396                 }
1397         }
1398
1399         return ilk_get_aux_clock_divider(intel_dp, index);
1400 }
1401
1402 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1403 {
1404         /*
1405          * SKL doesn't need us to program the AUX clock divider (Hardware will
1406          * derive the clock from CDCLK automatically). We still implement the
1407          * get_aux_clock_divider vfunc to plug-in into the existing code.
1408          */
1409         return index ? 0 : 1;
1410 }
1411
1412 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1413                                 int send_bytes,
1414                                 u32 aux_clock_divider)
1415 {
1416         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1417         struct drm_i915_private *dev_priv =
1418                         to_i915(dig_port->base.base.dev);
1419         u32 precharge, timeout;
1420
1421         if (IS_GEN(dev_priv, 6))
1422                 precharge = 3;
1423         else
1424                 precharge = 5;
1425
1426         if (IS_BROADWELL(dev_priv))
1427                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1428         else
1429                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1430
1431         return DP_AUX_CH_CTL_SEND_BUSY |
1432                DP_AUX_CH_CTL_DONE |
1433                DP_AUX_CH_CTL_INTERRUPT |
1434                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1435                timeout |
1436                DP_AUX_CH_CTL_RECEIVE_ERROR |
1437                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1438                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1439                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1440 }
1441
1442 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1443                                 int send_bytes,
1444                                 u32 unused)
1445 {
1446         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1447         struct drm_i915_private *i915 =
1448                         to_i915(dig_port->base.base.dev);
1449         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1450         u32 ret;
1451
1452         ret = DP_AUX_CH_CTL_SEND_BUSY |
1453               DP_AUX_CH_CTL_DONE |
1454               DP_AUX_CH_CTL_INTERRUPT |
1455               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1456               DP_AUX_CH_CTL_TIME_OUT_MAX |
1457               DP_AUX_CH_CTL_RECEIVE_ERROR |
1458               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1459               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1460               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1461
1462         if (intel_phy_is_tc(i915, phy) &&
1463             dig_port->tc_mode == TC_PORT_TBT_ALT)
1464                 ret |= DP_AUX_CH_CTL_TBT_IO;
1465
1466         return ret;
1467 }
1468
1469 static int
1470 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1471                   const u8 *send, int send_bytes,
1472                   u8 *recv, int recv_size,
1473                   u32 aux_send_ctl_flags)
1474 {
1475         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1476         struct drm_i915_private *i915 =
1477                         to_i915(dig_port->base.base.dev);
1478         struct intel_uncore *uncore = &i915->uncore;
1479         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1480         bool is_tc_port = intel_phy_is_tc(i915, phy);
1481         i915_reg_t ch_ctl, ch_data[5];
1482         u32 aux_clock_divider;
1483         enum intel_display_power_domain aux_domain;
1484         intel_wakeref_t aux_wakeref;
1485         intel_wakeref_t pps_wakeref;
1486         int i, ret, recv_bytes;
1487         int try, clock = 0;
1488         u32 status;
1489         bool vdd;
1490
1491         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1492         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1493                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1494
1495         if (is_tc_port)
1496                 intel_tc_port_lock(dig_port);
1497
1498         aux_domain = intel_aux_power_domain(dig_port);
1499
1500         aux_wakeref = intel_display_power_get(i915, aux_domain);
1501         pps_wakeref = pps_lock(intel_dp);
1502
1503         /*
1504          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1505          * In such cases we want to leave VDD enabled and it's up to upper layers
1506          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1507          * ourselves.
1508          */
1509         vdd = edp_panel_vdd_on(intel_dp);
1510
1511         /* dp aux is extremely sensitive to irq latency, hence request the
1512          * lowest possible wakeup latency and so prevent the cpu from going into
1513          * deep sleep states.
1514          */
1515         cpu_latency_qos_update_request(&i915->pm_qos, 0);
1516
1517         intel_dp_check_edp(intel_dp);
1518
1519         /* Try to wait for any previous AUX channel activity */
1520         for (try = 0; try < 3; try++) {
1521                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1522                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1523                         break;
1524                 msleep(1);
1525         }
1526         /* just trace the final value */
1527         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1528
1529         if (try == 3) {
1530                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1531
1532                 if (status != intel_dp->aux_busy_last_status) {
1533                         drm_WARN(&i915->drm, 1,
1534                                  "%s: not started (status 0x%08x)\n",
1535                                  intel_dp->aux.name, status);
1536                         intel_dp->aux_busy_last_status = status;
1537                 }
1538
1539                 ret = -EBUSY;
1540                 goto out;
1541         }
1542
1543         /* Only 5 data registers! */
1544         if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1545                 ret = -E2BIG;
1546                 goto out;
1547         }
1548
1549         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1550                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1551                                                           send_bytes,
1552                                                           aux_clock_divider);
1553
1554                 send_ctl |= aux_send_ctl_flags;
1555
1556                 /* Must try at least 3 times according to DP spec */
1557                 for (try = 0; try < 5; try++) {
1558                         /* Load the send data into the aux channel data registers */
1559                         for (i = 0; i < send_bytes; i += 4)
1560                                 intel_uncore_write(uncore,
1561                                                    ch_data[i >> 2],
1562                                                    intel_dp_pack_aux(send + i,
1563                                                                      send_bytes - i));
1564
1565                         /* Send the command and wait for it to complete */
1566                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1567
1568                         status = intel_dp_aux_wait_done(intel_dp);
1569
1570                         /* Clear done status and any errors */
1571                         intel_uncore_write(uncore,
1572                                            ch_ctl,
1573                                            status |
1574                                            DP_AUX_CH_CTL_DONE |
1575                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1576                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1577
1578                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1579                          *   400us delay required for errors and timeouts
1580                          *   Timeout errors from the HW already meet this
1581                          *   requirement so skip to next iteration
1582                          */
1583                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1584                                 continue;
1585
1586                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1587                                 usleep_range(400, 500);
1588                                 continue;
1589                         }
1590                         if (status & DP_AUX_CH_CTL_DONE)
1591                                 goto done;
1592                 }
1593         }
1594
1595         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1596                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1597                         intel_dp->aux.name, status);
1598                 ret = -EBUSY;
1599                 goto out;
1600         }
1601
1602 done:
1603         /* Check for timeout or receive error.
1604          * Timeouts occur when the sink is not connected
1605          */
1606         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1607                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1608                         intel_dp->aux.name, status);
1609                 ret = -EIO;
1610                 goto out;
1611         }
1612
1613         /* Timeouts occur when the device isn't connected, so they're
1614          * "normal" -- don't fill the kernel log with these */
1615         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1616                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1617                             intel_dp->aux.name, status);
1618                 ret = -ETIMEDOUT;
1619                 goto out;
1620         }
1621
1622         /* Unload any bytes sent back from the other side */
1623         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1624                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1625
1626         /*
1627          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1628          * We have no idea of what happened so we return -EBUSY so
1629          * drm layer takes care for the necessary retries.
1630          */
1631         if (recv_bytes == 0 || recv_bytes > 20) {
1632                 drm_dbg_kms(&i915->drm,
1633                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1634                             intel_dp->aux.name, recv_bytes);
1635                 ret = -EBUSY;
1636                 goto out;
1637         }
1638
1639         if (recv_bytes > recv_size)
1640                 recv_bytes = recv_size;
1641
1642         for (i = 0; i < recv_bytes; i += 4)
1643                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1644                                     recv + i, recv_bytes - i);
1645
1646         ret = recv_bytes;
1647 out:
1648         cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1649
1650         if (vdd)
1651                 edp_panel_vdd_off(intel_dp, false);
1652
1653         pps_unlock(intel_dp, pps_wakeref);
1654         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1655
1656         if (is_tc_port)
1657                 intel_tc_port_unlock(dig_port);
1658
1659         return ret;
1660 }
1661
1662 #define BARE_ADDRESS_SIZE       3
1663 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1664
1665 static void
1666 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1667                     const struct drm_dp_aux_msg *msg)
1668 {
1669         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1670         txbuf[1] = (msg->address >> 8) & 0xff;
1671         txbuf[2] = msg->address & 0xff;
1672         txbuf[3] = msg->size - 1;
1673 }
1674
1675 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
1676 {
1677         /*
1678          * If we're trying to send the HDCP Aksv, we need to set a the Aksv
1679          * select bit to inform the hardware to send the Aksv after our header
1680          * since we can't access that data from software.
1681          */
1682         if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
1683             msg->address == DP_AUX_HDCP_AKSV)
1684                 return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
1685
1686         return 0;
1687 }
1688
1689 static ssize_t
1690 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1691 {
1692         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1693         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1694         u8 txbuf[20], rxbuf[20];
1695         size_t txsize, rxsize;
1696         u32 flags = intel_dp_aux_xfer_flags(msg);
1697         int ret;
1698
1699         intel_dp_aux_header(txbuf, msg);
1700
1701         switch (msg->request & ~DP_AUX_I2C_MOT) {
1702         case DP_AUX_NATIVE_WRITE:
1703         case DP_AUX_I2C_WRITE:
1704         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1705                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1706                 rxsize = 2; /* 0 or 1 data bytes */
1707
1708                 if (drm_WARN_ON(&i915->drm, txsize > 20))
1709                         return -E2BIG;
1710
1711                 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
1712
1713                 if (msg->buffer)
1714                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1715
1716                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1717                                         rxbuf, rxsize, flags);
1718                 if (ret > 0) {
1719                         msg->reply = rxbuf[0] >> 4;
1720
1721                         if (ret > 1) {
1722                                 /* Number of bytes written in a short write. */
1723                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1724                         } else {
1725                                 /* Return payload size. */
1726                                 ret = msg->size;
1727                         }
1728                 }
1729                 break;
1730
1731         case DP_AUX_NATIVE_READ:
1732         case DP_AUX_I2C_READ:
1733                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1734                 rxsize = msg->size + 1;
1735
1736                 if (drm_WARN_ON(&i915->drm, rxsize > 20))
1737                         return -E2BIG;
1738
1739                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1740                                         rxbuf, rxsize, flags);
1741                 if (ret > 0) {
1742                         msg->reply = rxbuf[0] >> 4;
1743                         /*
1744                          * Assume happy day, and copy the data. The caller is
1745                          * expected to check msg->reply before touching it.
1746                          *
1747                          * Return payload size.
1748                          */
1749                         ret--;
1750                         memcpy(msg->buffer, rxbuf + 1, ret);
1751                 }
1752                 break;
1753
1754         default:
1755                 ret = -EINVAL;
1756                 break;
1757         }
1758
1759         return ret;
1760 }
1761
1762
1763 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1764 {
1765         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1766         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1767         enum aux_ch aux_ch = dig_port->aux_ch;
1768
1769         switch (aux_ch) {
1770         case AUX_CH_B:
1771         case AUX_CH_C:
1772         case AUX_CH_D:
1773                 return DP_AUX_CH_CTL(aux_ch);
1774         default:
1775                 MISSING_CASE(aux_ch);
1776                 return DP_AUX_CH_CTL(AUX_CH_B);
1777         }
1778 }
1779
1780 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1781 {
1782         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1783         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1784         enum aux_ch aux_ch = dig_port->aux_ch;
1785
1786         switch (aux_ch) {
1787         case AUX_CH_B:
1788         case AUX_CH_C:
1789         case AUX_CH_D:
1790                 return DP_AUX_CH_DATA(aux_ch, index);
1791         default:
1792                 MISSING_CASE(aux_ch);
1793                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1794         }
1795 }
1796
1797 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1798 {
1799         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1800         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1801         enum aux_ch aux_ch = dig_port->aux_ch;
1802
1803         switch (aux_ch) {
1804         case AUX_CH_A:
1805                 return DP_AUX_CH_CTL(aux_ch);
1806         case AUX_CH_B:
1807         case AUX_CH_C:
1808         case AUX_CH_D:
1809                 return PCH_DP_AUX_CH_CTL(aux_ch);
1810         default:
1811                 MISSING_CASE(aux_ch);
1812                 return DP_AUX_CH_CTL(AUX_CH_A);
1813         }
1814 }
1815
1816 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1817 {
1818         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1819         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1820         enum aux_ch aux_ch = dig_port->aux_ch;
1821
1822         switch (aux_ch) {
1823         case AUX_CH_A:
1824                 return DP_AUX_CH_DATA(aux_ch, index);
1825         case AUX_CH_B:
1826         case AUX_CH_C:
1827         case AUX_CH_D:
1828                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1829         default:
1830                 MISSING_CASE(aux_ch);
1831                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1832         }
1833 }
1834
1835 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1836 {
1837         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1838         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1839         enum aux_ch aux_ch = dig_port->aux_ch;
1840
1841         switch (aux_ch) {
1842         case AUX_CH_A:
1843         case AUX_CH_B:
1844         case AUX_CH_C:
1845         case AUX_CH_D:
1846         case AUX_CH_E:
1847         case AUX_CH_F:
1848                 return DP_AUX_CH_CTL(aux_ch);
1849         default:
1850                 MISSING_CASE(aux_ch);
1851                 return DP_AUX_CH_CTL(AUX_CH_A);
1852         }
1853 }
1854
1855 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1856 {
1857         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1858         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1859         enum aux_ch aux_ch = dig_port->aux_ch;
1860
1861         switch (aux_ch) {
1862         case AUX_CH_A:
1863         case AUX_CH_B:
1864         case AUX_CH_C:
1865         case AUX_CH_D:
1866         case AUX_CH_E:
1867         case AUX_CH_F:
1868                 return DP_AUX_CH_DATA(aux_ch, index);
1869         default:
1870                 MISSING_CASE(aux_ch);
1871                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1872         }
1873 }
1874
1875 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
1876 {
1877         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1878         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1879         enum aux_ch aux_ch = dig_port->aux_ch;
1880
1881         switch (aux_ch) {
1882         case AUX_CH_A:
1883         case AUX_CH_B:
1884         case AUX_CH_C:
1885         case AUX_CH_USBC1:
1886         case AUX_CH_USBC2:
1887         case AUX_CH_USBC3:
1888         case AUX_CH_USBC4:
1889         case AUX_CH_USBC5:
1890         case AUX_CH_USBC6:
1891                 return DP_AUX_CH_CTL(aux_ch);
1892         default:
1893                 MISSING_CASE(aux_ch);
1894                 return DP_AUX_CH_CTL(AUX_CH_A);
1895         }
1896 }
1897
1898 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
1899 {
1900         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1901         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1902         enum aux_ch aux_ch = dig_port->aux_ch;
1903
1904         switch (aux_ch) {
1905         case AUX_CH_A:
1906         case AUX_CH_B:
1907         case AUX_CH_C:
1908         case AUX_CH_USBC1:
1909         case AUX_CH_USBC2:
1910         case AUX_CH_USBC3:
1911         case AUX_CH_USBC4:
1912         case AUX_CH_USBC5:
1913         case AUX_CH_USBC6:
1914                 return DP_AUX_CH_DATA(aux_ch, index);
1915         default:
1916                 MISSING_CASE(aux_ch);
1917                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1918         }
1919 }
1920
1921 static void
1922 intel_dp_aux_fini(struct intel_dp *intel_dp)
1923 {
1924         kfree(intel_dp->aux.name);
1925 }
1926
1927 static void
1928 intel_dp_aux_init(struct intel_dp *intel_dp)
1929 {
1930         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1931         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1932         struct intel_encoder *encoder = &dig_port->base;
1933         enum aux_ch aux_ch = dig_port->aux_ch;
1934
1935         if (INTEL_GEN(dev_priv) >= 12) {
1936                 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
1937                 intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
1938         } else if (INTEL_GEN(dev_priv) >= 9) {
1939                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1940                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1941         } else if (HAS_PCH_SPLIT(dev_priv)) {
1942                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1943                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1944         } else {
1945                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1946                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1947         }
1948
1949         if (INTEL_GEN(dev_priv) >= 9)
1950                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1951         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1952                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1953         else if (HAS_PCH_SPLIT(dev_priv))
1954                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1955         else
1956                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1957
1958         if (INTEL_GEN(dev_priv) >= 9)
1959                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1960         else
1961                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1962
1963         drm_dp_aux_init(&intel_dp->aux);
1964
1965         /* Failure to allocate our preferred name is not critical */
1966         if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
1967                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
1968                                                aux_ch - AUX_CH_USBC1 + '1',
1969                                                encoder->base.name);
1970         else
1971                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
1972                                                aux_ch_name(aux_ch),
1973                                                encoder->base.name);
1974
1975         intel_dp->aux.transfer = intel_dp_aux_transfer;
1976 }
1977
1978 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1979 {
1980         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1981
1982         return max_rate >= 540000;
1983 }
1984
1985 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1986 {
1987         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1988
1989         return max_rate >= 810000;
1990 }
1991
1992 static void
1993 intel_dp_set_clock(struct intel_encoder *encoder,
1994                    struct intel_crtc_state *pipe_config)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1997         const struct dp_link_dpll *divisor = NULL;
1998         int i, count = 0;
1999
2000         if (IS_G4X(dev_priv)) {
2001                 divisor = g4x_dpll;
2002                 count = ARRAY_SIZE(g4x_dpll);
2003         } else if (HAS_PCH_SPLIT(dev_priv)) {
2004                 divisor = pch_dpll;
2005                 count = ARRAY_SIZE(pch_dpll);
2006         } else if (IS_CHERRYVIEW(dev_priv)) {
2007                 divisor = chv_dpll;
2008                 count = ARRAY_SIZE(chv_dpll);
2009         } else if (IS_VALLEYVIEW(dev_priv)) {
2010                 divisor = vlv_dpll;
2011                 count = ARRAY_SIZE(vlv_dpll);
2012         }
2013
2014         if (divisor && count) {
2015                 for (i = 0; i < count; i++) {
2016                         if (pipe_config->port_clock == divisor[i].clock) {
2017                                 pipe_config->dpll = divisor[i].dpll;
2018                                 pipe_config->clock_set = true;
2019                                 break;
2020                         }
2021                 }
2022         }
2023 }
2024
2025 static void snprintf_int_array(char *str, size_t len,
2026                                const int *array, int nelem)
2027 {
2028         int i;
2029
2030         str[0] = '\0';
2031
2032         for (i = 0; i < nelem; i++) {
2033                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
2034                 if (r >= len)
2035                         return;
2036                 str += r;
2037                 len -= r;
2038         }
2039 }
2040
2041 static void intel_dp_print_rates(struct intel_dp *intel_dp)
2042 {
2043         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2044         char str[128]; /* FIXME: too big for stack? */
2045
2046         if (!drm_debug_enabled(DRM_UT_KMS))
2047                 return;
2048
2049         snprintf_int_array(str, sizeof(str),
2050                            intel_dp->source_rates, intel_dp->num_source_rates);
2051         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
2052
2053         snprintf_int_array(str, sizeof(str),
2054                            intel_dp->sink_rates, intel_dp->num_sink_rates);
2055         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
2056
2057         snprintf_int_array(str, sizeof(str),
2058                            intel_dp->common_rates, intel_dp->num_common_rates);
2059         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
2060 }
2061
2062 int
2063 intel_dp_max_link_rate(struct intel_dp *intel_dp)
2064 {
2065         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2066         int len;
2067
2068         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
2069         if (drm_WARN_ON(&i915->drm, len <= 0))
2070                 return 162000;
2071
2072         return intel_dp->common_rates[len - 1];
2073 }
2074
2075 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
2076 {
2077         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2078         int i = intel_dp_rate_index(intel_dp->sink_rates,
2079                                     intel_dp->num_sink_rates, rate);
2080
2081         if (drm_WARN_ON(&i915->drm, i < 0))
2082                 i = 0;
2083
2084         return i;
2085 }
2086
2087 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
2088                            u8 *link_bw, u8 *rate_select)
2089 {
2090         /* eDP 1.4 rate select method. */
2091         if (intel_dp->use_rate_select) {
2092                 *link_bw = 0;
2093                 *rate_select =
2094                         intel_dp_rate_select(intel_dp, port_clock);
2095         } else {
2096                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
2097                 *rate_select = 0;
2098         }
2099 }
2100
2101 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
2102                                          const struct intel_crtc_state *pipe_config)
2103 {
2104         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2105
2106         /* On TGL, FEC is supported on all Pipes */
2107         if (INTEL_GEN(dev_priv) >= 12)
2108                 return true;
2109
2110         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
2111                 return true;
2112
2113         return false;
2114 }
2115
2116 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
2117                                   const struct intel_crtc_state *pipe_config)
2118 {
2119         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
2120                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
2121 }
2122
2123 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
2124                                   const struct intel_crtc_state *crtc_state)
2125 {
2126         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
2127                 return false;
2128
2129         return intel_dsc_source_support(crtc_state) &&
2130                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
2131 }
2132
2133 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
2134                                    const struct intel_crtc_state *crtc_state)
2135 {
2136         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2137                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2138                  intel_dp->dfp.ycbcr_444_to_420);
2139 }
2140
2141 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
2142                                     const struct intel_crtc_state *crtc_state, int bpc)
2143 {
2144         int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
2145
2146         if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
2147                 clock /= 2;
2148
2149         return clock;
2150 }
2151
2152 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
2153                                            const struct intel_crtc_state *crtc_state, int bpc)
2154 {
2155         int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
2156
2157         if (intel_dp->dfp.min_tmds_clock &&
2158             tmds_clock < intel_dp->dfp.min_tmds_clock)
2159                 return false;
2160
2161         if (intel_dp->dfp.max_tmds_clock &&
2162             tmds_clock > intel_dp->dfp.max_tmds_clock)
2163                 return false;
2164
2165         return true;
2166 }
2167
2168 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
2169                                               const struct intel_crtc_state *crtc_state,
2170                                               int bpc)
2171 {
2172
2173         return intel_hdmi_deep_color_possible(crtc_state, bpc,
2174                                               intel_dp->has_hdmi_sink,
2175                                               intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
2176                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
2177 }
2178
2179 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
2180                             const struct intel_crtc_state *crtc_state)
2181 {
2182         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2183         struct intel_connector *intel_connector = intel_dp->attached_connector;
2184         int bpp, bpc;
2185
2186         bpc = crtc_state->pipe_bpp / 3;
2187
2188         if (intel_dp->dfp.max_bpc)
2189                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
2190
2191         if (intel_dp->dfp.min_tmds_clock) {
2192                 for (; bpc >= 10; bpc -= 2) {
2193                         if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
2194                                 break;
2195                 }
2196         }
2197
2198         bpp = bpc * 3;
2199         if (intel_dp_is_edp(intel_dp)) {
2200                 /* Get bpp from vbt only for panels that dont have bpp in edid */
2201                 if (intel_connector->base.display_info.bpc == 0 &&
2202                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
2203                         drm_dbg_kms(&dev_priv->drm,
2204                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
2205                                     dev_priv->vbt.edp.bpp);
2206                         bpp = dev_priv->vbt.edp.bpp;
2207                 }
2208         }
2209
2210         return bpp;
2211 }
2212
2213 /* Adjust link config limits based on compliance test requests. */
2214 void
2215 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
2216                                   struct intel_crtc_state *pipe_config,
2217                                   struct link_config_limits *limits)
2218 {
2219         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2220
2221         /* For DP Compliance we override the computed bpp for the pipe */
2222         if (intel_dp->compliance.test_data.bpc != 0) {
2223                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
2224
2225                 limits->min_bpp = limits->max_bpp = bpp;
2226                 pipe_config->dither_force_disable = bpp == 6 * 3;
2227
2228                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
2229         }
2230
2231         /* Use values requested by Compliance Test Request */
2232         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
2233                 int index;
2234
2235                 /* Validate the compliance test data since max values
2236                  * might have changed due to link train fallback.
2237                  */
2238                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
2239                                                intel_dp->compliance.test_lane_count)) {
2240                         index = intel_dp_rate_index(intel_dp->common_rates,
2241                                                     intel_dp->num_common_rates,
2242                                                     intel_dp->compliance.test_link_rate);
2243                         if (index >= 0)
2244                                 limits->min_clock = limits->max_clock = index;
2245                         limits->min_lane_count = limits->max_lane_count =
2246                                 intel_dp->compliance.test_lane_count;
2247                 }
2248         }
2249 }
2250
2251 /* Optimize link config in order: max bpp, min clock, min lanes */
2252 static int
2253 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2254                                   struct intel_crtc_state *pipe_config,
2255                                   const struct link_config_limits *limits)
2256 {
2257         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2258         int bpp, clock, lane_count;
2259         int mode_rate, link_clock, link_avail;
2260
2261         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2262                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
2263
2264                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2265                                                    output_bpp);
2266
2267                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2268                         for (lane_count = limits->min_lane_count;
2269                              lane_count <= limits->max_lane_count;
2270                              lane_count <<= 1) {
2271                                 link_clock = intel_dp->common_rates[clock];
2272                                 link_avail = intel_dp_max_data_rate(link_clock,
2273                                                                     lane_count);
2274
2275                                 if (mode_rate <= link_avail) {
2276                                         pipe_config->lane_count = lane_count;
2277                                         pipe_config->pipe_bpp = bpp;
2278                                         pipe_config->port_clock = link_clock;
2279
2280                                         return 0;
2281                                 }
2282                         }
2283                 }
2284         }
2285
2286         return -EINVAL;
2287 }
2288
2289 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2290 {
2291         int i, num_bpc;
2292         u8 dsc_bpc[3] = {0};
2293
2294         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2295                                                        dsc_bpc);
2296         for (i = 0; i < num_bpc; i++) {
2297                 if (dsc_max_bpc >= dsc_bpc[i])
2298                         return dsc_bpc[i] * 3;
2299         }
2300
2301         return 0;
2302 }
2303
2304 #define DSC_SUPPORTED_VERSION_MIN               1
2305
2306 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2307                                        struct intel_crtc_state *crtc_state)
2308 {
2309         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2310         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2311         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2312         u8 line_buf_depth;
2313         int ret;
2314
2315         ret = intel_dsc_compute_params(encoder, crtc_state);
2316         if (ret)
2317                 return ret;
2318
2319         /*
2320          * Slice Height of 8 works for all currently available panels. So start
2321          * with that if pic_height is an integral multiple of 8. Eventually add
2322          * logic to try multiple slice heights.
2323          */
2324         if (vdsc_cfg->pic_height % 8 == 0)
2325                 vdsc_cfg->slice_height = 8;
2326         else if (vdsc_cfg->pic_height % 4 == 0)
2327                 vdsc_cfg->slice_height = 4;
2328         else
2329                 vdsc_cfg->slice_height = 2;
2330
2331         vdsc_cfg->dsc_version_major =
2332                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2333                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2334         vdsc_cfg->dsc_version_minor =
2335                 min(DSC_SUPPORTED_VERSION_MIN,
2336                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2337                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2338
2339         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2340                 DP_DSC_RGB;
2341
2342         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2343         if (!line_buf_depth) {
2344                 drm_dbg_kms(&i915->drm,
2345                             "DSC Sink Line Buffer Depth invalid\n");
2346                 return -EINVAL;
2347         }
2348
2349         if (vdsc_cfg->dsc_version_minor == 2)
2350                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2351                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2352         else
2353                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2354                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2355
2356         vdsc_cfg->block_pred_enable =
2357                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2358                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2359
2360         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2361 }
2362
2363 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2364                                        struct intel_crtc_state *pipe_config,
2365                                        struct drm_connector_state *conn_state,
2366                                        struct link_config_limits *limits)
2367 {
2368         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2369         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2370         const struct drm_display_mode *adjusted_mode =
2371                 &pipe_config->hw.adjusted_mode;
2372         u8 dsc_max_bpc;
2373         int pipe_bpp;
2374         int ret;
2375
2376         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2377                 intel_dp_supports_fec(intel_dp, pipe_config);
2378
2379         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2380                 return -EINVAL;
2381
2382         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2383         if (INTEL_GEN(dev_priv) >= 12)
2384                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2385         else
2386                 dsc_max_bpc = min_t(u8, 10,
2387                                     conn_state->max_requested_bpc);
2388
2389         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2390
2391         /* Min Input BPC for ICL+ is 8 */
2392         if (pipe_bpp < 8 * 3) {
2393                 drm_dbg_kms(&dev_priv->drm,
2394                             "No DSC support for less than 8bpc\n");
2395                 return -EINVAL;
2396         }
2397
2398         /*
2399          * For now enable DSC for max bpp, max link rate, max lane count.
2400          * Optimize this later for the minimum possible link rate/lane count
2401          * with DSC enabled for the requested mode.
2402          */
2403         pipe_config->pipe_bpp = pipe_bpp;
2404         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2405         pipe_config->lane_count = limits->max_lane_count;
2406
2407         if (intel_dp_is_edp(intel_dp)) {
2408                 pipe_config->dsc.compressed_bpp =
2409                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2410                               pipe_config->pipe_bpp);
2411                 pipe_config->dsc.slice_count =
2412                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2413                                                         true);
2414         } else {
2415                 u16 dsc_max_output_bpp;
2416                 u8 dsc_dp_slice_count;
2417
2418                 dsc_max_output_bpp =
2419                         intel_dp_dsc_get_output_bpp(dev_priv,
2420                                                     pipe_config->port_clock,
2421                                                     pipe_config->lane_count,
2422                                                     adjusted_mode->crtc_clock,
2423                                                     adjusted_mode->crtc_hdisplay,
2424                                                     pipe_config->bigjoiner);
2425                 dsc_dp_slice_count =
2426                         intel_dp_dsc_get_slice_count(intel_dp,
2427                                                      adjusted_mode->crtc_clock,
2428                                                      adjusted_mode->crtc_hdisplay,
2429                                                      pipe_config->bigjoiner);
2430                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2431                         drm_dbg_kms(&dev_priv->drm,
2432                                     "Compressed BPP/Slice Count not supported\n");
2433                         return -EINVAL;
2434                 }
2435                 pipe_config->dsc.compressed_bpp = min_t(u16,
2436                                                                dsc_max_output_bpp >> 4,
2437                                                                pipe_config->pipe_bpp);
2438                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2439         }
2440         /*
2441          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2442          * is greater than the maximum Cdclock and if slice count is even
2443          * then we need to use 2 VDSC instances.
2444          */
2445         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
2446             pipe_config->bigjoiner) {
2447                 if (pipe_config->dsc.slice_count < 2) {
2448                         drm_dbg_kms(&dev_priv->drm,
2449                                     "Cannot split stream to use 2 VDSC instances\n");
2450                         return -EINVAL;
2451                 }
2452
2453                 pipe_config->dsc.dsc_split = true;
2454         }
2455
2456         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2457         if (ret < 0) {
2458                 drm_dbg_kms(&dev_priv->drm,
2459                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2460                             "Compressed BPP = %d\n",
2461                             pipe_config->pipe_bpp,
2462                             pipe_config->dsc.compressed_bpp);
2463                 return ret;
2464         }
2465
2466         pipe_config->dsc.compression_enable = true;
2467         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2468                     "Compressed Bpp = %d Slice Count = %d\n",
2469                     pipe_config->pipe_bpp,
2470                     pipe_config->dsc.compressed_bpp,
2471                     pipe_config->dsc.slice_count);
2472
2473         return 0;
2474 }
2475
2476 static int
2477 intel_dp_compute_link_config(struct intel_encoder *encoder,
2478                              struct intel_crtc_state *pipe_config,
2479                              struct drm_connector_state *conn_state)
2480 {
2481         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2482         const struct drm_display_mode *adjusted_mode =
2483                 &pipe_config->hw.adjusted_mode;
2484         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2485         struct link_config_limits limits;
2486         int common_len;
2487         int ret;
2488
2489         common_len = intel_dp_common_len_rate_limit(intel_dp,
2490                                                     intel_dp->max_link_rate);
2491
2492         /* No common link rates between source and sink */
2493         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2494
2495         limits.min_clock = 0;
2496         limits.max_clock = common_len - 1;
2497
2498         limits.min_lane_count = 1;
2499         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2500
2501         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
2502         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
2503
2504         if (intel_dp_is_edp(intel_dp)) {
2505                 /*
2506                  * Use the maximum clock and number of lanes the eDP panel
2507                  * advertizes being capable of. The panels are generally
2508                  * designed to support only a single clock and lane
2509                  * configuration, and typically these values correspond to the
2510                  * native resolution of the panel.
2511                  */
2512                 limits.min_lane_count = limits.max_lane_count;
2513                 limits.min_clock = limits.max_clock;
2514         }
2515
2516         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2517
2518         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2519                     "max rate %d max bpp %d pixel clock %iKHz\n",
2520                     limits.max_lane_count,
2521                     intel_dp->common_rates[limits.max_clock],
2522                     limits.max_bpp, adjusted_mode->crtc_clock);
2523
2524         if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
2525              adjusted_mode->crtc_hdisplay > 5120) &&
2526             intel_dp_can_bigjoiner(intel_dp))
2527                 pipe_config->bigjoiner = true;
2528
2529         /*
2530          * Optimize for slow and wide. This is the place to add alternative
2531          * optimization policy.
2532          */
2533         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2534
2535         /* enable compression if the mode doesn't fit available BW */
2536         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2537         if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
2538                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2539                                                   conn_state, &limits);
2540                 if (ret < 0)
2541                         return ret;
2542         }
2543
2544         if (pipe_config->dsc.compression_enable) {
2545                 drm_dbg_kms(&i915->drm,
2546                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2547                             pipe_config->lane_count, pipe_config->port_clock,
2548                             pipe_config->pipe_bpp,
2549                             pipe_config->dsc.compressed_bpp);
2550
2551                 drm_dbg_kms(&i915->drm,
2552                             "DP link rate required %i available %i\n",
2553                             intel_dp_link_required(adjusted_mode->crtc_clock,
2554                                                    pipe_config->dsc.compressed_bpp),
2555                             intel_dp_max_data_rate(pipe_config->port_clock,
2556                                                    pipe_config->lane_count));
2557         } else {
2558                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2559                             pipe_config->lane_count, pipe_config->port_clock,
2560                             pipe_config->pipe_bpp);
2561
2562                 drm_dbg_kms(&i915->drm,
2563                             "DP link rate required %i available %i\n",
2564                             intel_dp_link_required(adjusted_mode->crtc_clock,
2565                                                    pipe_config->pipe_bpp),
2566                             intel_dp_max_data_rate(pipe_config->port_clock,
2567                                                    pipe_config->lane_count));
2568         }
2569         return 0;
2570 }
2571
2572 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2573                                   const struct drm_connector_state *conn_state)
2574 {
2575         const struct intel_digital_connector_state *intel_conn_state =
2576                 to_intel_digital_connector_state(conn_state);
2577         const struct drm_display_mode *adjusted_mode =
2578                 &crtc_state->hw.adjusted_mode;
2579
2580         /*
2581          * Our YCbCr output is always limited range.
2582          * crtc_state->limited_color_range only applies to RGB,
2583          * and it must never be set for YCbCr or we risk setting
2584          * some conflicting bits in PIPECONF which will mess up
2585          * the colors on the monitor.
2586          */
2587         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2588                 return false;
2589
2590         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2591                 /*
2592                  * See:
2593                  * CEA-861-E - 5.1 Default Encoding Parameters
2594                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2595                  */
2596                 return crtc_state->pipe_bpp != 18 &&
2597                         drm_default_rgb_quant_range(adjusted_mode) ==
2598                         HDMI_QUANTIZATION_RANGE_LIMITED;
2599         } else {
2600                 return intel_conn_state->broadcast_rgb ==
2601                         INTEL_BROADCAST_RGB_LIMITED;
2602         }
2603 }
2604
2605 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2606                                     enum port port)
2607 {
2608         if (IS_G4X(dev_priv))
2609                 return false;
2610         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2611                 return false;
2612
2613         return true;
2614 }
2615
2616 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2617                                              const struct drm_connector_state *conn_state,
2618                                              struct drm_dp_vsc_sdp *vsc)
2619 {
2620         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2621         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2622
2623         /*
2624          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2625          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2626          * Colorimetry Format indication.
2627          */
2628         vsc->revision = 0x5;
2629         vsc->length = 0x13;
2630
2631         /* DP 1.4a spec, Table 2-120 */
2632         switch (crtc_state->output_format) {
2633         case INTEL_OUTPUT_FORMAT_YCBCR444:
2634                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2635                 break;
2636         case INTEL_OUTPUT_FORMAT_YCBCR420:
2637                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2638                 break;
2639         case INTEL_OUTPUT_FORMAT_RGB:
2640         default:
2641                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2642         }
2643
2644         switch (conn_state->colorspace) {
2645         case DRM_MODE_COLORIMETRY_BT709_YCC:
2646                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2647                 break;
2648         case DRM_MODE_COLORIMETRY_XVYCC_601:
2649                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2650                 break;
2651         case DRM_MODE_COLORIMETRY_XVYCC_709:
2652                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2653                 break;
2654         case DRM_MODE_COLORIMETRY_SYCC_601:
2655                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2656                 break;
2657         case DRM_MODE_COLORIMETRY_OPYCC_601:
2658                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2659                 break;
2660         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2661                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2662                 break;
2663         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2664                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2665                 break;
2666         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2667                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2668                 break;
2669         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2670         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2671                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2672                 break;
2673         default:
2674                 /*
2675                  * RGB->YCBCR color conversion uses the BT.709
2676                  * color space.
2677                  */
2678                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2679                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2680                 else
2681                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2682                 break;
2683         }
2684
2685         vsc->bpc = crtc_state->pipe_bpp / 3;
2686
2687         /* only RGB pixelformat supports 6 bpc */
2688         drm_WARN_ON(&dev_priv->drm,
2689                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2690
2691         /* all YCbCr are always limited range */
2692         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2693         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2694 }
2695
2696 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2697                                      struct intel_crtc_state *crtc_state,
2698                                      const struct drm_connector_state *conn_state)
2699 {
2700         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2701
2702         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2703         if (crtc_state->has_psr)
2704                 return;
2705
2706         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2707                 return;
2708
2709         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2710         vsc->sdp_type = DP_SDP_VSC;
2711         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2712                                          &crtc_state->infoframes.vsc);
2713 }
2714
2715 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2716                                   const struct intel_crtc_state *crtc_state,
2717                                   const struct drm_connector_state *conn_state,
2718                                   struct drm_dp_vsc_sdp *vsc)
2719 {
2720         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2721
2722         vsc->sdp_type = DP_SDP_VSC;
2723
2724         if (dev_priv->psr.psr2_enabled) {
2725                 if (dev_priv->psr.colorimetry_support &&
2726                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2727                         /* [PSR2, +Colorimetry] */
2728                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2729                                                          vsc);
2730                 } else {
2731                         /*
2732                          * [PSR2, -Colorimetry]
2733                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2734                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2735                          */
2736                         vsc->revision = 0x4;
2737                         vsc->length = 0xe;
2738                 }
2739         } else {
2740                 /*
2741                  * [PSR1]
2742                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2743                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2744                  * higher).
2745                  */
2746                 vsc->revision = 0x2;
2747                 vsc->length = 0x8;
2748         }
2749 }
2750
2751 static void
2752 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2753                                             struct intel_crtc_state *crtc_state,
2754                                             const struct drm_connector_state *conn_state)
2755 {
2756         int ret;
2757         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2758         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2759
2760         if (!conn_state->hdr_output_metadata)
2761                 return;
2762
2763         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2764
2765         if (ret) {
2766                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2767                 return;
2768         }
2769
2770         crtc_state->infoframes.enable |=
2771                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2772 }
2773
2774 static void
2775 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
2776                              struct intel_crtc_state *pipe_config,
2777                              int output_bpp, bool constant_n)
2778 {
2779         struct intel_connector *intel_connector = intel_dp->attached_connector;
2780         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2781
2782         /*
2783          * DRRS and PSR can't be enable together, so giving preference to PSR
2784          * as it allows more power-savings by complete shutting down display,
2785          * so to guarantee this, intel_dp_drrs_compute_config() must be called
2786          * after intel_psr_compute_config().
2787          */
2788         if (pipe_config->has_psr)
2789                 return;
2790
2791         if (!intel_connector->panel.downclock_mode ||
2792             dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
2793                 return;
2794
2795         pipe_config->has_drrs = true;
2796         intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
2797                                intel_connector->panel.downclock_mode->clock,
2798                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2799                                constant_n, pipe_config->fec_enable);
2800 }
2801
2802 int
2803 intel_dp_compute_config(struct intel_encoder *encoder,
2804                         struct intel_crtc_state *pipe_config,
2805                         struct drm_connector_state *conn_state)
2806 {
2807         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2808         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2809         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2810         enum port port = encoder->port;
2811         struct intel_connector *intel_connector = intel_dp->attached_connector;
2812         struct intel_digital_connector_state *intel_conn_state =
2813                 to_intel_digital_connector_state(conn_state);
2814         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2815                                            DP_DPCD_QUIRK_CONSTANT_N);
2816         int ret = 0, output_bpp;
2817
2818         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2819                 pipe_config->has_pch_encoder = true;
2820
2821         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
2822                                                             adjusted_mode);
2823
2824         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2825                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2826                 if (ret)
2827                         return ret;
2828         }
2829
2830         if (!intel_dp_port_has_audio(dev_priv, port))
2831                 pipe_config->has_audio = false;
2832         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2833                 pipe_config->has_audio = intel_dp->has_audio;
2834         else
2835                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2836
2837         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2838                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2839                                        adjusted_mode);
2840
2841                 if (HAS_GMCH(dev_priv))
2842                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
2843                 else
2844                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
2845                 if (ret)
2846                         return ret;
2847         }
2848
2849         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2850                 return -EINVAL;
2851
2852         if (HAS_GMCH(dev_priv) &&
2853             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2854                 return -EINVAL;
2855
2856         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2857                 return -EINVAL;
2858
2859         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2860                 return -EINVAL;
2861
2862         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2863         if (ret < 0)
2864                 return ret;
2865
2866         pipe_config->limited_color_range =
2867                 intel_dp_limited_color_range(pipe_config, conn_state);
2868
2869         if (pipe_config->dsc.compression_enable)
2870                 output_bpp = pipe_config->dsc.compressed_bpp;
2871         else
2872                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2873                                                  pipe_config->pipe_bpp);
2874
2875         intel_link_compute_m_n(output_bpp,
2876                                pipe_config->lane_count,
2877                                adjusted_mode->crtc_clock,
2878                                pipe_config->port_clock,
2879                                &pipe_config->dp_m_n,
2880                                constant_n, pipe_config->fec_enable);
2881
2882         if (!HAS_DDI(dev_priv))
2883                 intel_dp_set_clock(encoder, pipe_config);
2884
2885         intel_psr_compute_config(intel_dp, pipe_config);
2886         intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
2887                                      constant_n);
2888         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2889         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2890
2891         return 0;
2892 }
2893
2894 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2895                               int link_rate, int lane_count)
2896 {
2897         intel_dp->link_trained = false;
2898         intel_dp->link_rate = link_rate;
2899         intel_dp->lane_count = lane_count;
2900 }
2901
2902 static void intel_dp_prepare(struct intel_encoder *encoder,
2903                              const struct intel_crtc_state *pipe_config)
2904 {
2905         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2906         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2907         enum port port = encoder->port;
2908         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2909         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2910
2911         intel_dp_set_link_params(intel_dp,
2912                                  pipe_config->port_clock,
2913                                  pipe_config->lane_count);
2914
2915         /*
2916          * There are four kinds of DP registers:
2917          *
2918          *      IBX PCH
2919          *      SNB CPU
2920          *      IVB CPU
2921          *      CPT PCH
2922          *
2923          * IBX PCH and CPU are the same for almost everything,
2924          * except that the CPU DP PLL is configured in this
2925          * register
2926          *
2927          * CPT PCH is quite different, having many bits moved
2928          * to the TRANS_DP_CTL register instead. That
2929          * configuration happens (oddly) in ilk_pch_enable
2930          */
2931
2932         /* Preserve the BIOS-computed detected bit. This is
2933          * supposed to be read-only.
2934          */
2935         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2936
2937         /* Handle DP bits in common between all three register formats */
2938         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2939         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2940
2941         /* Split out the IBX/CPU vs CPT settings */
2942
2943         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2944                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2945                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2946                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2947                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2948                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2949
2950                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2951                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2952
2953                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2954         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2955                 u32 trans_dp;
2956
2957                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2958
2959                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2960                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2961                         trans_dp |= TRANS_DP_ENH_FRAMING;
2962                 else
2963                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2964                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2965         } else {
2966                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2967                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2968
2969                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2970                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2971                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2972                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2973                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2974
2975                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2976                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2977
2978                 if (IS_CHERRYVIEW(dev_priv))
2979                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2980                 else
2981                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2982         }
2983 }
2984
2985 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2986 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2987
2988 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2989 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2990
2991 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2992 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2993
2994 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2995
2996 static void wait_panel_status(struct intel_dp *intel_dp,
2997                                        u32 mask,
2998                                        u32 value)
2999 {
3000         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3001         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3002
3003         lockdep_assert_held(&dev_priv->pps_mutex);
3004
3005         intel_pps_verify_state(intel_dp);
3006
3007         pp_stat_reg = _pp_stat_reg(intel_dp);
3008         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3009
3010         drm_dbg_kms(&dev_priv->drm,
3011                     "mask %08x value %08x status %08x control %08x\n",
3012                     mask, value,
3013                     intel_de_read(dev_priv, pp_stat_reg),
3014                     intel_de_read(dev_priv, pp_ctrl_reg));
3015
3016         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
3017                                        mask, value, 5000))
3018                 drm_err(&dev_priv->drm,
3019                         "Panel status timeout: status %08x control %08x\n",
3020                         intel_de_read(dev_priv, pp_stat_reg),
3021                         intel_de_read(dev_priv, pp_ctrl_reg));
3022
3023         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
3024 }
3025
3026 static void wait_panel_on(struct intel_dp *intel_dp)
3027 {
3028         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3029
3030         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
3031         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
3032 }
3033
3034 static void wait_panel_off(struct intel_dp *intel_dp)
3035 {
3036         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3037
3038         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
3039         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
3040 }
3041
3042 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
3043 {
3044         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3045         ktime_t panel_power_on_time;
3046         s64 panel_power_off_duration;
3047
3048         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
3049
3050         /* take the difference of currrent time and panel power off time
3051          * and then make panel wait for t11_t12 if needed. */
3052         panel_power_on_time = ktime_get_boottime();
3053         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
3054
3055         /* When we disable the VDD override bit last we have to do the manual
3056          * wait. */
3057         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
3058                 wait_remaining_ms_from_jiffies(jiffies,
3059                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
3060
3061         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
3062 }
3063
3064 static void wait_backlight_on(struct intel_dp *intel_dp)
3065 {
3066         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
3067                                        intel_dp->backlight_on_delay);
3068 }
3069
3070 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
3071 {
3072         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
3073                                        intel_dp->backlight_off_delay);
3074 }
3075
3076 /* Read the current pp_control value, unlocking the register if it
3077  * is locked
3078  */
3079
3080 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
3081 {
3082         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3083         u32 control;
3084
3085         lockdep_assert_held(&dev_priv->pps_mutex);
3086
3087         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
3088         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
3089                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
3090                 control &= ~PANEL_UNLOCK_MASK;
3091                 control |= PANEL_UNLOCK_REGS;
3092         }
3093         return control;
3094 }
3095
3096 /*
3097  * Must be paired with edp_panel_vdd_off().
3098  * Must hold pps_mutex around the whole on/off sequence.
3099  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3100  */
3101 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
3102 {
3103         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3104         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3105         u32 pp;
3106         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3107         bool need_to_disable = !intel_dp->want_panel_vdd;
3108
3109         lockdep_assert_held(&dev_priv->pps_mutex);
3110
3111         if (!intel_dp_is_edp(intel_dp))
3112                 return false;
3113
3114         cancel_delayed_work(&intel_dp->panel_vdd_work);
3115         intel_dp->want_panel_vdd = true;
3116
3117         if (edp_have_panel_vdd(intel_dp))
3118                 return need_to_disable;
3119
3120         intel_display_power_get(dev_priv,
3121                                 intel_aux_power_domain(dig_port));
3122
3123         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
3124                     dig_port->base.base.base.id,
3125                     dig_port->base.base.name);
3126
3127         if (!edp_have_panel_power(intel_dp))
3128                 wait_panel_power_cycle(intel_dp);
3129
3130         pp = ilk_get_pp_control(intel_dp);
3131         pp |= EDP_FORCE_VDD;
3132
3133         pp_stat_reg = _pp_stat_reg(intel_dp);
3134         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3135
3136         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3137         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3138         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3139                     intel_de_read(dev_priv, pp_stat_reg),
3140                     intel_de_read(dev_priv, pp_ctrl_reg));
3141         /*
3142          * If the panel wasn't on, delay before accessing aux channel
3143          */
3144         if (!edp_have_panel_power(intel_dp)) {
3145                 drm_dbg_kms(&dev_priv->drm,
3146                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
3147                             dig_port->base.base.base.id,
3148                             dig_port->base.base.name);
3149                 msleep(intel_dp->panel_power_up_delay);
3150         }
3151
3152         return need_to_disable;
3153 }
3154
3155 /*
3156  * Must be paired with intel_edp_panel_vdd_off() or
3157  * intel_edp_panel_off().
3158  * Nested calls to these functions are not allowed since
3159  * we drop the lock. Caller must use some higher level
3160  * locking to prevent nested calls from other threads.
3161  */
3162 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
3163 {
3164         intel_wakeref_t wakeref;
3165         bool vdd;
3166
3167         if (!intel_dp_is_edp(intel_dp))
3168                 return;
3169
3170         vdd = false;
3171         with_pps_lock(intel_dp, wakeref)
3172                 vdd = edp_panel_vdd_on(intel_dp);
3173         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
3174                         dp_to_dig_port(intel_dp)->base.base.base.id,
3175                         dp_to_dig_port(intel_dp)->base.base.name);
3176 }
3177
3178 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
3179 {
3180         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3181         struct intel_digital_port *dig_port =
3182                 dp_to_dig_port(intel_dp);
3183         u32 pp;
3184         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3185
3186         lockdep_assert_held(&dev_priv->pps_mutex);
3187
3188         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
3189
3190         if (!edp_have_panel_vdd(intel_dp))
3191                 return;
3192
3193         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
3194                     dig_port->base.base.base.id,
3195                     dig_port->base.base.name);
3196
3197         pp = ilk_get_pp_control(intel_dp);
3198         pp &= ~EDP_FORCE_VDD;
3199
3200         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3201         pp_stat_reg = _pp_stat_reg(intel_dp);
3202
3203         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3204         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3205
3206         /* Make sure sequencer is idle before allowing subsequent activity */
3207         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3208                     intel_de_read(dev_priv, pp_stat_reg),
3209                     intel_de_read(dev_priv, pp_ctrl_reg));
3210
3211         if ((pp & PANEL_POWER_ON) == 0)
3212                 intel_dp->panel_power_off_time = ktime_get_boottime();
3213
3214         intel_display_power_put_unchecked(dev_priv,
3215                                           intel_aux_power_domain(dig_port));
3216 }
3217
3218 static void edp_panel_vdd_work(struct work_struct *__work)
3219 {
3220         struct intel_dp *intel_dp =
3221                 container_of(to_delayed_work(__work),
3222                              struct intel_dp, panel_vdd_work);
3223         intel_wakeref_t wakeref;
3224
3225         with_pps_lock(intel_dp, wakeref) {
3226                 if (!intel_dp->want_panel_vdd)
3227                         edp_panel_vdd_off_sync(intel_dp);
3228         }
3229 }
3230
3231 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
3232 {
3233         unsigned long delay;
3234
3235         /*
3236          * Queue the timer to fire a long time from now (relative to the power
3237          * down delay) to keep the panel power up across a sequence of
3238          * operations.
3239          */
3240         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3241         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3242 }
3243
3244 /*
3245  * Must be paired with edp_panel_vdd_on().
3246  * Must hold pps_mutex around the whole on/off sequence.
3247  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3248  */
3249 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3250 {
3251         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3252
3253         lockdep_assert_held(&dev_priv->pps_mutex);
3254
3255         if (!intel_dp_is_edp(intel_dp))
3256                 return;
3257
3258         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3259                         dp_to_dig_port(intel_dp)->base.base.base.id,
3260                         dp_to_dig_port(intel_dp)->base.base.name);
3261
3262         intel_dp->want_panel_vdd = false;
3263
3264         if (sync)
3265                 edp_panel_vdd_off_sync(intel_dp);
3266         else
3267                 edp_panel_vdd_schedule_off(intel_dp);
3268 }
3269
3270 static void edp_panel_on(struct intel_dp *intel_dp)
3271 {
3272         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3273         u32 pp;
3274         i915_reg_t pp_ctrl_reg;
3275
3276         lockdep_assert_held(&dev_priv->pps_mutex);
3277
3278         if (!intel_dp_is_edp(intel_dp))
3279                 return;
3280
3281         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3282                     dp_to_dig_port(intel_dp)->base.base.base.id,
3283                     dp_to_dig_port(intel_dp)->base.base.name);
3284
3285         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3286                      "[ENCODER:%d:%s] panel power already on\n",
3287                      dp_to_dig_port(intel_dp)->base.base.base.id,
3288                      dp_to_dig_port(intel_dp)->base.base.name))
3289                 return;
3290
3291         wait_panel_power_cycle(intel_dp);
3292
3293         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3294         pp = ilk_get_pp_control(intel_dp);
3295         if (IS_GEN(dev_priv, 5)) {
3296                 /* ILK workaround: disable reset around power sequence */
3297                 pp &= ~PANEL_POWER_RESET;
3298                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3299                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3300         }
3301
3302         pp |= PANEL_POWER_ON;
3303         if (!IS_GEN(dev_priv, 5))
3304                 pp |= PANEL_POWER_RESET;
3305
3306         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3307         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3308
3309         wait_panel_on(intel_dp);
3310         intel_dp->last_power_on = jiffies;
3311
3312         if (IS_GEN(dev_priv, 5)) {
3313                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3314                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3315                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3316         }
3317 }
3318
3319 void intel_edp_panel_on(struct intel_dp *intel_dp)
3320 {
3321         intel_wakeref_t wakeref;
3322
3323         if (!intel_dp_is_edp(intel_dp))
3324                 return;
3325
3326         with_pps_lock(intel_dp, wakeref)
3327                 edp_panel_on(intel_dp);
3328 }
3329
3330
3331 static void edp_panel_off(struct intel_dp *intel_dp)
3332 {
3333         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3334         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3335         u32 pp;
3336         i915_reg_t pp_ctrl_reg;
3337
3338         lockdep_assert_held(&dev_priv->pps_mutex);
3339
3340         if (!intel_dp_is_edp(intel_dp))
3341                 return;
3342
3343         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3344                     dig_port->base.base.base.id, dig_port->base.base.name);
3345
3346         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3347                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3348                  dig_port->base.base.base.id, dig_port->base.base.name);
3349
3350         pp = ilk_get_pp_control(intel_dp);
3351         /* We need to switch off panel power _and_ force vdd, for otherwise some
3352          * panels get very unhappy and cease to work. */
3353         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3354                 EDP_BLC_ENABLE);
3355
3356         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3357
3358         intel_dp->want_panel_vdd = false;
3359
3360         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3361         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3362
3363         wait_panel_off(intel_dp);
3364         intel_dp->panel_power_off_time = ktime_get_boottime();
3365
3366         /* We got a reference when we enabled the VDD. */
3367         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3368 }
3369
3370 void intel_edp_panel_off(struct intel_dp *intel_dp)
3371 {
3372         intel_wakeref_t wakeref;
3373
3374         if (!intel_dp_is_edp(intel_dp))
3375                 return;
3376
3377         with_pps_lock(intel_dp, wakeref)
3378                 edp_panel_off(intel_dp);
3379 }
3380
3381 /* Enable backlight in the panel power control. */
3382 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3383 {
3384         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3385         intel_wakeref_t wakeref;
3386
3387         /*
3388          * If we enable the backlight right away following a panel power
3389          * on, we may see slight flicker as the panel syncs with the eDP
3390          * link.  So delay a bit to make sure the image is solid before
3391          * allowing it to appear.
3392          */
3393         wait_backlight_on(intel_dp);
3394
3395         with_pps_lock(intel_dp, wakeref) {
3396                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3397                 u32 pp;
3398
3399                 pp = ilk_get_pp_control(intel_dp);
3400                 pp |= EDP_BLC_ENABLE;
3401
3402                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3403                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3404         }
3405 }
3406
3407 /* Enable backlight PWM and backlight PP control. */
3408 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3409                             const struct drm_connector_state *conn_state)
3410 {
3411         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3412         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3413
3414         if (!intel_dp_is_edp(intel_dp))
3415                 return;
3416
3417         drm_dbg_kms(&i915->drm, "\n");
3418
3419         intel_panel_enable_backlight(crtc_state, conn_state);
3420         _intel_edp_backlight_on(intel_dp);
3421 }
3422
3423 /* Disable backlight in the panel power control. */
3424 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3425 {
3426         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3427         intel_wakeref_t wakeref;
3428
3429         if (!intel_dp_is_edp(intel_dp))
3430                 return;
3431
3432         with_pps_lock(intel_dp, wakeref) {
3433                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3434                 u32 pp;
3435
3436                 pp = ilk_get_pp_control(intel_dp);
3437                 pp &= ~EDP_BLC_ENABLE;
3438
3439                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3440                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3441         }
3442
3443         intel_dp->last_backlight_off = jiffies;
3444         edp_wait_backlight_off(intel_dp);
3445 }
3446
3447 /* Disable backlight PP control and backlight PWM. */
3448 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3449 {
3450         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3451         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3452
3453         if (!intel_dp_is_edp(intel_dp))
3454                 return;
3455
3456         drm_dbg_kms(&i915->drm, "\n");
3457
3458         _intel_edp_backlight_off(intel_dp);
3459         intel_panel_disable_backlight(old_conn_state);
3460 }
3461
3462 /*
3463  * Hook for controlling the panel power control backlight through the bl_power
3464  * sysfs attribute. Take care to handle multiple calls.
3465  */
3466 static void intel_edp_backlight_power(struct intel_connector *connector,
3467                                       bool enable)
3468 {
3469         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3470         struct intel_dp *intel_dp = intel_attached_dp(connector);
3471         intel_wakeref_t wakeref;
3472         bool is_enabled;
3473
3474         is_enabled = false;
3475         with_pps_lock(intel_dp, wakeref)
3476                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3477         if (is_enabled == enable)
3478                 return;
3479
3480         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3481                     enable ? "enable" : "disable");
3482
3483         if (enable)
3484                 _intel_edp_backlight_on(intel_dp);
3485         else
3486                 _intel_edp_backlight_off(intel_dp);
3487 }
3488
3489 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3490 {
3491         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3492         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3493         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3494
3495         I915_STATE_WARN(cur_state != state,
3496                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3497                         dig_port->base.base.base.id, dig_port->base.base.name,
3498                         onoff(state), onoff(cur_state));
3499 }
3500 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3501
3502 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3503 {
3504         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3505
3506         I915_STATE_WARN(cur_state != state,
3507                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3508                         onoff(state), onoff(cur_state));
3509 }
3510 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3511 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3512
3513 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3514                            const struct intel_crtc_state *pipe_config)
3515 {
3516         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3517         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3518
3519         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3520         assert_dp_port_disabled(intel_dp);
3521         assert_edp_pll_disabled(dev_priv);
3522
3523         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3524                     pipe_config->port_clock);
3525
3526         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3527
3528         if (pipe_config->port_clock == 162000)
3529                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3530         else
3531                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3532
3533         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3534         intel_de_posting_read(dev_priv, DP_A);
3535         udelay(500);
3536
3537         /*
3538          * [DevILK] Work around required when enabling DP PLL
3539          * while a pipe is enabled going to FDI:
3540          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3541          * 2. Program DP PLL enable
3542          */
3543         if (IS_GEN(dev_priv, 5))
3544                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3545
3546         intel_dp->DP |= DP_PLL_ENABLE;
3547
3548         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3549         intel_de_posting_read(dev_priv, DP_A);
3550         udelay(200);
3551 }
3552
3553 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3554                             const struct intel_crtc_state *old_crtc_state)
3555 {
3556         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3558
3559         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3560         assert_dp_port_disabled(intel_dp);
3561         assert_edp_pll_enabled(dev_priv);
3562
3563         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3564
3565         intel_dp->DP &= ~DP_PLL_ENABLE;
3566
3567         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3568         intel_de_posting_read(dev_priv, DP_A);
3569         udelay(200);
3570 }
3571
3572 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3573 {
3574         /*
3575          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3576          * be capable of signalling downstream hpd with a long pulse.
3577          * Whether or not that means D3 is safe to use is not clear,
3578          * but let's assume so until proven otherwise.
3579          *
3580          * FIXME should really check all downstream ports...
3581          */
3582         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3583                 drm_dp_is_branch(intel_dp->dpcd) &&
3584                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3585 }
3586
3587 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3588                                            const struct intel_crtc_state *crtc_state,
3589                                            bool enable)
3590 {
3591         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3592         int ret;
3593
3594         if (!crtc_state->dsc.compression_enable)
3595                 return;
3596
3597         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3598                                  enable ? DP_DECOMPRESSION_EN : 0);
3599         if (ret < 0)
3600                 drm_dbg_kms(&i915->drm,
3601                             "Failed to %s sink decompression state\n",
3602                             enable ? "enable" : "disable");
3603 }
3604
3605 /* If the device supports it, try to set the power state appropriately */
3606 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3607 {
3608         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3609         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3610         int ret, i;
3611
3612         /* Should have a valid DPCD by this point */
3613         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3614                 return;
3615
3616         if (mode != DP_SET_POWER_D0) {
3617                 if (downstream_hpd_needs_d0(intel_dp))
3618                         return;
3619
3620                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3621         } else {
3622                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3623
3624                 lspcon_resume(dp_to_dig_port(intel_dp));
3625
3626                 /*
3627                  * When turning on, we need to retry for 1ms to give the sink
3628                  * time to wake up.
3629                  */
3630                 for (i = 0; i < 3; i++) {
3631                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3632                         if (ret == 1)
3633                                 break;
3634                         msleep(1);
3635                 }
3636
3637                 if (ret == 1 && lspcon->active)
3638                         lspcon_wait_pcon_mode(lspcon);
3639         }
3640
3641         if (ret != 1)
3642                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3643                             encoder->base.base.id, encoder->base.name,
3644                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3645 }
3646
3647 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3648                                  enum port port, enum pipe *pipe)
3649 {
3650         enum pipe p;
3651
3652         for_each_pipe(dev_priv, p) {
3653                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3654
3655                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3656                         *pipe = p;
3657                         return true;
3658                 }
3659         }
3660
3661         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3662                     port_name(port));
3663
3664         /* must initialize pipe to something for the asserts */
3665         *pipe = PIPE_A;
3666
3667         return false;
3668 }
3669
3670 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3671                            i915_reg_t dp_reg, enum port port,
3672                            enum pipe *pipe)
3673 {
3674         bool ret;
3675         u32 val;
3676
3677         val = intel_de_read(dev_priv, dp_reg);
3678
3679         ret = val & DP_PORT_EN;
3680
3681         /* asserts want to know the pipe even if the port is disabled */
3682         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3683                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3684         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3685                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3686         else if (IS_CHERRYVIEW(dev_priv))
3687                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3688         else
3689                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3690
3691         return ret;
3692 }
3693
3694 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3695                                   enum pipe *pipe)
3696 {
3697         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3698         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3699         intel_wakeref_t wakeref;
3700         bool ret;
3701
3702         wakeref = intel_display_power_get_if_enabled(dev_priv,
3703                                                      encoder->power_domain);
3704         if (!wakeref)
3705                 return false;
3706
3707         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3708                                     encoder->port, pipe);
3709
3710         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3711
3712         return ret;
3713 }
3714
3715 static void intel_dp_get_config(struct intel_encoder *encoder,
3716                                 struct intel_crtc_state *pipe_config)
3717 {
3718         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3719         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3720         u32 tmp, flags = 0;
3721         enum port port = encoder->port;
3722         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3723
3724         if (encoder->type == INTEL_OUTPUT_EDP)
3725                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3726         else
3727                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3728
3729         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3730
3731         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3732
3733         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3734                 u32 trans_dp = intel_de_read(dev_priv,
3735                                              TRANS_DP_CTL(crtc->pipe));
3736
3737                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3738                         flags |= DRM_MODE_FLAG_PHSYNC;
3739                 else
3740                         flags |= DRM_MODE_FLAG_NHSYNC;
3741
3742                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3743                         flags |= DRM_MODE_FLAG_PVSYNC;
3744                 else
3745                         flags |= DRM_MODE_FLAG_NVSYNC;
3746         } else {
3747                 if (tmp & DP_SYNC_HS_HIGH)
3748                         flags |= DRM_MODE_FLAG_PHSYNC;
3749                 else
3750                         flags |= DRM_MODE_FLAG_NHSYNC;
3751
3752                 if (tmp & DP_SYNC_VS_HIGH)
3753                         flags |= DRM_MODE_FLAG_PVSYNC;
3754                 else
3755                         flags |= DRM_MODE_FLAG_NVSYNC;
3756         }
3757
3758         pipe_config->hw.adjusted_mode.flags |= flags;
3759
3760         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3761                 pipe_config->limited_color_range = true;
3762
3763         pipe_config->lane_count =
3764                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3765
3766         intel_dp_get_m_n(crtc, pipe_config);
3767
3768         if (port == PORT_A) {
3769                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3770                         pipe_config->port_clock = 162000;
3771                 else
3772                         pipe_config->port_clock = 270000;
3773         }
3774
3775         pipe_config->hw.adjusted_mode.crtc_clock =
3776                 intel_dotclock_calculate(pipe_config->port_clock,
3777                                          &pipe_config->dp_m_n);
3778
3779         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3780             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3781                 /*
3782                  * This is a big fat ugly hack.
3783                  *
3784                  * Some machines in UEFI boot mode provide us a VBT that has 18
3785                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3786                  * unknown we fail to light up. Yet the same BIOS boots up with
3787                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3788                  * max, not what it tells us to use.
3789                  *
3790                  * Note: This will still be broken if the eDP panel is not lit
3791                  * up by the BIOS, and thus we can't get the mode at module
3792                  * load.
3793                  */
3794                 drm_dbg_kms(&dev_priv->drm,
3795                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3796                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3797                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3798         }
3799 }
3800
3801 static bool
3802 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3803
3804 /**
3805  * intel_dp_sync_state - sync the encoder state during init/resume
3806  * @encoder: intel encoder to sync
3807  * @crtc_state: state for the CRTC connected to the encoder
3808  *
3809  * Sync any state stored in the encoder wrt. HW state during driver init
3810  * and system resume.
3811  */
3812 void intel_dp_sync_state(struct intel_encoder *encoder,
3813                          const struct intel_crtc_state *crtc_state)
3814 {
3815         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3816
3817         /*
3818          * Don't clobber DPCD if it's been already read out during output
3819          * setup (eDP) or detect.
3820          */
3821         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3822                 intel_dp_get_dpcd(intel_dp);
3823
3824         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
3825         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
3826 }
3827
3828 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3829                                     struct intel_crtc_state *crtc_state)
3830 {
3831         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3832         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3833
3834         /*
3835          * If BIOS has set an unsupported or non-standard link rate for some
3836          * reason force an encoder recompute and full modeset.
3837          */
3838         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3839                                 crtc_state->port_clock) < 0) {
3840                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
3841                 crtc_state->uapi.connectors_changed = true;
3842                 return false;
3843         }
3844
3845         /*
3846          * FIXME hack to force full modeset when DSC is being used.
3847          *
3848          * As long as we do not have full state readout and config comparison
3849          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3850          * Remove once we have readout for DSC.
3851          */
3852         if (crtc_state->dsc.compression_enable) {
3853                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
3854                 crtc_state->uapi.mode_changed = true;
3855                 return false;
3856         }
3857
3858         if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
3859                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
3860                 crtc_state->uapi.mode_changed = true;
3861                 return false;
3862         }
3863
3864         return true;
3865 }
3866
3867 static void intel_disable_dp(struct intel_atomic_state *state,
3868                              struct intel_encoder *encoder,
3869                              const struct intel_crtc_state *old_crtc_state,
3870                              const struct drm_connector_state *old_conn_state)
3871 {
3872         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3873
3874         intel_dp->link_trained = false;
3875
3876         if (old_crtc_state->has_audio)
3877                 intel_audio_codec_disable(encoder,
3878                                           old_crtc_state, old_conn_state);
3879
3880         /* Make sure the panel is off before trying to change the mode. But also
3881          * ensure that we have vdd while we switch off the panel. */
3882         intel_edp_panel_vdd_on(intel_dp);
3883         intel_edp_backlight_off(old_conn_state);
3884         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3885         intel_edp_panel_off(intel_dp);
3886         intel_dp->frl.is_trained = false;
3887         intel_dp->frl.trained_rate_gbps = 0;
3888 }
3889
3890 static void g4x_disable_dp(struct intel_atomic_state *state,
3891                            struct intel_encoder *encoder,
3892                            const struct intel_crtc_state *old_crtc_state,
3893                            const struct drm_connector_state *old_conn_state)
3894 {
3895         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3896 }
3897
3898 static void vlv_disable_dp(struct intel_atomic_state *state,
3899                            struct intel_encoder *encoder,
3900                            const struct intel_crtc_state *old_crtc_state,
3901                            const struct drm_connector_state *old_conn_state)
3902 {
3903         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3904 }
3905
3906 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3907                                 struct intel_encoder *encoder,
3908                                 const struct intel_crtc_state *old_crtc_state,
3909                                 const struct drm_connector_state *old_conn_state)
3910 {
3911         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3912         enum port port = encoder->port;
3913
3914         /*
3915          * Bspec does not list a specific disable sequence for g4x DP.
3916          * Follow the ilk+ sequence (disable pipe before the port) for
3917          * g4x DP as it does not suffer from underruns like the normal
3918          * g4x modeset sequence (disable pipe after the port).
3919          */
3920         intel_dp_link_down(encoder, old_crtc_state);
3921
3922         /* Only ilk+ has port A */
3923         if (port == PORT_A)
3924                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3925 }
3926
3927 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3928                                 struct intel_encoder *encoder,
3929                                 const struct intel_crtc_state *old_crtc_state,
3930                                 const struct drm_connector_state *old_conn_state)
3931 {
3932         intel_dp_link_down(encoder, old_crtc_state);
3933 }
3934
3935 static void chv_post_disable_dp(struct intel_atomic_state *state,
3936                                 struct intel_encoder *encoder,
3937                                 const struct intel_crtc_state *old_crtc_state,
3938                                 const struct drm_connector_state *old_conn_state)
3939 {
3940         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3941
3942         intel_dp_link_down(encoder, old_crtc_state);
3943
3944         vlv_dpio_get(dev_priv);
3945
3946         /* Assert data lane reset */
3947         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3948
3949         vlv_dpio_put(dev_priv);
3950 }
3951
3952 static void
3953 cpt_set_link_train(struct intel_dp *intel_dp,
3954                    const struct intel_crtc_state *crtc_state,
3955                    u8 dp_train_pat)
3956 {
3957         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3958         u32 *DP = &intel_dp->DP;
3959
3960         *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3961
3962         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3963         case DP_TRAINING_PATTERN_DISABLE:
3964                 *DP |= DP_LINK_TRAIN_OFF_CPT;
3965                 break;
3966         case DP_TRAINING_PATTERN_1:
3967                 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3968                 break;
3969         case DP_TRAINING_PATTERN_2:
3970                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3971                 break;
3972         case DP_TRAINING_PATTERN_3:
3973                 drm_dbg_kms(&dev_priv->drm,
3974                             "TPS3 not supported, using TPS2 instead\n");
3975                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3976                 break;
3977         }
3978
3979         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3980         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3981 }
3982
3983 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3984 {
3985         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3986
3987         /* Clear the cached register set to avoid using stale values */
3988
3989         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3990
3991         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3992                              intel_dp->pcon_dsc_dpcd,
3993                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3994                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3995                         DP_PCON_DSC_ENCODER);
3996
3997         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3998                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3999 }
4000
4001 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
4002 {
4003         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
4004         int i;
4005
4006         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
4007                 if (frl_bw_mask & (1 << i))
4008                         return bw_gbps[i];
4009         }
4010         return 0;
4011 }
4012
4013 static int intel_dp_pcon_set_frl_mask(int max_frl)
4014 {
4015         switch (max_frl) {
4016         case 48:
4017                 return DP_PCON_FRL_BW_MASK_48GBPS;
4018         case 40:
4019                 return DP_PCON_FRL_BW_MASK_40GBPS;
4020         case 32:
4021                 return DP_PCON_FRL_BW_MASK_32GBPS;
4022         case 24:
4023                 return DP_PCON_FRL_BW_MASK_24GBPS;
4024         case 18:
4025                 return DP_PCON_FRL_BW_MASK_18GBPS;
4026         case 9:
4027                 return DP_PCON_FRL_BW_MASK_9GBPS;
4028         }
4029
4030         return 0;
4031 }
4032
4033 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
4034 {
4035         struct intel_connector *intel_connector = intel_dp->attached_connector;
4036         struct drm_connector *connector = &intel_connector->base;
4037         int max_frl_rate;
4038         int max_lanes, rate_per_lane;
4039         int max_dsc_lanes, dsc_rate_per_lane;
4040
4041         max_lanes = connector->display_info.hdmi.max_lanes;
4042         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
4043         max_frl_rate = max_lanes * rate_per_lane;
4044
4045         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
4046                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
4047                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
4048                 if (max_dsc_lanes && dsc_rate_per_lane)
4049                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
4050         }
4051
4052         return max_frl_rate;
4053 }
4054
4055 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
4056 {
4057 #define PCON_EXTENDED_TRAIN_MODE (1 > 0)
4058 #define PCON_CONCURRENT_MODE (1 > 0)
4059 #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
4060 #define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
4061 #define TIMEOUT_FRL_READY_MS 500
4062 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
4063
4064         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4065         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
4066         u8 max_frl_bw_mask = 0, frl_trained_mask;
4067         bool is_active;
4068
4069         ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
4070         if (ret < 0)
4071                 return ret;
4072
4073         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
4074         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
4075
4076         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
4077         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
4078
4079         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
4080
4081         if (max_frl_bw <= 0)
4082                 return -EINVAL;
4083
4084         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
4085         if (ret < 0)
4086                 return ret;
4087         /* Wait for PCON to be FRL Ready */
4088         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
4089
4090         if (!is_active)
4091                 return -ETIMEDOUT;
4092
4093         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
4094         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
4095         if (ret < 0)
4096                 return ret;
4097         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
4098         if (ret < 0)
4099                 return ret;
4100         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
4101         if (ret < 0)
4102                 return ret;
4103         /*
4104          * Wait for FRL to be completed
4105          * Check if the HDMI Link is up and active.
4106          */
4107         wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
4108
4109         if (!is_active)
4110                 return -ETIMEDOUT;
4111
4112         /* Verify HDMI Link configuration shows FRL Mode */
4113         if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
4114             DP_PCON_HDMI_MODE_FRL) {
4115                 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
4116                 return -EINVAL;
4117         }
4118         drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
4119
4120         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
4121         intel_dp->frl.is_trained = true;
4122         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
4123
4124         return 0;
4125 }
4126
4127 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
4128 {
4129         if (drm_dp_is_branch(intel_dp->dpcd) &&
4130             intel_dp->has_hdmi_sink &&
4131             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
4132                 return true;
4133
4134         return false;
4135 }
4136
4137 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
4138 {
4139         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4140
4141         /* Always go for FRL training if supported */
4142         if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
4143             intel_dp->frl.is_trained)
4144                 return;
4145
4146         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
4147                 int ret, mode;
4148
4149                 drm_dbg(&dev_priv->drm, "Couldnt set FRL mode, continuing with TMDS mode\n");
4150                 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
4151                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
4152
4153                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
4154                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
4155         } else {
4156                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
4157         }
4158 }
4159
4160 static int
4161 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
4162 {
4163         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
4164
4165         return intel_hdmi_dsc_get_slice_height(vactive);
4166 }
4167
4168 static int
4169 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
4170                              const struct intel_crtc_state *crtc_state)
4171 {
4172         struct intel_connector *intel_connector = intel_dp->attached_connector;
4173         struct drm_connector *connector = &intel_connector->base;
4174         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
4175         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
4176         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
4177         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
4178
4179         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
4180                                              pcon_max_slice_width,
4181                                              hdmi_max_slices, hdmi_throughput);
4182 }
4183
4184 static int
4185 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
4186                           const struct intel_crtc_state *crtc_state,
4187                           int num_slices, int slice_width)
4188 {
4189         struct intel_connector *intel_connector = intel_dp->attached_connector;
4190         struct drm_connector *connector = &intel_connector->base;
4191         int output_format = crtc_state->output_format;
4192         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
4193         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
4194         int hdmi_max_chunk_bytes =
4195                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
4196
4197         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
4198                                       num_slices, output_format, hdmi_all_bpp,
4199                                       hdmi_max_chunk_bytes);
4200 }
4201
4202 void
4203 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
4204                             const struct intel_crtc_state *crtc_state)
4205 {
4206         u8 pps_param[6];
4207         int slice_height;
4208         int slice_width;
4209         int num_slices;
4210         int bits_per_pixel;
4211         int ret;
4212         struct intel_connector *intel_connector = intel_dp->attached_connector;
4213         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4214         struct drm_connector *connector;
4215         bool hdmi_is_dsc_1_2;
4216
4217         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
4218                 return;
4219
4220         if (!intel_connector)
4221                 return;
4222         connector = &intel_connector->base;
4223         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
4224
4225         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
4226             !hdmi_is_dsc_1_2)
4227                 return;
4228
4229         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
4230         if (!slice_height)
4231                 return;
4232
4233         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
4234         if (!num_slices)
4235                 return;
4236
4237         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
4238                                    num_slices);
4239
4240         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
4241                                                    num_slices, slice_width);
4242         if (!bits_per_pixel)
4243                 return;
4244
4245         pps_param[0] = slice_height & 0xFF;
4246         pps_param[1] = slice_height >> 8;
4247         pps_param[2] = slice_width & 0xFF;
4248         pps_param[3] = slice_width >> 8;
4249         pps_param[4] = bits_per_pixel & 0xFF;
4250         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
4251
4252         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
4253         if (ret < 0)
4254                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
4255 }
4256
4257 static void
4258 g4x_set_link_train(struct intel_dp *intel_dp,
4259                    const struct intel_crtc_state *crtc_state,
4260                    u8 dp_train_pat)
4261 {
4262         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4263         u32 *DP = &intel_dp->DP;
4264
4265         *DP &= ~DP_LINK_TRAIN_MASK;
4266
4267         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
4268         case DP_TRAINING_PATTERN_DISABLE:
4269                 *DP |= DP_LINK_TRAIN_OFF;
4270                 break;
4271         case DP_TRAINING_PATTERN_1:
4272                 *DP |= DP_LINK_TRAIN_PAT_1;
4273                 break;
4274         case DP_TRAINING_PATTERN_2:
4275                 *DP |= DP_LINK_TRAIN_PAT_2;
4276                 break;
4277         case DP_TRAINING_PATTERN_3:
4278                 drm_dbg_kms(&dev_priv->drm,
4279                             "TPS3 not supported, using TPS2 instead\n");
4280                 *DP |= DP_LINK_TRAIN_PAT_2;
4281                 break;
4282         }
4283
4284         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4285         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4286 }
4287
4288 static void intel_dp_enable_port(struct intel_dp *intel_dp,
4289                                  const struct intel_crtc_state *crtc_state)
4290 {
4291         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4292
4293         /* enable with pattern 1 (as per spec) */
4294
4295         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
4296                                                DP_TRAINING_PATTERN_1);
4297
4298         /*
4299          * Magic for VLV/CHV. We _must_ first set up the register
4300          * without actually enabling the port, and then do another
4301          * write to enable the port. Otherwise link training will
4302          * fail when the power sequencer is freshly used for this port.
4303          */
4304         intel_dp->DP |= DP_PORT_EN;
4305         if (crtc_state->has_audio)
4306                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
4307
4308         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4309         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4310 }
4311
4312 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
4313                                            const struct intel_crtc_state *crtc_state)
4314 {
4315         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4316         u8 tmp;
4317
4318         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
4319                 return;
4320
4321         if (!drm_dp_is_branch(intel_dp->dpcd))
4322                 return;
4323
4324         tmp = intel_dp->has_hdmi_sink ?
4325                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
4326
4327         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4328                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
4329                 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
4330                             enableddisabled(intel_dp->has_hdmi_sink));
4331
4332         tmp = intel_dp->dfp.ycbcr_444_to_420 ?
4333                 DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4334
4335         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4336                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4337                 drm_dbg_kms(&i915->drm,
4338                             "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
4339                             enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
4340
4341         tmp = 0;
4342         if (intel_dp->dfp.rgb_to_ycbcr) {
4343                 bool bt2020, bt709;
4344
4345                 /*
4346                  * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
4347                  * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
4348                  *
4349                  */
4350                 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
4351
4352                 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4353                                                                    intel_dp->downstream_ports,
4354                                                                    DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
4355                 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4356                                                                   intel_dp->downstream_ports,
4357                                                                   DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4358                 switch (crtc_state->infoframes.vsc.colorimetry) {
4359                 case DP_COLORIMETRY_BT2020_RGB:
4360                 case DP_COLORIMETRY_BT2020_YCC:
4361                         if (bt2020)
4362                                 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
4363                         break;
4364                 case DP_COLORIMETRY_BT709_YCC:
4365                 case DP_COLORIMETRY_XVYCC_709:
4366                         if (bt709)
4367                                 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
4368                         break;
4369                 default:
4370                         break;
4371                 }
4372         }
4373
4374         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
4375                 drm_dbg_kms(&i915->drm,
4376                            "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n",
4377                            enableddisabled(tmp ? true : false));
4378 }
4379
4380 static void intel_enable_dp(struct intel_atomic_state *state,
4381                             struct intel_encoder *encoder,
4382                             const struct intel_crtc_state *pipe_config,
4383                             const struct drm_connector_state *conn_state)
4384 {
4385         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4386         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4387         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4388         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
4389         enum pipe pipe = crtc->pipe;
4390         intel_wakeref_t wakeref;
4391
4392         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
4393                 return;
4394
4395         with_pps_lock(intel_dp, wakeref) {
4396                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4397                         vlv_init_panel_power_sequencer(encoder, pipe_config);
4398
4399                 intel_dp_enable_port(intel_dp, pipe_config);
4400
4401                 edp_panel_vdd_on(intel_dp);
4402                 edp_panel_on(intel_dp);
4403                 edp_panel_vdd_off(intel_dp, true);
4404         }
4405
4406         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4407                 unsigned int lane_mask = 0x0;
4408
4409                 if (IS_CHERRYVIEW(dev_priv))
4410                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
4411
4412                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
4413                                     lane_mask);
4414         }
4415
4416         intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
4417         intel_dp_configure_protocol_converter(intel_dp, pipe_config);
4418         intel_dp_check_frl_training(intel_dp);
4419         intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
4420         intel_dp_start_link_train(intel_dp, pipe_config);
4421         intel_dp_stop_link_train(intel_dp, pipe_config);
4422
4423         if (pipe_config->has_audio) {
4424                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
4425                         pipe_name(pipe));
4426                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
4427         }
4428 }
4429
4430 static void g4x_enable_dp(struct intel_atomic_state *state,
4431                           struct intel_encoder *encoder,
4432                           const struct intel_crtc_state *pipe_config,
4433                           const struct drm_connector_state *conn_state)
4434 {
4435         intel_enable_dp(state, encoder, pipe_config, conn_state);
4436         intel_edp_backlight_on(pipe_config, conn_state);
4437 }
4438
4439 static void vlv_enable_dp(struct intel_atomic_state *state,
4440                           struct intel_encoder *encoder,
4441                           const struct intel_crtc_state *pipe_config,
4442                           const struct drm_connector_state *conn_state)
4443 {
4444         intel_edp_backlight_on(pipe_config, conn_state);
4445 }
4446
4447 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
4448                               struct intel_encoder *encoder,
4449                               const struct intel_crtc_state *pipe_config,
4450                               const struct drm_connector_state *conn_state)
4451 {
4452         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4453         enum port port = encoder->port;
4454
4455         intel_dp_prepare(encoder, pipe_config);
4456
4457         /* Only ilk+ has port A */
4458         if (port == PORT_A)
4459                 ilk_edp_pll_on(intel_dp, pipe_config);
4460 }
4461
4462 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
4463 {
4464         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4465         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4466         enum pipe pipe = intel_dp->pps_pipe;
4467         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
4468
4469         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4470
4471         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
4472                 return;
4473
4474         edp_panel_vdd_off_sync(intel_dp);
4475
4476         /*
4477          * VLV seems to get confused when multiple power sequencers
4478          * have the same port selected (even if only one has power/vdd
4479          * enabled). The failure manifests as vlv_wait_port_ready() failing
4480          * CHV on the other hand doesn't seem to mind having the same port
4481          * selected in multiple power sequencers, but let's clear the
4482          * port select always when logically disconnecting a power sequencer
4483          * from a port.
4484          */
4485         drm_dbg_kms(&dev_priv->drm,
4486                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
4487                     pipe_name(pipe), dig_port->base.base.base.id,
4488                     dig_port->base.base.name);
4489         intel_de_write(dev_priv, pp_on_reg, 0);
4490         intel_de_posting_read(dev_priv, pp_on_reg);
4491
4492         intel_dp->pps_pipe = INVALID_PIPE;
4493 }
4494
4495 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
4496                                       enum pipe pipe)
4497 {
4498         struct intel_encoder *encoder;
4499
4500         lockdep_assert_held(&dev_priv->pps_mutex);
4501
4502         for_each_intel_dp(&dev_priv->drm, encoder) {
4503                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4504
4505                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
4506                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
4507                          pipe_name(pipe), encoder->base.base.id,
4508                          encoder->base.name);
4509
4510                 if (intel_dp->pps_pipe != pipe)
4511                         continue;
4512
4513                 drm_dbg_kms(&dev_priv->drm,
4514                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
4515                             pipe_name(pipe), encoder->base.base.id,
4516                             encoder->base.name);
4517
4518                 /* make sure vdd is off before we steal it */
4519                 vlv_detach_power_sequencer(intel_dp);
4520         }
4521 }
4522
4523 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
4524                                            const struct intel_crtc_state *crtc_state)
4525 {
4526         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4527         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4528         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4529
4530         lockdep_assert_held(&dev_priv->pps_mutex);
4531
4532         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4533
4534         if (intel_dp->pps_pipe != INVALID_PIPE &&
4535             intel_dp->pps_pipe != crtc->pipe) {
4536                 /*
4537                  * If another power sequencer was being used on this
4538                  * port previously make sure to turn off vdd there while
4539                  * we still have control of it.
4540                  */
4541                 vlv_detach_power_sequencer(intel_dp);
4542         }
4543
4544         /*
4545          * We may be stealing the power
4546          * sequencer from another port.
4547          */
4548         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
4549
4550         intel_dp->active_pipe = crtc->pipe;
4551
4552         if (!intel_dp_is_edp(intel_dp))
4553                 return;
4554
4555         /* now it's all ours */
4556         intel_dp->pps_pipe = crtc->pipe;
4557
4558         drm_dbg_kms(&dev_priv->drm,
4559                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
4560                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
4561                     encoder->base.name);
4562
4563         /* init power sequencer on this pipe and port */
4564         intel_dp_init_panel_power_sequencer(intel_dp);
4565         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
4566 }
4567
4568 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
4569                               struct intel_encoder *encoder,
4570                               const struct intel_crtc_state *pipe_config,
4571                               const struct drm_connector_state *conn_state)
4572 {
4573         vlv_phy_pre_encoder_enable(encoder, pipe_config);
4574
4575         intel_enable_dp(state, encoder, pipe_config, conn_state);
4576 }
4577
4578 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
4579                                   struct intel_encoder *encoder,
4580                                   const struct intel_crtc_state *pipe_config,
4581                                   const struct drm_connector_state *conn_state)
4582 {
4583         intel_dp_prepare(encoder, pipe_config);
4584
4585         vlv_phy_pre_pll_enable(encoder, pipe_config);
4586 }
4587
4588 static void chv_pre_enable_dp(struct intel_atomic_state *state,
4589                               struct intel_encoder *encoder,
4590                               const struct intel_crtc_state *pipe_config,
4591                               const struct drm_connector_state *conn_state)
4592 {
4593         chv_phy_pre_encoder_enable(encoder, pipe_config);
4594
4595         intel_enable_dp(state, encoder, pipe_config, conn_state);
4596
4597         /* Second common lane will stay alive on its own now */
4598         chv_phy_release_cl2_override(encoder);
4599 }
4600
4601 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
4602                                   struct intel_encoder *encoder,
4603                                   const struct intel_crtc_state *pipe_config,
4604                                   const struct drm_connector_state *conn_state)
4605 {
4606         intel_dp_prepare(encoder, pipe_config);
4607
4608         chv_phy_pre_pll_enable(encoder, pipe_config);
4609 }
4610
4611 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
4612                                     struct intel_encoder *encoder,
4613                                     const struct intel_crtc_state *old_crtc_state,
4614                                     const struct drm_connector_state *old_conn_state)
4615 {
4616         chv_phy_post_pll_disable(encoder, old_crtc_state);
4617 }
4618
4619 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
4620                                  const struct intel_crtc_state *crtc_state)
4621 {
4622         return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4623 }
4624
4625 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
4626                                  const struct intel_crtc_state *crtc_state)
4627 {
4628         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4629 }
4630
4631 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
4632 {
4633         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4634 }
4635
4636 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
4637 {
4638         return DP_TRAIN_PRE_EMPH_LEVEL_3;
4639 }
4640
4641 static void vlv_set_signal_levels(struct intel_dp *intel_dp,
4642                                   const struct intel_crtc_state *crtc_state)
4643 {
4644         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4645         unsigned long demph_reg_value, preemph_reg_value,
4646                 uniqtranscale_reg_value;
4647         u8 train_set = intel_dp->train_set[0];
4648
4649         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4650         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4651                 preemph_reg_value = 0x0004000;
4652                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4653                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4654                         demph_reg_value = 0x2B405555;
4655                         uniqtranscale_reg_value = 0x552AB83A;
4656                         break;
4657                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4658                         demph_reg_value = 0x2B404040;
4659                         uniqtranscale_reg_value = 0x5548B83A;
4660                         break;
4661                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4662                         demph_reg_value = 0x2B245555;
4663                         uniqtranscale_reg_value = 0x5560B83A;
4664                         break;
4665                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4666                         demph_reg_value = 0x2B405555;
4667                         uniqtranscale_reg_value = 0x5598DA3A;
4668                         break;
4669                 default:
4670                         return;
4671                 }
4672                 break;
4673         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4674                 preemph_reg_value = 0x0002000;
4675                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4676                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4677                         demph_reg_value = 0x2B404040;
4678                         uniqtranscale_reg_value = 0x5552B83A;
4679                         break;
4680                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4681                         demph_reg_value = 0x2B404848;
4682                         uniqtranscale_reg_value = 0x5580B83A;
4683                         break;
4684                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4685                         demph_reg_value = 0x2B404040;
4686                         uniqtranscale_reg_value = 0x55ADDA3A;
4687                         break;
4688                 default:
4689                         return;
4690                 }
4691                 break;
4692         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4693                 preemph_reg_value = 0x0000000;
4694                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4695                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4696                         demph_reg_value = 0x2B305555;
4697                         uniqtranscale_reg_value = 0x5570B83A;
4698                         break;
4699                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4700                         demph_reg_value = 0x2B2B4040;
4701                         uniqtranscale_reg_value = 0x55ADDA3A;
4702                         break;
4703                 default:
4704                         return;
4705                 }
4706                 break;
4707         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4708                 preemph_reg_value = 0x0006000;
4709                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4710                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4711                         demph_reg_value = 0x1B405555;
4712                         uniqtranscale_reg_value = 0x55ADDA3A;
4713                         break;
4714                 default:
4715                         return;
4716                 }
4717                 break;
4718         default:
4719                 return;
4720         }
4721
4722         vlv_set_phy_signal_level(encoder, crtc_state,
4723                                  demph_reg_value, preemph_reg_value,
4724                                  uniqtranscale_reg_value, 0);
4725 }
4726
4727 static void chv_set_signal_levels(struct intel_dp *intel_dp,
4728                                   const struct intel_crtc_state *crtc_state)
4729 {
4730         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4731         u32 deemph_reg_value, margin_reg_value;
4732         bool uniq_trans_scale = false;
4733         u8 train_set = intel_dp->train_set[0];
4734
4735         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4736         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4737                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4738                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4739                         deemph_reg_value = 128;
4740                         margin_reg_value = 52;
4741                         break;
4742                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4743                         deemph_reg_value = 128;
4744                         margin_reg_value = 77;
4745                         break;
4746                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4747                         deemph_reg_value = 128;
4748                         margin_reg_value = 102;
4749                         break;
4750                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4751                         deemph_reg_value = 128;
4752                         margin_reg_value = 154;
4753                         uniq_trans_scale = true;
4754                         break;
4755                 default:
4756                         return;
4757                 }
4758                 break;
4759         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4760                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4761                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4762                         deemph_reg_value = 85;
4763                         margin_reg_value = 78;
4764                         break;
4765                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4766                         deemph_reg_value = 85;
4767                         margin_reg_value = 116;
4768                         break;
4769                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4770                         deemph_reg_value = 85;
4771                         margin_reg_value = 154;
4772                         break;
4773                 default:
4774                         return;
4775                 }
4776                 break;
4777         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4778                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4779                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4780                         deemph_reg_value = 64;
4781                         margin_reg_value = 104;
4782                         break;
4783                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4784                         deemph_reg_value = 64;
4785                         margin_reg_value = 154;
4786                         break;
4787                 default:
4788                         return;
4789                 }
4790                 break;
4791         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4792                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4793                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4794                         deemph_reg_value = 43;
4795                         margin_reg_value = 154;
4796                         break;
4797                 default:
4798                         return;
4799                 }
4800                 break;
4801         default:
4802                 return;
4803         }
4804
4805         chv_set_phy_signal_level(encoder, crtc_state,
4806                                  deemph_reg_value, margin_reg_value,
4807                                  uniq_trans_scale);
4808 }
4809
4810 static u32 g4x_signal_levels(u8 train_set)
4811 {
4812         u32 signal_levels = 0;
4813
4814         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4815         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4816         default:
4817                 signal_levels |= DP_VOLTAGE_0_4;
4818                 break;
4819         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4820                 signal_levels |= DP_VOLTAGE_0_6;
4821                 break;
4822         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4823                 signal_levels |= DP_VOLTAGE_0_8;
4824                 break;
4825         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4826                 signal_levels |= DP_VOLTAGE_1_2;
4827                 break;
4828         }
4829         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4830         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4831         default:
4832                 signal_levels |= DP_PRE_EMPHASIS_0;
4833                 break;
4834         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4835                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4836                 break;
4837         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4838                 signal_levels |= DP_PRE_EMPHASIS_6;
4839                 break;
4840         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4841                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4842                 break;
4843         }
4844         return signal_levels;
4845 }
4846
4847 static void
4848 g4x_set_signal_levels(struct intel_dp *intel_dp,
4849                       const struct intel_crtc_state *crtc_state)
4850 {
4851         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4852         u8 train_set = intel_dp->train_set[0];
4853         u32 signal_levels;
4854
4855         signal_levels = g4x_signal_levels(train_set);
4856
4857         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4858                     signal_levels);
4859
4860         intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
4861         intel_dp->DP |= signal_levels;
4862
4863         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4864         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4865 }
4866
4867 /* SNB CPU eDP voltage swing and pre-emphasis control */
4868 static u32 snb_cpu_edp_signal_levels(u8 train_set)
4869 {
4870         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4871                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4872
4873         switch (signal_levels) {
4874         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4875         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4876                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4877         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4878                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4879         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4880         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4881                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4882         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4883         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4884                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4885         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4886         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4887                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4888         default:
4889                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4890                               "0x%x\n", signal_levels);
4891                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4892         }
4893 }
4894
4895 static void
4896 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4897                               const struct intel_crtc_state *crtc_state)
4898 {
4899         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4900         u8 train_set = intel_dp->train_set[0];
4901         u32 signal_levels;
4902
4903         signal_levels = snb_cpu_edp_signal_levels(train_set);
4904
4905         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4906                     signal_levels);
4907
4908         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4909         intel_dp->DP |= signal_levels;
4910
4911         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4912         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4913 }
4914
4915 /* IVB CPU eDP voltage swing and pre-emphasis control */
4916 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
4917 {
4918         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4919                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4920
4921         switch (signal_levels) {
4922         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4923                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4924         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4925                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4926         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4927         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4928                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4929
4930         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4931                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4932         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4933                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4934
4935         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4936                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4937         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4938                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4939
4940         default:
4941                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4942                               "0x%x\n", signal_levels);
4943                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4944         }
4945 }
4946
4947 static void
4948 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4949                               const struct intel_crtc_state *crtc_state)
4950 {
4951         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4952         u8 train_set = intel_dp->train_set[0];
4953         u32 signal_levels;
4954
4955         signal_levels = ivb_cpu_edp_signal_levels(train_set);
4956
4957         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4958                     signal_levels);
4959
4960         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4961         intel_dp->DP |= signal_levels;
4962
4963         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4964         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4965 }
4966
4967 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
4968                                 const struct intel_crtc_state *crtc_state)
4969 {
4970         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4971         u8 train_set = intel_dp->train_set[0];
4972
4973         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4974                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4975                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4976         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4977                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4978                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4979                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4980                     " (max)" : "");
4981
4982         intel_dp->set_signal_levels(intel_dp, crtc_state);
4983 }
4984
4985 void
4986 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4987                                        const struct intel_crtc_state *crtc_state,
4988                                        u8 dp_train_pat)
4989 {
4990         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4991
4992         if ((intel_dp_training_pattern_symbol(dp_train_pat)) !=
4993             DP_TRAINING_PATTERN_DISABLE)
4994                 drm_dbg_kms(&dev_priv->drm,
4995                             "Using DP training pattern TPS%d\n",
4996                             intel_dp_training_pattern_symbol(dp_train_pat));
4997
4998         intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
4999 }
5000
5001 static void
5002 intel_dp_link_down(struct intel_encoder *encoder,
5003                    const struct intel_crtc_state *old_crtc_state)
5004 {
5005         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5006         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5007         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
5008         enum port port = encoder->port;
5009         u32 DP = intel_dp->DP;
5010
5011         if (drm_WARN_ON(&dev_priv->drm,
5012                         (intel_de_read(dev_priv, intel_dp->output_reg) &
5013                          DP_PORT_EN) == 0))
5014                 return;
5015
5016         drm_dbg_kms(&dev_priv->drm, "\n");
5017
5018         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
5019             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
5020                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
5021                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
5022         } else {
5023                 DP &= ~DP_LINK_TRAIN_MASK;
5024                 DP |= DP_LINK_TRAIN_PAT_IDLE;
5025         }
5026         intel_de_write(dev_priv, intel_dp->output_reg, DP);
5027         intel_de_posting_read(dev_priv, intel_dp->output_reg);
5028
5029         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
5030         intel_de_write(dev_priv, intel_dp->output_reg, DP);
5031         intel_de_posting_read(dev_priv, intel_dp->output_reg);
5032
5033         /*
5034          * HW workaround for IBX, we need to move the port
5035          * to transcoder A after disabling it to allow the
5036          * matching HDMI port to be enabled on transcoder A.
5037          */
5038         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
5039                 /*
5040                  * We get CPU/PCH FIFO underruns on the other pipe when
5041                  * doing the workaround. Sweep them under the rug.
5042                  */
5043                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5044                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5045
5046                 /* always enable with pattern 1 (as per spec) */
5047                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
5048                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
5049                         DP_LINK_TRAIN_PAT_1;
5050                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
5051                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
5052
5053                 DP &= ~DP_PORT_EN;
5054                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
5055                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
5056
5057                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
5058                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5059                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5060         }
5061
5062         msleep(intel_dp->panel_power_down_delay);
5063
5064         intel_dp->DP = DP;
5065
5066         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5067                 intel_wakeref_t wakeref;
5068
5069                 with_pps_lock(intel_dp, wakeref)
5070                         intel_dp->active_pipe = INVALID_PIPE;
5071         }
5072 }
5073
5074 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
5075 {
5076         u8 dprx = 0;
5077
5078         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
5079                               &dprx) != 1)
5080                 return false;
5081         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
5082 }
5083
5084 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
5085 {
5086         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5087
5088         /*
5089          * Clear the cached register set to avoid using stale values
5090          * for the sinks that do not support DSC.
5091          */
5092         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5093
5094         /* Clear fec_capable to avoid using stale values */
5095         intel_dp->fec_capable = 0;
5096
5097         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
5098         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
5099             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
5100                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
5101                                      intel_dp->dsc_dpcd,
5102                                      sizeof(intel_dp->dsc_dpcd)) < 0)
5103                         drm_err(&i915->drm,
5104                                 "Failed to read DPCD register 0x%x\n",
5105                                 DP_DSC_SUPPORT);
5106
5107                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
5108                             (int)sizeof(intel_dp->dsc_dpcd),
5109                             intel_dp->dsc_dpcd);
5110
5111                 /* FEC is supported only on DP 1.4 */
5112                 if (!intel_dp_is_edp(intel_dp) &&
5113                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
5114                                       &intel_dp->fec_capable) < 0)
5115                         drm_err(&i915->drm,
5116                                 "Failed to read FEC DPCD register\n");
5117
5118                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
5119                             intel_dp->fec_capable);
5120         }
5121 }
5122
5123 static bool
5124 intel_edp_init_dpcd(struct intel_dp *intel_dp)
5125 {
5126         struct drm_i915_private *dev_priv =
5127                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5128
5129         /* this function is meant to be called only once */
5130         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
5131
5132         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
5133                 return false;
5134
5135         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5136                          drm_dp_is_branch(intel_dp->dpcd));
5137
5138         /*
5139          * Read the eDP display control registers.
5140          *
5141          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
5142          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
5143          * set, but require eDP 1.4+ detection (e.g. for supported link rates
5144          * method). The display control registers should read zero if they're
5145          * not supported anyway.
5146          */
5147         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
5148                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
5149                              sizeof(intel_dp->edp_dpcd))
5150                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
5151                             (int)sizeof(intel_dp->edp_dpcd),
5152                             intel_dp->edp_dpcd);
5153
5154         /*
5155          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
5156          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
5157          */
5158         intel_psr_init_dpcd(intel_dp);
5159
5160         /* Read the eDP 1.4+ supported link rates. */
5161         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
5162                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
5163                 int i;
5164
5165                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
5166                                 sink_rates, sizeof(sink_rates));
5167
5168                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
5169                         int val = le16_to_cpu(sink_rates[i]);
5170
5171                         if (val == 0)
5172                                 break;
5173
5174                         /* Value read multiplied by 200kHz gives the per-lane
5175                          * link rate in kHz. The source rates are, however,
5176                          * stored in terms of LS_Clk kHz. The full conversion
5177                          * back to symbols is
5178                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
5179                          */
5180                         intel_dp->sink_rates[i] = (val * 200) / 10;
5181                 }
5182                 intel_dp->num_sink_rates = i;
5183         }
5184
5185         /*
5186          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
5187          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
5188          */
5189         if (intel_dp->num_sink_rates)
5190                 intel_dp->use_rate_select = true;
5191         else
5192                 intel_dp_set_sink_rates(intel_dp);
5193
5194         intel_dp_set_common_rates(intel_dp);
5195
5196         /* Read the eDP DSC DPCD registers */
5197         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5198                 intel_dp_get_dsc_sink_cap(intel_dp);
5199
5200         return true;
5201 }
5202
5203 static bool
5204 intel_dp_has_sink_count(struct intel_dp *intel_dp)
5205 {
5206         if (!intel_dp->attached_connector)
5207                 return false;
5208
5209         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
5210                                           intel_dp->dpcd,
5211                                           &intel_dp->desc);
5212 }
5213
5214 static bool
5215 intel_dp_get_dpcd(struct intel_dp *intel_dp)
5216 {
5217         int ret;
5218
5219         intel_dp_lttpr_init(intel_dp);
5220
5221         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
5222                 return false;
5223
5224         /*
5225          * Don't clobber cached eDP rates. Also skip re-reading
5226          * the OUI/ID since we know it won't change.
5227          */
5228         if (!intel_dp_is_edp(intel_dp)) {
5229                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5230                                  drm_dp_is_branch(intel_dp->dpcd));
5231
5232                 intel_dp_set_sink_rates(intel_dp);
5233                 intel_dp_set_common_rates(intel_dp);
5234         }
5235
5236         if (intel_dp_has_sink_count(intel_dp)) {
5237                 ret = drm_dp_read_sink_count(&intel_dp->aux);
5238                 if (ret < 0)
5239                         return false;
5240
5241                 /*
5242                  * Sink count can change between short pulse hpd hence
5243                  * a member variable in intel_dp will track any changes
5244                  * between short pulse interrupts.
5245                  */
5246                 intel_dp->sink_count = ret;
5247
5248                 /*
5249                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
5250                  * a dongle is present but no display. Unless we require to know
5251                  * if a dongle is present or not, we don't need to update
5252                  * downstream port information. So, an early return here saves
5253                  * time from performing other operations which are not required.
5254                  */
5255                 if (!intel_dp->sink_count)
5256                         return false;
5257         }
5258
5259         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
5260                                            intel_dp->downstream_ports) == 0;
5261 }
5262
5263 static bool
5264 intel_dp_can_mst(struct intel_dp *intel_dp)
5265 {
5266         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5267
5268         return i915->params.enable_dp_mst &&
5269                 intel_dp->can_mst &&
5270                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
5271 }
5272
5273 static void
5274 intel_dp_configure_mst(struct intel_dp *intel_dp)
5275 {
5276         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5277         struct intel_encoder *encoder =
5278                 &dp_to_dig_port(intel_dp)->base;
5279         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
5280
5281         drm_dbg_kms(&i915->drm,
5282                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
5283                     encoder->base.base.id, encoder->base.name,
5284                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
5285                     yesno(i915->params.enable_dp_mst));
5286
5287         if (!intel_dp->can_mst)
5288                 return;
5289
5290         intel_dp->is_mst = sink_can_mst &&
5291                 i915->params.enable_dp_mst;
5292
5293         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5294                                         intel_dp->is_mst);
5295 }
5296
5297 static bool
5298 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
5299 {
5300         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
5301                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
5302                 DP_DPRX_ESI_LEN;
5303 }
5304
5305 bool
5306 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
5307                        const struct drm_connector_state *conn_state)
5308 {
5309         /*
5310          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
5311          * of Color Encoding Format and Content Color Gamut], in order to
5312          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
5313          */
5314         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5315                 return true;
5316
5317         switch (conn_state->colorspace) {
5318         case DRM_MODE_COLORIMETRY_SYCC_601:
5319         case DRM_MODE_COLORIMETRY_OPYCC_601:
5320         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5321         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5322         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
5323                 return true;
5324         default:
5325                 break;
5326         }
5327
5328         return false;
5329 }
5330
5331 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
5332                                      struct dp_sdp *sdp, size_t size)
5333 {
5334         size_t length = sizeof(struct dp_sdp);
5335
5336         if (size < length)
5337                 return -ENOSPC;
5338
5339         memset(sdp, 0, size);
5340
5341         /*
5342          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
5343          * VSC SDP Header Bytes
5344          */
5345         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
5346         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
5347         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
5348         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
5349
5350         /*
5351          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
5352          * per DP 1.4a spec.
5353          */
5354         if (vsc->revision != 0x5)
5355                 goto out;
5356
5357         /* VSC SDP Payload for DB16 through DB18 */
5358         /* Pixel Encoding and Colorimetry Formats  */
5359         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
5360         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
5361
5362         switch (vsc->bpc) {
5363         case 6:
5364                 /* 6bpc: 0x0 */
5365                 break;
5366         case 8:
5367                 sdp->db[17] = 0x1; /* DB17[3:0] */
5368                 break;
5369         case 10:
5370                 sdp->db[17] = 0x2;
5371                 break;
5372         case 12:
5373                 sdp->db[17] = 0x3;
5374                 break;
5375         case 16:
5376                 sdp->db[17] = 0x4;
5377                 break;
5378         default:
5379                 MISSING_CASE(vsc->bpc);
5380                 break;
5381         }
5382         /* Dynamic Range and Component Bit Depth */
5383         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
5384                 sdp->db[17] |= 0x80;  /* DB17[7] */
5385
5386         /* Content Type */
5387         sdp->db[18] = vsc->content_type & 0x7;
5388
5389 out:
5390         return length;
5391 }
5392
5393 static ssize_t
5394 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
5395                                          struct dp_sdp *sdp,
5396                                          size_t size)
5397 {
5398         size_t length = sizeof(struct dp_sdp);
5399         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5400         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5401         ssize_t len;
5402
5403         if (size < length)
5404                 return -ENOSPC;
5405
5406         memset(sdp, 0, size);
5407
5408         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
5409         if (len < 0) {
5410                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
5411                 return -ENOSPC;
5412         }
5413
5414         if (len != infoframe_size) {
5415                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
5416                 return -ENOSPC;
5417         }
5418
5419         /*
5420          * Set up the infoframe sdp packet for HDR static metadata.
5421          * Prepare VSC Header for SU as per DP 1.4a spec,
5422          * Table 2-100 and Table 2-101
5423          */
5424
5425         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
5426         sdp->sdp_header.HB0 = 0;
5427         /*
5428          * Packet Type 80h + Non-audio INFOFRAME Type value
5429          * HDMI_INFOFRAME_TYPE_DRM: 0x87
5430          * - 80h + Non-audio INFOFRAME Type value
5431          * - InfoFrame Type: 0x07
5432          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
5433          */
5434         sdp->sdp_header.HB1 = drm_infoframe->type;
5435         /*
5436          * Least Significant Eight Bits of (Data Byte Count – 1)
5437          * infoframe_size - 1
5438          */
5439         sdp->sdp_header.HB2 = 0x1D;
5440         /* INFOFRAME SDP Version Number */
5441         sdp->sdp_header.HB3 = (0x13 << 2);
5442         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5443         sdp->db[0] = drm_infoframe->version;
5444         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5445         sdp->db[1] = drm_infoframe->length;
5446         /*
5447          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5448          * HDMI_INFOFRAME_HEADER_SIZE
5449          */
5450         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5451         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5452                HDMI_DRM_INFOFRAME_SIZE);
5453
5454         /*
5455          * Size of DP infoframe sdp packet for HDR static metadata consists of
5456          * - DP SDP Header(struct dp_sdp_header): 4 bytes
5457          * - Two Data Blocks: 2 bytes
5458          *    CTA Header Byte2 (INFOFRAME Version Number)
5459          *    CTA Header Byte3 (Length of INFOFRAME)
5460          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5461          *
5462          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5463          * infoframe size. But GEN11+ has larger than that size, write_infoframe
5464          * will pad rest of the size.
5465          */
5466         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
5467 }
5468
5469 static void intel_write_dp_sdp(struct intel_encoder *encoder,
5470                                const struct intel_crtc_state *crtc_state,
5471                                unsigned int type)
5472 {
5473         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5474         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5475         struct dp_sdp sdp = {};
5476         ssize_t len;
5477
5478         if ((crtc_state->infoframes.enable &
5479              intel_hdmi_infoframe_enable(type)) == 0)
5480                 return;
5481
5482         switch (type) {
5483         case DP_SDP_VSC:
5484                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
5485                                             sizeof(sdp));
5486                 break;
5487         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5488                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
5489                                                                &sdp, sizeof(sdp));
5490                 break;
5491         default:
5492                 MISSING_CASE(type);
5493                 return;
5494         }
5495
5496         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5497                 return;
5498
5499         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
5500 }
5501
5502 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
5503                             const struct intel_crtc_state *crtc_state,
5504                             struct drm_dp_vsc_sdp *vsc)
5505 {
5506         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5507         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5508         struct dp_sdp sdp = {};
5509         ssize_t len;
5510
5511         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
5512
5513         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5514                 return;
5515
5516         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
5517                                         &sdp, len);
5518 }
5519
5520 void intel_dp_set_infoframes(struct intel_encoder *encoder,
5521                              bool enable,
5522                              const struct intel_crtc_state *crtc_state,
5523                              const struct drm_connector_state *conn_state)
5524 {
5525         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5526         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5527         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5528         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5529                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5530                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5531         u32 val = intel_de_read(dev_priv, reg);
5532
5533         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5534         /* When PSR is enabled, this routine doesn't disable VSC DIP */
5535         if (intel_psr_enabled(intel_dp))
5536                 val &= ~dip_enable;
5537         else
5538                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5539
5540         if (!enable) {
5541                 intel_de_write(dev_priv, reg, val);
5542                 intel_de_posting_read(dev_priv, reg);
5543                 return;
5544         }
5545
5546         intel_de_write(dev_priv, reg, val);
5547         intel_de_posting_read(dev_priv, reg);
5548
5549         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5550         if (!intel_psr_enabled(intel_dp))
5551                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5552
5553         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5554 }
5555
5556 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
5557                                    const void *buffer, size_t size)
5558 {
5559         const struct dp_sdp *sdp = buffer;
5560
5561         if (size < sizeof(struct dp_sdp))
5562                 return -EINVAL;
5563
5564         memset(vsc, 0, size);
5565
5566         if (sdp->sdp_header.HB0 != 0)
5567                 return -EINVAL;
5568
5569         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
5570                 return -EINVAL;
5571
5572         vsc->sdp_type = sdp->sdp_header.HB1;
5573         vsc->revision = sdp->sdp_header.HB2;
5574         vsc->length = sdp->sdp_header.HB3;
5575
5576         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
5577             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
5578                 /*
5579                  * - HB2 = 0x2, HB3 = 0x8
5580                  *   VSC SDP supporting 3D stereo + PSR
5581                  * - HB2 = 0x4, HB3 = 0xe
5582                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
5583                  *   first scan line of the SU region (applies to eDP v1.4b
5584                  *   and higher).
5585                  */
5586                 return 0;
5587         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
5588                 /*
5589                  * - HB2 = 0x5, HB3 = 0x13
5590                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5591                  *   Format.
5592                  */
5593                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5594                 vsc->colorimetry = sdp->db[16] & 0xf;
5595                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5596
5597                 switch (sdp->db[17] & 0x7) {
5598                 case 0x0:
5599                         vsc->bpc = 6;
5600                         break;
5601                 case 0x1:
5602                         vsc->bpc = 8;
5603                         break;
5604                 case 0x2:
5605                         vsc->bpc = 10;
5606                         break;
5607                 case 0x3:
5608                         vsc->bpc = 12;
5609                         break;
5610                 case 0x4:
5611                         vsc->bpc = 16;
5612                         break;
5613                 default:
5614                         MISSING_CASE(sdp->db[17] & 0x7);
5615                         return -EINVAL;
5616                 }
5617
5618                 vsc->content_type = sdp->db[18] & 0x7;
5619         } else {
5620                 return -EINVAL;
5621         }
5622
5623         return 0;
5624 }
5625
5626 static int
5627 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5628                                            const void *buffer, size_t size)
5629 {
5630         int ret;
5631
5632         const struct dp_sdp *sdp = buffer;
5633
5634         if (size < sizeof(struct dp_sdp))
5635                 return -EINVAL;
5636
5637         if (sdp->sdp_header.HB0 != 0)
5638                 return -EINVAL;
5639
5640         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5641                 return -EINVAL;
5642
5643         /*
5644          * Least Significant Eight Bits of (Data Byte Count – 1)
5645          * 1Dh (i.e., Data Byte Count = 30 bytes).
5646          */
5647         if (sdp->sdp_header.HB2 != 0x1D)
5648                 return -EINVAL;
5649
5650         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5651         if ((sdp->sdp_header.HB3 & 0x3) != 0)
5652                 return -EINVAL;
5653
5654         /* INFOFRAME SDP Version Number */
5655         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5656                 return -EINVAL;
5657
5658         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5659         if (sdp->db[0] != 1)
5660                 return -EINVAL;
5661
5662         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5663         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5664                 return -EINVAL;
5665
5666         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
5667                                              HDMI_DRM_INFOFRAME_SIZE);
5668
5669         return ret;
5670 }
5671
5672 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5673                                   struct intel_crtc_state *crtc_state,
5674                                   struct drm_dp_vsc_sdp *vsc)
5675 {
5676         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5677         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5678         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5679         unsigned int type = DP_SDP_VSC;
5680         struct dp_sdp sdp = {};
5681         int ret;
5682
5683         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5684         if (intel_psr_enabled(intel_dp))
5685                 return;
5686
5687         if ((crtc_state->infoframes.enable &
5688              intel_hdmi_infoframe_enable(type)) == 0)
5689                 return;
5690
5691         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5692
5693         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
5694
5695         if (ret)
5696                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
5697 }
5698
5699 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5700                                                      struct intel_crtc_state *crtc_state,
5701                                                      struct hdmi_drm_infoframe *drm_infoframe)
5702 {
5703         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5704         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5705         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5706         struct dp_sdp sdp = {};
5707         int ret;
5708
5709         if ((crtc_state->infoframes.enable &
5710             intel_hdmi_infoframe_enable(type)) == 0)
5711                 return;
5712
5713         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5714                                  sizeof(sdp));
5715
5716         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
5717                                                          sizeof(sdp));
5718
5719         if (ret)
5720                 drm_dbg_kms(&dev_priv->drm,
5721                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5722 }
5723
5724 void intel_read_dp_sdp(struct intel_encoder *encoder,
5725                        struct intel_crtc_state *crtc_state,
5726                        unsigned int type)
5727 {
5728         if (encoder->type != INTEL_OUTPUT_DDI)
5729                 return;
5730
5731         switch (type) {
5732         case DP_SDP_VSC:
5733                 intel_read_dp_vsc_sdp(encoder, crtc_state,
5734                                       &crtc_state->infoframes.vsc);
5735                 break;
5736         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5737                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5738                                                          &crtc_state->infoframes.drm.drm);
5739                 break;
5740         default:
5741                 MISSING_CASE(type);
5742                 break;
5743         }
5744 }
5745
5746 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5747 {
5748         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5749         int status = 0;
5750         int test_link_rate;
5751         u8 test_lane_count, test_link_bw;
5752         /* (DP CTS 1.2)
5753          * 4.3.1.11
5754          */
5755         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5756         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5757                                    &test_lane_count);
5758
5759         if (status <= 0) {
5760                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5761                 return DP_TEST_NAK;
5762         }
5763         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5764
5765         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5766                                    &test_link_bw);
5767         if (status <= 0) {
5768                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5769                 return DP_TEST_NAK;
5770         }
5771         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5772
5773         /* Validate the requested link rate and lane count */
5774         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5775                                         test_lane_count))
5776                 return DP_TEST_NAK;
5777
5778         intel_dp->compliance.test_lane_count = test_lane_count;
5779         intel_dp->compliance.test_link_rate = test_link_rate;
5780
5781         return DP_TEST_ACK;
5782 }
5783
5784 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5785 {
5786         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5787         u8 test_pattern;
5788         u8 test_misc;
5789         __be16 h_width, v_height;
5790         int status = 0;
5791
5792         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5793         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5794                                    &test_pattern);
5795         if (status <= 0) {
5796                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5797                 return DP_TEST_NAK;
5798         }
5799         if (test_pattern != DP_COLOR_RAMP)
5800                 return DP_TEST_NAK;
5801
5802         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5803                                   &h_width, 2);
5804         if (status <= 0) {
5805                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5806                 return DP_TEST_NAK;
5807         }
5808
5809         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5810                                   &v_height, 2);
5811         if (status <= 0) {
5812                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5813                 return DP_TEST_NAK;
5814         }
5815
5816         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5817                                    &test_misc);
5818         if (status <= 0) {
5819                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5820                 return DP_TEST_NAK;
5821         }
5822         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5823                 return DP_TEST_NAK;
5824         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5825                 return DP_TEST_NAK;
5826         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5827         case DP_TEST_BIT_DEPTH_6:
5828                 intel_dp->compliance.test_data.bpc = 6;
5829                 break;
5830         case DP_TEST_BIT_DEPTH_8:
5831                 intel_dp->compliance.test_data.bpc = 8;
5832                 break;
5833         default:
5834                 return DP_TEST_NAK;
5835         }
5836
5837         intel_dp->compliance.test_data.video_pattern = test_pattern;
5838         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5839         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5840         /* Set test active flag here so userspace doesn't interrupt things */
5841         intel_dp->compliance.test_active = true;
5842
5843         return DP_TEST_ACK;
5844 }
5845
5846 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5847 {
5848         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5849         u8 test_result = DP_TEST_ACK;
5850         struct intel_connector *intel_connector = intel_dp->attached_connector;
5851         struct drm_connector *connector = &intel_connector->base;
5852
5853         if (intel_connector->detect_edid == NULL ||
5854             connector->edid_corrupt ||
5855             intel_dp->aux.i2c_defer_count > 6) {
5856                 /* Check EDID read for NACKs, DEFERs and corruption
5857                  * (DP CTS 1.2 Core r1.1)
5858                  *    4.2.2.4 : Failed EDID read, I2C_NAK
5859                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
5860                  *    4.2.2.6 : EDID corruption detected
5861                  * Use failsafe mode for all cases
5862                  */
5863                 if (intel_dp->aux.i2c_nack_count > 0 ||
5864                         intel_dp->aux.i2c_defer_count > 0)
5865                         drm_dbg_kms(&i915->drm,
5866                                     "EDID read had %d NACKs, %d DEFERs\n",
5867                                     intel_dp->aux.i2c_nack_count,
5868                                     intel_dp->aux.i2c_defer_count);
5869                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5870         } else {
5871                 struct edid *block = intel_connector->detect_edid;
5872
5873                 /* We have to write the checksum
5874                  * of the last block read
5875                  */
5876                 block += intel_connector->detect_edid->extensions;
5877
5878                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5879                                        block->checksum) <= 0)
5880                         drm_dbg_kms(&i915->drm,
5881                                     "Failed to write EDID checksum\n");
5882
5883                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5884                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5885         }
5886
5887         /* Set test active flag here so userspace doesn't interrupt things */
5888         intel_dp->compliance.test_active = true;
5889
5890         return test_result;
5891 }
5892
5893 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
5894                                         const struct intel_crtc_state *crtc_state)
5895 {
5896         struct drm_i915_private *dev_priv =
5897                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5898         struct drm_dp_phy_test_params *data =
5899                         &intel_dp->compliance.test_data.phytest;
5900         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5901         enum pipe pipe = crtc->pipe;
5902         u32 pattern_val;
5903
5904         switch (data->phy_pattern) {
5905         case DP_PHY_TEST_PATTERN_NONE:
5906                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5907                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5908                 break;
5909         case DP_PHY_TEST_PATTERN_D10_2:
5910                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5911                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5912                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5913                 break;
5914         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5915                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5916                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5917                                DDI_DP_COMP_CTL_ENABLE |
5918                                DDI_DP_COMP_CTL_SCRAMBLED_0);
5919                 break;
5920         case DP_PHY_TEST_PATTERN_PRBS7:
5921                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5922                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5923                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5924                 break;
5925         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5926                 /*
5927                  * FIXME: Ideally pattern should come from DPCD 0x250. As
5928                  * current firmware of DPR-100 could not set it, so hardcoding
5929                  * now for complaince test.
5930                  */
5931                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5932                 pattern_val = 0x3e0f83e0;
5933                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5934                 pattern_val = 0x0f83e0f8;
5935                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5936                 pattern_val = 0x0000f83e;
5937                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5938                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5939                                DDI_DP_COMP_CTL_ENABLE |
5940                                DDI_DP_COMP_CTL_CUSTOM80);
5941                 break;
5942         case DP_PHY_TEST_PATTERN_CP2520:
5943                 /*
5944                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
5945                  * current firmware of DPR-100 could not set it, so hardcoding
5946                  * now for complaince test.
5947                  */
5948                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5949                 pattern_val = 0xFB;
5950                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5951                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5952                                pattern_val);
5953                 break;
5954         default:
5955                 WARN(1, "Invalid Phy Test Pattern\n");
5956         }
5957 }
5958
5959 static void
5960 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
5961                                   const struct intel_crtc_state *crtc_state)
5962 {
5963         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5964         struct drm_device *dev = dig_port->base.base.dev;
5965         struct drm_i915_private *dev_priv = to_i915(dev);
5966         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5967         enum pipe pipe = crtc->pipe;
5968         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5969
5970         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5971                                                  TRANS_DDI_FUNC_CTL(pipe));
5972         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5973         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5974
5975         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5976                                       TGL_TRANS_DDI_PORT_MASK);
5977         trans_conf_value &= ~PIPECONF_ENABLE;
5978         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5979
5980         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5981         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5982                        trans_ddi_func_ctl_value);
5983         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5984 }
5985
5986 static void
5987 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
5988                                  const struct intel_crtc_state *crtc_state)
5989 {
5990         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5991         struct drm_device *dev = dig_port->base.base.dev;
5992         struct drm_i915_private *dev_priv = to_i915(dev);
5993         enum port port = dig_port->base.port;
5994         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5995         enum pipe pipe = crtc->pipe;
5996         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5997
5998         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5999                                                  TRANS_DDI_FUNC_CTL(pipe));
6000         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
6001         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
6002
6003         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
6004                                     TGL_TRANS_DDI_SELECT_PORT(port);
6005         trans_conf_value |= PIPECONF_ENABLE;
6006         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
6007
6008         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
6009         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
6010         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
6011                        trans_ddi_func_ctl_value);
6012 }
6013
6014 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
6015                                          const struct intel_crtc_state *crtc_state)
6016 {
6017         struct drm_dp_phy_test_params *data =
6018                 &intel_dp->compliance.test_data.phytest;
6019         u8 link_status[DP_LINK_STATUS_SIZE];
6020
6021         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
6022                                              link_status) < 0) {
6023                 DRM_DEBUG_KMS("failed to get link status\n");
6024                 return;
6025         }
6026
6027         /* retrieve vswing & pre-emphasis setting */
6028         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
6029                                   link_status);
6030
6031         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
6032
6033         intel_dp_set_signal_levels(intel_dp, crtc_state);
6034
6035         intel_dp_phy_pattern_update(intel_dp, crtc_state);
6036
6037         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
6038
6039         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
6040                                     link_status[DP_DPCD_REV]);
6041 }
6042
6043 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
6044 {
6045         struct drm_dp_phy_test_params *data =
6046                 &intel_dp->compliance.test_data.phytest;
6047
6048         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
6049                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
6050                 return DP_TEST_NAK;
6051         }
6052
6053         /* Set test active flag here so userspace doesn't interrupt things */
6054         intel_dp->compliance.test_active = true;
6055
6056         return DP_TEST_ACK;
6057 }
6058
6059 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
6060 {
6061         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6062         u8 response = DP_TEST_NAK;
6063         u8 request = 0;
6064         int status;
6065
6066         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
6067         if (status <= 0) {
6068                 drm_dbg_kms(&i915->drm,
6069                             "Could not read test request from sink\n");
6070                 goto update_status;
6071         }
6072
6073         switch (request) {
6074         case DP_TEST_LINK_TRAINING:
6075                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
6076                 response = intel_dp_autotest_link_training(intel_dp);
6077                 break;
6078         case DP_TEST_LINK_VIDEO_PATTERN:
6079                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
6080                 response = intel_dp_autotest_video_pattern(intel_dp);
6081                 break;
6082         case DP_TEST_LINK_EDID_READ:
6083                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
6084                 response = intel_dp_autotest_edid(intel_dp);
6085                 break;
6086         case DP_TEST_LINK_PHY_TEST_PATTERN:
6087                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
6088                 response = intel_dp_autotest_phy_pattern(intel_dp);
6089                 break;
6090         default:
6091                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
6092                             request);
6093                 break;
6094         }
6095
6096         if (response & DP_TEST_ACK)
6097                 intel_dp->compliance.test_type = request;
6098
6099 update_status:
6100         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
6101         if (status <= 0)
6102                 drm_dbg_kms(&i915->drm,
6103                             "Could not write test response to sink\n");
6104 }
6105
6106 /**
6107  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
6108  * @intel_dp: Intel DP struct
6109  *
6110  * Read any pending MST interrupts, call MST core to handle these and ack the
6111  * interrupts. Check if the main and AUX link state is ok.
6112  *
6113  * Returns:
6114  * - %true if pending interrupts were serviced (or no interrupts were
6115  *   pending) w/o detecting an error condition.
6116  * - %false if an error condition - like AUX failure or a loss of link - is
6117  *   detected, which needs servicing from the hotplug work.
6118  */
6119 static bool
6120 intel_dp_check_mst_status(struct intel_dp *intel_dp)
6121 {
6122         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6123         bool link_ok = true;
6124
6125         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
6126
6127         for (;;) {
6128                 u8 esi[DP_DPRX_ESI_LEN] = {};
6129                 bool handled;
6130                 int retry;
6131
6132                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
6133                         drm_dbg_kms(&i915->drm,
6134                                     "failed to get ESI - device may have failed\n");
6135                         link_ok = false;
6136
6137                         break;
6138                 }
6139
6140                 /* check link status - esi[10] = 0x200c */
6141                 if (intel_dp->active_mst_links > 0 && link_ok &&
6142                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
6143                         drm_dbg_kms(&i915->drm,
6144                                     "channel EQ not ok, retraining\n");
6145                         link_ok = false;
6146                 }
6147
6148                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
6149
6150                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
6151                 if (!handled)
6152                         break;
6153
6154                 for (retry = 0; retry < 3; retry++) {
6155                         int wret;
6156
6157                         wret = drm_dp_dpcd_write(&intel_dp->aux,
6158                                                  DP_SINK_COUNT_ESI+1,
6159                                                  &esi[1], 3);
6160                         if (wret == 3)
6161                                 break;
6162                 }
6163         }
6164
6165         return link_ok;
6166 }
6167
6168 static void
6169 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
6170 {
6171         bool is_active;
6172         u8 buf = 0;
6173
6174         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
6175         if (intel_dp->frl.is_trained && !is_active) {
6176                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
6177                         return;
6178
6179                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
6180                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
6181                         return;
6182
6183                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
6184
6185                 /* Restart FRL training or fall back to TMDS mode */
6186                 intel_dp_check_frl_training(intel_dp);
6187         }
6188 }
6189
6190 static bool
6191 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
6192 {
6193         u8 link_status[DP_LINK_STATUS_SIZE];
6194
6195         if (!intel_dp->link_trained)
6196                 return false;
6197
6198         /*
6199          * While PSR source HW is enabled, it will control main-link sending
6200          * frames, enabling and disabling it so trying to do a retrain will fail
6201          * as the link would or not be on or it could mix training patterns
6202          * and frame data at the same time causing retrain to fail.
6203          * Also when exiting PSR, HW will retrain the link anyways fixing
6204          * any link status error.
6205          */
6206         if (intel_psr_enabled(intel_dp))
6207                 return false;
6208
6209         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
6210                                              link_status) < 0)
6211                 return false;
6212
6213         /*
6214          * Validate the cached values of intel_dp->link_rate and
6215          * intel_dp->lane_count before attempting to retrain.
6216          *
6217          * FIXME would be nice to user the crtc state here, but since
6218          * we need to call this from the short HPD handler that seems
6219          * a bit hard.
6220          */
6221         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
6222                                         intel_dp->lane_count))
6223                 return false;
6224
6225         /* Retrain if Channel EQ or CR not ok */
6226         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
6227 }
6228
6229 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
6230                                    const struct drm_connector_state *conn_state)
6231 {
6232         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6233         struct intel_encoder *encoder;
6234         enum pipe pipe;
6235
6236         if (!conn_state->best_encoder)
6237                 return false;
6238
6239         /* SST */
6240         encoder = &dp_to_dig_port(intel_dp)->base;
6241         if (conn_state->best_encoder == &encoder->base)
6242                 return true;
6243
6244         /* MST */
6245         for_each_pipe(i915, pipe) {
6246                 encoder = &intel_dp->mst_encoders[pipe]->base;
6247                 if (conn_state->best_encoder == &encoder->base)
6248                         return true;
6249         }
6250
6251         return false;
6252 }
6253
6254 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
6255                                       struct drm_modeset_acquire_ctx *ctx,
6256                                       u32 *crtc_mask)
6257 {
6258         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6259         struct drm_connector_list_iter conn_iter;
6260         struct intel_connector *connector;
6261         int ret = 0;
6262
6263         *crtc_mask = 0;
6264
6265         if (!intel_dp_needs_link_retrain(intel_dp))
6266                 return 0;
6267
6268         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
6269         for_each_intel_connector_iter(connector, &conn_iter) {
6270                 struct drm_connector_state *conn_state =
6271                         connector->base.state;
6272                 struct intel_crtc_state *crtc_state;
6273                 struct intel_crtc *crtc;
6274
6275                 if (!intel_dp_has_connector(intel_dp, conn_state))
6276                         continue;
6277
6278                 crtc = to_intel_crtc(conn_state->crtc);
6279                 if (!crtc)
6280                         continue;
6281
6282                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6283                 if (ret)
6284                         break;
6285
6286                 crtc_state = to_intel_crtc_state(crtc->base.state);
6287
6288                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
6289
6290                 if (!crtc_state->hw.active)
6291                         continue;
6292
6293                 if (conn_state->commit &&
6294                     !try_wait_for_completion(&conn_state->commit->hw_done))
6295                         continue;
6296
6297                 *crtc_mask |= drm_crtc_mask(&crtc->base);
6298         }
6299         drm_connector_list_iter_end(&conn_iter);
6300
6301         if (!intel_dp_needs_link_retrain(intel_dp))
6302                 *crtc_mask = 0;
6303
6304         return ret;
6305 }
6306
6307 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
6308 {
6309         struct intel_connector *connector = intel_dp->attached_connector;
6310
6311         return connector->base.status == connector_status_connected ||
6312                 intel_dp->is_mst;
6313 }
6314
6315 int intel_dp_retrain_link(struct intel_encoder *encoder,
6316                           struct drm_modeset_acquire_ctx *ctx)
6317 {
6318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6319         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6320         struct intel_crtc *crtc;
6321         u32 crtc_mask;
6322         int ret;
6323
6324         if (!intel_dp_is_connected(intel_dp))
6325                 return 0;
6326
6327         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
6328                                ctx);
6329         if (ret)
6330                 return ret;
6331
6332         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
6333         if (ret)
6334                 return ret;
6335
6336         if (crtc_mask == 0)
6337                 return 0;
6338
6339         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
6340                     encoder->base.base.id, encoder->base.name);
6341
6342         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6343                 const struct intel_crtc_state *crtc_state =
6344                         to_intel_crtc_state(crtc->base.state);
6345
6346                 /* Suppress underruns caused by re-training */
6347                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
6348                 if (crtc_state->has_pch_encoder)
6349                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6350                                                               intel_crtc_pch_transcoder(crtc), false);
6351         }
6352
6353         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6354                 const struct intel_crtc_state *crtc_state =
6355                         to_intel_crtc_state(crtc->base.state);
6356
6357                 /* retrain on the MST master transcoder */
6358                 if (INTEL_GEN(dev_priv) >= 12 &&
6359                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6360                     !intel_dp_mst_is_master_trans(crtc_state))
6361                         continue;
6362
6363                 intel_dp_check_frl_training(intel_dp);
6364                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
6365                 intel_dp_start_link_train(intel_dp, crtc_state);
6366                 intel_dp_stop_link_train(intel_dp, crtc_state);
6367                 break;
6368         }
6369
6370         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6371                 const struct intel_crtc_state *crtc_state =
6372                         to_intel_crtc_state(crtc->base.state);
6373
6374                 /* Keep underrun reporting disabled until things are stable */
6375                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6376
6377                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6378                 if (crtc_state->has_pch_encoder)
6379                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6380                                                               intel_crtc_pch_transcoder(crtc), true);
6381         }
6382
6383         return 0;
6384 }
6385
6386 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
6387                                   struct drm_modeset_acquire_ctx *ctx,
6388                                   u32 *crtc_mask)
6389 {
6390         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6391         struct drm_connector_list_iter conn_iter;
6392         struct intel_connector *connector;
6393         int ret = 0;
6394
6395         *crtc_mask = 0;
6396
6397         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
6398         for_each_intel_connector_iter(connector, &conn_iter) {
6399                 struct drm_connector_state *conn_state =
6400                         connector->base.state;
6401                 struct intel_crtc_state *crtc_state;
6402                 struct intel_crtc *crtc;
6403
6404                 if (!intel_dp_has_connector(intel_dp, conn_state))
6405                         continue;
6406
6407                 crtc = to_intel_crtc(conn_state->crtc);
6408                 if (!crtc)
6409                         continue;
6410
6411                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6412                 if (ret)
6413                         break;
6414
6415                 crtc_state = to_intel_crtc_state(crtc->base.state);
6416
6417                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
6418
6419                 if (!crtc_state->hw.active)
6420                         continue;
6421
6422                 if (conn_state->commit &&
6423                     !try_wait_for_completion(&conn_state->commit->hw_done))
6424                         continue;
6425
6426                 *crtc_mask |= drm_crtc_mask(&crtc->base);
6427         }
6428         drm_connector_list_iter_end(&conn_iter);
6429
6430         return ret;
6431 }
6432
6433 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
6434                                 struct drm_modeset_acquire_ctx *ctx)
6435 {
6436         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6437         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6438         struct intel_crtc *crtc;
6439         u32 crtc_mask;
6440         int ret;
6441
6442         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
6443                                ctx);
6444         if (ret)
6445                 return ret;
6446
6447         ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
6448         if (ret)
6449                 return ret;
6450
6451         if (crtc_mask == 0)
6452                 return 0;
6453
6454         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
6455                     encoder->base.base.id, encoder->base.name);
6456
6457         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6458                 const struct intel_crtc_state *crtc_state =
6459                         to_intel_crtc_state(crtc->base.state);
6460
6461                 /* test on the MST master transcoder */
6462                 if (INTEL_GEN(dev_priv) >= 12 &&
6463                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6464                     !intel_dp_mst_is_master_trans(crtc_state))
6465                         continue;
6466
6467                 intel_dp_process_phy_request(intel_dp, crtc_state);
6468                 break;
6469         }
6470
6471         return 0;
6472 }
6473
6474 static void intel_dp_phy_test(struct intel_encoder *encoder)
6475 {
6476         struct drm_modeset_acquire_ctx ctx;
6477         int ret;
6478
6479         drm_modeset_acquire_init(&ctx, 0);
6480
6481         for (;;) {
6482                 ret = intel_dp_do_phy_test(encoder, &ctx);
6483
6484                 if (ret == -EDEADLK) {
6485                         drm_modeset_backoff(&ctx);
6486                         continue;
6487                 }
6488
6489                 break;
6490         }
6491
6492         drm_modeset_drop_locks(&ctx);
6493         drm_modeset_acquire_fini(&ctx);
6494         drm_WARN(encoder->base.dev, ret,
6495                  "Acquiring modeset locks failed with %i\n", ret);
6496 }
6497
6498 /*
6499  * If display is now connected check links status,
6500  * there has been known issues of link loss triggering
6501  * long pulse.
6502  *
6503  * Some sinks (eg. ASUS PB287Q) seem to perform some
6504  * weird HPD ping pong during modesets. So we can apparently
6505  * end up with HPD going low during a modeset, and then
6506  * going back up soon after. And once that happens we must
6507  * retrain the link to get a picture. That's in case no
6508  * userspace component reacted to intermittent HPD dip.
6509  */
6510 static enum intel_hotplug_state
6511 intel_dp_hotplug(struct intel_encoder *encoder,
6512                  struct intel_connector *connector)
6513 {
6514         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6515         struct drm_modeset_acquire_ctx ctx;
6516         enum intel_hotplug_state state;
6517         int ret;
6518
6519         if (intel_dp->compliance.test_active &&
6520             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
6521                 intel_dp_phy_test(encoder);
6522                 /* just do the PHY test and nothing else */
6523                 return INTEL_HOTPLUG_UNCHANGED;
6524         }
6525
6526         state = intel_encoder_hotplug(encoder, connector);
6527
6528         drm_modeset_acquire_init(&ctx, 0);
6529
6530         for (;;) {
6531                 ret = intel_dp_retrain_link(encoder, &ctx);
6532
6533                 if (ret == -EDEADLK) {
6534                         drm_modeset_backoff(&ctx);
6535                         continue;
6536                 }
6537
6538                 break;
6539         }
6540
6541         drm_modeset_drop_locks(&ctx);
6542         drm_modeset_acquire_fini(&ctx);
6543         drm_WARN(encoder->base.dev, ret,
6544                  "Acquiring modeset locks failed with %i\n", ret);
6545
6546         /*
6547          * Keeping it consistent with intel_ddi_hotplug() and
6548          * intel_hdmi_hotplug().
6549          */
6550         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
6551                 state = INTEL_HOTPLUG_RETRY;
6552
6553         return state;
6554 }
6555
6556 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
6557 {
6558         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6559         u8 val;
6560
6561         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
6562                 return;
6563
6564         if (drm_dp_dpcd_readb(&intel_dp->aux,
6565                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
6566                 return;
6567
6568         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
6569
6570         if (val & DP_AUTOMATED_TEST_REQUEST)
6571                 intel_dp_handle_test_request(intel_dp);
6572
6573         if (val & DP_CP_IRQ)
6574                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
6575
6576         if (val & DP_SINK_SPECIFIC_IRQ)
6577                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
6578 }
6579
6580 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
6581 {
6582         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6583         u8 val;
6584
6585         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
6586                 return;
6587
6588         if (drm_dp_dpcd_readb(&intel_dp->aux,
6589                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) {
6590                 drm_dbg_kms(&i915->drm, "Error in reading link service irq vector\n");
6591                 return;
6592         }
6593
6594         if (drm_dp_dpcd_writeb(&intel_dp->aux,
6595                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
6596                 drm_dbg_kms(&i915->drm, "Error in writing link service irq vector\n");
6597                 return;
6598         }
6599
6600         if (val & HDMI_LINK_STATUS_CHANGED)
6601                 intel_dp_handle_hdmi_link_status_change(intel_dp);
6602 }
6603
6604 /*
6605  * According to DP spec
6606  * 5.1.2:
6607  *  1. Read DPCD
6608  *  2. Configure link according to Receiver Capabilities
6609  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
6610  *  4. Check link status on receipt of hot-plug interrupt
6611  *
6612  * intel_dp_short_pulse -  handles short pulse interrupts
6613  * when full detection is not required.
6614  * Returns %true if short pulse is handled and full detection
6615  * is NOT required and %false otherwise.
6616  */
6617 static bool
6618 intel_dp_short_pulse(struct intel_dp *intel_dp)
6619 {
6620         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6621         u8 old_sink_count = intel_dp->sink_count;
6622         bool ret;
6623
6624         /*
6625          * Clearing compliance test variables to allow capturing
6626          * of values for next automated test request.
6627          */
6628         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6629
6630         /*
6631          * Now read the DPCD to see if it's actually running
6632          * If the current value of sink count doesn't match with
6633          * the value that was stored earlier or dpcd read failed
6634          * we need to do full detection
6635          */
6636         ret = intel_dp_get_dpcd(intel_dp);
6637
6638         if ((old_sink_count != intel_dp->sink_count) || !ret) {
6639                 /* No need to proceed if we are going to do full detect */
6640                 return false;
6641         }
6642
6643         intel_dp_check_device_service_irq(intel_dp);
6644         intel_dp_check_link_service_irq(intel_dp);
6645
6646         /* Handle CEC interrupts, if any */
6647         drm_dp_cec_irq(&intel_dp->aux);
6648
6649         /* defer to the hotplug work for link retraining if needed */
6650         if (intel_dp_needs_link_retrain(intel_dp))
6651                 return false;
6652
6653         intel_psr_short_pulse(intel_dp);
6654
6655         switch (intel_dp->compliance.test_type) {
6656         case DP_TEST_LINK_TRAINING:
6657                 drm_dbg_kms(&dev_priv->drm,
6658                             "Link Training Compliance Test requested\n");
6659                 /* Send a Hotplug Uevent to userspace to start modeset */
6660                 drm_kms_helper_hotplug_event(&dev_priv->drm);
6661                 break;
6662         case DP_TEST_LINK_PHY_TEST_PATTERN:
6663                 drm_dbg_kms(&dev_priv->drm,
6664                             "PHY test pattern Compliance Test requested\n");
6665                 /*
6666                  * Schedule long hpd to do the test
6667                  *
6668                  * FIXME get rid of the ad-hoc phy test modeset code
6669                  * and properly incorporate it into the normal modeset.
6670                  */
6671                 return false;
6672         }
6673
6674         return true;
6675 }
6676
6677 /* XXX this is probably wrong for multiple downstream ports */
6678 static enum drm_connector_status
6679 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
6680 {
6681         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6682         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6683         u8 *dpcd = intel_dp->dpcd;
6684         u8 type;
6685
6686         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
6687                 return connector_status_connected;
6688
6689         lspcon_resume(dig_port);
6690
6691         if (!intel_dp_get_dpcd(intel_dp))
6692                 return connector_status_disconnected;
6693
6694         /* if there's no downstream port, we're done */
6695         if (!drm_dp_is_branch(dpcd))
6696                 return connector_status_connected;
6697
6698         /* If we're HPD-aware, SINK_COUNT changes dynamically */
6699         if (intel_dp_has_sink_count(intel_dp) &&
6700             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
6701                 return intel_dp->sink_count ?
6702                 connector_status_connected : connector_status_disconnected;
6703         }
6704
6705         if (intel_dp_can_mst(intel_dp))
6706                 return connector_status_connected;
6707
6708         /* If no HPD, poke DDC gently */
6709         if (drm_probe_ddc(&intel_dp->aux.ddc))
6710                 return connector_status_connected;
6711
6712         /* Well we tried, say unknown for unreliable port types */
6713         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
6714                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
6715                 if (type == DP_DS_PORT_TYPE_VGA ||
6716                     type == DP_DS_PORT_TYPE_NON_EDID)
6717                         return connector_status_unknown;
6718         } else {
6719                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
6720                         DP_DWN_STRM_PORT_TYPE_MASK;
6721                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
6722                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
6723                         return connector_status_unknown;
6724         }
6725
6726         /* Anything else is out of spec, warn and ignore */
6727         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
6728         return connector_status_disconnected;
6729 }
6730
6731 static enum drm_connector_status
6732 edp_detect(struct intel_dp *intel_dp)
6733 {
6734         return connector_status_connected;
6735 }
6736
6737 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
6738 {
6739         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6740         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
6741
6742         return intel_de_read(dev_priv, SDEISR) & bit;
6743 }
6744
6745 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6746 {
6747         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6748         u32 bit;
6749
6750         switch (encoder->hpd_pin) {
6751         case HPD_PORT_B:
6752                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6753                 break;
6754         case HPD_PORT_C:
6755                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6756                 break;
6757         case HPD_PORT_D:
6758                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6759                 break;
6760         default:
6761                 MISSING_CASE(encoder->hpd_pin);
6762                 return false;
6763         }
6764
6765         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6766 }
6767
6768 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6769 {
6770         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6771         u32 bit;
6772
6773         switch (encoder->hpd_pin) {
6774         case HPD_PORT_B:
6775                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6776                 break;
6777         case HPD_PORT_C:
6778                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6779                 break;
6780         case HPD_PORT_D:
6781                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6782                 break;
6783         default:
6784                 MISSING_CASE(encoder->hpd_pin);
6785                 return false;
6786         }
6787
6788         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6789 }
6790
6791 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6792 {
6793         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6794         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
6795
6796         return intel_de_read(dev_priv, DEISR) & bit;
6797 }
6798
6799 /*
6800  * intel_digital_port_connected - is the specified port connected?
6801  * @encoder: intel_encoder
6802  *
6803  * In cases where there's a connector physically connected but it can't be used
6804  * by our hardware we also return false, since the rest of the driver should
6805  * pretty much treat the port as disconnected. This is relevant for type-C
6806  * (starting on ICL) where there's ownership involved.
6807  *
6808  * Return %true if port is connected, %false otherwise.
6809  */
6810 bool intel_digital_port_connected(struct intel_encoder *encoder)
6811 {
6812         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6813         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6814         bool is_connected = false;
6815         intel_wakeref_t wakeref;
6816
6817         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6818                 is_connected = dig_port->connected(encoder);
6819
6820         return is_connected;
6821 }
6822
6823 static struct edid *
6824 intel_dp_get_edid(struct intel_dp *intel_dp)
6825 {
6826         struct intel_connector *intel_connector = intel_dp->attached_connector;
6827
6828         /* use cached edid if we have one */
6829         if (intel_connector->edid) {
6830                 /* invalid edid */
6831                 if (IS_ERR(intel_connector->edid))
6832                         return NULL;
6833
6834                 return drm_edid_duplicate(intel_connector->edid);
6835         } else
6836                 return drm_get_edid(&intel_connector->base,
6837                                     &intel_dp->aux.ddc);
6838 }
6839
6840 static void
6841 intel_dp_update_dfp(struct intel_dp *intel_dp,
6842                     const struct edid *edid)
6843 {
6844         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6845         struct intel_connector *connector = intel_dp->attached_connector;
6846
6847         intel_dp->dfp.max_bpc =
6848                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
6849                                           intel_dp->downstream_ports, edid);
6850
6851         intel_dp->dfp.max_dotclock =
6852                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
6853                                                intel_dp->downstream_ports);
6854
6855         intel_dp->dfp.min_tmds_clock =
6856                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
6857                                                  intel_dp->downstream_ports,
6858                                                  edid);
6859         intel_dp->dfp.max_tmds_clock =
6860                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
6861                                                  intel_dp->downstream_ports,
6862                                                  edid);
6863
6864         intel_dp->dfp.pcon_max_frl_bw =
6865                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
6866                                            intel_dp->downstream_ports);
6867
6868         drm_dbg_kms(&i915->drm,
6869                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
6870                     connector->base.base.id, connector->base.name,
6871                     intel_dp->dfp.max_bpc,
6872                     intel_dp->dfp.max_dotclock,
6873                     intel_dp->dfp.min_tmds_clock,
6874                     intel_dp->dfp.max_tmds_clock,
6875                     intel_dp->dfp.pcon_max_frl_bw);
6876
6877         intel_dp_get_pcon_dsc_cap(intel_dp);
6878 }
6879
6880 static void
6881 intel_dp_update_420(struct intel_dp *intel_dp)
6882 {
6883         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6884         struct intel_connector *connector = intel_dp->attached_connector;
6885         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
6886
6887         /* No YCbCr output support on gmch platforms */
6888         if (HAS_GMCH(i915))
6889                 return;
6890
6891         /*
6892          * ILK doesn't seem capable of DP YCbCr output. The
6893          * displayed image is severly corrupted. SNB+ is fine.
6894          */
6895         if (IS_GEN(i915, 5))
6896                 return;
6897
6898         is_branch = drm_dp_is_branch(intel_dp->dpcd);
6899         ycbcr_420_passthrough =
6900                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
6901                                                   intel_dp->downstream_ports);
6902         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
6903         ycbcr_444_to_420 =
6904                 dp_to_dig_port(intel_dp)->lspcon.active ||
6905                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
6906                                                         intel_dp->downstream_ports);
6907         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
6908                                                                  intel_dp->downstream_ports,
6909                                                                  DP_DS_HDMI_BT601_RGB_YCBCR_CONV ||
6910                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV ||
6911                                                                  DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
6912
6913         if (INTEL_GEN(i915) >= 11) {
6914                 /* Let PCON convert from RGB->YCbCr if possible */
6915                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
6916                         intel_dp->dfp.rgb_to_ycbcr = true;
6917                         intel_dp->dfp.ycbcr_444_to_420 = true;
6918                         connector->base.ycbcr_420_allowed = true;
6919                 } else {
6920                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
6921                         intel_dp->dfp.ycbcr_444_to_420 =
6922                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
6923
6924                         connector->base.ycbcr_420_allowed =
6925                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
6926                 }
6927         } else {
6928                 /* 4:4:4->4:2:0 conversion is the only way */
6929                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
6930
6931                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
6932         }
6933
6934         drm_dbg_kms(&i915->drm,
6935                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
6936                     connector->base.base.id, connector->base.name,
6937                     yesno(intel_dp->dfp.rgb_to_ycbcr),
6938                     yesno(connector->base.ycbcr_420_allowed),
6939                     yesno(intel_dp->dfp.ycbcr_444_to_420));
6940 }
6941
6942 static void
6943 intel_dp_set_edid(struct intel_dp *intel_dp)
6944 {
6945         struct intel_connector *connector = intel_dp->attached_connector;
6946         struct edid *edid;
6947
6948         intel_dp_unset_edid(intel_dp);
6949         edid = intel_dp_get_edid(intel_dp);
6950         connector->detect_edid = edid;
6951
6952         intel_dp_update_dfp(intel_dp, edid);
6953         intel_dp_update_420(intel_dp);
6954
6955         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
6956                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
6957                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6958         }
6959
6960         drm_dp_cec_set_edid(&intel_dp->aux, edid);
6961         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6962 }
6963
6964 static void
6965 intel_dp_unset_edid(struct intel_dp *intel_dp)
6966 {
6967         struct intel_connector *connector = intel_dp->attached_connector;
6968
6969         drm_dp_cec_unset_edid(&intel_dp->aux);
6970         kfree(connector->detect_edid);
6971         connector->detect_edid = NULL;
6972
6973         intel_dp->has_hdmi_sink = false;
6974         intel_dp->has_audio = false;
6975         intel_dp->edid_quirks = 0;
6976
6977         intel_dp->dfp.max_bpc = 0;
6978         intel_dp->dfp.max_dotclock = 0;
6979         intel_dp->dfp.min_tmds_clock = 0;
6980         intel_dp->dfp.max_tmds_clock = 0;
6981
6982         intel_dp->dfp.pcon_max_frl_bw = 0;
6983
6984         intel_dp->dfp.ycbcr_444_to_420 = false;
6985         connector->base.ycbcr_420_allowed = false;
6986 }
6987
6988 static int
6989 intel_dp_detect(struct drm_connector *connector,
6990                 struct drm_modeset_acquire_ctx *ctx,
6991                 bool force)
6992 {
6993         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6994         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6995         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6996         struct intel_encoder *encoder = &dig_port->base;
6997         enum drm_connector_status status;
6998
6999         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
7000                     connector->base.id, connector->name);
7001         drm_WARN_ON(&dev_priv->drm,
7002                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
7003
7004         if (!INTEL_DISPLAY_ENABLED(dev_priv))
7005                 return connector_status_disconnected;
7006
7007         /* Can't disconnect eDP */
7008         if (intel_dp_is_edp(intel_dp))
7009                 status = edp_detect(intel_dp);
7010         else if (intel_digital_port_connected(encoder))
7011                 status = intel_dp_detect_dpcd(intel_dp);
7012         else
7013                 status = connector_status_disconnected;
7014
7015         if (status == connector_status_disconnected) {
7016                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
7017                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
7018
7019                 if (intel_dp->is_mst) {
7020                         drm_dbg_kms(&dev_priv->drm,
7021                                     "MST device may have disappeared %d vs %d\n",
7022                                     intel_dp->is_mst,
7023                                     intel_dp->mst_mgr.mst_state);
7024                         intel_dp->is_mst = false;
7025                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7026                                                         intel_dp->is_mst);
7027                 }
7028
7029                 goto out;
7030         }
7031
7032         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
7033         if (INTEL_GEN(dev_priv) >= 11)
7034                 intel_dp_get_dsc_sink_cap(intel_dp);
7035
7036         intel_dp_configure_mst(intel_dp);
7037
7038         /*
7039          * TODO: Reset link params when switching to MST mode, until MST
7040          * supports link training fallback params.
7041          */
7042         if (intel_dp->reset_link_params || intel_dp->is_mst) {
7043                 /* Initial max link lane count */
7044                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
7045
7046                 /* Initial max link rate */
7047                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
7048
7049                 intel_dp->reset_link_params = false;
7050         }
7051
7052         intel_dp_print_rates(intel_dp);
7053
7054         if (intel_dp->is_mst) {
7055                 /*
7056                  * If we are in MST mode then this connector
7057                  * won't appear connected or have anything
7058                  * with EDID on it
7059                  */
7060                 status = connector_status_disconnected;
7061                 goto out;
7062         }
7063
7064         /*
7065          * Some external monitors do not signal loss of link synchronization
7066          * with an IRQ_HPD, so force a link status check.
7067          */
7068         if (!intel_dp_is_edp(intel_dp)) {
7069                 int ret;
7070
7071                 ret = intel_dp_retrain_link(encoder, ctx);
7072                 if (ret)
7073                         return ret;
7074         }
7075
7076         /*
7077          * Clearing NACK and defer counts to get their exact values
7078          * while reading EDID which are required by Compliance tests
7079          * 4.2.2.4 and 4.2.2.5
7080          */
7081         intel_dp->aux.i2c_nack_count = 0;
7082         intel_dp->aux.i2c_defer_count = 0;
7083
7084         intel_dp_set_edid(intel_dp);
7085         if (intel_dp_is_edp(intel_dp) ||
7086             to_intel_connector(connector)->detect_edid)
7087                 status = connector_status_connected;
7088
7089         intel_dp_check_device_service_irq(intel_dp);
7090
7091 out:
7092         if (status != connector_status_connected && !intel_dp->is_mst)
7093                 intel_dp_unset_edid(intel_dp);
7094
7095         /*
7096          * Make sure the refs for power wells enabled during detect are
7097          * dropped to avoid a new detect cycle triggered by HPD polling.
7098          */
7099         intel_display_power_flush_work(dev_priv);
7100
7101         if (!intel_dp_is_edp(intel_dp))
7102                 drm_dp_set_subconnector_property(connector,
7103                                                  status,
7104                                                  intel_dp->dpcd,
7105                                                  intel_dp->downstream_ports);
7106         return status;
7107 }
7108
7109 static void
7110 intel_dp_force(struct drm_connector *connector)
7111 {
7112         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
7113         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7114         struct intel_encoder *intel_encoder = &dig_port->base;
7115         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
7116         enum intel_display_power_domain aux_domain =
7117                 intel_aux_power_domain(dig_port);
7118         intel_wakeref_t wakeref;
7119
7120         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
7121                     connector->base.id, connector->name);
7122         intel_dp_unset_edid(intel_dp);
7123
7124         if (connector->status != connector_status_connected)
7125                 return;
7126
7127         wakeref = intel_display_power_get(dev_priv, aux_domain);
7128
7129         intel_dp_set_edid(intel_dp);
7130
7131         intel_display_power_put(dev_priv, aux_domain, wakeref);
7132 }
7133
7134 static int intel_dp_get_modes(struct drm_connector *connector)
7135 {
7136         struct intel_connector *intel_connector = to_intel_connector(connector);
7137         struct edid *edid;
7138
7139         edid = intel_connector->detect_edid;
7140         if (edid) {
7141                 int ret = intel_connector_update_modes(connector, edid);
7142                 if (ret)
7143                         return ret;
7144         }
7145
7146         /* if eDP has no EDID, fall back to fixed mode */
7147         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
7148             intel_connector->panel.fixed_mode) {
7149                 struct drm_display_mode *mode;
7150
7151                 mode = drm_mode_duplicate(connector->dev,
7152                                           intel_connector->panel.fixed_mode);
7153                 if (mode) {
7154                         drm_mode_probed_add(connector, mode);
7155                         return 1;
7156                 }
7157         }
7158
7159         if (!edid) {
7160                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
7161                 struct drm_display_mode *mode;
7162
7163                 mode = drm_dp_downstream_mode(connector->dev,
7164                                               intel_dp->dpcd,
7165                                               intel_dp->downstream_ports);
7166                 if (mode) {
7167                         drm_mode_probed_add(connector, mode);
7168                         return 1;
7169                 }
7170         }
7171
7172         return 0;
7173 }
7174
7175 static int
7176 intel_dp_connector_register(struct drm_connector *connector)
7177 {
7178         struct drm_i915_private *i915 = to_i915(connector->dev);
7179         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
7180         int ret;
7181
7182         ret = intel_connector_register(connector);
7183         if (ret)
7184                 return ret;
7185
7186         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
7187                     intel_dp->aux.name, connector->kdev->kobj.name);
7188
7189         intel_dp->aux.dev = connector->kdev;
7190         ret = drm_dp_aux_register(&intel_dp->aux);
7191         if (!ret)
7192                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
7193         return ret;
7194 }
7195
7196 static void
7197 intel_dp_connector_unregister(struct drm_connector *connector)
7198 {
7199         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
7200
7201         drm_dp_cec_unregister_connector(&intel_dp->aux);
7202         drm_dp_aux_unregister(&intel_dp->aux);
7203         intel_connector_unregister(connector);
7204 }
7205
7206 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
7207 {
7208         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
7209         struct intel_dp *intel_dp = &dig_port->dp;
7210
7211         intel_dp_mst_encoder_cleanup(dig_port);
7212         if (intel_dp_is_edp(intel_dp)) {
7213                 intel_wakeref_t wakeref;
7214
7215                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7216                 /*
7217                  * vdd might still be enabled do to the delayed vdd off.
7218                  * Make sure vdd is actually turned off here.
7219                  */
7220                 with_pps_lock(intel_dp, wakeref)
7221                         edp_panel_vdd_off_sync(intel_dp);
7222         }
7223
7224         intel_dp_aux_fini(intel_dp);
7225 }
7226
7227 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
7228 {
7229         intel_dp_encoder_flush_work(encoder);
7230
7231         drm_encoder_cleanup(encoder);
7232         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
7233 }
7234
7235 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
7236 {
7237         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
7238         intel_wakeref_t wakeref;
7239
7240         if (!intel_dp_is_edp(intel_dp))
7241                 return;
7242
7243         /*
7244          * vdd might still be enabled do to the delayed vdd off.
7245          * Make sure vdd is actually turned off here.
7246          */
7247         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7248         with_pps_lock(intel_dp, wakeref)
7249                 edp_panel_vdd_off_sync(intel_dp);
7250 }
7251
7252 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
7253 {
7254         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
7255         intel_wakeref_t wakeref;
7256
7257         if (!intel_dp_is_edp(intel_dp))
7258                 return;
7259
7260         with_pps_lock(intel_dp, wakeref)
7261                 wait_panel_power_cycle(intel_dp);
7262 }
7263
7264 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
7265 {
7266         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7267         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7268
7269         lockdep_assert_held(&dev_priv->pps_mutex);
7270
7271         if (!edp_have_panel_vdd(intel_dp))
7272                 return;
7273
7274         /*
7275          * The VDD bit needs a power domain reference, so if the bit is
7276          * already enabled when we boot or resume, grab this reference and
7277          * schedule a vdd off, so we don't hold on to the reference
7278          * indefinitely.
7279          */
7280         drm_dbg_kms(&dev_priv->drm,
7281                     "VDD left on by BIOS, adjusting state tracking\n");
7282         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
7283
7284         edp_panel_vdd_schedule_off(intel_dp);
7285 }
7286
7287 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7288 {
7289         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7290         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7291         enum pipe pipe;
7292
7293         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7294                                   encoder->port, &pipe))
7295                 return pipe;
7296
7297         return INVALID_PIPE;
7298 }
7299
7300 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7301 {
7302         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7303         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7304         intel_wakeref_t wakeref;
7305
7306         if (!HAS_DDI(dev_priv))
7307                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7308
7309         intel_dp->reset_link_params = true;
7310
7311         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7312             !intel_dp_is_edp(intel_dp))
7313                 return;
7314
7315         with_pps_lock(intel_dp, wakeref) {
7316                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7317                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7318
7319                 if (intel_dp_is_edp(intel_dp)) {
7320                         /*
7321                          * Reinit the power sequencer, in case BIOS did
7322                          * something nasty with it.
7323                          */
7324                         intel_dp_pps_init(intel_dp);
7325                         intel_edp_panel_vdd_sanitize(intel_dp);
7326                 }
7327         }
7328 }
7329
7330 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7331                                     int tile_group_id)
7332 {
7333         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7334         struct drm_connector_list_iter conn_iter;
7335         struct drm_connector *connector;
7336         int ret = 0;
7337
7338         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7339         drm_for_each_connector_iter(connector, &conn_iter) {
7340                 struct drm_connector_state *conn_state;
7341                 struct intel_crtc_state *crtc_state;
7342                 struct intel_crtc *crtc;
7343
7344                 if (!connector->has_tile ||
7345                     connector->tile_group->id != tile_group_id)
7346                         continue;
7347
7348                 conn_state = drm_atomic_get_connector_state(&state->base,
7349                                                             connector);
7350                 if (IS_ERR(conn_state)) {
7351                         ret = PTR_ERR(conn_state);
7352                         break;
7353                 }
7354
7355                 crtc = to_intel_crtc(conn_state->crtc);
7356
7357                 if (!crtc)
7358                         continue;
7359
7360                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7361                 crtc_state->uapi.mode_changed = true;
7362
7363                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7364                 if (ret)
7365                         break;
7366         }
7367         drm_connector_list_iter_end(&conn_iter);
7368
7369         return ret;
7370 }
7371
7372 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7373 {
7374         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7375         struct intel_crtc *crtc;
7376
7377         if (transcoders == 0)
7378                 return 0;
7379
7380         for_each_intel_crtc(&dev_priv->drm, crtc) {
7381                 struct intel_crtc_state *crtc_state;
7382                 int ret;
7383
7384                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7385                 if (IS_ERR(crtc_state))
7386                         return PTR_ERR(crtc_state);
7387
7388                 if (!crtc_state->hw.enable)
7389                         continue;
7390
7391                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7392                         continue;
7393
7394                 crtc_state->uapi.mode_changed = true;
7395
7396                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7397                 if (ret)
7398                         return ret;
7399
7400                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7401                 if (ret)
7402                         return ret;
7403
7404                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7405         }
7406
7407         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7408
7409         return 0;
7410 }
7411
7412 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7413                                       struct drm_connector *connector)
7414 {
7415         const struct drm_connector_state *old_conn_state =
7416                 drm_atomic_get_old_connector_state(&state->base, connector);
7417         const struct intel_crtc_state *old_crtc_state;
7418         struct intel_crtc *crtc;
7419         u8 transcoders;
7420
7421         crtc = to_intel_crtc(old_conn_state->crtc);
7422         if (!crtc)
7423                 return 0;
7424
7425         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7426
7427         if (!old_crtc_state->hw.active)
7428                 return 0;
7429
7430         transcoders = old_crtc_state->sync_mode_slaves_mask;
7431         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7432                 transcoders |= BIT(old_crtc_state->master_transcoder);
7433
7434         return intel_modeset_affected_transcoders(state,
7435                                                   transcoders);
7436 }
7437
7438 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7439                                            struct drm_atomic_state *_state)
7440 {
7441         struct drm_i915_private *dev_priv = to_i915(conn->dev);
7442         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7443         int ret;
7444
7445         ret = intel_digital_connector_atomic_check(conn, &state->base);
7446         if (ret)
7447                 return ret;
7448
7449         /*
7450          * We don't enable port sync on BDW due to missing w/as and
7451          * due to not having adjusted the modeset sequence appropriately.
7452          */
7453         if (INTEL_GEN(dev_priv) < 9)
7454                 return 0;
7455
7456         if (!intel_connector_needs_modeset(state, conn))
7457                 return 0;
7458
7459         if (conn->has_tile) {
7460                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7461                 if (ret)
7462                         return ret;
7463         }
7464
7465         return intel_modeset_synced_crtcs(state, conn);
7466 }
7467
7468 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7469         .force = intel_dp_force,
7470         .fill_modes = drm_helper_probe_single_connector_modes,
7471         .atomic_get_property = intel_digital_connector_atomic_get_property,
7472         .atomic_set_property = intel_digital_connector_atomic_set_property,
7473         .late_register = intel_dp_connector_register,
7474         .early_unregister = intel_dp_connector_unregister,
7475         .destroy = intel_connector_destroy,
7476         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7477         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7478 };
7479
7480 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7481         .detect_ctx = intel_dp_detect,
7482         .get_modes = intel_dp_get_modes,
7483         .mode_valid = intel_dp_mode_valid,
7484         .atomic_check = intel_dp_connector_atomic_check,
7485 };
7486
7487 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7488         .reset = intel_dp_encoder_reset,
7489         .destroy = intel_dp_encoder_destroy,
7490 };
7491
7492 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7493 {
7494         intel_wakeref_t wakeref;
7495         bool have_power = false;
7496
7497         with_pps_lock(intel_dp, wakeref) {
7498                 have_power = edp_have_panel_power(intel_dp) &&
7499                                                   edp_have_panel_vdd(intel_dp);
7500         }
7501
7502         return have_power;
7503 }
7504
7505 enum irqreturn
7506 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
7507 {
7508         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
7509         struct intel_dp *intel_dp = &dig_port->dp;
7510
7511         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
7512             (long_hpd || !intel_edp_have_power(intel_dp))) {
7513                 /*
7514                  * vdd off can generate a long/short pulse on eDP which
7515                  * would require vdd on to handle it, and thus we
7516                  * would end up in an endless cycle of
7517                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7518                  */
7519                 drm_dbg_kms(&i915->drm,
7520                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7521                             long_hpd ? "long" : "short",
7522                             dig_port->base.base.base.id,
7523                             dig_port->base.base.name);
7524                 return IRQ_HANDLED;
7525         }
7526
7527         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7528                     dig_port->base.base.base.id,
7529                     dig_port->base.base.name,
7530                     long_hpd ? "long" : "short");
7531
7532         if (long_hpd) {
7533                 intel_dp->reset_link_params = true;
7534                 return IRQ_NONE;
7535         }
7536
7537         if (intel_dp->is_mst) {
7538                 if (!intel_dp_check_mst_status(intel_dp))
7539                         return IRQ_NONE;
7540         } else if (!intel_dp_short_pulse(intel_dp)) {
7541                 return IRQ_NONE;
7542         }
7543
7544         return IRQ_HANDLED;
7545 }
7546
7547 /* check the VBT to see whether the eDP is on another port */
7548 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7549 {
7550         /*
7551          * eDP not supported on g4x. so bail out early just
7552          * for a bit extra safety in case the VBT is bonkers.
7553          */
7554         if (INTEL_GEN(dev_priv) < 5)
7555                 return false;
7556
7557         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7558                 return true;
7559
7560         return intel_bios_is_port_edp(dev_priv, port);
7561 }
7562
7563 static void
7564 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7565 {
7566         struct drm_i915_private *dev_priv = to_i915(connector->dev);
7567         enum port port = dp_to_dig_port(intel_dp)->base.port;
7568
7569         if (!intel_dp_is_edp(intel_dp))
7570                 drm_connector_attach_dp_subconnector_property(connector);
7571
7572         if (!IS_G4X(dev_priv) && port != PORT_A)
7573                 intel_attach_force_audio_property(connector);
7574
7575         intel_attach_broadcast_rgb_property(connector);
7576         if (HAS_GMCH(dev_priv))
7577                 drm_connector_attach_max_bpc_property(connector, 6, 10);
7578         else if (INTEL_GEN(dev_priv) >= 5)
7579                 drm_connector_attach_max_bpc_property(connector, 6, 12);
7580
7581         intel_attach_colorspace_property(connector);
7582
7583         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7584                 drm_object_attach_property(&connector->base,
7585                                            connector->dev->mode_config.hdr_output_metadata_property,
7586                                            0);
7587
7588         if (intel_dp_is_edp(intel_dp)) {
7589                 u32 allowed_scalers;
7590
7591                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7592                 if (!HAS_GMCH(dev_priv))
7593                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7594
7595                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7596
7597                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7598
7599         }
7600 }
7601
7602 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7603 {
7604         intel_dp->panel_power_off_time = ktime_get_boottime();
7605         intel_dp->last_power_on = jiffies;
7606         intel_dp->last_backlight_off = jiffies;
7607 }
7608
7609 static void
7610 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7611 {
7612         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7613         u32 pp_on, pp_off, pp_ctl;
7614         struct pps_registers regs;
7615
7616         intel_pps_get_registers(intel_dp, &regs);
7617
7618         pp_ctl = ilk_get_pp_control(intel_dp);
7619
7620         /* Ensure PPS is unlocked */
7621         if (!HAS_DDI(dev_priv))
7622                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7623
7624         pp_on = intel_de_read(dev_priv, regs.pp_on);
7625         pp_off = intel_de_read(dev_priv, regs.pp_off);
7626
7627         /* Pull timing values out of registers */
7628         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7629         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7630         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7631         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7632
7633         if (i915_mmio_reg_valid(regs.pp_div)) {
7634                 u32 pp_div;
7635
7636                 pp_div = intel_de_read(dev_priv, regs.pp_div);
7637
7638                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7639         } else {
7640                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7641         }
7642 }
7643
7644 static void
7645 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7646 {
7647         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7648                       state_name,
7649                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7650 }
7651
7652 static void
7653 intel_pps_verify_state(struct intel_dp *intel_dp)
7654 {
7655         struct edp_power_seq hw;
7656         struct edp_power_seq *sw = &intel_dp->pps_delays;
7657
7658         intel_pps_readout_hw_state(intel_dp, &hw);
7659
7660         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7661             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7662                 DRM_ERROR("PPS state mismatch\n");
7663                 intel_pps_dump_state("sw", sw);
7664                 intel_pps_dump_state("hw", &hw);
7665         }
7666 }
7667
7668 static void
7669 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7670 {
7671         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7672         struct edp_power_seq cur, vbt, spec,
7673                 *final = &intel_dp->pps_delays;
7674
7675         lockdep_assert_held(&dev_priv->pps_mutex);
7676
7677         /* already initialized? */
7678         if (final->t11_t12 != 0)
7679                 return;
7680
7681         intel_pps_readout_hw_state(intel_dp, &cur);
7682
7683         intel_pps_dump_state("cur", &cur);
7684
7685         vbt = dev_priv->vbt.edp.pps;
7686         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7687          * of 500ms appears to be too short. Ocassionally the panel
7688          * just fails to power back on. Increasing the delay to 800ms
7689          * seems sufficient to avoid this problem.
7690          */
7691         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7692                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7693                 drm_dbg_kms(&dev_priv->drm,
7694                             "Increasing T12 panel delay as per the quirk to %d\n",
7695                             vbt.t11_t12);
7696         }
7697         /* T11_T12 delay is special and actually in units of 100ms, but zero
7698          * based in the hw (so we need to add 100 ms). But the sw vbt
7699          * table multiplies it with 1000 to make it in units of 100usec,
7700          * too. */
7701         vbt.t11_t12 += 100 * 10;
7702
7703         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7704          * our hw here, which are all in 100usec. */
7705         spec.t1_t3 = 210 * 10;
7706         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7707         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7708         spec.t10 = 500 * 10;
7709         /* This one is special and actually in units of 100ms, but zero
7710          * based in the hw (so we need to add 100 ms). But the sw vbt
7711          * table multiplies it with 1000 to make it in units of 100usec,
7712          * too. */
7713         spec.t11_t12 = (510 + 100) * 10;
7714
7715         intel_pps_dump_state("vbt", &vbt);
7716
7717         /* Use the max of the register settings and vbt. If both are
7718          * unset, fall back to the spec limits. */
7719 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
7720                                        spec.field : \
7721                                        max(cur.field, vbt.field))
7722         assign_final(t1_t3);
7723         assign_final(t8);
7724         assign_final(t9);
7725         assign_final(t10);
7726         assign_final(t11_t12);
7727 #undef assign_final
7728
7729 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
7730         intel_dp->panel_power_up_delay = get_delay(t1_t3);
7731         intel_dp->backlight_on_delay = get_delay(t8);
7732         intel_dp->backlight_off_delay = get_delay(t9);
7733         intel_dp->panel_power_down_delay = get_delay(t10);
7734         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7735 #undef get_delay
7736
7737         drm_dbg_kms(&dev_priv->drm,
7738                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7739                     intel_dp->panel_power_up_delay,
7740                     intel_dp->panel_power_down_delay,
7741                     intel_dp->panel_power_cycle_delay);
7742
7743         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7744                     intel_dp->backlight_on_delay,
7745                     intel_dp->backlight_off_delay);
7746
7747         /*
7748          * We override the HW backlight delays to 1 because we do manual waits
7749          * on them. For T8, even BSpec recommends doing it. For T9, if we
7750          * don't do this, we'll end up waiting for the backlight off delay
7751          * twice: once when we do the manual sleep, and once when we disable
7752          * the panel and wait for the PP_STATUS bit to become zero.
7753          */
7754         final->t8 = 1;
7755         final->t9 = 1;
7756
7757         /*
7758          * HW has only a 100msec granularity for t11_t12 so round it up
7759          * accordingly.
7760          */
7761         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7762 }
7763
7764 static void
7765 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7766                                               bool force_disable_vdd)
7767 {
7768         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7769         u32 pp_on, pp_off, port_sel = 0;
7770         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7771         struct pps_registers regs;
7772         enum port port = dp_to_dig_port(intel_dp)->base.port;
7773         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7774
7775         lockdep_assert_held(&dev_priv->pps_mutex);
7776
7777         intel_pps_get_registers(intel_dp, &regs);
7778
7779         /*
7780          * On some VLV machines the BIOS can leave the VDD
7781          * enabled even on power sequencers which aren't
7782          * hooked up to any port. This would mess up the
7783          * power domain tracking the first time we pick
7784          * one of these power sequencers for use since
7785          * edp_panel_vdd_on() would notice that the VDD was
7786          * already on and therefore wouldn't grab the power
7787          * domain reference. Disable VDD first to avoid this.
7788          * This also avoids spuriously turning the VDD on as
7789          * soon as the new power sequencer gets initialized.
7790          */
7791         if (force_disable_vdd) {
7792                 u32 pp = ilk_get_pp_control(intel_dp);
7793
7794                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7795                          "Panel power already on\n");
7796
7797                 if (pp & EDP_FORCE_VDD)
7798                         drm_dbg_kms(&dev_priv->drm,
7799                                     "VDD already on, disabling first\n");
7800
7801                 pp &= ~EDP_FORCE_VDD;
7802
7803                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7804         }
7805
7806         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7807                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7808         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7809                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7810
7811         /* Haswell doesn't have any port selection bits for the panel
7812          * power sequencer any more. */
7813         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7814                 port_sel = PANEL_PORT_SELECT_VLV(port);
7815         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7816                 switch (port) {
7817                 case PORT_A:
7818                         port_sel = PANEL_PORT_SELECT_DPA;
7819                         break;
7820                 case PORT_C:
7821                         port_sel = PANEL_PORT_SELECT_DPC;
7822                         break;
7823                 case PORT_D:
7824                         port_sel = PANEL_PORT_SELECT_DPD;
7825                         break;
7826                 default:
7827                         MISSING_CASE(port);
7828                         break;
7829                 }
7830         }
7831
7832         pp_on |= port_sel;
7833
7834         intel_de_write(dev_priv, regs.pp_on, pp_on);
7835         intel_de_write(dev_priv, regs.pp_off, pp_off);
7836
7837         /*
7838          * Compute the divisor for the pp clock, simply match the Bspec formula.
7839          */
7840         if (i915_mmio_reg_valid(regs.pp_div)) {
7841                 intel_de_write(dev_priv, regs.pp_div,
7842                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7843         } else {
7844                 u32 pp_ctl;
7845
7846                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7847                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7848                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7849                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7850         }
7851
7852         drm_dbg_kms(&dev_priv->drm,
7853                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7854                     intel_de_read(dev_priv, regs.pp_on),
7855                     intel_de_read(dev_priv, regs.pp_off),
7856                     i915_mmio_reg_valid(regs.pp_div) ?
7857                     intel_de_read(dev_priv, regs.pp_div) :
7858                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7859 }
7860
7861 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7862 {
7863         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7864
7865         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7866                 vlv_initial_power_sequencer_setup(intel_dp);
7867         } else {
7868                 intel_dp_init_panel_power_sequencer(intel_dp);
7869                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7870         }
7871 }
7872
7873 /**
7874  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7875  * @dev_priv: i915 device
7876  * @crtc_state: a pointer to the active intel_crtc_state
7877  * @refresh_rate: RR to be programmed
7878  *
7879  * This function gets called when refresh rate (RR) has to be changed from
7880  * one frequency to another. Switches can be between high and low RR
7881  * supported by the panel or to any other RR based on media playback (in
7882  * this case, RR value needs to be passed from user space).
7883  *
7884  * The caller of this function needs to take a lock on dev_priv->drrs.
7885  */
7886 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7887                                     const struct intel_crtc_state *crtc_state,
7888                                     int refresh_rate)
7889 {
7890         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7892         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7893
7894         if (refresh_rate <= 0) {
7895                 drm_dbg_kms(&dev_priv->drm,
7896                             "Refresh rate should be positive non-zero.\n");
7897                 return;
7898         }
7899
7900         if (intel_dp == NULL) {
7901                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7902                 return;
7903         }
7904
7905         if (!intel_crtc) {
7906                 drm_dbg_kms(&dev_priv->drm,
7907                             "DRRS: intel_crtc not initialized\n");
7908                 return;
7909         }
7910
7911         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7912                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7913                 return;
7914         }
7915
7916         if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
7917                         refresh_rate)
7918                 index = DRRS_LOW_RR;
7919
7920         if (index == dev_priv->drrs.refresh_rate_type) {
7921                 drm_dbg_kms(&dev_priv->drm,
7922                             "DRRS requested for previously set RR...ignoring\n");
7923                 return;
7924         }
7925
7926         if (!crtc_state->hw.active) {
7927                 drm_dbg_kms(&dev_priv->drm,
7928                             "eDP encoder disabled. CRTC not Active\n");
7929                 return;
7930         }
7931
7932         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7933                 switch (index) {
7934                 case DRRS_HIGH_RR:
7935                         intel_dp_set_m_n(crtc_state, M1_N1);
7936                         break;
7937                 case DRRS_LOW_RR:
7938                         intel_dp_set_m_n(crtc_state, M2_N2);
7939                         break;
7940                 case DRRS_MAX_RR:
7941                 default:
7942                         drm_err(&dev_priv->drm,
7943                                 "Unsupported refreshrate type\n");
7944                 }
7945         } else if (INTEL_GEN(dev_priv) > 6) {
7946                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7947                 u32 val;
7948
7949                 val = intel_de_read(dev_priv, reg);
7950                 if (index > DRRS_HIGH_RR) {
7951                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7952                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7953                         else
7954                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7955                 } else {
7956                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7957                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7958                         else
7959                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7960                 }
7961                 intel_de_write(dev_priv, reg, val);
7962         }
7963
7964         dev_priv->drrs.refresh_rate_type = index;
7965
7966         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7967                     refresh_rate);
7968 }
7969
7970 static void
7971 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
7972 {
7973         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7974
7975         dev_priv->drrs.busy_frontbuffer_bits = 0;
7976         dev_priv->drrs.dp = intel_dp;
7977 }
7978
7979 /**
7980  * intel_edp_drrs_enable - init drrs struct if supported
7981  * @intel_dp: DP struct
7982  * @crtc_state: A pointer to the active crtc state.
7983  *
7984  * Initializes frontbuffer_bits and drrs.dp
7985  */
7986 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7987                            const struct intel_crtc_state *crtc_state)
7988 {
7989         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7990
7991         if (!crtc_state->has_drrs)
7992                 return;
7993
7994         drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
7995
7996         mutex_lock(&dev_priv->drrs.mutex);
7997
7998         if (dev_priv->drrs.dp) {
7999                 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
8000                 goto unlock;
8001         }
8002
8003         intel_edp_drrs_enable_locked(intel_dp);
8004
8005 unlock:
8006         mutex_unlock(&dev_priv->drrs.mutex);
8007 }
8008
8009 static void
8010 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
8011                               const struct intel_crtc_state *crtc_state)
8012 {
8013         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8014
8015         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
8016                 int refresh;
8017
8018                 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
8019                 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
8020         }
8021
8022         dev_priv->drrs.dp = NULL;
8023 }
8024
8025 /**
8026  * intel_edp_drrs_disable - Disable DRRS
8027  * @intel_dp: DP struct
8028  * @old_crtc_state: Pointer to old crtc_state.
8029  *
8030  */
8031 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
8032                             const struct intel_crtc_state *old_crtc_state)
8033 {
8034         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8035
8036         if (!old_crtc_state->has_drrs)
8037                 return;
8038
8039         mutex_lock(&dev_priv->drrs.mutex);
8040         if (!dev_priv->drrs.dp) {
8041                 mutex_unlock(&dev_priv->drrs.mutex);
8042                 return;
8043         }
8044
8045         intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
8046         mutex_unlock(&dev_priv->drrs.mutex);
8047
8048         cancel_delayed_work_sync(&dev_priv->drrs.work);
8049 }
8050
8051 /**
8052  * intel_edp_drrs_update - Update DRRS state
8053  * @intel_dp: Intel DP
8054  * @crtc_state: new CRTC state
8055  *
8056  * This function will update DRRS states, disabling or enabling DRRS when
8057  * executing fastsets. For full modeset, intel_edp_drrs_disable() and
8058  * intel_edp_drrs_enable() should be called instead.
8059  */
8060 void
8061 intel_edp_drrs_update(struct intel_dp *intel_dp,
8062                       const struct intel_crtc_state *crtc_state)
8063 {
8064         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8065
8066         if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
8067                 return;
8068
8069         mutex_lock(&dev_priv->drrs.mutex);
8070
8071         /* New state matches current one? */
8072         if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
8073                 goto unlock;
8074
8075         if (crtc_state->has_drrs)
8076                 intel_edp_drrs_enable_locked(intel_dp);
8077         else
8078                 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
8079
8080 unlock:
8081         mutex_unlock(&dev_priv->drrs.mutex);
8082 }
8083
8084 static void intel_edp_drrs_downclock_work(struct work_struct *work)
8085 {
8086         struct drm_i915_private *dev_priv =
8087                 container_of(work, typeof(*dev_priv), drrs.work.work);
8088         struct intel_dp *intel_dp;
8089
8090         mutex_lock(&dev_priv->drrs.mutex);
8091
8092         intel_dp = dev_priv->drrs.dp;
8093
8094         if (!intel_dp)
8095                 goto unlock;
8096
8097         /*
8098          * The delayed work can race with an invalidate hence we need to
8099          * recheck.
8100          */
8101
8102         if (dev_priv->drrs.busy_frontbuffer_bits)
8103                 goto unlock;
8104
8105         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
8106                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
8107
8108                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8109                         drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
8110         }
8111
8112 unlock:
8113         mutex_unlock(&dev_priv->drrs.mutex);
8114 }
8115
8116 /**
8117  * intel_edp_drrs_invalidate - Disable Idleness DRRS
8118  * @dev_priv: i915 device
8119  * @frontbuffer_bits: frontbuffer plane tracking bits
8120  *
8121  * This function gets called everytime rendering on the given planes start.
8122  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
8123  *
8124  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
8125  */
8126 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
8127                                unsigned int frontbuffer_bits)
8128 {
8129         struct intel_dp *intel_dp;
8130         struct drm_crtc *crtc;
8131         enum pipe pipe;
8132
8133         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
8134                 return;
8135
8136         cancel_delayed_work(&dev_priv->drrs.work);
8137
8138         mutex_lock(&dev_priv->drrs.mutex);
8139
8140         intel_dp = dev_priv->drrs.dp;
8141         if (!intel_dp) {
8142                 mutex_unlock(&dev_priv->drrs.mutex);
8143                 return;
8144         }
8145
8146         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
8147         pipe = to_intel_crtc(crtc)->pipe;
8148
8149         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8150         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
8151
8152         /* invalidate means busy screen hence upclock */
8153         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8154                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8155                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
8156
8157         mutex_unlock(&dev_priv->drrs.mutex);
8158 }
8159
8160 /**
8161  * intel_edp_drrs_flush - Restart Idleness DRRS
8162  * @dev_priv: i915 device
8163  * @frontbuffer_bits: frontbuffer plane tracking bits
8164  *
8165  * This function gets called every time rendering on the given planes has
8166  * completed or flip on a crtc is completed. So DRRS should be upclocked
8167  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
8168  * if no other planes are dirty.
8169  *
8170  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
8171  */
8172 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
8173                           unsigned int frontbuffer_bits)
8174 {
8175         struct intel_dp *intel_dp;
8176         struct drm_crtc *crtc;
8177         enum pipe pipe;
8178
8179         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
8180                 return;
8181
8182         cancel_delayed_work(&dev_priv->drrs.work);
8183
8184         mutex_lock(&dev_priv->drrs.mutex);
8185
8186         intel_dp = dev_priv->drrs.dp;
8187         if (!intel_dp) {
8188                 mutex_unlock(&dev_priv->drrs.mutex);
8189                 return;
8190         }
8191
8192         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
8193         pipe = to_intel_crtc(crtc)->pipe;
8194
8195         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8196         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
8197
8198         /* flush means busy screen hence upclock */
8199         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8200                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8201                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
8202
8203         /*
8204          * flush also means no more activity hence schedule downclock, if all
8205          * other fbs are quiescent too
8206          */
8207         if (!dev_priv->drrs.busy_frontbuffer_bits)
8208                 schedule_delayed_work(&dev_priv->drrs.work,
8209                                 msecs_to_jiffies(1000));
8210         mutex_unlock(&dev_priv->drrs.mutex);
8211 }
8212
8213 /**
8214  * DOC: Display Refresh Rate Switching (DRRS)
8215  *
8216  * Display Refresh Rate Switching (DRRS) is a power conservation feature
8217  * which enables swtching between low and high refresh rates,
8218  * dynamically, based on the usage scenario. This feature is applicable
8219  * for internal panels.
8220  *
8221  * Indication that the panel supports DRRS is given by the panel EDID, which
8222  * would list multiple refresh rates for one resolution.
8223  *
8224  * DRRS is of 2 types - static and seamless.
8225  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
8226  * (may appear as a blink on screen) and is used in dock-undock scenario.
8227  * Seamless DRRS involves changing RR without any visual effect to the user
8228  * and can be used during normal system usage. This is done by programming
8229  * certain registers.
8230  *
8231  * Support for static/seamless DRRS may be indicated in the VBT based on
8232  * inputs from the panel spec.
8233  *
8234  * DRRS saves power by switching to low RR based on usage scenarios.
8235  *
8236  * The implementation is based on frontbuffer tracking implementation.  When
8237  * there is a disturbance on the screen triggered by user activity or a periodic
8238  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
8239  * no movement on screen, after a timeout of 1 second, a switch to low RR is
8240  * made.
8241  *
8242  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
8243  * and intel_edp_drrs_flush() are called.
8244  *
8245  * DRRS can be further extended to support other internal panels and also
8246  * the scenario of video playback wherein RR is set based on the rate
8247  * requested by userspace.
8248  */
8249
8250 /**
8251  * intel_dp_drrs_init - Init basic DRRS work and mutex.
8252  * @connector: eDP connector
8253  * @fixed_mode: preferred mode of panel
8254  *
8255  * This function is  called only once at driver load to initialize basic
8256  * DRRS stuff.
8257  *
8258  * Returns:
8259  * Downclock mode if panel supports it, else return NULL.
8260  * DRRS support is determined by the presence of downclock mode (apart
8261  * from VBT setting).
8262  */
8263 static struct drm_display_mode *
8264 intel_dp_drrs_init(struct intel_connector *connector,
8265                    struct drm_display_mode *fixed_mode)
8266 {
8267         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8268         struct drm_display_mode *downclock_mode = NULL;
8269
8270         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
8271         mutex_init(&dev_priv->drrs.mutex);
8272
8273         if (INTEL_GEN(dev_priv) <= 6) {
8274                 drm_dbg_kms(&dev_priv->drm,
8275                             "DRRS supported for Gen7 and above\n");
8276                 return NULL;
8277         }
8278
8279         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
8280                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
8281                 return NULL;
8282         }
8283
8284         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
8285         if (!downclock_mode) {
8286                 drm_dbg_kms(&dev_priv->drm,
8287                             "Downclock mode is not found. DRRS not supported\n");
8288                 return NULL;
8289         }
8290
8291         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
8292
8293         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
8294         drm_dbg_kms(&dev_priv->drm,
8295                     "seamless DRRS supported for eDP panel.\n");
8296         return downclock_mode;
8297 }
8298
8299 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
8300                                      struct intel_connector *intel_connector)
8301 {
8302         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8303         struct drm_device *dev = &dev_priv->drm;
8304         struct drm_connector *connector = &intel_connector->base;
8305         struct drm_display_mode *fixed_mode = NULL;
8306         struct drm_display_mode *downclock_mode = NULL;
8307         bool has_dpcd;
8308         enum pipe pipe = INVALID_PIPE;
8309         intel_wakeref_t wakeref;
8310         struct edid *edid;
8311
8312         if (!intel_dp_is_edp(intel_dp))
8313                 return true;
8314
8315         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8316
8317         /*
8318          * On IBX/CPT we may get here with LVDS already registered. Since the
8319          * driver uses the only internal power sequencer available for both
8320          * eDP and LVDS bail out early in this case to prevent interfering
8321          * with an already powered-on LVDS power sequencer.
8322          */
8323         if (intel_get_lvds_encoder(dev_priv)) {
8324                 drm_WARN_ON(dev,
8325                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8326                 drm_info(&dev_priv->drm,
8327                          "LVDS was detected, not registering eDP\n");
8328
8329                 return false;
8330         }
8331
8332         with_pps_lock(intel_dp, wakeref) {
8333                 intel_dp_init_panel_power_timestamps(intel_dp);
8334                 intel_dp_pps_init(intel_dp);
8335                 intel_edp_panel_vdd_sanitize(intel_dp);
8336         }
8337
8338         /* Cache DPCD and EDID for edp. */
8339         has_dpcd = intel_edp_init_dpcd(intel_dp);
8340
8341         if (!has_dpcd) {
8342                 /* if this fails, presume the device is a ghost */
8343                 drm_info(&dev_priv->drm,
8344                          "failed to retrieve link info, disabling eDP\n");
8345                 goto out_vdd_off;
8346         }
8347
8348         mutex_lock(&dev->mode_config.mutex);
8349         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8350         if (edid) {
8351                 if (drm_add_edid_modes(connector, edid)) {
8352                         drm_connector_update_edid_property(connector, edid);
8353                         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8354                 } else {
8355                         kfree(edid);
8356                         edid = ERR_PTR(-EINVAL);
8357                 }
8358         } else {
8359                 edid = ERR_PTR(-ENOENT);
8360         }
8361         intel_connector->edid = edid;
8362
8363         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8364         if (fixed_mode)
8365                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8366
8367         /* fallback to VBT if available for eDP */
8368         if (!fixed_mode)
8369                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8370         mutex_unlock(&dev->mode_config.mutex);
8371
8372         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8373                 /*
8374                  * Figure out the current pipe for the initial backlight setup.
8375                  * If the current pipe isn't valid, try the PPS pipe, and if that
8376                  * fails just assume pipe A.
8377                  */
8378                 pipe = vlv_active_pipe(intel_dp);
8379
8380                 if (pipe != PIPE_A && pipe != PIPE_B)
8381                         pipe = intel_dp->pps_pipe;
8382
8383                 if (pipe != PIPE_A && pipe != PIPE_B)
8384                         pipe = PIPE_A;
8385
8386                 drm_dbg_kms(&dev_priv->drm,
8387                             "using pipe %c for initial backlight setup\n",
8388                             pipe_name(pipe));
8389         }
8390
8391         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8392         intel_connector->panel.backlight.power = intel_edp_backlight_power;
8393         intel_panel_setup_backlight(connector, pipe);
8394
8395         if (fixed_mode) {
8396                 drm_connector_set_panel_orientation_with_quirk(connector,
8397                                 dev_priv->vbt.orientation,
8398                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
8399         }
8400
8401         return true;
8402
8403 out_vdd_off:
8404         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8405         /*
8406          * vdd might still be enabled do to the delayed vdd off.
8407          * Make sure vdd is actually turned off here.
8408          */
8409         with_pps_lock(intel_dp, wakeref)
8410                 edp_panel_vdd_off_sync(intel_dp);
8411
8412         return false;
8413 }
8414
8415 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8416 {
8417         struct intel_connector *intel_connector;
8418         struct drm_connector *connector;
8419
8420         intel_connector = container_of(work, typeof(*intel_connector),
8421                                        modeset_retry_work);
8422         connector = &intel_connector->base;
8423         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8424                       connector->name);
8425
8426         /* Grab the locks before changing connector property*/
8427         mutex_lock(&connector->dev->mode_config.mutex);
8428         /* Set connector link status to BAD and send a Uevent to notify
8429          * userspace to do a modeset.
8430          */
8431         drm_connector_set_link_status_property(connector,
8432                                                DRM_MODE_LINK_STATUS_BAD);
8433         mutex_unlock(&connector->dev->mode_config.mutex);
8434         /* Send Hotplug uevent so userspace can reprobe */
8435         drm_kms_helper_hotplug_event(connector->dev);
8436 }
8437
8438 bool
8439 intel_dp_init_connector(struct intel_digital_port *dig_port,
8440                         struct intel_connector *intel_connector)
8441 {
8442         struct drm_connector *connector = &intel_connector->base;
8443         struct intel_dp *intel_dp = &dig_port->dp;
8444         struct intel_encoder *intel_encoder = &dig_port->base;
8445         struct drm_device *dev = intel_encoder->base.dev;
8446         struct drm_i915_private *dev_priv = to_i915(dev);
8447         enum port port = intel_encoder->port;
8448         enum phy phy = intel_port_to_phy(dev_priv, port);
8449         int type;
8450
8451         /* Initialize the work for modeset in case of link train failure */
8452         INIT_WORK(&intel_connector->modeset_retry_work,
8453                   intel_dp_modeset_retry_work_fn);
8454
8455         if (drm_WARN(dev, dig_port->max_lanes < 1,
8456                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8457                      dig_port->max_lanes, intel_encoder->base.base.id,
8458                      intel_encoder->base.name))
8459                 return false;
8460
8461         intel_dp_set_source_rates(intel_dp);
8462
8463         intel_dp->reset_link_params = true;
8464         intel_dp->pps_pipe = INVALID_PIPE;
8465         intel_dp->active_pipe = INVALID_PIPE;
8466
8467         /* Preserve the current hw state. */
8468         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8469         intel_dp->attached_connector = intel_connector;
8470
8471         if (intel_dp_is_port_edp(dev_priv, port)) {
8472                 /*
8473                  * Currently we don't support eDP on TypeC ports, although in
8474                  * theory it could work on TypeC legacy ports.
8475                  */
8476                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8477                 type = DRM_MODE_CONNECTOR_eDP;
8478         } else {
8479                 type = DRM_MODE_CONNECTOR_DisplayPort;
8480         }
8481
8482         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8483                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8484
8485         /*
8486          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8487          * for DP the encoder type can be set by the caller to
8488          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8489          */
8490         if (type == DRM_MODE_CONNECTOR_eDP)
8491                 intel_encoder->type = INTEL_OUTPUT_EDP;
8492
8493         /* eDP only on port B and/or C on vlv/chv */
8494         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8495                               IS_CHERRYVIEW(dev_priv)) &&
8496                         intel_dp_is_edp(intel_dp) &&
8497                         port != PORT_B && port != PORT_C))
8498                 return false;
8499
8500         drm_dbg_kms(&dev_priv->drm,
8501                     "Adding %s connector on [ENCODER:%d:%s]\n",
8502                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8503                     intel_encoder->base.base.id, intel_encoder->base.name);
8504
8505         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8506         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8507
8508         if (!HAS_GMCH(dev_priv))
8509                 connector->interlace_allowed = true;
8510         connector->doublescan_allowed = 0;
8511
8512         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8513
8514         intel_dp_aux_init(intel_dp);
8515
8516         intel_connector_attach_encoder(intel_connector, intel_encoder);
8517
8518         if (HAS_DDI(dev_priv))
8519                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8520         else
8521                 intel_connector->get_hw_state = intel_connector_get_hw_state;
8522
8523         /* init MST on ports that can support it */
8524         intel_dp_mst_encoder_init(dig_port,
8525                                   intel_connector->base.base.id);
8526
8527         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8528                 intel_dp_aux_fini(intel_dp);
8529                 intel_dp_mst_encoder_cleanup(dig_port);
8530                 goto fail;
8531         }
8532
8533         intel_dp_add_properties(intel_dp, connector);
8534
8535         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8536                 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
8537                 if (ret)
8538                         drm_dbg_kms(&dev_priv->drm,
8539                                     "HDCP init failed, skipping.\n");
8540         }
8541
8542         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8543          * 0xd.  Failure to do so will result in spurious interrupts being
8544          * generated on the port when a cable is not attached.
8545          */
8546         if (IS_G45(dev_priv)) {
8547                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8548                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8549                                (temp & ~0xf) | 0xd);
8550         }
8551
8552         intel_dp->frl.is_trained = false;
8553         intel_dp->frl.trained_rate_gbps = 0;
8554
8555         return true;
8556
8557 fail:
8558         drm_connector_cleanup(connector);
8559
8560         return false;
8561 }
8562
8563 bool intel_dp_init(struct drm_i915_private *dev_priv,
8564                    i915_reg_t output_reg,
8565                    enum port port)
8566 {
8567         struct intel_digital_port *dig_port;
8568         struct intel_encoder *intel_encoder;
8569         struct drm_encoder *encoder;
8570         struct intel_connector *intel_connector;
8571
8572         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
8573         if (!dig_port)
8574                 return false;
8575
8576         intel_connector = intel_connector_alloc();
8577         if (!intel_connector)
8578                 goto err_connector_alloc;
8579
8580         intel_encoder = &dig_port->base;
8581         encoder = &intel_encoder->base;
8582
8583         mutex_init(&dig_port->hdcp_mutex);
8584
8585         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8586                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8587                              "DP %c", port_name(port)))
8588                 goto err_encoder_init;
8589
8590         intel_encoder->hotplug = intel_dp_hotplug;
8591         intel_encoder->compute_config = intel_dp_compute_config;
8592         intel_encoder->get_hw_state = intel_dp_get_hw_state;
8593         intel_encoder->get_config = intel_dp_get_config;
8594         intel_encoder->sync_state = intel_dp_sync_state;
8595         intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
8596         intel_encoder->update_pipe = intel_panel_update_backlight;
8597         intel_encoder->suspend = intel_dp_encoder_suspend;
8598         intel_encoder->shutdown = intel_dp_encoder_shutdown;
8599         if (IS_CHERRYVIEW(dev_priv)) {
8600                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8601                 intel_encoder->pre_enable = chv_pre_enable_dp;
8602                 intel_encoder->enable = vlv_enable_dp;
8603                 intel_encoder->disable = vlv_disable_dp;
8604                 intel_encoder->post_disable = chv_post_disable_dp;
8605                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8606         } else if (IS_VALLEYVIEW(dev_priv)) {
8607                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8608                 intel_encoder->pre_enable = vlv_pre_enable_dp;
8609                 intel_encoder->enable = vlv_enable_dp;
8610                 intel_encoder->disable = vlv_disable_dp;
8611                 intel_encoder->post_disable = vlv_post_disable_dp;
8612         } else {
8613                 intel_encoder->pre_enable = g4x_pre_enable_dp;
8614                 intel_encoder->enable = g4x_enable_dp;
8615                 intel_encoder->disable = g4x_disable_dp;
8616                 intel_encoder->post_disable = g4x_post_disable_dp;
8617         }
8618
8619         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
8620             (HAS_PCH_CPT(dev_priv) && port != PORT_A))
8621                 dig_port->dp.set_link_train = cpt_set_link_train;
8622         else
8623                 dig_port->dp.set_link_train = g4x_set_link_train;
8624
8625         if (IS_CHERRYVIEW(dev_priv))
8626                 dig_port->dp.set_signal_levels = chv_set_signal_levels;
8627         else if (IS_VALLEYVIEW(dev_priv))
8628                 dig_port->dp.set_signal_levels = vlv_set_signal_levels;
8629         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
8630                 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
8631         else if (IS_GEN(dev_priv, 6) && port == PORT_A)
8632                 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
8633         else
8634                 dig_port->dp.set_signal_levels = g4x_set_signal_levels;
8635
8636         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
8637             (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
8638                 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
8639                 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
8640         } else {
8641                 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
8642                 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
8643         }
8644
8645         dig_port->dp.output_reg = output_reg;
8646         dig_port->max_lanes = 4;
8647
8648         intel_encoder->type = INTEL_OUTPUT_DP;
8649         intel_encoder->power_domain = intel_port_to_power_domain(port);
8650         if (IS_CHERRYVIEW(dev_priv)) {
8651                 if (port == PORT_D)
8652                         intel_encoder->pipe_mask = BIT(PIPE_C);
8653                 else
8654                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8655         } else {
8656                 intel_encoder->pipe_mask = ~0;
8657         }
8658         intel_encoder->cloneable = 0;
8659         intel_encoder->port = port;
8660         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8661
8662         dig_port->hpd_pulse = intel_dp_hpd_pulse;
8663
8664         if (HAS_GMCH(dev_priv)) {
8665                 if (IS_GM45(dev_priv))
8666                         dig_port->connected = gm45_digital_port_connected;
8667                 else
8668                         dig_port->connected = g4x_digital_port_connected;
8669         } else {
8670                 if (port == PORT_A)
8671                         dig_port->connected = ilk_digital_port_connected;
8672                 else
8673                         dig_port->connected = ibx_digital_port_connected;
8674         }
8675
8676         if (port != PORT_A)
8677                 intel_infoframe_init(dig_port);
8678
8679         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8680         if (!intel_dp_init_connector(dig_port, intel_connector))
8681                 goto err_init_connector;
8682
8683         return true;
8684
8685 err_init_connector:
8686         drm_encoder_cleanup(encoder);
8687 err_encoder_init:
8688         kfree(intel_connector);
8689 err_connector_alloc:
8690         kfree(dig_port);
8691         return false;
8692 }
8693
8694 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8695 {
8696         struct intel_encoder *encoder;
8697
8698         for_each_intel_encoder(&dev_priv->drm, encoder) {
8699                 struct intel_dp *intel_dp;
8700
8701                 if (encoder->type != INTEL_OUTPUT_DDI)
8702                         continue;
8703
8704                 intel_dp = enc_to_intel_dp(encoder);
8705
8706                 if (!intel_dp->can_mst)
8707                         continue;
8708
8709                 if (intel_dp->is_mst)
8710                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8711         }
8712 }
8713
8714 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8715 {
8716         struct intel_encoder *encoder;
8717
8718         for_each_intel_encoder(&dev_priv->drm, encoder) {
8719                 struct intel_dp *intel_dp;
8720                 int ret;
8721
8722                 if (encoder->type != INTEL_OUTPUT_DDI)
8723                         continue;
8724
8725                 intel_dp = enc_to_intel_dp(encoder);
8726
8727                 if (!intel_dp->can_mst)
8728                         continue;
8729
8730                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8731                                                      true);
8732                 if (ret) {
8733                         intel_dp->is_mst = false;
8734                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
8735                                                         false);
8736                 }
8737         }
8738 }