drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_debugfs.h"
  48 #include "i915_drv.h"
  49 #include "i915_reg.h"
  50 #include "intel_atomic.h"
  51 #include "intel_audio.h"
  52 #include "intel_backlight.h"
  53 #include "intel_combo_phy_regs.h"
  54 #include "intel_connector.h"
  55 #include "intel_crtc.h"
  56 #include "intel_ddi.h"
  57 #include "intel_de.h"
  58 #include "intel_display_types.h"
  59 #include "intel_dp.h"
  60 #include "intel_dp_aux.h"
  61 #include "intel_dp_hdcp.h"
  62 #include "intel_dp_link_training.h"
  63 #include "intel_dp_mst.h"
  64 #include "intel_dpio_phy.h"
  65 #include "intel_dpll.h"
  66 #include "intel_fifo_underrun.h"
  67 #include "intel_hdcp.h"
  68 #include "intel_hdmi.h"
  69 #include "intel_hotplug.h"
  70 #include "intel_lspcon.h"
  71 #include "intel_lvds.h"
  72 #include "intel_panel.h"
  73 #include "intel_pch_display.h"
  74 #include "intel_pps.h"
  75 #include "intel_psr.h"
  76 #include "intel_tc.h"
  77 #include "intel_vdsc.h"
  78 #include "intel_vrr.h"
  79 #include "intel_crtc_state_dump.h"
  80
  81 /* DP DSC throughput values used for slice count calculations KPixels/s */
  82 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  83 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  84 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  85
  86 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  87 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  88
  89 /* Compliance test status bits  */
  90 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  91 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  92 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  93 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  94
  95
  96 /* Constants for DP DSC configurations */
  97 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  98
  99 /* With Single pipe configuration, HW is capable of supporting maximum
 100  * of 4 slices per line.
 101  */
 102 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 103
 104 /**
 105  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 106  * @intel_dp: DP struct
 107  *
 108  * If a CPU or PCH DP output is attached to an eDP panel, this function
 109  * will return true, and false otherwise.
 110  *
 111  * This function is not safe to use prior to encoder type being set.
 112  */
 113 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 114 {
 115         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 116
 117         return dig_port->base.type == INTEL_OUTPUT_EDP;
 118 }
 119
 120 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 121
 122 /* Is link rate UHBR and thus 128b/132b? */
 123 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 124 {
 125         return crtc_state->port_clock >= 1000000;
 126 }
 127
 128 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 129 {
 130         intel_dp->sink_rates[0] = 162000;
 131         intel_dp->num_sink_rates = 1;
 132 }
 133
 134 /* update sink rates from dpcd */
 135 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 136 {
 137         static const int dp_rates[] = {
 138                 162000, 270000, 540000, 810000
 139         };
 140         int i, max_rate;
 141         int max_lttpr_rate;
 142
 143         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 144                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 145                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 146
 147                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 148                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 149
 150                 return;
 151         }
 152
 153         /*
 154          * Sink rates for 8b/10b.
 155          */
 156         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 157         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 158         if (max_lttpr_rate)
 159                 max_rate = min(max_rate, max_lttpr_rate);
 160
 161         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 162                 if (dp_rates[i] > max_rate)
 163                         break;
 164                 intel_dp->sink_rates[i] = dp_rates[i];
 165         }
 166
 167         /*
 168          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 169          * rates and 10 Gbps.
 170          */
 171         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 172                 u8 uhbr_rates = 0;
 173
 174                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 175
 176                 drm_dp_dpcd_readb(&intel_dp->aux,
 177                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 178
 179                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 180                         /* We have a repeater */
 181                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 182                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 183                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 184                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 185                                 /* Repeater supports 128b/132b, valid UHBR rates */
 186                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 187                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 188                         } else {
 189                                 /* Does not support 128b/132b */
 190                                 uhbr_rates = 0;
 191                         }
 192                 }
 193
 194                 if (uhbr_rates & DP_UHBR10)
 195                         intel_dp->sink_rates[i++] = 1000000;
 196                 if (uhbr_rates & DP_UHBR13_5)
 197                         intel_dp->sink_rates[i++] = 1350000;
 198                 if (uhbr_rates & DP_UHBR20)
 199                         intel_dp->sink_rates[i++] = 2000000;
 200         }
 201
 202         intel_dp->num_sink_rates = i;
 203 }
 204
 205 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 206 {
 207         struct intel_connector *connector = intel_dp->attached_connector;
 208         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 209         struct intel_encoder *encoder = &intel_dig_port->base;
 210
 211         intel_dp_set_dpcd_sink_rates(intel_dp);
 212
 213         if (intel_dp->num_sink_rates)
 214                 return;
 215
 216         drm_err(&dp_to_i915(intel_dp)->drm,
 217                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 218                 connector->base.base.id, connector->base.name,
 219                 encoder->base.base.id, encoder->base.name);
 220
 221         intel_dp_set_default_sink_rates(intel_dp);
 222 }
 223
 224 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 225 {
 226         intel_dp->max_sink_lane_count = 1;
 227 }
 228
 229 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 230 {
 231         struct intel_connector *connector = intel_dp->attached_connector;
 232         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 233         struct intel_encoder *encoder = &intel_dig_port->base;
 234
 235         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 236
 237         switch (intel_dp->max_sink_lane_count) {
 238         case 1:
 239         case 2:
 240         case 4:
 241                 return;
 242         }
 243
 244         drm_err(&dp_to_i915(intel_dp)->drm,
 245                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 246                 connector->base.base.id, connector->base.name,
 247                 encoder->base.base.id, encoder->base.name,
 248                 intel_dp->max_sink_lane_count);
 249
 250         intel_dp_set_default_max_sink_lane_count(intel_dp);
 251 }
 252
 253 /* Get length of rates array potentially limited by max_rate. */
 254 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 255 {
 256         int i;
 257
 258         /* Limit results by potentially reduced max rate */
 259         for (i = 0; i < len; i++) {
 260                 if (rates[len - i - 1] <= max_rate)
 261                         return len - i;
 262         }
 263
 264         return 0;
 265 }
 266
 267 /* Get length of common rates array potentially limited by max_rate. */
 268 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 269                                           int max_rate)
 270 {
 271         return intel_dp_rate_limit_len(intel_dp->common_rates,
 272                                        intel_dp->num_common_rates, max_rate);
 273 }
 274
 275 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 276 {
 277         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 278                         index < 0 || index >= intel_dp->num_common_rates))
 279                 return 162000;
 280
 281         return intel_dp->common_rates[index];
 282 }
 283
 284 /* Theoretical max between source and sink */
 285 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 286 {
 287         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 288 }
 289
 290 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 291 {
 292         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 293         int max_lanes = dig_port->max_lanes;
 294
 295         if (vbt_max_lanes)
 296                 max_lanes = min(max_lanes, vbt_max_lanes);
 297
 298         return max_lanes;
 299 }
 300
 301 /* Theoretical max between source and sink */
 302 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 303 {
 304         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 305         int source_max = intel_dp_max_source_lane_count(dig_port);
 306         int sink_max = intel_dp->max_sink_lane_count;
 307         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 308         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 309
 310         if (lttpr_max)
 311                 sink_max = min(sink_max, lttpr_max);
 312
 313         return min3(source_max, sink_max, fia_max);
 314 }
 315
 316 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 317 {
 318         switch (intel_dp->max_link_lane_count) {
 319         case 1:
 320         case 2:
 321         case 4:
 322                 return intel_dp->max_link_lane_count;
 323         default:
 324                 MISSING_CASE(intel_dp->max_link_lane_count);
 325                 return 1;
 326         }
 327 }
 328
 329 /*
 330  * The required data bandwidth for a mode with given pixel clock and bpp. This
 331  * is the required net bandwidth independent of the data bandwidth efficiency.
 332  */
 333 int
 334 intel_dp_link_required(int pixel_clock, int bpp)
 335 {
 336         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 337         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 338 }
 339
 340 /*
 341  * Given a link rate and lanes, get the data bandwidth.
 342  *
 343  * Data bandwidth is the actual payload rate, which depends on the data
 344  * bandwidth efficiency and the link rate.
 345  *
 346  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 347  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 348  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 349  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 350  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 351  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 352  *
 353  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 354  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 355  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 356  * does not match the symbol clock, the port clock (not even if you think in
 357  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 358  * rate in units of 10000 bps.
 359  */
 360 int
 361 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 362 {
 363         if (max_link_rate >= 1000000) {
 364                 /*
 365                  * UHBR rates always use 128b/132b channel encoding, and have
 366                  * 97.71% data bandwidth efficiency. Consider max_link_rate the
 367                  * link bit rate in units of 10000 bps.
 368                  */
 369                 int max_link_rate_kbps = max_link_rate * 10;
 370
 371                 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 372                 max_link_rate = max_link_rate_kbps / 8;
 373         }
 374
 375         /*
 376          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 377          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 378          * out to be a nop by coincidence, and can be skipped:
 379          *
 380          *      int max_link_rate_kbps = max_link_rate * 10;
 381          *      max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 382          *      max_link_rate = max_link_rate_kbps / 8;
 383          */
 384
 385         return max_link_rate * max_lanes;
 386 }
 387
 388 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 389 {
 390         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 391         struct intel_encoder *encoder = &intel_dig_port->base;
 392         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 393
 394         return DISPLAY_VER(dev_priv) >= 12 ||
 395                 (DISPLAY_VER(dev_priv) == 11 &&
 396                  encoder->port != PORT_A);
 397 }
 398
 399 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 400 {
 401         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 402 }
 403
 404 static int icl_max_source_rate(struct intel_dp *intel_dp)
 405 {
 406         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 407         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 408         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 409
 410         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 411                 return 540000;
 412
 413         return 810000;
 414 }
 415
 416 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 417 {
 418         if (intel_dp_is_edp(intel_dp))
 419                 return 540000;
 420
 421         return 810000;
 422 }
 423
 424 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 425 {
 426         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 427         int max_rate;
 428
 429         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 430
 431         if (intel_dp_is_edp(intel_dp)) {
 432                 struct intel_connector *connector = intel_dp->attached_connector;
 433                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 434
 435                 if (max_rate && edp_max_rate)
 436                         max_rate = min(max_rate, edp_max_rate);
 437                 else if (edp_max_rate)
 438                         max_rate = edp_max_rate;
 439         }
 440
 441         return max_rate;
 442 }
 443
 444 static void
 445 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 446 {
 447         /* The values must be in increasing order */
 448         static const int icl_rates[] = {
 449                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 450                 1000000, 1350000,
 451         };
 452         static const int bxt_rates[] = {
 453                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 454         };
 455         static const int skl_rates[] = {
 456                 162000, 216000, 270000, 324000, 432000, 540000
 457         };
 458         static const int hsw_rates[] = {
 459                 162000, 270000, 540000
 460         };
 461         static const int g4x_rates[] = {
 462                 162000, 270000
 463         };
 464         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 465         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 466         const int *source_rates;
 467         int size, max_rate = 0, vbt_max_rate;
 468
 469         /* This should only be done once */
 470         drm_WARN_ON(&dev_priv->drm,
 471                     intel_dp->source_rates || intel_dp->num_source_rates);
 472
 473         if (DISPLAY_VER(dev_priv) >= 11) {
 474                 source_rates = icl_rates;
 475                 size = ARRAY_SIZE(icl_rates);
 476                 if (IS_DG2(dev_priv))
 477                         max_rate = dg2_max_source_rate(intel_dp);
 478                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 479                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 480                         max_rate = 810000;
 481                 else if (IS_JSL_EHL(dev_priv))
 482                         max_rate = ehl_max_source_rate(intel_dp);
 483                 else
 484                         max_rate = icl_max_source_rate(intel_dp);
 485         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 486                 source_rates = bxt_rates;
 487                 size = ARRAY_SIZE(bxt_rates);
 488         } else if (DISPLAY_VER(dev_priv) == 9) {
 489                 source_rates = skl_rates;
 490                 size = ARRAY_SIZE(skl_rates);
 491         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 492                    IS_BROADWELL(dev_priv)) {
 493                 source_rates = hsw_rates;
 494                 size = ARRAY_SIZE(hsw_rates);
 495         } else {
 496                 source_rates = g4x_rates;
 497                 size = ARRAY_SIZE(g4x_rates);
 498         }
 499
 500         vbt_max_rate = vbt_max_link_rate(intel_dp);
 501         if (max_rate && vbt_max_rate)
 502                 max_rate = min(max_rate, vbt_max_rate);
 503         else if (vbt_max_rate)
 504                 max_rate = vbt_max_rate;
 505
 506         if (max_rate)
 507                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 508
 509         intel_dp->source_rates = source_rates;
 510         intel_dp->num_source_rates = size;
 511 }
 512
 513 static int intersect_rates(const int *source_rates, int source_len,
 514                            const int *sink_rates, int sink_len,
 515                            int *common_rates)
 516 {
 517         int i = 0, j = 0, k = 0;
 518
 519         while (i < source_len && j < sink_len) {
 520                 if (source_rates[i] == sink_rates[j]) {
 521                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 522                                 return k;
 523                         common_rates[k] = source_rates[i];
 524                         ++k;
 525                         ++i;
 526                         ++j;
 527                 } else if (source_rates[i] < sink_rates[j]) {
 528                         ++i;
 529                 } else {
 530                         ++j;
 531                 }
 532         }
 533         return k;
 534 }
 535
 536 /* return index of rate in rates array, or -1 if not found */
 537 static int intel_dp_rate_index(const int *rates, int len, int rate)
 538 {
 539         int i;
 540
 541         for (i = 0; i < len; i++)
 542                 if (rate == rates[i])
 543                         return i;
 544
 545         return -1;
 546 }
 547
 548 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 549 {
 550         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 551
 552         drm_WARN_ON(&i915->drm,
 553                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 554
 555         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 556                                                      intel_dp->num_source_rates,
 557                                                      intel_dp->sink_rates,
 558                                                      intel_dp->num_sink_rates,
 559                                                      intel_dp->common_rates);
 560
 561         /* Paranoia, there should always be something in common. */
 562         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 563                 intel_dp->common_rates[0] = 162000;
 564                 intel_dp->num_common_rates = 1;
 565         }
 566 }
 567
 568 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 569                                        u8 lane_count)
 570 {
 571         /*
 572          * FIXME: we need to synchronize the current link parameters with
 573          * hardware readout. Currently fast link training doesn't work on
 574          * boot-up.
 575          */
 576         if (link_rate == 0 ||
 577             link_rate > intel_dp->max_link_rate)
 578                 return false;
 579
 580         if (lane_count == 0 ||
 581             lane_count > intel_dp_max_lane_count(intel_dp))
 582                 return false;
 583
 584         return true;
 585 }
 586
 587 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 588                                                      int link_rate,
 589                                                      u8 lane_count)
 590 {
 591         /* FIXME figure out what we actually want here */
 592         const struct drm_display_mode *fixed_mode =
 593                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 594         int mode_rate, max_rate;
 595
 596         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 597         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 598         if (mode_rate > max_rate)
 599                 return false;
 600
 601         return true;
 602 }
 603
 604 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 605                                             int link_rate, u8 lane_count)
 606 {
 607         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 608         int index;
 609
 610         /*
 611          * TODO: Enable fallback on MST links once MST link compute can handle
 612          * the fallback params.
 613          */
 614         if (intel_dp->is_mst) {
 615                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 616                 return -1;
 617         }
 618
 619         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 620                 drm_dbg_kms(&i915->drm,
 621                             "Retrying Link training for eDP with max parameters\n");
 622                 intel_dp->use_max_params = true;
 623                 return 0;
 624         }
 625
 626         index = intel_dp_rate_index(intel_dp->common_rates,
 627                                     intel_dp->num_common_rates,
 628                                     link_rate);
 629         if (index > 0) {
 630                 if (intel_dp_is_edp(intel_dp) &&
 631                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 632                                                               intel_dp_common_rate(intel_dp, index - 1),
 633                                                               lane_count)) {
 634                         drm_dbg_kms(&i915->drm,
 635                                     "Retrying Link training for eDP with same parameters\n");
 636                         return 0;
 637                 }
 638                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 639                 intel_dp->max_link_lane_count = lane_count;
 640         } else if (lane_count > 1) {
 641                 if (intel_dp_is_edp(intel_dp) &&
 642                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 643                                                               intel_dp_max_common_rate(intel_dp),
 644                                                               lane_count >> 1)) {
 645                         drm_dbg_kms(&i915->drm,
 646                                     "Retrying Link training for eDP with same parameters\n");
 647                         return 0;
 648                 }
 649                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 650                 intel_dp->max_link_lane_count = lane_count >> 1;
 651         } else {
 652                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 653                 return -1;
 654         }
 655
 656         return 0;
 657 }
 658
 659 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 660 {
 661         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 662                        DP_DSC_FEC_OVERHEAD_FACTOR);
 663 }
 664
 665 static int
 666 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 667 {
 668         if (DISPLAY_VER(i915) >= 13)
 669                 return 17280 * 8;
 670         else if (DISPLAY_VER(i915) >= 11)
 671                 return 7680 * 8;
 672         else
 673                 return 6144 * 8;
 674 }
 675
 676 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 677 {
 678         u32 bits_per_pixel = bpp;
 679         int i;
 680
 681         /* Error out if the max bpp is less than smallest allowed valid bpp */
 682         if (bits_per_pixel < valid_dsc_bpp[0]) {
 683                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 684                             bits_per_pixel, valid_dsc_bpp[0]);
 685                 return 0;
 686         }
 687
 688         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 689         if (DISPLAY_VER(i915) >= 13) {
 690                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 691
 692                 /*
 693                  * According to BSpec, 27 is the max DSC output bpp,
 694                  * 8 is the min DSC output bpp
 695                  */
 696                 bits_per_pixel = clamp_t(u32, bits_per_pixel, 8, 27);
 697         } else {
 698                 /* Find the nearest match in the array of known BPPs from VESA */
 699                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 700                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 701                                 break;
 702                 }
 703                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 704                             bits_per_pixel, valid_dsc_bpp[i]);
 705
 706                 bits_per_pixel = valid_dsc_bpp[i];
 707         }
 708
 709         return bits_per_pixel;
 710 }
 711
 712 u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 713                                 u32 link_clock, u32 lane_count,
 714                                 u32 mode_clock, u32 mode_hdisplay,
 715                                 bool bigjoiner,
 716                                 u32 pipe_bpp,
 717                                 u32 timeslots)
 718 {
 719         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 720
 721         /*
 722          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 723          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 724          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 725          * for MST -> TimeSlots has to be calculated, based on mode requirements
 726          *
 727          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 728          * To support the given mode:
 729          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 730          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 731          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 732          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 733          *                     (ModeClock / FEC Overhead)
 734          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 735          *                     (ModeClock / FEC Overhead * 8)
 736          */
 737         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 738                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 739
 740         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 741                                 "total bw %u pixel clock %u\n",
 742                                 bits_per_pixel, timeslots,
 743                                 (link_clock * lane_count * 8),
 744                                 intel_dp_mode_to_fec_clock(mode_clock));
 745
 746         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 747         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 748                 mode_hdisplay;
 749
 750         if (bigjoiner)
 751                 max_bpp_small_joiner_ram *= 2;
 752
 753         /*
 754          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 755          * check, output bpp from small joiner RAM check)
 756          */
 757         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 758
 759         if (bigjoiner) {
 760                 u32 max_bpp_bigjoiner =
 761                         i915->display.cdclk.max_cdclk_freq * 48 /
 762                         intel_dp_mode_to_fec_clock(mode_clock);
 763
 764                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 765         }
 766
 767         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 768
 769         /*
 770          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 771          * fractional part is 0
 772          */
 773         return bits_per_pixel << 4;
 774 }
 775
 776 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 777                                 int mode_clock, int mode_hdisplay,
 778                                 bool bigjoiner)
 779 {
 780         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 781         u8 min_slice_count, i;
 782         int max_slice_width;
 783
 784         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 785                 min_slice_count = DIV_ROUND_UP(mode_clock,
 786                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 787         else
 788                 min_slice_count = DIV_ROUND_UP(mode_clock,
 789                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 790
 791         /*
 792          * Due to some DSC engine BW limitations, we need to enable second
 793          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 794          */
 795         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 796                 min_slice_count = max_t(u8, min_slice_count, 2);
 797
 798         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 799         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 800                 drm_dbg_kms(&i915->drm,
 801                             "Unsupported slice width %d by DP DSC Sink device\n",
 802                             max_slice_width);
 803                 return 0;
 804         }
 805         /* Also take into account max slice width */
 806         min_slice_count = max_t(u8, min_slice_count,
 807                                 DIV_ROUND_UP(mode_hdisplay,
 808                                              max_slice_width));
 809
 810         /* Find the closest match to the valid slice count values */
 811         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 812                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 813
 814                 if (test_slice_count >
 815                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 816                         break;
 817
 818                 /* big joiner needs small joiner to be enabled */
 819                 if (bigjoiner && test_slice_count < 4)
 820                         continue;
 821
 822                 if (min_slice_count <= test_slice_count)
 823                         return test_slice_count;
 824         }
 825
 826         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 827                     min_slice_count);
 828         return 0;
 829 }
 830
 831 static enum intel_output_format
 832 intel_dp_output_format(struct intel_connector *connector,
 833                        bool ycbcr_420_output)
 834 {
 835         struct intel_dp *intel_dp = intel_attached_dp(connector);
 836
 837         if (intel_dp->force_dsc_output_format)
 838                 return intel_dp->force_dsc_output_format;
 839
 840         if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 841                 return INTEL_OUTPUT_FORMAT_RGB;
 842
 843         if (intel_dp->dfp.rgb_to_ycbcr &&
 844             intel_dp->dfp.ycbcr_444_to_420)
 845                 return INTEL_OUTPUT_FORMAT_RGB;
 846
 847         if (intel_dp->dfp.ycbcr_444_to_420)
 848                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 849         else
 850                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 851 }
 852
 853 int intel_dp_min_bpp(enum intel_output_format output_format)
 854 {
 855         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 856                 return 6 * 3;
 857         else
 858                 return 8 * 3;
 859 }
 860
 861 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 862 {
 863         /*
 864          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 865          * format of the number of bytes per pixel will be half the number
 866          * of bytes of RGB pixel.
 867          */
 868         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 869                 bpp /= 2;
 870
 871         return bpp;
 872 }
 873
 874 static int
 875 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 876                              const struct drm_display_mode *mode)
 877 {
 878         const struct drm_display_info *info = &connector->base.display_info;
 879         enum intel_output_format output_format =
 880                 intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
 881
 882         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 883 }
 884
 885 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 886                                   int hdisplay)
 887 {
 888         /*
 889          * Older platforms don't like hdisplay==4096 with DP.
 890          *
 891          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 892          * and frame counter increment), but we don't get vblank interrupts,
 893          * and the pipe underruns immediately. The link also doesn't seem
 894          * to get trained properly.
 895          *
 896          * On CHV the vblank interrupts don't seem to disappear but
 897          * otherwise the symptoms are similar.
 898          *
 899          * TODO: confirm the behaviour on HSW+
 900          */
 901         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 902 }
 903
 904 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
 905 {
 906         struct intel_connector *connector = intel_dp->attached_connector;
 907         const struct drm_display_info *info = &connector->base.display_info;
 908         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
 909
 910         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
 911         if (max_tmds_clock && info->max_tmds_clock)
 912                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
 913
 914         return max_tmds_clock;
 915 }
 916
 917 static enum drm_mode_status
 918 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
 919                           int clock, int bpc, bool ycbcr420_output,
 920                           bool respect_downstream_limits)
 921 {
 922         int tmds_clock, min_tmds_clock, max_tmds_clock;
 923
 924         if (!respect_downstream_limits)
 925                 return MODE_OK;
 926
 927         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
 928
 929         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
 930         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
 931
 932         if (min_tmds_clock && tmds_clock < min_tmds_clock)
 933                 return MODE_CLOCK_LOW;
 934
 935         if (max_tmds_clock && tmds_clock > max_tmds_clock)
 936                 return MODE_CLOCK_HIGH;
 937
 938         return MODE_OK;
 939 }
 940
 941 static enum drm_mode_status
 942 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 943                                const struct drm_display_mode *mode,
 944                                int target_clock)
 945 {
 946         struct intel_dp *intel_dp = intel_attached_dp(connector);
 947         const struct drm_display_info *info = &connector->base.display_info;
 948         enum drm_mode_status status;
 949         bool ycbcr_420_only;
 950
 951         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 952         if (intel_dp->dfp.pcon_max_frl_bw) {
 953                 int target_bw;
 954                 int max_frl_bw;
 955                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
 956
 957                 target_bw = bpp * target_clock;
 958
 959                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 960
 961                 /* converting bw from Gbps to Kbps*/
 962                 max_frl_bw = max_frl_bw * 1000000;
 963
 964                 if (target_bw > max_frl_bw)
 965                         return MODE_CLOCK_HIGH;
 966
 967                 return MODE_OK;
 968         }
 969
 970         if (intel_dp->dfp.max_dotclock &&
 971             target_clock > intel_dp->dfp.max_dotclock)
 972                 return MODE_CLOCK_HIGH;
 973
 974         ycbcr_420_only = drm_mode_is_420_only(info, mode);
 975
 976         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 977         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 978                                            8, ycbcr_420_only, true);
 979
 980         if (status != MODE_OK) {
 981                 if (ycbcr_420_only ||
 982                     !connector->base.ycbcr_420_allowed ||
 983                     !drm_mode_is_420_also(info, mode))
 984                         return status;
 985
 986                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 987                                                    8, true, true);
 988                 if (status != MODE_OK)
 989                         return status;
 990         }
 991
 992         return MODE_OK;
 993 }
 994
 995 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
 996                              int hdisplay, int clock)
 997 {
 998         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 999
1000         if (!intel_dp_can_bigjoiner(intel_dp))
1001                 return false;
1002
1003         return clock > i915->max_dotclk_freq || hdisplay > 5120;
1004 }
1005
1006 static enum drm_mode_status
1007 intel_dp_mode_valid(struct drm_connector *_connector,
1008                     struct drm_display_mode *mode)
1009 {
1010         struct intel_connector *connector = to_intel_connector(_connector);
1011         struct intel_dp *intel_dp = intel_attached_dp(connector);
1012         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1013         const struct drm_display_mode *fixed_mode;
1014         int target_clock = mode->clock;
1015         int max_rate, mode_rate, max_lanes, max_link_clock;
1016         int max_dotclk = dev_priv->max_dotclk_freq;
1017         u16 dsc_max_output_bpp = 0;
1018         u8 dsc_slice_count = 0;
1019         enum drm_mode_status status;
1020         bool dsc = false, bigjoiner = false;
1021
1022         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1023                 return MODE_H_ILLEGAL;
1024
1025         fixed_mode = intel_panel_fixed_mode(connector, mode);
1026         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1027                 status = intel_panel_mode_valid(connector, mode);
1028                 if (status != MODE_OK)
1029                         return status;
1030
1031                 target_clock = fixed_mode->clock;
1032         }
1033
1034         if (mode->clock < 10000)
1035                 return MODE_CLOCK_LOW;
1036
1037         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1038                 bigjoiner = true;
1039                 max_dotclk *= 2;
1040         }
1041         if (target_clock > max_dotclk)
1042                 return MODE_CLOCK_HIGH;
1043
1044         max_link_clock = intel_dp_max_link_rate(intel_dp);
1045         max_lanes = intel_dp_max_lane_count(intel_dp);
1046
1047         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1048         mode_rate = intel_dp_link_required(target_clock,
1049                                            intel_dp_mode_min_output_bpp(connector, mode));
1050
1051         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1052                 return MODE_H_ILLEGAL;
1053
1054         /*
1055          * Output bpp is stored in 6.4 format so right shift by 4 to get the
1056          * integer value since we support only integer values of bpp.
1057          */
1058         if (HAS_DSC(dev_priv) &&
1059             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1060                 /*
1061                  * TBD pass the connector BPC,
1062                  * for now U8_MAX so that max BPC on that platform would be picked
1063                  */
1064                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1065
1066                 if (intel_dp_is_edp(intel_dp)) {
1067                         dsc_max_output_bpp =
1068                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1069                         dsc_slice_count =
1070                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1071                                                                 true);
1072                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1073                         dsc_max_output_bpp =
1074                                 intel_dp_dsc_get_output_bpp(dev_priv,
1075                                                             max_link_clock,
1076                                                             max_lanes,
1077                                                             target_clock,
1078                                                             mode->hdisplay,
1079                                                             bigjoiner,
1080                                                             pipe_bpp, 64) >> 4;
1081                         dsc_slice_count =
1082                                 intel_dp_dsc_get_slice_count(intel_dp,
1083                                                              target_clock,
1084                                                              mode->hdisplay,
1085                                                              bigjoiner);
1086                 }
1087
1088                 dsc = dsc_max_output_bpp && dsc_slice_count;
1089         }
1090
1091         /*
1092          * Big joiner configuration needs DSC for TGL which is not true for
1093          * XE_LPD where uncompressed joiner is supported.
1094          */
1095         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1096                 return MODE_CLOCK_HIGH;
1097
1098         if (mode_rate > max_rate && !dsc)
1099                 return MODE_CLOCK_HIGH;
1100
1101         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1102         if (status != MODE_OK)
1103                 return status;
1104
1105         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1106 }
1107
1108 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1109 {
1110         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1111 }
1112
1113 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1114 {
1115         return DISPLAY_VER(i915) >= 10;
1116 }
1117
1118 static void snprintf_int_array(char *str, size_t len,
1119                                const int *array, int nelem)
1120 {
1121         int i;
1122
1123         str[0] = '\0';
1124
1125         for (i = 0; i < nelem; i++) {
1126                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1127                 if (r >= len)
1128                         return;
1129                 str += r;
1130                 len -= r;
1131         }
1132 }
1133
1134 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1135 {
1136         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1137         char str[128]; /* FIXME: too big for stack? */
1138
1139         if (!drm_debug_enabled(DRM_UT_KMS))
1140                 return;
1141
1142         snprintf_int_array(str, sizeof(str),
1143                            intel_dp->source_rates, intel_dp->num_source_rates);
1144         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1145
1146         snprintf_int_array(str, sizeof(str),
1147                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1148         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1149
1150         snprintf_int_array(str, sizeof(str),
1151                            intel_dp->common_rates, intel_dp->num_common_rates);
1152         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1153 }
1154
1155 int
1156 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1157 {
1158         int len;
1159
1160         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1161
1162         return intel_dp_common_rate(intel_dp, len - 1);
1163 }
1164
1165 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1166 {
1167         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1168         int i = intel_dp_rate_index(intel_dp->sink_rates,
1169                                     intel_dp->num_sink_rates, rate);
1170
1171         if (drm_WARN_ON(&i915->drm, i < 0))
1172                 i = 0;
1173
1174         return i;
1175 }
1176
1177 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1178                            u8 *link_bw, u8 *rate_select)
1179 {
1180         /* eDP 1.4 rate select method. */
1181         if (intel_dp->use_rate_select) {
1182                 *link_bw = 0;
1183                 *rate_select =
1184                         intel_dp_rate_select(intel_dp, port_clock);
1185         } else {
1186                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1187                 *rate_select = 0;
1188         }
1189 }
1190
1191 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1192                                          const struct intel_crtc_state *pipe_config)
1193 {
1194         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1195
1196         /* On TGL, FEC is supported on all Pipes */
1197         if (DISPLAY_VER(dev_priv) >= 12)
1198                 return true;
1199
1200         if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1201                 return true;
1202
1203         return false;
1204 }
1205
1206 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1207                                   const struct intel_crtc_state *pipe_config)
1208 {
1209         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1210                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1211 }
1212
1213 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1214                                   const struct intel_crtc_state *crtc_state)
1215 {
1216         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1217                 return false;
1218
1219         return intel_dsc_source_support(crtc_state) &&
1220                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1221 }
1222
1223 static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
1224                                  const struct intel_crtc_state *crtc_state)
1225 {
1226         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1227                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1228                  intel_dp->dfp.ycbcr_444_to_420);
1229 }
1230
1231 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1232                                      const struct intel_crtc_state *crtc_state,
1233                                      int bpc, bool respect_downstream_limits)
1234 {
1235         bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
1236         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1237
1238         /*
1239          * Current bpc could already be below 8bpc due to
1240          * FDI bandwidth constraints or other limits.
1241          * HDMI minimum is 8bpc however.
1242          */
1243         bpc = max(bpc, 8);
1244
1245         /*
1246          * We will never exceed downstream TMDS clock limits while
1247          * attempting deep color. If the user insists on forcing an
1248          * out of spec mode they will have to be satisfied with 8bpc.
1249          */
1250         if (!respect_downstream_limits)
1251                 bpc = 8;
1252
1253         for (; bpc >= 8; bpc -= 2) {
1254                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1255                                             intel_dp->has_hdmi_sink, ycbcr420_output) &&
1256                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
1257                                               respect_downstream_limits) == MODE_OK)
1258                         return bpc;
1259         }
1260
1261         return -EINVAL;
1262 }
1263
1264 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1265                             const struct intel_crtc_state *crtc_state,
1266                             bool respect_downstream_limits)
1267 {
1268         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1269         struct intel_connector *intel_connector = intel_dp->attached_connector;
1270         int bpp, bpc;
1271
1272         bpc = crtc_state->pipe_bpp / 3;
1273
1274         if (intel_dp->dfp.max_bpc)
1275                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1276
1277         if (intel_dp->dfp.min_tmds_clock) {
1278                 int max_hdmi_bpc;
1279
1280                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1281                                                          respect_downstream_limits);
1282                 if (max_hdmi_bpc < 0)
1283                         return 0;
1284
1285                 bpc = min(bpc, max_hdmi_bpc);
1286         }
1287
1288         bpp = bpc * 3;
1289         if (intel_dp_is_edp(intel_dp)) {
1290                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1291                 if (intel_connector->base.display_info.bpc == 0 &&
1292                     intel_connector->panel.vbt.edp.bpp &&
1293                     intel_connector->panel.vbt.edp.bpp < bpp) {
1294                         drm_dbg_kms(&dev_priv->drm,
1295                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1296                                     intel_connector->panel.vbt.edp.bpp);
1297                         bpp = intel_connector->panel.vbt.edp.bpp;
1298                 }
1299         }
1300
1301         return bpp;
1302 }
1303
1304 /* Adjust link config limits based on compliance test requests. */
1305 void
1306 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1307                                   struct intel_crtc_state *pipe_config,
1308                                   struct link_config_limits *limits)
1309 {
1310         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1311
1312         /* For DP Compliance we override the computed bpp for the pipe */
1313         if (intel_dp->compliance.test_data.bpc != 0) {
1314                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1315
1316                 limits->min_bpp = limits->max_bpp = bpp;
1317                 pipe_config->dither_force_disable = bpp == 6 * 3;
1318
1319                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1320         }
1321
1322         /* Use values requested by Compliance Test Request */
1323         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1324                 int index;
1325
1326                 /* Validate the compliance test data since max values
1327                  * might have changed due to link train fallback.
1328                  */
1329                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1330                                                intel_dp->compliance.test_lane_count)) {
1331                         index = intel_dp_rate_index(intel_dp->common_rates,
1332                                                     intel_dp->num_common_rates,
1333                                                     intel_dp->compliance.test_link_rate);
1334                         if (index >= 0)
1335                                 limits->min_rate = limits->max_rate =
1336                                         intel_dp->compliance.test_link_rate;
1337                         limits->min_lane_count = limits->max_lane_count =
1338                                 intel_dp->compliance.test_lane_count;
1339                 }
1340         }
1341 }
1342
1343 static bool has_seamless_m_n(struct intel_connector *connector)
1344 {
1345         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1346
1347         /*
1348          * Seamless M/N reprogramming only implemented
1349          * for BDW+ double buffered M/N registers so far.
1350          */
1351         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1352                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1353 }
1354
1355 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1356                                const struct drm_connector_state *conn_state)
1357 {
1358         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1359         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1360
1361         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1362         if (has_seamless_m_n(connector))
1363                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1364         else
1365                 return adjusted_mode->crtc_clock;
1366 }
1367
1368 /* Optimize link config in order: max bpp, min clock, min lanes */
1369 static int
1370 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1371                                   struct intel_crtc_state *pipe_config,
1372                                   const struct drm_connector_state *conn_state,
1373                                   const struct link_config_limits *limits)
1374 {
1375         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1376         int mode_rate, link_rate, link_avail;
1377
1378         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1379                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1380
1381                 mode_rate = intel_dp_link_required(clock, output_bpp);
1382
1383                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1384                         link_rate = intel_dp_common_rate(intel_dp, i);
1385                         if (link_rate < limits->min_rate ||
1386                             link_rate > limits->max_rate)
1387                                 continue;
1388
1389                         for (lane_count = limits->min_lane_count;
1390                              lane_count <= limits->max_lane_count;
1391                              lane_count <<= 1) {
1392                                 link_avail = intel_dp_max_data_rate(link_rate,
1393                                                                     lane_count);
1394
1395                                 if (mode_rate <= link_avail) {
1396                                         pipe_config->lane_count = lane_count;
1397                                         pipe_config->pipe_bpp = bpp;
1398                                         pipe_config->port_clock = link_rate;
1399
1400                                         return 0;
1401                                 }
1402                         }
1403                 }
1404         }
1405
1406         return -EINVAL;
1407 }
1408
1409 int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1410 {
1411         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1412         int i, num_bpc;
1413         u8 dsc_bpc[3] = {0};
1414         u8 dsc_max_bpc;
1415
1416         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1417         if (DISPLAY_VER(i915) >= 12)
1418                 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1419         else
1420                 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1421
1422         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1423                                                        dsc_bpc);
1424         for (i = 0; i < num_bpc; i++) {
1425                 if (dsc_max_bpc >= dsc_bpc[i])
1426                         return dsc_bpc[i] * 3;
1427         }
1428
1429         return 0;
1430 }
1431
1432 static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
1433 {
1434         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1435
1436         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1437 }
1438
1439 static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
1440 {
1441         return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1442                 DP_DSC_MINOR_SHIFT;
1443 }
1444
1445 static int intel_dp_get_slice_height(int vactive)
1446 {
1447         int slice_height;
1448
1449         /*
1450          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1451          * lines is an optimal slice height, but any size can be used as long as
1452          * vertical active integer multiple and maximum vertical slice count
1453          * requirements are met.
1454          */
1455         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1456                 if (vactive % slice_height == 0)
1457                         return slice_height;
1458
1459         /*
1460          * Highly unlikely we reach here as most of the resolutions will end up
1461          * finding appropriate slice_height in above loop but returning
1462          * slice_height as 2 here as it should work with all resolutions.
1463          */
1464         return 2;
1465 }
1466
1467 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1468                                        struct intel_crtc_state *crtc_state)
1469 {
1470         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1471         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1472         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1473         u8 line_buf_depth;
1474         int ret;
1475
1476         /*
1477          * RC_MODEL_SIZE is currently a constant across all configurations.
1478          *
1479          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1480          * DP_DSC_RC_BUF_SIZE for this.
1481          */
1482         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1483         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1484
1485         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1486
1487         ret = intel_dsc_compute_params(crtc_state);
1488         if (ret)
1489                 return ret;
1490
1491         vdsc_cfg->dsc_version_major =
1492                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1493                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1494         vdsc_cfg->dsc_version_minor =
1495                 min(intel_dp_source_dsc_version_minor(intel_dp),
1496                     intel_dp_sink_dsc_version_minor(intel_dp));
1497         if (vdsc_cfg->convert_rgb)
1498                 vdsc_cfg->convert_rgb =
1499                         intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1500                         DP_DSC_RGB;
1501
1502         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1503         if (!line_buf_depth) {
1504                 drm_dbg_kms(&i915->drm,
1505                             "DSC Sink Line Buffer Depth invalid\n");
1506                 return -EINVAL;
1507         }
1508
1509         if (vdsc_cfg->dsc_version_minor == 2)
1510                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1511                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1512         else
1513                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1514                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1515
1516         vdsc_cfg->block_pred_enable =
1517                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1518                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1519
1520         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1521 }
1522
1523 static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
1524                                          enum intel_output_format output_format)
1525 {
1526         u8 sink_dsc_format;
1527
1528         switch (output_format) {
1529         case INTEL_OUTPUT_FORMAT_RGB:
1530                 sink_dsc_format = DP_DSC_RGB;
1531                 break;
1532         case INTEL_OUTPUT_FORMAT_YCBCR444:
1533                 sink_dsc_format = DP_DSC_YCbCr444;
1534                 break;
1535         case INTEL_OUTPUT_FORMAT_YCBCR420:
1536                 if (min(intel_dp_source_dsc_version_minor(intel_dp),
1537                         intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
1538                         return false;
1539                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1540                 break;
1541         default:
1542                 return false;
1543         }
1544
1545         return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
1546 }
1547
1548 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1549                                 struct intel_crtc_state *pipe_config,
1550                                 struct drm_connector_state *conn_state,
1551                                 struct link_config_limits *limits,
1552                                 int timeslots,
1553                                 bool compute_pipe_bpp)
1554 {
1555         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1556         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1557         const struct drm_display_mode *adjusted_mode =
1558                 &pipe_config->hw.adjusted_mode;
1559         int pipe_bpp;
1560         int ret;
1561
1562         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1563                 intel_dp_supports_fec(intel_dp, pipe_config);
1564
1565         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1566                 return -EINVAL;
1567
1568         if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
1569                 return -EINVAL;
1570
1571         if (compute_pipe_bpp)
1572                 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1573         else
1574                 pipe_bpp = pipe_config->pipe_bpp;
1575
1576         if (intel_dp->force_dsc_bpc) {
1577                 pipe_bpp = intel_dp->force_dsc_bpc * 3;
1578                 drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
1579         }
1580
1581         /* Min Input BPC for ICL+ is 8 */
1582         if (pipe_bpp < 8 * 3) {
1583                 drm_dbg_kms(&dev_priv->drm,
1584                             "No DSC support for less than 8bpc\n");
1585                 return -EINVAL;
1586         }
1587
1588         /*
1589          * For now enable DSC for max bpp, max link rate, max lane count.
1590          * Optimize this later for the minimum possible link rate/lane count
1591          * with DSC enabled for the requested mode.
1592          */
1593         pipe_config->pipe_bpp = pipe_bpp;
1594         pipe_config->port_clock = limits->max_rate;
1595         pipe_config->lane_count = limits->max_lane_count;
1596
1597         if (intel_dp_is_edp(intel_dp)) {
1598                 pipe_config->dsc.compressed_bpp =
1599                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1600                               pipe_config->pipe_bpp);
1601                 pipe_config->dsc.slice_count =
1602                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1603                                                         true);
1604                 if (!pipe_config->dsc.slice_count) {
1605                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
1606                                     pipe_config->dsc.slice_count);
1607                         return -EINVAL;
1608                 }
1609         } else {
1610                 u16 dsc_max_output_bpp = 0;
1611                 u8 dsc_dp_slice_count;
1612
1613                 if (compute_pipe_bpp) {
1614                         dsc_max_output_bpp =
1615                                 intel_dp_dsc_get_output_bpp(dev_priv,
1616                                                             pipe_config->port_clock,
1617                                                             pipe_config->lane_count,
1618                                                             adjusted_mode->crtc_clock,
1619                                                             adjusted_mode->crtc_hdisplay,
1620                                                             pipe_config->bigjoiner_pipes,
1621                                                             pipe_bpp,
1622                                                             timeslots);
1623                         /*
1624                          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
1625                          * supported PPS value can be 63.9375 and with the further
1626                          * mention that bpp should be programmed double the target bpp
1627                          * restricting our target bpp to be 31.9375 at max
1628                          */
1629                         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1630                                 dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
1631
1632                         if (!dsc_max_output_bpp) {
1633                                 drm_dbg_kms(&dev_priv->drm,
1634                                             "Compressed BPP not supported\n");
1635                                 return -EINVAL;
1636                         }
1637                 }
1638                 dsc_dp_slice_count =
1639                         intel_dp_dsc_get_slice_count(intel_dp,
1640                                                      adjusted_mode->crtc_clock,
1641                                                      adjusted_mode->crtc_hdisplay,
1642                                                      pipe_config->bigjoiner_pipes);
1643                 if (!dsc_dp_slice_count) {
1644                         drm_dbg_kms(&dev_priv->drm,
1645                                     "Compressed Slice Count not supported\n");
1646                         return -EINVAL;
1647                 }
1648
1649                 /*
1650                  * compute pipe bpp is set to false for DP MST DSC case
1651                  * and compressed_bpp is calculated same time once
1652                  * vpci timeslots are allocated, because overall bpp
1653                  * calculation procedure is bit different for MST case.
1654                  */
1655                 if (compute_pipe_bpp) {
1656                         pipe_config->dsc.compressed_bpp = min_t(u16,
1657                                                                 dsc_max_output_bpp >> 4,
1658                                                                 pipe_config->pipe_bpp);
1659                 }
1660                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1661                 drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
1662                             pipe_config->dsc.compressed_bpp,
1663                             pipe_config->dsc.slice_count);
1664         }
1665         /*
1666          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1667          * is greater than the maximum Cdclock and if slice count is even
1668          * then we need to use 2 VDSC instances.
1669          */
1670         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
1671                 pipe_config->dsc.dsc_split = true;
1672
1673         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1674         if (ret < 0) {
1675                 drm_dbg_kms(&dev_priv->drm,
1676                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1677                             "Compressed BPP = %d\n",
1678                             pipe_config->pipe_bpp,
1679                             pipe_config->dsc.compressed_bpp);
1680                 return ret;
1681         }
1682
1683         pipe_config->dsc.compression_enable = true;
1684         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1685                     "Compressed Bpp = %d Slice Count = %d\n",
1686                     pipe_config->pipe_bpp,
1687                     pipe_config->dsc.compressed_bpp,
1688                     pipe_config->dsc.slice_count);
1689
1690         return 0;
1691 }
1692
1693 static int
1694 intel_dp_compute_link_config(struct intel_encoder *encoder,
1695                              struct intel_crtc_state *pipe_config,
1696                              struct drm_connector_state *conn_state,
1697                              bool respect_downstream_limits)
1698 {
1699         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1700         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1701         const struct drm_display_mode *adjusted_mode =
1702                 &pipe_config->hw.adjusted_mode;
1703         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1704         struct link_config_limits limits;
1705         bool joiner_needs_dsc = false;
1706         int ret;
1707
1708         limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1709         limits.max_rate = intel_dp_max_link_rate(intel_dp);
1710
1711         limits.min_lane_count = 1;
1712         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1713
1714         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1715         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1716
1717         if (intel_dp->use_max_params) {
1718                 /*
1719                  * Use the maximum clock and number of lanes the eDP panel
1720                  * advertizes being capable of in case the initial fast
1721                  * optimal params failed us. The panels are generally
1722                  * designed to support only a single clock and lane
1723                  * configuration, and typically on older panels these
1724                  * values correspond to the native resolution of the panel.
1725                  */
1726                 limits.min_lane_count = limits.max_lane_count;
1727                 limits.min_rate = limits.max_rate;
1728         }
1729
1730         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1731
1732         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1733                     "max rate %d max bpp %d pixel clock %iKHz\n",
1734                     limits.max_lane_count, limits.max_rate,
1735                     limits.max_bpp, adjusted_mode->crtc_clock);
1736
1737         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1738                                     adjusted_mode->crtc_clock))
1739                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1740
1741         /*
1742          * Pipe joiner needs compression up to display 12 due to bandwidth
1743          * limitation. DG2 onwards pipe joiner can be enabled without
1744          * compression.
1745          */
1746         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1747
1748         /*
1749          * Optimize for slow and wide for everything, because there are some
1750          * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1751          */
1752         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
1753
1754         if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1755                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1756                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1757                             str_yes_no(intel_dp->force_dsc_en));
1758                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1759                                                   conn_state, &limits, 64, true);
1760                 if (ret < 0)
1761                         return ret;
1762         }
1763
1764         if (pipe_config->dsc.compression_enable) {
1765                 drm_dbg_kms(&i915->drm,
1766                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1767                             pipe_config->lane_count, pipe_config->port_clock,
1768                             pipe_config->pipe_bpp,
1769                             pipe_config->dsc.compressed_bpp);
1770
1771                 drm_dbg_kms(&i915->drm,
1772                             "DP link rate required %i available %i\n",
1773                             intel_dp_link_required(adjusted_mode->crtc_clock,
1774                                                    pipe_config->dsc.compressed_bpp),
1775                             intel_dp_max_data_rate(pipe_config->port_clock,
1776                                                    pipe_config->lane_count));
1777         } else {
1778                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1779                             pipe_config->lane_count, pipe_config->port_clock,
1780                             pipe_config->pipe_bpp);
1781
1782                 drm_dbg_kms(&i915->drm,
1783                             "DP link rate required %i available %i\n",
1784                             intel_dp_link_required(adjusted_mode->crtc_clock,
1785                                                    pipe_config->pipe_bpp),
1786                             intel_dp_max_data_rate(pipe_config->port_clock,
1787                                                    pipe_config->lane_count));
1788         }
1789         return 0;
1790 }
1791
1792 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1793                                   const struct drm_connector_state *conn_state)
1794 {
1795         const struct intel_digital_connector_state *intel_conn_state =
1796                 to_intel_digital_connector_state(conn_state);
1797         const struct drm_display_mode *adjusted_mode =
1798                 &crtc_state->hw.adjusted_mode;
1799
1800         /*
1801          * Our YCbCr output is always limited range.
1802          * crtc_state->limited_color_range only applies to RGB,
1803          * and it must never be set for YCbCr or we risk setting
1804          * some conflicting bits in TRANSCONF which will mess up
1805          * the colors on the monitor.
1806          */
1807         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1808                 return false;
1809
1810         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1811                 /*
1812                  * See:
1813                  * CEA-861-E - 5.1 Default Encoding Parameters
1814                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1815                  */
1816                 return crtc_state->pipe_bpp != 18 &&
1817                         drm_default_rgb_quant_range(adjusted_mode) ==
1818                         HDMI_QUANTIZATION_RANGE_LIMITED;
1819         } else {
1820                 return intel_conn_state->broadcast_rgb ==
1821                         INTEL_BROADCAST_RGB_LIMITED;
1822         }
1823 }
1824
1825 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1826                                     enum port port)
1827 {
1828         if (IS_G4X(dev_priv))
1829                 return false;
1830         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1831                 return false;
1832
1833         return true;
1834 }
1835
1836 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1837                                              const struct drm_connector_state *conn_state,
1838                                              struct drm_dp_vsc_sdp *vsc)
1839 {
1840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1841         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1842
1843         /*
1844          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1845          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1846          * Colorimetry Format indication.
1847          */
1848         vsc->revision = 0x5;
1849         vsc->length = 0x13;
1850
1851         /* DP 1.4a spec, Table 2-120 */
1852         switch (crtc_state->output_format) {
1853         case INTEL_OUTPUT_FORMAT_YCBCR444:
1854                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1855                 break;
1856         case INTEL_OUTPUT_FORMAT_YCBCR420:
1857                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1858                 break;
1859         case INTEL_OUTPUT_FORMAT_RGB:
1860         default:
1861                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1862         }
1863
1864         switch (conn_state->colorspace) {
1865         case DRM_MODE_COLORIMETRY_BT709_YCC:
1866                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1867                 break;
1868         case DRM_MODE_COLORIMETRY_XVYCC_601:
1869                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1870                 break;
1871         case DRM_MODE_COLORIMETRY_XVYCC_709:
1872                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1873                 break;
1874         case DRM_MODE_COLORIMETRY_SYCC_601:
1875                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1876                 break;
1877         case DRM_MODE_COLORIMETRY_OPYCC_601:
1878                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1879                 break;
1880         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1881                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1882                 break;
1883         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1884                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1885                 break;
1886         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1887                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1888                 break;
1889         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1890         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1891                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1892                 break;
1893         default:
1894                 /*
1895                  * RGB->YCBCR color conversion uses the BT.709
1896                  * color space.
1897                  */
1898                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1899                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1900                 else
1901                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1902                 break;
1903         }
1904
1905         vsc->bpc = crtc_state->pipe_bpp / 3;
1906
1907         /* only RGB pixelformat supports 6 bpc */
1908         drm_WARN_ON(&dev_priv->drm,
1909                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1910
1911         /* all YCbCr are always limited range */
1912         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1913         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1914 }
1915
1916 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1917                                      struct intel_crtc_state *crtc_state,
1918                                      const struct drm_connector_state *conn_state)
1919 {
1920         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1921
1922         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1923         if (crtc_state->has_psr)
1924                 return;
1925
1926         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1927                 return;
1928
1929         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1930         vsc->sdp_type = DP_SDP_VSC;
1931         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1932                                          &crtc_state->infoframes.vsc);
1933 }
1934
1935 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1936                                   const struct intel_crtc_state *crtc_state,
1937                                   const struct drm_connector_state *conn_state,
1938                                   struct drm_dp_vsc_sdp *vsc)
1939 {
1940         vsc->sdp_type = DP_SDP_VSC;
1941
1942         if (crtc_state->has_psr2) {
1943                 if (intel_dp->psr.colorimetry_support &&
1944                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1945                         /* [PSR2, +Colorimetry] */
1946                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1947                                                          vsc);
1948                 } else {
1949                         /*
1950                          * [PSR2, -Colorimetry]
1951                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1952                          * 3D stereo + PSR/PSR2 + Y-coordinate.
1953                          */
1954                         vsc->revision = 0x4;
1955                         vsc->length = 0xe;
1956                 }
1957         } else {
1958                 /*
1959                  * [PSR1]
1960                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1961                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1962                  * higher).
1963                  */
1964                 vsc->revision = 0x2;
1965                 vsc->length = 0x8;
1966         }
1967 }
1968
1969 static void
1970 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1971                                             struct intel_crtc_state *crtc_state,
1972                                             const struct drm_connector_state *conn_state)
1973 {
1974         int ret;
1975         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1976         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1977
1978         if (!conn_state->hdr_output_metadata)
1979                 return;
1980
1981         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1982
1983         if (ret) {
1984                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1985                 return;
1986         }
1987
1988         crtc_state->infoframes.enable |=
1989                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1990 }
1991
1992 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
1993                                     enum transcoder cpu_transcoder)
1994 {
1995         if (HAS_DOUBLE_BUFFERED_M_N(i915))
1996                 return true;
1997
1998         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
1999 }
2000
2001 static bool can_enable_drrs(struct intel_connector *connector,
2002                             const struct intel_crtc_state *pipe_config,
2003                             const struct drm_display_mode *downclock_mode)
2004 {
2005         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2006
2007         if (pipe_config->vrr.enable)
2008                 return false;
2009
2010         /*
2011          * DRRS and PSR can't be enable together, so giving preference to PSR
2012          * as it allows more power-savings by complete shutting down display,
2013          * so to guarantee this, intel_drrs_compute_config() must be called
2014          * after intel_psr_compute_config().
2015          */
2016         if (pipe_config->has_psr)
2017                 return false;
2018
2019         /* FIXME missing FDI M2/N2 etc. */
2020         if (pipe_config->has_pch_encoder)
2021                 return false;
2022
2023         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2024                 return false;
2025
2026         return downclock_mode &&
2027                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2028 }
2029
2030 static void
2031 intel_dp_drrs_compute_config(struct intel_connector *connector,
2032                              struct intel_crtc_state *pipe_config,
2033                              int output_bpp)
2034 {
2035         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2036         const struct drm_display_mode *downclock_mode =
2037                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2038         int pixel_clock;
2039
2040         if (has_seamless_m_n(connector))
2041                 pipe_config->seamless_m_n = true;
2042
2043         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2044                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2045                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2046                 return;
2047         }
2048
2049         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2050                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2051
2052         pipe_config->has_drrs = true;
2053
2054         pixel_clock = downclock_mode->clock;
2055         if (pipe_config->splitter.enable)
2056                 pixel_clock /= pipe_config->splitter.link_count;
2057
2058         intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
2059                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2060                                pipe_config->fec_enable);
2061
2062         /* FIXME: abstract this better */
2063         if (pipe_config->splitter.enable)
2064                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2065 }
2066
2067 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2068                                const struct drm_connector_state *conn_state)
2069 {
2070         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2071         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2072         const struct intel_digital_connector_state *intel_conn_state =
2073                 to_intel_digital_connector_state(conn_state);
2074
2075         if (!intel_dp_port_has_audio(i915, encoder->port))
2076                 return false;
2077
2078         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2079                 return intel_dp->has_audio;
2080         else
2081                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2082 }
2083
2084 static int
2085 intel_dp_compute_output_format(struct intel_encoder *encoder,
2086                                struct intel_crtc_state *crtc_state,
2087                                struct drm_connector_state *conn_state,
2088                                bool respect_downstream_limits)
2089 {
2090         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2091         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2092         struct intel_connector *connector = intel_dp->attached_connector;
2093         const struct drm_display_info *info = &connector->base.display_info;
2094         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2095         bool ycbcr_420_only;
2096         int ret;
2097
2098         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2099
2100         crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
2101
2102         if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
2103                 drm_dbg_kms(&i915->drm,
2104                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2105                 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2106         }
2107
2108         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2109                                            respect_downstream_limits);
2110         if (ret) {
2111                 if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
2112                     !connector->base.ycbcr_420_allowed ||
2113                     !drm_mode_is_420_also(info, adjusted_mode))
2114                         return ret;
2115
2116                 crtc_state->output_format = intel_dp_output_format(connector, true);
2117                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2118                                                    respect_downstream_limits);
2119         }
2120
2121         return ret;
2122 }
2123
2124 static void
2125 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2126                               struct intel_crtc_state *pipe_config,
2127                               struct drm_connector_state *conn_state)
2128 {
2129         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2130         struct drm_connector *connector = conn_state->connector;
2131
2132         pipe_config->sdp_split_enable =
2133                 intel_dp_has_audio(encoder, conn_state) &&
2134                 intel_dp_is_uhbr(pipe_config);
2135
2136         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
2137                     connector->base.id, connector->name,
2138                     str_yes_no(pipe_config->sdp_split_enable));
2139 }
2140
2141 int
2142 intel_dp_compute_config(struct intel_encoder *encoder,
2143                         struct intel_crtc_state *pipe_config,
2144                         struct drm_connector_state *conn_state)
2145 {
2146         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2147         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2148         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2149         const struct drm_display_mode *fixed_mode;
2150         struct intel_connector *connector = intel_dp->attached_connector;
2151         int ret = 0, output_bpp;
2152
2153         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2154                 pipe_config->has_pch_encoder = true;
2155
2156         pipe_config->has_audio =
2157                 intel_dp_has_audio(encoder, conn_state) &&
2158                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2159
2160         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2161         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2162                 ret = intel_panel_compute_config(connector, adjusted_mode);
2163                 if (ret)
2164                         return ret;
2165         }
2166
2167         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2168                 return -EINVAL;
2169
2170         if (!connector->base.interlace_allowed &&
2171             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2172                 return -EINVAL;
2173
2174         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2175                 return -EINVAL;
2176
2177         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2178                 return -EINVAL;
2179
2180         /*
2181          * Try to respect downstream TMDS clock limits first, if
2182          * that fails assume the user might know something we don't.
2183          */
2184         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2185         if (ret)
2186                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2187         if (ret)
2188                 return ret;
2189
2190         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2191             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2192                 ret = intel_panel_fitting(pipe_config, conn_state);
2193                 if (ret)
2194                         return ret;
2195         }
2196
2197         pipe_config->limited_color_range =
2198                 intel_dp_limited_color_range(pipe_config, conn_state);
2199
2200         if (pipe_config->dsc.compression_enable)
2201                 output_bpp = pipe_config->dsc.compressed_bpp;
2202         else
2203                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2204                                                  pipe_config->pipe_bpp);
2205
2206         if (intel_dp->mso_link_count) {
2207                 int n = intel_dp->mso_link_count;
2208                 int overlap = intel_dp->mso_pixel_overlap;
2209
2210                 pipe_config->splitter.enable = true;
2211                 pipe_config->splitter.link_count = n;
2212                 pipe_config->splitter.pixel_overlap = overlap;
2213
2214                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2215                             n, overlap);
2216
2217                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2218                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2219                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2220                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2221                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2222                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2223                 adjusted_mode->crtc_clock /= n;
2224         }
2225
2226         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2227
2228         intel_link_compute_m_n(output_bpp,
2229                                pipe_config->lane_count,
2230                                adjusted_mode->crtc_clock,
2231                                pipe_config->port_clock,
2232                                &pipe_config->dp_m_n,
2233                                pipe_config->fec_enable);
2234
2235         /* FIXME: abstract this better */
2236         if (pipe_config->splitter.enable)
2237                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2238
2239         if (!HAS_DDI(dev_priv))
2240                 g4x_dp_set_clock(encoder, pipe_config);
2241
2242         intel_vrr_compute_config(pipe_config, conn_state);
2243         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2244         intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2245         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2246         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2247
2248         return 0;
2249 }
2250
2251 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2252                               int link_rate, int lane_count)
2253 {
2254         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2255         intel_dp->link_trained = false;
2256         intel_dp->link_rate = link_rate;
2257         intel_dp->lane_count = lane_count;
2258 }
2259
2260 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2261 {
2262         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2263         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2264 }
2265
2266 /* Enable backlight PWM and backlight PP control. */
2267 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2268                             const struct drm_connector_state *conn_state)
2269 {
2270         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2271         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2272
2273         if (!intel_dp_is_edp(intel_dp))
2274                 return;
2275
2276         drm_dbg_kms(&i915->drm, "\n");
2277
2278         intel_backlight_enable(crtc_state, conn_state);
2279         intel_pps_backlight_on(intel_dp);
2280 }
2281
2282 /* Disable backlight PP control and backlight PWM. */
2283 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2284 {
2285         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2286         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2287
2288         if (!intel_dp_is_edp(intel_dp))
2289                 return;
2290
2291         drm_dbg_kms(&i915->drm, "\n");
2292
2293         intel_pps_backlight_off(intel_dp);
2294         intel_backlight_disable(old_conn_state);
2295 }
2296
2297 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2298 {
2299         /*
2300          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2301          * be capable of signalling downstream hpd with a long pulse.
2302          * Whether or not that means D3 is safe to use is not clear,
2303          * but let's assume so until proven otherwise.
2304          *
2305          * FIXME should really check all downstream ports...
2306          */
2307         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2308                 drm_dp_is_branch(intel_dp->dpcd) &&
2309                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2310 }
2311
2312 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2313                                            const struct intel_crtc_state *crtc_state,
2314                                            bool enable)
2315 {
2316         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2317         int ret;
2318
2319         if (!crtc_state->dsc.compression_enable)
2320                 return;
2321
2322         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2323                                  enable ? DP_DECOMPRESSION_EN : 0);
2324         if (ret < 0)
2325                 drm_dbg_kms(&i915->drm,
2326                             "Failed to %s sink decompression state\n",
2327                             str_enable_disable(enable));
2328 }
2329
2330 static void
2331 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2332 {
2333         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2334         u8 oui[] = { 0x00, 0xaa, 0x01 };
2335         u8 buf[3] = { 0 };
2336
2337         /*
2338          * During driver init, we want to be careful and avoid changing the source OUI if it's
2339          * already set to what we want, so as to avoid clearing any state by accident
2340          */
2341         if (careful) {
2342                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2343                         drm_err(&i915->drm, "Failed to read source OUI\n");
2344
2345                 if (memcmp(oui, buf, sizeof(oui)) == 0)
2346                         return;
2347         }
2348
2349         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2350                 drm_err(&i915->drm, "Failed to write source OUI\n");
2351
2352         intel_dp->last_oui_write = jiffies;
2353 }
2354
2355 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2356 {
2357         struct intel_connector *connector = intel_dp->attached_connector;
2358         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2359
2360         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
2361                     connector->base.base.id, connector->base.name,
2362                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2363
2364         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
2365                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2366 }
2367
2368 /* If the device supports it, try to set the power state appropriately */
2369 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2370 {
2371         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2372         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2373         int ret, i;
2374
2375         /* Should have a valid DPCD by this point */
2376         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2377                 return;
2378
2379         if (mode != DP_SET_POWER_D0) {
2380                 if (downstream_hpd_needs_d0(intel_dp))
2381                         return;
2382
2383                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2384         } else {
2385                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2386
2387                 lspcon_resume(dp_to_dig_port(intel_dp));
2388
2389                 /* Write the source OUI as early as possible */
2390                 if (intel_dp_is_edp(intel_dp))
2391                         intel_edp_init_source_oui(intel_dp, false);
2392
2393                 /*
2394                  * When turning on, we need to retry for 1ms to give the sink
2395                  * time to wake up.
2396                  */
2397                 for (i = 0; i < 3; i++) {
2398                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2399                         if (ret == 1)
2400                                 break;
2401                         msleep(1);
2402                 }
2403
2404                 if (ret == 1 && lspcon->active)
2405                         lspcon_wait_pcon_mode(lspcon);
2406         }
2407
2408         if (ret != 1)
2409                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2410                             encoder->base.base.id, encoder->base.name,
2411                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
2412 }
2413
2414 static bool
2415 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2416
2417 /**
2418  * intel_dp_sync_state - sync the encoder state during init/resume
2419  * @encoder: intel encoder to sync
2420  * @crtc_state: state for the CRTC connected to the encoder
2421  *
2422  * Sync any state stored in the encoder wrt. HW state during driver init
2423  * and system resume.
2424  */
2425 void intel_dp_sync_state(struct intel_encoder *encoder,
2426                          const struct intel_crtc_state *crtc_state)
2427 {
2428         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2429
2430         if (!crtc_state)
2431                 return;
2432
2433         /*
2434          * Don't clobber DPCD if it's been already read out during output
2435          * setup (eDP) or detect.
2436          */
2437         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2438                 intel_dp_get_dpcd(intel_dp);
2439
2440         intel_dp_reset_max_link_params(intel_dp);
2441 }
2442
2443 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2444                                     struct intel_crtc_state *crtc_state)
2445 {
2446         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2447         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2448         bool fastset = true;
2449
2450         /*
2451          * If BIOS has set an unsupported or non-standard link rate for some
2452          * reason force an encoder recompute and full modeset.
2453          */
2454         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2455                                 crtc_state->port_clock) < 0) {
2456                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
2457                             encoder->base.base.id, encoder->base.name);
2458                 crtc_state->uapi.connectors_changed = true;
2459                 fastset = false;
2460         }
2461
2462         /*
2463          * FIXME hack to force full modeset when DSC is being used.
2464          *
2465          * As long as we do not have full state readout and config comparison
2466          * of crtc_state->dsc, we have no way to ensure reliable fastset.
2467          * Remove once we have readout for DSC.
2468          */
2469         if (crtc_state->dsc.compression_enable) {
2470                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
2471                             encoder->base.base.id, encoder->base.name);
2472                 crtc_state->uapi.mode_changed = true;
2473                 fastset = false;
2474         }
2475
2476         if (CAN_PSR(intel_dp)) {
2477                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
2478                             encoder->base.base.id, encoder->base.name);
2479                 crtc_state->uapi.mode_changed = true;
2480                 fastset = false;
2481         }
2482
2483         return fastset;
2484 }
2485
2486 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2487 {
2488         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2489
2490         /* Clear the cached register set to avoid using stale values */
2491
2492         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2493
2494         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2495                              intel_dp->pcon_dsc_dpcd,
2496                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2497                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2498                         DP_PCON_DSC_ENCODER);
2499
2500         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2501                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2502 }
2503
2504 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2505 {
2506         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2507         int i;
2508
2509         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2510                 if (frl_bw_mask & (1 << i))
2511                         return bw_gbps[i];
2512         }
2513         return 0;
2514 }
2515
2516 static int intel_dp_pcon_set_frl_mask(int max_frl)
2517 {
2518         switch (max_frl) {
2519         case 48:
2520                 return DP_PCON_FRL_BW_MASK_48GBPS;
2521         case 40:
2522                 return DP_PCON_FRL_BW_MASK_40GBPS;
2523         case 32:
2524                 return DP_PCON_FRL_BW_MASK_32GBPS;
2525         case 24:
2526                 return DP_PCON_FRL_BW_MASK_24GBPS;
2527         case 18:
2528                 return DP_PCON_FRL_BW_MASK_18GBPS;
2529         case 9:
2530                 return DP_PCON_FRL_BW_MASK_9GBPS;
2531         }
2532
2533         return 0;
2534 }
2535
2536 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2537 {
2538         struct intel_connector *intel_connector = intel_dp->attached_connector;
2539         struct drm_connector *connector = &intel_connector->base;
2540         int max_frl_rate;
2541         int max_lanes, rate_per_lane;
2542         int max_dsc_lanes, dsc_rate_per_lane;
2543
2544         max_lanes = connector->display_info.hdmi.max_lanes;
2545         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2546         max_frl_rate = max_lanes * rate_per_lane;
2547
2548         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2549                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2550                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2551                 if (max_dsc_lanes && dsc_rate_per_lane)
2552                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2553         }
2554
2555         return max_frl_rate;
2556 }
2557
2558 static bool
2559 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2560                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
2561 {
2562         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2563             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2564             *frl_trained_mask >= max_frl_bw_mask)
2565                 return true;
2566
2567         return false;
2568 }
2569
2570 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2571 {
2572 #define TIMEOUT_FRL_READY_MS 500
2573 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2574
2575         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2576         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2577         u8 max_frl_bw_mask = 0, frl_trained_mask;
2578         bool is_active;
2579
2580         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2581         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2582
2583         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2584         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2585
2586         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2587
2588         if (max_frl_bw <= 0)
2589                 return -EINVAL;
2590
2591         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2592         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2593
2594         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2595                 goto frl_trained;
2596
2597         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2598         if (ret < 0)
2599                 return ret;
2600         /* Wait for PCON to be FRL Ready */
2601         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2602
2603         if (!is_active)
2604                 return -ETIMEDOUT;
2605
2606         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2607                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2608         if (ret < 0)
2609                 return ret;
2610         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2611                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2612         if (ret < 0)
2613                 return ret;
2614         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2615         if (ret < 0)
2616                 return ret;
2617         /*
2618          * Wait for FRL to be completed
2619          * Check if the HDMI Link is up and active.
2620          */
2621         wait_for(is_active =
2622                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2623                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
2624
2625         if (!is_active)
2626                 return -ETIMEDOUT;
2627
2628 frl_trained:
2629         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2630         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2631         intel_dp->frl.is_trained = true;
2632         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2633
2634         return 0;
2635 }
2636
2637 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2638 {
2639         if (drm_dp_is_branch(intel_dp->dpcd) &&
2640             intel_dp->has_hdmi_sink &&
2641             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2642                 return true;
2643
2644         return false;
2645 }
2646
2647 static
2648 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2649 {
2650         int ret;
2651         u8 buf = 0;
2652
2653         /* Set PCON source control mode */
2654         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2655
2656         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2657         if (ret < 0)
2658                 return ret;
2659
2660         /* Set HDMI LINK ENABLE */
2661         buf |= DP_PCON_ENABLE_HDMI_LINK;
2662         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2663         if (ret < 0)
2664                 return ret;
2665
2666         return 0;
2667 }
2668
2669 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2670 {
2671         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2672
2673         /*
2674          * Always go for FRL training if:
2675          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2676          * -sink is HDMI2.1
2677          */
2678         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2679             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2680             intel_dp->frl.is_trained)
2681                 return;
2682
2683         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2684                 int ret, mode;
2685
2686                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2687                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2688                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2689
2690                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2691                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2692         } else {
2693                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2694         }
2695 }
2696
2697 static int
2698 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2699 {
2700         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2701
2702         return intel_hdmi_dsc_get_slice_height(vactive);
2703 }
2704
2705 static int
2706 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2707                              const struct intel_crtc_state *crtc_state)
2708 {
2709         struct intel_connector *intel_connector = intel_dp->attached_connector;
2710         struct drm_connector *connector = &intel_connector->base;
2711         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2712         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2713         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2714         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2715
2716         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2717                                              pcon_max_slice_width,
2718                                              hdmi_max_slices, hdmi_throughput);
2719 }
2720
2721 static int
2722 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2723                           const struct intel_crtc_state *crtc_state,
2724                           int num_slices, int slice_width)
2725 {
2726         struct intel_connector *intel_connector = intel_dp->attached_connector;
2727         struct drm_connector *connector = &intel_connector->base;
2728         int output_format = crtc_state->output_format;
2729         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2730         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2731         int hdmi_max_chunk_bytes =
2732                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2733
2734         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2735                                       num_slices, output_format, hdmi_all_bpp,
2736                                       hdmi_max_chunk_bytes);
2737 }
2738
2739 void
2740 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2741                             const struct intel_crtc_state *crtc_state)
2742 {
2743         u8 pps_param[6];
2744         int slice_height;
2745         int slice_width;
2746         int num_slices;
2747         int bits_per_pixel;
2748         int ret;
2749         struct intel_connector *intel_connector = intel_dp->attached_connector;
2750         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2751         struct drm_connector *connector;
2752         bool hdmi_is_dsc_1_2;
2753
2754         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2755                 return;
2756
2757         if (!intel_connector)
2758                 return;
2759         connector = &intel_connector->base;
2760         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2761
2762         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2763             !hdmi_is_dsc_1_2)
2764                 return;
2765
2766         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2767         if (!slice_height)
2768                 return;
2769
2770         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2771         if (!num_slices)
2772                 return;
2773
2774         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2775                                    num_slices);
2776
2777         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2778                                                    num_slices, slice_width);
2779         if (!bits_per_pixel)
2780                 return;
2781
2782         pps_param[0] = slice_height & 0xFF;
2783         pps_param[1] = slice_height >> 8;
2784         pps_param[2] = slice_width & 0xFF;
2785         pps_param[3] = slice_width >> 8;
2786         pps_param[4] = bits_per_pixel & 0xFF;
2787         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2788
2789         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2790         if (ret < 0)
2791                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2792 }
2793
2794 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2795                                            const struct intel_crtc_state *crtc_state)
2796 {
2797         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2798         u8 tmp;
2799
2800         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2801                 return;
2802
2803         if (!drm_dp_is_branch(intel_dp->dpcd))
2804                 return;
2805
2806         tmp = intel_dp->has_hdmi_sink ?
2807                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2808
2809         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2810                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2811                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2812                             str_enable_disable(intel_dp->has_hdmi_sink));
2813
2814         tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2815                 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2816
2817         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2818                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2819                 drm_dbg_kms(&i915->drm,
2820                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2821                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2822
2823         tmp = intel_dp->dfp.rgb_to_ycbcr ?
2824                 DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2825
2826         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2827                 drm_dbg_kms(&i915->drm,
2828                            "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2829                            str_enable_disable(tmp));
2830 }
2831
2832 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2833 {
2834         u8 dprx = 0;
2835
2836         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2837                               &dprx) != 1)
2838                 return false;
2839         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2840 }
2841
2842 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2843 {
2844         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2845
2846         /*
2847          * Clear the cached register set to avoid using stale values
2848          * for the sinks that do not support DSC.
2849          */
2850         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2851
2852         /* Clear fec_capable to avoid using stale values */
2853         intel_dp->fec_capable = 0;
2854
2855         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2856         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2857             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2858                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2859                                      intel_dp->dsc_dpcd,
2860                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2861                         drm_err(&i915->drm,
2862                                 "Failed to read DPCD register 0x%x\n",
2863                                 DP_DSC_SUPPORT);
2864
2865                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2866                             (int)sizeof(intel_dp->dsc_dpcd),
2867                             intel_dp->dsc_dpcd);
2868
2869                 /* FEC is supported only on DP 1.4 */
2870                 if (!intel_dp_is_edp(intel_dp) &&
2871                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2872                                       &intel_dp->fec_capable) < 0)
2873                         drm_err(&i915->drm,
2874                                 "Failed to read FEC DPCD register\n");
2875
2876                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2877                             intel_dp->fec_capable);
2878         }
2879 }
2880
2881 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2882                                      struct drm_display_mode *mode)
2883 {
2884         struct intel_dp *intel_dp = intel_attached_dp(connector);
2885         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2886         int n = intel_dp->mso_link_count;
2887         int overlap = intel_dp->mso_pixel_overlap;
2888
2889         if (!mode || !n)
2890                 return;
2891
2892         mode->hdisplay = (mode->hdisplay - overlap) * n;
2893         mode->hsync_start = (mode->hsync_start - overlap) * n;
2894         mode->hsync_end = (mode->hsync_end - overlap) * n;
2895         mode->htotal = (mode->htotal - overlap) * n;
2896         mode->clock *= n;
2897
2898         drm_mode_set_name(mode);
2899
2900         drm_dbg_kms(&i915->drm,
2901                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
2902                     connector->base.base.id, connector->base.name,
2903                     DRM_MODE_ARG(mode));
2904 }
2905
2906 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
2907 {
2908         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2909         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2910         struct intel_connector *connector = intel_dp->attached_connector;
2911
2912         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
2913                 /*
2914                  * This is a big fat ugly hack.
2915                  *
2916                  * Some machines in UEFI boot mode provide us a VBT that has 18
2917                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2918                  * unknown we fail to light up. Yet the same BIOS boots up with
2919                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2920                  * max, not what it tells us to use.
2921                  *
2922                  * Note: This will still be broken if the eDP panel is not lit
2923                  * up by the BIOS, and thus we can't get the mode at module
2924                  * load.
2925                  */
2926                 drm_dbg_kms(&dev_priv->drm,
2927                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2928                             pipe_bpp, connector->panel.vbt.edp.bpp);
2929                 connector->panel.vbt.edp.bpp = pipe_bpp;
2930         }
2931 }
2932
2933 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2934 {
2935         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2936         struct intel_connector *connector = intel_dp->attached_connector;
2937         struct drm_display_info *info = &connector->base.display_info;
2938         u8 mso;
2939
2940         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2941                 return;
2942
2943         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2944                 drm_err(&i915->drm, "Failed to read MSO cap\n");
2945                 return;
2946         }
2947
2948         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2949         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2950         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2951                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2952                 mso = 0;
2953         }
2954
2955         if (mso) {
2956                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
2957                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
2958                             info->mso_pixel_overlap);
2959                 if (!HAS_MSO(i915)) {
2960                         drm_err(&i915->drm, "No source MSO support, disabling\n");
2961                         mso = 0;
2962                 }
2963         }
2964
2965         intel_dp->mso_link_count = mso;
2966         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
2967 }
2968
2969 static bool
2970 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2971 {
2972         struct drm_i915_private *dev_priv =
2973                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2974
2975         /* this function is meant to be called only once */
2976         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2977
2978         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2979                 return false;
2980
2981         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2982                          drm_dp_is_branch(intel_dp->dpcd));
2983
2984         /*
2985          * Read the eDP display control registers.
2986          *
2987          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2988          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2989          * set, but require eDP 1.4+ detection (e.g. for supported link rates
2990          * method). The display control registers should read zero if they're
2991          * not supported anyway.
2992          */
2993         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2994                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2995                              sizeof(intel_dp->edp_dpcd)) {
2996                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2997                             (int)sizeof(intel_dp->edp_dpcd),
2998                             intel_dp->edp_dpcd);
2999
3000                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3001         }
3002
3003         /*
3004          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3005          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3006          */
3007         intel_psr_init_dpcd(intel_dp);
3008
3009         /* Clear the default sink rates */
3010         intel_dp->num_sink_rates = 0;
3011
3012         /* Read the eDP 1.4+ supported link rates. */
3013         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3014                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3015                 int i;
3016
3017                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3018                                 sink_rates, sizeof(sink_rates));
3019
3020                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3021                         int val = le16_to_cpu(sink_rates[i]);
3022
3023                         if (val == 0)
3024                                 break;
3025
3026                         /* Value read multiplied by 200kHz gives the per-lane
3027                          * link rate in kHz. The source rates are, however,
3028                          * stored in terms of LS_Clk kHz. The full conversion
3029                          * back to symbols is
3030                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3031                          */
3032                         intel_dp->sink_rates[i] = (val * 200) / 10;
3033                 }
3034                 intel_dp->num_sink_rates = i;
3035         }
3036
3037         /*
3038          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3039          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3040          */
3041         if (intel_dp->num_sink_rates)
3042                 intel_dp->use_rate_select = true;
3043         else
3044                 intel_dp_set_sink_rates(intel_dp);
3045         intel_dp_set_max_sink_lane_count(intel_dp);
3046
3047         /* Read the eDP DSC DPCD registers */
3048         if (HAS_DSC(dev_priv))
3049                 intel_dp_get_dsc_sink_cap(intel_dp);
3050
3051         /*
3052          * If needed, program our source OUI so we can make various Intel-specific AUX services
3053          * available (such as HDR backlight controls)
3054          */
3055         intel_edp_init_source_oui(intel_dp, true);
3056
3057         return true;
3058 }
3059
3060 static bool
3061 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3062 {
3063         if (!intel_dp->attached_connector)
3064                 return false;
3065
3066         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3067                                           intel_dp->dpcd,
3068                                           &intel_dp->desc);
3069 }
3070
3071 static bool
3072 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3073 {
3074         int ret;
3075
3076         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3077                 return false;
3078
3079         /*
3080          * Don't clobber cached eDP rates. Also skip re-reading
3081          * the OUI/ID since we know it won't change.
3082          */
3083         if (!intel_dp_is_edp(intel_dp)) {
3084                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3085                                  drm_dp_is_branch(intel_dp->dpcd));
3086
3087                 intel_dp_set_sink_rates(intel_dp);
3088                 intel_dp_set_max_sink_lane_count(intel_dp);
3089                 intel_dp_set_common_rates(intel_dp);
3090         }
3091
3092         if (intel_dp_has_sink_count(intel_dp)) {
3093                 ret = drm_dp_read_sink_count(&intel_dp->aux);
3094                 if (ret < 0)
3095                         return false;
3096
3097                 /*
3098                  * Sink count can change between short pulse hpd hence
3099                  * a member variable in intel_dp will track any changes
3100                  * between short pulse interrupts.
3101                  */
3102                 intel_dp->sink_count = ret;
3103
3104                 /*
3105                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3106                  * a dongle is present but no display. Unless we require to know
3107                  * if a dongle is present or not, we don't need to update
3108                  * downstream port information. So, an early return here saves
3109                  * time from performing other operations which are not required.
3110                  */
3111                 if (!intel_dp->sink_count)
3112                         return false;
3113         }
3114
3115         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
3116                                            intel_dp->downstream_ports) == 0;
3117 }
3118
3119 static bool
3120 intel_dp_can_mst(struct intel_dp *intel_dp)
3121 {
3122         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3123
3124         return i915->params.enable_dp_mst &&
3125                 intel_dp_mst_source_support(intel_dp) &&
3126                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3127 }
3128
3129 static void
3130 intel_dp_configure_mst(struct intel_dp *intel_dp)
3131 {
3132         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3133         struct intel_encoder *encoder =
3134                 &dp_to_dig_port(intel_dp)->base;
3135         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3136
3137         drm_dbg_kms(&i915->drm,
3138                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3139                     encoder->base.base.id, encoder->base.name,
3140                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
3141                     str_yes_no(sink_can_mst),
3142                     str_yes_no(i915->params.enable_dp_mst));
3143
3144         if (!intel_dp_mst_source_support(intel_dp))
3145                 return;
3146
3147         intel_dp->is_mst = sink_can_mst &&
3148                 i915->params.enable_dp_mst;
3149
3150         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3151                                         intel_dp->is_mst);
3152 }
3153
3154 static bool
3155 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3156 {
3157         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3158 }
3159
3160 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3161 {
3162         int retry;
3163
3164         for (retry = 0; retry < 3; retry++) {
3165                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3166                                       &esi[1], 3) == 3)
3167                         return true;
3168         }
3169
3170         return false;
3171 }
3172
3173 bool
3174 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3175                        const struct drm_connector_state *conn_state)
3176 {
3177         /*
3178          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3179          * of Color Encoding Format and Content Color Gamut], in order to
3180          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3181          */
3182         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3183                 return true;
3184
3185         switch (conn_state->colorspace) {
3186         case DRM_MODE_COLORIMETRY_SYCC_601:
3187         case DRM_MODE_COLORIMETRY_OPYCC_601:
3188         case DRM_MODE_COLORIMETRY_BT2020_YCC:
3189         case DRM_MODE_COLORIMETRY_BT2020_RGB:
3190         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3191                 return true;
3192         default:
3193                 break;
3194         }
3195
3196         return false;
3197 }
3198
3199 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3200                                      struct dp_sdp *sdp, size_t size)
3201 {
3202         size_t length = sizeof(struct dp_sdp);
3203
3204         if (size < length)
3205                 return -ENOSPC;
3206
3207         memset(sdp, 0, size);
3208
3209         /*
3210          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3211          * VSC SDP Header Bytes
3212          */
3213         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3214         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3215         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3216         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3217
3218         /*
3219          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3220          * per DP 1.4a spec.
3221          */
3222         if (vsc->revision != 0x5)
3223                 goto out;
3224
3225         /* VSC SDP Payload for DB16 through DB18 */
3226         /* Pixel Encoding and Colorimetry Formats  */
3227         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3228         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3229
3230         switch (vsc->bpc) {
3231         case 6:
3232                 /* 6bpc: 0x0 */
3233                 break;
3234         case 8:
3235                 sdp->db[17] = 0x1; /* DB17[3:0] */
3236                 break;
3237         case 10:
3238                 sdp->db[17] = 0x2;
3239                 break;
3240         case 12:
3241                 sdp->db[17] = 0x3;
3242                 break;
3243         case 16:
3244                 sdp->db[17] = 0x4;
3245                 break;
3246         default:
3247                 MISSING_CASE(vsc->bpc);
3248                 break;
3249         }
3250         /* Dynamic Range and Component Bit Depth */
3251         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3252                 sdp->db[17] |= 0x80;  /* DB17[7] */
3253
3254         /* Content Type */
3255         sdp->db[18] = vsc->content_type & 0x7;
3256
3257 out:
3258         return length;
3259 }
3260
3261 static ssize_t
3262 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3263                                          const struct hdmi_drm_infoframe *drm_infoframe,
3264                                          struct dp_sdp *sdp,
3265                                          size_t size)
3266 {
3267         size_t length = sizeof(struct dp_sdp);
3268         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3269         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3270         ssize_t len;
3271
3272         if (size < length)
3273                 return -ENOSPC;
3274
3275         memset(sdp, 0, size);
3276
3277         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3278         if (len < 0) {
3279                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3280                 return -ENOSPC;
3281         }
3282
3283         if (len != infoframe_size) {
3284                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3285                 return -ENOSPC;
3286         }
3287
3288         /*
3289          * Set up the infoframe sdp packet for HDR static metadata.
3290          * Prepare VSC Header for SU as per DP 1.4a spec,
3291          * Table 2-100 and Table 2-101
3292          */
3293
3294         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3295         sdp->sdp_header.HB0 = 0;
3296         /*
3297          * Packet Type 80h + Non-audio INFOFRAME Type value
3298          * HDMI_INFOFRAME_TYPE_DRM: 0x87
3299          * - 80h + Non-audio INFOFRAME Type value
3300          * - InfoFrame Type: 0x07
3301          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3302          */
3303         sdp->sdp_header.HB1 = drm_infoframe->type;
3304         /*
3305          * Least Significant Eight Bits of (Data Byte Count – 1)
3306          * infoframe_size - 1
3307          */
3308         sdp->sdp_header.HB2 = 0x1D;
3309         /* INFOFRAME SDP Version Number */
3310         sdp->sdp_header.HB3 = (0x13 << 2);
3311         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3312         sdp->db[0] = drm_infoframe->version;
3313         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3314         sdp->db[1] = drm_infoframe->length;
3315         /*
3316          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3317          * HDMI_INFOFRAME_HEADER_SIZE
3318          */
3319         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3320         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3321                HDMI_DRM_INFOFRAME_SIZE);
3322
3323         /*
3324          * Size of DP infoframe sdp packet for HDR static metadata consists of
3325          * - DP SDP Header(struct dp_sdp_header): 4 bytes
3326          * - Two Data Blocks: 2 bytes
3327          *    CTA Header Byte2 (INFOFRAME Version Number)
3328          *    CTA Header Byte3 (Length of INFOFRAME)
3329          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3330          *
3331          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3332          * infoframe size. But GEN11+ has larger than that size, write_infoframe
3333          * will pad rest of the size.
3334          */
3335         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3336 }
3337
3338 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3339                                const struct intel_crtc_state *crtc_state,
3340                                unsigned int type)
3341 {
3342         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3343         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3344         struct dp_sdp sdp = {};
3345         ssize_t len;
3346
3347         if ((crtc_state->infoframes.enable &
3348              intel_hdmi_infoframe_enable(type)) == 0)
3349                 return;
3350
3351         switch (type) {
3352         case DP_SDP_VSC:
3353                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3354                                             sizeof(sdp));
3355                 break;
3356         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3357                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3358                                                                &crtc_state->infoframes.drm.drm,
3359                                                                &sdp, sizeof(sdp));
3360                 break;
3361         default:
3362                 MISSING_CASE(type);
3363                 return;
3364         }
3365
3366         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3367                 return;
3368
3369         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3370 }
3371
3372 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3373                             const struct intel_crtc_state *crtc_state,
3374                             const struct drm_dp_vsc_sdp *vsc)
3375 {
3376         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3377         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3378         struct dp_sdp sdp = {};
3379         ssize_t len;
3380
3381         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3382
3383         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3384                 return;
3385
3386         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3387                                         &sdp, len);
3388 }
3389
3390 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3391                              bool enable,
3392                              const struct intel_crtc_state *crtc_state,
3393                              const struct drm_connector_state *conn_state)
3394 {
3395         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3396         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3397         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3398                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3399                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3400         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3401
3402         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3403         /* When PSR is enabled, this routine doesn't disable VSC DIP */
3404         if (!crtc_state->has_psr)
3405                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3406
3407         intel_de_write(dev_priv, reg, val);
3408         intel_de_posting_read(dev_priv, reg);
3409
3410         if (!enable)
3411                 return;
3412
3413         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3414         if (!crtc_state->has_psr)
3415                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3416
3417         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3418 }
3419
3420 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3421                                    const void *buffer, size_t size)
3422 {
3423         const struct dp_sdp *sdp = buffer;
3424
3425         if (size < sizeof(struct dp_sdp))
3426                 return -EINVAL;
3427
3428         memset(vsc, 0, sizeof(*vsc));
3429
3430         if (sdp->sdp_header.HB0 != 0)
3431                 return -EINVAL;
3432
3433         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3434                 return -EINVAL;
3435
3436         vsc->sdp_type = sdp->sdp_header.HB1;
3437         vsc->revision = sdp->sdp_header.HB2;
3438         vsc->length = sdp->sdp_header.HB3;
3439
3440         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3441             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3442                 /*
3443                  * - HB2 = 0x2, HB3 = 0x8
3444                  *   VSC SDP supporting 3D stereo + PSR
3445                  * - HB2 = 0x4, HB3 = 0xe
3446                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3447                  *   first scan line of the SU region (applies to eDP v1.4b
3448                  *   and higher).
3449                  */
3450                 return 0;
3451         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3452                 /*
3453                  * - HB2 = 0x5, HB3 = 0x13
3454                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3455                  *   Format.
3456                  */
3457                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3458                 vsc->colorimetry = sdp->db[16] & 0xf;
3459                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3460
3461                 switch (sdp->db[17] & 0x7) {
3462                 case 0x0:
3463                         vsc->bpc = 6;
3464                         break;
3465                 case 0x1:
3466                         vsc->bpc = 8;
3467                         break;
3468                 case 0x2:
3469                         vsc->bpc = 10;
3470                         break;
3471                 case 0x3:
3472                         vsc->bpc = 12;
3473                         break;
3474                 case 0x4:
3475                         vsc->bpc = 16;
3476                         break;
3477                 default:
3478                         MISSING_CASE(sdp->db[17] & 0x7);
3479                         return -EINVAL;
3480                 }
3481
3482                 vsc->content_type = sdp->db[18] & 0x7;
3483         } else {
3484                 return -EINVAL;
3485         }
3486
3487         return 0;
3488 }
3489
3490 static int
3491 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3492                                            const void *buffer, size_t size)
3493 {
3494         int ret;
3495
3496         const struct dp_sdp *sdp = buffer;
3497
3498         if (size < sizeof(struct dp_sdp))
3499                 return -EINVAL;
3500
3501         if (sdp->sdp_header.HB0 != 0)
3502                 return -EINVAL;
3503
3504         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3505                 return -EINVAL;
3506
3507         /*
3508          * Least Significant Eight Bits of (Data Byte Count – 1)
3509          * 1Dh (i.e., Data Byte Count = 30 bytes).
3510          */
3511         if (sdp->sdp_header.HB2 != 0x1D)
3512                 return -EINVAL;
3513
3514         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3515         if ((sdp->sdp_header.HB3 & 0x3) != 0)
3516                 return -EINVAL;
3517
3518         /* INFOFRAME SDP Version Number */
3519         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3520                 return -EINVAL;
3521
3522         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3523         if (sdp->db[0] != 1)
3524                 return -EINVAL;
3525
3526         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3527         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3528                 return -EINVAL;
3529
3530         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3531                                              HDMI_DRM_INFOFRAME_SIZE);
3532
3533         return ret;
3534 }
3535
3536 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3537                                   struct intel_crtc_state *crtc_state,
3538                                   struct drm_dp_vsc_sdp *vsc)
3539 {
3540         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3541         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3542         unsigned int type = DP_SDP_VSC;
3543         struct dp_sdp sdp = {};
3544         int ret;
3545
3546         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3547         if (crtc_state->has_psr)
3548                 return;
3549
3550         if ((crtc_state->infoframes.enable &
3551              intel_hdmi_infoframe_enable(type)) == 0)
3552                 return;
3553
3554         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3555
3556         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3557
3558         if (ret)
3559                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3560 }
3561
3562 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3563                                                      struct intel_crtc_state *crtc_state,
3564                                                      struct hdmi_drm_infoframe *drm_infoframe)
3565 {
3566         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3567         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3568         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3569         struct dp_sdp sdp = {};
3570         int ret;
3571
3572         if ((crtc_state->infoframes.enable &
3573             intel_hdmi_infoframe_enable(type)) == 0)
3574                 return;
3575
3576         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3577                                  sizeof(sdp));
3578
3579         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3580                                                          sizeof(sdp));
3581
3582         if (ret)
3583                 drm_dbg_kms(&dev_priv->drm,
3584                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3585 }
3586
3587 void intel_read_dp_sdp(struct intel_encoder *encoder,
3588                        struct intel_crtc_state *crtc_state,
3589                        unsigned int type)
3590 {
3591         switch (type) {
3592         case DP_SDP_VSC:
3593                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3594                                       &crtc_state->infoframes.vsc);
3595                 break;
3596         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3597                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3598                                                          &crtc_state->infoframes.drm.drm);
3599                 break;
3600         default:
3601                 MISSING_CASE(type);
3602                 break;
3603         }
3604 }
3605
3606 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3607 {
3608         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3609         int status = 0;
3610         int test_link_rate;
3611         u8 test_lane_count, test_link_bw;
3612         /* (DP CTS 1.2)
3613          * 4.3.1.11
3614          */
3615         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3616         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3617                                    &test_lane_count);
3618
3619         if (status <= 0) {
3620                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3621                 return DP_TEST_NAK;
3622         }
3623         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3624
3625         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3626                                    &test_link_bw);
3627         if (status <= 0) {
3628                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3629                 return DP_TEST_NAK;
3630         }
3631         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3632
3633         /* Validate the requested link rate and lane count */
3634         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3635                                         test_lane_count))
3636                 return DP_TEST_NAK;
3637
3638         intel_dp->compliance.test_lane_count = test_lane_count;
3639         intel_dp->compliance.test_link_rate = test_link_rate;
3640
3641         return DP_TEST_ACK;
3642 }
3643
3644 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3645 {
3646         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3647         u8 test_pattern;
3648         u8 test_misc;
3649         __be16 h_width, v_height;
3650         int status = 0;
3651
3652         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3653         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3654                                    &test_pattern);
3655         if (status <= 0) {
3656                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3657                 return DP_TEST_NAK;
3658         }
3659         if (test_pattern != DP_COLOR_RAMP)
3660                 return DP_TEST_NAK;
3661
3662         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3663                                   &h_width, 2);
3664         if (status <= 0) {
3665                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3666                 return DP_TEST_NAK;
3667         }
3668
3669         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3670                                   &v_height, 2);
3671         if (status <= 0) {
3672                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3673                 return DP_TEST_NAK;
3674         }
3675
3676         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3677                                    &test_misc);
3678         if (status <= 0) {
3679                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3680                 return DP_TEST_NAK;
3681         }
3682         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3683                 return DP_TEST_NAK;
3684         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3685                 return DP_TEST_NAK;
3686         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3687         case DP_TEST_BIT_DEPTH_6:
3688                 intel_dp->compliance.test_data.bpc = 6;
3689                 break;
3690         case DP_TEST_BIT_DEPTH_8:
3691                 intel_dp->compliance.test_data.bpc = 8;
3692                 break;
3693         default:
3694                 return DP_TEST_NAK;
3695         }
3696
3697         intel_dp->compliance.test_data.video_pattern = test_pattern;
3698         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3699         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3700         /* Set test active flag here so userspace doesn't interrupt things */
3701         intel_dp->compliance.test_active = true;
3702
3703         return DP_TEST_ACK;
3704 }
3705
3706 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3707 {
3708         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3709         u8 test_result = DP_TEST_ACK;
3710         struct intel_connector *intel_connector = intel_dp->attached_connector;
3711         struct drm_connector *connector = &intel_connector->base;
3712
3713         if (intel_connector->detect_edid == NULL ||
3714             connector->edid_corrupt ||
3715             intel_dp->aux.i2c_defer_count > 6) {
3716                 /* Check EDID read for NACKs, DEFERs and corruption
3717                  * (DP CTS 1.2 Core r1.1)
3718                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3719                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3720                  *    4.2.2.6 : EDID corruption detected
3721                  * Use failsafe mode for all cases
3722                  */
3723                 if (intel_dp->aux.i2c_nack_count > 0 ||
3724                         intel_dp->aux.i2c_defer_count > 0)
3725                         drm_dbg_kms(&i915->drm,
3726                                     "EDID read had %d NACKs, %d DEFERs\n",
3727                                     intel_dp->aux.i2c_nack_count,
3728                                     intel_dp->aux.i2c_defer_count);
3729                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3730         } else {
3731                 /* FIXME: Get rid of drm_edid_raw() */
3732                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
3733
3734                 /* We have to write the checksum of the last block read */
3735                 block += block->extensions;
3736
3737                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3738                                        block->checksum) <= 0)
3739                         drm_dbg_kms(&i915->drm,
3740                                     "Failed to write EDID checksum\n");
3741
3742                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3743                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3744         }
3745
3746         /* Set test active flag here so userspace doesn't interrupt things */
3747         intel_dp->compliance.test_active = true;
3748
3749         return test_result;
3750 }
3751
3752 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3753                                         const struct intel_crtc_state *crtc_state)
3754 {
3755         struct drm_i915_private *dev_priv =
3756                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3757         struct drm_dp_phy_test_params *data =
3758                         &intel_dp->compliance.test_data.phytest;
3759         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3760         enum pipe pipe = crtc->pipe;
3761         u32 pattern_val;
3762
3763         switch (data->phy_pattern) {
3764         case DP_PHY_TEST_PATTERN_NONE:
3765                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3766                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3767                 break;
3768         case DP_PHY_TEST_PATTERN_D10_2:
3769                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3770                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3771                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3772                 break;
3773         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3774                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3775                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3776                                DDI_DP_COMP_CTL_ENABLE |
3777                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3778                 break;
3779         case DP_PHY_TEST_PATTERN_PRBS7:
3780                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3781                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3782                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3783                 break;
3784         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3785                 /*
3786                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3787                  * current firmware of DPR-100 could not set it, so hardcoding
3788                  * now for complaince test.
3789                  */
3790                 drm_dbg_kms(&dev_priv->drm,
3791                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3792                 pattern_val = 0x3e0f83e0;
3793                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3794                 pattern_val = 0x0f83e0f8;
3795                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3796                 pattern_val = 0x0000f83e;
3797                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3798                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3799                                DDI_DP_COMP_CTL_ENABLE |
3800                                DDI_DP_COMP_CTL_CUSTOM80);
3801                 break;
3802         case DP_PHY_TEST_PATTERN_CP2520:
3803                 /*
3804                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3805                  * current firmware of DPR-100 could not set it, so hardcoding
3806                  * now for complaince test.
3807                  */
3808                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3809                 pattern_val = 0xFB;
3810                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3811                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3812                                pattern_val);
3813                 break;
3814         default:
3815                 WARN(1, "Invalid Phy Test Pattern\n");
3816         }
3817 }
3818
3819 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3820                                          const struct intel_crtc_state *crtc_state)
3821 {
3822         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3823         struct drm_dp_phy_test_params *data =
3824                 &intel_dp->compliance.test_data.phytest;
3825         u8 link_status[DP_LINK_STATUS_SIZE];
3826
3827         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3828                                              link_status) < 0) {
3829                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3830                 return;
3831         }
3832
3833         /* retrieve vswing & pre-emphasis setting */
3834         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3835                                   link_status);
3836
3837         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3838
3839         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3840
3841         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3842                           intel_dp->train_set, crtc_state->lane_count);
3843
3844         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3845                                     link_status[DP_DPCD_REV]);
3846 }
3847
3848 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3849 {
3850         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3851         struct drm_dp_phy_test_params *data =
3852                 &intel_dp->compliance.test_data.phytest;
3853
3854         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3855                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3856                 return DP_TEST_NAK;
3857         }
3858
3859         /* Set test active flag here so userspace doesn't interrupt things */
3860         intel_dp->compliance.test_active = true;
3861
3862         return DP_TEST_ACK;
3863 }
3864
3865 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3866 {
3867         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3868         u8 response = DP_TEST_NAK;
3869         u8 request = 0;
3870         int status;
3871
3872         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3873         if (status <= 0) {
3874                 drm_dbg_kms(&i915->drm,
3875                             "Could not read test request from sink\n");
3876                 goto update_status;
3877         }
3878
3879         switch (request) {
3880         case DP_TEST_LINK_TRAINING:
3881                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3882                 response = intel_dp_autotest_link_training(intel_dp);
3883                 break;
3884         case DP_TEST_LINK_VIDEO_PATTERN:
3885                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3886                 response = intel_dp_autotest_video_pattern(intel_dp);
3887                 break;
3888         case DP_TEST_LINK_EDID_READ:
3889                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3890                 response = intel_dp_autotest_edid(intel_dp);
3891                 break;
3892         case DP_TEST_LINK_PHY_TEST_PATTERN:
3893                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3894                 response = intel_dp_autotest_phy_pattern(intel_dp);
3895                 break;
3896         default:
3897                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3898                             request);
3899                 break;
3900         }
3901
3902         if (response & DP_TEST_ACK)
3903                 intel_dp->compliance.test_type = request;
3904
3905 update_status:
3906         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3907         if (status <= 0)
3908                 drm_dbg_kms(&i915->drm,
3909                             "Could not write test response to sink\n");
3910 }
3911
3912 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
3913                              u8 link_status[DP_LINK_STATUS_SIZE])
3914 {
3915         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3916         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3917         bool uhbr = intel_dp->link_rate >= 1000000;
3918         bool ok;
3919
3920         if (uhbr)
3921                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
3922                                                           intel_dp->lane_count);
3923         else
3924                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3925
3926         if (ok)
3927                 return true;
3928
3929         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
3930         drm_dbg_kms(&i915->drm,
3931                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
3932                     encoder->base.base.id, encoder->base.name,
3933                     uhbr ? "128b/132b" : "8b/10b");
3934
3935         return false;
3936 }
3937
3938 static void
3939 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
3940 {
3941         bool handled = false;
3942
3943         drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3944         if (handled)
3945                 ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3946
3947         if (esi[1] & DP_CP_IRQ) {
3948                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3949                 ack[1] |= DP_CP_IRQ;
3950         }
3951 }
3952
3953 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3954 {
3955         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3956         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3957         u8 link_status[DP_LINK_STATUS_SIZE] = {};
3958         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3959
3960         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3961                              esi_link_status_size) != esi_link_status_size) {
3962                 drm_err(&i915->drm,
3963                         "[ENCODER:%d:%s] Failed to read link status\n",
3964                         encoder->base.base.id, encoder->base.name);
3965                 return false;
3966         }
3967
3968         return intel_dp_link_ok(intel_dp, link_status);
3969 }
3970
3971 /**
3972  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3973  * @intel_dp: Intel DP struct
3974  *
3975  * Read any pending MST interrupts, call MST core to handle these and ack the
3976  * interrupts. Check if the main and AUX link state is ok.
3977  *
3978  * Returns:
3979  * - %true if pending interrupts were serviced (or no interrupts were
3980  *   pending) w/o detecting an error condition.
3981  * - %false if an error condition - like AUX failure or a loss of link - is
3982  *   detected, which needs servicing from the hotplug work.
3983  */
3984 static bool
3985 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3986 {
3987         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3988         bool link_ok = true;
3989
3990         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3991
3992         for (;;) {
3993                 u8 esi[4] = {};
3994                 u8 ack[4] = {};
3995
3996                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3997                         drm_dbg_kms(&i915->drm,
3998                                     "failed to get ESI - device may have failed\n");
3999                         link_ok = false;
4000
4001                         break;
4002                 }
4003
4004                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4005
4006                 if (intel_dp->active_mst_links > 0 && link_ok &&
4007                     esi[3] & LINK_STATUS_CHANGED) {
4008                         if (!intel_dp_mst_link_status(intel_dp))
4009                                 link_ok = false;
4010                         ack[3] |= LINK_STATUS_CHANGED;
4011                 }
4012
4013                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4014
4015                 if (!memchr_inv(ack, 0, sizeof(ack)))
4016                         break;
4017
4018                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4019                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4020         }
4021
4022         return link_ok;
4023 }
4024
4025 static void
4026 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4027 {
4028         bool is_active;
4029         u8 buf = 0;
4030
4031         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4032         if (intel_dp->frl.is_trained && !is_active) {
4033                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4034                         return;
4035
4036                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4037                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4038                         return;
4039
4040                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4041
4042                 intel_dp->frl.is_trained = false;
4043
4044                 /* Restart FRL training or fall back to TMDS mode */
4045                 intel_dp_check_frl_training(intel_dp);
4046         }
4047 }
4048
4049 static bool
4050 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4051 {
4052         u8 link_status[DP_LINK_STATUS_SIZE];
4053
4054         if (!intel_dp->link_trained)
4055                 return false;
4056
4057         /*
4058          * While PSR source HW is enabled, it will control main-link sending
4059          * frames, enabling and disabling it so trying to do a retrain will fail
4060          * as the link would or not be on or it could mix training patterns
4061          * and frame data at the same time causing retrain to fail.
4062          * Also when exiting PSR, HW will retrain the link anyways fixing
4063          * any link status error.
4064          */
4065         if (intel_psr_enabled(intel_dp))
4066                 return false;
4067
4068         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4069                                              link_status) < 0)
4070                 return false;
4071
4072         /*
4073          * Validate the cached values of intel_dp->link_rate and
4074          * intel_dp->lane_count before attempting to retrain.
4075          *
4076          * FIXME would be nice to user the crtc state here, but since
4077          * we need to call this from the short HPD handler that seems
4078          * a bit hard.
4079          */
4080         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4081                                         intel_dp->lane_count))
4082                 return false;
4083
4084         /* Retrain if link not ok */
4085         return !intel_dp_link_ok(intel_dp, link_status);
4086 }
4087
4088 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4089                                    const struct drm_connector_state *conn_state)
4090 {
4091         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4092         struct intel_encoder *encoder;
4093         enum pipe pipe;
4094
4095         if (!conn_state->best_encoder)
4096                 return false;
4097
4098         /* SST */
4099         encoder = &dp_to_dig_port(intel_dp)->base;
4100         if (conn_state->best_encoder == &encoder->base)
4101                 return true;
4102
4103         /* MST */
4104         for_each_pipe(i915, pipe) {
4105                 encoder = &intel_dp->mst_encoders[pipe]->base;
4106                 if (conn_state->best_encoder == &encoder->base)
4107                         return true;
4108         }
4109
4110         return false;
4111 }
4112
4113 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
4114                                       struct drm_modeset_acquire_ctx *ctx,
4115                                       u8 *pipe_mask)
4116 {
4117         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4118         struct drm_connector_list_iter conn_iter;
4119         struct intel_connector *connector;
4120         int ret = 0;
4121
4122         *pipe_mask = 0;
4123
4124         if (!intel_dp_needs_link_retrain(intel_dp))
4125                 return 0;
4126
4127         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4128         for_each_intel_connector_iter(connector, &conn_iter) {
4129                 struct drm_connector_state *conn_state =
4130                         connector->base.state;
4131                 struct intel_crtc_state *crtc_state;
4132                 struct intel_crtc *crtc;
4133
4134                 if (!intel_dp_has_connector(intel_dp, conn_state))
4135                         continue;
4136
4137                 crtc = to_intel_crtc(conn_state->crtc);
4138                 if (!crtc)
4139                         continue;
4140
4141                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4142                 if (ret)
4143                         break;
4144
4145                 crtc_state = to_intel_crtc_state(crtc->base.state);
4146
4147                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4148
4149                 if (!crtc_state->hw.active)
4150                         continue;
4151
4152                 if (conn_state->commit &&
4153                     !try_wait_for_completion(&conn_state->commit->hw_done))
4154                         continue;
4155
4156                 *pipe_mask |= BIT(crtc->pipe);
4157         }
4158         drm_connector_list_iter_end(&conn_iter);
4159
4160         if (!intel_dp_needs_link_retrain(intel_dp))
4161                 *pipe_mask = 0;
4162
4163         return ret;
4164 }
4165
4166 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4167 {
4168         struct intel_connector *connector = intel_dp->attached_connector;
4169
4170         return connector->base.status == connector_status_connected ||
4171                 intel_dp->is_mst;
4172 }
4173
4174 int intel_dp_retrain_link(struct intel_encoder *encoder,
4175                           struct drm_modeset_acquire_ctx *ctx)
4176 {
4177         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4178         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4179         struct intel_crtc *crtc;
4180         u8 pipe_mask;
4181         int ret;
4182
4183         if (!intel_dp_is_connected(intel_dp))
4184                 return 0;
4185
4186         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4187                                ctx);
4188         if (ret)
4189                 return ret;
4190
4191         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask);
4192         if (ret)
4193                 return ret;
4194
4195         if (pipe_mask == 0)
4196                 return 0;
4197
4198         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4199                     encoder->base.base.id, encoder->base.name);
4200
4201         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4202                 const struct intel_crtc_state *crtc_state =
4203                         to_intel_crtc_state(crtc->base.state);
4204
4205                 /* Suppress underruns caused by re-training */
4206                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4207                 if (crtc_state->has_pch_encoder)
4208                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4209                                                               intel_crtc_pch_transcoder(crtc), false);
4210         }
4211
4212         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4213                 const struct intel_crtc_state *crtc_state =
4214                         to_intel_crtc_state(crtc->base.state);
4215
4216                 /* retrain on the MST master transcoder */
4217                 if (DISPLAY_VER(dev_priv) >= 12 &&
4218                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4219                     !intel_dp_mst_is_master_trans(crtc_state))
4220                         continue;
4221
4222                 intel_dp_check_frl_training(intel_dp);
4223                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4224                 intel_dp_start_link_train(intel_dp, crtc_state);
4225                 intel_dp_stop_link_train(intel_dp, crtc_state);
4226                 break;
4227         }
4228
4229         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4230                 const struct intel_crtc_state *crtc_state =
4231                         to_intel_crtc_state(crtc->base.state);
4232
4233                 /* Keep underrun reporting disabled until things are stable */
4234                 intel_crtc_wait_for_next_vblank(crtc);
4235
4236                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4237                 if (crtc_state->has_pch_encoder)
4238                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4239                                                               intel_crtc_pch_transcoder(crtc), true);
4240         }
4241
4242         return 0;
4243 }
4244
4245 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4246                                   struct drm_modeset_acquire_ctx *ctx,
4247                                   u8 *pipe_mask)
4248 {
4249         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4250         struct drm_connector_list_iter conn_iter;
4251         struct intel_connector *connector;
4252         int ret = 0;
4253
4254         *pipe_mask = 0;
4255
4256         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4257         for_each_intel_connector_iter(connector, &conn_iter) {
4258                 struct drm_connector_state *conn_state =
4259                         connector->base.state;
4260                 struct intel_crtc_state *crtc_state;
4261                 struct intel_crtc *crtc;
4262
4263                 if (!intel_dp_has_connector(intel_dp, conn_state))
4264                         continue;
4265
4266                 crtc = to_intel_crtc(conn_state->crtc);
4267                 if (!crtc)
4268                         continue;
4269
4270                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4271                 if (ret)
4272                         break;
4273
4274                 crtc_state = to_intel_crtc_state(crtc->base.state);
4275
4276                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4277
4278                 if (!crtc_state->hw.active)
4279                         continue;
4280
4281                 if (conn_state->commit &&
4282                     !try_wait_for_completion(&conn_state->commit->hw_done))
4283                         continue;
4284
4285                 *pipe_mask |= BIT(crtc->pipe);
4286         }
4287         drm_connector_list_iter_end(&conn_iter);
4288
4289         return ret;
4290 }
4291
4292 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4293                                 struct drm_modeset_acquire_ctx *ctx)
4294 {
4295         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4296         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4297         struct intel_crtc *crtc;
4298         u8 pipe_mask;
4299         int ret;
4300
4301         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4302                                ctx);
4303         if (ret)
4304                 return ret;
4305
4306         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4307         if (ret)
4308                 return ret;
4309
4310         if (pipe_mask == 0)
4311                 return 0;
4312
4313         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4314                     encoder->base.base.id, encoder->base.name);
4315
4316         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4317                 const struct intel_crtc_state *crtc_state =
4318                         to_intel_crtc_state(crtc->base.state);
4319
4320                 /* test on the MST master transcoder */
4321                 if (DISPLAY_VER(dev_priv) >= 12 &&
4322                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4323                     !intel_dp_mst_is_master_trans(crtc_state))
4324                         continue;
4325
4326                 intel_dp_process_phy_request(intel_dp, crtc_state);
4327                 break;
4328         }
4329
4330         return 0;
4331 }
4332
4333 void intel_dp_phy_test(struct intel_encoder *encoder)
4334 {
4335         struct drm_modeset_acquire_ctx ctx;
4336         int ret;
4337
4338         drm_modeset_acquire_init(&ctx, 0);
4339
4340         for (;;) {
4341                 ret = intel_dp_do_phy_test(encoder, &ctx);
4342
4343                 if (ret == -EDEADLK) {
4344                         drm_modeset_backoff(&ctx);
4345                         continue;
4346                 }
4347
4348                 break;
4349         }
4350
4351         drm_modeset_drop_locks(&ctx);
4352         drm_modeset_acquire_fini(&ctx);
4353         drm_WARN(encoder->base.dev, ret,
4354                  "Acquiring modeset locks failed with %i\n", ret);
4355 }
4356
4357 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4358 {
4359         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4360         u8 val;
4361
4362         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4363                 return;
4364
4365         if (drm_dp_dpcd_readb(&intel_dp->aux,
4366                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4367                 return;
4368
4369         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4370
4371         if (val & DP_AUTOMATED_TEST_REQUEST)
4372                 intel_dp_handle_test_request(intel_dp);
4373
4374         if (val & DP_CP_IRQ)
4375                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4376
4377         if (val & DP_SINK_SPECIFIC_IRQ)
4378                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4379 }
4380
4381 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4382 {
4383         u8 val;
4384
4385         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4386                 return;
4387
4388         if (drm_dp_dpcd_readb(&intel_dp->aux,
4389                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4390                 return;
4391
4392         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4393                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4394                 return;
4395
4396         if (val & HDMI_LINK_STATUS_CHANGED)
4397                 intel_dp_handle_hdmi_link_status_change(intel_dp);
4398 }
4399
4400 /*
4401  * According to DP spec
4402  * 5.1.2:
4403  *  1. Read DPCD
4404  *  2. Configure link according to Receiver Capabilities
4405  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4406  *  4. Check link status on receipt of hot-plug interrupt
4407  *
4408  * intel_dp_short_pulse -  handles short pulse interrupts
4409  * when full detection is not required.
4410  * Returns %true if short pulse is handled and full detection
4411  * is NOT required and %false otherwise.
4412  */
4413 static bool
4414 intel_dp_short_pulse(struct intel_dp *intel_dp)
4415 {
4416         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4417         u8 old_sink_count = intel_dp->sink_count;
4418         bool ret;
4419
4420         /*
4421          * Clearing compliance test variables to allow capturing
4422          * of values for next automated test request.
4423          */
4424         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4425
4426         /*
4427          * Now read the DPCD to see if it's actually running
4428          * If the current value of sink count doesn't match with
4429          * the value that was stored earlier or dpcd read failed
4430          * we need to do full detection
4431          */
4432         ret = intel_dp_get_dpcd(intel_dp);
4433
4434         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4435                 /* No need to proceed if we are going to do full detect */
4436                 return false;
4437         }
4438
4439         intel_dp_check_device_service_irq(intel_dp);
4440         intel_dp_check_link_service_irq(intel_dp);
4441
4442         /* Handle CEC interrupts, if any */
4443         drm_dp_cec_irq(&intel_dp->aux);
4444
4445         /* defer to the hotplug work for link retraining if needed */
4446         if (intel_dp_needs_link_retrain(intel_dp))
4447                 return false;
4448
4449         intel_psr_short_pulse(intel_dp);
4450
4451         switch (intel_dp->compliance.test_type) {
4452         case DP_TEST_LINK_TRAINING:
4453                 drm_dbg_kms(&dev_priv->drm,
4454                             "Link Training Compliance Test requested\n");
4455                 /* Send a Hotplug Uevent to userspace to start modeset */
4456                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4457                 break;
4458         case DP_TEST_LINK_PHY_TEST_PATTERN:
4459                 drm_dbg_kms(&dev_priv->drm,
4460                             "PHY test pattern Compliance Test requested\n");
4461                 /*
4462                  * Schedule long hpd to do the test
4463                  *
4464                  * FIXME get rid of the ad-hoc phy test modeset code
4465                  * and properly incorporate it into the normal modeset.
4466                  */
4467                 return false;
4468         }
4469
4470         return true;
4471 }
4472
4473 /* XXX this is probably wrong for multiple downstream ports */
4474 static enum drm_connector_status
4475 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4476 {
4477         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4478         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4479         u8 *dpcd = intel_dp->dpcd;
4480         u8 type;
4481
4482         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4483                 return connector_status_connected;
4484
4485         lspcon_resume(dig_port);
4486
4487         if (!intel_dp_get_dpcd(intel_dp))
4488                 return connector_status_disconnected;
4489
4490         /* if there's no downstream port, we're done */
4491         if (!drm_dp_is_branch(dpcd))
4492                 return connector_status_connected;
4493
4494         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4495         if (intel_dp_has_sink_count(intel_dp) &&
4496             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4497                 return intel_dp->sink_count ?
4498                 connector_status_connected : connector_status_disconnected;
4499         }
4500
4501         if (intel_dp_can_mst(intel_dp))
4502                 return connector_status_connected;
4503
4504         /* If no HPD, poke DDC gently */
4505         if (drm_probe_ddc(&intel_dp->aux.ddc))
4506                 return connector_status_connected;
4507
4508         /* Well we tried, say unknown for unreliable port types */
4509         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4510                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4511                 if (type == DP_DS_PORT_TYPE_VGA ||
4512                     type == DP_DS_PORT_TYPE_NON_EDID)
4513                         return connector_status_unknown;
4514         } else {
4515                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4516                         DP_DWN_STRM_PORT_TYPE_MASK;
4517                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4518                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4519                         return connector_status_unknown;
4520         }
4521
4522         /* Anything else is out of spec, warn and ignore */
4523         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4524         return connector_status_disconnected;
4525 }
4526
4527 static enum drm_connector_status
4528 edp_detect(struct intel_dp *intel_dp)
4529 {
4530         return connector_status_connected;
4531 }
4532
4533 /*
4534  * intel_digital_port_connected - is the specified port connected?
4535  * @encoder: intel_encoder
4536  *
4537  * In cases where there's a connector physically connected but it can't be used
4538  * by our hardware we also return false, since the rest of the driver should
4539  * pretty much treat the port as disconnected. This is relevant for type-C
4540  * (starting on ICL) where there's ownership involved.
4541  *
4542  * Return %true if port is connected, %false otherwise.
4543  */
4544 bool intel_digital_port_connected(struct intel_encoder *encoder)
4545 {
4546         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4547         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4548         bool is_connected = false;
4549         intel_wakeref_t wakeref;
4550
4551         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4552                 is_connected = dig_port->connected(encoder);
4553
4554         return is_connected;
4555 }
4556
4557 static const struct drm_edid *
4558 intel_dp_get_edid(struct intel_dp *intel_dp)
4559 {
4560         struct intel_connector *connector = intel_dp->attached_connector;
4561         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
4562
4563         /* Use panel fixed edid if we have one */
4564         if (fixed_edid) {
4565                 /* invalid edid */
4566                 if (IS_ERR(fixed_edid))
4567                         return NULL;
4568
4569                 return drm_edid_dup(fixed_edid);
4570         }
4571
4572         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
4573 }
4574
4575 static void
4576 intel_dp_update_dfp(struct intel_dp *intel_dp,
4577                     const struct drm_edid *drm_edid)
4578 {
4579         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4580         struct intel_connector *connector = intel_dp->attached_connector;
4581         const struct edid *edid;
4582
4583         /* FIXME: Get rid of drm_edid_raw() */
4584         edid = drm_edid_raw(drm_edid);
4585
4586         intel_dp->dfp.max_bpc =
4587                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4588                                           intel_dp->downstream_ports, edid);
4589
4590         intel_dp->dfp.max_dotclock =
4591                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4592                                                intel_dp->downstream_ports);
4593
4594         intel_dp->dfp.min_tmds_clock =
4595                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4596                                                  intel_dp->downstream_ports,
4597                                                  edid);
4598         intel_dp->dfp.max_tmds_clock =
4599                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4600                                                  intel_dp->downstream_ports,
4601                                                  edid);
4602
4603         intel_dp->dfp.pcon_max_frl_bw =
4604                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4605                                            intel_dp->downstream_ports);
4606
4607         drm_dbg_kms(&i915->drm,
4608                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4609                     connector->base.base.id, connector->base.name,
4610                     intel_dp->dfp.max_bpc,
4611                     intel_dp->dfp.max_dotclock,
4612                     intel_dp->dfp.min_tmds_clock,
4613                     intel_dp->dfp.max_tmds_clock,
4614                     intel_dp->dfp.pcon_max_frl_bw);
4615
4616         intel_dp_get_pcon_dsc_cap(intel_dp);
4617 }
4618
4619 static void
4620 intel_dp_update_420(struct intel_dp *intel_dp)
4621 {
4622         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4623         struct intel_connector *connector = intel_dp->attached_connector;
4624         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4625
4626         /* No YCbCr output support on gmch platforms */
4627         if (HAS_GMCH(i915))
4628                 return;
4629
4630         /*
4631          * ILK doesn't seem capable of DP YCbCr output. The
4632          * displayed image is severly corrupted. SNB+ is fine.
4633          */
4634         if (IS_IRONLAKE(i915))
4635                 return;
4636
4637         is_branch = drm_dp_is_branch(intel_dp->dpcd);
4638         ycbcr_420_passthrough =
4639                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4640                                                   intel_dp->downstream_ports);
4641         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4642         ycbcr_444_to_420 =
4643                 dp_to_dig_port(intel_dp)->lspcon.active ||
4644                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4645                                                         intel_dp->downstream_ports);
4646         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4647                                                                  intel_dp->downstream_ports,
4648                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4649
4650         if (DISPLAY_VER(i915) >= 11) {
4651                 /* Let PCON convert from RGB->YCbCr if possible */
4652                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4653                         intel_dp->dfp.rgb_to_ycbcr = true;
4654                         intel_dp->dfp.ycbcr_444_to_420 = true;
4655                         connector->base.ycbcr_420_allowed = true;
4656                 } else {
4657                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4658                         intel_dp->dfp.ycbcr_444_to_420 =
4659                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4660
4661                         connector->base.ycbcr_420_allowed =
4662                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4663                 }
4664         } else {
4665                 /* 4:4:4->4:2:0 conversion is the only way */
4666                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4667
4668                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4669         }
4670
4671         drm_dbg_kms(&i915->drm,
4672                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4673                     connector->base.base.id, connector->base.name,
4674                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4675                     str_yes_no(connector->base.ycbcr_420_allowed),
4676                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4677 }
4678
4679 static void
4680 intel_dp_set_edid(struct intel_dp *intel_dp)
4681 {
4682         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4683         struct intel_connector *connector = intel_dp->attached_connector;
4684         const struct drm_edid *drm_edid;
4685         const struct edid *edid;
4686         bool vrr_capable;
4687
4688         intel_dp_unset_edid(intel_dp);
4689         drm_edid = intel_dp_get_edid(intel_dp);
4690         connector->detect_edid = drm_edid;
4691
4692         /* Below we depend on display info having been updated */
4693         drm_edid_connector_update(&connector->base, drm_edid);
4694
4695         vrr_capable = intel_vrr_is_capable(connector);
4696         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4697                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4698         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4699
4700         intel_dp_update_dfp(intel_dp, drm_edid);
4701         intel_dp_update_420(intel_dp);
4702
4703         /* FIXME: Get rid of drm_edid_raw() */
4704         edid = drm_edid_raw(drm_edid);
4705         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4706                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4707                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4708         }
4709
4710         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4711 }
4712
4713 static void
4714 intel_dp_unset_edid(struct intel_dp *intel_dp)
4715 {
4716         struct intel_connector *connector = intel_dp->attached_connector;
4717
4718         drm_dp_cec_unset_edid(&intel_dp->aux);
4719         drm_edid_free(connector->detect_edid);
4720         connector->detect_edid = NULL;
4721
4722         intel_dp->has_hdmi_sink = false;
4723         intel_dp->has_audio = false;
4724
4725         intel_dp->dfp.max_bpc = 0;
4726         intel_dp->dfp.max_dotclock = 0;
4727         intel_dp->dfp.min_tmds_clock = 0;
4728         intel_dp->dfp.max_tmds_clock = 0;
4729
4730         intel_dp->dfp.pcon_max_frl_bw = 0;
4731
4732         intel_dp->dfp.ycbcr_444_to_420 = false;
4733         connector->base.ycbcr_420_allowed = false;
4734
4735         drm_connector_set_vrr_capable_property(&connector->base,
4736                                                false);
4737 }
4738
4739 static int
4740 intel_dp_detect(struct drm_connector *connector,
4741                 struct drm_modeset_acquire_ctx *ctx,
4742                 bool force)
4743 {
4744         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4745         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4746         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4747         struct intel_encoder *encoder = &dig_port->base;
4748         enum drm_connector_status status;
4749
4750         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4751                     connector->base.id, connector->name);
4752         drm_WARN_ON(&dev_priv->drm,
4753                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4754
4755         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4756                 return connector_status_disconnected;
4757
4758         /* Can't disconnect eDP */
4759         if (intel_dp_is_edp(intel_dp))
4760                 status = edp_detect(intel_dp);
4761         else if (intel_digital_port_connected(encoder))
4762                 status = intel_dp_detect_dpcd(intel_dp);
4763         else
4764                 status = connector_status_disconnected;
4765
4766         if (status == connector_status_disconnected) {
4767                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4768                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4769
4770                 if (intel_dp->is_mst) {
4771                         drm_dbg_kms(&dev_priv->drm,
4772                                     "MST device may have disappeared %d vs %d\n",
4773                                     intel_dp->is_mst,
4774                                     intel_dp->mst_mgr.mst_state);
4775                         intel_dp->is_mst = false;
4776                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4777                                                         intel_dp->is_mst);
4778                 }
4779
4780                 goto out;
4781         }
4782
4783         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4784         if (HAS_DSC(dev_priv))
4785                 intel_dp_get_dsc_sink_cap(intel_dp);
4786
4787         intel_dp_configure_mst(intel_dp);
4788
4789         /*
4790          * TODO: Reset link params when switching to MST mode, until MST
4791          * supports link training fallback params.
4792          */
4793         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4794                 intel_dp_reset_max_link_params(intel_dp);
4795                 intel_dp->reset_link_params = false;
4796         }
4797
4798         intel_dp_print_rates(intel_dp);
4799
4800         if (intel_dp->is_mst) {
4801                 /*
4802                  * If we are in MST mode then this connector
4803                  * won't appear connected or have anything
4804                  * with EDID on it
4805                  */
4806                 status = connector_status_disconnected;
4807                 goto out;
4808         }
4809
4810         /*
4811          * Some external monitors do not signal loss of link synchronization
4812          * with an IRQ_HPD, so force a link status check.
4813          */
4814         if (!intel_dp_is_edp(intel_dp)) {
4815                 int ret;
4816
4817                 ret = intel_dp_retrain_link(encoder, ctx);
4818                 if (ret)
4819                         return ret;
4820         }
4821
4822         /*
4823          * Clearing NACK and defer counts to get their exact values
4824          * while reading EDID which are required by Compliance tests
4825          * 4.2.2.4 and 4.2.2.5
4826          */
4827         intel_dp->aux.i2c_nack_count = 0;
4828         intel_dp->aux.i2c_defer_count = 0;
4829
4830         intel_dp_set_edid(intel_dp);
4831         if (intel_dp_is_edp(intel_dp) ||
4832             to_intel_connector(connector)->detect_edid)
4833                 status = connector_status_connected;
4834
4835         intel_dp_check_device_service_irq(intel_dp);
4836
4837 out:
4838         if (status != connector_status_connected && !intel_dp->is_mst)
4839                 intel_dp_unset_edid(intel_dp);
4840
4841         /*
4842          * Make sure the refs for power wells enabled during detect are
4843          * dropped to avoid a new detect cycle triggered by HPD polling.
4844          */
4845         intel_display_power_flush_work(dev_priv);
4846
4847         if (!intel_dp_is_edp(intel_dp))
4848                 drm_dp_set_subconnector_property(connector,
4849                                                  status,
4850                                                  intel_dp->dpcd,
4851                                                  intel_dp->downstream_ports);
4852         return status;
4853 }
4854
4855 static void
4856 intel_dp_force(struct drm_connector *connector)
4857 {
4858         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4859         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4860         struct intel_encoder *intel_encoder = &dig_port->base;
4861         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4862         enum intel_display_power_domain aux_domain =
4863                 intel_aux_power_domain(dig_port);
4864         intel_wakeref_t wakeref;
4865
4866         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4867                     connector->base.id, connector->name);
4868         intel_dp_unset_edid(intel_dp);
4869
4870         if (connector->status != connector_status_connected)
4871                 return;
4872
4873         wakeref = intel_display_power_get(dev_priv, aux_domain);
4874
4875         intel_dp_set_edid(intel_dp);
4876
4877         intel_display_power_put(dev_priv, aux_domain, wakeref);
4878 }
4879
4880 static int intel_dp_get_modes(struct drm_connector *connector)
4881 {
4882         struct intel_connector *intel_connector = to_intel_connector(connector);
4883         int num_modes;
4884
4885         /* drm_edid_connector_update() done in ->detect() or ->force() */
4886         num_modes = drm_edid_connector_add_modes(connector);
4887
4888         /* Also add fixed mode, which may or may not be present in EDID */
4889         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
4890                 num_modes += intel_panel_get_modes(intel_connector);
4891
4892         if (num_modes)
4893                 return num_modes;
4894
4895         if (!intel_connector->detect_edid) {
4896                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4897                 struct drm_display_mode *mode;
4898
4899                 mode = drm_dp_downstream_mode(connector->dev,
4900                                               intel_dp->dpcd,
4901                                               intel_dp->downstream_ports);
4902                 if (mode) {
4903                         drm_mode_probed_add(connector, mode);
4904                         num_modes++;
4905                 }
4906         }
4907
4908         return num_modes;
4909 }
4910
4911 static int
4912 intel_dp_connector_register(struct drm_connector *connector)
4913 {
4914         struct drm_i915_private *i915 = to_i915(connector->dev);
4915         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4916         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4917         struct intel_lspcon *lspcon = &dig_port->lspcon;
4918         int ret;
4919
4920         ret = intel_connector_register(connector);
4921         if (ret)
4922                 return ret;
4923
4924         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4925                     intel_dp->aux.name, connector->kdev->kobj.name);
4926
4927         intel_dp->aux.dev = connector->kdev;
4928         ret = drm_dp_aux_register(&intel_dp->aux);
4929         if (!ret)
4930                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4931
4932         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
4933                 return ret;
4934
4935         /*
4936          * ToDo: Clean this up to handle lspcon init and resume more
4937          * efficiently and streamlined.
4938          */
4939         if (lspcon_init(dig_port)) {
4940                 lspcon_detect_hdr_capability(lspcon);
4941                 if (lspcon->hdr_supported)
4942                         drm_connector_attach_hdr_output_metadata_property(connector);
4943         }
4944
4945         return ret;
4946 }
4947
4948 static void
4949 intel_dp_connector_unregister(struct drm_connector *connector)
4950 {
4951         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4952
4953         drm_dp_cec_unregister_connector(&intel_dp->aux);
4954         drm_dp_aux_unregister(&intel_dp->aux);
4955         intel_connector_unregister(connector);
4956 }
4957
4958 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4959 {
4960         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4961         struct intel_dp *intel_dp = &dig_port->dp;
4962
4963         intel_dp_mst_encoder_cleanup(dig_port);
4964
4965         intel_pps_vdd_off_sync(intel_dp);
4966
4967         /*
4968          * Ensure power off delay is respected on module remove, so that we can
4969          * reduce delays at driver probe. See pps_init_timestamps().
4970          */
4971         intel_pps_wait_power_cycle(intel_dp);
4972
4973         intel_dp_aux_fini(intel_dp);
4974 }
4975
4976 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4977 {
4978         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4979
4980         intel_pps_vdd_off_sync(intel_dp);
4981 }
4982
4983 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4984 {
4985         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4986
4987         intel_pps_wait_power_cycle(intel_dp);
4988 }
4989
4990 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4991                                     int tile_group_id)
4992 {
4993         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4994         struct drm_connector_list_iter conn_iter;
4995         struct drm_connector *connector;
4996         int ret = 0;
4997
4998         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4999         drm_for_each_connector_iter(connector, &conn_iter) {
5000                 struct drm_connector_state *conn_state;
5001                 struct intel_crtc_state *crtc_state;
5002                 struct intel_crtc *crtc;
5003
5004                 if (!connector->has_tile ||
5005                     connector->tile_group->id != tile_group_id)
5006                         continue;
5007
5008                 conn_state = drm_atomic_get_connector_state(&state->base,
5009                                                             connector);
5010                 if (IS_ERR(conn_state)) {
5011                         ret = PTR_ERR(conn_state);
5012                         break;
5013                 }
5014
5015                 crtc = to_intel_crtc(conn_state->crtc);
5016
5017                 if (!crtc)
5018                         continue;
5019
5020                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5021                 crtc_state->uapi.mode_changed = true;
5022
5023                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5024                 if (ret)
5025                         break;
5026         }
5027         drm_connector_list_iter_end(&conn_iter);
5028
5029         return ret;
5030 }
5031
5032 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5033 {
5034         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5035         struct intel_crtc *crtc;
5036
5037         if (transcoders == 0)
5038                 return 0;
5039
5040         for_each_intel_crtc(&dev_priv->drm, crtc) {
5041                 struct intel_crtc_state *crtc_state;
5042                 int ret;
5043
5044                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5045                 if (IS_ERR(crtc_state))
5046                         return PTR_ERR(crtc_state);
5047
5048                 if (!crtc_state->hw.enable)
5049                         continue;
5050
5051                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5052                         continue;
5053
5054                 crtc_state->uapi.mode_changed = true;
5055
5056                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5057                 if (ret)
5058                         return ret;
5059
5060                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5061                 if (ret)
5062                         return ret;
5063
5064                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5065         }
5066
5067         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5068
5069         return 0;
5070 }
5071
5072 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5073                                       struct drm_connector *connector)
5074 {
5075         const struct drm_connector_state *old_conn_state =
5076                 drm_atomic_get_old_connector_state(&state->base, connector);
5077         const struct intel_crtc_state *old_crtc_state;
5078         struct intel_crtc *crtc;
5079         u8 transcoders;
5080
5081         crtc = to_intel_crtc(old_conn_state->crtc);
5082         if (!crtc)
5083                 return 0;
5084
5085         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5086
5087         if (!old_crtc_state->hw.active)
5088                 return 0;
5089
5090         transcoders = old_crtc_state->sync_mode_slaves_mask;
5091         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5092                 transcoders |= BIT(old_crtc_state->master_transcoder);
5093
5094         return intel_modeset_affected_transcoders(state,
5095                                                   transcoders);
5096 }
5097
5098 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5099                                            struct drm_atomic_state *_state)
5100 {
5101         struct drm_i915_private *dev_priv = to_i915(conn->dev);
5102         struct intel_atomic_state *state = to_intel_atomic_state(_state);
5103         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
5104         struct intel_connector *intel_conn = to_intel_connector(conn);
5105         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
5106         int ret;
5107
5108         ret = intel_digital_connector_atomic_check(conn, &state->base);
5109         if (ret)
5110                 return ret;
5111
5112         if (intel_dp_mst_source_support(intel_dp)) {
5113                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
5114                 if (ret)
5115                         return ret;
5116         }
5117
5118         /*
5119          * We don't enable port sync on BDW due to missing w/as and
5120          * due to not having adjusted the modeset sequence appropriately.
5121          */
5122         if (DISPLAY_VER(dev_priv) < 9)
5123                 return 0;
5124
5125         if (!intel_connector_needs_modeset(state, conn))
5126                 return 0;
5127
5128         if (conn->has_tile) {
5129                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5130                 if (ret)
5131                         return ret;
5132         }
5133
5134         return intel_modeset_synced_crtcs(state, conn);
5135 }
5136
5137 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
5138 {
5139         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5140         struct drm_i915_private *i915 = to_i915(connector->dev);
5141
5142         spin_lock_irq(&i915->irq_lock);
5143         i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
5144         spin_unlock_irq(&i915->irq_lock);
5145         queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0);
5146 }
5147
5148 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5149         .force = intel_dp_force,
5150         .fill_modes = drm_helper_probe_single_connector_modes,
5151         .atomic_get_property = intel_digital_connector_atomic_get_property,
5152         .atomic_set_property = intel_digital_connector_atomic_set_property,
5153         .late_register = intel_dp_connector_register,
5154         .early_unregister = intel_dp_connector_unregister,
5155         .destroy = intel_connector_destroy,
5156         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5157         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5158         .oob_hotplug_event = intel_dp_oob_hotplug_event,
5159 };
5160
5161 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5162         .detect_ctx = intel_dp_detect,
5163         .get_modes = intel_dp_get_modes,
5164         .mode_valid = intel_dp_mode_valid,
5165         .atomic_check = intel_dp_connector_atomic_check,
5166 };
5167
5168 enum irqreturn
5169 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5170 {
5171         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5172         struct intel_dp *intel_dp = &dig_port->dp;
5173
5174         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5175             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5176                 /*
5177                  * vdd off can generate a long/short pulse on eDP which
5178                  * would require vdd on to handle it, and thus we
5179                  * would end up in an endless cycle of
5180                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5181                  */
5182                 drm_dbg_kms(&i915->drm,
5183                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5184                             long_hpd ? "long" : "short",
5185                             dig_port->base.base.base.id,
5186                             dig_port->base.base.name);
5187                 return IRQ_HANDLED;
5188         }
5189
5190         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5191                     dig_port->base.base.base.id,
5192                     dig_port->base.base.name,
5193                     long_hpd ? "long" : "short");
5194
5195         if (long_hpd) {
5196                 intel_dp->reset_link_params = true;
5197                 return IRQ_NONE;
5198         }
5199
5200         if (intel_dp->is_mst) {
5201                 if (!intel_dp_check_mst_status(intel_dp))
5202                         return IRQ_NONE;
5203         } else if (!intel_dp_short_pulse(intel_dp)) {
5204                 return IRQ_NONE;
5205         }
5206
5207         return IRQ_HANDLED;
5208 }
5209
5210 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
5211                                   const struct intel_bios_encoder_data *devdata,
5212                                   enum port port)
5213 {
5214         /*
5215          * eDP not supported on g4x. so bail out early just
5216          * for a bit extra safety in case the VBT is bonkers.
5217          */
5218         if (DISPLAY_VER(dev_priv) < 5)
5219                 return false;
5220
5221         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5222                 return true;
5223
5224         return devdata && intel_bios_encoder_supports_edp(devdata);
5225 }
5226
5227 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
5228 {
5229         const struct intel_bios_encoder_data *devdata =
5230                 intel_bios_encoder_data_lookup(i915, port);
5231
5232         return _intel_dp_is_port_edp(i915, devdata, port);
5233 }
5234
5235 static bool
5236 has_gamut_metadata_dip(struct intel_encoder *encoder)
5237 {
5238         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
5239         enum port port = encoder->port;
5240
5241         if (intel_bios_encoder_is_lspcon(encoder->devdata))
5242                 return false;
5243
5244         if (DISPLAY_VER(i915) >= 11)
5245                 return true;
5246
5247         if (port == PORT_A)
5248                 return false;
5249
5250         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5251             DISPLAY_VER(i915) >= 9)
5252                 return true;
5253
5254         return false;
5255 }
5256
5257 static void
5258 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5259 {
5260         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5261         enum port port = dp_to_dig_port(intel_dp)->base.port;
5262
5263         if (!intel_dp_is_edp(intel_dp))
5264                 drm_connector_attach_dp_subconnector_property(connector);
5265
5266         if (!IS_G4X(dev_priv) && port != PORT_A)
5267                 intel_attach_force_audio_property(connector);
5268
5269         intel_attach_broadcast_rgb_property(connector);
5270         if (HAS_GMCH(dev_priv))
5271                 drm_connector_attach_max_bpc_property(connector, 6, 10);
5272         else if (DISPLAY_VER(dev_priv) >= 5)
5273                 drm_connector_attach_max_bpc_property(connector, 6, 12);
5274
5275         /* Register HDMI colorspace for case of lspcon */
5276         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
5277                 drm_connector_attach_content_type_property(connector);
5278                 intel_attach_hdmi_colorspace_property(connector);
5279         } else {
5280                 intel_attach_dp_colorspace_property(connector);
5281         }
5282
5283         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
5284                 drm_connector_attach_hdr_output_metadata_property(connector);
5285
5286         if (HAS_VRR(dev_priv))
5287                 drm_connector_attach_vrr_capable_property(connector);
5288 }
5289
5290 static void
5291 intel_edp_add_properties(struct intel_dp *intel_dp)
5292 {
5293         struct intel_connector *connector = intel_dp->attached_connector;
5294         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5295         const struct drm_display_mode *fixed_mode =
5296                 intel_panel_preferred_fixed_mode(connector);
5297
5298         intel_attach_scaling_mode_property(&connector->base);
5299
5300         drm_connector_set_panel_orientation_with_quirk(&connector->base,
5301                                                        i915->display.vbt.orientation,
5302                                                        fixed_mode->hdisplay,
5303                                                        fixed_mode->vdisplay);
5304 }
5305
5306 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
5307                                       struct intel_connector *connector)
5308 {
5309         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5310         enum pipe pipe = INVALID_PIPE;
5311
5312         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
5313                 /*
5314                  * Figure out the current pipe for the initial backlight setup.
5315                  * If the current pipe isn't valid, try the PPS pipe, and if that
5316                  * fails just assume pipe A.
5317                  */
5318                 pipe = vlv_active_pipe(intel_dp);
5319
5320                 if (pipe != PIPE_A && pipe != PIPE_B)
5321                         pipe = intel_dp->pps.pps_pipe;
5322
5323                 if (pipe != PIPE_A && pipe != PIPE_B)
5324                         pipe = PIPE_A;
5325         }
5326
5327         intel_backlight_setup(connector, pipe);
5328 }
5329
5330 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5331                                      struct intel_connector *intel_connector)
5332 {
5333         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5334         struct drm_connector *connector = &intel_connector->base;
5335         struct drm_display_mode *fixed_mode;
5336         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5337         bool has_dpcd;
5338         const struct drm_edid *drm_edid;
5339
5340         if (!intel_dp_is_edp(intel_dp))
5341                 return true;
5342
5343         /*
5344          * On IBX/CPT we may get here with LVDS already registered. Since the
5345          * driver uses the only internal power sequencer available for both
5346          * eDP and LVDS bail out early in this case to prevent interfering
5347          * with an already powered-on LVDS power sequencer.
5348          */
5349         if (intel_get_lvds_encoder(dev_priv)) {
5350                 drm_WARN_ON(&dev_priv->drm,
5351                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5352                 drm_info(&dev_priv->drm,
5353                          "LVDS was detected, not registering eDP\n");
5354
5355                 return false;
5356         }
5357
5358         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
5359                                     encoder->devdata);
5360
5361         if (!intel_pps_init(intel_dp)) {
5362                 drm_info(&dev_priv->drm,
5363                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
5364                          encoder->base.base.id, encoder->base.name);
5365                 /*
5366                  * The BIOS may have still enabled VDD on the PPS even
5367                  * though it's unusable. Make sure we turn it back off
5368                  * and to release the power domain references/etc.
5369                  */
5370                 goto out_vdd_off;
5371         }
5372
5373         /* Cache DPCD and EDID for edp. */
5374         has_dpcd = intel_edp_init_dpcd(intel_dp);
5375
5376         if (!has_dpcd) {
5377                 /* if this fails, presume the device is a ghost */
5378                 drm_info(&dev_priv->drm,
5379                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
5380                          encoder->base.base.id, encoder->base.name);
5381                 goto out_vdd_off;
5382         }
5383
5384         mutex_lock(&dev_priv->drm.mode_config.mutex);
5385         drm_edid = drm_edid_read_ddc(connector, &intel_dp->aux.ddc);
5386         if (!drm_edid) {
5387                 /* Fallback to EDID from ACPI OpRegion, if any */
5388                 drm_edid = intel_opregion_get_edid(intel_connector);
5389                 if (drm_edid)
5390                         drm_dbg_kms(&dev_priv->drm,
5391                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5392                                     connector->base.id, connector->name);
5393         }
5394         if (drm_edid) {
5395                 if (drm_edid_connector_update(connector, drm_edid) ||
5396                     !drm_edid_connector_add_modes(connector)) {
5397                         drm_edid_connector_update(connector, NULL);
5398                         drm_edid_free(drm_edid);
5399                         drm_edid = ERR_PTR(-EINVAL);
5400                 }
5401         } else {
5402                 drm_edid = ERR_PTR(-ENOENT);
5403         }
5404
5405         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
5406                                    IS_ERR(drm_edid) ? NULL : drm_edid);
5407
5408         intel_panel_add_edid_fixed_modes(intel_connector, true);
5409
5410         /* MSO requires information from the EDID */
5411         intel_edp_mso_init(intel_dp);
5412
5413         /* multiply the mode clock and horizontal timings for MSO */
5414         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5415                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5416
5417         /* fallback to VBT if available for eDP */
5418         if (!intel_panel_preferred_fixed_mode(intel_connector))
5419                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5420
5421         mutex_unlock(&dev_priv->drm.mode_config.mutex);
5422
5423         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
5424                 drm_info(&dev_priv->drm,
5425                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
5426                          encoder->base.base.id, encoder->base.name);
5427                 goto out_vdd_off;
5428         }
5429
5430         intel_panel_init(intel_connector, drm_edid);
5431
5432         intel_edp_backlight_setup(intel_dp, intel_connector);
5433
5434         intel_edp_add_properties(intel_dp);
5435
5436         intel_pps_init_late(intel_dp);
5437
5438         return true;
5439
5440 out_vdd_off:
5441         intel_pps_vdd_off_sync(intel_dp);
5442
5443         return false;
5444 }
5445
5446 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5447 {
5448         struct intel_connector *intel_connector;
5449         struct drm_connector *connector;
5450
5451         intel_connector = container_of(work, typeof(*intel_connector),
5452                                        modeset_retry_work);
5453         connector = &intel_connector->base;
5454         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5455                     connector->name);
5456
5457         /* Grab the locks before changing connector property*/
5458         mutex_lock(&connector->dev->mode_config.mutex);
5459         /* Set connector link status to BAD and send a Uevent to notify
5460          * userspace to do a modeset.
5461          */
5462         drm_connector_set_link_status_property(connector,
5463                                                DRM_MODE_LINK_STATUS_BAD);
5464         mutex_unlock(&connector->dev->mode_config.mutex);
5465         /* Send Hotplug uevent so userspace can reprobe */
5466         drm_kms_helper_connector_hotplug_event(connector);
5467 }
5468
5469 bool
5470 intel_dp_init_connector(struct intel_digital_port *dig_port,
5471                         struct intel_connector *intel_connector)
5472 {
5473         struct drm_connector *connector = &intel_connector->base;
5474         struct intel_dp *intel_dp = &dig_port->dp;
5475         struct intel_encoder *intel_encoder = &dig_port->base;
5476         struct drm_device *dev = intel_encoder->base.dev;
5477         struct drm_i915_private *dev_priv = to_i915(dev);
5478         enum port port = intel_encoder->port;
5479         enum phy phy = intel_port_to_phy(dev_priv, port);
5480         int type;
5481
5482         /* Initialize the work for modeset in case of link train failure */
5483         INIT_WORK(&intel_connector->modeset_retry_work,
5484                   intel_dp_modeset_retry_work_fn);
5485
5486         if (drm_WARN(dev, dig_port->max_lanes < 1,
5487                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5488                      dig_port->max_lanes, intel_encoder->base.base.id,
5489                      intel_encoder->base.name))
5490                 return false;
5491
5492         intel_dp->reset_link_params = true;
5493         intel_dp->pps.pps_pipe = INVALID_PIPE;
5494         intel_dp->pps.active_pipe = INVALID_PIPE;
5495
5496         /* Preserve the current hw state. */
5497         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5498         intel_dp->attached_connector = intel_connector;
5499
5500         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
5501                 /*
5502                  * Currently we don't support eDP on TypeC ports, although in
5503                  * theory it could work on TypeC legacy ports.
5504                  */
5505                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5506                 type = DRM_MODE_CONNECTOR_eDP;
5507                 intel_encoder->type = INTEL_OUTPUT_EDP;
5508
5509                 /* eDP only on port B and/or C on vlv/chv */
5510                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5511                                       IS_CHERRYVIEW(dev_priv)) &&
5512                                 port != PORT_B && port != PORT_C))
5513                         return false;
5514         } else {
5515                 type = DRM_MODE_CONNECTOR_DisplayPort;
5516         }
5517
5518         intel_dp_set_default_sink_rates(intel_dp);
5519         intel_dp_set_default_max_sink_lane_count(intel_dp);
5520
5521         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5522                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5523
5524         drm_dbg_kms(&dev_priv->drm,
5525                     "Adding %s connector on [ENCODER:%d:%s]\n",
5526                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5527                     intel_encoder->base.base.id, intel_encoder->base.name);
5528
5529         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5530         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5531
5532         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
5533                 connector->interlace_allowed = true;
5534
5535         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5536
5537         intel_dp_aux_init(intel_dp);
5538
5539         intel_connector_attach_encoder(intel_connector, intel_encoder);
5540
5541         if (HAS_DDI(dev_priv))
5542                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5543         else
5544                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5545
5546         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5547                 intel_dp_aux_fini(intel_dp);
5548                 goto fail;
5549         }
5550
5551         intel_dp_set_source_rates(intel_dp);
5552         intel_dp_set_common_rates(intel_dp);
5553         intel_dp_reset_max_link_params(intel_dp);
5554
5555         /* init MST on ports that can support it */
5556         intel_dp_mst_encoder_init(dig_port,
5557                                   intel_connector->base.base.id);
5558
5559         intel_dp_add_properties(intel_dp, connector);
5560
5561         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5562                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5563                 if (ret)
5564                         drm_dbg_kms(&dev_priv->drm,
5565                                     "HDCP init failed, skipping.\n");
5566         }
5567
5568         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5569          * 0xd.  Failure to do so will result in spurious interrupts being
5570          * generated on the port when a cable is not attached.
5571          */
5572         if (IS_G45(dev_priv)) {
5573                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5574                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5575                                (temp & ~0xf) | 0xd);
5576         }
5577
5578         intel_dp->frl.is_trained = false;
5579         intel_dp->frl.trained_rate_gbps = 0;
5580
5581         intel_psr_init(intel_dp);
5582
5583         return true;
5584
5585 fail:
5586         drm_connector_cleanup(connector);
5587
5588         return false;
5589 }
5590
5591 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5592 {
5593         struct intel_encoder *encoder;
5594
5595         if (!HAS_DISPLAY(dev_priv))
5596                 return;
5597
5598         for_each_intel_encoder(&dev_priv->drm, encoder) {
5599                 struct intel_dp *intel_dp;
5600
5601                 if (encoder->type != INTEL_OUTPUT_DDI)
5602                         continue;
5603
5604                 intel_dp = enc_to_intel_dp(encoder);
5605
5606                 if (!intel_dp_mst_source_support(intel_dp))
5607                         continue;
5608
5609                 if (intel_dp->is_mst)
5610                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5611         }
5612 }
5613
5614 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5615 {
5616         struct intel_encoder *encoder;
5617
5618         if (!HAS_DISPLAY(dev_priv))
5619                 return;
5620
5621         for_each_intel_encoder(&dev_priv->drm, encoder) {
5622                 struct intel_dp *intel_dp;
5623                 int ret;
5624
5625                 if (encoder->type != INTEL_OUTPUT_DDI)
5626                         continue;
5627
5628                 intel_dp = enc_to_intel_dp(encoder);
5629
5630                 if (!intel_dp_mst_source_support(intel_dp))
5631                         continue;
5632
5633                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5634                                                      true);
5635                 if (ret) {
5636                         intel_dp->is_mst = false;
5637                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5638                                                         false);
5639                 }
5640         }
5641 }