2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/i915_mei_hdcp_interface.h>
44 #include <media/cec-notifier.h>
50 struct __intel_global_objs_state;
53 * Display related stuff
56 /* these are outputs from the chip - integrated only
57 external chips are via DVO or SDVO output */
58 enum intel_output_type {
59 INTEL_OUTPUT_UNUSED = 0,
60 INTEL_OUTPUT_ANALOG = 1,
62 INTEL_OUTPUT_SDVO = 3,
63 INTEL_OUTPUT_LVDS = 4,
64 INTEL_OUTPUT_TVOUT = 5,
65 INTEL_OUTPUT_HDMI = 6,
69 INTEL_OUTPUT_DDI = 10,
70 INTEL_OUTPUT_DP_MST = 11,
73 enum hdmi_force_audio {
74 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
75 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
76 HDMI_AUDIO_AUTO, /* trust EDID */
77 HDMI_AUDIO_ON, /* force turn on HDMI audio */
80 /* "Broadcast RGB" property */
81 enum intel_broadcast_rgb {
82 INTEL_BROADCAST_RGB_AUTO,
83 INTEL_BROADCAST_RGB_FULL,
84 INTEL_BROADCAST_RGB_LIMITED,
87 struct intel_framebuffer {
88 struct drm_framebuffer base;
89 struct intel_frontbuffer *frontbuffer;
90 struct intel_rotation_info rot_info;
92 /* for each plane in the normal GTT view */
96 /* for each plane in the rotated GTT view for no-CCS formats */
99 unsigned int pitch; /* pixels */
104 struct drm_fb_helper helper;
105 struct intel_framebuffer *fb;
106 struct i915_vma *vma;
107 unsigned long vma_flags;
108 async_cookie_t cookie;
111 /* Whether or not fbdev hpd processing is temporarily suspended */
112 bool hpd_suspended : 1;
113 /* Set when a hotplug was received while HPD processing was
116 bool hpd_waiting : 1;
118 /* Protects hpd_suspended */
119 struct mutex hpd_lock;
122 enum intel_hotplug_state {
123 INTEL_HOTPLUG_UNCHANGED,
124 INTEL_HOTPLUG_CHANGED,
128 struct intel_encoder {
129 struct drm_encoder base;
131 enum intel_output_type type;
135 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
136 struct intel_connector *connector);
137 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
138 struct intel_crtc_state *,
139 struct drm_connector_state *);
140 int (*compute_config)(struct intel_encoder *,
141 struct intel_crtc_state *,
142 struct drm_connector_state *);
143 int (*compute_config_late)(struct intel_encoder *,
144 struct intel_crtc_state *,
145 struct drm_connector_state *);
146 void (*update_prepare)(struct intel_atomic_state *,
147 struct intel_encoder *,
148 struct intel_crtc *);
149 void (*pre_pll_enable)(struct intel_atomic_state *,
150 struct intel_encoder *,
151 const struct intel_crtc_state *,
152 const struct drm_connector_state *);
153 void (*pre_enable)(struct intel_atomic_state *,
154 struct intel_encoder *,
155 const struct intel_crtc_state *,
156 const struct drm_connector_state *);
157 void (*enable)(struct intel_atomic_state *,
158 struct intel_encoder *,
159 const struct intel_crtc_state *,
160 const struct drm_connector_state *);
161 void (*update_complete)(struct intel_atomic_state *,
162 struct intel_encoder *,
163 struct intel_crtc *);
164 void (*disable)(struct intel_atomic_state *,
165 struct intel_encoder *,
166 const struct intel_crtc_state *,
167 const struct drm_connector_state *);
168 void (*post_disable)(struct intel_atomic_state *,
169 struct intel_encoder *,
170 const struct intel_crtc_state *,
171 const struct drm_connector_state *);
172 void (*post_pll_disable)(struct intel_atomic_state *,
173 struct intel_encoder *,
174 const struct intel_crtc_state *,
175 const struct drm_connector_state *);
176 void (*update_pipe)(struct intel_atomic_state *,
177 struct intel_encoder *,
178 const struct intel_crtc_state *,
179 const struct drm_connector_state *);
180 /* Read out the current hw state of this connector, returning true if
181 * the encoder is active. If the encoder is enabled it also set the pipe
182 * it is connected to in the pipe parameter. */
183 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
184 /* Reconstructs the equivalent mode flags for the current hardware
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
187 * be set correctly before calling this function. */
188 void (*get_config)(struct intel_encoder *,
189 struct intel_crtc_state *pipe_config);
192 * Optional hook called during init/resume to sync any state
193 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
195 void (*sync_state)(struct intel_encoder *encoder,
196 const struct intel_crtc_state *crtc_state);
199 * Optional hook, returning true if this encoder allows a fastset
200 * during the initial commit, false otherwise.
202 bool (*initial_fastset_check)(struct intel_encoder *encoder,
203 struct intel_crtc_state *crtc_state);
206 * Acquires the power domains needed for an active encoder during
207 * hardware state readout.
209 void (*get_power_domains)(struct intel_encoder *encoder,
210 struct intel_crtc_state *crtc_state);
212 * Called during system suspend after all pending requests for the
213 * encoder are flushed (for example for DP AUX transactions) and
214 * device interrupts are disabled.
216 void (*suspend)(struct intel_encoder *);
218 * Called during system reboot/shutdown after all the
219 * encoders have been disabled and suspended.
221 void (*shutdown)(struct intel_encoder *encoder);
222 enum hpd_pin hpd_pin;
223 enum intel_display_power_domain power_domain;
224 /* for communication with audio component; protected by av_mutex */
225 const struct drm_connector *audio_connector;
229 struct drm_display_mode *fixed_mode;
230 struct drm_display_mode *downclock_mode;
239 bool combination_mode; /* gen 2/4 only */
241 bool alternate_pwm_increment; /* lpt+ */
244 bool util_pin_active_low; /* bxt+ */
245 u8 controller; /* bxt+ only */
246 struct pwm_device *pwm;
247 struct pwm_state pwm_state;
252 struct backlight_device *device;
254 /* Connector and platform specific backlight functions */
255 int (*setup)(struct intel_connector *connector, enum pipe pipe);
256 u32 (*get)(struct intel_connector *connector);
257 void (*set)(const struct drm_connector_state *conn_state, u32 level);
258 void (*disable)(const struct drm_connector_state *conn_state);
259 void (*enable)(const struct intel_crtc_state *crtc_state,
260 const struct drm_connector_state *conn_state);
261 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
262 void (*power)(struct intel_connector *, bool enable);
266 struct intel_digital_port;
268 enum check_link_response {
269 HDCP_LINK_PROTECTED = 0,
270 HDCP_TOPOLOGY_CHANGE,
271 HDCP_LINK_INTEGRITY_FAILURE,
276 * This structure serves as a translation layer between the generic HDCP code
277 * and the bus-specific code. What that means is that HDCP over HDMI differs
278 * from HDCP over DP, so to account for these differences, we need to
279 * communicate with the receiver through this shim.
281 * For completeness, the 2 buses differ in the following ways:
283 * HDCP registers on the receiver are set via DP AUX for DP, and
284 * they are set via DDC for HDMI.
285 * - Receiver register offsets
286 * The offsets of the registers are different for DP vs. HDMI
287 * - Receiver register masks/offsets
288 * For instance, the ready bit for the KSV fifo is in a different
289 * place on DP vs HDMI
290 * - Receiver register names
291 * Seriously. In the DP spec, the 16-bit register containing
292 * downstream information is called BINFO, on HDMI it's called
293 * BSTATUS. To confuse matters further, DP has a BSTATUS register
294 * with a completely different definition.
296 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
297 * be read 3 keys at a time
299 * Since Aksv is hidden in hardware, there's different procedures
300 * to send it over DP AUX vs DDC
302 struct intel_hdcp_shim {
303 /* Outputs the transmitter's An and Aksv values to the receiver. */
304 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
306 /* Reads the receiver's key selection vector */
307 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
310 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
311 * definitions are the same in the respective specs, but the names are
312 * different. Call it BSTATUS since that's the name the HDMI spec
313 * uses and it was there first.
315 int (*read_bstatus)(struct intel_digital_port *dig_port,
318 /* Determines whether a repeater is present downstream */
319 int (*repeater_present)(struct intel_digital_port *dig_port,
320 bool *repeater_present);
322 /* Reads the receiver's Ri' value */
323 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
325 /* Determines if the receiver's KSV FIFO is ready for consumption */
326 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
329 /* Reads the ksv fifo for num_downstream devices */
330 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
331 int num_downstream, u8 *ksv_fifo);
333 /* Reads a 32-bit part of V' from the receiver */
334 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
337 /* Enables HDCP signalling on the port */
338 int (*toggle_signalling)(struct intel_digital_port *dig_port,
339 enum transcoder cpu_transcoder,
342 /* Ensures the link is still protected */
343 bool (*check_link)(struct intel_digital_port *dig_port,
344 struct intel_connector *connector);
346 /* Detects panel's hdcp capability. This is optional for HDMI. */
347 int (*hdcp_capable)(struct intel_digital_port *dig_port,
350 /* HDCP adaptation(DP/HDMI) required on the port */
351 enum hdcp_wired_protocol protocol;
353 /* Detects whether sink is HDCP2.2 capable */
354 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
357 /* Write HDCP2.2 messages */
358 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
359 void *buf, size_t size);
361 /* Read HDCP2.2 messages */
362 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
363 u8 msg_id, void *buf, size_t size);
366 * Implementation of DP HDCP2.2 Errata for the communication of stream
367 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
368 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
370 int (*config_stream_type)(struct intel_digital_port *dig_port,
371 bool is_repeater, u8 type);
373 /* HDCP2.2 Link Integrity Check */
374 int (*check_2_2_link)(struct intel_digital_port *dig_port);
378 const struct intel_hdcp_shim *shim;
379 /* Mutex for hdcp state of the connector */
382 struct delayed_work check_work;
383 struct work_struct prop_work;
385 /* HDCP1.4 Encryption status */
388 /* HDCP2.2 related definitions */
389 /* Flag indicates whether this connector supports HDCP2.2 or not. */
390 bool hdcp2_supported;
392 /* HDCP2.2 Encryption status */
393 bool hdcp2_encrypted;
396 * Content Stream Type defined by content owner. TYPE0(0x0) content can
397 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
398 * content can flow only through a link protected by HDCP2.2.
401 struct hdcp_port_data port_data;
407 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
408 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
409 * When it rolls over re-auth has to be triggered.
414 * Count of RepeaterAuth_Stream_Manage msg propagated.
415 * Initialized to 0 on AKE_INIT. Incremented after every successful
416 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
417 * over re-Auth has to be triggered.
422 * Work queue to signal the CP_IRQ. Used for the waiters to read the
423 * available information from HDCP DP sink.
425 wait_queue_head_t cp_irq_queue;
426 atomic_t cp_irq_count;
427 int cp_irq_count_cached;
430 * HDCP register access for gen12+ need the transcoder associated.
431 * Transcoder attached to the connector could be changed at modeset.
432 * Hence caching the transcoder here.
434 enum transcoder cpu_transcoder;
437 struct intel_connector {
438 struct drm_connector base;
440 * The fixed encoder this connector is connected to.
442 struct intel_encoder *encoder;
444 /* ACPI device id for ACPI and driver cooperation */
447 /* Reads out the current hw, returning true if the connector is enabled
448 * and active (i.e. dpms ON state). */
449 bool (*get_hw_state)(struct intel_connector *);
451 /* Panel info for eDP and LVDS */
452 struct intel_panel panel;
454 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
456 struct edid *detect_edid;
458 /* Number of times hotplug detection was tried after an HPD interrupt */
461 /* since POLL and HPD connectors may use the same HPD line keep the native
462 state of connector->polled in case hotplug storm detection changes it */
465 struct drm_dp_mst_port *port;
467 struct intel_dp *mst_port;
469 /* Work struct to schedule a uevent on link train failure */
470 struct work_struct modeset_retry_work;
472 struct intel_hdcp hdcp;
475 struct intel_digital_connector_state {
476 struct drm_connector_state base;
478 enum hdmi_force_audio force_audio;
482 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
496 struct intel_atomic_state {
497 struct drm_atomic_state base;
499 intel_wakeref_t wakeref;
501 struct __intel_global_objs_state *global_objs;
504 bool dpll_set, modeset;
506 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
509 * Current watermarks can't be trusted during hardware readout, so
510 * don't bother calculating intermediate watermarks.
512 bool skip_intermediate_wm;
514 bool rps_interactive;
516 struct i915_sw_fence commit_ready;
518 struct llist_node freed;
521 struct intel_plane_state {
522 struct drm_plane_state uapi;
525 * actual hardware state, the state we program to the hardware.
526 * The following members are used to verify the hardware state:
527 * During initial hw readout, they need to be copied from uapi.
530 struct drm_crtc *crtc;
531 struct drm_framebuffer *fb;
534 uint16_t pixel_blend_mode;
535 unsigned int rotation;
536 enum drm_color_encoding color_encoding;
537 enum drm_color_range color_range;
538 enum drm_scaling_filter scaling_filter;
541 struct i915_ggtt_view view;
542 struct i915_vma *vma;
544 #define PLANE_HAS_FENCE BIT(0)
550 * bytes for 0/180 degree rotation
551 * pixels for 90/270 degree rotation
557 /* plane control register */
560 /* plane color control register */
563 /* chroma upsampler control register */
568 * = -1 : not using a scaler
569 * >= 0 : using a scalers
571 * plane requiring a scaler:
572 * - During check_plane, its bit is set in
573 * crtc_state->scaler_state.scaler_users by calling helper function
574 * update_scaler_plane.
575 * - scaler_id indicates the scaler it got assigned.
577 * plane doesn't require a scaler:
578 * - this can happen when scaling is no more required or plane simply
580 * - During check_plane, corresponding bit is reset in
581 * crtc_state->scaler_state.scaler_users by calling helper function
582 * update_scaler_plane.
587 * planar_linked_plane:
589 * ICL planar formats require 2 planes that are updated as pairs.
590 * This member is used to make sure the other plane is also updated
591 * when required, and for update_slave() to find the correct
592 * plane_state to pass as argument.
594 struct intel_plane *planar_linked_plane;
598 * If set don't update use the linked plane's state for updating
599 * this plane during atomic commit with the update_slave() callback.
601 * It's also used by the watermark code to ignore wm calculations on
602 * this plane. They're calculated by the linked plane's wm code.
606 struct drm_intel_sprite_colorkey ckey;
609 struct intel_initial_plane_config {
610 struct intel_framebuffer *fb;
611 struct i915_vma *vma;
618 struct intel_scaler {
623 struct intel_crtc_scaler_state {
624 #define SKL_NUM_SCALERS 2
625 struct intel_scaler scalers[SKL_NUM_SCALERS];
628 * scaler_users: keeps track of users requesting scalers on this crtc.
630 * If a bit is set, a user is using a scaler.
631 * Here user can be a plane or crtc as defined below:
632 * bits 0-30 - plane (bit position is index from drm_plane_index)
635 * Instead of creating a new index to cover planes and crtc, using
636 * existing drm_plane_index for planes which is well less than 31
637 * planes and bit 31 for crtc. This should be fine to cover all
640 * intel_atomic_setup_scalers will setup available scalers to users
641 * requesting scalers. It will gracefully fail if request exceeds
644 #define SKL_CRTC_INDEX 31
645 unsigned scaler_users;
647 /* scaler used by crtc for panel fitting purpose */
651 /* {crtc,crtc_state}->mode_flags */
652 /* Flag to get scanline using frame time stamps */
653 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
654 /* Flag to use the scanline counter instead of the pixel counter */
655 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
657 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
658 * is operating in command mode.
659 * Flag to use TE from DSI0 instead of VBI in command mode
661 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
662 /* Flag to use TE from DSI1 instead of VBI in command mode */
663 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
664 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
665 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
667 struct intel_wm_level {
675 struct intel_pipe_wm {
676 struct intel_wm_level wm[5];
679 bool sprites_enabled;
683 struct skl_wm_level {
692 struct skl_plane_wm {
693 struct skl_wm_level wm[8];
694 struct skl_wm_level uv_wm[8];
695 struct skl_wm_level trans_wm;
696 struct skl_wm_level sagv_wm0;
701 struct skl_plane_wm planes[I915_MAX_PLANES];
708 VLV_WM_LEVEL_DDR_DVFS,
712 struct vlv_wm_state {
713 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
714 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
719 struct vlv_fifo_state {
720 u16 plane[I915_MAX_PLANES];
730 struct g4x_wm_state {
731 struct g4x_pipe_wm wm;
733 struct g4x_sr_wm hpll;
739 struct intel_crtc_wm_state {
743 * The "raw" watermark values produced by the formula
744 * given the plane's current state. They do not consider
745 * how much FIFO is actually allocated for each plane.
748 * The "optimal" watermark values given the current
749 * state of the planes and the amount of FIFO
750 * allocated to each, ignoring any previous state
754 * The "intermediate" watermark values when transitioning
755 * between the old and new "optimal" values. Used when
756 * the watermark registers are single buffered and hence
757 * their state changes asynchronously with regards to the
758 * actual plane registers. These are essentially the
759 * worst case combination of the old and new "optimal"
760 * watermarks, which are therefore safe to use when the
761 * plane is in either its old or new state.
764 struct intel_pipe_wm intermediate;
765 struct intel_pipe_wm optimal;
769 struct skl_pipe_wm raw;
770 /* gen9+ only needs 1-step wm programming */
771 struct skl_pipe_wm optimal;
772 struct skl_ddb_entry ddb;
773 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
774 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
778 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
779 struct vlv_wm_state intermediate; /* inverted */
780 struct vlv_wm_state optimal; /* inverted */
781 struct vlv_fifo_state fifo_state;
785 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
786 struct g4x_wm_state intermediate;
787 struct g4x_wm_state optimal;
792 * Platforms with two-step watermark programming will need to
793 * update watermark programming post-vblank to switch from the
794 * safe intermediate watermarks to the optimal final
797 bool need_postvbl_update;
800 enum intel_output_format {
801 INTEL_OUTPUT_FORMAT_INVALID,
802 INTEL_OUTPUT_FORMAT_RGB,
803 INTEL_OUTPUT_FORMAT_YCBCR420,
804 INTEL_OUTPUT_FORMAT_YCBCR444,
807 struct intel_crtc_state {
809 * uapi (drm) state. This is the software state shown to userspace.
810 * In particular, the following members are used for bookkeeping:
818 struct drm_crtc_state uapi;
821 * actual hardware state, the state we program to the hardware.
822 * The following members are used to verify the hardware state:
825 * - mode / pipe_mode / adjusted_mode
826 * - color property blobs.
828 * During initial hw readout, they need to be copied to uapi.
830 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
831 * Use the pipe_mode for calculations like watermarks, pipe
832 * scaler, and bandwidth.
834 * Use adjusted_mode for things that need to know the full
835 * mode on the transcoder, which spans all pipes.
839 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
840 struct drm_display_mode mode, pipe_mode, adjusted_mode;
841 enum drm_scaling_filter scaling_filter;
845 * quirks - bitfield with hw state readout quirks
847 * For various reasons the hw state readout code might not be able to
848 * completely faithfully read out the current state. These cases are
849 * tracked with quirk flags so that fastboot and state checker can act
852 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
853 #define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
854 unsigned long quirks;
856 unsigned fb_bits; /* framebuffers to flip */
857 bool update_pipe; /* can a fast modeset be performed? */
859 bool update_wm_pre, update_wm_post; /* watermarks are updated */
860 bool fifo_changed; /* FIFO split is changed */
862 bool inherited; /* state inherited from BIOS? */
864 /* Pipe source size (ie. panel fitter input size)
865 * All planes will be positioned inside this space,
866 * and get clipped at the edges. */
867 int pipe_src_w, pipe_src_h;
870 * Pipe pixel rate, adjusted for
871 * panel fitter/pipe scaler downscaling.
873 unsigned int pixel_rate;
875 /* Whether to set up the PCH/FDI. Note that we never allow sharing
876 * between pch encoders and cpu encoders. */
877 bool has_pch_encoder;
879 /* Are we sending infoframes on the attached port */
882 /* CPU Transcoder for the pipe. Currently this can only differ from the
883 * pipe on Haswell and later (where we have a special eDP transcoder)
884 * and Broxton (where we have special DSI transcoders). */
885 enum transcoder cpu_transcoder;
888 * Use reduced/limited/broadcast rbg range, compressing from the full
889 * range fed into the crtcs.
891 bool limited_color_range;
893 /* Bitmask of encoder types (enum intel_output_type)
894 * driven by the pipe.
896 unsigned int output_types;
898 /* Whether we should send NULL infoframes. Required for audio. */
901 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
902 * has_dp_encoder is set. */
906 * Enable dithering, used when the selected pipe bpp doesn't match the
912 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
913 * compliance video pattern tests.
914 * Disable dither only if it is a compliance test request for
917 bool dither_force_disable;
919 /* Controls for the clock computation, to override various stages. */
922 /* SDVO TV has a bunch of special case. To make multifunction encoders
923 * work correctly, we need to track this at runtime.*/
927 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
928 * required. This is set in the 2nd loop of calling encoder's
929 * ->compute_config if the first pick doesn't work out.
933 /* Settings for the intel dpll used on pretty much everything but
937 /* Selected dpll when shared or NULL. */
938 struct intel_shared_dpll *shared_dpll;
940 /* Actual register state of the dpll, for shared dpll cross-checking. */
941 struct intel_dpll_hw_state dpll_hw_state;
944 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
945 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
947 struct icl_port_dpll {
948 struct intel_shared_dpll *pll;
949 struct intel_dpll_hw_state hw_state;
950 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
952 /* DSI PLL registers */
958 struct intel_link_m_n dp_m_n;
960 /* m2_n2 for eDP downclock */
961 struct intel_link_m_n dp_m2_n2;
966 bool enable_psr2_sel_fetch;
970 * Frequence the dpll for the port should run at. Differs from the
971 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
972 * already multiplied by pixel_multiplier.
976 /* Used by SDVO (and if we ever fix it, HDMI). */
977 unsigned pixel_multiplier;
979 /* I915_MODE_FLAG_* */
985 * Used by platforms having DP/HDMI PHY with programmable lane
986 * latency optimization.
988 u8 lane_lat_optim_mask;
990 /* minimum acceptable voltage level */
991 u8 min_voltage_level;
993 /* Panel fitter controls for gen2-gen4 + VLV */
997 u32 lvds_border_bits;
1000 /* Panel fitter placement and size for Ironlake+ */
1002 struct drm_rect dst;
1007 /* FDI configuration, only valid if has_pch_encoder is set. */
1009 struct intel_link_m_n fdi_m_n;
1021 struct intel_crtc_scaler_state scaler_state;
1023 /* w/a for waiting 2 vblanks during crtc enable */
1024 enum pipe hsw_workaround_pipe;
1026 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1029 struct intel_crtc_wm_state wm;
1031 int min_cdclk[I915_MAX_PLANES];
1033 u32 data_rate[I915_MAX_PLANES];
1035 /* FIXME unify with data_rate[] */
1036 u64 plane_data_rate[I915_MAX_PLANES];
1037 u64 uv_plane_data_rate[I915_MAX_PLANES];
1039 /* Gamma mode programmed on the pipe */
1043 /* CSC mode programmed on the pipe */
1050 /* bitmask of visible planes (enum plane_id) */
1055 /* bitmask of planes that will be updated during the commit */
1061 union hdmi_infoframe avi;
1062 union hdmi_infoframe spd;
1063 union hdmi_infoframe hdmi;
1064 union hdmi_infoframe drm;
1065 struct drm_dp_vsc_sdp vsc;
1068 /* HDMI scrambling status */
1069 bool hdmi_scrambling;
1071 /* HDMI High TMDS char rate ratio */
1072 bool hdmi_high_tmds_clock_ratio;
1074 /* Output format RGB/YCBCR etc */
1075 enum intel_output_format output_format;
1077 /* enable pipe gamma? */
1080 /* enable pipe csc? */
1083 /* enable pipe big joiner? */
1086 /* big joiner slave crtc? */
1087 bool bigjoiner_slave;
1089 /* linked crtc for bigjoiner, either slave or master */
1090 struct intel_crtc *bigjoiner_linked_crtc;
1092 /* Display Stream compression state */
1094 bool compression_enable;
1098 struct drm_dsc_config config;
1101 /* HSW+ linetime watermarks */
1105 /* Forward Error correction State */
1108 /* Pointer to master transcoder in case of tiled displays */
1109 enum transcoder master_transcoder;
1111 /* Bitmask to indicate slaves attached */
1112 u8 sync_mode_slaves_mask;
1114 /* Only valid on TGL+ */
1115 enum transcoder mst_master_transcoder;
1117 /* For DSB related info */
1118 struct intel_dsb *dsb;
1120 u32 psr2_man_track_ctl;
1123 enum intel_pipe_crc_source {
1124 INTEL_PIPE_CRC_SOURCE_NONE,
1125 INTEL_PIPE_CRC_SOURCE_PLANE1,
1126 INTEL_PIPE_CRC_SOURCE_PLANE2,
1127 INTEL_PIPE_CRC_SOURCE_PLANE3,
1128 INTEL_PIPE_CRC_SOURCE_PLANE4,
1129 INTEL_PIPE_CRC_SOURCE_PLANE5,
1130 INTEL_PIPE_CRC_SOURCE_PLANE6,
1131 INTEL_PIPE_CRC_SOURCE_PLANE7,
1132 INTEL_PIPE_CRC_SOURCE_PIPE,
1133 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1134 INTEL_PIPE_CRC_SOURCE_TV,
1135 INTEL_PIPE_CRC_SOURCE_DP_B,
1136 INTEL_PIPE_CRC_SOURCE_DP_C,
1137 INTEL_PIPE_CRC_SOURCE_DP_D,
1138 INTEL_PIPE_CRC_SOURCE_AUTO,
1139 INTEL_PIPE_CRC_SOURCE_MAX,
1142 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1143 struct intel_pipe_crc {
1146 enum intel_pipe_crc_source source;
1150 struct drm_crtc base;
1153 * Whether the crtc and the connected output pipeline is active. Implies
1154 * that crtc->enabled is set, i.e. the current mode configuration has
1155 * some outputs connected to this crtc.
1160 /* I915_MODE_FLAG_* */
1163 unsigned long long enabled_power_domains;
1164 struct intel_overlay *overlay;
1166 struct intel_crtc_state *config;
1168 /* Access to these should be protected by dev_priv->irq_lock. */
1169 bool cpu_fifo_underrun_disabled;
1170 bool pch_fifo_underrun_disabled;
1172 /* per-pipe watermark state */
1174 /* watermarks currently being used */
1176 struct intel_pipe_wm ilk;
1177 struct vlv_wm_state vlv;
1178 struct g4x_wm_state g4x;
1182 int scanline_offset;
1185 unsigned start_vbl_count;
1186 ktime_t start_vbl_time;
1187 int min_vbl, max_vbl;
1191 /* scalers available on this crtc */
1194 #ifdef CONFIG_DEBUG_FS
1195 struct intel_pipe_crc pipe_crc;
1199 struct intel_plane {
1200 struct drm_plane base;
1201 enum i9xx_plane_id i9xx_plane;
1206 u32 frontbuffer_bit;
1209 u32 base, cntl, size;
1213 * NOTE: Do not place new plane state fields here (e.g., when adding
1214 * new plane properties). New runtime state should now be placed in
1215 * the intel_plane_state structure and accessed via plane_state.
1218 int (*min_width)(const struct drm_framebuffer *fb,
1220 unsigned int rotation);
1221 int (*max_width)(const struct drm_framebuffer *fb,
1223 unsigned int rotation);
1224 int (*max_height)(const struct drm_framebuffer *fb,
1226 unsigned int rotation);
1227 unsigned int (*max_stride)(struct intel_plane *plane,
1228 u32 pixel_format, u64 modifier,
1229 unsigned int rotation);
1230 void (*update_plane)(struct intel_plane *plane,
1231 const struct intel_crtc_state *crtc_state,
1232 const struct intel_plane_state *plane_state);
1233 void (*disable_plane)(struct intel_plane *plane,
1234 const struct intel_crtc_state *crtc_state);
1235 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1236 int (*check_plane)(struct intel_crtc_state *crtc_state,
1237 struct intel_plane_state *plane_state);
1238 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1239 const struct intel_plane_state *plane_state);
1240 void (*async_flip)(struct intel_plane *plane,
1241 const struct intel_crtc_state *crtc_state,
1242 const struct intel_plane_state *plane_state);
1245 struct intel_watermark_params {
1253 struct cxsr_latency {
1254 bool is_desktop : 1;
1259 u16 display_hpll_disable;
1261 u16 cursor_hpll_disable;
1264 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1265 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1266 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1267 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1268 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1269 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1270 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1271 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1272 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1275 i915_reg_t hdmi_reg;
1278 enum drm_dp_dual_mode_type type;
1283 struct intel_connector *attached_connector;
1284 struct cec_notifier *cec_notifier;
1287 struct intel_dp_mst_encoder;
1289 * enum link_m_n_set:
1290 * When platform provides two set of M_N registers for dp, we can
1291 * program them and switch between them incase of DRRS.
1292 * But When only one such register is provided, we have to program the
1293 * required divider value on that registers itself based on the DRRS state.
1295 * M1_N1 : Program dp_m_n on M1_N1 registers
1296 * dp_m2_n2 on M2_N2 registers (If supported)
1298 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1299 * M2_N2 registers are not supported
1303 /* Sets the m1_n1 and m2_n2 */
1308 struct intel_dp_compliance_data {
1311 u16 hdisplay, vdisplay;
1313 struct drm_dp_phy_test_params phytest;
1316 struct intel_dp_compliance {
1317 unsigned long test_type;
1318 struct intel_dp_compliance_data test_data;
1324 struct intel_dp_pcon_frl {
1326 int trained_rate_gbps;
1330 i915_reg_t output_reg;
1338 bool reset_link_params;
1339 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1340 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1341 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1342 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1343 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1344 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1345 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1347 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1349 int num_source_rates;
1350 const int *source_rates;
1351 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1353 int sink_rates[DP_MAX_SUPPORTED_RATES];
1354 bool use_rate_select;
1355 /* intersection of source and sink rates */
1356 int num_common_rates;
1357 int common_rates[DP_MAX_SUPPORTED_RATES];
1358 /* Max lane count for the current link */
1359 int max_link_lane_count;
1360 /* Max rate for the current link */
1362 /* sink or branch descriptor */
1363 struct drm_dp_desc desc;
1365 struct drm_dp_aux aux;
1366 u32 aux_busy_last_status;
1368 int panel_power_up_delay;
1369 int panel_power_down_delay;
1370 int panel_power_cycle_delay;
1371 int backlight_on_delay;
1372 int backlight_off_delay;
1373 struct delayed_work panel_vdd_work;
1374 bool want_panel_vdd;
1375 unsigned long last_power_on;
1376 unsigned long last_backlight_off;
1377 ktime_t panel_power_off_time;
1380 * Pipe whose power sequencer is currently locked into
1381 * this port. Only relevant on VLV/CHV.
1385 * Pipe currently driving the port. Used for preventing
1386 * the use of the PPS for any pipe currentrly driving
1387 * external DP as that will mess things up on VLV.
1389 enum pipe active_pipe;
1391 * Set if the sequencer may be reset due to a power transition,
1392 * requiring a reinitialization. Only relevant on BXT.
1395 struct edp_power_seq pps_delays;
1397 bool can_mst; /* this port supports mst */
1399 int active_mst_links;
1401 /* connector directly attached - won't be use for modeset in mst world */
1402 struct intel_connector *attached_connector;
1404 /* mst connector list */
1405 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1406 struct drm_dp_mst_topology_mgr mst_mgr;
1408 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1410 * This function returns the value we have to program the AUX_CTL
1411 * register with to kick off an AUX transaction.
1413 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1414 u32 aux_clock_divider);
1416 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1417 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1419 /* This is called before a link training is starterd */
1420 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1421 const struct intel_crtc_state *crtc_state);
1422 void (*set_link_train)(struct intel_dp *intel_dp,
1423 const struct intel_crtc_state *crtc_state,
1425 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1426 const struct intel_crtc_state *crtc_state);
1427 void (*set_signal_levels)(struct intel_dp *intel_dp,
1428 const struct intel_crtc_state *crtc_state);
1430 u8 (*preemph_max)(struct intel_dp *intel_dp);
1431 u8 (*voltage_max)(struct intel_dp *intel_dp,
1432 const struct intel_crtc_state *crtc_state);
1434 /* Displayport compliance testing */
1435 struct intel_dp_compliance compliance;
1437 /* Downstream facing port caps */
1439 int min_tmds_clock, max_tmds_clock;
1441 int pcon_max_frl_bw;
1443 bool ycbcr_444_to_420;
1447 /* Display stream compression testing */
1453 struct intel_dp_pcon_frl frl;
1456 enum lspcon_vendor {
1458 LSPCON_VENDOR_PARADE
1461 struct intel_lspcon {
1463 enum drm_lspcon_mode mode;
1464 enum lspcon_vendor vendor;
1467 struct intel_digital_port {
1468 struct intel_encoder base;
1469 u32 saved_port_bits;
1471 struct intel_hdmi hdmi;
1472 struct intel_lspcon lspcon;
1473 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1474 bool release_cl2_override;
1476 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1478 enum intel_display_power_domain ddi_io_power_domain;
1479 struct mutex tc_lock; /* protects the TypeC port mode */
1480 intel_wakeref_t tc_lock_wakeref;
1481 int tc_link_refcount;
1482 bool tc_legacy_port:1;
1483 char tc_port_name[8];
1484 enum tc_port_mode tc_mode;
1485 enum phy_fia tc_phy_fia;
1488 /* protects num_hdcp_streams reference count */
1489 struct mutex hdcp_mutex;
1490 /* the number of pipes using HDCP signalling out of this port */
1491 unsigned int num_hdcp_streams;
1493 void (*write_infoframe)(struct intel_encoder *encoder,
1494 const struct intel_crtc_state *crtc_state,
1496 const void *frame, ssize_t len);
1497 void (*read_infoframe)(struct intel_encoder *encoder,
1498 const struct intel_crtc_state *crtc_state,
1500 void *frame, ssize_t len);
1501 void (*set_infoframes)(struct intel_encoder *encoder,
1503 const struct intel_crtc_state *crtc_state,
1504 const struct drm_connector_state *conn_state);
1505 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1506 const struct intel_crtc_state *pipe_config);
1507 bool (*connected)(struct intel_encoder *encoder);
1510 struct intel_dp_mst_encoder {
1511 struct intel_encoder base;
1513 struct intel_digital_port *primary;
1514 struct intel_connector *connector;
1517 static inline enum dpio_channel
1518 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1520 switch (dig_port->base.port) {
1531 static inline enum dpio_phy
1532 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1534 switch (dig_port->base.port) {
1545 static inline enum dpio_channel
1546 vlv_pipe_to_channel(enum pipe pipe)
1559 static inline struct intel_crtc *
1560 intel_get_first_crtc(struct drm_i915_private *dev_priv)
1562 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1565 static inline struct intel_crtc *
1566 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1568 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
1569 drm_WARN_ON(&dev_priv->drm,
1570 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1571 return dev_priv->pipe_to_crtc_mapping[pipe];
1574 static inline struct intel_crtc *
1575 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1577 return dev_priv->plane_to_crtc_mapping[plane];
1580 struct intel_load_detect_pipe {
1581 struct drm_atomic_state *restore_state;
1584 static inline struct intel_encoder *
1585 intel_attached_encoder(struct intel_connector *connector)
1587 return connector->encoder;
1590 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1592 switch (encoder->type) {
1593 case INTEL_OUTPUT_DDI:
1594 case INTEL_OUTPUT_DP:
1595 case INTEL_OUTPUT_EDP:
1596 case INTEL_OUTPUT_HDMI:
1603 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1605 return encoder->type == INTEL_OUTPUT_DP_MST;
1608 static inline struct intel_dp_mst_encoder *
1609 enc_to_mst(struct intel_encoder *encoder)
1611 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1615 static inline struct intel_digital_port *
1616 enc_to_dig_port(struct intel_encoder *encoder)
1618 struct intel_encoder *intel_encoder = encoder;
1620 if (intel_encoder_is_dig_port(intel_encoder))
1621 return container_of(&encoder->base, struct intel_digital_port,
1623 else if (intel_encoder_is_mst(intel_encoder))
1624 return enc_to_mst(encoder)->primary;
1629 static inline struct intel_digital_port *
1630 intel_attached_dig_port(struct intel_connector *connector)
1632 return enc_to_dig_port(intel_attached_encoder(connector));
1635 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1637 return &enc_to_dig_port(encoder)->dp;
1640 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1642 return enc_to_intel_dp(intel_attached_encoder(connector));
1645 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1647 switch (encoder->type) {
1648 case INTEL_OUTPUT_DP:
1649 case INTEL_OUTPUT_EDP:
1651 case INTEL_OUTPUT_DDI:
1652 /* Skip pure HDMI/DVI DDI encoders */
1653 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1659 static inline struct intel_lspcon *
1660 enc_to_intel_lspcon(struct intel_encoder *encoder)
1662 return &enc_to_dig_port(encoder)->lspcon;
1665 static inline struct intel_digital_port *
1666 dp_to_dig_port(struct intel_dp *intel_dp)
1668 return container_of(intel_dp, struct intel_digital_port, dp);
1671 static inline struct intel_lspcon *
1672 dp_to_lspcon(struct intel_dp *intel_dp)
1674 return &dp_to_dig_port(intel_dp)->lspcon;
1677 static inline struct drm_i915_private *
1678 dp_to_i915(struct intel_dp *intel_dp)
1680 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1683 static inline struct intel_digital_port *
1684 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1686 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1689 static inline struct intel_plane_state *
1690 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1691 struct intel_plane *plane)
1693 struct drm_plane_state *ret =
1694 drm_atomic_get_plane_state(&state->base, &plane->base);
1697 return ERR_CAST(ret);
1699 return to_intel_plane_state(ret);
1702 static inline struct intel_plane_state *
1703 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1704 struct intel_plane *plane)
1706 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1710 static inline struct intel_plane_state *
1711 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1712 struct intel_plane *plane)
1714 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1718 static inline struct intel_crtc_state *
1719 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1720 struct intel_crtc *crtc)
1722 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1726 static inline struct intel_crtc_state *
1727 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1728 struct intel_crtc *crtc)
1730 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1734 static inline struct intel_digital_connector_state *
1735 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1736 struct intel_connector *connector)
1738 return to_intel_digital_connector_state(
1739 drm_atomic_get_new_connector_state(&state->base,
1743 static inline struct intel_digital_connector_state *
1744 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1745 struct intel_connector *connector)
1747 return to_intel_digital_connector_state(
1748 drm_atomic_get_old_connector_state(&state->base,
1752 /* intel_display.c */
1754 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1755 enum intel_output_type type)
1757 return crtc_state->output_types & (1 << type);
1760 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1762 return crtc_state->output_types &
1763 ((1 << INTEL_OUTPUT_DP) |
1764 (1 << INTEL_OUTPUT_DP_MST) |
1765 (1 << INTEL_OUTPUT_EDP));
1769 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1771 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1773 drm_crtc_wait_one_vblank(&crtc->base);
1777 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1779 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1782 intel_wait_for_vblank(dev_priv, pipe);
1785 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1787 return i915_ggtt_offset(state->vma);
1790 #endif /* __INTEL_DISPLAY_TYPES_H__ */