2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/i2c.h>
30 #include <linux/pm_qos.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
34 #include <drm/display/drm_dp_dual_mode_helper.h>
35 #include <drm/display/drm_dp_mst_helper.h>
36 #include <drm/display/drm_dsc.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_encoder.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_framebuffer.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_rect.h>
44 #include <drm/drm_vblank.h>
45 #include <drm/drm_vblank_work.h>
46 #include <drm/i915_hdcp_interface.h>
47 #include <media/cec-notifier.h>
50 #include "i915_vma_types.h"
51 #include "intel_bios.h"
52 #include "intel_display.h"
53 #include "intel_display_limits.h"
54 #include "intel_display_power.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_wm_types.h"
59 struct __intel_global_objs_state;
60 struct intel_ddi_buf_trans;
62 struct intel_connector;
66 * Display related stuff
69 /* these are outputs from the chip - integrated only
70 external chips are via DVO or SDVO output */
71 enum intel_output_type {
72 INTEL_OUTPUT_UNUSED = 0,
73 INTEL_OUTPUT_ANALOG = 1,
75 INTEL_OUTPUT_SDVO = 3,
76 INTEL_OUTPUT_LVDS = 4,
77 INTEL_OUTPUT_TVOUT = 5,
78 INTEL_OUTPUT_HDMI = 6,
82 INTEL_OUTPUT_DDI = 10,
83 INTEL_OUTPUT_DP_MST = 11,
86 enum hdmi_force_audio {
87 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
88 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
89 HDMI_AUDIO_AUTO, /* trust EDID */
90 HDMI_AUDIO_ON, /* force turn on HDMI audio */
93 /* "Broadcast RGB" property */
94 enum intel_broadcast_rgb {
95 INTEL_BROADCAST_RGB_AUTO,
96 INTEL_BROADCAST_RGB_FULL,
97 INTEL_BROADCAST_RGB_LIMITED,
100 struct intel_fb_view {
102 * The remap information used in the remapped and rotated views to
103 * create the DMA scatter-gather list for each FB color plane. This sg
104 * list is created along with the view type (gtt.type) specific
105 * i915_vma object and contains the list of FB object pages (reordered
106 * in the rotated view) that are visible in the view.
107 * In the normal view the FB object's backing store sg list is used
108 * directly and hence the remap information here is not used.
110 struct i915_gtt_view gtt;
113 * The GTT view (gtt.type) specific information for each FB color
114 * plane. In the normal GTT view all formats (up to 4 color planes),
115 * in the rotated and remapped GTT view all no-CCS formats (up to 2
116 * color planes) are supported.
118 * The view information shared by all FB color planes in the FB,
119 * like dst x/y and src/dst width, is stored separately in
122 struct i915_color_plane_view {
127 * bytes for 0/180 degree rotation
128 * pixels for 90/270 degree rotation
130 unsigned int mapping_stride;
131 unsigned int scanout_stride;
135 struct intel_framebuffer {
136 struct drm_framebuffer base;
137 struct intel_frontbuffer *frontbuffer;
139 /* Params to remap the FB pages and program the plane registers in each view. */
140 struct intel_fb_view normal_view;
142 struct intel_fb_view rotated_view;
143 struct intel_fb_view remapped_view;
146 struct i915_address_space *dpt_vm;
149 enum intel_hotplug_state {
150 INTEL_HOTPLUG_UNCHANGED,
151 INTEL_HOTPLUG_CHANGED,
155 struct intel_encoder {
156 struct drm_encoder base;
158 enum intel_output_type type;
162 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
163 struct intel_connector *connector);
164 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
165 struct intel_crtc_state *,
166 struct drm_connector_state *);
167 int (*compute_config)(struct intel_encoder *,
168 struct intel_crtc_state *,
169 struct drm_connector_state *);
170 int (*compute_config_late)(struct intel_encoder *,
171 struct intel_crtc_state *,
172 struct drm_connector_state *);
173 void (*pre_pll_enable)(struct intel_atomic_state *,
174 struct intel_encoder *,
175 const struct intel_crtc_state *,
176 const struct drm_connector_state *);
177 void (*pre_enable)(struct intel_atomic_state *,
178 struct intel_encoder *,
179 const struct intel_crtc_state *,
180 const struct drm_connector_state *);
181 void (*enable)(struct intel_atomic_state *,
182 struct intel_encoder *,
183 const struct intel_crtc_state *,
184 const struct drm_connector_state *);
185 void (*disable)(struct intel_atomic_state *,
186 struct intel_encoder *,
187 const struct intel_crtc_state *,
188 const struct drm_connector_state *);
189 void (*post_disable)(struct intel_atomic_state *,
190 struct intel_encoder *,
191 const struct intel_crtc_state *,
192 const struct drm_connector_state *);
193 void (*post_pll_disable)(struct intel_atomic_state *,
194 struct intel_encoder *,
195 const struct intel_crtc_state *,
196 const struct drm_connector_state *);
197 void (*update_pipe)(struct intel_atomic_state *,
198 struct intel_encoder *,
199 const struct intel_crtc_state *,
200 const struct drm_connector_state *);
201 /* Read out the current hw state of this connector, returning true if
202 * the encoder is active. If the encoder is enabled it also set the pipe
203 * it is connected to in the pipe parameter. */
204 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
205 /* Reconstructs the equivalent mode flags for the current hardware
206 * state. This must be called _after_ display->get_pipe_config has
207 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
208 * be set correctly before calling this function. */
209 void (*get_config)(struct intel_encoder *,
210 struct intel_crtc_state *pipe_config);
213 * Optional hook called during init/resume to sync any state
214 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
216 void (*sync_state)(struct intel_encoder *encoder,
217 const struct intel_crtc_state *crtc_state);
220 * Optional hook, returning true if this encoder allows a fastset
221 * during the initial commit, false otherwise.
223 bool (*initial_fastset_check)(struct intel_encoder *encoder,
224 struct intel_crtc_state *crtc_state);
227 * Acquires the power domains needed for an active encoder during
228 * hardware state readout.
230 void (*get_power_domains)(struct intel_encoder *encoder,
231 struct intel_crtc_state *crtc_state);
233 * Called during system suspend after all pending requests for the
234 * encoder are flushed (for example for DP AUX transactions) and
235 * device interrupts are disabled.
236 * All modeset locks are held while the hook is called.
238 void (*suspend)(struct intel_encoder *);
240 * Called without the modeset locks held after the suspend() hook for
241 * all encoders have been called.
243 void (*suspend_complete)(struct intel_encoder *encoder);
245 * Called during system reboot/shutdown after all the
246 * encoders have been disabled and suspended.
247 * All modeset locks are held while the hook is called.
249 void (*shutdown)(struct intel_encoder *encoder);
251 * Called without the modeset locks held after the shutdown() hook for
252 * all encoders have been called.
254 void (*shutdown_complete)(struct intel_encoder *encoder);
256 * Enable/disable the clock to the port.
258 void (*enable_clock)(struct intel_encoder *encoder,
259 const struct intel_crtc_state *crtc_state);
260 void (*disable_clock)(struct intel_encoder *encoder);
262 * Returns whether the port clock is enabled or not.
264 bool (*is_clock_enabled)(struct intel_encoder *encoder);
266 * Returns the PLL type the port uses.
268 enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder,
269 const struct intel_crtc_state *crtc_state);
270 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
271 const struct intel_crtc_state *crtc_state,
273 void (*set_signal_levels)(struct intel_encoder *encoder,
274 const struct intel_crtc_state *crtc_state);
276 enum hpd_pin hpd_pin;
277 enum intel_display_power_domain power_domain;
279 /* VBT information for this encoder (may be NULL for older platforms) */
280 const struct intel_bios_encoder_data *devdata;
283 struct intel_panel_bl_funcs {
284 /* Connector and platform specific backlight functions */
285 int (*setup)(struct intel_connector *connector, enum pipe pipe);
286 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
287 void (*set)(const struct drm_connector_state *conn_state, u32 level);
288 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
289 void (*enable)(const struct intel_crtc_state *crtc_state,
290 const struct drm_connector_state *conn_state, u32 level);
291 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
300 struct intel_vbt_panel_data {
301 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
302 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
306 unsigned int lvds_dither:1;
307 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
311 u8 seamless_drrs_min_refresh_rate;
312 enum drrs_type drrs_type;
321 struct edp_power_seq pps;
322 u8 drrs_msa_timing_delay;
331 bool require_aux_wakeup;
333 int tp1_wakeup_time_us;
334 int tp2_tp3_wakeup_time_us;
335 int psr2_tp2_tp3_wakeup_time_us;
340 u16 brightness_precision_bits;
341 u16 hdr_dpcd_refresh_timeout;
344 u8 min_brightness; /* min_brightness/255 of max */
345 s8 controller; /* brightness controller number */
346 enum intel_backlight_type type;
352 struct mipi_config *config;
353 struct mipi_pps_data *pps;
359 const u8 *sequence[MIPI_SEQ_MAX];
360 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
361 enum drm_panel_orientation orientation;
366 /* Fixed EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
367 const struct drm_edid *fixed_edid;
369 struct list_head fixed_modes;
378 bool combination_mode; /* gen 2/4 only */
380 bool alternate_pwm_increment; /* lpt+ */
386 bool util_pin_active_low; /* bxt+ */
387 u8 controller; /* bxt+ only */
388 struct pwm_device *pwm;
389 struct pwm_state pwm_state;
394 struct drm_edp_backlight_info info;
401 struct backlight_device *device;
403 const struct intel_panel_bl_funcs *funcs;
404 const struct intel_panel_bl_funcs *pwm_funcs;
405 void (*power)(struct intel_connector *, bool enable);
408 struct intel_vbt_panel_data vbt;
411 struct intel_digital_port;
413 enum check_link_response {
414 HDCP_LINK_PROTECTED = 0,
415 HDCP_TOPOLOGY_CHANGE,
416 HDCP_LINK_INTEGRITY_FAILURE,
421 * This structure serves as a translation layer between the generic HDCP code
422 * and the bus-specific code. What that means is that HDCP over HDMI differs
423 * from HDCP over DP, so to account for these differences, we need to
424 * communicate with the receiver through this shim.
426 * For completeness, the 2 buses differ in the following ways:
428 * HDCP registers on the receiver are set via DP AUX for DP, and
429 * they are set via DDC for HDMI.
430 * - Receiver register offsets
431 * The offsets of the registers are different for DP vs. HDMI
432 * - Receiver register masks/offsets
433 * For instance, the ready bit for the KSV fifo is in a different
434 * place on DP vs HDMI
435 * - Receiver register names
436 * Seriously. In the DP spec, the 16-bit register containing
437 * downstream information is called BINFO, on HDMI it's called
438 * BSTATUS. To confuse matters further, DP has a BSTATUS register
439 * with a completely different definition.
441 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
442 * be read 3 keys at a time
444 * Since Aksv is hidden in hardware, there's different procedures
445 * to send it over DP AUX vs DDC
447 struct intel_hdcp_shim {
448 /* Outputs the transmitter's An and Aksv values to the receiver. */
449 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
451 /* Reads the receiver's key selection vector */
452 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
455 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
456 * definitions are the same in the respective specs, but the names are
457 * different. Call it BSTATUS since that's the name the HDMI spec
458 * uses and it was there first.
460 int (*read_bstatus)(struct intel_digital_port *dig_port,
463 /* Determines whether a repeater is present downstream */
464 int (*repeater_present)(struct intel_digital_port *dig_port,
465 bool *repeater_present);
467 /* Reads the receiver's Ri' value */
468 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
470 /* Determines if the receiver's KSV FIFO is ready for consumption */
471 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
474 /* Reads the ksv fifo for num_downstream devices */
475 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
476 int num_downstream, u8 *ksv_fifo);
478 /* Reads a 32-bit part of V' from the receiver */
479 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
482 /* Enables HDCP signalling on the port */
483 int (*toggle_signalling)(struct intel_digital_port *dig_port,
484 enum transcoder cpu_transcoder,
487 /* Enable/Disable stream encryption on DP MST Transport Link */
488 int (*stream_encryption)(struct intel_connector *connector,
491 /* Ensures the link is still protected */
492 bool (*check_link)(struct intel_digital_port *dig_port,
493 struct intel_connector *connector);
495 /* Detects panel's hdcp capability. This is optional for HDMI. */
496 int (*hdcp_capable)(struct intel_digital_port *dig_port,
499 /* HDCP adaptation(DP/HDMI) required on the port */
500 enum hdcp_wired_protocol protocol;
502 /* Detects whether sink is HDCP2.2 capable */
503 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
506 /* Write HDCP2.2 messages */
507 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
508 void *buf, size_t size);
510 /* Read HDCP2.2 messages */
511 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
512 u8 msg_id, void *buf, size_t size);
515 * Implementation of DP HDCP2.2 Errata for the communication of stream
516 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
517 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
519 int (*config_stream_type)(struct intel_digital_port *dig_port,
520 bool is_repeater, u8 type);
522 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
523 int (*stream_2_2_encryption)(struct intel_connector *connector,
526 /* HDCP2.2 Link Integrity Check */
527 int (*check_2_2_link)(struct intel_digital_port *dig_port,
528 struct intel_connector *connector);
532 const struct intel_hdcp_shim *shim;
533 /* Mutex for hdcp state of the connector */
536 struct delayed_work check_work;
537 struct work_struct prop_work;
539 /* HDCP1.4 Encryption status */
542 /* HDCP2.2 related definitions */
543 /* Flag indicates whether this connector supports HDCP2.2 or not. */
544 bool hdcp2_supported;
546 /* HDCP2.2 Encryption status */
547 bool hdcp2_encrypted;
550 * Content Stream Type defined by content owner. TYPE0(0x0) content can
551 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
552 * content can flow only through a link protected by HDCP2.2.
560 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
561 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
562 * When it rolls over re-auth has to be triggered.
567 * Count of RepeaterAuth_Stream_Manage msg propagated.
568 * Initialized to 0 on AKE_INIT. Incremented after every successful
569 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
570 * over re-Auth has to be triggered.
575 * Work queue to signal the CP_IRQ. Used for the waiters to read the
576 * available information from HDCP DP sink.
578 wait_queue_head_t cp_irq_queue;
579 atomic_t cp_irq_count;
580 int cp_irq_count_cached;
583 * HDCP register access for gen12+ need the transcoder associated.
584 * Transcoder attached to the connector could be changed at modeset.
585 * Hence caching the transcoder here.
587 enum transcoder cpu_transcoder;
588 /* Only used for DP MST stream encryption */
589 enum transcoder stream_transcoder;
592 struct intel_connector {
593 struct drm_connector base;
595 * The fixed encoder this connector is connected to.
597 struct intel_encoder *encoder;
599 /* ACPI device id for ACPI and driver cooperation */
602 /* Reads out the current hw, returning true if the connector is enabled
603 * and active (i.e. dpms ON state). */
604 bool (*get_hw_state)(struct intel_connector *);
606 /* Panel info for eDP and LVDS */
607 struct intel_panel panel;
609 /* Cached EDID for detect. */
610 const struct drm_edid *detect_edid;
612 /* Number of times hotplug detection was tried after an HPD interrupt */
615 /* since POLL and HPD connectors may use the same HPD line keep the native
616 state of connector->polled in case hotplug storm detection changes it */
619 struct drm_dp_mst_port *port;
621 struct intel_dp *mst_port;
623 /* Work struct to schedule a uevent on link train failure */
624 struct work_struct modeset_retry_work;
626 struct intel_hdcp hdcp;
629 struct intel_digital_connector_state {
630 struct drm_connector_state base;
632 enum hdmi_force_audio force_audio;
636 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
650 struct intel_atomic_state {
651 struct drm_atomic_state base;
653 intel_wakeref_t wakeref;
655 struct __intel_global_objs_state *global_objs;
658 /* Internal commit, as opposed to userspace/client initiated one */
661 bool dpll_set, modeset;
663 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
666 * Current watermarks can't be trusted during hardware readout, so
667 * don't bother calculating intermediate watermarks.
669 bool skip_intermediate_wm;
671 bool rps_interactive;
673 struct i915_sw_fence commit_ready;
675 struct llist_node freed;
678 struct intel_plane_state {
679 struct drm_plane_state uapi;
682 * actual hardware state, the state we program to the hardware.
683 * The following members are used to verify the hardware state:
684 * During initial hw readout, they need to be copied from uapi.
687 struct drm_crtc *crtc;
688 struct drm_framebuffer *fb;
691 u16 pixel_blend_mode;
692 unsigned int rotation;
693 enum drm_color_encoding color_encoding;
694 enum drm_color_range color_range;
695 enum drm_scaling_filter scaling_filter;
698 struct i915_vma *ggtt_vma;
699 struct i915_vma *dpt_vma;
701 #define PLANE_HAS_FENCE BIT(0)
703 struct intel_fb_view view;
705 /* Plane pxp decryption state */
708 /* Plane state to display black pixels when pxp is borked */
711 /* plane control register */
714 /* plane color control register */
717 /* chroma upsampler control register */
722 * = -1 : not using a scaler
723 * >= 0 : using a scalers
725 * plane requiring a scaler:
726 * - During check_plane, its bit is set in
727 * crtc_state->scaler_state.scaler_users by calling helper function
728 * update_scaler_plane.
729 * - scaler_id indicates the scaler it got assigned.
731 * plane doesn't require a scaler:
732 * - this can happen when scaling is no more required or plane simply
734 * - During check_plane, corresponding bit is reset in
735 * crtc_state->scaler_state.scaler_users by calling helper function
736 * update_scaler_plane.
741 * planar_linked_plane:
743 * ICL planar formats require 2 planes that are updated as pairs.
744 * This member is used to make sure the other plane is also updated
745 * when required, and for update_slave() to find the correct
746 * plane_state to pass as argument.
748 struct intel_plane *planar_linked_plane;
752 * If set don't update use the linked plane's state for updating
753 * this plane during atomic commit with the update_slave() callback.
755 * It's also used by the watermark code to ignore wm calculations on
756 * this plane. They're calculated by the linked plane's wm code.
760 struct drm_intel_sprite_colorkey ckey;
762 struct drm_rect psr2_sel_fetch_area;
764 /* Clear Color Value */
767 const char *no_fbc_reason;
770 struct intel_initial_plane_config {
771 struct intel_framebuffer *fb;
772 struct i915_vma *vma;
779 struct intel_scaler {
784 struct intel_crtc_scaler_state {
785 #define SKL_NUM_SCALERS 2
786 struct intel_scaler scalers[SKL_NUM_SCALERS];
789 * scaler_users: keeps track of users requesting scalers on this crtc.
791 * If a bit is set, a user is using a scaler.
792 * Here user can be a plane or crtc as defined below:
793 * bits 0-30 - plane (bit position is index from drm_plane_index)
796 * Instead of creating a new index to cover planes and crtc, using
797 * existing drm_plane_index for planes which is well less than 31
798 * planes and bit 31 for crtc. This should be fine to cover all
801 * intel_atomic_setup_scalers will setup available scalers to users
802 * requesting scalers. It will gracefully fail if request exceeds
805 #define SKL_CRTC_INDEX 31
806 unsigned scaler_users;
808 /* scaler used by crtc for panel fitting purpose */
812 /* {crtc,crtc_state}->mode_flags */
813 /* Flag to get scanline using frame time stamps */
814 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
815 /* Flag to use the scanline counter instead of the pixel counter */
816 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
818 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
819 * is operating in command mode.
820 * Flag to use TE from DSI0 instead of VBI in command mode
822 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
823 /* Flag to use TE from DSI1 instead of VBI in command mode */
824 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
825 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
826 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
827 /* Do tricks to make vblank timestamps sane with VRR? */
828 #define I915_MODE_FLAG_VRR (1<<6)
830 struct intel_wm_level {
838 struct intel_pipe_wm {
839 struct intel_wm_level wm[5];
842 bool sprites_enabled;
846 struct skl_wm_level {
855 struct skl_plane_wm {
856 struct skl_wm_level wm[8];
857 struct skl_wm_level uv_wm[8];
858 struct skl_wm_level trans_wm;
860 struct skl_wm_level wm0;
861 struct skl_wm_level trans_wm;
867 struct skl_plane_wm planes[I915_MAX_PLANES];
874 VLV_WM_LEVEL_DDR_DVFS,
878 struct vlv_wm_state {
879 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
880 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
885 struct vlv_fifo_state {
886 u16 plane[I915_MAX_PLANES];
896 struct g4x_wm_state {
897 struct g4x_pipe_wm wm;
899 struct g4x_sr_wm hpll;
905 struct intel_crtc_wm_state {
909 * The "raw" watermark values produced by the formula
910 * given the plane's current state. They do not consider
911 * how much FIFO is actually allocated for each plane.
914 * The "optimal" watermark values given the current
915 * state of the planes and the amount of FIFO
916 * allocated to each, ignoring any previous state
920 * The "intermediate" watermark values when transitioning
921 * between the old and new "optimal" values. Used when
922 * the watermark registers are single buffered and hence
923 * their state changes asynchronously with regards to the
924 * actual plane registers. These are essentially the
925 * worst case combination of the old and new "optimal"
926 * watermarks, which are therefore safe to use when the
927 * plane is in either its old or new state.
930 struct intel_pipe_wm intermediate;
931 struct intel_pipe_wm optimal;
935 struct skl_pipe_wm raw;
936 /* gen9+ only needs 1-step wm programming */
937 struct skl_pipe_wm optimal;
938 struct skl_ddb_entry ddb;
940 * pre-icl: for packed/planar CbCr
941 * icl+: for everything
943 struct skl_ddb_entry plane_ddb[I915_MAX_PLANES];
944 /* pre-icl: for planar Y */
945 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
949 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
950 struct vlv_wm_state intermediate; /* inverted */
951 struct vlv_wm_state optimal; /* inverted */
952 struct vlv_fifo_state fifo_state;
956 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
957 struct g4x_wm_state intermediate;
958 struct g4x_wm_state optimal;
963 * Platforms with two-step watermark programming will need to
964 * update watermark programming post-vblank to switch from the
965 * safe intermediate watermarks to the optimal final
968 bool need_postvbl_update;
971 enum intel_output_format {
972 INTEL_OUTPUT_FORMAT_RGB,
973 INTEL_OUTPUT_FORMAT_YCBCR420,
974 INTEL_OUTPUT_FORMAT_YCBCR444,
977 struct intel_mpllb_state {
978 u32 clock; /* in KHz */
989 /* Used by dp and fdi links */
990 struct intel_link_m_n {
998 struct intel_csc_matrix {
1004 struct intel_c10pll_state {
1005 u32 clock; /* in KHz */
1011 struct intel_c20pll_state {
1013 u32 clock; /* in kHz */
1022 struct intel_cx0pll_state {
1024 struct intel_c10pll_state c10;
1025 struct intel_c20pll_state c20;
1030 struct intel_crtc_state {
1032 * uapi (drm) state. This is the software state shown to userspace.
1033 * In particular, the following members are used for bookkeeping:
1041 struct drm_crtc_state uapi;
1044 * actual hardware state, the state we program to the hardware.
1045 * The following members are used to verify the hardware state:
1048 * - mode / pipe_mode / adjusted_mode
1049 * - color property blobs.
1051 * During initial hw readout, they need to be copied to uapi.
1053 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
1054 * Use the pipe_mode for calculations like watermarks, pipe
1055 * scaler, and bandwidth.
1057 * Use adjusted_mode for things that need to know the full
1058 * mode on the transcoder, which spans all pipes.
1061 bool active, enable;
1062 /* logical state of LUTs */
1063 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
1064 struct drm_display_mode mode, pipe_mode, adjusted_mode;
1065 enum drm_scaling_filter scaling_filter;
1068 /* actual state of LUTs */
1069 struct drm_property_blob *pre_csc_lut, *post_csc_lut;
1071 struct intel_csc_matrix csc, output_csc;
1074 * quirks - bitfield with hw state readout quirks
1076 * For various reasons the hw state readout code might not be able to
1077 * completely faithfully read out the current state. These cases are
1078 * tracked with quirk flags so that fastboot and state checker can act
1081 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
1082 unsigned long quirks;
1084 unsigned fb_bits; /* framebuffers to flip */
1085 bool update_pipe; /* can a fast modeset be performed? */
1087 bool update_wm_pre, update_wm_post; /* watermarks are updated */
1088 bool fifo_changed; /* FIFO split is changed */
1090 bool inherited; /* state inherited from BIOS? */
1092 /* Ask the hardware to actually async flip? */
1095 /* Pipe source size (ie. panel fitter input size)
1096 * All planes will be positioned inside this space,
1097 * and get clipped at the edges. */
1098 struct drm_rect pipe_src;
1101 * Pipe pixel rate, adjusted for
1102 * panel fitter/pipe scaler downscaling.
1104 unsigned int pixel_rate;
1106 /* Whether to set up the PCH/FDI. Note that we never allow sharing
1107 * between pch encoders and cpu encoders. */
1108 bool has_pch_encoder;
1110 /* Are we sending infoframes on the attached port */
1113 /* CPU Transcoder for the pipe. Currently this can only differ from the
1114 * pipe on Haswell and later (where we have a special eDP transcoder)
1115 * and Broxton (where we have special DSI transcoders). */
1116 enum transcoder cpu_transcoder;
1119 * Use reduced/limited/broadcast rbg range, compressing from the full
1120 * range fed into the crtcs.
1122 bool limited_color_range;
1124 /* Bitmask of encoder types (enum intel_output_type)
1125 * driven by the pipe.
1127 unsigned int output_types;
1129 /* Whether we should send NULL infoframes. Required for audio. */
1132 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
1133 * has_dp_encoder is set. */
1137 * Enable dithering, used when the selected pipe bpp doesn't match the
1143 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1144 * compliance video pattern tests.
1145 * Disable dither only if it is a compliance test request for
1148 bool dither_force_disable;
1150 /* Controls for the clock computation, to override various stages. */
1153 /* SDVO TV has a bunch of special case. To make multifunction encoders
1154 * work correctly, we need to track this at runtime.*/
1158 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1159 * required. This is set in the 2nd loop of calling encoder's
1160 * ->compute_config if the first pick doesn't work out.
1162 bool bw_constrained;
1164 /* Settings for the intel dpll used on pretty much everything but
1168 /* Selected dpll when shared or NULL. */
1169 struct intel_shared_dpll *shared_dpll;
1171 /* Actual register state of the dpll, for shared dpll cross-checking. */
1173 struct intel_dpll_hw_state dpll_hw_state;
1174 struct intel_mpllb_state mpllb_state;
1175 struct intel_cx0pll_state cx0pll_state;
1179 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1180 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1182 struct icl_port_dpll {
1183 struct intel_shared_dpll *pll;
1184 struct intel_dpll_hw_state hw_state;
1185 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1187 /* DSI PLL registers */
1193 struct intel_link_m_n dp_m_n;
1195 /* m2_n2 for eDP downclock */
1196 struct intel_link_m_n dp_m2_n2;
1200 /* PSR is supported but might not be enabled due the lack of enabled planes */
1203 bool enable_psr2_sel_fetch;
1204 bool req_psr2_sdp_prior_scanline;
1205 bool wm_level_disabled;
1207 u16 su_y_granularity;
1208 struct drm_dp_vsc_sdp psr_vsc;
1211 * Frequence the dpll for the port should run at. Differs from the
1212 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1213 * already multiplied by pixel_multiplier.
1217 /* Used by SDVO (and if we ever fix it, HDMI). */
1218 unsigned pixel_multiplier;
1220 /* I915_MODE_FLAG_* */
1226 * Used by platforms having DP/HDMI PHY with programmable lane
1227 * latency optimization.
1229 u8 lane_lat_optim_mask;
1231 /* minimum acceptable voltage level */
1232 u8 min_voltage_level;
1234 /* Panel fitter controls for gen2-gen4 + VLV */
1238 u32 lvds_border_bits;
1241 /* Panel fitter placement and size for Ironlake+ */
1243 struct drm_rect dst;
1248 /* FDI configuration, only valid if has_pch_encoder is set. */
1250 struct intel_link_m_n fdi_m_n;
1260 struct intel_crtc_scaler_state scaler_state;
1262 /* w/a for waiting 2 vblanks during crtc enable */
1263 enum pipe hsw_workaround_pipe;
1265 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1268 struct intel_crtc_wm_state wm;
1270 int min_cdclk[I915_MAX_PLANES];
1272 /* for packed/planar CbCr */
1273 u32 data_rate[I915_MAX_PLANES];
1275 u32 data_rate_y[I915_MAX_PLANES];
1277 /* FIXME unify with data_rate[]? */
1278 u64 rel_data_rate[I915_MAX_PLANES];
1279 u64 rel_data_rate_y[I915_MAX_PLANES];
1281 /* Gamma mode programmed on the pipe */
1285 /* CSC mode programmed on the pipe */
1292 /* bitmask of logically enabled planes (enum plane_id) */
1295 /* bitmask of actually visible planes (enum plane_id) */
1301 /* bitmask of planes that will be updated during the commit */
1304 /* bitmask of planes with async flip active */
1305 u8 async_flip_planes;
1307 u8 framestart_delay; /* 1-4 */
1308 u8 msa_timing_delay; /* 0-3 */
1313 union hdmi_infoframe avi;
1314 union hdmi_infoframe spd;
1315 union hdmi_infoframe hdmi;
1316 union hdmi_infoframe drm;
1317 struct drm_dp_vsc_sdp vsc;
1320 u8 eld[MAX_ELD_BYTES];
1322 /* HDMI scrambling status */
1323 bool hdmi_scrambling;
1325 /* HDMI High TMDS char rate ratio */
1326 bool hdmi_high_tmds_clock_ratio;
1329 * Output format RGB/YCBCR etc., that is coming out
1330 * at the end of the pipe.
1332 enum intel_output_format output_format;
1335 * Sink output format RGB/YCBCR etc., that is going
1338 enum intel_output_format sink_format;
1340 /* enable pipe gamma? */
1343 /* enable pipe csc? */
1346 /* enable vlv/chv wgc csc? */
1349 /* big joiner pipe bitmask */
1352 /* Display Stream compression state */
1354 bool compression_enable;
1358 struct drm_dsc_config config;
1361 /* HSW+ linetime watermarks */
1365 /* Forward Error correction State */
1368 bool sdp_split_enable;
1370 /* Pointer to master transcoder in case of tiled displays */
1371 enum transcoder master_transcoder;
1373 /* Bitmask to indicate slaves attached */
1374 u8 sync_mode_slaves_mask;
1376 /* Only valid on TGL+ */
1377 enum transcoder mst_master_transcoder;
1379 /* For DSB related info */
1380 struct intel_dsb *dsb;
1382 u32 psr2_man_track_ctl;
1384 /* Variable Refresh Rate state */
1388 u16 flipline, vmin, vmax, guardband;
1391 /* Stream Splitter for eDP MSO */
1398 /* for loading single buffered registers during vblank */
1399 struct drm_vblank_work vblank_work;
1402 enum intel_pipe_crc_source {
1403 INTEL_PIPE_CRC_SOURCE_NONE,
1404 INTEL_PIPE_CRC_SOURCE_PLANE1,
1405 INTEL_PIPE_CRC_SOURCE_PLANE2,
1406 INTEL_PIPE_CRC_SOURCE_PLANE3,
1407 INTEL_PIPE_CRC_SOURCE_PLANE4,
1408 INTEL_PIPE_CRC_SOURCE_PLANE5,
1409 INTEL_PIPE_CRC_SOURCE_PLANE6,
1410 INTEL_PIPE_CRC_SOURCE_PLANE7,
1411 INTEL_PIPE_CRC_SOURCE_PIPE,
1412 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1413 INTEL_PIPE_CRC_SOURCE_TV,
1414 INTEL_PIPE_CRC_SOURCE_DP_B,
1415 INTEL_PIPE_CRC_SOURCE_DP_C,
1416 INTEL_PIPE_CRC_SOURCE_DP_D,
1417 INTEL_PIPE_CRC_SOURCE_AUTO,
1418 INTEL_PIPE_CRC_SOURCE_MAX,
1421 enum drrs_refresh_rate {
1422 DRRS_REFRESH_RATE_HIGH,
1423 DRRS_REFRESH_RATE_LOW,
1426 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1427 struct intel_pipe_crc {
1430 enum intel_pipe_crc_source source;
1434 struct drm_crtc base;
1437 * Whether the crtc and the connected output pipeline is active. Implies
1438 * that crtc->enabled is set, i.e. the current mode configuration has
1439 * some outputs connected to this crtc.
1444 /* I915_MODE_FLAG_* */
1447 u16 vmax_vblank_start;
1449 struct intel_display_power_domain_set enabled_power_domains;
1450 struct intel_display_power_domain_set hw_readout_power_domains;
1451 struct intel_overlay *overlay;
1453 struct intel_crtc_state *config;
1455 /* Access to these should be protected by dev_priv->irq_lock. */
1456 bool cpu_fifo_underrun_disabled;
1457 bool pch_fifo_underrun_disabled;
1459 /* per-pipe watermark state */
1461 /* watermarks currently being used */
1463 struct intel_pipe_wm ilk;
1464 struct vlv_wm_state vlv;
1465 struct g4x_wm_state g4x;
1471 struct delayed_work work;
1472 enum drrs_refresh_rate refresh_rate;
1473 unsigned int frontbuffer_bits;
1474 unsigned int busy_frontbuffer_bits;
1475 enum transcoder cpu_transcoder;
1476 struct intel_link_m_n m_n, m2_n2;
1479 int scanline_offset;
1482 unsigned start_vbl_count;
1483 ktime_t start_vbl_time;
1484 int min_vbl, max_vbl;
1486 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1492 unsigned int times[17]; /* [1us, 16ms] */
1497 /* scalers available on this crtc */
1500 /* for loading single buffered registers during vblank */
1501 struct pm_qos_request vblank_pm_qos;
1503 #ifdef CONFIG_DEBUG_FS
1504 struct intel_pipe_crc pipe_crc;
1508 struct intel_plane {
1509 struct drm_plane base;
1510 enum i9xx_plane_id i9xx_plane;
1513 bool need_async_flip_disable_wa;
1514 u32 frontbuffer_bit;
1517 u32 base, cntl, size;
1520 struct intel_fbc *fbc;
1523 * NOTE: Do not place new plane state fields here (e.g., when adding
1524 * new plane properties). New runtime state should now be placed in
1525 * the intel_plane_state structure and accessed via plane_state.
1528 int (*min_width)(const struct drm_framebuffer *fb,
1530 unsigned int rotation);
1531 int (*max_width)(const struct drm_framebuffer *fb,
1533 unsigned int rotation);
1534 int (*max_height)(const struct drm_framebuffer *fb,
1536 unsigned int rotation);
1537 unsigned int (*max_stride)(struct intel_plane *plane,
1538 u32 pixel_format, u64 modifier,
1539 unsigned int rotation);
1540 /* Write all non-self arming plane registers */
1541 void (*update_noarm)(struct intel_plane *plane,
1542 const struct intel_crtc_state *crtc_state,
1543 const struct intel_plane_state *plane_state);
1544 /* Write all self-arming plane registers */
1545 void (*update_arm)(struct intel_plane *plane,
1546 const struct intel_crtc_state *crtc_state,
1547 const struct intel_plane_state *plane_state);
1548 /* Disable the plane, must arm */
1549 void (*disable_arm)(struct intel_plane *plane,
1550 const struct intel_crtc_state *crtc_state);
1551 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1552 int (*check_plane)(struct intel_crtc_state *crtc_state,
1553 struct intel_plane_state *plane_state);
1554 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1555 const struct intel_plane_state *plane_state);
1556 void (*async_flip)(struct intel_plane *plane,
1557 const struct intel_crtc_state *crtc_state,
1558 const struct intel_plane_state *plane_state,
1560 void (*enable_flip_done)(struct intel_plane *plane);
1561 void (*disable_flip_done)(struct intel_plane *plane);
1564 struct intel_watermark_params {
1572 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1573 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1574 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1575 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1576 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1577 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1578 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1579 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1580 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1583 i915_reg_t hdmi_reg;
1586 enum drm_dp_dual_mode_type type;
1591 struct intel_connector *attached_connector;
1592 struct cec_notifier *cec_notifier;
1595 struct intel_dp_mst_encoder;
1597 struct intel_dp_compliance_data {
1600 u16 hdisplay, vdisplay;
1602 struct drm_dp_phy_test_params phytest;
1605 struct intel_dp_compliance {
1606 unsigned long test_type;
1607 struct intel_dp_compliance_data test_data;
1613 struct intel_dp_pcon_frl {
1615 int trained_rate_gbps;
1619 int panel_power_up_delay;
1620 int panel_power_down_delay;
1621 int panel_power_cycle_delay;
1622 int backlight_on_delay;
1623 int backlight_off_delay;
1624 struct delayed_work panel_vdd_work;
1625 bool want_panel_vdd;
1627 unsigned long last_power_on;
1628 unsigned long last_backlight_off;
1629 ktime_t panel_power_off_time;
1630 intel_wakeref_t vdd_wakeref;
1634 * Pipe whose power sequencer is currently locked into
1635 * this port. Only relevant on VLV/CHV.
1640 * Power sequencer index. Only relevant on BXT+.
1646 * Pipe currently driving the port. Used for preventing
1647 * the use of the PPS for any pipe currentrly driving
1648 * external DP as that will mess things up on VLV.
1650 enum pipe active_pipe;
1652 * Set if the sequencer may be reset due to a power transition,
1653 * requiring a reinitialization. Only relevant on BXT+.
1656 struct edp_power_seq pps_delays;
1657 struct edp_power_seq bios_pps_delays;
1661 /* Mutex for PSR state of the transcoder */
1664 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1665 #define I915_PSR_DEBUG_DEFAULT 0x00
1666 #define I915_PSR_DEBUG_DISABLE 0x01
1667 #define I915_PSR_DEBUG_ENABLE 0x02
1668 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1669 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1670 #define I915_PSR_DEBUG_IRQ 0x10
1674 bool source_support;
1678 enum transcoder transcoder;
1680 struct work_struct work;
1681 unsigned int busy_frontbuffer_bits;
1682 bool sink_psr2_support;
1684 bool colorimetry_support;
1686 bool psr2_sel_fetch_enabled;
1687 bool psr2_sel_fetch_cff_enabled;
1688 bool req_psr2_sdp_prior_scanline;
1689 u8 sink_sync_latency;
1692 ktime_t last_entry_attempt;
1694 bool sink_not_reliable;
1696 u16 su_w_granularity;
1697 u16 su_y_granularity;
1699 u32 dc3co_exit_delay;
1700 struct delayed_work dc3co_work;
1704 i915_reg_t output_reg;
1711 bool reset_link_params;
1712 bool use_max_params;
1713 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1714 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1715 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1716 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1717 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1718 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1719 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1721 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1723 int num_source_rates;
1724 const int *source_rates;
1725 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1727 int sink_rates[DP_MAX_SUPPORTED_RATES];
1728 bool use_rate_select;
1729 /* Max sink lane count as reported by DP_MAX_LANE_COUNT */
1730 int max_sink_lane_count;
1731 /* intersection of source and sink rates */
1732 int num_common_rates;
1733 int common_rates[DP_MAX_SUPPORTED_RATES];
1734 /* Max lane count for the current link */
1735 int max_link_lane_count;
1736 /* Max rate for the current link */
1739 int mso_pixel_overlap;
1740 /* sink or branch descriptor */
1741 struct drm_dp_desc desc;
1742 struct drm_dp_aux aux;
1743 u32 aux_busy_last_status;
1746 struct intel_pps pps;
1749 int active_mst_links;
1751 /* connector directly attached - won't be use for modeset in mst world */
1752 struct intel_connector *attached_connector;
1754 /* mst connector list */
1755 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1756 struct drm_dp_mst_topology_mgr mst_mgr;
1758 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1760 * This function returns the value we have to program the AUX_CTL
1761 * register with to kick off an AUX transaction.
1763 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1764 u32 aux_clock_divider);
1766 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1767 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1769 /* This is called before a link training is starterd */
1770 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1771 const struct intel_crtc_state *crtc_state);
1772 void (*set_link_train)(struct intel_dp *intel_dp,
1773 const struct intel_crtc_state *crtc_state,
1775 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1776 const struct intel_crtc_state *crtc_state);
1778 u8 (*preemph_max)(struct intel_dp *intel_dp);
1779 u8 (*voltage_max)(struct intel_dp *intel_dp,
1780 const struct intel_crtc_state *crtc_state);
1782 /* Displayport compliance testing */
1783 struct intel_dp_compliance compliance;
1785 /* Downstream facing port caps */
1787 int min_tmds_clock, max_tmds_clock;
1789 int pcon_max_frl_bw;
1791 bool ycbcr_444_to_420;
1792 bool ycbcr420_passthrough;
1796 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1797 struct pm_qos_request pm_qos;
1799 /* Display stream compression testing */
1801 int force_dsc_output_format;
1807 struct intel_dp_pcon_frl frl;
1809 struct intel_psr psr;
1811 /* When we last wrote the OUI for eDP */
1812 unsigned long last_oui_write;
1815 enum lspcon_vendor {
1817 LSPCON_VENDOR_PARADE
1820 struct intel_lspcon {
1823 enum drm_lspcon_mode mode;
1824 enum lspcon_vendor vendor;
1827 struct intel_digital_port {
1828 struct intel_encoder base;
1829 u32 saved_port_bits;
1831 struct intel_hdmi hdmi;
1832 struct intel_lspcon lspcon;
1833 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1834 bool release_cl2_override;
1836 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1838 enum intel_display_power_domain ddi_io_power_domain;
1839 intel_wakeref_t ddi_io_wakeref;
1840 intel_wakeref_t aux_wakeref;
1842 struct intel_tc_port *tc;
1844 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1845 struct mutex hdcp_mutex;
1846 /* the number of pipes using HDCP signalling out of this port */
1847 unsigned int num_hdcp_streams;
1848 /* port HDCP auth status */
1849 bool hdcp_auth_status;
1850 /* HDCP port data need to pass to security f/w */
1851 struct hdcp_port_data hdcp_port_data;
1852 /* Whether the MST topology supports HDCP Type 1 Content */
1853 bool hdcp_mst_type1_capable;
1855 void (*write_infoframe)(struct intel_encoder *encoder,
1856 const struct intel_crtc_state *crtc_state,
1858 const void *frame, ssize_t len);
1859 void (*read_infoframe)(struct intel_encoder *encoder,
1860 const struct intel_crtc_state *crtc_state,
1862 void *frame, ssize_t len);
1863 void (*set_infoframes)(struct intel_encoder *encoder,
1865 const struct intel_crtc_state *crtc_state,
1866 const struct drm_connector_state *conn_state);
1867 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1868 const struct intel_crtc_state *pipe_config);
1869 bool (*connected)(struct intel_encoder *encoder);
1872 struct intel_dp_mst_encoder {
1873 struct intel_encoder base;
1875 struct intel_digital_port *primary;
1876 struct intel_connector *connector;
1879 static inline struct intel_encoder *
1880 intel_attached_encoder(struct intel_connector *connector)
1882 return connector->encoder;
1885 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1887 switch (encoder->type) {
1888 case INTEL_OUTPUT_DDI:
1889 case INTEL_OUTPUT_DP:
1890 case INTEL_OUTPUT_EDP:
1891 case INTEL_OUTPUT_HDMI:
1898 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1900 return encoder->type == INTEL_OUTPUT_DP_MST;
1903 static inline struct intel_dp_mst_encoder *
1904 enc_to_mst(struct intel_encoder *encoder)
1906 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1910 static inline struct intel_digital_port *
1911 enc_to_dig_port(struct intel_encoder *encoder)
1913 struct intel_encoder *intel_encoder = encoder;
1915 if (intel_encoder_is_dig_port(intel_encoder))
1916 return container_of(&encoder->base, struct intel_digital_port,
1918 else if (intel_encoder_is_mst(intel_encoder))
1919 return enc_to_mst(encoder)->primary;
1924 static inline struct intel_digital_port *
1925 intel_attached_dig_port(struct intel_connector *connector)
1927 return enc_to_dig_port(intel_attached_encoder(connector));
1930 static inline struct intel_hdmi *
1931 enc_to_intel_hdmi(struct intel_encoder *encoder)
1933 return &enc_to_dig_port(encoder)->hdmi;
1936 static inline struct intel_hdmi *
1937 intel_attached_hdmi(struct intel_connector *connector)
1939 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1942 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1944 return &enc_to_dig_port(encoder)->dp;
1947 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1949 return enc_to_intel_dp(intel_attached_encoder(connector));
1952 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1954 switch (encoder->type) {
1955 case INTEL_OUTPUT_DP:
1956 case INTEL_OUTPUT_EDP:
1958 case INTEL_OUTPUT_DDI:
1959 /* Skip pure HDMI/DVI DDI encoders */
1960 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1966 static inline struct intel_lspcon *
1967 enc_to_intel_lspcon(struct intel_encoder *encoder)
1969 return &enc_to_dig_port(encoder)->lspcon;
1972 static inline struct intel_digital_port *
1973 dp_to_dig_port(struct intel_dp *intel_dp)
1975 return container_of(intel_dp, struct intel_digital_port, dp);
1978 static inline struct intel_lspcon *
1979 dp_to_lspcon(struct intel_dp *intel_dp)
1981 return &dp_to_dig_port(intel_dp)->lspcon;
1984 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
1986 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1987 (intel_dp)->psr.source_support)
1989 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
1991 if (!intel_encoder_is_dp(encoder))
1994 return CAN_PSR(enc_to_intel_dp(encoder));
1997 static inline struct intel_digital_port *
1998 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
2000 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
2003 static inline struct intel_plane_state *
2004 intel_atomic_get_plane_state(struct intel_atomic_state *state,
2005 struct intel_plane *plane)
2007 struct drm_plane_state *ret =
2008 drm_atomic_get_plane_state(&state->base, &plane->base);
2011 return ERR_CAST(ret);
2013 return to_intel_plane_state(ret);
2016 static inline struct intel_plane_state *
2017 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
2018 struct intel_plane *plane)
2020 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
2024 static inline struct intel_plane_state *
2025 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
2026 struct intel_plane *plane)
2028 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
2032 static inline struct intel_crtc_state *
2033 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
2034 struct intel_crtc *crtc)
2036 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
2040 static inline struct intel_crtc_state *
2041 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
2042 struct intel_crtc *crtc)
2044 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
2048 static inline struct intel_digital_connector_state *
2049 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
2050 struct intel_connector *connector)
2052 return to_intel_digital_connector_state(
2053 drm_atomic_get_new_connector_state(&state->base,
2057 static inline struct intel_digital_connector_state *
2058 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
2059 struct intel_connector *connector)
2061 return to_intel_digital_connector_state(
2062 drm_atomic_get_old_connector_state(&state->base,
2066 /* intel_display.c */
2068 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
2069 enum intel_output_type type)
2071 return crtc_state->output_types & BIT(type);
2075 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
2077 return crtc_state->output_types &
2078 (BIT(INTEL_OUTPUT_DP) |
2079 BIT(INTEL_OUTPUT_DP_MST) |
2080 BIT(INTEL_OUTPUT_EDP));
2084 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2086 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2090 intel_crtc_needs_fastset(const struct intel_crtc_state *crtc_state)
2092 return crtc_state->update_pipe;
2096 intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state)
2098 return crtc_state->uapi.color_mgmt_changed ||
2099 intel_crtc_needs_fastset(crtc_state) ||
2100 intel_crtc_needs_modeset(crtc_state);
2103 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2105 return i915_ggtt_offset(plane_state->ggtt_vma);
2108 static inline struct intel_frontbuffer *
2109 to_intel_frontbuffer(struct drm_framebuffer *fb)
2111 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2114 #endif /* __INTEL_DISPLAY_TYPES_H__ */