2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/input.h>
29 #include <linux/intel-iommu.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/dma-resv.h>
33 #include <linux/slab.h>
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_atomic_uapi.h>
38 #include <drm/drm_damage_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_fourcc.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_probe_helper.h>
44 #include <drm/drm_rect.h>
46 #include "display/intel_crt.h"
47 #include "display/intel_ddi.h"
48 #include "display/intel_dp.h"
49 #include "display/intel_dp_mst.h"
50 #include "display/intel_dpll_mgr.h"
51 #include "display/intel_dsi.h"
52 #include "display/intel_dvo.h"
53 #include "display/intel_gmbus.h"
54 #include "display/intel_hdmi.h"
55 #include "display/intel_lvds.h"
56 #include "display/intel_sdvo.h"
57 #include "display/intel_tv.h"
58 #include "display/intel_vdsc.h"
60 #include "gt/intel_rps.h"
63 #include "i915_trace.h"
64 #include "intel_acpi.h"
65 #include "intel_atomic.h"
66 #include "intel_atomic_plane.h"
68 #include "intel_cdclk.h"
69 #include "intel_color.h"
70 #include "intel_csr.h"
71 #include "intel_display_types.h"
72 #include "intel_dp_link_training.h"
73 #include "intel_fbc.h"
74 #include "intel_fbdev.h"
75 #include "intel_fifo_underrun.h"
76 #include "intel_frontbuffer.h"
77 #include "intel_hdcp.h"
78 #include "intel_hotplug.h"
79 #include "intel_overlay.h"
80 #include "intel_pipe_crc.h"
82 #include "intel_psr.h"
83 #include "intel_quirks.h"
84 #include "intel_sideband.h"
85 #include "intel_sprite.h"
87 #include "intel_vga.h"
89 /* Primary plane formats for gen <= 3 */
90 static const u32 i8xx_primary_formats[] = {
97 /* Primary plane formats for ivb (no fp16 due to hw issue) */
98 static const u32 ivb_primary_formats[] = {
103 DRM_FORMAT_XRGB2101010,
104 DRM_FORMAT_XBGR2101010,
107 /* Primary plane formats for gen >= 4, except ivb */
108 static const u32 i965_primary_formats[] = {
113 DRM_FORMAT_XRGB2101010,
114 DRM_FORMAT_XBGR2101010,
115 DRM_FORMAT_XBGR16161616F,
118 /* Primary plane formats for vlv/chv */
119 static const u32 vlv_primary_formats[] = {
126 DRM_FORMAT_XRGB2101010,
127 DRM_FORMAT_XBGR2101010,
128 DRM_FORMAT_ARGB2101010,
129 DRM_FORMAT_ABGR2101010,
130 DRM_FORMAT_XBGR16161616F,
133 static const u64 i9xx_format_modifiers[] = {
134 I915_FORMAT_MOD_X_TILED,
135 DRM_FORMAT_MOD_LINEAR,
136 DRM_FORMAT_MOD_INVALID
140 static const u32 intel_cursor_formats[] = {
144 static const u64 cursor_format_modifiers[] = {
145 DRM_FORMAT_MOD_LINEAR,
146 DRM_FORMAT_MOD_INVALID
149 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
150 struct intel_crtc_state *pipe_config);
151 static void ilk_pch_clock_get(struct intel_crtc *crtc,
152 struct intel_crtc_state *pipe_config);
154 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
155 struct drm_i915_gem_object *obj,
156 struct drm_mode_fb_cmd2 *mode_cmd);
157 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
160 const struct intel_link_m_n *m_n,
161 const struct intel_link_m_n *m2_n2);
162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
166 static void vlv_prepare_pll(struct intel_crtc *crtc,
167 const struct intel_crtc_state *pipe_config);
168 static void chv_prepare_pll(struct intel_crtc *crtc,
169 const struct intel_crtc_state *pipe_config);
170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
172 static void intel_modeset_setup_hw_state(struct drm_device *dev,
173 struct drm_modeset_acquire_ctx *ctx);
174 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
179 } dot, vco, n, m, m1, m2, p, p1;
183 int p2_slow, p2_fast;
187 /* returns HPLL frequency in kHz */
188 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
190 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
192 /* Obtain SKU information */
193 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
194 CCK_FUSE_HPLL_FREQ_MASK;
196 return vco_freq[hpll_freq] * 1000;
199 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
200 const char *name, u32 reg, int ref_freq)
205 val = vlv_cck_read(dev_priv, reg);
206 divider = val & CCK_FREQUENCY_VALUES;
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
209 (divider << CCK_FREQUENCY_STATUS_SHIFT),
210 "%s change in progress\n", name);
212 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
215 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
216 const char *name, u32 reg)
220 vlv_cck_get(dev_priv);
222 if (dev_priv->hpll_freq == 0)
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
227 vlv_cck_put(dev_priv);
232 static void intel_update_czclk(struct drm_i915_private *dev_priv)
234 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL);
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
241 dev_priv->czclk_freq);
244 /* units of 100MHz */
245 static u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
246 const struct intel_crtc_state *pipe_config)
248 if (HAS_DDI(dev_priv))
249 return pipe_config->port_clock; /* SPLL */
251 return dev_priv->fdi_pll_freq;
254 static const struct intel_limit intel_limits_i8xx_dac = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 2, .max = 33 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 4, .p2_fast = 2 },
267 static const struct intel_limit intel_limits_i8xx_dvo = {
268 .dot = { .min = 25000, .max = 350000 },
269 .vco = { .min = 908000, .max = 1512000 },
270 .n = { .min = 2, .max = 16 },
271 .m = { .min = 96, .max = 140 },
272 .m1 = { .min = 18, .max = 26 },
273 .m2 = { .min = 6, .max = 16 },
274 .p = { .min = 4, .max = 128 },
275 .p1 = { .min = 2, .max = 33 },
276 .p2 = { .dot_limit = 165000,
277 .p2_slow = 4, .p2_fast = 4 },
280 static const struct intel_limit intel_limits_i8xx_lvds = {
281 .dot = { .min = 25000, .max = 350000 },
282 .vco = { .min = 908000, .max = 1512000 },
283 .n = { .min = 2, .max = 16 },
284 .m = { .min = 96, .max = 140 },
285 .m1 = { .min = 18, .max = 26 },
286 .m2 = { .min = 6, .max = 16 },
287 .p = { .min = 4, .max = 128 },
288 .p1 = { .min = 1, .max = 6 },
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 14, .p2_fast = 7 },
293 static const struct intel_limit intel_limits_i9xx_sdvo = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1400000, .max = 2800000 },
296 .n = { .min = 1, .max = 6 },
297 .m = { .min = 70, .max = 120 },
298 .m1 = { .min = 8, .max = 18 },
299 .m2 = { .min = 3, .max = 7 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 200000,
303 .p2_slow = 10, .p2_fast = 5 },
306 static const struct intel_limit intel_limits_i9xx_lvds = {
307 .dot = { .min = 20000, .max = 400000 },
308 .vco = { .min = 1400000, .max = 2800000 },
309 .n = { .min = 1, .max = 6 },
310 .m = { .min = 70, .max = 120 },
311 .m1 = { .min = 8, .max = 18 },
312 .m2 = { .min = 3, .max = 7 },
313 .p = { .min = 7, .max = 98 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 112000,
316 .p2_slow = 14, .p2_fast = 7 },
320 static const struct intel_limit intel_limits_g4x_sdvo = {
321 .dot = { .min = 25000, .max = 270000 },
322 .vco = { .min = 1750000, .max = 3500000},
323 .n = { .min = 1, .max = 4 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 10, .max = 30 },
328 .p1 = { .min = 1, .max = 3},
329 .p2 = { .dot_limit = 270000,
335 static const struct intel_limit intel_limits_g4x_hdmi = {
336 .dot = { .min = 22000, .max = 400000 },
337 .vco = { .min = 1750000, .max = 3500000},
338 .n = { .min = 1, .max = 4 },
339 .m = { .min = 104, .max = 138 },
340 .m1 = { .min = 16, .max = 23 },
341 .m2 = { .min = 5, .max = 11 },
342 .p = { .min = 5, .max = 80 },
343 .p1 = { .min = 1, .max = 8},
344 .p2 = { .dot_limit = 165000,
345 .p2_slow = 10, .p2_fast = 5 },
348 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
349 .dot = { .min = 20000, .max = 115000 },
350 .vco = { .min = 1750000, .max = 3500000 },
351 .n = { .min = 1, .max = 3 },
352 .m = { .min = 104, .max = 138 },
353 .m1 = { .min = 17, .max = 23 },
354 .m2 = { .min = 5, .max = 11 },
355 .p = { .min = 28, .max = 112 },
356 .p1 = { .min = 2, .max = 8 },
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 14, .p2_fast = 14
362 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
363 .dot = { .min = 80000, .max = 224000 },
364 .vco = { .min = 1750000, .max = 3500000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 104, .max = 138 },
367 .m1 = { .min = 17, .max = 23 },
368 .m2 = { .min = 5, .max = 11 },
369 .p = { .min = 14, .max = 42 },
370 .p1 = { .min = 2, .max = 6 },
371 .p2 = { .dot_limit = 0,
372 .p2_slow = 7, .p2_fast = 7
376 static const struct intel_limit pnv_limits_sdvo = {
377 .dot = { .min = 20000, .max = 400000},
378 .vco = { .min = 1700000, .max = 3500000 },
379 /* Pineview's Ncounter is a ring counter */
380 .n = { .min = 3, .max = 6 },
381 .m = { .min = 2, .max = 256 },
382 /* Pineview only has one combined m divider, which we treat as m2. */
383 .m1 = { .min = 0, .max = 0 },
384 .m2 = { .min = 0, .max = 254 },
385 .p = { .min = 5, .max = 80 },
386 .p1 = { .min = 1, .max = 8 },
387 .p2 = { .dot_limit = 200000,
388 .p2_slow = 10, .p2_fast = 5 },
391 static const struct intel_limit pnv_limits_lvds = {
392 .dot = { .min = 20000, .max = 400000 },
393 .vco = { .min = 1700000, .max = 3500000 },
394 .n = { .min = 3, .max = 6 },
395 .m = { .min = 2, .max = 256 },
396 .m1 = { .min = 0, .max = 0 },
397 .m2 = { .min = 0, .max = 254 },
398 .p = { .min = 7, .max = 112 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 112000,
401 .p2_slow = 14, .p2_fast = 14 },
404 /* Ironlake / Sandybridge
406 * We calculate clock using (register_value + 2) for N/M1/M2, so here
407 * the range value for them is (actual_value - 2).
409 static const struct intel_limit ilk_limits_dac = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 5 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 5, .max = 80 },
417 .p1 = { .min = 1, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 10, .p2_fast = 5 },
422 static const struct intel_limit ilk_limits_single_lvds = {
423 .dot = { .min = 25000, .max = 350000 },
424 .vco = { .min = 1760000, .max = 3510000 },
425 .n = { .min = 1, .max = 3 },
426 .m = { .min = 79, .max = 118 },
427 .m1 = { .min = 12, .max = 22 },
428 .m2 = { .min = 5, .max = 9 },
429 .p = { .min = 28, .max = 112 },
430 .p1 = { .min = 2, .max = 8 },
431 .p2 = { .dot_limit = 225000,
432 .p2_slow = 14, .p2_fast = 14 },
435 static const struct intel_limit ilk_limits_dual_lvds = {
436 .dot = { .min = 25000, .max = 350000 },
437 .vco = { .min = 1760000, .max = 3510000 },
438 .n = { .min = 1, .max = 3 },
439 .m = { .min = 79, .max = 127 },
440 .m1 = { .min = 12, .max = 22 },
441 .m2 = { .min = 5, .max = 9 },
442 .p = { .min = 14, .max = 56 },
443 .p1 = { .min = 2, .max = 8 },
444 .p2 = { .dot_limit = 225000,
445 .p2_slow = 7, .p2_fast = 7 },
448 /* LVDS 100mhz refclk limits. */
449 static const struct intel_limit ilk_limits_single_lvds_100m = {
450 .dot = { .min = 25000, .max = 350000 },
451 .vco = { .min = 1760000, .max = 3510000 },
452 .n = { .min = 1, .max = 2 },
453 .m = { .min = 79, .max = 126 },
454 .m1 = { .min = 12, .max = 22 },
455 .m2 = { .min = 5, .max = 9 },
456 .p = { .min = 28, .max = 112 },
457 .p1 = { .min = 2, .max = 8 },
458 .p2 = { .dot_limit = 225000,
459 .p2_slow = 14, .p2_fast = 14 },
462 static const struct intel_limit ilk_limits_dual_lvds_100m = {
463 .dot = { .min = 25000, .max = 350000 },
464 .vco = { .min = 1760000, .max = 3510000 },
465 .n = { .min = 1, .max = 3 },
466 .m = { .min = 79, .max = 126 },
467 .m1 = { .min = 12, .max = 22 },
468 .m2 = { .min = 5, .max = 9 },
469 .p = { .min = 14, .max = 42 },
470 .p1 = { .min = 2, .max = 6 },
471 .p2 = { .dot_limit = 225000,
472 .p2_slow = 7, .p2_fast = 7 },
475 static const struct intel_limit intel_limits_vlv = {
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
482 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
483 .vco = { .min = 4000000, .max = 6000000 },
484 .n = { .min = 1, .max = 7 },
485 .m1 = { .min = 2, .max = 3 },
486 .m2 = { .min = 11, .max = 156 },
487 .p1 = { .min = 2, .max = 3 },
488 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
491 static const struct intel_limit intel_limits_chv = {
493 * These are the data rate limits (measured in fast clocks)
494 * since those are the strictest limits we have. The fast
495 * clock and actual rate limits are more relaxed, so checking
496 * them would make no difference.
498 .dot = { .min = 25000 * 5, .max = 540000 * 5},
499 .vco = { .min = 4800000, .max = 6480000 },
500 .n = { .min = 1, .max = 1 },
501 .m1 = { .min = 2, .max = 2 },
502 .m2 = { .min = 24 << 22, .max = 175 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 14 },
507 static const struct intel_limit intel_limits_bxt = {
508 /* FIXME: find real dot limits */
509 .dot = { .min = 0, .max = INT_MAX },
510 .vco = { .min = 4800000, .max = 6700000 },
511 .n = { .min = 1, .max = 1 },
512 .m1 = { .min = 2, .max = 2 },
513 /* FIXME: find real m2 limits */
514 .m2 = { .min = 2 << 22, .max = 255 << 22 },
515 .p1 = { .min = 2, .max = 4 },
516 .p2 = { .p2_slow = 1, .p2_fast = 20 },
519 /* WA Display #0827: Gen9:all */
521 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
524 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
525 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
527 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
528 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
531 /* Wa_2006604312:icl,ehl */
533 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
537 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
538 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
540 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
541 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
545 needs_modeset(const struct intel_crtc_state *state)
547 return drm_atomic_crtc_needs_modeset(&state->uapi);
551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
553 return crtc_state->master_transcoder != INVALID_TRANSCODER;
557 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
559 return crtc_state->sync_mode_slaves_mask != 0;
563 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
565 return is_trans_port_sync_master(crtc_state) ||
566 is_trans_port_sync_slave(crtc_state);
570 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
571 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
572 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
573 * The helpers' return value is the rate of the clock that is fed to the
574 * display engine's pipe which can be the above fast dot clock rate or a
575 * divided-down version of it.
577 /* m1 is reserved as 0 in Pineview, n is a ring counter */
578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
580 clock->m = clock->m2 + 2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0))
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
597 clock->m = i9xx_dpll_compute_m(clock);
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
609 clock->m = clock->m1 * clock->m2;
610 clock->p = clock->p1 * clock->p2;
611 if (WARN_ON(clock->n == 0 || clock->p == 0))
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
616 return clock->dot / 5;
619 int chv_calc_dpll_params(int refclk, struct dpll *clock)
621 clock->m = clock->m1 * clock->m2;
622 clock->p = clock->p1 * clock->p2;
623 if (WARN_ON(clock->n == 0 || clock->p == 0))
625 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
627 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
629 return clock->dot / 5;
633 * Returns whether the given set of divisors are valid for a given refclk with
634 * the given connectors.
636 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
637 const struct intel_limit *limit,
638 const struct dpll *clock)
640 if (clock->n < limit->n.min || limit->n.max < clock->n)
642 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
644 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
646 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
649 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
650 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
651 if (clock->m1 <= clock->m2)
654 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
655 !IS_GEN9_LP(dev_priv)) {
656 if (clock->p < limit->p.min || limit->p.max < clock->p)
658 if (clock->m < limit->m.min || limit->m.max < clock->m)
662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
665 * connector, etc., rather than just a single range.
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
674 i9xx_select_p2_div(const struct intel_limit *limit,
675 const struct intel_crtc_state *crtc_state,
678 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
682 * For LVDS just rely on its current settings for dual-channel.
683 * We haven't figured out how to reliably set up different
684 * single/dual channel state, if we even can.
686 if (intel_is_dual_link_lvds(dev_priv))
687 return limit->p2.p2_fast;
689 return limit->p2.p2_slow;
691 if (target < limit->p2.dot_limit)
692 return limit->p2.p2_slow;
694 return limit->p2.p2_fast;
699 * Returns a set of divisors for the desired target clock with the given
700 * refclk, or FALSE. The returned values represent the clock equation:
701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
703 * Target and reference clocks are specified in kHz.
705 * If match_clock is provided, then best_clock P divider must match the P
706 * divider from @match_clock used for LVDS downclocking.
709 i9xx_find_best_dpll(const struct intel_limit *limit,
710 struct intel_crtc_state *crtc_state,
711 int target, int refclk, struct dpll *match_clock,
712 struct dpll *best_clock)
714 struct drm_device *dev = crtc_state->uapi.crtc->dev;
718 memset(best_clock, 0, sizeof(*best_clock));
720 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
724 for (clock.m2 = limit->m2.min;
725 clock.m2 <= limit->m2.max; clock.m2++) {
726 if (clock.m2 >= clock.m1)
728 for (clock.n = limit->n.min;
729 clock.n <= limit->n.max; clock.n++) {
730 for (clock.p1 = limit->p1.min;
731 clock.p1 <= limit->p1.max; clock.p1++) {
734 i9xx_calc_dpll_params(refclk, &clock);
735 if (!intel_pll_is_valid(to_i915(dev),
740 clock.p != match_clock->p)
743 this_err = abs(clock.dot - target);
744 if (this_err < err) {
753 return (err != target);
757 * Returns a set of divisors for the desired target clock with the given
758 * refclk, or FALSE. The returned values represent the clock equation:
759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
761 * Target and reference clocks are specified in kHz.
763 * If match_clock is provided, then best_clock P divider must match the P
764 * divider from @match_clock used for LVDS downclocking.
767 pnv_find_best_dpll(const struct intel_limit *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, struct dpll *match_clock,
770 struct dpll *best_clock)
772 struct drm_device *dev = crtc_state->uapi.crtc->dev;
776 memset(best_clock, 0, sizeof(*best_clock));
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
790 pnv_calc_dpll_params(refclk, &clock);
791 if (!intel_pll_is_valid(to_i915(dev),
796 clock.p != match_clock->p)
799 this_err = abs(clock.dot - target);
800 if (this_err < err) {
809 return (err != target);
813 * Returns a set of divisors for the desired target clock with the given
814 * refclk, or FALSE. The returned values represent the clock equation:
815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
817 * Target and reference clocks are specified in kHz.
819 * If match_clock is provided, then best_clock P divider must match the P
820 * divider from @match_clock used for LVDS downclocking.
823 g4x_find_best_dpll(const struct intel_limit *limit,
824 struct intel_crtc_state *crtc_state,
825 int target, int refclk, struct dpll *match_clock,
826 struct dpll *best_clock)
828 struct drm_device *dev = crtc_state->uapi.crtc->dev;
832 /* approximately equals target * 0.00585 */
833 int err_most = (target >> 8) + (target >> 9);
835 memset(best_clock, 0, sizeof(*best_clock));
837 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
839 max_n = limit->n.max;
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 /* based on hardware requirement, prefere larger m1,m2 */
843 for (clock.m1 = limit->m1.max;
844 clock.m1 >= limit->m1.min; clock.m1--) {
845 for (clock.m2 = limit->m2.max;
846 clock.m2 >= limit->m2.min; clock.m2--) {
847 for (clock.p1 = limit->p1.max;
848 clock.p1 >= limit->p1.min; clock.p1--) {
851 i9xx_calc_dpll_params(refclk, &clock);
852 if (!intel_pll_is_valid(to_i915(dev),
857 this_err = abs(clock.dot - target);
858 if (this_err < err_most) {
872 * Check if the calculated PLL configuration is more optimal compared to the
873 * best configuration and error found so far. Return the calculated error.
875 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
876 const struct dpll *calculated_clock,
877 const struct dpll *best_clock,
878 unsigned int best_error_ppm,
879 unsigned int *error_ppm)
882 * For CHV ignore the error and consider only the P value.
883 * Prefer a bigger P value based on HW requirements.
885 if (IS_CHERRYVIEW(to_i915(dev))) {
888 return calculated_clock->p > best_clock->p;
891 if (drm_WARN_ON_ONCE(dev, !target_freq))
894 *error_ppm = div_u64(1000000ULL *
895 abs(target_freq - calculated_clock->dot),
898 * Prefer a better P value over a better (smaller) error if the error
899 * is small. Ensure this preference for future configurations too by
900 * setting the error to 0.
902 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
908 return *error_ppm + 10 < best_error_ppm;
912 * Returns a set of divisors for the desired target clock with the given
913 * refclk, or FALSE. The returned values represent the clock equation:
914 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
917 vlv_find_best_dpll(const struct intel_limit *limit,
918 struct intel_crtc_state *crtc_state,
919 int target, int refclk, struct dpll *match_clock,
920 struct dpll *best_clock)
922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
923 struct drm_device *dev = crtc->base.dev;
925 unsigned int bestppm = 1000000;
926 /* min update 19.2 MHz */
927 int max_n = min(limit->n.max, refclk / 19200);
930 target *= 5; /* fast clock */
932 memset(best_clock, 0, sizeof(*best_clock));
934 /* based on hardware requirement, prefer smaller n to precision */
935 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
937 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 clock.p = clock.p1 * clock.p2;
940 /* based on hardware requirement, prefer bigger m1,m2 values */
941 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
944 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
947 vlv_calc_dpll_params(refclk, &clock);
949 if (!intel_pll_is_valid(to_i915(dev),
954 if (!vlv_PLL_is_optimal(dev, target,
972 * Returns a set of divisors for the desired target clock with the given
973 * refclk, or FALSE. The returned values represent the clock equation:
974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
977 chv_find_best_dpll(const struct intel_limit *limit,
978 struct intel_crtc_state *crtc_state,
979 int target, int refclk, struct dpll *match_clock,
980 struct dpll *best_clock)
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
983 struct drm_device *dev = crtc->base.dev;
984 unsigned int best_error_ppm;
989 memset(best_clock, 0, sizeof(*best_clock));
990 best_error_ppm = 1000000;
993 * Based on hardware doc, the n always set to 1, and m1 always
994 * set to 2. If requires to support 200Mhz refclk, we need to
995 * revisit this because n may not 1 anymore.
997 clock.n = 1, clock.m1 = 2;
998 target *= 5; /* fast clock */
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001 for (clock.p2 = limit->p2.p2_fast;
1002 clock.p2 >= limit->p2.p2_slow;
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004 unsigned int error_ppm;
1006 clock.p = clock.p1 * clock.p2;
1008 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1011 if (m2 > INT_MAX/clock.m1)
1016 chv_calc_dpll_params(refclk, &clock);
1018 if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1021 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022 best_error_ppm, &error_ppm))
1025 *best_clock = clock;
1026 best_error_ppm = error_ppm;
1034 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035 struct dpll *best_clock)
1037 int refclk = 100000;
1038 const struct intel_limit *limit = &intel_limits_bxt;
1040 return chv_find_best_dpll(limit, crtc_state,
1041 crtc_state->port_clock, refclk,
1045 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1048 i915_reg_t reg = PIPEDSL(pipe);
1052 if (IS_GEN(dev_priv, 2))
1053 line_mask = DSL_LINEMASK_GEN2;
1055 line_mask = DSL_LINEMASK_GEN3;
1057 line1 = intel_de_read(dev_priv, reg) & line_mask;
1059 line2 = intel_de_read(dev_priv, reg) & line_mask;
1061 return line1 != line2;
1064 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1066 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1067 enum pipe pipe = crtc->pipe;
1069 /* Wait for the display line to settle/start moving */
1070 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1071 drm_err(&dev_priv->drm,
1072 "pipe %c scanline %s wait timed out\n",
1073 pipe_name(pipe), onoff(state));
1076 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1078 wait_for_pipe_scanline_moving(crtc, false);
1081 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1083 wait_for_pipe_scanline_moving(crtc, true);
1087 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1089 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1090 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1092 if (INTEL_GEN(dev_priv) >= 4) {
1093 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094 i915_reg_t reg = PIPECONF(cpu_transcoder);
1096 /* Wait for the Pipe State to go off */
1097 if (intel_de_wait_for_clear(dev_priv, reg,
1098 I965_PIPECONF_ACTIVE, 100))
1099 drm_WARN(&dev_priv->drm, 1,
1100 "pipe_off wait timed out\n");
1102 intel_wait_for_pipe_scanline_stopped(crtc);
1106 /* Only for pre-ILK configs */
1107 void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1113 val = intel_de_read(dev_priv, DPLL(pipe));
1114 cur_state = !!(val & DPLL_VCO_ENABLE);
1115 I915_STATE_WARN(cur_state != state,
1116 "PLL state assertion failure (expected %s, current %s)\n",
1117 onoff(state), onoff(cur_state));
1120 /* XXX: the dsi pll is shared between MIPI DSI ports */
1121 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1126 vlv_cck_get(dev_priv);
1127 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1128 vlv_cck_put(dev_priv);
1130 cur_state = val & DSI_PLL_VCO_EN;
1131 I915_STATE_WARN(cur_state != state,
1132 "DSI PLL state assertion failure (expected %s, current %s)\n",
1133 onoff(state), onoff(cur_state));
1136 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1137 enum pipe pipe, bool state)
1141 if (HAS_DDI(dev_priv)) {
1143 * DDI does not have a specific FDI_TX register.
1145 * FDI is never fed from EDP transcoder
1146 * so pipe->transcoder cast is fine here.
1148 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149 u32 val = intel_de_read(dev_priv,
1150 TRANS_DDI_FUNC_CTL(cpu_transcoder));
1151 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1153 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1154 cur_state = !!(val & FDI_TX_ENABLE);
1156 I915_STATE_WARN(cur_state != state,
1157 "FDI TX state assertion failure (expected %s, current %s)\n",
1158 onoff(state), onoff(cur_state));
1160 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1161 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1163 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1169 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1170 cur_state = !!(val & FDI_RX_ENABLE);
1171 I915_STATE_WARN(cur_state != state,
1172 "FDI RX state assertion failure (expected %s, current %s)\n",
1173 onoff(state), onoff(cur_state));
1175 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1176 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1178 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1183 /* ILK FDI PLL is always enabled */
1184 if (IS_GEN(dev_priv, 5))
1187 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188 if (HAS_DDI(dev_priv))
1191 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1192 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1195 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1201 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1202 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1205 onoff(state), onoff(cur_state));
1208 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1212 enum pipe panel_pipe = INVALID_PIPE;
1215 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1218 if (HAS_PCH_SPLIT(dev_priv)) {
1221 pp_reg = PP_CONTROL(0);
1222 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1225 case PANEL_PORT_SELECT_LVDS:
1226 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1228 case PANEL_PORT_SELECT_DPA:
1229 intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1231 case PANEL_PORT_SELECT_DPC:
1232 intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1234 case PANEL_PORT_SELECT_DPD:
1235 intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1238 MISSING_CASE(port_sel);
1241 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1242 /* presumably write lock depends on pipe, not port select */
1243 pp_reg = PP_CONTROL(pipe);
1248 pp_reg = PP_CONTROL(0);
1249 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1251 drm_WARN_ON(&dev_priv->drm,
1252 port_sel != PANEL_PORT_SELECT_LVDS);
1253 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1256 val = intel_de_read(dev_priv, pp_reg);
1257 if (!(val & PANEL_POWER_ON) ||
1258 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1261 I915_STATE_WARN(panel_pipe == pipe && locked,
1262 "panel assertion failure, pipe %c regs locked\n",
1266 void assert_pipe(struct drm_i915_private *dev_priv,
1267 enum transcoder cpu_transcoder, bool state)
1270 enum intel_display_power_domain power_domain;
1271 intel_wakeref_t wakeref;
1273 /* we keep both pipes enabled on 830 */
1274 if (IS_I830(dev_priv))
1277 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1278 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1281 cur_state = !!(val & PIPECONF_ENABLE);
1283 intel_display_power_put(dev_priv, power_domain, wakeref);
1288 I915_STATE_WARN(cur_state != state,
1289 "transcoder %s assertion failure (expected %s, current %s)\n",
1290 transcoder_name(cpu_transcoder),
1291 onoff(state), onoff(cur_state));
1294 static void assert_plane(struct intel_plane *plane, bool state)
1299 cur_state = plane->get_hw_state(plane, &pipe);
1301 I915_STATE_WARN(cur_state != state,
1302 "%s assertion failure (expected %s, current %s)\n",
1303 plane->base.name, onoff(state), onoff(cur_state));
1306 #define assert_plane_enabled(p) assert_plane(p, true)
1307 #define assert_plane_disabled(p) assert_plane(p, false)
1309 static void assert_planes_disabled(struct intel_crtc *crtc)
1311 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1312 struct intel_plane *plane;
1314 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1315 assert_plane_disabled(plane);
1318 static void assert_vblank_disabled(struct drm_crtc *crtc)
1320 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1321 drm_crtc_vblank_put(crtc);
1324 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1330 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1331 enabled = !!(val & TRANS_ENABLE);
1332 I915_STATE_WARN(enabled,
1333 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1337 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, enum port port,
1341 enum pipe port_pipe;
1344 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1346 I915_STATE_WARN(state && port_pipe == pipe,
1347 "PCH DP %c enabled on transcoder %c, should be disabled\n",
1348 port_name(port), pipe_name(pipe));
1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1351 "IBX PCH DP %c still using transcoder B\n",
1355 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe, enum port port,
1357 i915_reg_t hdmi_reg)
1359 enum pipe port_pipe;
1362 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1364 I915_STATE_WARN(state && port_pipe == pipe,
1365 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1366 port_name(port), pipe_name(pipe));
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1369 "IBX PCH HDMI %c still using transcoder B\n",
1373 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1376 enum pipe port_pipe;
1378 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1379 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1380 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1382 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1384 "PCH VGA enabled on transcoder %c, should be disabled\n",
1387 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1389 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1392 /* PCH SDVOB multiplex with HDMIB */
1393 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1394 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1395 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1398 static void _vlv_enable_pll(struct intel_crtc *crtc,
1399 const struct intel_crtc_state *pipe_config)
1401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1402 enum pipe pipe = crtc->pipe;
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1405 intel_de_posting_read(dev_priv, DPLL(pipe));
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1412 static void vlv_enable_pll(struct intel_crtc *crtc,
1413 const struct intel_crtc_state *pipe_config)
1415 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1416 enum pipe pipe = crtc->pipe;
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1420 /* PLL is protected by panel, make sure we can write it */
1421 assert_panel_unlocked(dev_priv, pipe);
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1424 _vlv_enable_pll(crtc, pipe_config);
1426 intel_de_write(dev_priv, DPLL_MD(pipe),
1427 pipe_config->dpll_hw_state.dpll_md);
1428 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1432 static void _chv_enable_pll(struct intel_crtc *crtc,
1433 const struct intel_crtc_state *pipe_config)
1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1436 enum pipe pipe = crtc->pipe;
1437 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1440 vlv_dpio_get(dev_priv);
1442 /* Enable back the 10bit clock to display controller */
1443 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1444 tmp |= DPIO_DCLKP_EN;
1445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1447 vlv_dpio_put(dev_priv);
1450 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1457 /* Check PLL is locked */
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1459 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1462 static void chv_enable_pll(struct intel_crtc *crtc,
1463 const struct intel_crtc_state *pipe_config)
1465 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1466 enum pipe pipe = crtc->pipe;
1468 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1470 /* PLL is protected by panel, make sure we can write it */
1471 assert_panel_unlocked(dev_priv, pipe);
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1474 _chv_enable_pll(crtc, pipe_config);
1476 if (pipe != PIPE_A) {
1478 * WaPixelRepeatModeFixForC0:chv
1480 * DPLLCMD is AWOL. Use chicken bits to propagate
1481 * the value from DPLLBMD to either pipe B or C.
1483 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1485 pipe_config->dpll_hw_state.dpll_md);
1486 intel_de_write(dev_priv, CBR4_VLV, 0);
1487 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1490 * DPLLB VGA mode also seems to cause problems.
1491 * We should always have it disabled.
1493 drm_WARN_ON(&dev_priv->drm,
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1495 DPLL_VGA_MODE_DIS) == 0);
1497 intel_de_write(dev_priv, DPLL_MD(pipe),
1498 pipe_config->dpll_hw_state.dpll_md);
1499 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1503 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1505 if (IS_I830(dev_priv))
1508 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1511 static void i9xx_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *crtc_state)
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 i915_reg_t reg = DPLL(crtc->pipe);
1516 u32 dpll = crtc_state->dpll_hw_state.dpll;
1519 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1521 /* PLL is protected by panel, make sure we can write it */
1522 if (i9xx_has_pps(dev_priv))
1523 assert_panel_unlocked(dev_priv, crtc->pipe);
1526 * Apparently we need to have VGA mode enabled prior to changing
1527 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528 * dividers, even though the register value does change.
1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1531 intel_de_write(dev_priv, reg, dpll);
1533 /* Wait for the clocks to stabilize. */
1534 intel_de_posting_read(dev_priv, reg);
1537 if (INTEL_GEN(dev_priv) >= 4) {
1538 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1539 crtc_state->dpll_hw_state.dpll_md);
1541 /* The pixel multiplier can only be updated once the
1542 * DPLL is enabled and the clocks are stable.
1544 * So write it again.
1546 intel_de_write(dev_priv, reg, dpll);
1549 /* We do this three times for luck */
1550 for (i = 0; i < 3; i++) {
1551 intel_de_write(dev_priv, reg, dpll);
1552 intel_de_posting_read(dev_priv, reg);
1553 udelay(150); /* wait for warmup */
1557 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1563 /* Don't disable pipe or pipe PLLs if needed */
1564 if (IS_I830(dev_priv))
1567 /* Make sure the pipe isn't still relying on us */
1568 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1571 intel_de_posting_read(dev_priv, DPLL(pipe));
1574 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1578 /* Make sure the pipe isn't still relying on us */
1579 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1581 val = DPLL_INTEGRATED_REF_CLK_VLV |
1582 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1584 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1586 intel_de_write(dev_priv, DPLL(pipe), val);
1587 intel_de_posting_read(dev_priv, DPLL(pipe));
1590 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1592 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1595 /* Make sure the pipe isn't still relying on us */
1596 assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1598 val = DPLL_SSC_REF_CLK_CHV |
1599 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1601 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1603 intel_de_write(dev_priv, DPLL(pipe), val);
1604 intel_de_posting_read(dev_priv, DPLL(pipe));
1606 vlv_dpio_get(dev_priv);
1608 /* Disable 10bit clock to display controller */
1609 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 val &= ~DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1613 vlv_dpio_put(dev_priv);
1616 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1617 struct intel_digital_port *dig_port,
1618 unsigned int expected_mask)
1621 i915_reg_t dpll_reg;
1623 switch (dig_port->base.port) {
1625 port_mask = DPLL_PORTB_READY_MASK;
1629 port_mask = DPLL_PORTC_READY_MASK;
1631 expected_mask <<= 4;
1634 port_mask = DPLL_PORTD_READY_MASK;
1635 dpll_reg = DPIO_PHY_STATUS;
1641 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642 port_mask, expected_mask, 1000))
1643 drm_WARN(&dev_priv->drm, 1,
1644 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1645 dig_port->base.base.base.id, dig_port->base.base.name,
1646 intel_de_read(dev_priv, dpll_reg) & port_mask,
1650 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1653 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1654 enum pipe pipe = crtc->pipe;
1656 u32 val, pipeconf_val;
1658 /* Make sure PCH DPLL is enabled */
1659 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1665 if (HAS_PCH_CPT(dev_priv)) {
1666 reg = TRANS_CHICKEN2(pipe);
1667 val = intel_de_read(dev_priv, reg);
1669 * Workaround: Set the timing override bit
1670 * before enabling the pch transcoder.
1672 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1673 /* Configure frame start delay to match the CPU */
1674 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1675 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1676 intel_de_write(dev_priv, reg, val);
1679 reg = PCH_TRANSCONF(pipe);
1680 val = intel_de_read(dev_priv, reg);
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1683 if (HAS_PCH_IBX(dev_priv)) {
1684 /* Configure frame start delay to match the CPU */
1685 val &= ~TRANS_FRAME_START_DELAY_MASK;
1686 val |= TRANS_FRAME_START_DELAY(0);
1689 * Make the BPC in transcoder be consistent with
1690 * that in pipeconf reg. For HDMI we must use 8bpc
1691 * here for both 8bpc and 12bpc.
1693 val &= ~PIPECONF_BPC_MASK;
1694 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695 val |= PIPECONF_8BPC;
1697 val |= pipeconf_val & PIPECONF_BPC_MASK;
1700 val &= ~TRANS_INTERLACE_MASK;
1701 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1702 if (HAS_PCH_IBX(dev_priv) &&
1703 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704 val |= TRANS_LEGACY_INTERLACED_ILK;
1706 val |= TRANS_INTERLACED;
1708 val |= TRANS_PROGRESSIVE;
1711 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1712 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1713 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1717 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1718 enum transcoder cpu_transcoder)
1720 u32 val, pipeconf_val;
1722 /* FDI must be feeding us bits for PCH ports */
1723 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1724 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1726 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1727 /* Workaround: set timing override bit. */
1728 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 /* Configure frame start delay to match the CPU */
1730 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1731 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1732 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1737 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1738 PIPECONF_INTERLACED_ILK)
1739 val |= TRANS_INTERLACED;
1741 val |= TRANS_PROGRESSIVE;
1743 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1744 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1745 TRANS_STATE_ENABLE, 100))
1746 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1749 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1762 reg = PCH_TRANSCONF(pipe);
1763 val = intel_de_read(dev_priv, reg);
1764 val &= ~TRANS_ENABLE;
1765 intel_de_write(dev_priv, reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1768 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1771 if (HAS_PCH_CPT(dev_priv)) {
1772 /* Workaround: Clear the timing override chicken bit again. */
1773 reg = TRANS_CHICKEN2(pipe);
1774 val = intel_de_read(dev_priv, reg);
1775 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1776 intel_de_write(dev_priv, reg, val);
1780 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1784 val = intel_de_read(dev_priv, LPT_TRANSCONF);
1785 val &= ~TRANS_ENABLE;
1786 intel_de_write(dev_priv, LPT_TRANSCONF, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1789 TRANS_STATE_ENABLE, 50))
1790 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1792 /* Workaround: clear timing override bit. */
1793 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1794 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1795 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1798 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1802 if (HAS_PCH_LPT(dev_priv))
1808 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1810 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1812 u32 mode_flags = crtc->mode_flags;
1815 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt
1816 * have updated at the beginning of TE, if we want to use
1817 * the hw counter, then we would find it updated in only
1818 * the next TE, hence switching to sw counter.
1820 if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1))
1824 * On i965gm the hardware frame counter reads
1825 * zero when the TV encoder is enabled :(
1827 if (IS_I965GM(dev_priv) &&
1828 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1831 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1832 return 0xffffffff; /* full 32 bit counter */
1833 else if (INTEL_GEN(dev_priv) >= 3)
1834 return 0xffffff; /* only 24 bits of frame count */
1836 return 0; /* Gen2 doesn't have a hardware frame counter */
1839 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1841 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1843 assert_vblank_disabled(&crtc->base);
1844 drm_crtc_set_max_vblank_count(&crtc->base,
1845 intel_crtc_max_vblank_count(crtc_state));
1846 drm_crtc_vblank_on(&crtc->base);
1849 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1851 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1853 drm_crtc_vblank_off(&crtc->base);
1854 assert_vblank_disabled(&crtc->base);
1857 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1859 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1860 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1861 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1862 enum pipe pipe = crtc->pipe;
1866 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1868 assert_planes_disabled(crtc);
1871 * A pipe without a PLL won't actually be able to drive bits from
1872 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1875 if (HAS_GMCH(dev_priv)) {
1876 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1877 assert_dsi_pll_enabled(dev_priv);
1879 assert_pll_enabled(dev_priv, pipe);
1881 if (new_crtc_state->has_pch_encoder) {
1882 /* if driving the PCH, we need FDI enabled */
1883 assert_fdi_rx_pll_enabled(dev_priv,
1884 intel_crtc_pch_transcoder(crtc));
1885 assert_fdi_tx_pll_enabled(dev_priv,
1886 (enum pipe) cpu_transcoder);
1888 /* FIXME: assert CPU port conditions for SNB+ */
1891 trace_intel_pipe_enable(crtc);
1893 reg = PIPECONF(cpu_transcoder);
1894 val = intel_de_read(dev_priv, reg);
1895 if (val & PIPECONF_ENABLE) {
1896 /* we keep both pipes enabled on 830 */
1897 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1901 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1902 intel_de_posting_read(dev_priv, reg);
1905 * Until the pipe starts PIPEDSL reads will return a stale value,
1906 * which causes an apparent vblank timestamp jump when PIPEDSL
1907 * resets to its proper value. That also messes up the frame count
1908 * when it's derived from the timestamps. So let's wait for the
1909 * pipe to start properly before we call drm_crtc_vblank_on()
1911 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1912 intel_wait_for_pipe_scanline_moving(crtc);
1915 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1917 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1918 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1919 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1920 enum pipe pipe = crtc->pipe;
1924 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1927 * Make sure planes won't keep trying to pump pixels to us,
1928 * or we might hang the display.
1930 assert_planes_disabled(crtc);
1932 trace_intel_pipe_disable(crtc);
1934 reg = PIPECONF(cpu_transcoder);
1935 val = intel_de_read(dev_priv, reg);
1936 if ((val & PIPECONF_ENABLE) == 0)
1940 * Double wide has implications for planes
1941 * so best keep it disabled when not needed.
1943 if (old_crtc_state->double_wide)
1944 val &= ~PIPECONF_DOUBLE_WIDE;
1946 /* Don't disable pipe or pipe PLLs if needed */
1947 if (!IS_I830(dev_priv))
1948 val &= ~PIPECONF_ENABLE;
1950 intel_de_write(dev_priv, reg, val);
1951 if ((val & PIPECONF_ENABLE) == 0)
1952 intel_wait_for_pipe_off(old_crtc_state);
1955 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1957 return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1960 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1962 if (!is_ccs_modifier(fb->modifier))
1965 return plane >= fb->format->num_planes / 2;
1968 static bool is_gen12_ccs_modifier(u64 modifier)
1970 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1971 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1975 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1977 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1980 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1982 if (is_ccs_modifier(fb->modifier))
1983 return is_ccs_plane(fb, plane);
1988 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1990 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1991 (main_plane && main_plane >= fb->format->num_planes / 2));
1993 return fb->format->num_planes / 2 + main_plane;
1996 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1998 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
1999 ccs_plane < fb->format->num_planes / 2);
2001 return ccs_plane - fb->format->num_planes / 2;
2004 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
2006 struct drm_i915_private *i915 = to_i915(fb->dev);
2008 if (is_ccs_modifier(fb->modifier))
2009 return main_to_ccs_plane(fb, main_plane);
2010 else if (INTEL_GEN(i915) < 11 &&
2011 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
2018 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2021 return info->is_yuv &&
2022 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2025 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2028 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2033 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2035 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2036 unsigned int cpp = fb->format->cpp[color_plane];
2038 switch (fb->modifier) {
2039 case DRM_FORMAT_MOD_LINEAR:
2040 return intel_tile_size(dev_priv);
2041 case I915_FORMAT_MOD_X_TILED:
2042 if (IS_GEN(dev_priv, 2))
2046 case I915_FORMAT_MOD_Y_TILED_CCS:
2047 if (is_ccs_plane(fb, color_plane))
2050 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2051 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2052 if (is_ccs_plane(fb, color_plane))
2055 case I915_FORMAT_MOD_Y_TILED:
2056 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2060 case I915_FORMAT_MOD_Yf_TILED_CCS:
2061 if (is_ccs_plane(fb, color_plane))
2064 case I915_FORMAT_MOD_Yf_TILED:
2080 MISSING_CASE(fb->modifier);
2086 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2088 if (is_gen12_ccs_plane(fb, color_plane))
2091 return intel_tile_size(to_i915(fb->dev)) /
2092 intel_tile_width_bytes(fb, color_plane);
2095 /* Return the tile dimensions in pixel units */
2096 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2097 unsigned int *tile_width,
2098 unsigned int *tile_height)
2100 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2101 unsigned int cpp = fb->format->cpp[color_plane];
2103 *tile_width = tile_width_bytes / cpp;
2104 *tile_height = intel_tile_height(fb, color_plane);
2107 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2110 unsigned int tile_width, tile_height;
2112 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2114 return fb->pitches[color_plane] * tile_height;
2118 intel_fb_align_height(const struct drm_framebuffer *fb,
2119 int color_plane, unsigned int height)
2121 unsigned int tile_height = intel_tile_height(fb, color_plane);
2123 return ALIGN(height, tile_height);
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2128 unsigned int size = 0;
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2137 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2139 unsigned int size = 0;
2142 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2143 size += rem_info->plane[i].width * rem_info->plane[i].height;
2149 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2150 const struct drm_framebuffer *fb,
2151 unsigned int rotation)
2153 view->type = I915_GGTT_VIEW_NORMAL;
2154 if (drm_rotation_90_or_270(rotation)) {
2155 view->type = I915_GGTT_VIEW_ROTATED;
2156 view->rotated = to_intel_framebuffer(fb)->rot_info;
2160 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2162 if (IS_I830(dev_priv))
2164 else if (IS_I85X(dev_priv))
2166 else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2172 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2174 if (INTEL_GEN(dev_priv) >= 9)
2176 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2177 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2179 else if (INTEL_GEN(dev_priv) >= 4)
2185 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2188 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2190 /* AUX_DIST needs only 4K alignment */
2191 if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2192 is_ccs_plane(fb, color_plane))
2195 switch (fb->modifier) {
2196 case DRM_FORMAT_MOD_LINEAR:
2197 return intel_linear_alignment(dev_priv);
2198 case I915_FORMAT_MOD_X_TILED:
2199 if (INTEL_GEN(dev_priv) >= 9)
2202 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2203 if (is_semiplanar_uv_plane(fb, color_plane))
2204 return intel_tile_row_size(fb, color_plane);
2206 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2208 case I915_FORMAT_MOD_Y_TILED_CCS:
2209 case I915_FORMAT_MOD_Yf_TILED_CCS:
2210 case I915_FORMAT_MOD_Y_TILED:
2211 if (INTEL_GEN(dev_priv) >= 12 &&
2212 is_semiplanar_uv_plane(fb, color_plane))
2213 return intel_tile_row_size(fb, color_plane);
2215 case I915_FORMAT_MOD_Yf_TILED:
2216 return 1 * 1024 * 1024;
2218 MISSING_CASE(fb->modifier);
2223 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2225 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2226 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2228 return INTEL_GEN(dev_priv) < 4 ||
2230 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2234 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2235 const struct i915_ggtt_view *view,
2237 unsigned long *out_flags)
2239 struct drm_device *dev = fb->dev;
2240 struct drm_i915_private *dev_priv = to_i915(dev);
2241 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2242 intel_wakeref_t wakeref;
2243 struct i915_vma *vma;
2244 unsigned int pinctl;
2247 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2248 return ERR_PTR(-EINVAL);
2250 alignment = intel_surf_alignment(fb, 0);
2251 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2252 return ERR_PTR(-EINVAL);
2254 /* Note that the w/a also requires 64 PTE of padding following the
2255 * bo. We currently fill all unused PTE with the shadow page and so
2256 * we should always have valid PTE following the scanout preventing
2259 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2260 alignment = 256 * 1024;
2263 * Global gtt pte registers are special registers which actually forward
2264 * writes to a chunk of system memory. Which means that there is no risk
2265 * that the register values disappear as soon as we call
2266 * intel_runtime_pm_put(), so it is correct to wrap only the
2267 * pin/unpin/fence and not more.
2269 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2271 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2274 * Valleyview is definitely limited to scanning out the first
2275 * 512MiB. Lets presume this behaviour was inherited from the
2276 * g4x display engine and that all earlier gen are similarly
2277 * limited. Testing suggests that it is a little more
2278 * complicated than this. For example, Cherryview appears quite
2279 * happy to scanout from anywhere within its global aperture.
2282 if (HAS_GMCH(dev_priv))
2283 pinctl |= PIN_MAPPABLE;
2285 vma = i915_gem_object_pin_to_display_plane(obj,
2286 alignment, view, pinctl);
2290 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2294 * Install a fence for tiled scan-out. Pre-i965 always needs a
2295 * fence, whereas 965+ only requires a fence if using
2296 * framebuffer compression. For simplicity, we always, when
2297 * possible, install a fence as the cost is not that onerous.
2299 * If we fail to fence the tiled scanout, then either the
2300 * modeset will reject the change (which is highly unlikely as
2301 * the affected systems, all but one, do not have unmappable
2302 * space) or we will not be able to enable full powersaving
2303 * techniques (also likely not to apply due to various limits
2304 * FBC and the like impose on the size of the buffer, which
2305 * presumably we violated anyway with this unmappable buffer).
2306 * Anyway, it is presumably better to stumble onwards with
2307 * something and try to run the system in a "less than optimal"
2308 * mode that matches the user configuration.
2310 ret = i915_vma_pin_fence(vma);
2311 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2312 i915_gem_object_unpin_from_display_plane(vma);
2317 if (ret == 0 && vma->fence)
2318 *out_flags |= PLANE_HAS_FENCE;
2323 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2324 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2328 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2330 i915_gem_object_lock(vma->obj, NULL);
2331 if (flags & PLANE_HAS_FENCE)
2332 i915_vma_unpin_fence(vma);
2333 i915_gem_object_unpin_from_display_plane(vma);
2334 i915_gem_object_unlock(vma->obj);
2339 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2340 unsigned int rotation)
2342 if (drm_rotation_90_or_270(rotation))
2343 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2345 return fb->pitches[color_plane];
2349 * Convert the x/y offsets into a linear offset.
2350 * Only valid with 0/180 degree rotation, which is fine since linear
2351 * offset is only used with linear buffers on pre-hsw and tiled buffers
2352 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2354 u32 intel_fb_xy_to_linear(int x, int y,
2355 const struct intel_plane_state *state,
2358 const struct drm_framebuffer *fb = state->hw.fb;
2359 unsigned int cpp = fb->format->cpp[color_plane];
2360 unsigned int pitch = state->color_plane[color_plane].stride;
2362 return y * pitch + x * cpp;
2366 * Add the x/y offsets derived from fb->offsets[] to the user
2367 * specified plane src x/y offsets. The resulting x/y offsets
2368 * specify the start of scanout from the beginning of the gtt mapping.
2370 void intel_add_fb_offsets(int *x, int *y,
2371 const struct intel_plane_state *state,
2375 *x += state->color_plane[color_plane].x;
2376 *y += state->color_plane[color_plane].y;
2379 static u32 intel_adjust_tile_offset(int *x, int *y,
2380 unsigned int tile_width,
2381 unsigned int tile_height,
2382 unsigned int tile_size,
2383 unsigned int pitch_tiles,
2387 unsigned int pitch_pixels = pitch_tiles * tile_width;
2390 WARN_ON(old_offset & (tile_size - 1));
2391 WARN_ON(new_offset & (tile_size - 1));
2392 WARN_ON(new_offset > old_offset);
2394 tiles = (old_offset - new_offset) / tile_size;
2396 *y += tiles / pitch_tiles * tile_height;
2397 *x += tiles % pitch_tiles * tile_width;
2399 /* minimize x in case it got needlessly big */
2400 *y += *x / pitch_pixels * tile_height;
2406 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2408 return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2409 is_gen12_ccs_plane(fb, color_plane);
2412 static u32 intel_adjust_aligned_offset(int *x, int *y,
2413 const struct drm_framebuffer *fb,
2415 unsigned int rotation,
2417 u32 old_offset, u32 new_offset)
2419 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2420 unsigned int cpp = fb->format->cpp[color_plane];
2422 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2424 if (!is_surface_linear(fb, color_plane)) {
2425 unsigned int tile_size, tile_width, tile_height;
2426 unsigned int pitch_tiles;
2428 tile_size = intel_tile_size(dev_priv);
2429 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2431 if (drm_rotation_90_or_270(rotation)) {
2432 pitch_tiles = pitch / tile_height;
2433 swap(tile_width, tile_height);
2435 pitch_tiles = pitch / (tile_width * cpp);
2438 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2439 tile_size, pitch_tiles,
2440 old_offset, new_offset);
2442 old_offset += *y * pitch + *x * cpp;
2444 *y = (old_offset - new_offset) / pitch;
2445 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2452 * Adjust the tile offset by moving the difference into
2455 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2456 const struct intel_plane_state *state,
2458 u32 old_offset, u32 new_offset)
2460 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2462 state->color_plane[color_plane].stride,
2463 old_offset, new_offset);
2467 * Computes the aligned offset to the base tile and adjusts
2468 * x, y. bytes per pixel is assumed to be a power-of-two.
2470 * In the 90/270 rotated case, x and y are assumed
2471 * to be already rotated to match the rotated GTT view, and
2472 * pitch is the tile_height aligned framebuffer height.
2474 * This function is used when computing the derived information
2475 * under intel_framebuffer, so using any of that information
2476 * here is not allowed. Anything under drm_framebuffer can be
2477 * used. This is why the user has to pass in the pitch since it
2478 * is specified in the rotated orientation.
2480 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2482 const struct drm_framebuffer *fb,
2485 unsigned int rotation,
2488 unsigned int cpp = fb->format->cpp[color_plane];
2489 u32 offset, offset_aligned;
2491 if (!is_surface_linear(fb, color_plane)) {
2492 unsigned int tile_size, tile_width, tile_height;
2493 unsigned int tile_rows, tiles, pitch_tiles;
2495 tile_size = intel_tile_size(dev_priv);
2496 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2498 if (drm_rotation_90_or_270(rotation)) {
2499 pitch_tiles = pitch / tile_height;
2500 swap(tile_width, tile_height);
2502 pitch_tiles = pitch / (tile_width * cpp);
2505 tile_rows = *y / tile_height;
2508 tiles = *x / tile_width;
2511 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2513 offset_aligned = offset;
2515 offset_aligned = rounddown(offset_aligned, alignment);
2517 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2518 tile_size, pitch_tiles,
2519 offset, offset_aligned);
2521 offset = *y * pitch + *x * cpp;
2522 offset_aligned = offset;
2524 offset_aligned = rounddown(offset_aligned, alignment);
2525 *y = (offset % alignment) / pitch;
2526 *x = ((offset % alignment) - *y * pitch) / cpp;
2532 return offset_aligned;
2535 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2536 const struct intel_plane_state *state,
2539 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2540 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2541 const struct drm_framebuffer *fb = state->hw.fb;
2542 unsigned int rotation = state->hw.rotation;
2543 int pitch = state->color_plane[color_plane].stride;
2546 if (intel_plane->id == PLANE_CURSOR)
2547 alignment = intel_cursor_alignment(dev_priv);
2549 alignment = intel_surf_alignment(fb, color_plane);
2551 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2552 pitch, rotation, alignment);
2555 /* Convert the fb->offset[] into x/y offsets */
2556 static int intel_fb_offset_to_xy(int *x, int *y,
2557 const struct drm_framebuffer *fb,
2560 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2561 unsigned int height;
2564 if (INTEL_GEN(dev_priv) >= 12 &&
2565 is_semiplanar_uv_plane(fb, color_plane))
2566 alignment = intel_tile_row_size(fb, color_plane);
2567 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2568 alignment = intel_tile_size(dev_priv);
2572 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2573 drm_dbg_kms(&dev_priv->drm,
2574 "Misaligned offset 0x%08x for color plane %d\n",
2575 fb->offsets[color_plane], color_plane);
2579 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2580 height = ALIGN(height, intel_tile_height(fb, color_plane));
2582 /* Catch potential overflows early */
2583 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2584 fb->offsets[color_plane])) {
2585 drm_dbg_kms(&dev_priv->drm,
2586 "Bad offset 0x%08x or pitch %d for color plane %d\n",
2587 fb->offsets[color_plane], fb->pitches[color_plane],
2595 intel_adjust_aligned_offset(x, y,
2596 fb, color_plane, DRM_MODE_ROTATE_0,
2597 fb->pitches[color_plane],
2598 fb->offsets[color_plane], 0);
2603 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2605 switch (fb_modifier) {
2606 case I915_FORMAT_MOD_X_TILED:
2607 return I915_TILING_X;
2608 case I915_FORMAT_MOD_Y_TILED:
2609 case I915_FORMAT_MOD_Y_TILED_CCS:
2610 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2611 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2612 return I915_TILING_Y;
2614 return I915_TILING_NONE;
2619 * From the Sky Lake PRM:
2620 * "The Color Control Surface (CCS) contains the compression status of
2621 * the cache-line pairs. The compression state of the cache-line pair
2622 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2623 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2624 * cache-line-pairs. CCS is always Y tiled."
2626 * Since cache line pairs refers to horizontally adjacent cache lines,
2627 * each cache line in the CCS corresponds to an area of 32x16 cache
2628 * lines on the main surface. Since each pixel is 4 bytes, this gives
2629 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2632 static const struct drm_format_info skl_ccs_formats[] = {
2633 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2634 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2635 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2636 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2637 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2638 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2639 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2640 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2644 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2645 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2646 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2647 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2650 static const struct drm_format_info gen12_ccs_formats[] = {
2651 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2652 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653 .hsub = 1, .vsub = 1, },
2654 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2655 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656 .hsub = 1, .vsub = 1, },
2657 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2658 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2659 .hsub = 1, .vsub = 1, .has_alpha = true },
2660 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2661 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2662 .hsub = 1, .vsub = 1, .has_alpha = true },
2663 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2664 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2665 .hsub = 2, .vsub = 1, .is_yuv = true },
2666 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2667 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2668 .hsub = 2, .vsub = 1, .is_yuv = true },
2669 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2670 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2671 .hsub = 2, .vsub = 1, .is_yuv = true },
2672 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2673 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2674 .hsub = 2, .vsub = 1, .is_yuv = true },
2675 { .format = DRM_FORMAT_NV12, .num_planes = 4,
2676 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2677 .hsub = 2, .vsub = 2, .is_yuv = true },
2678 { .format = DRM_FORMAT_P010, .num_planes = 4,
2679 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2680 .hsub = 2, .vsub = 2, .is_yuv = true },
2681 { .format = DRM_FORMAT_P012, .num_planes = 4,
2682 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2683 .hsub = 2, .vsub = 2, .is_yuv = true },
2684 { .format = DRM_FORMAT_P016, .num_planes = 4,
2685 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2686 .hsub = 2, .vsub = 2, .is_yuv = true },
2689 static const struct drm_format_info *
2690 lookup_format_info(const struct drm_format_info formats[],
2691 int num_formats, u32 format)
2695 for (i = 0; i < num_formats; i++) {
2696 if (formats[i].format == format)
2703 static const struct drm_format_info *
2704 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2706 switch (cmd->modifier[0]) {
2707 case I915_FORMAT_MOD_Y_TILED_CCS:
2708 case I915_FORMAT_MOD_Yf_TILED_CCS:
2709 return lookup_format_info(skl_ccs_formats,
2710 ARRAY_SIZE(skl_ccs_formats),
2712 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2713 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2714 return lookup_format_info(gen12_ccs_formats,
2715 ARRAY_SIZE(gen12_ccs_formats),
2722 bool is_ccs_modifier(u64 modifier)
2724 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2725 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2726 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2727 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2730 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2732 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2736 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2737 u32 pixel_format, u64 modifier)
2739 struct intel_crtc *crtc;
2740 struct intel_plane *plane;
2743 * We assume the primary plane for pipe A has
2744 * the highest stride limits of them all,
2745 * if in case pipe A is disabled, use the first pipe from pipe_mask.
2747 crtc = intel_get_first_crtc(dev_priv);
2751 plane = to_intel_plane(crtc->base.primary);
2753 return plane->max_stride(plane, pixel_format, modifier,
2758 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2759 u32 pixel_format, u64 modifier)
2762 * Arbitrary limit for gen4+ chosen to match the
2763 * render engine max stride.
2765 * The new CCS hash mode makes remapping impossible
2767 if (!is_ccs_modifier(modifier)) {
2768 if (INTEL_GEN(dev_priv) >= 7)
2770 else if (INTEL_GEN(dev_priv) >= 4)
2774 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2778 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2780 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2783 if (is_surface_linear(fb, color_plane)) {
2784 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2789 * To make remapping with linear generally feasible
2790 * we need the stride to be page aligned.
2792 if (fb->pitches[color_plane] > max_stride &&
2793 !is_ccs_modifier(fb->modifier))
2794 return intel_tile_size(dev_priv);
2799 tile_width = intel_tile_width_bytes(fb, color_plane);
2800 if (is_ccs_modifier(fb->modifier)) {
2802 * Display WA #0531: skl,bxt,kbl,glk
2804 * Render decompression and plane width > 3840
2805 * combined with horizontal panning requires the
2806 * plane stride to be a multiple of 4. We'll just
2807 * require the entire fb to accommodate that to avoid
2808 * potential runtime errors at plane configuration time.
2810 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2813 * The main surface pitch must be padded to a multiple of four
2816 else if (INTEL_GEN(dev_priv) >= 12)
2822 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2824 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2825 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2826 const struct drm_framebuffer *fb = plane_state->hw.fb;
2829 /* We don't want to deal with remapping with cursors */
2830 if (plane->id == PLANE_CURSOR)
2834 * The display engine limits already match/exceed the
2835 * render engine limits, so not much point in remapping.
2836 * Would also need to deal with the fence POT alignment
2837 * and gen2 2KiB GTT tile size.
2839 if (INTEL_GEN(dev_priv) < 4)
2843 * The new CCS hash mode isn't compatible with remapping as
2844 * the virtual address of the pages affects the compressed data.
2846 if (is_ccs_modifier(fb->modifier))
2849 /* Linear needs a page aligned stride for remapping */
2850 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2851 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2853 for (i = 0; i < fb->format->num_planes; i++) {
2854 if (fb->pitches[i] & alignment)
2862 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2864 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2865 const struct drm_framebuffer *fb = plane_state->hw.fb;
2866 unsigned int rotation = plane_state->hw.rotation;
2867 u32 stride, max_stride;
2870 * No remapping for invisible planes since we don't have
2871 * an actual source viewport to remap.
2873 if (!plane_state->uapi.visible)
2876 if (!intel_plane_can_remap(plane_state))
2880 * FIXME: aux plane limits on gen9+ are
2881 * unclear in Bspec, for now no checking.
2883 stride = intel_fb_pitch(fb, 0, rotation);
2884 max_stride = plane->max_stride(plane, fb->format->format,
2885 fb->modifier, rotation);
2887 return stride > max_stride;
2891 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2892 const struct drm_framebuffer *fb,
2897 if (color_plane == 0) {
2905 * TODO: Deduct the subsampling from the char block for all CCS
2906 * formats and planes.
2908 if (!is_gen12_ccs_plane(fb, color_plane)) {
2909 *hsub = fb->format->hsub;
2910 *vsub = fb->format->vsub;
2915 main_plane = ccs_to_main_plane(fb, color_plane);
2916 *hsub = drm_format_info_block_width(fb->format, color_plane) /
2917 drm_format_info_block_width(fb->format, main_plane);
2920 * The min stride check in the core framebuffer_check() function
2921 * assumes that format->hsub applies to every plane except for the
2922 * first plane. That's incorrect for the CCS AUX plane of the first
2923 * plane, but for the above check to pass we must define the block
2924 * width with that subsampling applied to it. Adjust the width here
2925 * accordingly, so we can calculate the actual subsampling factor.
2927 if (main_plane == 0)
2928 *hsub *= fb->format->hsub;
2933 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2935 struct drm_i915_private *i915 = to_i915(fb->dev);
2936 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2939 int tile_width, tile_height;
2943 if (!is_ccs_plane(fb, ccs_plane))
2946 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2947 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2950 tile_height *= vsub;
2952 ccs_x = (x * hsub) % tile_width;
2953 ccs_y = (y * vsub) % tile_height;
2955 main_plane = ccs_to_main_plane(fb, ccs_plane);
2956 main_x = intel_fb->normal[main_plane].x % tile_width;
2957 main_y = intel_fb->normal[main_plane].y % tile_height;
2960 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2961 * x/y offsets must match between CCS and the main surface.
2963 if (main_x != ccs_x || main_y != ccs_y) {
2964 drm_dbg_kms(&i915->drm,
2965 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2968 intel_fb->normal[main_plane].x,
2969 intel_fb->normal[main_plane].y,
2978 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2980 int main_plane = is_ccs_plane(fb, color_plane) ?
2981 ccs_to_main_plane(fb, color_plane) : 0;
2982 int main_hsub, main_vsub;
2985 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2986 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2987 *w = fb->width / main_hsub / hsub;
2988 *h = fb->height / main_vsub / vsub;
2992 * Setup the rotated view for an FB plane and return the size the GTT mapping
2993 * requires for this view.
2996 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2997 u32 gtt_offset_rotated, int x, int y,
2998 unsigned int width, unsigned int height,
2999 unsigned int tile_size,
3000 unsigned int tile_width, unsigned int tile_height,
3001 struct drm_framebuffer *fb)
3003 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3004 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
3005 unsigned int pitch_tiles;
3008 /* Y or Yf modifiers required for 90/270 rotation */
3009 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3010 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
3013 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane)))
3016 rot_info->plane[plane] = *plane_info;
3018 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3020 /* rotate the x/y offsets to match the GTT view */
3021 drm_rect_init(&r, x, y, width, height);
3023 plane_info->width * tile_width,
3024 plane_info->height * tile_height,
3025 DRM_MODE_ROTATE_270);
3029 /* rotate the tile dimensions to match the GTT view */
3030 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3031 swap(tile_width, tile_height);
3034 * We only keep the x/y offsets, so push all of the
3035 * gtt offset into the x/y offsets.
3037 intel_adjust_tile_offset(&x, &y,
3038 tile_width, tile_height,
3039 tile_size, pitch_tiles,
3040 gtt_offset_rotated * tile_size, 0);
3043 * First pixel of the framebuffer from
3044 * the start of the rotated gtt mapping.
3046 intel_fb->rotated[plane].x = x;
3047 intel_fb->rotated[plane].y = y;
3049 return plane_info->width * plane_info->height;
3053 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3054 struct drm_framebuffer *fb)
3056 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3057 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3058 u32 gtt_offset_rotated = 0;
3059 unsigned int max_size = 0;
3060 int i, num_planes = fb->format->num_planes;
3061 unsigned int tile_size = intel_tile_size(dev_priv);
3063 for (i = 0; i < num_planes; i++) {
3064 unsigned int width, height;
3065 unsigned int cpp, size;
3070 cpp = fb->format->cpp[i];
3071 intel_fb_plane_dims(&width, &height, fb, i);
3073 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3075 drm_dbg_kms(&dev_priv->drm,
3076 "bad fb plane %d offset: 0x%x\n",
3081 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3086 * The fence (if used) is aligned to the start of the object
3087 * so having the framebuffer wrap around across the edge of the
3088 * fenced region doesn't really work. We have no API to configure
3089 * the fence start offset within the object (nor could we probably
3090 * on gen2/3). So it's just easier if we just require that the
3091 * fb layout agrees with the fence layout. We already check that the
3092 * fb stride matches the fence stride elsewhere.
3094 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3095 (x + width) * cpp > fb->pitches[i]) {
3096 drm_dbg_kms(&dev_priv->drm,
3097 "bad fb plane %d offset: 0x%x\n",
3103 * First pixel of the framebuffer from
3104 * the start of the normal gtt mapping.
3106 intel_fb->normal[i].x = x;
3107 intel_fb->normal[i].y = y;
3109 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3113 offset /= tile_size;
3115 if (!is_surface_linear(fb, i)) {
3116 struct intel_remapped_plane_info plane_info;
3117 unsigned int tile_width, tile_height;
3119 intel_tile_dims(fb, i, &tile_width, &tile_height);
3121 plane_info.offset = offset;
3122 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3124 plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3125 plane_info.height = DIV_ROUND_UP(y + height,
3128 /* how many tiles does this plane need */
3129 size = plane_info.stride * plane_info.height;
3131 * If the plane isn't horizontally tile aligned,
3132 * we need one more tile.
3137 gtt_offset_rotated +=
3138 setup_fb_rotation(i, &plane_info,
3140 x, y, width, height,
3142 tile_width, tile_height,
3145 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3146 x * cpp, tile_size);
3149 /* how many tiles in total needed in the bo */
3150 max_size = max(max_size, offset + size);
3153 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3154 drm_dbg_kms(&dev_priv->drm,
3155 "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3156 mul_u32_u32(max_size, tile_size), obj->base.size);
3164 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3166 struct drm_i915_private *dev_priv =
3167 to_i915(plane_state->uapi.plane->dev);
3168 struct drm_framebuffer *fb = plane_state->hw.fb;
3169 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3170 struct intel_rotation_info *info = &plane_state->view.rotated;
3171 unsigned int rotation = plane_state->hw.rotation;
3172 int i, num_planes = fb->format->num_planes;
3173 unsigned int tile_size = intel_tile_size(dev_priv);
3174 unsigned int src_x, src_y;
3175 unsigned int src_w, src_h;
3178 memset(&plane_state->view, 0, sizeof(plane_state->view));
3179 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3180 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3182 src_x = plane_state->uapi.src.x1 >> 16;
3183 src_y = plane_state->uapi.src.y1 >> 16;
3184 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3185 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3187 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3189 /* Make src coordinates relative to the viewport */
3190 drm_rect_translate(&plane_state->uapi.src,
3191 -(src_x << 16), -(src_y << 16));
3193 /* Rotate src coordinates to match rotated GTT view */
3194 if (drm_rotation_90_or_270(rotation))
3195 drm_rect_rotate(&plane_state->uapi.src,
3196 src_w << 16, src_h << 16,
3197 DRM_MODE_ROTATE_270);
3199 for (i = 0; i < num_planes; i++) {
3200 unsigned int hsub = i ? fb->format->hsub : 1;
3201 unsigned int vsub = i ? fb->format->vsub : 1;
3202 unsigned int cpp = fb->format->cpp[i];
3203 unsigned int tile_width, tile_height;
3204 unsigned int width, height;
3205 unsigned int pitch_tiles;
3209 intel_tile_dims(fb, i, &tile_width, &tile_height);
3213 width = src_w / hsub;
3214 height = src_h / vsub;
3217 * First pixel of the src viewport from the
3218 * start of the normal gtt mapping.
3220 x += intel_fb->normal[i].x;
3221 y += intel_fb->normal[i].y;
3223 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3224 fb, i, fb->pitches[i],
3225 DRM_MODE_ROTATE_0, tile_size);
3226 offset /= tile_size;
3228 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3229 info->plane[i].offset = offset;
3230 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3232 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3233 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3235 if (drm_rotation_90_or_270(rotation)) {
3238 /* rotate the x/y offsets to match the GTT view */
3239 drm_rect_init(&r, x, y, width, height);
3241 info->plane[i].width * tile_width,
3242 info->plane[i].height * tile_height,
3243 DRM_MODE_ROTATE_270);
3247 pitch_tiles = info->plane[i].height;
3248 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3250 /* rotate the tile dimensions to match the GTT view */
3251 swap(tile_width, tile_height);
3253 pitch_tiles = info->plane[i].width;
3254 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3258 * We only keep the x/y offsets, so push all of the
3259 * gtt offset into the x/y offsets.
3261 intel_adjust_tile_offset(&x, &y,
3262 tile_width, tile_height,
3263 tile_size, pitch_tiles,
3264 gtt_offset * tile_size, 0);
3266 gtt_offset += info->plane[i].width * info->plane[i].height;
3268 plane_state->color_plane[i].offset = 0;
3269 plane_state->color_plane[i].x = x;
3270 plane_state->color_plane[i].y = y;
3275 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3277 const struct intel_framebuffer *fb =
3278 to_intel_framebuffer(plane_state->hw.fb);
3279 unsigned int rotation = plane_state->hw.rotation;
3285 num_planes = fb->base.format->num_planes;
3287 if (intel_plane_needs_remap(plane_state)) {
3288 intel_plane_remap_gtt(plane_state);
3291 * Sometimes even remapping can't overcome
3292 * the stride limitations :( Can happen with
3293 * big plane sizes and suitably misaligned
3296 return intel_plane_check_stride(plane_state);
3299 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3301 for (i = 0; i < num_planes; i++) {
3302 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3303 plane_state->color_plane[i].offset = 0;
3305 if (drm_rotation_90_or_270(rotation)) {
3306 plane_state->color_plane[i].x = fb->rotated[i].x;
3307 plane_state->color_plane[i].y = fb->rotated[i].y;
3309 plane_state->color_plane[i].x = fb->normal[i].x;
3310 plane_state->color_plane[i].y = fb->normal[i].y;
3314 /* Rotate src coordinates to match rotated GTT view */
3315 if (drm_rotation_90_or_270(rotation))
3316 drm_rect_rotate(&plane_state->uapi.src,
3317 fb->base.width << 16, fb->base.height << 16,
3318 DRM_MODE_ROTATE_270);
3320 return intel_plane_check_stride(plane_state);
3323 static int i9xx_format_to_fourcc(int format)
3326 case DISPPLANE_8BPP:
3327 return DRM_FORMAT_C8;
3328 case DISPPLANE_BGRA555:
3329 return DRM_FORMAT_ARGB1555;
3330 case DISPPLANE_BGRX555:
3331 return DRM_FORMAT_XRGB1555;
3332 case DISPPLANE_BGRX565:
3333 return DRM_FORMAT_RGB565;
3335 case DISPPLANE_BGRX888:
3336 return DRM_FORMAT_XRGB8888;
3337 case DISPPLANE_RGBX888:
3338 return DRM_FORMAT_XBGR8888;
3339 case DISPPLANE_BGRA888:
3340 return DRM_FORMAT_ARGB8888;
3341 case DISPPLANE_RGBA888:
3342 return DRM_FORMAT_ABGR8888;
3343 case DISPPLANE_BGRX101010:
3344 return DRM_FORMAT_XRGB2101010;
3345 case DISPPLANE_RGBX101010:
3346 return DRM_FORMAT_XBGR2101010;
3347 case DISPPLANE_BGRA101010:
3348 return DRM_FORMAT_ARGB2101010;
3349 case DISPPLANE_RGBA101010:
3350 return DRM_FORMAT_ABGR2101010;
3351 case DISPPLANE_RGBX161616:
3352 return DRM_FORMAT_XBGR16161616F;
3356 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3359 case PLANE_CTL_FORMAT_RGB_565:
3360 return DRM_FORMAT_RGB565;
3361 case PLANE_CTL_FORMAT_NV12:
3362 return DRM_FORMAT_NV12;
3363 case PLANE_CTL_FORMAT_XYUV:
3364 return DRM_FORMAT_XYUV8888;
3365 case PLANE_CTL_FORMAT_P010:
3366 return DRM_FORMAT_P010;
3367 case PLANE_CTL_FORMAT_P012:
3368 return DRM_FORMAT_P012;
3369 case PLANE_CTL_FORMAT_P016:
3370 return DRM_FORMAT_P016;
3371 case PLANE_CTL_FORMAT_Y210:
3372 return DRM_FORMAT_Y210;
3373 case PLANE_CTL_FORMAT_Y212:
3374 return DRM_FORMAT_Y212;
3375 case PLANE_CTL_FORMAT_Y216:
3376 return DRM_FORMAT_Y216;
3377 case PLANE_CTL_FORMAT_Y410:
3378 return DRM_FORMAT_XVYU2101010;
3379 case PLANE_CTL_FORMAT_Y412:
3380 return DRM_FORMAT_XVYU12_16161616;
3381 case PLANE_CTL_FORMAT_Y416:
3382 return DRM_FORMAT_XVYU16161616;
3384 case PLANE_CTL_FORMAT_XRGB_8888:
3387 return DRM_FORMAT_ABGR8888;
3389 return DRM_FORMAT_XBGR8888;
3392 return DRM_FORMAT_ARGB8888;
3394 return DRM_FORMAT_XRGB8888;
3396 case PLANE_CTL_FORMAT_XRGB_2101010:
3399 return DRM_FORMAT_ABGR2101010;
3401 return DRM_FORMAT_XBGR2101010;
3404 return DRM_FORMAT_ARGB2101010;
3406 return DRM_FORMAT_XRGB2101010;
3408 case PLANE_CTL_FORMAT_XRGB_16161616F:
3411 return DRM_FORMAT_ABGR16161616F;
3413 return DRM_FORMAT_XBGR16161616F;
3416 return DRM_FORMAT_ARGB16161616F;
3418 return DRM_FORMAT_XRGB16161616F;
3423 static struct i915_vma *
3424 initial_plane_vma(struct drm_i915_private *i915,
3425 struct intel_initial_plane_config *plane_config)
3427 struct drm_i915_gem_object *obj;
3428 struct i915_vma *vma;
3431 if (plane_config->size == 0)
3434 base = round_down(plane_config->base,
3435 I915_GTT_MIN_ALIGNMENT);
3436 size = round_up(plane_config->base + plane_config->size,
3437 I915_GTT_MIN_ALIGNMENT);
3441 * If the FB is too big, just don't use it since fbdev is not very
3442 * important and we should probably use that space with FBC or other
3445 if (size * 2 > i915->stolen_usable_size)
3448 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3453 * Mark it WT ahead of time to avoid changing the
3454 * cache_level during fbdev initialization. The
3455 * unbind there would get stuck waiting for rcu.
3457 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
3458 I915_CACHE_WT : I915_CACHE_NONE);
3460 switch (plane_config->tiling) {
3461 case I915_TILING_NONE:
3465 obj->tiling_and_stride =
3466 plane_config->fb->base.pitches[0] |
3467 plane_config->tiling;
3470 MISSING_CASE(plane_config->tiling);
3474 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3478 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3481 if (i915_gem_object_is_tiled(obj) &&
3482 !i915_vma_is_map_and_fenceable(vma))
3488 i915_gem_object_put(obj);
3493 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3494 struct intel_initial_plane_config *plane_config)
3496 struct drm_device *dev = crtc->base.dev;
3497 struct drm_i915_private *dev_priv = to_i915(dev);
3498 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3499 struct drm_framebuffer *fb = &plane_config->fb->base;
3500 struct i915_vma *vma;
3502 switch (fb->modifier) {
3503 case DRM_FORMAT_MOD_LINEAR:
3504 case I915_FORMAT_MOD_X_TILED:
3505 case I915_FORMAT_MOD_Y_TILED:
3508 drm_dbg(&dev_priv->drm,
3509 "Unsupported modifier for initial FB: 0x%llx\n",
3514 vma = initial_plane_vma(dev_priv, plane_config);
3518 mode_cmd.pixel_format = fb->format->format;
3519 mode_cmd.width = fb->width;
3520 mode_cmd.height = fb->height;
3521 mode_cmd.pitches[0] = fb->pitches[0];
3522 mode_cmd.modifier[0] = fb->modifier;
3523 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3525 if (intel_framebuffer_init(to_intel_framebuffer(fb),
3526 vma->obj, &mode_cmd)) {
3527 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3531 plane_config->vma = vma;
3540 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3541 struct intel_plane_state *plane_state,
3544 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3546 plane_state->uapi.visible = visible;
3549 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3551 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3554 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3556 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3557 struct drm_plane *plane;
3560 * Active_planes aliases if multiple "primary" or cursor planes
3561 * have been used on the same (or wrong) pipe. plane_mask uses
3562 * unique ids, hence we can use that to reconstruct active_planes.
3564 crtc_state->active_planes = 0;
3566 drm_for_each_plane_mask(plane, &dev_priv->drm,
3567 crtc_state->uapi.plane_mask)
3568 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3571 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3572 struct intel_plane *plane)
3574 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3575 struct intel_crtc_state *crtc_state =
3576 to_intel_crtc_state(crtc->base.state);
3577 struct intel_plane_state *plane_state =
3578 to_intel_plane_state(plane->base.state);
3580 drm_dbg_kms(&dev_priv->drm,
3581 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3582 plane->base.base.id, plane->base.name,
3583 crtc->base.base.id, crtc->base.name);
3585 intel_set_plane_visible(crtc_state, plane_state, false);
3586 fixup_active_planes(crtc_state);
3587 crtc_state->data_rate[plane->id] = 0;
3588 crtc_state->min_cdclk[plane->id] = 0;
3590 if (plane->id == PLANE_PRIMARY)
3591 hsw_disable_ips(crtc_state);
3594 * Vblank time updates from the shadow to live plane control register
3595 * are blocked if the memory self-refresh mode is active at that
3596 * moment. So to make sure the plane gets truly disabled, disable
3597 * first the self-refresh mode. The self-refresh enable bit in turn
3598 * will be checked/applied by the HW only at the next frame start
3599 * event which is after the vblank start event, so we need to have a
3600 * wait-for-vblank between disabling the plane and the pipe.
3602 if (HAS_GMCH(dev_priv) &&
3603 intel_set_memory_cxsr(dev_priv, false))
3604 intel_wait_for_vblank(dev_priv, crtc->pipe);
3607 * Gen2 reports pipe underruns whenever all planes are disabled.
3608 * So disable underrun reporting before all the planes get disabled.
3610 if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3611 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3613 intel_disable_plane(plane, crtc_state);
3616 static struct intel_frontbuffer *
3617 to_intel_frontbuffer(struct drm_framebuffer *fb)
3619 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3623 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3624 struct intel_initial_plane_config *plane_config)
3626 struct drm_device *dev = intel_crtc->base.dev;
3627 struct drm_i915_private *dev_priv = to_i915(dev);
3629 struct drm_plane *primary = intel_crtc->base.primary;
3630 struct drm_plane_state *plane_state = primary->state;
3631 struct intel_plane *intel_plane = to_intel_plane(primary);
3632 struct intel_plane_state *intel_state =
3633 to_intel_plane_state(plane_state);
3634 struct drm_framebuffer *fb;
3635 struct i915_vma *vma;
3637 if (!plane_config->fb)
3640 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3641 fb = &plane_config->fb->base;
3642 vma = plane_config->vma;
3647 * Failed to alloc the obj, check to see if we should share
3648 * an fb with another CRTC instead
3650 for_each_crtc(dev, c) {
3651 struct intel_plane_state *state;
3653 if (c == &intel_crtc->base)
3656 if (!to_intel_crtc(c)->active)
3659 state = to_intel_plane_state(c->primary->state);
3663 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3671 * We've failed to reconstruct the BIOS FB. Current display state
3672 * indicates that the primary plane is visible, but has a NULL FB,
3673 * which will lead to problems later if we don't fix it up. The
3674 * simplest solution is to just disable the primary plane now and
3675 * pretend the BIOS never had it enabled.
3677 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3682 intel_state->hw.rotation = plane_config->rotation;
3683 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3684 intel_state->hw.rotation);
3685 intel_state->color_plane[0].stride =
3686 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3688 __i915_vma_pin(vma);
3689 intel_state->vma = i915_vma_get(vma);
3690 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3692 intel_state->flags |= PLANE_HAS_FENCE;
3694 plane_state->src_x = 0;
3695 plane_state->src_y = 0;
3696 plane_state->src_w = fb->width << 16;
3697 plane_state->src_h = fb->height << 16;
3699 plane_state->crtc_x = 0;
3700 plane_state->crtc_y = 0;
3701 plane_state->crtc_w = fb->width;
3702 plane_state->crtc_h = fb->height;
3704 intel_state->uapi.src = drm_plane_state_src(plane_state);
3705 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3707 if (plane_config->tiling)
3708 dev_priv->preserve_bios_swizzle = true;
3710 plane_state->fb = fb;
3711 drm_framebuffer_get(fb);
3713 plane_state->crtc = &intel_crtc->base;
3714 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3716 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3718 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3719 &to_intel_frontbuffer(fb)->bits);
3724 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3725 int main_x, int main_y, u32 main_offset,
3728 const struct drm_framebuffer *fb = plane_state->hw.fb;
3729 int aux_x = plane_state->color_plane[ccs_plane].x;
3730 int aux_y = plane_state->color_plane[ccs_plane].y;
3731 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3732 u32 alignment = intel_surf_alignment(fb, ccs_plane);
3736 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3737 while (aux_offset >= main_offset && aux_y <= main_y) {
3740 if (aux_x == main_x && aux_y == main_y)
3743 if (aux_offset == 0)
3748 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3754 aux_x = x * hsub + aux_x % hsub;
3755 aux_y = y * vsub + aux_y % vsub;
3758 if (aux_x != main_x || aux_y != main_y)
3761 plane_state->color_plane[ccs_plane].offset = aux_offset;
3762 plane_state->color_plane[ccs_plane].x = aux_x;
3763 plane_state->color_plane[ccs_plane].y = aux_y;
3769 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3773 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3774 plane_state->color_plane[0].offset, 0);
3779 static int intel_plane_min_width(struct intel_plane *plane,
3780 const struct drm_framebuffer *fb,
3782 unsigned int rotation)
3784 if (plane->min_width)
3785 return plane->min_width(fb, color_plane, rotation);
3790 static int intel_plane_max_width(struct intel_plane *plane,
3791 const struct drm_framebuffer *fb,
3793 unsigned int rotation)
3795 if (plane->max_width)
3796 return plane->max_width(fb, color_plane, rotation);
3801 static int intel_plane_max_height(struct intel_plane *plane,
3802 const struct drm_framebuffer *fb,
3804 unsigned int rotation)
3806 if (plane->max_height)
3807 return plane->max_height(fb, color_plane, rotation);
3812 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3814 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3815 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
3816 const struct drm_framebuffer *fb = plane_state->hw.fb;
3817 unsigned int rotation = plane_state->hw.rotation;
3818 int x = plane_state->uapi.src.x1 >> 16;
3819 int y = plane_state->uapi.src.y1 >> 16;
3820 int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3821 int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3822 int min_width = intel_plane_min_width(plane, fb, 0, rotation);
3823 int max_width = intel_plane_max_width(plane, fb, 0, rotation);
3824 int max_height = intel_plane_max_height(plane, fb, 0, rotation);
3825 int aux_plane = intel_main_to_aux_plane(fb, 0);
3826 u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3827 u32 alignment, offset;
3829 if (w > max_width || w < min_width || h > max_height) {
3830 drm_dbg_kms(&dev_priv->drm,
3831 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
3832 w, h, min_width, max_width, max_height);
3836 intel_add_fb_offsets(&x, &y, plane_state, 0);
3837 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3838 alignment = intel_surf_alignment(fb, 0);
3839 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3843 * AUX surface offset is specified as the distance from the
3844 * main surface offset, and it must be non-negative. Make
3845 * sure that is what we will get.
3847 if (aux_plane && offset > aux_offset)
3848 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3849 offset, aux_offset & ~(alignment - 1));
3852 * When using an X-tiled surface, the plane blows up
3853 * if the x offset + width exceed the stride.
3855 * TODO: linear and Y-tiled seem fine, Yf untested,
3857 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3858 int cpp = fb->format->cpp[0];
3860 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3862 drm_dbg_kms(&dev_priv->drm,
3863 "Unable to find suitable display surface offset due to X-tiling\n");
3867 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3868 offset, offset - alignment);
3873 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3874 * they match with the main surface x/y offsets.
3876 if (is_ccs_modifier(fb->modifier)) {
3877 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3878 offset, aux_plane)) {
3882 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3883 offset, offset - alignment);
3886 if (x != plane_state->color_plane[aux_plane].x ||
3887 y != plane_state->color_plane[aux_plane].y) {
3888 drm_dbg_kms(&dev_priv->drm,
3889 "Unable to find suitable display surface offset due to CCS\n");
3894 plane_state->color_plane[0].offset = offset;
3895 plane_state->color_plane[0].x = x;
3896 plane_state->color_plane[0].y = y;
3899 * Put the final coordinates back so that the src
3900 * coordinate checks will see the right values.
3902 drm_rect_translate_to(&plane_state->uapi.src,
3908 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3910 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3911 struct drm_i915_private *i915 = to_i915(plane->base.dev);
3912 const struct drm_framebuffer *fb = plane_state->hw.fb;
3913 unsigned int rotation = plane_state->hw.rotation;
3915 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
3916 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
3917 int x = plane_state->uapi.src.x1 >> 17;
3918 int y = plane_state->uapi.src.y1 >> 17;
3919 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3920 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3923 /* FIXME not quite sure how/if these apply to the chroma plane */
3924 if (w > max_width || h > max_height) {
3925 drm_dbg_kms(&i915->drm,
3926 "CbCr source size %dx%d too big (limit %dx%d)\n",
3927 w, h, max_width, max_height);
3931 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
3932 offset = intel_plane_compute_aligned_offset(&x, &y,
3933 plane_state, uv_plane);
3935 if (is_ccs_modifier(fb->modifier)) {
3936 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
3937 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3938 u32 alignment = intel_surf_alignment(fb, uv_plane);
3940 if (offset > aux_offset)
3941 offset = intel_plane_adjust_aligned_offset(&x, &y,
3945 aux_offset & ~(alignment - 1));
3947 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3948 offset, ccs_plane)) {
3952 offset = intel_plane_adjust_aligned_offset(&x, &y,
3955 offset, offset - alignment);
3958 if (x != plane_state->color_plane[ccs_plane].x ||
3959 y != plane_state->color_plane[ccs_plane].y) {
3960 drm_dbg_kms(&i915->drm,
3961 "Unable to find suitable display surface offset due to CCS\n");
3966 plane_state->color_plane[uv_plane].offset = offset;
3967 plane_state->color_plane[uv_plane].x = x;
3968 plane_state->color_plane[uv_plane].y = y;
3973 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3975 const struct drm_framebuffer *fb = plane_state->hw.fb;
3976 int src_x = plane_state->uapi.src.x1 >> 16;
3977 int src_y = plane_state->uapi.src.y1 >> 16;
3981 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
3982 int main_hsub, main_vsub;
3986 if (!is_ccs_plane(fb, ccs_plane))
3989 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
3990 ccs_to_main_plane(fb, ccs_plane));
3991 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3998 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4000 offset = intel_plane_compute_aligned_offset(&x, &y,
4004 plane_state->color_plane[ccs_plane].offset = offset;
4005 plane_state->color_plane[ccs_plane].x = (x * hsub +
4008 plane_state->color_plane[ccs_plane].y = (y * vsub +
4016 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4018 const struct drm_framebuffer *fb = plane_state->hw.fb;
4021 ret = intel_plane_compute_gtt(plane_state);
4025 if (!plane_state->uapi.visible)
4029 * Handle the AUX surface first since the main surface setup depends on
4032 if (is_ccs_modifier(fb->modifier)) {
4033 ret = skl_check_ccs_aux_surface(plane_state);
4038 if (intel_format_info_is_yuv_semiplanar(fb->format,
4040 ret = skl_check_nv12_aux_surface(plane_state);
4045 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
4046 plane_state->color_plane[i].offset = 0;
4047 plane_state->color_plane[i].x = 0;
4048 plane_state->color_plane[i].y = 0;
4051 ret = skl_check_main_surface(plane_state);
4058 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4059 const struct intel_plane_state *plane_state,
4060 unsigned int *num, unsigned int *den)
4062 const struct drm_framebuffer *fb = plane_state->hw.fb;
4063 unsigned int cpp = fb->format->cpp[0];
4066 * g4x bspec says 64bpp pixel rate can't exceed 80%
4067 * of cdclk when the sprite plane is enabled on the
4068 * same pipe. ilk/snb bspec says 64bpp pixel rate is
4069 * never allowed to exceed 80% of cdclk. Let's just go
4070 * with the ilk/snb limit always.
4081 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4082 const struct intel_plane_state *plane_state)
4084 unsigned int pixel_rate;
4085 unsigned int num, den;
4088 * Note that crtc_state->pixel_rate accounts for both
4089 * horizontal and vertical panel fitter downscaling factors.
4090 * Pre-HSW bspec tells us to only consider the horizontal
4091 * downscaling factor here. We ignore that and just consider
4092 * both for simplicity.
4094 pixel_rate = crtc_state->pixel_rate;
4096 i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4098 /* two pixels per clock with double wide pipe */
4099 if (crtc_state->double_wide)
4102 return DIV_ROUND_UP(pixel_rate * num, den);
4106 i9xx_plane_max_stride(struct intel_plane *plane,
4107 u32 pixel_format, u64 modifier,
4108 unsigned int rotation)
4110 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4112 if (!HAS_GMCH(dev_priv)) {
4114 } else if (INTEL_GEN(dev_priv) >= 4) {
4115 if (modifier == I915_FORMAT_MOD_X_TILED)
4119 } else if (INTEL_GEN(dev_priv) >= 3) {
4120 if (modifier == I915_FORMAT_MOD_X_TILED)
4125 if (plane->i9xx_plane == PLANE_C)
4132 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4134 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4135 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4138 if (crtc_state->gamma_enable)
4139 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4141 if (crtc_state->csc_enable)
4142 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4144 if (INTEL_GEN(dev_priv) < 5)
4145 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4150 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4151 const struct intel_plane_state *plane_state)
4153 struct drm_i915_private *dev_priv =
4154 to_i915(plane_state->uapi.plane->dev);
4155 const struct drm_framebuffer *fb = plane_state->hw.fb;
4156 unsigned int rotation = plane_state->hw.rotation;
4159 dspcntr = DISPLAY_PLANE_ENABLE;
4161 if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4162 IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4163 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4165 switch (fb->format->format) {
4167 dspcntr |= DISPPLANE_8BPP;
4169 case DRM_FORMAT_XRGB1555:
4170 dspcntr |= DISPPLANE_BGRX555;
4172 case DRM_FORMAT_ARGB1555:
4173 dspcntr |= DISPPLANE_BGRA555;
4175 case DRM_FORMAT_RGB565:
4176 dspcntr |= DISPPLANE_BGRX565;
4178 case DRM_FORMAT_XRGB8888:
4179 dspcntr |= DISPPLANE_BGRX888;
4181 case DRM_FORMAT_XBGR8888:
4182 dspcntr |= DISPPLANE_RGBX888;
4184 case DRM_FORMAT_ARGB8888:
4185 dspcntr |= DISPPLANE_BGRA888;
4187 case DRM_FORMAT_ABGR8888:
4188 dspcntr |= DISPPLANE_RGBA888;
4190 case DRM_FORMAT_XRGB2101010:
4191 dspcntr |= DISPPLANE_BGRX101010;
4193 case DRM_FORMAT_XBGR2101010:
4194 dspcntr |= DISPPLANE_RGBX101010;
4196 case DRM_FORMAT_ARGB2101010:
4197 dspcntr |= DISPPLANE_BGRA101010;
4199 case DRM_FORMAT_ABGR2101010:
4200 dspcntr |= DISPPLANE_RGBA101010;
4202 case DRM_FORMAT_XBGR16161616F:
4203 dspcntr |= DISPPLANE_RGBX161616;
4206 MISSING_CASE(fb->format->format);
4210 if (INTEL_GEN(dev_priv) >= 4 &&
4211 fb->modifier == I915_FORMAT_MOD_X_TILED)
4212 dspcntr |= DISPPLANE_TILED;
4214 if (rotation & DRM_MODE_ROTATE_180)
4215 dspcntr |= DISPPLANE_ROTATE_180;
4217 if (rotation & DRM_MODE_REFLECT_X)
4218 dspcntr |= DISPPLANE_MIRROR;
4223 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4225 struct drm_i915_private *dev_priv =
4226 to_i915(plane_state->uapi.plane->dev);
4227 const struct drm_framebuffer *fb = plane_state->hw.fb;
4228 int src_x, src_y, src_w;
4232 ret = intel_plane_compute_gtt(plane_state);
4236 if (!plane_state->uapi.visible)
4239 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4240 src_x = plane_state->uapi.src.x1 >> 16;
4241 src_y = plane_state->uapi.src.y1 >> 16;
4243 /* Undocumented hardware limit on i965/g4x/vlv/chv */
4244 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4247 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4249 if (INTEL_GEN(dev_priv) >= 4)
4250 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4256 * Put the final coordinates back so that the src
4257 * coordinate checks will see the right values.
4259 drm_rect_translate_to(&plane_state->uapi.src,
4260 src_x << 16, src_y << 16);
4262 /* HSW/BDW do this automagically in hardware */
4263 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4264 unsigned int rotation = plane_state->hw.rotation;
4265 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4266 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4268 if (rotation & DRM_MODE_ROTATE_180) {
4271 } else if (rotation & DRM_MODE_REFLECT_X) {
4276 plane_state->color_plane[0].offset = offset;
4277 plane_state->color_plane[0].x = src_x;
4278 plane_state->color_plane[0].y = src_y;
4283 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4285 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4286 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4288 if (IS_CHERRYVIEW(dev_priv))
4289 return i9xx_plane == PLANE_B;
4290 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4292 else if (IS_GEN(dev_priv, 4))
4293 return i9xx_plane == PLANE_C;
4295 return i9xx_plane == PLANE_B ||
4296 i9xx_plane == PLANE_C;
4300 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4301 struct intel_plane_state *plane_state)
4303 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4306 ret = chv_plane_check_rotation(plane_state);
4310 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4312 DRM_PLANE_HELPER_NO_SCALING,
4313 DRM_PLANE_HELPER_NO_SCALING,
4314 i9xx_plane_has_windowing(plane),
4319 ret = i9xx_check_plane_surface(plane_state);
4323 if (!plane_state->uapi.visible)
4326 ret = intel_plane_check_src_coordinates(plane_state);
4330 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4335 static void i9xx_update_plane(struct intel_plane *plane,
4336 const struct intel_crtc_state *crtc_state,
4337 const struct intel_plane_state *plane_state)
4339 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4340 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4342 int x = plane_state->color_plane[0].x;
4343 int y = plane_state->color_plane[0].y;
4344 int crtc_x = plane_state->uapi.dst.x1;
4345 int crtc_y = plane_state->uapi.dst.y1;
4346 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4347 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4348 unsigned long irqflags;
4352 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4354 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4356 if (INTEL_GEN(dev_priv) >= 4)
4357 dspaddr_offset = plane_state->color_plane[0].offset;
4359 dspaddr_offset = linear_offset;
4361 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4363 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4364 plane_state->color_plane[0].stride);
4366 if (INTEL_GEN(dev_priv) < 4) {
4368 * PLANE_A doesn't actually have a full window
4369 * generator but let's assume we still need to
4370 * program whatever is there.
4372 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4373 (crtc_y << 16) | crtc_x);
4374 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4375 ((crtc_h - 1) << 16) | (crtc_w - 1));
4376 } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4377 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4378 (crtc_y << 16) | crtc_x);
4379 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4380 ((crtc_h - 1) << 16) | (crtc_w - 1));
4381 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4384 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4385 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4387 } else if (INTEL_GEN(dev_priv) >= 4) {
4388 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4390 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4395 * The control register self-arms if the plane was previously
4396 * disabled. Try to make the plane enable atomic by writing
4397 * the control register just before the surface register.
4399 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4400 if (INTEL_GEN(dev_priv) >= 4)
4401 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4402 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4404 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4405 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4407 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4410 static void i9xx_disable_plane(struct intel_plane *plane,
4411 const struct intel_crtc_state *crtc_state)
4413 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4414 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4415 unsigned long irqflags;
4419 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4420 * enable on ilk+ affect the pipe bottom color as
4421 * well, so we must configure them even if the plane
4424 * On pre-g4x there is no way to gamma correct the
4425 * pipe bottom color but we'll keep on doing this
4426 * anyway so that the crtc state readout works correctly.
4428 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4430 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4432 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4433 if (INTEL_GEN(dev_priv) >= 4)
4434 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4436 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4438 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4441 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4444 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4445 enum intel_display_power_domain power_domain;
4446 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4447 intel_wakeref_t wakeref;
4452 * Not 100% correct for planes that can move between pipes,
4453 * but that's only the case for gen2-4 which don't have any
4454 * display power wells.
4456 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4457 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4461 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4463 ret = val & DISPLAY_PLANE_ENABLE;
4465 if (INTEL_GEN(dev_priv) >= 5)
4466 *pipe = plane->pipe;
4468 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4469 DISPPLANE_SEL_PIPE_SHIFT;
4471 intel_display_power_put(dev_priv, power_domain, wakeref);
4476 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4478 struct drm_device *dev = intel_crtc->base.dev;
4479 struct drm_i915_private *dev_priv = to_i915(dev);
4480 unsigned long irqflags;
4482 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4484 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4485 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4486 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4488 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4492 * This function detaches (aka. unbinds) unused scalers in hardware
4494 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4497 const struct intel_crtc_scaler_state *scaler_state =
4498 &crtc_state->scaler_state;
4501 /* loop through and disable scalers that aren't in use */
4502 for (i = 0; i < intel_crtc->num_scalers; i++) {
4503 if (!scaler_state->scalers[i].in_use)
4504 skl_detach_scaler(intel_crtc, i);
4508 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4509 int color_plane, unsigned int rotation)
4512 * The stride is either expressed as a multiple of 64 bytes chunks for
4513 * linear buffers or in number of tiles for tiled buffers.
4515 if (is_surface_linear(fb, color_plane))
4517 else if (drm_rotation_90_or_270(rotation))
4518 return intel_tile_height(fb, color_plane);
4520 return intel_tile_width_bytes(fb, color_plane);
4523 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4526 const struct drm_framebuffer *fb = plane_state->hw.fb;
4527 unsigned int rotation = plane_state->hw.rotation;
4528 u32 stride = plane_state->color_plane[color_plane].stride;
4530 if (color_plane >= fb->format->num_planes)
4533 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4536 static u32 skl_plane_ctl_format(u32 pixel_format)
4538 switch (pixel_format) {
4540 return PLANE_CTL_FORMAT_INDEXED;
4541 case DRM_FORMAT_RGB565:
4542 return PLANE_CTL_FORMAT_RGB_565;
4543 case DRM_FORMAT_XBGR8888:
4544 case DRM_FORMAT_ABGR8888:
4545 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4546 case DRM_FORMAT_XRGB8888:
4547 case DRM_FORMAT_ARGB8888:
4548 return PLANE_CTL_FORMAT_XRGB_8888;
4549 case DRM_FORMAT_XBGR2101010:
4550 case DRM_FORMAT_ABGR2101010:
4551 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4552 case DRM_FORMAT_XRGB2101010:
4553 case DRM_FORMAT_ARGB2101010:
4554 return PLANE_CTL_FORMAT_XRGB_2101010;
4555 case DRM_FORMAT_XBGR16161616F:
4556 case DRM_FORMAT_ABGR16161616F:
4557 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4558 case DRM_FORMAT_XRGB16161616F:
4559 case DRM_FORMAT_ARGB16161616F:
4560 return PLANE_CTL_FORMAT_XRGB_16161616F;
4561 case DRM_FORMAT_XYUV8888:
4562 return PLANE_CTL_FORMAT_XYUV;
4563 case DRM_FORMAT_YUYV:
4564 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4565 case DRM_FORMAT_YVYU:
4566 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4567 case DRM_FORMAT_UYVY:
4568 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4569 case DRM_FORMAT_VYUY:
4570 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4571 case DRM_FORMAT_NV12:
4572 return PLANE_CTL_FORMAT_NV12;
4573 case DRM_FORMAT_P010:
4574 return PLANE_CTL_FORMAT_P010;
4575 case DRM_FORMAT_P012:
4576 return PLANE_CTL_FORMAT_P012;
4577 case DRM_FORMAT_P016:
4578 return PLANE_CTL_FORMAT_P016;
4579 case DRM_FORMAT_Y210:
4580 return PLANE_CTL_FORMAT_Y210;
4581 case DRM_FORMAT_Y212:
4582 return PLANE_CTL_FORMAT_Y212;
4583 case DRM_FORMAT_Y216:
4584 return PLANE_CTL_FORMAT_Y216;
4585 case DRM_FORMAT_XVYU2101010:
4586 return PLANE_CTL_FORMAT_Y410;
4587 case DRM_FORMAT_XVYU12_16161616:
4588 return PLANE_CTL_FORMAT_Y412;
4589 case DRM_FORMAT_XVYU16161616:
4590 return PLANE_CTL_FORMAT_Y416;
4592 MISSING_CASE(pixel_format);
4598 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4600 if (!plane_state->hw.fb->format->has_alpha)
4601 return PLANE_CTL_ALPHA_DISABLE;
4603 switch (plane_state->hw.pixel_blend_mode) {
4604 case DRM_MODE_BLEND_PIXEL_NONE:
4605 return PLANE_CTL_ALPHA_DISABLE;
4606 case DRM_MODE_BLEND_PREMULTI:
4607 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4608 case DRM_MODE_BLEND_COVERAGE:
4609 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4611 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4612 return PLANE_CTL_ALPHA_DISABLE;
4616 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4618 if (!plane_state->hw.fb->format->has_alpha)
4619 return PLANE_COLOR_ALPHA_DISABLE;
4621 switch (plane_state->hw.pixel_blend_mode) {
4622 case DRM_MODE_BLEND_PIXEL_NONE:
4623 return PLANE_COLOR_ALPHA_DISABLE;
4624 case DRM_MODE_BLEND_PREMULTI:
4625 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4626 case DRM_MODE_BLEND_COVERAGE:
4627 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4629 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4630 return PLANE_COLOR_ALPHA_DISABLE;
4634 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4636 switch (fb_modifier) {
4637 case DRM_FORMAT_MOD_LINEAR:
4639 case I915_FORMAT_MOD_X_TILED:
4640 return PLANE_CTL_TILED_X;
4641 case I915_FORMAT_MOD_Y_TILED:
4642 return PLANE_CTL_TILED_Y;
4643 case I915_FORMAT_MOD_Y_TILED_CCS:
4644 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4645 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4646 return PLANE_CTL_TILED_Y |
4647 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4648 PLANE_CTL_CLEAR_COLOR_DISABLE;
4649 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4650 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4651 case I915_FORMAT_MOD_Yf_TILED:
4652 return PLANE_CTL_TILED_YF;
4653 case I915_FORMAT_MOD_Yf_TILED_CCS:
4654 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4656 MISSING_CASE(fb_modifier);
4662 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4665 case DRM_MODE_ROTATE_0:
4668 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4669 * while i915 HW rotation is clockwise, thats why this swapping.
4671 case DRM_MODE_ROTATE_90:
4672 return PLANE_CTL_ROTATE_270;
4673 case DRM_MODE_ROTATE_180:
4674 return PLANE_CTL_ROTATE_180;
4675 case DRM_MODE_ROTATE_270:
4676 return PLANE_CTL_ROTATE_90;
4678 MISSING_CASE(rotate);
4684 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4689 case DRM_MODE_REFLECT_X:
4690 return PLANE_CTL_FLIP_HORIZONTAL;
4691 case DRM_MODE_REFLECT_Y:
4693 MISSING_CASE(reflect);
4699 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4701 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4704 if (crtc_state->uapi.async_flip)
4705 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
4707 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4710 if (crtc_state->gamma_enable)
4711 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4713 if (crtc_state->csc_enable)
4714 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4719 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4720 const struct intel_plane_state *plane_state)
4722 struct drm_i915_private *dev_priv =
4723 to_i915(plane_state->uapi.plane->dev);
4724 const struct drm_framebuffer *fb = plane_state->hw.fb;
4725 unsigned int rotation = plane_state->hw.rotation;
4726 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4729 plane_ctl = PLANE_CTL_ENABLE;
4731 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4732 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4733 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4735 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4736 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4738 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4739 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4742 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4743 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4744 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4746 if (INTEL_GEN(dev_priv) >= 10)
4747 plane_ctl |= cnl_plane_ctl_flip(rotation &
4748 DRM_MODE_REFLECT_MASK);
4750 if (key->flags & I915_SET_COLORKEY_DESTINATION)
4751 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4752 else if (key->flags & I915_SET_COLORKEY_SOURCE)
4753 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4758 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4760 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4761 u32 plane_color_ctl = 0;
4763 if (INTEL_GEN(dev_priv) >= 11)
4764 return plane_color_ctl;
4766 if (crtc_state->gamma_enable)
4767 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4769 if (crtc_state->csc_enable)
4770 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4772 return plane_color_ctl;
4775 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4776 const struct intel_plane_state *plane_state)
4778 struct drm_i915_private *dev_priv =
4779 to_i915(plane_state->uapi.plane->dev);
4780 const struct drm_framebuffer *fb = plane_state->hw.fb;
4781 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4782 u32 plane_color_ctl = 0;
4784 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4785 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4787 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4788 switch (plane_state->hw.color_encoding) {
4789 case DRM_COLOR_YCBCR_BT709:
4790 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4792 case DRM_COLOR_YCBCR_BT2020:
4794 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
4798 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
4800 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4801 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4802 } else if (fb->format->is_yuv) {
4803 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4806 return plane_color_ctl;
4810 __intel_display_resume(struct drm_device *dev,
4811 struct drm_atomic_state *state,
4812 struct drm_modeset_acquire_ctx *ctx)
4814 struct drm_crtc_state *crtc_state;
4815 struct drm_crtc *crtc;
4818 intel_modeset_setup_hw_state(dev, ctx);
4819 intel_vga_redisable(to_i915(dev));
4825 * We've duplicated the state, pointers to the old state are invalid.
4827 * Don't attempt to use the old state until we commit the duplicated state.
4829 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4831 * Force recalculation even if we restore
4832 * current state. With fast modeset this may not result
4833 * in a modeset when the state is compatible.
4835 crtc_state->mode_changed = true;
4838 /* ignore any reset values/BIOS leftovers in the WM registers */
4839 if (!HAS_GMCH(to_i915(dev)))
4840 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4842 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4844 drm_WARN_ON(dev, ret == -EDEADLK);
4848 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4850 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4851 intel_has_gpu_reset(&dev_priv->gt));
4854 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
4856 struct drm_device *dev = &dev_priv->drm;
4857 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4858 struct drm_atomic_state *state;
4861 if (!HAS_DISPLAY(dev_priv))
4864 /* reset doesn't touch the display */
4865 if (!dev_priv->params.force_reset_modeset_test &&
4866 !gpu_reset_clobbers_display(dev_priv))
4869 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4870 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4871 smp_mb__after_atomic();
4872 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4874 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4875 drm_dbg_kms(&dev_priv->drm,
4876 "Modeset potentially stuck, unbreaking through wedging\n");
4877 intel_gt_set_wedged(&dev_priv->gt);
4881 * Need mode_config.mutex so that we don't
4882 * trample ongoing ->detect() and whatnot.
4884 mutex_lock(&dev->mode_config.mutex);
4885 drm_modeset_acquire_init(ctx, 0);
4887 ret = drm_modeset_lock_all_ctx(dev, ctx);
4888 if (ret != -EDEADLK)
4891 drm_modeset_backoff(ctx);
4894 * Disabling the crtcs gracefully seems nicer. Also the
4895 * g33 docs say we should at least disable all the planes.
4897 state = drm_atomic_helper_duplicate_state(dev, ctx);
4898 if (IS_ERR(state)) {
4899 ret = PTR_ERR(state);
4900 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
4905 ret = drm_atomic_helper_disable_all(dev, ctx);
4907 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4909 drm_atomic_state_put(state);
4913 dev_priv->modeset_restore_state = state;
4914 state->acquire_ctx = ctx;
4917 void intel_display_finish_reset(struct drm_i915_private *dev_priv)
4919 struct drm_device *dev = &dev_priv->drm;
4920 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4921 struct drm_atomic_state *state;
4924 if (!HAS_DISPLAY(dev_priv))
4927 /* reset doesn't touch the display */
4928 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4931 state = fetch_and_zero(&dev_priv->modeset_restore_state);
4935 /* reset doesn't touch the display */
4936 if (!gpu_reset_clobbers_display(dev_priv)) {
4937 /* for testing only restore the display */
4938 ret = __intel_display_resume(dev, state, ctx);
4940 drm_err(&dev_priv->drm,
4941 "Restoring old state failed with %i\n", ret);
4944 * The display has been reset as well,
4945 * so need a full re-initialization.
4947 intel_pps_unlock_regs_wa(dev_priv);
4948 intel_modeset_init_hw(dev_priv);
4949 intel_init_clock_gating(dev_priv);
4950 intel_hpd_init(dev_priv);
4952 ret = __intel_display_resume(dev, state, ctx);
4954 drm_err(&dev_priv->drm,
4955 "Restoring old state failed with %i\n", ret);
4957 intel_hpd_poll_disable(dev_priv);
4960 drm_atomic_state_put(state);
4962 drm_modeset_drop_locks(ctx);
4963 drm_modeset_acquire_fini(ctx);
4964 mutex_unlock(&dev->mode_config.mutex);
4966 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4969 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4971 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4972 enum pipe pipe = crtc->pipe;
4975 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
4978 * Display WA #1153: icl
4979 * enable hardware to bypass the alpha math
4980 * and rounding for per-pixel values 00 and 0xff
4982 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4984 * Display WA # 1605353570: icl
4985 * Set the pixel rounding bit to 1 for allowing
4986 * passthrough of Frame buffer pixels unmodified
4989 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4990 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
4993 static void intel_fdi_normal_train(struct intel_crtc *crtc)
4995 struct drm_device *dev = crtc->base.dev;
4996 struct drm_i915_private *dev_priv = to_i915(dev);
4997 enum pipe pipe = crtc->pipe;
5001 /* enable normal train */
5002 reg = FDI_TX_CTL(pipe);
5003 temp = intel_de_read(dev_priv, reg);
5004 if (IS_IVYBRIDGE(dev_priv)) {
5005 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5006 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5008 temp &= ~FDI_LINK_TRAIN_NONE;
5009 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5011 intel_de_write(dev_priv, reg, temp);
5013 reg = FDI_RX_CTL(pipe);
5014 temp = intel_de_read(dev_priv, reg);
5015 if (HAS_PCH_CPT(dev_priv)) {
5016 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5017 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5019 temp &= ~FDI_LINK_TRAIN_NONE;
5020 temp |= FDI_LINK_TRAIN_NONE;
5022 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5024 /* wait one idle pattern time */
5025 intel_de_posting_read(dev_priv, reg);
5028 /* IVB wants error correction enabled */
5029 if (IS_IVYBRIDGE(dev_priv))
5030 intel_de_write(dev_priv, reg,
5031 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5034 /* The FDI link training functions for ILK/Ibexpeak. */
5035 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5036 const struct intel_crtc_state *crtc_state)
5038 struct drm_device *dev = crtc->base.dev;
5039 struct drm_i915_private *dev_priv = to_i915(dev);
5040 enum pipe pipe = crtc->pipe;
5044 /* FDI needs bits from pipe first */
5045 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5047 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5049 reg = FDI_RX_IMR(pipe);
5050 temp = intel_de_read(dev_priv, reg);
5051 temp &= ~FDI_RX_SYMBOL_LOCK;
5052 temp &= ~FDI_RX_BIT_LOCK;
5053 intel_de_write(dev_priv, reg, temp);
5054 intel_de_read(dev_priv, reg);
5057 /* enable CPU FDI TX and PCH FDI RX */
5058 reg = FDI_TX_CTL(pipe);
5059 temp = intel_de_read(dev_priv, reg);
5060 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5061 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5062 temp &= ~FDI_LINK_TRAIN_NONE;
5063 temp |= FDI_LINK_TRAIN_PATTERN_1;
5064 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5066 reg = FDI_RX_CTL(pipe);
5067 temp = intel_de_read(dev_priv, reg);
5068 temp &= ~FDI_LINK_TRAIN_NONE;
5069 temp |= FDI_LINK_TRAIN_PATTERN_1;
5070 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5072 intel_de_posting_read(dev_priv, reg);
5075 /* Ironlake workaround, enable clock pointer after FDI enable*/
5076 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5077 FDI_RX_PHASE_SYNC_POINTER_OVR);
5078 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5079 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5081 reg = FDI_RX_IIR(pipe);
5082 for (tries = 0; tries < 5; tries++) {
5083 temp = intel_de_read(dev_priv, reg);
5084 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5086 if ((temp & FDI_RX_BIT_LOCK)) {
5087 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5088 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5093 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5096 reg = FDI_TX_CTL(pipe);
5097 temp = intel_de_read(dev_priv, reg);
5098 temp &= ~FDI_LINK_TRAIN_NONE;
5099 temp |= FDI_LINK_TRAIN_PATTERN_2;
5100 intel_de_write(dev_priv, reg, temp);
5102 reg = FDI_RX_CTL(pipe);
5103 temp = intel_de_read(dev_priv, reg);
5104 temp &= ~FDI_LINK_TRAIN_NONE;
5105 temp |= FDI_LINK_TRAIN_PATTERN_2;
5106 intel_de_write(dev_priv, reg, temp);
5108 intel_de_posting_read(dev_priv, reg);
5111 reg = FDI_RX_IIR(pipe);
5112 for (tries = 0; tries < 5; tries++) {
5113 temp = intel_de_read(dev_priv, reg);
5114 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5116 if (temp & FDI_RX_SYMBOL_LOCK) {
5117 intel_de_write(dev_priv, reg,
5118 temp | FDI_RX_SYMBOL_LOCK);
5119 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5124 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5126 drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5130 static const int snb_b_fdi_train_param[] = {
5131 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5132 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5133 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5134 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5137 /* The FDI link training functions for SNB/Cougarpoint. */
5138 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5139 const struct intel_crtc_state *crtc_state)
5141 struct drm_device *dev = crtc->base.dev;
5142 struct drm_i915_private *dev_priv = to_i915(dev);
5143 enum pipe pipe = crtc->pipe;
5147 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5149 reg = FDI_RX_IMR(pipe);
5150 temp = intel_de_read(dev_priv, reg);
5151 temp &= ~FDI_RX_SYMBOL_LOCK;
5152 temp &= ~FDI_RX_BIT_LOCK;
5153 intel_de_write(dev_priv, reg, temp);
5155 intel_de_posting_read(dev_priv, reg);
5158 /* enable CPU FDI TX and PCH FDI RX */
5159 reg = FDI_TX_CTL(pipe);
5160 temp = intel_de_read(dev_priv, reg);
5161 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5162 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5163 temp &= ~FDI_LINK_TRAIN_NONE;
5164 temp |= FDI_LINK_TRAIN_PATTERN_1;
5165 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5167 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5168 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5170 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5171 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5173 reg = FDI_RX_CTL(pipe);
5174 temp = intel_de_read(dev_priv, reg);
5175 if (HAS_PCH_CPT(dev_priv)) {
5176 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5177 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5179 temp &= ~FDI_LINK_TRAIN_NONE;
5180 temp |= FDI_LINK_TRAIN_PATTERN_1;
5182 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5184 intel_de_posting_read(dev_priv, reg);
5187 for (i = 0; i < 4; i++) {
5188 reg = FDI_TX_CTL(pipe);
5189 temp = intel_de_read(dev_priv, reg);
5190 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5191 temp |= snb_b_fdi_train_param[i];
5192 intel_de_write(dev_priv, reg, temp);
5194 intel_de_posting_read(dev_priv, reg);
5197 for (retry = 0; retry < 5; retry++) {
5198 reg = FDI_RX_IIR(pipe);
5199 temp = intel_de_read(dev_priv, reg);
5200 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5201 if (temp & FDI_RX_BIT_LOCK) {
5202 intel_de_write(dev_priv, reg,
5203 temp | FDI_RX_BIT_LOCK);
5204 drm_dbg_kms(&dev_priv->drm,
5205 "FDI train 1 done.\n");
5214 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5217 reg = FDI_TX_CTL(pipe);
5218 temp = intel_de_read(dev_priv, reg);
5219 temp &= ~FDI_LINK_TRAIN_NONE;
5220 temp |= FDI_LINK_TRAIN_PATTERN_2;
5221 if (IS_GEN(dev_priv, 6)) {
5222 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5224 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5226 intel_de_write(dev_priv, reg, temp);
5228 reg = FDI_RX_CTL(pipe);
5229 temp = intel_de_read(dev_priv, reg);
5230 if (HAS_PCH_CPT(dev_priv)) {
5231 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5232 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5234 temp &= ~FDI_LINK_TRAIN_NONE;
5235 temp |= FDI_LINK_TRAIN_PATTERN_2;
5237 intel_de_write(dev_priv, reg, temp);
5239 intel_de_posting_read(dev_priv, reg);
5242 for (i = 0; i < 4; i++) {
5243 reg = FDI_TX_CTL(pipe);
5244 temp = intel_de_read(dev_priv, reg);
5245 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5246 temp |= snb_b_fdi_train_param[i];
5247 intel_de_write(dev_priv, reg, temp);
5249 intel_de_posting_read(dev_priv, reg);
5252 for (retry = 0; retry < 5; retry++) {
5253 reg = FDI_RX_IIR(pipe);
5254 temp = intel_de_read(dev_priv, reg);
5255 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5256 if (temp & FDI_RX_SYMBOL_LOCK) {
5257 intel_de_write(dev_priv, reg,
5258 temp | FDI_RX_SYMBOL_LOCK);
5259 drm_dbg_kms(&dev_priv->drm,
5260 "FDI train 2 done.\n");
5269 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5271 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5274 /* Manual link training for Ivy Bridge A0 parts */
5275 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5276 const struct intel_crtc_state *crtc_state)
5278 struct drm_device *dev = crtc->base.dev;
5279 struct drm_i915_private *dev_priv = to_i915(dev);
5280 enum pipe pipe = crtc->pipe;
5284 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5286 reg = FDI_RX_IMR(pipe);
5287 temp = intel_de_read(dev_priv, reg);
5288 temp &= ~FDI_RX_SYMBOL_LOCK;
5289 temp &= ~FDI_RX_BIT_LOCK;
5290 intel_de_write(dev_priv, reg, temp);
5292 intel_de_posting_read(dev_priv, reg);
5295 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5296 intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5298 /* Try each vswing and preemphasis setting twice before moving on */
5299 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5300 /* disable first in case we need to retry */
5301 reg = FDI_TX_CTL(pipe);
5302 temp = intel_de_read(dev_priv, reg);
5303 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5304 temp &= ~FDI_TX_ENABLE;
5305 intel_de_write(dev_priv, reg, temp);
5307 reg = FDI_RX_CTL(pipe);
5308 temp = intel_de_read(dev_priv, reg);
5309 temp &= ~FDI_LINK_TRAIN_AUTO;
5310 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5311 temp &= ~FDI_RX_ENABLE;
5312 intel_de_write(dev_priv, reg, temp);
5314 /* enable CPU FDI TX and PCH FDI RX */
5315 reg = FDI_TX_CTL(pipe);
5316 temp = intel_de_read(dev_priv, reg);
5317 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5318 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5319 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5320 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5321 temp |= snb_b_fdi_train_param[j/2];
5322 temp |= FDI_COMPOSITE_SYNC;
5323 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5325 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5326 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5328 reg = FDI_RX_CTL(pipe);
5329 temp = intel_de_read(dev_priv, reg);
5330 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5331 temp |= FDI_COMPOSITE_SYNC;
5332 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5334 intel_de_posting_read(dev_priv, reg);
5335 udelay(1); /* should be 0.5us */
5337 for (i = 0; i < 4; i++) {
5338 reg = FDI_RX_IIR(pipe);
5339 temp = intel_de_read(dev_priv, reg);
5340 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5342 if (temp & FDI_RX_BIT_LOCK ||
5343 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5344 intel_de_write(dev_priv, reg,
5345 temp | FDI_RX_BIT_LOCK);
5346 drm_dbg_kms(&dev_priv->drm,
5347 "FDI train 1 done, level %i.\n",
5351 udelay(1); /* should be 0.5us */
5354 drm_dbg_kms(&dev_priv->drm,
5355 "FDI train 1 fail on vswing %d\n", j / 2);
5360 reg = FDI_TX_CTL(pipe);
5361 temp = intel_de_read(dev_priv, reg);
5362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5363 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5364 intel_de_write(dev_priv, reg, temp);
5366 reg = FDI_RX_CTL(pipe);
5367 temp = intel_de_read(dev_priv, reg);
5368 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5369 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5370 intel_de_write(dev_priv, reg, temp);
5372 intel_de_posting_read(dev_priv, reg);
5373 udelay(2); /* should be 1.5us */
5375 for (i = 0; i < 4; i++) {
5376 reg = FDI_RX_IIR(pipe);
5377 temp = intel_de_read(dev_priv, reg);
5378 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5380 if (temp & FDI_RX_SYMBOL_LOCK ||
5381 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5382 intel_de_write(dev_priv, reg,
5383 temp | FDI_RX_SYMBOL_LOCK);
5384 drm_dbg_kms(&dev_priv->drm,
5385 "FDI train 2 done, level %i.\n",
5389 udelay(2); /* should be 1.5us */
5392 drm_dbg_kms(&dev_priv->drm,
5393 "FDI train 2 fail on vswing %d\n", j / 2);
5397 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5400 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5403 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5404 enum pipe pipe = intel_crtc->pipe;
5408 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5409 reg = FDI_RX_CTL(pipe);
5410 temp = intel_de_read(dev_priv, reg);
5411 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5412 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5413 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5414 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5416 intel_de_posting_read(dev_priv, reg);
5419 /* Switch from Rawclk to PCDclk */
5420 temp = intel_de_read(dev_priv, reg);
5421 intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5423 intel_de_posting_read(dev_priv, reg);
5426 /* Enable CPU FDI TX PLL, always on for Ironlake */
5427 reg = FDI_TX_CTL(pipe);
5428 temp = intel_de_read(dev_priv, reg);
5429 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5430 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5432 intel_de_posting_read(dev_priv, reg);
5437 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5439 struct drm_device *dev = intel_crtc->base.dev;
5440 struct drm_i915_private *dev_priv = to_i915(dev);
5441 enum pipe pipe = intel_crtc->pipe;
5445 /* Switch from PCDclk to Rawclk */
5446 reg = FDI_RX_CTL(pipe);
5447 temp = intel_de_read(dev_priv, reg);
5448 intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5450 /* Disable CPU FDI TX PLL */
5451 reg = FDI_TX_CTL(pipe);
5452 temp = intel_de_read(dev_priv, reg);
5453 intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5455 intel_de_posting_read(dev_priv, reg);
5458 reg = FDI_RX_CTL(pipe);
5459 temp = intel_de_read(dev_priv, reg);
5460 intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5462 /* Wait for the clocks to turn off. */
5463 intel_de_posting_read(dev_priv, reg);
5467 static void ilk_fdi_disable(struct intel_crtc *crtc)
5469 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5470 enum pipe pipe = crtc->pipe;
5474 /* disable CPU FDI tx and PCH FDI rx */
5475 reg = FDI_TX_CTL(pipe);
5476 temp = intel_de_read(dev_priv, reg);
5477 intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5478 intel_de_posting_read(dev_priv, reg);
5480 reg = FDI_RX_CTL(pipe);
5481 temp = intel_de_read(dev_priv, reg);
5482 temp &= ~(0x7 << 16);
5483 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5484 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5486 intel_de_posting_read(dev_priv, reg);
5489 /* Ironlake workaround, disable clock pointer after downing FDI */
5490 if (HAS_PCH_IBX(dev_priv))
5491 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5492 FDI_RX_PHASE_SYNC_POINTER_OVR);
5494 /* still set train pattern 1 */
5495 reg = FDI_TX_CTL(pipe);
5496 temp = intel_de_read(dev_priv, reg);
5497 temp &= ~FDI_LINK_TRAIN_NONE;
5498 temp |= FDI_LINK_TRAIN_PATTERN_1;
5499 intel_de_write(dev_priv, reg, temp);
5501 reg = FDI_RX_CTL(pipe);
5502 temp = intel_de_read(dev_priv, reg);
5503 if (HAS_PCH_CPT(dev_priv)) {
5504 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5505 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5507 temp &= ~FDI_LINK_TRAIN_NONE;
5508 temp |= FDI_LINK_TRAIN_PATTERN_1;
5510 /* BPC in FDI rx is consistent with that in PIPECONF */
5511 temp &= ~(0x07 << 16);
5512 temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5513 intel_de_write(dev_priv, reg, temp);
5515 intel_de_posting_read(dev_priv, reg);
5519 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5521 struct drm_crtc *crtc;
5524 drm_for_each_crtc(crtc, &dev_priv->drm) {
5525 struct drm_crtc_commit *commit;
5526 spin_lock(&crtc->commit_lock);
5527 commit = list_first_entry_or_null(&crtc->commit_list,
5528 struct drm_crtc_commit, commit_entry);
5529 cleanup_done = commit ?
5530 try_wait_for_completion(&commit->cleanup_done) : true;
5531 spin_unlock(&crtc->commit_lock);
5536 drm_crtc_wait_one_vblank(crtc);
5544 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5548 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5550 mutex_lock(&dev_priv->sb_lock);
5552 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5553 temp |= SBI_SSCCTL_DISABLE;
5554 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5556 mutex_unlock(&dev_priv->sb_lock);
5559 /* Program iCLKIP clock to the desired frequency */
5560 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5562 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5563 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5564 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5565 u32 divsel, phaseinc, auxdiv, phasedir = 0;
5568 lpt_disable_iclkip(dev_priv);
5570 /* The iCLK virtual clock root frequency is in MHz,
5571 * but the adjusted_mode->crtc_clock in in KHz. To get the
5572 * divisors, it is necessary to divide one by another, so we
5573 * convert the virtual clock precision to KHz here for higher
5576 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5577 u32 iclk_virtual_root_freq = 172800 * 1000;
5578 u32 iclk_pi_range = 64;
5579 u32 desired_divisor;
5581 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5583 divsel = (desired_divisor / iclk_pi_range) - 2;
5584 phaseinc = desired_divisor % iclk_pi_range;
5587 * Near 20MHz is a corner case which is
5588 * out of range for the 7-bit divisor
5594 /* This should not happen with any sane values */
5595 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5596 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5597 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5598 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5600 drm_dbg_kms(&dev_priv->drm,
5601 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5602 clock, auxdiv, divsel, phasedir, phaseinc);
5604 mutex_lock(&dev_priv->sb_lock);
5606 /* Program SSCDIVINTPHASE6 */
5607 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5608 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5609 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5610 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5611 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5612 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5613 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5614 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5616 /* Program SSCAUXDIV */
5617 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5618 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5619 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5620 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5622 /* Enable modulator and associated divider */
5623 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5624 temp &= ~SBI_SSCCTL_DISABLE;
5625 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5627 mutex_unlock(&dev_priv->sb_lock);
5629 /* Wait for initialization time */
5632 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5635 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5637 u32 divsel, phaseinc, auxdiv;
5638 u32 iclk_virtual_root_freq = 172800 * 1000;
5639 u32 iclk_pi_range = 64;
5640 u32 desired_divisor;
5643 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5646 mutex_lock(&dev_priv->sb_lock);
5648 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5649 if (temp & SBI_SSCCTL_DISABLE) {
5650 mutex_unlock(&dev_priv->sb_lock);
5654 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5655 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5656 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5657 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5658 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5660 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5661 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5662 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5664 mutex_unlock(&dev_priv->sb_lock);
5666 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5668 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5669 desired_divisor << auxdiv);
5672 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5673 enum pipe pch_transcoder)
5675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5676 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5677 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5679 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5680 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5681 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5682 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5683 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5684 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5686 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5687 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5688 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5689 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5690 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5691 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5692 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5693 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5696 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5700 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5701 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5704 drm_WARN_ON(&dev_priv->drm,
5705 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5707 drm_WARN_ON(&dev_priv->drm,
5708 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5711 temp &= ~FDI_BC_BIFURCATION_SELECT;
5713 temp |= FDI_BC_BIFURCATION_SELECT;
5715 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5716 enable ? "en" : "dis");
5717 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5718 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5721 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5723 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5724 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5726 switch (crtc->pipe) {
5730 if (crtc_state->fdi_lanes > 2)
5731 cpt_set_fdi_bc_bifurcation(dev_priv, false);
5733 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5737 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5746 * Finds the encoder associated with the given CRTC. This can only be
5747 * used when we know that the CRTC isn't feeding multiple encoders!
5749 static struct intel_encoder *
5750 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5751 const struct intel_crtc_state *crtc_state)
5753 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5754 const struct drm_connector_state *connector_state;
5755 const struct drm_connector *connector;
5756 struct intel_encoder *encoder = NULL;
5757 int num_encoders = 0;
5760 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5761 if (connector_state->crtc != &crtc->base)
5764 encoder = to_intel_encoder(connector_state->best_encoder);
5768 drm_WARN(encoder->base.dev, num_encoders != 1,
5769 "%d encoders for pipe %c\n",
5770 num_encoders, pipe_name(crtc->pipe));
5776 * Enable PCH resources required for PCH ports:
5778 * - FDI training & RX/TX
5779 * - update transcoder timings
5780 * - DP transcoding bits
5783 static void ilk_pch_enable(const struct intel_atomic_state *state,
5784 const struct intel_crtc_state *crtc_state)
5786 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5787 struct drm_device *dev = crtc->base.dev;
5788 struct drm_i915_private *dev_priv = to_i915(dev);
5789 enum pipe pipe = crtc->pipe;
5792 assert_pch_transcoder_disabled(dev_priv, pipe);
5794 if (IS_IVYBRIDGE(dev_priv))
5795 ivb_update_fdi_bc_bifurcation(crtc_state);
5797 /* Write the TU size bits before fdi link training, so that error
5798 * detection works. */
5799 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5800 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5802 /* For PCH output, training FDI link */
5803 dev_priv->display.fdi_link_train(crtc, crtc_state);
5805 /* We need to program the right clock selection before writing the pixel
5806 * mutliplier into the DPLL. */
5807 if (HAS_PCH_CPT(dev_priv)) {
5810 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5811 temp |= TRANS_DPLL_ENABLE(pipe);
5812 sel = TRANS_DPLLB_SEL(pipe);
5813 if (crtc_state->shared_dpll ==
5814 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5818 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5821 /* XXX: pch pll's can be enabled any time before we enable the PCH
5822 * transcoder, and we actually should do this to not upset any PCH
5823 * transcoder that already use the clock when we share it.
5825 * Note that enable_shared_dpll tries to do the right thing, but
5826 * get_shared_dpll unconditionally resets the pll - we need that to have
5827 * the right LVDS enable sequence. */
5828 intel_enable_shared_dpll(crtc_state);
5830 /* set transcoder timing, panel must allow it */
5831 assert_panel_unlocked(dev_priv, pipe);
5832 ilk_pch_transcoder_set_timings(crtc_state, pipe);
5834 intel_fdi_normal_train(crtc);
5836 /* For PCH DP, enable TRANS_DP_CTL */
5837 if (HAS_PCH_CPT(dev_priv) &&
5838 intel_crtc_has_dp_encoder(crtc_state)) {
5839 const struct drm_display_mode *adjusted_mode =
5840 &crtc_state->hw.adjusted_mode;
5841 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5842 i915_reg_t reg = TRANS_DP_CTL(pipe);
5845 temp = intel_de_read(dev_priv, reg);
5846 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5847 TRANS_DP_SYNC_MASK |
5849 temp |= TRANS_DP_OUTPUT_ENABLE;
5850 temp |= bpc << 9; /* same format but at 11:9 */
5852 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5853 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5854 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5855 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5857 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5858 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5859 temp |= TRANS_DP_PORT_SEL(port);
5861 intel_de_write(dev_priv, reg, temp);
5864 ilk_enable_pch_transcoder(crtc_state);
5867 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5869 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5871 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5873 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5875 lpt_program_iclkip(crtc_state);
5877 /* Set transcoder timing. */
5878 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5880 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5883 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5886 i915_reg_t dslreg = PIPEDSL(pipe);
5889 temp = intel_de_read(dev_priv, dslreg);
5891 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5892 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5893 drm_err(&dev_priv->drm,
5894 "mode set failed: pipe %c stuck\n",
5900 * The hardware phase 0.0 refers to the center of the pixel.
5901 * We want to start from the top/left edge which is phase
5902 * -0.5. That matches how the hardware calculates the scaling
5903 * factors (from top-left of the first pixel to bottom-right
5904 * of the last pixel, as opposed to the pixel centers).
5906 * For 4:2:0 subsampled chroma planes we obviously have to
5907 * adjust that so that the chroma sample position lands in
5910 * Note that for packed YCbCr 4:2:2 formats there is no way to
5911 * control chroma siting. The hardware simply replicates the
5912 * chroma samples for both of the luma samples, and thus we don't
5913 * actually get the expected MPEG2 chroma siting convention :(
5914 * The same behaviour is observed on pre-SKL platforms as well.
5916 * Theory behind the formula (note that we ignore sub-pixel
5917 * source coordinates):
5918 * s = source sample position
5919 * d = destination sample position
5924 * | | 1.5 (initial phase)
5932 * | -0.375 (initial phase)
5939 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5941 int phase = -0x8000;
5945 phase += (sub - 1) * 0x8000 / sub;
5947 phase += scale / (2 * sub);
5950 * Hardware initial phase limited to [-0.5:1.5].
5951 * Since the max hardware scale factor is 3.0, we
5952 * should never actually excdeed 1.0 here.
5954 WARN_ON(phase < -0x8000 || phase > 0x18000);
5957 phase = 0x10000 + phase;
5959 trip = PS_PHASE_TRIP;
5961 return ((phase >> 2) & PS_PHASE_MASK) | trip;
5964 #define SKL_MIN_SRC_W 8
5965 #define SKL_MAX_SRC_W 4096
5966 #define SKL_MIN_SRC_H 8
5967 #define SKL_MAX_SRC_H 4096
5968 #define SKL_MIN_DST_W 8
5969 #define SKL_MAX_DST_W 4096
5970 #define SKL_MIN_DST_H 8
5971 #define SKL_MAX_DST_H 4096
5972 #define ICL_MAX_SRC_W 5120
5973 #define ICL_MAX_SRC_H 4096
5974 #define ICL_MAX_DST_W 5120
5975 #define ICL_MAX_DST_H 4096
5976 #define SKL_MIN_YUV_420_SRC_W 16
5977 #define SKL_MIN_YUV_420_SRC_H 16
5980 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
5981 unsigned int scaler_user, int *scaler_id,
5982 int src_w, int src_h, int dst_w, int dst_h,
5983 const struct drm_format_info *format,
5984 u64 modifier, bool need_scaler)
5986 struct intel_crtc_scaler_state *scaler_state =
5987 &crtc_state->scaler_state;
5988 struct intel_crtc *intel_crtc =
5989 to_intel_crtc(crtc_state->uapi.crtc);
5990 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5991 const struct drm_display_mode *adjusted_mode =
5992 &crtc_state->hw.adjusted_mode;
5995 * Src coordinates are already rotated by 270 degrees for
5996 * the 90/270 degree plane rotation cases (to match the
5997 * GTT mapping), hence no need to account for rotation here.
5999 if (src_w != dst_w || src_h != dst_h)
6003 * Scaling/fitting not supported in IF-ID mode in GEN9+
6004 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6005 * Once NV12 is enabled, handle it here while allocating scaler
6008 if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6009 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6010 drm_dbg_kms(&dev_priv->drm,
6011 "Pipe/Plane scaling not supported with IF-ID mode\n");
6016 * if plane is being disabled or scaler is no more required or force detach
6017 * - free scaler binded to this plane/crtc
6018 * - in order to do this, update crtc->scaler_usage
6020 * Here scaler state in crtc_state is set free so that
6021 * scaler can be assigned to other user. Actual register
6022 * update to free the scaler is done in plane/panel-fit programming.
6023 * For this purpose crtc/plane_state->scaler_id isn't reset here.
6025 if (force_detach || !need_scaler) {
6026 if (*scaler_id >= 0) {
6027 scaler_state->scaler_users &= ~(1 << scaler_user);
6028 scaler_state->scalers[*scaler_id].in_use = 0;
6030 drm_dbg_kms(&dev_priv->drm,
6031 "scaler_user index %u.%u: "
6032 "Staged freeing scaler id %d scaler_users = 0x%x\n",
6033 intel_crtc->pipe, scaler_user, *scaler_id,
6034 scaler_state->scaler_users);
6040 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6041 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6042 drm_dbg_kms(&dev_priv->drm,
6043 "Planar YUV: src dimensions not met\n");
6048 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6049 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6050 (INTEL_GEN(dev_priv) >= 11 &&
6051 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6052 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6053 (INTEL_GEN(dev_priv) < 11 &&
6054 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6055 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6056 drm_dbg_kms(&dev_priv->drm,
6057 "scaler_user index %u.%u: src %ux%u dst %ux%u "
6058 "size is out of scaler range\n",
6059 intel_crtc->pipe, scaler_user, src_w, src_h,
6064 /* mark this plane as a scaler user in crtc_state */
6065 scaler_state->scaler_users |= (1 << scaler_user);
6066 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6067 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6068 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6069 scaler_state->scaler_users);
6074 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
6076 const struct drm_display_mode *adjusted_mode =
6077 &crtc_state->hw.adjusted_mode;
6080 if (crtc_state->pch_pfit.enabled) {
6081 width = drm_rect_width(&crtc_state->pch_pfit.dst);
6082 height = drm_rect_height(&crtc_state->pch_pfit.dst);
6084 width = adjusted_mode->crtc_hdisplay;
6085 height = adjusted_mode->crtc_vdisplay;
6088 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
6090 &crtc_state->scaler_state.scaler_id,
6091 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
6092 width, height, NULL, 0,
6093 crtc_state->pch_pfit.enabled);
6097 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6098 * @crtc_state: crtc's scaler state
6099 * @plane_state: atomic plane state to update
6102 * 0 - scaler_usage updated successfully
6103 * error - requested scaling cannot be supported or other error condition
6105 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6106 struct intel_plane_state *plane_state)
6108 struct intel_plane *intel_plane =
6109 to_intel_plane(plane_state->uapi.plane);
6110 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6111 struct drm_framebuffer *fb = plane_state->hw.fb;
6113 bool force_detach = !fb || !plane_state->uapi.visible;
6114 bool need_scaler = false;
6116 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6117 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6118 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6121 ret = skl_update_scaler(crtc_state, force_detach,
6122 drm_plane_index(&intel_plane->base),
6123 &plane_state->scaler_id,
6124 drm_rect_width(&plane_state->uapi.src) >> 16,
6125 drm_rect_height(&plane_state->uapi.src) >> 16,
6126 drm_rect_width(&plane_state->uapi.dst),
6127 drm_rect_height(&plane_state->uapi.dst),
6128 fb ? fb->format : NULL,
6129 fb ? fb->modifier : 0,
6132 if (ret || plane_state->scaler_id < 0)
6135 /* check colorkey */
6136 if (plane_state->ckey.flags) {
6137 drm_dbg_kms(&dev_priv->drm,
6138 "[PLANE:%d:%s] scaling with color key not allowed",
6139 intel_plane->base.base.id,
6140 intel_plane->base.name);
6144 /* Check src format */
6145 switch (fb->format->format) {
6146 case DRM_FORMAT_RGB565:
6147 case DRM_FORMAT_XBGR8888:
6148 case DRM_FORMAT_XRGB8888:
6149 case DRM_FORMAT_ABGR8888:
6150 case DRM_FORMAT_ARGB8888:
6151 case DRM_FORMAT_XRGB2101010:
6152 case DRM_FORMAT_XBGR2101010:
6153 case DRM_FORMAT_ARGB2101010:
6154 case DRM_FORMAT_ABGR2101010:
6155 case DRM_FORMAT_YUYV:
6156 case DRM_FORMAT_YVYU:
6157 case DRM_FORMAT_UYVY:
6158 case DRM_FORMAT_VYUY:
6159 case DRM_FORMAT_NV12:
6160 case DRM_FORMAT_XYUV8888:
6161 case DRM_FORMAT_P010:
6162 case DRM_FORMAT_P012:
6163 case DRM_FORMAT_P016:
6164 case DRM_FORMAT_Y210:
6165 case DRM_FORMAT_Y212:
6166 case DRM_FORMAT_Y216:
6167 case DRM_FORMAT_XVYU2101010:
6168 case DRM_FORMAT_XVYU12_16161616:
6169 case DRM_FORMAT_XVYU16161616:
6171 case DRM_FORMAT_XBGR16161616F:
6172 case DRM_FORMAT_ABGR16161616F:
6173 case DRM_FORMAT_XRGB16161616F:
6174 case DRM_FORMAT_ARGB16161616F:
6175 if (INTEL_GEN(dev_priv) >= 11)
6179 drm_dbg_kms(&dev_priv->drm,
6180 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6181 intel_plane->base.base.id, intel_plane->base.name,
6182 fb->base.id, fb->format->format);
6189 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6191 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6194 for (i = 0; i < crtc->num_scalers; i++)
6195 skl_detach_scaler(crtc, i);
6198 static int cnl_coef_tap(int i)
6203 static u16 cnl_nearest_filter_coef(int t)
6205 return t == 3 ? 0x0800 : 0x3000;
6209 * Theory behind setting nearest-neighbor integer scaling:
6211 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
6212 * The letter represents the filter tap (D is the center tap) and the number
6213 * represents the coefficient set for a phase (0-16).
6215 * +------------+------------------------+------------------------+
6216 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
6217 * +------------+------------------------+------------------------+
6219 * +------------+------------------------+------------------------+
6221 * +------------+------------------------+------------------------+
6223 * +------------+------------------------+------------------------+
6225 * +------------+------------------------+------------------------+
6227 * +------------+------------------------+------------------------+
6228 * | ... | ... | ... |
6229 * +------------+------------------------+------------------------+
6230 * | 38h | B16 | A16 |
6231 * +------------+------------------------+------------------------+
6232 * | 39h | D16 | C16 |
6233 * +------------+------------------------+------------------------+
6234 * | 3Ah | F16 | C16 |
6235 * +------------+------------------------+------------------------+
6236 * | 3Bh | Reserved | G16 |
6237 * +------------+------------------------+------------------------+
6239 * To enable nearest-neighbor scaling: program scaler coefficents with
6240 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
6241 * SCALER_COEFFICIENT_FORMAT
6245 static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
6246 enum pipe pipe, int id, int set)
6250 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
6251 PS_COEE_INDEX_AUTO_INC);
6253 for (i = 0; i < 17 * 7; i += 2) {
6257 t = cnl_coef_tap(i);
6258 tmp = cnl_nearest_filter_coef(t);
6260 t = cnl_coef_tap(i + 1);
6261 tmp |= cnl_nearest_filter_coef(t) << 16;
6263 intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
6267 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
6270 inline u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
6272 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
6273 return (PS_FILTER_PROGRAMMED |
6274 PS_Y_VERT_FILTER_SELECT(set) |
6275 PS_Y_HORZ_FILTER_SELECT(set) |
6276 PS_UV_VERT_FILTER_SELECT(set) |
6277 PS_UV_HORZ_FILTER_SELECT(set));
6280 return PS_FILTER_MEDIUM;
6283 void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
6284 int id, int set, enum drm_scaling_filter filter)
6287 case DRM_SCALING_FILTER_DEFAULT:
6289 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
6290 cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
6293 MISSING_CASE(filter);
6297 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6299 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6300 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6301 const struct intel_crtc_scaler_state *scaler_state =
6302 &crtc_state->scaler_state;
6303 struct drm_rect src = {
6304 .x2 = crtc_state->pipe_src_w << 16,
6305 .y2 = crtc_state->pipe_src_h << 16,
6307 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6308 u16 uv_rgb_hphase, uv_rgb_vphase;
6309 enum pipe pipe = crtc->pipe;
6310 int width = drm_rect_width(dst);
6311 int height = drm_rect_height(dst);
6315 unsigned long irqflags;
6319 if (!crtc_state->pch_pfit.enabled)
6322 if (drm_WARN_ON(&dev_priv->drm,
6323 crtc_state->scaler_state.scaler_id < 0))
6326 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
6327 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
6329 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6330 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6332 id = scaler_state->scaler_id;
6334 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
6335 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
6337 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6339 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
6340 crtc_state->hw.scaling_filter);
6342 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
6344 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6345 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6346 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6347 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6348 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6350 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6351 width << 16 | height);
6353 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6356 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6360 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
6361 enum pipe pipe = crtc->pipe;
6362 int width = drm_rect_width(dst);
6363 int height = drm_rect_height(dst);
6367 if (!crtc_state->pch_pfit.enabled)
6370 /* Force use of hard-coded filter coefficients
6371 * as some pre-programmed values are broken,
6374 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6375 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6376 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6378 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
6380 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
6381 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
6384 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6386 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6387 struct drm_device *dev = crtc->base.dev;
6388 struct drm_i915_private *dev_priv = to_i915(dev);
6390 if (!crtc_state->ips_enabled)
6394 * We can only enable IPS after we enable a plane and wait for a vblank
6395 * This function is called from post_plane_update, which is run after
6398 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6400 if (IS_BROADWELL(dev_priv)) {
6401 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6402 IPS_ENABLE | IPS_PCODE_CONTROL));
6403 /* Quoting Art Runyan: "its not safe to expect any particular
6404 * value in IPS_CTL bit 31 after enabling IPS through the
6405 * mailbox." Moreover, the mailbox may return a bogus state,
6406 * so we need to just enable it and continue on.
6409 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6410 /* The bit only becomes 1 in the next vblank, so this wait here
6411 * is essentially intel_wait_for_vblank. If we don't have this
6412 * and don't wait for vblanks until the end of crtc_enable, then
6413 * the HW state readout code will complain that the expected
6414 * IPS_CTL value is not the one we read. */
6415 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6416 drm_err(&dev_priv->drm,
6417 "Timed out waiting for IPS enable\n");
6421 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6423 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6424 struct drm_device *dev = crtc->base.dev;
6425 struct drm_i915_private *dev_priv = to_i915(dev);
6427 if (!crtc_state->ips_enabled)
6430 if (IS_BROADWELL(dev_priv)) {
6432 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6434 * Wait for PCODE to finish disabling IPS. The BSpec specified
6435 * 42ms timeout value leads to occasional timeouts so use 100ms
6438 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6439 drm_err(&dev_priv->drm,
6440 "Timed out waiting for IPS disable\n");
6442 intel_de_write(dev_priv, IPS_CTL, 0);
6443 intel_de_posting_read(dev_priv, IPS_CTL);
6446 /* We need to wait for a vblank before we can disable the plane. */
6447 intel_wait_for_vblank(dev_priv, crtc->pipe);
6450 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6452 if (intel_crtc->overlay)
6453 (void) intel_overlay_switch_off(intel_crtc->overlay);
6455 /* Let userspace switch the overlay on again. In most cases userspace
6456 * has to recompute where to put it anyway.
6460 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6461 const struct intel_crtc_state *new_crtc_state)
6463 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6464 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6466 if (!old_crtc_state->ips_enabled)
6469 if (needs_modeset(new_crtc_state))
6473 * Workaround : Do not read or write the pipe palette/gamma data while
6474 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6476 * Disable IPS before we program the LUT.
6478 if (IS_HASWELL(dev_priv) &&
6479 (new_crtc_state->uapi.color_mgmt_changed ||
6480 new_crtc_state->update_pipe) &&
6481 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6484 return !new_crtc_state->ips_enabled;
6487 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6488 const struct intel_crtc_state *new_crtc_state)
6490 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6491 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6493 if (!new_crtc_state->ips_enabled)
6496 if (needs_modeset(new_crtc_state))
6500 * Workaround : Do not read or write the pipe palette/gamma data while
6501 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6503 * Re-enable IPS after the LUT has been programmed.
6505 if (IS_HASWELL(dev_priv) &&
6506 (new_crtc_state->uapi.color_mgmt_changed ||
6507 new_crtc_state->update_pipe) &&
6508 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6512 * We can't read out IPS on broadwell, assume the worst and
6513 * forcibly enable IPS on the first fastset.
6515 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
6518 return !old_crtc_state->ips_enabled;
6521 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6523 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6525 if (!crtc_state->nv12_planes)
6528 /* WA Display #0827: Gen9:all */
6529 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6535 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6537 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6539 /* Wa_2006604312:icl,ehl */
6540 if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11))
6546 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6547 const struct intel_crtc_state *new_crtc_state)
6549 return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6550 new_crtc_state->active_planes;
6553 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6554 const struct intel_crtc_state *new_crtc_state)
6556 return old_crtc_state->active_planes &&
6557 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6560 static void intel_post_plane_update(struct intel_atomic_state *state,
6561 struct intel_crtc *crtc)
6563 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6564 const struct intel_crtc_state *old_crtc_state =
6565 intel_atomic_get_old_crtc_state(state, crtc);
6566 const struct intel_crtc_state *new_crtc_state =
6567 intel_atomic_get_new_crtc_state(state, crtc);
6568 enum pipe pipe = crtc->pipe;
6570 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6572 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6573 intel_update_watermarks(crtc);
6575 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6576 hsw_enable_ips(new_crtc_state);
6578 intel_fbc_post_update(state, crtc);
6580 if (needs_nv12_wa(old_crtc_state) &&
6581 !needs_nv12_wa(new_crtc_state))
6582 skl_wa_827(dev_priv, pipe, false);
6584 if (needs_scalerclk_wa(old_crtc_state) &&
6585 !needs_scalerclk_wa(new_crtc_state))
6586 icl_wa_scalerclkgating(dev_priv, pipe, false);
6589 static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
6590 struct intel_crtc *crtc,
6591 const struct intel_crtc_state *new_crtc_state)
6593 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6594 struct intel_plane *plane;
6595 struct intel_plane_state *new_plane_state;
6598 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
6599 u32 update_mask = new_crtc_state->update_planes;
6600 u32 plane_ctl, surf_addr;
6601 enum plane_id plane_id;
6602 unsigned long irqflags;
6605 if (crtc->pipe != plane->pipe ||
6606 !(update_mask & BIT(plane->id)))
6609 plane_id = plane->id;
6612 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6613 plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
6614 surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
6616 plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
6618 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
6619 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
6620 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6623 intel_wait_for_vblank(dev_priv, crtc->pipe);
6626 static void intel_pre_plane_update(struct intel_atomic_state *state,
6627 struct intel_crtc *crtc)
6629 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6630 const struct intel_crtc_state *old_crtc_state =
6631 intel_atomic_get_old_crtc_state(state, crtc);
6632 const struct intel_crtc_state *new_crtc_state =
6633 intel_atomic_get_new_crtc_state(state, crtc);
6634 enum pipe pipe = crtc->pipe;
6636 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6637 hsw_disable_ips(old_crtc_state);
6639 if (intel_fbc_pre_update(state, crtc))
6640 intel_wait_for_vblank(dev_priv, pipe);
6642 /* Display WA 827 */
6643 if (!needs_nv12_wa(old_crtc_state) &&
6644 needs_nv12_wa(new_crtc_state))
6645 skl_wa_827(dev_priv, pipe, true);
6647 /* Wa_2006604312:icl,ehl */
6648 if (!needs_scalerclk_wa(old_crtc_state) &&
6649 needs_scalerclk_wa(new_crtc_state))
6650 icl_wa_scalerclkgating(dev_priv, pipe, true);
6653 * Vblank time updates from the shadow to live plane control register
6654 * are blocked if the memory self-refresh mode is active at that
6655 * moment. So to make sure the plane gets truly disabled, disable
6656 * first the self-refresh mode. The self-refresh enable bit in turn
6657 * will be checked/applied by the HW only at the next frame start
6658 * event which is after the vblank start event, so we need to have a
6659 * wait-for-vblank between disabling the plane and the pipe.
6661 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6662 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6663 intel_wait_for_vblank(dev_priv, pipe);
6666 * IVB workaround: must disable low power watermarks for at least
6667 * one frame before enabling scaling. LP watermarks can be re-enabled
6668 * when scaling is disabled.
6670 * WaCxSRDisabledForSpriteScaling:ivb
6672 if (old_crtc_state->hw.active &&
6673 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6674 intel_wait_for_vblank(dev_priv, pipe);
6677 * If we're doing a modeset we don't need to do any
6678 * pre-vblank watermark programming here.
6680 if (!needs_modeset(new_crtc_state)) {
6682 * For platforms that support atomic watermarks, program the
6683 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
6684 * will be the intermediate values that are safe for both pre- and
6685 * post- vblank; when vblank happens, the 'active' values will be set
6686 * to the final 'target' values and we'll do this again to get the
6687 * optimal watermarks. For gen9+ platforms, the values we program here
6688 * will be the final target values which will get automatically latched
6689 * at vblank time; no further programming will be necessary.
6691 * If a platform hasn't been transitioned to atomic watermarks yet,
6692 * we'll continue to update watermarks the old way, if flags tell
6695 if (dev_priv->display.initial_watermarks)
6696 dev_priv->display.initial_watermarks(state, crtc);
6697 else if (new_crtc_state->update_wm_pre)
6698 intel_update_watermarks(crtc);
6702 * Gen2 reports pipe underruns whenever all planes are disabled.
6703 * So disable underrun reporting before all the planes get disabled.
6705 * We do this after .initial_watermarks() so that we have a
6706 * chance of catching underruns with the intermediate watermarks
6707 * vs. the old plane configuration.
6709 if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6710 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6713 * WA for platforms where async address update enable bit
6714 * is double buffered and only latched at start of vblank.
6716 if (old_crtc_state->uapi.async_flip &&
6717 !new_crtc_state->uapi.async_flip &&
6718 IS_GEN_RANGE(dev_priv, 9, 10))
6719 skl_disable_async_flip_wa(state, crtc, new_crtc_state);
6722 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6723 struct intel_crtc *crtc)
6725 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6726 const struct intel_crtc_state *new_crtc_state =
6727 intel_atomic_get_new_crtc_state(state, crtc);
6728 unsigned int update_mask = new_crtc_state->update_planes;
6729 const struct intel_plane_state *old_plane_state;
6730 struct intel_plane *plane;
6731 unsigned fb_bits = 0;
6734 intel_crtc_dpms_overlay_disable(crtc);
6736 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6737 if (crtc->pipe != plane->pipe ||
6738 !(update_mask & BIT(plane->id)))
6741 intel_disable_plane(plane, new_crtc_state);
6743 if (old_plane_state->uapi.visible)
6744 fb_bits |= plane->frontbuffer_bit;
6747 intel_frontbuffer_flip(dev_priv, fb_bits);
6751 * intel_connector_primary_encoder - get the primary encoder for a connector
6752 * @connector: connector for which to return the encoder
6754 * Returns the primary encoder for a connector. There is a 1:1 mapping from
6755 * all connectors to their encoder, except for DP-MST connectors which have
6756 * both a virtual and a primary encoder. These DP-MST primary encoders can be
6757 * pointed to by as many DP-MST connectors as there are pipes.
6759 static struct intel_encoder *
6760 intel_connector_primary_encoder(struct intel_connector *connector)
6762 struct intel_encoder *encoder;
6764 if (connector->mst_port)
6765 return &dp_to_dig_port(connector->mst_port)->base;
6767 encoder = intel_attached_encoder(connector);
6768 drm_WARN_ON(connector->base.dev, !encoder);
6773 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6775 struct drm_connector_state *new_conn_state;
6776 struct drm_connector *connector;
6779 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6781 struct intel_connector *intel_connector;
6782 struct intel_encoder *encoder;
6783 struct intel_crtc *crtc;
6785 if (!intel_connector_needs_modeset(state, connector))
6788 intel_connector = to_intel_connector(connector);
6789 encoder = intel_connector_primary_encoder(intel_connector);
6790 if (!encoder->update_prepare)
6793 crtc = new_conn_state->crtc ?
6794 to_intel_crtc(new_conn_state->crtc) : NULL;
6795 encoder->update_prepare(state, encoder, crtc);
6799 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6801 struct drm_connector_state *new_conn_state;
6802 struct drm_connector *connector;
6805 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6807 struct intel_connector *intel_connector;
6808 struct intel_encoder *encoder;
6809 struct intel_crtc *crtc;
6811 if (!intel_connector_needs_modeset(state, connector))
6814 intel_connector = to_intel_connector(connector);
6815 encoder = intel_connector_primary_encoder(intel_connector);
6816 if (!encoder->update_complete)
6819 crtc = new_conn_state->crtc ?
6820 to_intel_crtc(new_conn_state->crtc) : NULL;
6821 encoder->update_complete(state, encoder, crtc);
6825 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6826 struct intel_crtc *crtc)
6828 const struct intel_crtc_state *crtc_state =
6829 intel_atomic_get_new_crtc_state(state, crtc);
6830 const struct drm_connector_state *conn_state;
6831 struct drm_connector *conn;
6834 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6835 struct intel_encoder *encoder =
6836 to_intel_encoder(conn_state->best_encoder);
6838 if (conn_state->crtc != &crtc->base)
6841 if (encoder->pre_pll_enable)
6842 encoder->pre_pll_enable(state, encoder,
6843 crtc_state, conn_state);
6847 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6848 struct intel_crtc *crtc)
6850 const struct intel_crtc_state *crtc_state =
6851 intel_atomic_get_new_crtc_state(state, crtc);
6852 const struct drm_connector_state *conn_state;
6853 struct drm_connector *conn;
6856 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6857 struct intel_encoder *encoder =
6858 to_intel_encoder(conn_state->best_encoder);
6860 if (conn_state->crtc != &crtc->base)
6863 if (encoder->pre_enable)
6864 encoder->pre_enable(state, encoder,
6865 crtc_state, conn_state);
6869 static void intel_encoders_enable(struct intel_atomic_state *state,
6870 struct intel_crtc *crtc)
6872 const struct intel_crtc_state *crtc_state =
6873 intel_atomic_get_new_crtc_state(state, crtc);
6874 const struct drm_connector_state *conn_state;
6875 struct drm_connector *conn;
6878 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6879 struct intel_encoder *encoder =
6880 to_intel_encoder(conn_state->best_encoder);
6882 if (conn_state->crtc != &crtc->base)
6885 if (encoder->enable)
6886 encoder->enable(state, encoder,
6887 crtc_state, conn_state);
6888 intel_opregion_notify_encoder(encoder, true);
6892 static void intel_encoders_disable(struct intel_atomic_state *state,
6893 struct intel_crtc *crtc)
6895 const struct intel_crtc_state *old_crtc_state =
6896 intel_atomic_get_old_crtc_state(state, crtc);
6897 const struct drm_connector_state *old_conn_state;
6898 struct drm_connector *conn;
6901 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6902 struct intel_encoder *encoder =
6903 to_intel_encoder(old_conn_state->best_encoder);
6905 if (old_conn_state->crtc != &crtc->base)
6908 intel_opregion_notify_encoder(encoder, false);
6909 if (encoder->disable)
6910 encoder->disable(state, encoder,
6911 old_crtc_state, old_conn_state);
6915 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6916 struct intel_crtc *crtc)
6918 const struct intel_crtc_state *old_crtc_state =
6919 intel_atomic_get_old_crtc_state(state, crtc);
6920 const struct drm_connector_state *old_conn_state;
6921 struct drm_connector *conn;
6924 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6925 struct intel_encoder *encoder =
6926 to_intel_encoder(old_conn_state->best_encoder);
6928 if (old_conn_state->crtc != &crtc->base)
6931 if (encoder->post_disable)
6932 encoder->post_disable(state, encoder,
6933 old_crtc_state, old_conn_state);
6937 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6938 struct intel_crtc *crtc)
6940 const struct intel_crtc_state *old_crtc_state =
6941 intel_atomic_get_old_crtc_state(state, crtc);
6942 const struct drm_connector_state *old_conn_state;
6943 struct drm_connector *conn;
6946 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6947 struct intel_encoder *encoder =
6948 to_intel_encoder(old_conn_state->best_encoder);
6950 if (old_conn_state->crtc != &crtc->base)
6953 if (encoder->post_pll_disable)
6954 encoder->post_pll_disable(state, encoder,
6955 old_crtc_state, old_conn_state);
6959 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6960 struct intel_crtc *crtc)
6962 const struct intel_crtc_state *crtc_state =
6963 intel_atomic_get_new_crtc_state(state, crtc);
6964 const struct drm_connector_state *conn_state;
6965 struct drm_connector *conn;
6968 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6969 struct intel_encoder *encoder =
6970 to_intel_encoder(conn_state->best_encoder);
6972 if (conn_state->crtc != &crtc->base)
6975 if (encoder->update_pipe)
6976 encoder->update_pipe(state, encoder,
6977 crtc_state, conn_state);
6981 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6984 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6986 plane->disable_plane(plane, crtc_state);
6989 static void ilk_crtc_enable(struct intel_atomic_state *state,
6990 struct intel_crtc *crtc)
6992 const struct intel_crtc_state *new_crtc_state =
6993 intel_atomic_get_new_crtc_state(state, crtc);
6994 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6995 enum pipe pipe = crtc->pipe;
6997 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7001 * Sometimes spurious CPU pipe underruns happen during FDI
7002 * training, at least with VGA+HDMI cloning. Suppress them.
7004 * On ILK we get an occasional spurious CPU pipe underruns
7005 * between eDP port A enable and vdd enable. Also PCH port
7006 * enable seems to result in the occasional CPU pipe underrun.
7008 * Spurious PCH underruns also occur during PCH enabling.
7010 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7011 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7013 if (new_crtc_state->has_pch_encoder)
7014 intel_prepare_shared_dpll(new_crtc_state);
7016 if (intel_crtc_has_dp_encoder(new_crtc_state))
7017 intel_dp_set_m_n(new_crtc_state, M1_N1);
7019 intel_set_transcoder_timings(new_crtc_state);
7020 intel_set_pipe_src_size(new_crtc_state);
7022 if (new_crtc_state->has_pch_encoder)
7023 intel_cpu_transcoder_set_m_n(new_crtc_state,
7024 &new_crtc_state->fdi_m_n, NULL);
7026 ilk_set_pipeconf(new_crtc_state);
7028 crtc->active = true;
7030 intel_encoders_pre_enable(state, crtc);
7032 if (new_crtc_state->has_pch_encoder) {
7033 /* Note: FDI PLL enabling _must_ be done before we enable the
7034 * cpu pipes, hence this is separate from all the other fdi/pch
7036 ilk_fdi_pll_enable(new_crtc_state);
7038 assert_fdi_tx_disabled(dev_priv, pipe);
7039 assert_fdi_rx_disabled(dev_priv, pipe);
7042 ilk_pfit_enable(new_crtc_state);
7045 * On ILK+ LUT must be loaded before the pipe is running but with
7048 intel_color_load_luts(new_crtc_state);
7049 intel_color_commit(new_crtc_state);
7050 /* update DSPCNTR to configure gamma for pipe bottom color */
7051 intel_disable_primary_plane(new_crtc_state);
7053 if (dev_priv->display.initial_watermarks)
7054 dev_priv->display.initial_watermarks(state, crtc);
7055 intel_enable_pipe(new_crtc_state);
7057 if (new_crtc_state->has_pch_encoder)
7058 ilk_pch_enable(state, new_crtc_state);
7060 intel_crtc_vblank_on(new_crtc_state);
7062 intel_encoders_enable(state, crtc);
7064 if (HAS_PCH_CPT(dev_priv))
7065 cpt_verify_modeset(dev_priv, pipe);
7068 * Must wait for vblank to avoid spurious PCH FIFO underruns.
7069 * And a second vblank wait is needed at least on ILK with
7070 * some interlaced HDMI modes. Let's do the double wait always
7071 * in case there are more corner cases we don't know about.
7073 if (new_crtc_state->has_pch_encoder) {
7074 intel_wait_for_vblank(dev_priv, pipe);
7075 intel_wait_for_vblank(dev_priv, pipe);
7077 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7078 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7081 /* IPS only exists on ULT machines and is tied to pipe A. */
7082 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
7084 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
7087 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
7088 enum pipe pipe, bool apply)
7090 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
7091 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
7098 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
7101 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
7103 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7104 enum pipe pipe = crtc->pipe;
7107 val = MBUS_DBOX_A_CREDIT(2);
7109 if (INTEL_GEN(dev_priv) >= 12) {
7110 val |= MBUS_DBOX_BW_CREDIT(2);
7111 val |= MBUS_DBOX_B_CREDIT(12);
7113 val |= MBUS_DBOX_BW_CREDIT(1);
7114 val |= MBUS_DBOX_B_CREDIT(8);
7117 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
7120 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
7122 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7123 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7125 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7126 HSW_LINETIME(crtc_state->linetime) |
7127 HSW_IPS_LINETIME(crtc_state->ips_linetime));
7130 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7132 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7133 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7134 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7137 val = intel_de_read(dev_priv, reg);
7138 val &= ~HSW_FRAME_START_DELAY_MASK;
7139 val |= HSW_FRAME_START_DELAY(0);
7140 intel_de_write(dev_priv, reg, val);
7143 static void hsw_crtc_enable(struct intel_atomic_state *state,
7144 struct intel_crtc *crtc)
7146 const struct intel_crtc_state *new_crtc_state =
7147 intel_atomic_get_new_crtc_state(state, crtc);
7148 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7149 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7150 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7151 bool psl_clkgate_wa;
7153 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7156 intel_encoders_pre_pll_enable(state, crtc);
7158 if (new_crtc_state->shared_dpll)
7159 intel_enable_shared_dpll(new_crtc_state);
7161 intel_encoders_pre_enable(state, crtc);
7163 if (!transcoder_is_dsi(cpu_transcoder))
7164 intel_set_transcoder_timings(new_crtc_state);
7166 intel_set_pipe_src_size(new_crtc_state);
7168 if (cpu_transcoder != TRANSCODER_EDP &&
7169 !transcoder_is_dsi(cpu_transcoder))
7170 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7171 new_crtc_state->pixel_multiplier - 1);
7173 if (new_crtc_state->has_pch_encoder)
7174 intel_cpu_transcoder_set_m_n(new_crtc_state,
7175 &new_crtc_state->fdi_m_n, NULL);
7177 if (!transcoder_is_dsi(cpu_transcoder)) {
7178 hsw_set_frame_start_delay(new_crtc_state);
7179 hsw_set_pipeconf(new_crtc_state);
7182 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7183 bdw_set_pipemisc(new_crtc_state);
7185 crtc->active = true;
7187 /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7188 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7189 new_crtc_state->pch_pfit.enabled;
7191 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7193 if (INTEL_GEN(dev_priv) >= 9)
7194 skl_pfit_enable(new_crtc_state);
7196 ilk_pfit_enable(new_crtc_state);
7199 * On ILK+ LUT must be loaded before the pipe is running but with
7202 intel_color_load_luts(new_crtc_state);
7203 intel_color_commit(new_crtc_state);
7204 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7205 if (INTEL_GEN(dev_priv) < 9)
7206 intel_disable_primary_plane(new_crtc_state);
7208 hsw_set_linetime_wm(new_crtc_state);
7210 if (INTEL_GEN(dev_priv) >= 11)
7211 icl_set_pipe_chicken(crtc);
7213 if (dev_priv->display.initial_watermarks)
7214 dev_priv->display.initial_watermarks(state, crtc);
7216 if (INTEL_GEN(dev_priv) >= 11)
7217 icl_pipe_mbus_enable(crtc);
7219 intel_encoders_enable(state, crtc);
7221 if (psl_clkgate_wa) {
7222 intel_wait_for_vblank(dev_priv, pipe);
7223 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7226 /* If we change the relative order between pipe/planes enabling, we need
7227 * to change the workaround. */
7228 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7229 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7230 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7231 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7235 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7237 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7239 enum pipe pipe = crtc->pipe;
7241 /* To avoid upsetting the power well on haswell only disable the pfit if
7242 * it's in use. The hw state code will make sure we get this right. */
7243 if (!old_crtc_state->pch_pfit.enabled)
7246 intel_de_write(dev_priv, PF_CTL(pipe), 0);
7247 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7248 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7251 static void ilk_crtc_disable(struct intel_atomic_state *state,
7252 struct intel_crtc *crtc)
7254 const struct intel_crtc_state *old_crtc_state =
7255 intel_atomic_get_old_crtc_state(state, crtc);
7256 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7257 enum pipe pipe = crtc->pipe;
7260 * Sometimes spurious CPU pipe underruns happen when the
7261 * pipe is already disabled, but FDI RX/TX is still enabled.
7262 * Happens at least with VGA+HDMI cloning. Suppress them.
7264 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7265 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7267 intel_encoders_disable(state, crtc);
7269 intel_crtc_vblank_off(old_crtc_state);
7271 intel_disable_pipe(old_crtc_state);
7273 ilk_pfit_disable(old_crtc_state);
7275 if (old_crtc_state->has_pch_encoder)
7276 ilk_fdi_disable(crtc);
7278 intel_encoders_post_disable(state, crtc);
7280 if (old_crtc_state->has_pch_encoder) {
7281 ilk_disable_pch_transcoder(dev_priv, pipe);
7283 if (HAS_PCH_CPT(dev_priv)) {
7287 /* disable TRANS_DP_CTL */
7288 reg = TRANS_DP_CTL(pipe);
7289 temp = intel_de_read(dev_priv, reg);
7290 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7291 TRANS_DP_PORT_SEL_MASK);
7292 temp |= TRANS_DP_PORT_SEL_NONE;
7293 intel_de_write(dev_priv, reg, temp);
7295 /* disable DPLL_SEL */
7296 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7297 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7298 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7301 ilk_fdi_pll_disable(crtc);
7304 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7305 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7308 static void hsw_crtc_disable(struct intel_atomic_state *state,
7309 struct intel_crtc *crtc)
7312 * FIXME collapse everything to one hook.
7313 * Need care with mst->ddi interactions.
7315 intel_encoders_disable(state, crtc);
7316 intel_encoders_post_disable(state, crtc);
7319 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7321 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7322 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7324 if (!crtc_state->gmch_pfit.control)
7328 * The panel fitter should only be adjusted whilst the pipe is disabled,
7329 * according to register description and PRM.
7331 drm_WARN_ON(&dev_priv->drm,
7332 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7333 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7335 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7336 crtc_state->gmch_pfit.pgm_ratios);
7337 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7339 /* Border color in case we don't scale up to the full screen. Black by
7340 * default, change to something else for debugging. */
7341 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7344 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7346 if (phy == PHY_NONE)
7348 else if (IS_ROCKETLAKE(dev_priv))
7349 return phy <= PHY_D;
7350 else if (IS_JSL_EHL(dev_priv))
7351 return phy <= PHY_C;
7352 else if (INTEL_GEN(dev_priv) >= 11)
7353 return phy <= PHY_B;
7358 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7360 if (IS_ROCKETLAKE(dev_priv))
7362 else if (INTEL_GEN(dev_priv) >= 12)
7363 return phy >= PHY_D && phy <= PHY_I;
7364 else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
7365 return phy >= PHY_C && phy <= PHY_F;
7370 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7372 if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
7373 return PHY_C + port - PORT_TC1;
7374 else if (IS_JSL_EHL(i915) && port == PORT_D)
7377 return PHY_A + port - PORT_A;
7380 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7382 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7383 return TC_PORT_NONE;
7385 if (INTEL_GEN(dev_priv) >= 12)
7386 return TC_PORT_1 + port - PORT_TC1;
7388 return TC_PORT_1 + port - PORT_C;
7391 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7395 return POWER_DOMAIN_PORT_DDI_A_LANES;
7397 return POWER_DOMAIN_PORT_DDI_B_LANES;
7399 return POWER_DOMAIN_PORT_DDI_C_LANES;
7401 return POWER_DOMAIN_PORT_DDI_D_LANES;
7403 return POWER_DOMAIN_PORT_DDI_E_LANES;
7405 return POWER_DOMAIN_PORT_DDI_F_LANES;
7407 return POWER_DOMAIN_PORT_DDI_G_LANES;
7409 return POWER_DOMAIN_PORT_DDI_H_LANES;
7411 return POWER_DOMAIN_PORT_DDI_I_LANES;
7414 return POWER_DOMAIN_PORT_OTHER;
7418 enum intel_display_power_domain
7419 intel_aux_power_domain(struct intel_digital_port *dig_port)
7421 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7422 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7424 if (intel_phy_is_tc(dev_priv, phy) &&
7425 dig_port->tc_mode == TC_PORT_TBT_ALT) {
7426 switch (dig_port->aux_ch) {
7428 return POWER_DOMAIN_AUX_C_TBT;
7430 return POWER_DOMAIN_AUX_D_TBT;
7432 return POWER_DOMAIN_AUX_E_TBT;
7434 return POWER_DOMAIN_AUX_F_TBT;
7436 return POWER_DOMAIN_AUX_G_TBT;
7438 return POWER_DOMAIN_AUX_H_TBT;
7440 return POWER_DOMAIN_AUX_I_TBT;
7442 MISSING_CASE(dig_port->aux_ch);
7443 return POWER_DOMAIN_AUX_C_TBT;
7447 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
7451 * Converts aux_ch to power_domain without caring about TBT ports for that use
7452 * intel_aux_power_domain()
7454 enum intel_display_power_domain
7455 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
7459 return POWER_DOMAIN_AUX_A;
7461 return POWER_DOMAIN_AUX_B;
7463 return POWER_DOMAIN_AUX_C;
7465 return POWER_DOMAIN_AUX_D;
7467 return POWER_DOMAIN_AUX_E;
7469 return POWER_DOMAIN_AUX_F;
7471 return POWER_DOMAIN_AUX_G;
7473 return POWER_DOMAIN_AUX_H;
7475 return POWER_DOMAIN_AUX_I;
7477 MISSING_CASE(aux_ch);
7478 return POWER_DOMAIN_AUX_A;
7482 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7484 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7485 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7486 struct drm_encoder *encoder;
7487 enum pipe pipe = crtc->pipe;
7489 enum transcoder transcoder = crtc_state->cpu_transcoder;
7491 if (!crtc_state->hw.active)
7494 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7495 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7496 if (crtc_state->pch_pfit.enabled ||
7497 crtc_state->pch_pfit.force_thru)
7498 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7500 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7501 crtc_state->uapi.encoder_mask) {
7502 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7504 mask |= BIT_ULL(intel_encoder->power_domain);
7507 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7508 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7510 if (crtc_state->shared_dpll)
7511 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7517 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7519 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7520 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7521 enum intel_display_power_domain domain;
7522 u64 domains, new_domains, old_domains;
7524 old_domains = crtc->enabled_power_domains;
7525 crtc->enabled_power_domains = new_domains =
7526 get_crtc_power_domains(crtc_state);
7528 domains = new_domains & ~old_domains;
7530 for_each_power_domain(domain, domains)
7531 intel_display_power_get(dev_priv, domain);
7533 return old_domains & ~new_domains;
7536 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7539 enum intel_display_power_domain domain;
7541 for_each_power_domain(domain, domains)
7542 intel_display_power_put_unchecked(dev_priv, domain);
7545 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7546 struct intel_crtc *crtc)
7548 const struct intel_crtc_state *new_crtc_state =
7549 intel_atomic_get_new_crtc_state(state, crtc);
7550 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7551 enum pipe pipe = crtc->pipe;
7553 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7556 if (intel_crtc_has_dp_encoder(new_crtc_state))
7557 intel_dp_set_m_n(new_crtc_state, M1_N1);
7559 intel_set_transcoder_timings(new_crtc_state);
7560 intel_set_pipe_src_size(new_crtc_state);
7562 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7563 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7564 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7567 i9xx_set_pipeconf(new_crtc_state);
7569 crtc->active = true;
7571 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7573 intel_encoders_pre_pll_enable(state, crtc);
7575 if (IS_CHERRYVIEW(dev_priv)) {
7576 chv_prepare_pll(crtc, new_crtc_state);
7577 chv_enable_pll(crtc, new_crtc_state);
7579 vlv_prepare_pll(crtc, new_crtc_state);
7580 vlv_enable_pll(crtc, new_crtc_state);
7583 intel_encoders_pre_enable(state, crtc);
7585 i9xx_pfit_enable(new_crtc_state);
7587 intel_color_load_luts(new_crtc_state);
7588 intel_color_commit(new_crtc_state);
7589 /* update DSPCNTR to configure gamma for pipe bottom color */
7590 intel_disable_primary_plane(new_crtc_state);
7592 dev_priv->display.initial_watermarks(state, crtc);
7593 intel_enable_pipe(new_crtc_state);
7595 intel_crtc_vblank_on(new_crtc_state);
7597 intel_encoders_enable(state, crtc);
7600 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7602 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7603 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7605 intel_de_write(dev_priv, FP0(crtc->pipe),
7606 crtc_state->dpll_hw_state.fp0);
7607 intel_de_write(dev_priv, FP1(crtc->pipe),
7608 crtc_state->dpll_hw_state.fp1);
7611 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7612 struct intel_crtc *crtc)
7614 const struct intel_crtc_state *new_crtc_state =
7615 intel_atomic_get_new_crtc_state(state, crtc);
7616 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7617 enum pipe pipe = crtc->pipe;
7619 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7622 i9xx_set_pll_dividers(new_crtc_state);
7624 if (intel_crtc_has_dp_encoder(new_crtc_state))
7625 intel_dp_set_m_n(new_crtc_state, M1_N1);
7627 intel_set_transcoder_timings(new_crtc_state);
7628 intel_set_pipe_src_size(new_crtc_state);
7630 i9xx_set_pipeconf(new_crtc_state);
7632 crtc->active = true;
7634 if (!IS_GEN(dev_priv, 2))
7635 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7637 intel_encoders_pre_enable(state, crtc);
7639 i9xx_enable_pll(crtc, new_crtc_state);
7641 i9xx_pfit_enable(new_crtc_state);
7643 intel_color_load_luts(new_crtc_state);
7644 intel_color_commit(new_crtc_state);
7645 /* update DSPCNTR to configure gamma for pipe bottom color */
7646 intel_disable_primary_plane(new_crtc_state);
7648 if (dev_priv->display.initial_watermarks)
7649 dev_priv->display.initial_watermarks(state, crtc);
7651 intel_update_watermarks(crtc);
7652 intel_enable_pipe(new_crtc_state);
7654 intel_crtc_vblank_on(new_crtc_state);
7656 intel_encoders_enable(state, crtc);
7658 /* prevents spurious underruns */
7659 if (IS_GEN(dev_priv, 2))
7660 intel_wait_for_vblank(dev_priv, pipe);
7663 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7665 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7666 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7668 if (!old_crtc_state->gmch_pfit.control)
7671 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7673 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7674 intel_de_read(dev_priv, PFIT_CONTROL));
7675 intel_de_write(dev_priv, PFIT_CONTROL, 0);
7678 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7679 struct intel_crtc *crtc)
7681 struct intel_crtc_state *old_crtc_state =
7682 intel_atomic_get_old_crtc_state(state, crtc);
7683 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7684 enum pipe pipe = crtc->pipe;
7687 * On gen2 planes are double buffered but the pipe isn't, so we must
7688 * wait for planes to fully turn off before disabling the pipe.
7690 if (IS_GEN(dev_priv, 2))
7691 intel_wait_for_vblank(dev_priv, pipe);
7693 intel_encoders_disable(state, crtc);
7695 intel_crtc_vblank_off(old_crtc_state);
7697 intel_disable_pipe(old_crtc_state);
7699 i9xx_pfit_disable(old_crtc_state);
7701 intel_encoders_post_disable(state, crtc);
7703 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7704 if (IS_CHERRYVIEW(dev_priv))
7705 chv_disable_pll(dev_priv, pipe);
7706 else if (IS_VALLEYVIEW(dev_priv))
7707 vlv_disable_pll(dev_priv, pipe);
7709 i9xx_disable_pll(old_crtc_state);
7712 intel_encoders_post_pll_disable(state, crtc);
7714 if (!IS_GEN(dev_priv, 2))
7715 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7717 if (!dev_priv->display.initial_watermarks)
7718 intel_update_watermarks(crtc);
7720 /* clock the pipe down to 640x480@60 to potentially save power */
7721 if (IS_I830(dev_priv))
7722 i830_enable_pipe(dev_priv, pipe);
7725 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7726 struct drm_modeset_acquire_ctx *ctx)
7728 struct intel_encoder *encoder;
7729 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7730 struct intel_bw_state *bw_state =
7731 to_intel_bw_state(dev_priv->bw_obj.state);
7732 struct intel_cdclk_state *cdclk_state =
7733 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7734 struct intel_dbuf_state *dbuf_state =
7735 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
7736 struct intel_crtc_state *crtc_state =
7737 to_intel_crtc_state(crtc->base.state);
7738 enum intel_display_power_domain domain;
7739 struct intel_plane *plane;
7740 struct drm_atomic_state *state;
7741 struct intel_crtc_state *temp_crtc_state;
7742 enum pipe pipe = crtc->pipe;
7746 if (!crtc_state->hw.active)
7749 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7750 const struct intel_plane_state *plane_state =
7751 to_intel_plane_state(plane->base.state);
7753 if (plane_state->uapi.visible)
7754 intel_plane_disable_noatomic(crtc, plane);
7757 state = drm_atomic_state_alloc(&dev_priv->drm);
7759 drm_dbg_kms(&dev_priv->drm,
7760 "failed to disable [CRTC:%d:%s], out of memory",
7761 crtc->base.base.id, crtc->base.name);
7765 state->acquire_ctx = ctx;
7767 /* Everything's already locked, -EDEADLK can't happen. */
7768 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7769 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7771 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7773 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7775 drm_atomic_state_put(state);
7777 drm_dbg_kms(&dev_priv->drm,
7778 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7779 crtc->base.base.id, crtc->base.name);
7781 crtc->active = false;
7782 crtc->base.enabled = false;
7784 drm_WARN_ON(&dev_priv->drm,
7785 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7786 crtc_state->uapi.active = false;
7787 crtc_state->uapi.connector_mask = 0;
7788 crtc_state->uapi.encoder_mask = 0;
7789 intel_crtc_free_hw_state(crtc_state);
7790 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7792 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7793 encoder->base.crtc = NULL;
7795 intel_fbc_disable(crtc);
7796 intel_update_watermarks(crtc);
7797 intel_disable_shared_dpll(crtc_state);
7799 domains = crtc->enabled_power_domains;
7800 for_each_power_domain(domain, domains)
7801 intel_display_power_put_unchecked(dev_priv, domain);
7802 crtc->enabled_power_domains = 0;
7804 dev_priv->active_pipes &= ~BIT(pipe);
7805 cdclk_state->min_cdclk[pipe] = 0;
7806 cdclk_state->min_voltage_level[pipe] = 0;
7807 cdclk_state->active_pipes &= ~BIT(pipe);
7809 dbuf_state->active_pipes &= ~BIT(pipe);
7811 bw_state->data_rate[pipe] = 0;
7812 bw_state->num_active_planes[pipe] = 0;
7816 * turn all crtc's off, but do not adjust state
7817 * This has to be paired with a call to intel_modeset_setup_hw_state.
7819 int intel_display_suspend(struct drm_device *dev)
7821 struct drm_i915_private *dev_priv = to_i915(dev);
7822 struct drm_atomic_state *state;
7825 state = drm_atomic_helper_suspend(dev);
7826 ret = PTR_ERR_OR_ZERO(state);
7828 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7831 dev_priv->modeset_restore_state = state;
7835 void intel_encoder_destroy(struct drm_encoder *encoder)
7837 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7839 drm_encoder_cleanup(encoder);
7840 kfree(intel_encoder);
7843 /* Cross check the actual hw state with our own modeset state tracking (and it's
7844 * internal consistency). */
7845 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7846 struct drm_connector_state *conn_state)
7848 struct intel_connector *connector = to_intel_connector(conn_state->connector);
7849 struct drm_i915_private *i915 = to_i915(connector->base.dev);
7851 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7852 connector->base.base.id, connector->base.name);
7854 if (connector->get_hw_state(connector)) {
7855 struct intel_encoder *encoder = intel_attached_encoder(connector);
7857 I915_STATE_WARN(!crtc_state,
7858 "connector enabled without attached crtc\n");
7863 I915_STATE_WARN(!crtc_state->hw.active,
7864 "connector is active, but attached crtc isn't\n");
7866 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7869 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7870 "atomic encoder doesn't match attached encoder\n");
7872 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7873 "attached encoder crtc differs from connector crtc\n");
7875 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7876 "attached crtc is active, but connector isn't\n");
7877 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7878 "best encoder set without crtc!\n");
7882 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7884 if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7885 return crtc_state->fdi_lanes;
7890 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7891 struct intel_crtc_state *pipe_config)
7893 struct drm_i915_private *dev_priv = to_i915(dev);
7894 struct drm_atomic_state *state = pipe_config->uapi.state;
7895 struct intel_crtc *other_crtc;
7896 struct intel_crtc_state *other_crtc_state;
7898 drm_dbg_kms(&dev_priv->drm,
7899 "checking fdi config on pipe %c, lanes %i\n",
7900 pipe_name(pipe), pipe_config->fdi_lanes);
7901 if (pipe_config->fdi_lanes > 4) {
7902 drm_dbg_kms(&dev_priv->drm,
7903 "invalid fdi lane config on pipe %c: %i lanes\n",
7904 pipe_name(pipe), pipe_config->fdi_lanes);
7908 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7909 if (pipe_config->fdi_lanes > 2) {
7910 drm_dbg_kms(&dev_priv->drm,
7911 "only 2 lanes on haswell, required: %i lanes\n",
7912 pipe_config->fdi_lanes);
7919 if (INTEL_NUM_PIPES(dev_priv) == 2)
7922 /* Ivybridge 3 pipe is really complicated */
7927 if (pipe_config->fdi_lanes <= 2)
7930 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7932 intel_atomic_get_crtc_state(state, other_crtc);
7933 if (IS_ERR(other_crtc_state))
7934 return PTR_ERR(other_crtc_state);
7936 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7937 drm_dbg_kms(&dev_priv->drm,
7938 "invalid shared fdi lane config on pipe %c: %i lanes\n",
7939 pipe_name(pipe), pipe_config->fdi_lanes);
7944 if (pipe_config->fdi_lanes > 2) {
7945 drm_dbg_kms(&dev_priv->drm,
7946 "only 2 lanes on pipe %c: required %i lanes\n",
7947 pipe_name(pipe), pipe_config->fdi_lanes);
7951 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7953 intel_atomic_get_crtc_state(state, other_crtc);
7954 if (IS_ERR(other_crtc_state))
7955 return PTR_ERR(other_crtc_state);
7957 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7958 drm_dbg_kms(&dev_priv->drm,
7959 "fdi link B uses too many lanes to enable link C\n");
7969 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7970 struct intel_crtc_state *pipe_config)
7972 struct drm_device *dev = intel_crtc->base.dev;
7973 struct drm_i915_private *i915 = to_i915(dev);
7974 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7975 int lane, link_bw, fdi_dotclock, ret;
7976 bool needs_recompute = false;
7979 /* FDI is a binary signal running at ~2.7GHz, encoding
7980 * each output octet as 10 bits. The actual frequency
7981 * is stored as a divider into a 100MHz clock, and the
7982 * mode pixel clock is stored in units of 1KHz.
7983 * Hence the bw of each lane in terms of the mode signal
7986 link_bw = intel_fdi_link_freq(i915, pipe_config);
7988 fdi_dotclock = adjusted_mode->crtc_clock;
7990 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7991 pipe_config->pipe_bpp);
7993 pipe_config->fdi_lanes = lane;
7995 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7996 link_bw, &pipe_config->fdi_m_n, false, false);
7998 ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7999 if (ret == -EDEADLK)
8002 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
8003 pipe_config->pipe_bpp -= 2*3;
8004 drm_dbg_kms(&i915->drm,
8005 "fdi link bw constraint, reducing pipe bpp to %i\n",
8006 pipe_config->pipe_bpp);
8007 needs_recompute = true;
8008 pipe_config->bw_constrained = true;
8013 if (needs_recompute)
8019 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
8021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8022 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8024 /* IPS only exists on ULT machines and is tied to pipe A. */
8025 if (!hsw_crtc_supports_ips(crtc))
8028 if (!dev_priv->params.enable_ips)
8031 if (crtc_state->pipe_bpp > 24)
8035 * We compare against max which means we must take
8036 * the increased cdclk requirement into account when
8037 * calculating the new cdclk.
8039 * Should measure whether using a lower cdclk w/o IPS
8041 if (IS_BROADWELL(dev_priv) &&
8042 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
8048 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
8050 struct drm_i915_private *dev_priv =
8051 to_i915(crtc_state->uapi.crtc->dev);
8052 struct intel_atomic_state *state =
8053 to_intel_atomic_state(crtc_state->uapi.state);
8055 crtc_state->ips_enabled = false;
8057 if (!hsw_crtc_state_ips_capable(crtc_state))
8061 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
8062 * enabled and disabled dynamically based on package C states,
8063 * user space can't make reliable use of the CRCs, so let's just
8064 * completely disable it.
8066 if (crtc_state->crc_enabled)
8069 /* IPS should be fine as long as at least one plane is enabled. */
8070 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
8073 if (IS_BROADWELL(dev_priv)) {
8074 const struct intel_cdclk_state *cdclk_state;
8076 cdclk_state = intel_atomic_get_cdclk_state(state);
8077 if (IS_ERR(cdclk_state))
8078 return PTR_ERR(cdclk_state);
8080 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
8081 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
8085 crtc_state->ips_enabled = true;
8090 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
8092 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8094 /* GDG double wide on either pipe, otherwise pipe A only */
8095 return INTEL_GEN(dev_priv) < 4 &&
8096 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
8099 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
8101 u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
8102 unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
8105 * We only use IF-ID interlacing. If we ever use
8106 * PF-ID we'll need to adjust the pixel_rate here.
8109 if (!crtc_state->pch_pfit.enabled)
8112 pipe_w = crtc_state->pipe_src_w;
8113 pipe_h = crtc_state->pipe_src_h;
8115 pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
8116 pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
8118 if (pipe_w < pfit_w)
8120 if (pipe_h < pfit_h)
8123 if (drm_WARN_ON(crtc_state->uapi.crtc->dev,
8124 !pfit_w || !pfit_h))
8127 return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
8131 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
8132 const struct drm_display_mode *timings)
8134 mode->hdisplay = timings->crtc_hdisplay;
8135 mode->htotal = timings->crtc_htotal;
8136 mode->hsync_start = timings->crtc_hsync_start;
8137 mode->hsync_end = timings->crtc_hsync_end;
8139 mode->vdisplay = timings->crtc_vdisplay;
8140 mode->vtotal = timings->crtc_vtotal;
8141 mode->vsync_start = timings->crtc_vsync_start;
8142 mode->vsync_end = timings->crtc_vsync_end;
8144 mode->flags = timings->flags;
8145 mode->type = DRM_MODE_TYPE_DRIVER;
8147 mode->clock = timings->crtc_clock;
8149 drm_mode_set_name(mode);
8152 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
8154 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8156 if (HAS_GMCH(dev_priv))
8157 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
8158 crtc_state->pixel_rate =
8159 crtc_state->hw.adjusted_mode.crtc_clock;
8161 crtc_state->pixel_rate =
8162 ilk_pipe_pixel_rate(crtc_state);
8165 static void intel_encoder_get_config(struct intel_encoder *encoder,
8166 struct intel_crtc_state *crtc_state)
8168 encoder->get_config(encoder, crtc_state);
8171 static int intel_crtc_compute_config(struct intel_crtc *crtc,
8172 struct intel_crtc_state *pipe_config)
8174 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8175 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
8176 int clock_limit = dev_priv->max_dotclk_freq;
8178 if (INTEL_GEN(dev_priv) < 4) {
8179 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8182 * Enable double wide mode when the dot clock
8183 * is > 90% of the (display) core speed.
8185 if (intel_crtc_supports_double_wide(crtc) &&
8186 adjusted_mode->crtc_clock > clock_limit) {
8187 clock_limit = dev_priv->max_dotclk_freq;
8188 pipe_config->double_wide = true;
8192 if (adjusted_mode->crtc_clock > clock_limit) {
8193 drm_dbg_kms(&dev_priv->drm,
8194 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8195 adjusted_mode->crtc_clock, clock_limit,
8196 yesno(pipe_config->double_wide));
8200 if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8201 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8202 pipe_config->hw.ctm) {
8204 * There is only one pipe CSC unit per pipe, and we need that
8205 * for output conversion from RGB->YCBCR. So if CTM is already
8206 * applied we can't support YCBCR420 output.
8208 drm_dbg_kms(&dev_priv->drm,
8209 "YCBCR420 and CTM together are not possible\n");
8214 * Pipe horizontal size must be even in:
8216 * - LVDS dual channel mode
8217 * - Double wide pipe
8219 if (pipe_config->pipe_src_w & 1) {
8220 if (pipe_config->double_wide) {
8221 drm_dbg_kms(&dev_priv->drm,
8222 "Odd pipe source width not supported with double wide pipe\n");
8226 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8227 intel_is_dual_link_lvds(dev_priv)) {
8228 drm_dbg_kms(&dev_priv->drm,
8229 "Odd pipe source width not supported with dual link LVDS\n");
8234 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8235 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8237 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8238 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8241 intel_crtc_compute_pixel_rate(pipe_config);
8243 if (pipe_config->has_pch_encoder)
8244 return ilk_fdi_compute_config(crtc, pipe_config);
8250 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8252 while (*num > DATA_LINK_M_N_MASK ||
8253 *den > DATA_LINK_M_N_MASK) {
8259 static void compute_m_n(unsigned int m, unsigned int n,
8260 u32 *ret_m, u32 *ret_n,
8264 * Several DP dongles in particular seem to be fussy about
8265 * too large link M/N values. Give N value as 0x8000 that
8266 * should be acceptable by specific devices. 0x8000 is the
8267 * specified fixed N value for asynchronous clock mode,
8268 * which the devices expect also in synchronous clock mode.
8271 *ret_n = DP_LINK_CONSTANT_N_VALUE;
8273 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8275 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8276 intel_reduce_m_n_ratio(ret_m, ret_n);
8280 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8281 int pixel_clock, int link_clock,
8282 struct intel_link_m_n *m_n,
8283 bool constant_n, bool fec_enable)
8285 u32 data_clock = bits_per_pixel * pixel_clock;
8288 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8291 compute_m_n(data_clock,
8292 link_clock * nlanes * 8,
8293 &m_n->gmch_m, &m_n->gmch_n,
8296 compute_m_n(pixel_clock, link_clock,
8297 &m_n->link_m, &m_n->link_n,
8301 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8304 * There may be no VBT; and if the BIOS enabled SSC we can
8305 * just keep using it to avoid unnecessary flicker. Whereas if the
8306 * BIOS isn't using it, don't assume it will work even if the VBT
8307 * indicates as much.
8309 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8310 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8314 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8315 drm_dbg_kms(&dev_priv->drm,
8316 "SSC %s by BIOS, overriding VBT which says %s\n",
8317 enableddisabled(bios_lvds_use_ssc),
8318 enableddisabled(dev_priv->vbt.lvds_use_ssc));
8319 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8324 static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8326 if (dev_priv->params.panel_use_ssc >= 0)
8327 return dev_priv->params.panel_use_ssc != 0;
8328 return dev_priv->vbt.lvds_use_ssc
8329 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8332 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8334 return (1 << dpll->n) << 16 | dpll->m2;
8337 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8339 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8342 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8343 struct intel_crtc_state *crtc_state,
8344 struct dpll *reduced_clock)
8346 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8349 if (IS_PINEVIEW(dev_priv)) {
8350 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8352 fp2 = pnv_dpll_compute_fp(reduced_clock);
8354 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8356 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8359 crtc_state->dpll_hw_state.fp0 = fp;
8361 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8363 crtc_state->dpll_hw_state.fp1 = fp2;
8365 crtc_state->dpll_hw_state.fp1 = fp;
8369 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8375 * PLLB opamp always calibrates to max value of 0x3f, force enable it
8376 * and set it to a reasonable value instead.
8378 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8379 reg_val &= 0xffffff00;
8380 reg_val |= 0x00000030;
8381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8383 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8384 reg_val &= 0x00ffffff;
8385 reg_val |= 0x8c000000;
8386 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8388 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8389 reg_val &= 0xffffff00;
8390 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8392 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8393 reg_val &= 0x00ffffff;
8394 reg_val |= 0xb0000000;
8395 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8398 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8399 const struct intel_link_m_n *m_n)
8401 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8402 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8403 enum pipe pipe = crtc->pipe;
8405 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8406 TU_SIZE(m_n->tu) | m_n->gmch_m);
8407 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8408 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8409 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8412 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8413 enum transcoder transcoder)
8415 if (IS_HASWELL(dev_priv))
8416 return transcoder == TRANSCODER_EDP;
8419 * Strictly speaking some registers are available before
8420 * gen7, but we only support DRRS on gen7+
8422 return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8425 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8426 const struct intel_link_m_n *m_n,
8427 const struct intel_link_m_n *m2_n2)
8429 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8430 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8431 enum pipe pipe = crtc->pipe;
8432 enum transcoder transcoder = crtc_state->cpu_transcoder;
8434 if (INTEL_GEN(dev_priv) >= 5) {
8435 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8436 TU_SIZE(m_n->tu) | m_n->gmch_m);
8437 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8439 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8441 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8444 * M2_N2 registers are set only if DRRS is supported
8445 * (to make sure the registers are not unnecessarily accessed).
8447 if (m2_n2 && crtc_state->has_drrs &&
8448 transcoder_has_m2_n2(dev_priv, transcoder)) {
8449 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8450 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8451 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8453 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8455 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8459 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8460 TU_SIZE(m_n->tu) | m_n->gmch_m);
8461 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8462 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8463 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8467 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8469 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8470 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8473 dp_m_n = &crtc_state->dp_m_n;
8474 dp_m2_n2 = &crtc_state->dp_m2_n2;
8475 } else if (m_n == M2_N2) {
8478 * M2_N2 registers are not supported. Hence m2_n2 divider value
8479 * needs to be programmed into M1_N1.
8481 dp_m_n = &crtc_state->dp_m2_n2;
8483 drm_err(&i915->drm, "Unsupported divider value\n");
8487 if (crtc_state->has_pch_encoder)
8488 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8490 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8493 static void vlv_compute_dpll(struct intel_crtc *crtc,
8494 struct intel_crtc_state *pipe_config)
8496 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8497 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8498 if (crtc->pipe != PIPE_A)
8499 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8501 /* DPLL not used with DSI, but still need the rest set up */
8502 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8503 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8504 DPLL_EXT_BUFFER_ENABLE_VLV;
8506 pipe_config->dpll_hw_state.dpll_md =
8507 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8510 static void chv_compute_dpll(struct intel_crtc *crtc,
8511 struct intel_crtc_state *pipe_config)
8513 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8514 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8515 if (crtc->pipe != PIPE_A)
8516 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8518 /* DPLL not used with DSI, but still need the rest set up */
8519 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8520 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8522 pipe_config->dpll_hw_state.dpll_md =
8523 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8526 static void vlv_prepare_pll(struct intel_crtc *crtc,
8527 const struct intel_crtc_state *pipe_config)
8529 struct drm_device *dev = crtc->base.dev;
8530 struct drm_i915_private *dev_priv = to_i915(dev);
8531 enum pipe pipe = crtc->pipe;
8533 u32 bestn, bestm1, bestm2, bestp1, bestp2;
8534 u32 coreclk, reg_val;
8537 intel_de_write(dev_priv, DPLL(pipe),
8538 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8540 /* No need to actually set up the DPLL with DSI */
8541 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8544 vlv_dpio_get(dev_priv);
8546 bestn = pipe_config->dpll.n;
8547 bestm1 = pipe_config->dpll.m1;
8548 bestm2 = pipe_config->dpll.m2;
8549 bestp1 = pipe_config->dpll.p1;
8550 bestp2 = pipe_config->dpll.p2;
8552 /* See eDP HDMI DPIO driver vbios notes doc */
8554 /* PLL B needs special handling */
8556 vlv_pllb_recal_opamp(dev_priv, pipe);
8558 /* Set up Tx target for periodic Rcomp update */
8559 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8561 /* Disable target IRef on PLL */
8562 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8563 reg_val &= 0x00ffffff;
8564 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8566 /* Disable fast lock */
8567 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8569 /* Set idtafcrecal before PLL is enabled */
8570 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8571 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8572 mdiv |= ((bestn << DPIO_N_SHIFT));
8573 mdiv |= (1 << DPIO_K_SHIFT);
8576 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8577 * but we don't support that).
8578 * Note: don't use the DAC post divider as it seems unstable.
8580 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8581 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8583 mdiv |= DPIO_ENABLE_CALIBRATION;
8584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8586 /* Set HBR and RBR LPF coefficients */
8587 if (pipe_config->port_clock == 162000 ||
8588 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8589 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8590 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8593 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8596 if (intel_crtc_has_dp_encoder(pipe_config)) {
8597 /* Use SSC source */
8599 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8602 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8604 } else { /* HDMI or VGA */
8605 /* Use bend source */
8607 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8610 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8614 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8615 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8616 if (intel_crtc_has_dp_encoder(pipe_config))
8617 coreclk |= 0x01000000;
8618 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8620 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8622 vlv_dpio_put(dev_priv);
8625 static void chv_prepare_pll(struct intel_crtc *crtc,
8626 const struct intel_crtc_state *pipe_config)
8628 struct drm_device *dev = crtc->base.dev;
8629 struct drm_i915_private *dev_priv = to_i915(dev);
8630 enum pipe pipe = crtc->pipe;
8631 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8632 u32 loopfilter, tribuf_calcntr;
8633 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8637 /* Enable Refclk and SSC */
8638 intel_de_write(dev_priv, DPLL(pipe),
8639 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8641 /* No need to actually set up the DPLL with DSI */
8642 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8645 bestn = pipe_config->dpll.n;
8646 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8647 bestm1 = pipe_config->dpll.m1;
8648 bestm2 = pipe_config->dpll.m2 >> 22;
8649 bestp1 = pipe_config->dpll.p1;
8650 bestp2 = pipe_config->dpll.p2;
8651 vco = pipe_config->dpll.vco;
8655 vlv_dpio_get(dev_priv);
8657 /* p1 and p2 divider */
8658 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8659 5 << DPIO_CHV_S1_DIV_SHIFT |
8660 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8661 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8662 1 << DPIO_CHV_K_DIV_SHIFT);
8664 /* Feedback post-divider - m2 */
8665 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8667 /* Feedback refclk divider - n and m1 */
8668 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8669 DPIO_CHV_M1_DIV_BY_2 |
8670 1 << DPIO_CHV_N_DIV_SHIFT);
8672 /* M2 fraction division */
8673 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8675 /* M2 fraction division enable */
8676 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8677 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8678 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8680 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8681 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8683 /* Program digital lock detect threshold */
8684 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8685 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8686 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8687 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8689 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8690 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8693 if (vco == 5400000) {
8694 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8695 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8696 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8697 tribuf_calcntr = 0x9;
8698 } else if (vco <= 6200000) {
8699 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8700 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8701 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8702 tribuf_calcntr = 0x9;
8703 } else if (vco <= 6480000) {
8704 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8705 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8706 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8707 tribuf_calcntr = 0x8;
8709 /* Not supported. Apply the same limits as in the max case */
8710 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8711 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8712 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8715 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8717 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8718 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8719 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8720 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8723 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8724 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8727 vlv_dpio_put(dev_priv);
8731 * vlv_force_pll_on - forcibly enable just the PLL
8732 * @dev_priv: i915 private structure
8733 * @pipe: pipe PLL to enable
8734 * @dpll: PLL configuration
8736 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8737 * in cases where we need the PLL enabled even when @pipe is not going to
8740 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8741 const struct dpll *dpll)
8743 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8744 struct intel_crtc_state *pipe_config;
8746 pipe_config = intel_crtc_state_alloc(crtc);
8750 pipe_config->cpu_transcoder = (enum transcoder)pipe;
8751 pipe_config->pixel_multiplier = 1;
8752 pipe_config->dpll = *dpll;
8754 if (IS_CHERRYVIEW(dev_priv)) {
8755 chv_compute_dpll(crtc, pipe_config);
8756 chv_prepare_pll(crtc, pipe_config);
8757 chv_enable_pll(crtc, pipe_config);
8759 vlv_compute_dpll(crtc, pipe_config);
8760 vlv_prepare_pll(crtc, pipe_config);
8761 vlv_enable_pll(crtc, pipe_config);
8770 * vlv_force_pll_off - forcibly disable just the PLL
8771 * @dev_priv: i915 private structure
8772 * @pipe: pipe PLL to disable
8774 * Disable the PLL for @pipe. To be used in cases where we need
8775 * the PLL enabled even when @pipe is not going to be enabled.
8777 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8779 if (IS_CHERRYVIEW(dev_priv))
8780 chv_disable_pll(dev_priv, pipe);
8782 vlv_disable_pll(dev_priv, pipe);
8785 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8786 struct intel_crtc_state *crtc_state,
8787 struct dpll *reduced_clock)
8789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8791 struct dpll *clock = &crtc_state->dpll;
8793 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8795 dpll = DPLL_VGA_MODE_DIS;
8797 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8798 dpll |= DPLLB_MODE_LVDS;
8800 dpll |= DPLLB_MODE_DAC_SERIAL;
8802 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8803 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8804 dpll |= (crtc_state->pixel_multiplier - 1)
8805 << SDVO_MULTIPLIER_SHIFT_HIRES;
8808 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8809 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8810 dpll |= DPLL_SDVO_HIGH_SPEED;
8812 if (intel_crtc_has_dp_encoder(crtc_state))
8813 dpll |= DPLL_SDVO_HIGH_SPEED;
8815 /* compute bitmask from p1 value */
8816 if (IS_PINEVIEW(dev_priv))
8817 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8819 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8820 if (IS_G4X(dev_priv) && reduced_clock)
8821 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8823 switch (clock->p2) {
8825 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8828 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8831 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8834 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8837 if (INTEL_GEN(dev_priv) >= 4)
8838 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8840 if (crtc_state->sdvo_tv_clock)
8841 dpll |= PLL_REF_INPUT_TVCLKINBC;
8842 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8843 intel_panel_use_ssc(dev_priv))
8844 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8846 dpll |= PLL_REF_INPUT_DREFCLK;
8848 dpll |= DPLL_VCO_ENABLE;
8849 crtc_state->dpll_hw_state.dpll = dpll;
8851 if (INTEL_GEN(dev_priv) >= 4) {
8852 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8853 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8854 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8858 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8859 struct intel_crtc_state *crtc_state,
8860 struct dpll *reduced_clock)
8862 struct drm_device *dev = crtc->base.dev;
8863 struct drm_i915_private *dev_priv = to_i915(dev);
8865 struct dpll *clock = &crtc_state->dpll;
8867 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8869 dpll = DPLL_VGA_MODE_DIS;
8871 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8872 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8875 dpll |= PLL_P1_DIVIDE_BY_TWO;
8877 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8879 dpll |= PLL_P2_DIVIDE_BY_4;
8884 * "[Almador Errata}: For the correct operation of the muxed DVO pins
8885 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8886 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8887 * Enable) must be set to “1” in both the DPLL A Control Register
8888 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8890 * For simplicity We simply keep both bits always enabled in
8891 * both DPLLS. The spec says we should disable the DVO 2X clock
8892 * when not needed, but this seems to work fine in practice.
8894 if (IS_I830(dev_priv) ||
8895 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8896 dpll |= DPLL_DVO_2X_MODE;
8898 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8899 intel_panel_use_ssc(dev_priv))
8900 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8902 dpll |= PLL_REF_INPUT_DREFCLK;
8904 dpll |= DPLL_VCO_ENABLE;
8905 crtc_state->dpll_hw_state.dpll = dpll;
8908 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
8910 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8911 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8912 enum pipe pipe = crtc->pipe;
8913 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8914 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8915 u32 crtc_vtotal, crtc_vblank_end;
8918 /* We need to be careful not to changed the adjusted mode, for otherwise
8919 * the hw state checker will get angry at the mismatch. */
8920 crtc_vtotal = adjusted_mode->crtc_vtotal;
8921 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8923 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8924 /* the chip adds 2 halflines automatically */
8926 crtc_vblank_end -= 1;
8928 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8929 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8931 vsyncshift = adjusted_mode->crtc_hsync_start -
8932 adjusted_mode->crtc_htotal / 2;
8934 vsyncshift += adjusted_mode->crtc_htotal;
8937 if (INTEL_GEN(dev_priv) > 3)
8938 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8941 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8942 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8943 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8944 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8945 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8946 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8948 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8949 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8950 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8951 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8952 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8953 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8955 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8956 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8957 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8959 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8960 (pipe == PIPE_B || pipe == PIPE_C))
8961 intel_de_write(dev_priv, VTOTAL(pipe),
8962 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8966 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8968 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8969 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8970 enum pipe pipe = crtc->pipe;
8972 /* pipesrc controls the size that is scaled from, which should
8973 * always be the user's requested size.
8975 intel_de_write(dev_priv, PIPESRC(pipe),
8976 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8979 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8981 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8982 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8984 if (IS_GEN(dev_priv, 2))
8987 if (INTEL_GEN(dev_priv) >= 9 ||
8988 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8989 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8991 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8994 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
8995 struct intel_crtc_state *pipe_config)
8997 struct drm_device *dev = crtc->base.dev;
8998 struct drm_i915_private *dev_priv = to_i915(dev);
8999 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
9002 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
9003 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
9004 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
9006 if (!transcoder_is_dsi(cpu_transcoder)) {
9007 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
9008 pipe_config->hw.adjusted_mode.crtc_hblank_start =
9010 pipe_config->hw.adjusted_mode.crtc_hblank_end =
9011 ((tmp >> 16) & 0xffff) + 1;
9013 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
9014 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
9015 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
9017 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
9018 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
9019 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
9021 if (!transcoder_is_dsi(cpu_transcoder)) {
9022 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
9023 pipe_config->hw.adjusted_mode.crtc_vblank_start =
9025 pipe_config->hw.adjusted_mode.crtc_vblank_end =
9026 ((tmp >> 16) & 0xffff) + 1;
9028 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
9029 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
9030 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
9032 if (intel_pipe_is_interlaced(pipe_config)) {
9033 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
9034 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
9035 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
9039 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
9040 struct intel_crtc_state *pipe_config)
9042 struct drm_device *dev = crtc->base.dev;
9043 struct drm_i915_private *dev_priv = to_i915(dev);
9046 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
9047 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
9048 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
9050 pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
9051 pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
9054 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
9056 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9057 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9062 /* we keep both pipes enabled on 830 */
9063 if (IS_I830(dev_priv))
9064 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
9066 if (crtc_state->double_wide)
9067 pipeconf |= PIPECONF_DOUBLE_WIDE;
9069 /* only g4x and later have fancy bpc/dither controls */
9070 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9071 IS_CHERRYVIEW(dev_priv)) {
9072 /* Bspec claims that we can't use dithering for 30bpp pipes. */
9073 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
9074 pipeconf |= PIPECONF_DITHER_EN |
9075 PIPECONF_DITHER_TYPE_SP;
9077 switch (crtc_state->pipe_bpp) {
9079 pipeconf |= PIPECONF_6BPC;
9082 pipeconf |= PIPECONF_8BPC;
9085 pipeconf |= PIPECONF_10BPC;
9088 /* Case prevented by intel_choose_pipe_bpp_dither. */
9093 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
9094 if (INTEL_GEN(dev_priv) < 4 ||
9095 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
9096 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
9098 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
9100 pipeconf |= PIPECONF_PROGRESSIVE;
9103 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9104 crtc_state->limited_color_range)
9105 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9107 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
9109 pipeconf |= PIPECONF_FRAME_START_DELAY(0);
9111 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
9112 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
9115 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
9116 struct intel_crtc_state *crtc_state)
9118 struct drm_device *dev = crtc->base.dev;
9119 struct drm_i915_private *dev_priv = to_i915(dev);
9120 const struct intel_limit *limit;
9123 memset(&crtc_state->dpll_hw_state, 0,
9124 sizeof(crtc_state->dpll_hw_state));
9126 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9127 if (intel_panel_use_ssc(dev_priv)) {
9128 refclk = dev_priv->vbt.lvds_ssc_freq;
9129 drm_dbg_kms(&dev_priv->drm,
9130 "using SSC reference clock of %d kHz\n",
9134 limit = &intel_limits_i8xx_lvds;
9135 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
9136 limit = &intel_limits_i8xx_dvo;
9138 limit = &intel_limits_i8xx_dac;
9141 if (!crtc_state->clock_set &&
9142 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9143 refclk, NULL, &crtc_state->dpll)) {
9144 drm_err(&dev_priv->drm,
9145 "Couldn't find PLL settings for mode!\n");
9149 i8xx_compute_dpll(crtc, crtc_state, NULL);
9154 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9155 struct intel_crtc_state *crtc_state)
9157 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9158 const struct intel_limit *limit;
9161 memset(&crtc_state->dpll_hw_state, 0,
9162 sizeof(crtc_state->dpll_hw_state));
9164 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9165 if (intel_panel_use_ssc(dev_priv)) {
9166 refclk = dev_priv->vbt.lvds_ssc_freq;
9167 drm_dbg_kms(&dev_priv->drm,
9168 "using SSC reference clock of %d kHz\n",
9172 if (intel_is_dual_link_lvds(dev_priv))
9173 limit = &intel_limits_g4x_dual_channel_lvds;
9175 limit = &intel_limits_g4x_single_channel_lvds;
9176 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9177 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9178 limit = &intel_limits_g4x_hdmi;
9179 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9180 limit = &intel_limits_g4x_sdvo;
9182 /* The option is for other outputs */
9183 limit = &intel_limits_i9xx_sdvo;
9186 if (!crtc_state->clock_set &&
9187 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9188 refclk, NULL, &crtc_state->dpll)) {
9189 drm_err(&dev_priv->drm,
9190 "Couldn't find PLL settings for mode!\n");
9194 i9xx_compute_dpll(crtc, crtc_state, NULL);
9199 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9200 struct intel_crtc_state *crtc_state)
9202 struct drm_device *dev = crtc->base.dev;
9203 struct drm_i915_private *dev_priv = to_i915(dev);
9204 const struct intel_limit *limit;
9207 memset(&crtc_state->dpll_hw_state, 0,
9208 sizeof(crtc_state->dpll_hw_state));
9210 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9211 if (intel_panel_use_ssc(dev_priv)) {
9212 refclk = dev_priv->vbt.lvds_ssc_freq;
9213 drm_dbg_kms(&dev_priv->drm,
9214 "using SSC reference clock of %d kHz\n",
9218 limit = &pnv_limits_lvds;
9220 limit = &pnv_limits_sdvo;
9223 if (!crtc_state->clock_set &&
9224 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9225 refclk, NULL, &crtc_state->dpll)) {
9226 drm_err(&dev_priv->drm,
9227 "Couldn't find PLL settings for mode!\n");
9231 i9xx_compute_dpll(crtc, crtc_state, NULL);
9236 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9237 struct intel_crtc_state *crtc_state)
9239 struct drm_device *dev = crtc->base.dev;
9240 struct drm_i915_private *dev_priv = to_i915(dev);
9241 const struct intel_limit *limit;
9244 memset(&crtc_state->dpll_hw_state, 0,
9245 sizeof(crtc_state->dpll_hw_state));
9247 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9248 if (intel_panel_use_ssc(dev_priv)) {
9249 refclk = dev_priv->vbt.lvds_ssc_freq;
9250 drm_dbg_kms(&dev_priv->drm,
9251 "using SSC reference clock of %d kHz\n",
9255 limit = &intel_limits_i9xx_lvds;
9257 limit = &intel_limits_i9xx_sdvo;
9260 if (!crtc_state->clock_set &&
9261 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9262 refclk, NULL, &crtc_state->dpll)) {
9263 drm_err(&dev_priv->drm,
9264 "Couldn't find PLL settings for mode!\n");
9268 i9xx_compute_dpll(crtc, crtc_state, NULL);
9273 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9274 struct intel_crtc_state *crtc_state)
9276 int refclk = 100000;
9277 const struct intel_limit *limit = &intel_limits_chv;
9278 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9280 memset(&crtc_state->dpll_hw_state, 0,
9281 sizeof(crtc_state->dpll_hw_state));
9283 if (!crtc_state->clock_set &&
9284 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9285 refclk, NULL, &crtc_state->dpll)) {
9286 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9290 chv_compute_dpll(crtc, crtc_state);
9295 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9296 struct intel_crtc_state *crtc_state)
9298 int refclk = 100000;
9299 const struct intel_limit *limit = &intel_limits_vlv;
9300 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9302 memset(&crtc_state->dpll_hw_state, 0,
9303 sizeof(crtc_state->dpll_hw_state));
9305 if (!crtc_state->clock_set &&
9306 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9307 refclk, NULL, &crtc_state->dpll)) {
9308 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9312 vlv_compute_dpll(crtc, crtc_state);
9317 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9319 if (IS_I830(dev_priv))
9322 return INTEL_GEN(dev_priv) >= 4 ||
9323 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9326 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
9328 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9329 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9332 if (!i9xx_has_pfit(dev_priv))
9335 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9336 if (!(tmp & PFIT_ENABLE))
9339 /* Check whether the pfit is attached to our pipe. */
9340 if (INTEL_GEN(dev_priv) < 4) {
9341 if (crtc->pipe != PIPE_B)
9344 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9348 crtc_state->gmch_pfit.control = tmp;
9349 crtc_state->gmch_pfit.pgm_ratios =
9350 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
9353 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9354 struct intel_crtc_state *pipe_config)
9356 struct drm_device *dev = crtc->base.dev;
9357 struct drm_i915_private *dev_priv = to_i915(dev);
9358 enum pipe pipe = crtc->pipe;
9361 int refclk = 100000;
9363 /* In case of DSI, DPLL will not be used */
9364 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9367 vlv_dpio_get(dev_priv);
9368 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9369 vlv_dpio_put(dev_priv);
9371 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9372 clock.m2 = mdiv & DPIO_M2DIV_MASK;
9373 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9374 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9375 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9377 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9381 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9382 struct intel_initial_plane_config *plane_config)
9384 struct drm_device *dev = crtc->base.dev;
9385 struct drm_i915_private *dev_priv = to_i915(dev);
9386 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9387 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9389 u32 val, base, offset;
9390 int fourcc, pixel_format;
9391 unsigned int aligned_height;
9392 struct drm_framebuffer *fb;
9393 struct intel_framebuffer *intel_fb;
9395 if (!plane->get_hw_state(plane, &pipe))
9398 drm_WARN_ON(dev, pipe != crtc->pipe);
9400 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9402 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9406 fb = &intel_fb->base;
9410 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9412 if (INTEL_GEN(dev_priv) >= 4) {
9413 if (val & DISPPLANE_TILED) {
9414 plane_config->tiling = I915_TILING_X;
9415 fb->modifier = I915_FORMAT_MOD_X_TILED;
9418 if (val & DISPPLANE_ROTATE_180)
9419 plane_config->rotation = DRM_MODE_ROTATE_180;
9422 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9423 val & DISPPLANE_MIRROR)
9424 plane_config->rotation |= DRM_MODE_REFLECT_X;
9426 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9427 fourcc = i9xx_format_to_fourcc(pixel_format);
9428 fb->format = drm_format_info(fourcc);
9430 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9431 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9432 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9433 } else if (INTEL_GEN(dev_priv) >= 4) {
9434 if (plane_config->tiling)
9435 offset = intel_de_read(dev_priv,
9436 DSPTILEOFF(i9xx_plane));
9438 offset = intel_de_read(dev_priv,
9439 DSPLINOFF(i9xx_plane));
9440 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9442 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9444 plane_config->base = base;
9446 val = intel_de_read(dev_priv, PIPESRC(pipe));
9447 fb->width = ((val >> 16) & 0xfff) + 1;
9448 fb->height = ((val >> 0) & 0xfff) + 1;
9450 val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9451 fb->pitches[0] = val & 0xffffffc0;
9453 aligned_height = intel_fb_align_height(fb, 0, fb->height);
9455 plane_config->size = fb->pitches[0] * aligned_height;
9457 drm_dbg_kms(&dev_priv->drm,
9458 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9459 crtc->base.name, plane->base.name, fb->width, fb->height,
9460 fb->format->cpp[0] * 8, base, fb->pitches[0],
9461 plane_config->size);
9463 plane_config->fb = intel_fb;
9466 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9467 struct intel_crtc_state *pipe_config)
9469 struct drm_device *dev = crtc->base.dev;
9470 struct drm_i915_private *dev_priv = to_i915(dev);
9471 enum pipe pipe = crtc->pipe;
9472 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9474 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9475 int refclk = 100000;
9477 /* In case of DSI, DPLL will not be used */
9478 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9481 vlv_dpio_get(dev_priv);
9482 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9483 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9484 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9485 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9486 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9487 vlv_dpio_put(dev_priv);
9489 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9490 clock.m2 = (pll_dw0 & 0xff) << 22;
9491 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9492 clock.m2 |= pll_dw2 & 0x3fffff;
9493 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9494 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9495 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9497 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9500 static enum intel_output_format
9501 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9503 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9506 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9508 if (tmp & PIPEMISC_YUV420_ENABLE) {
9509 /* We support 4:2:0 in full blend mode only */
9510 drm_WARN_ON(&dev_priv->drm,
9511 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9513 return INTEL_OUTPUT_FORMAT_YCBCR420;
9514 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9515 return INTEL_OUTPUT_FORMAT_YCBCR444;
9517 return INTEL_OUTPUT_FORMAT_RGB;
9521 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9523 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9524 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9525 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9526 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9529 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9531 if (tmp & DISPPLANE_GAMMA_ENABLE)
9532 crtc_state->gamma_enable = true;
9534 if (!HAS_GMCH(dev_priv) &&
9535 tmp & DISPPLANE_PIPE_CSC_ENABLE)
9536 crtc_state->csc_enable = true;
9539 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9540 struct intel_crtc_state *pipe_config)
9542 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9543 enum intel_display_power_domain power_domain;
9544 intel_wakeref_t wakeref;
9548 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9549 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9553 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9554 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9555 pipe_config->shared_dpll = NULL;
9559 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9560 if (!(tmp & PIPECONF_ENABLE))
9563 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9564 IS_CHERRYVIEW(dev_priv)) {
9565 switch (tmp & PIPECONF_BPC_MASK) {
9567 pipe_config->pipe_bpp = 18;
9570 pipe_config->pipe_bpp = 24;
9572 case PIPECONF_10BPC:
9573 pipe_config->pipe_bpp = 30;
9580 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9581 (tmp & PIPECONF_COLOR_RANGE_SELECT))
9582 pipe_config->limited_color_range = true;
9584 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9585 PIPECONF_GAMMA_MODE_SHIFT;
9587 if (IS_CHERRYVIEW(dev_priv))
9588 pipe_config->cgm_mode = intel_de_read(dev_priv,
9589 CGM_PIPE_MODE(crtc->pipe));
9591 i9xx_get_pipe_color_config(pipe_config);
9592 intel_color_get_config(pipe_config);
9594 if (INTEL_GEN(dev_priv) < 4)
9595 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9597 intel_get_transcoder_timings(crtc, pipe_config);
9598 intel_get_pipe_src_size(crtc, pipe_config);
9600 i9xx_get_pfit_config(pipe_config);
9602 if (INTEL_GEN(dev_priv) >= 4) {
9603 /* No way to read it out on pipes B and C */
9604 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9605 tmp = dev_priv->chv_dpll_md[crtc->pipe];
9607 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9608 pipe_config->pixel_multiplier =
9609 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9610 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9611 pipe_config->dpll_hw_state.dpll_md = tmp;
9612 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9613 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9614 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9615 pipe_config->pixel_multiplier =
9616 ((tmp & SDVO_MULTIPLIER_MASK)
9617 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9619 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9620 * port and will be fixed up in the encoder->get_config
9622 pipe_config->pixel_multiplier = 1;
9624 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9626 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9627 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9629 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9632 /* Mask out read-only status bits. */
9633 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9634 DPLL_PORTC_READY_MASK |
9635 DPLL_PORTB_READY_MASK);
9638 if (IS_CHERRYVIEW(dev_priv))
9639 chv_crtc_clock_get(crtc, pipe_config);
9640 else if (IS_VALLEYVIEW(dev_priv))
9641 vlv_crtc_clock_get(crtc, pipe_config);
9643 i9xx_crtc_clock_get(crtc, pipe_config);
9646 * Normally the dotclock is filled in by the encoder .get_config()
9647 * but in case the pipe is enabled w/o any ports we need a sane
9650 pipe_config->hw.adjusted_mode.crtc_clock =
9651 pipe_config->port_clock / pipe_config->pixel_multiplier;
9656 intel_display_power_put(dev_priv, power_domain, wakeref);
9661 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9663 struct intel_encoder *encoder;
9666 bool has_lvds = false;
9667 bool has_cpu_edp = false;
9668 bool has_panel = false;
9669 bool has_ck505 = false;
9670 bool can_ssc = false;
9671 bool using_ssc_source = false;
9673 /* We need to take the global config into account */
9674 for_each_intel_encoder(&dev_priv->drm, encoder) {
9675 switch (encoder->type) {
9676 case INTEL_OUTPUT_LVDS:
9680 case INTEL_OUTPUT_EDP:
9682 if (encoder->port == PORT_A)
9690 if (HAS_PCH_IBX(dev_priv)) {
9691 has_ck505 = dev_priv->vbt.display_clock_mode;
9692 can_ssc = has_ck505;
9698 /* Check if any DPLLs are using the SSC source */
9699 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9700 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9702 if (!(temp & DPLL_VCO_ENABLE))
9705 if ((temp & PLL_REF_INPUT_MASK) ==
9706 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9707 using_ssc_source = true;
9712 drm_dbg_kms(&dev_priv->drm,
9713 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9714 has_panel, has_lvds, has_ck505, using_ssc_source);
9716 /* Ironlake: try to setup display ref clock before DPLL
9717 * enabling. This is only under driver's control after
9718 * PCH B stepping, previous chipset stepping should be
9719 * ignoring this setting.
9721 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9723 /* As we must carefully and slowly disable/enable each source in turn,
9724 * compute the final state we want first and check if we need to
9725 * make any changes at all.
9728 final &= ~DREF_NONSPREAD_SOURCE_MASK;
9730 final |= DREF_NONSPREAD_CK505_ENABLE;
9732 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9734 final &= ~DREF_SSC_SOURCE_MASK;
9735 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9736 final &= ~DREF_SSC1_ENABLE;
9739 final |= DREF_SSC_SOURCE_ENABLE;
9741 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9742 final |= DREF_SSC1_ENABLE;
9745 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9746 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9748 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9750 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9751 } else if (using_ssc_source) {
9752 final |= DREF_SSC_SOURCE_ENABLE;
9753 final |= DREF_SSC1_ENABLE;
9759 /* Always enable nonspread source */
9760 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9763 val |= DREF_NONSPREAD_CK505_ENABLE;
9765 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9768 val &= ~DREF_SSC_SOURCE_MASK;
9769 val |= DREF_SSC_SOURCE_ENABLE;
9771 /* SSC must be turned on before enabling the CPU output */
9772 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9773 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9774 val |= DREF_SSC1_ENABLE;
9776 val &= ~DREF_SSC1_ENABLE;
9778 /* Get SSC going before enabling the outputs */
9779 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9780 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9783 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9785 /* Enable CPU source on CPU attached eDP */
9787 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9788 drm_dbg_kms(&dev_priv->drm,
9789 "Using SSC on eDP\n");
9790 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9792 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9794 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9796 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9797 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9800 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9802 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9804 /* Turn off CPU output */
9805 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9807 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9808 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9811 if (!using_ssc_source) {
9812 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9814 /* Turn off the SSC source */
9815 val &= ~DREF_SSC_SOURCE_MASK;
9816 val |= DREF_SSC_SOURCE_DISABLE;
9819 val &= ~DREF_SSC1_ENABLE;
9821 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9822 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9827 BUG_ON(val != final);
9830 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9834 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9835 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9836 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9838 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9839 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9840 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9842 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9843 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9844 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9846 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9847 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9848 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9851 /* WaMPhyProgramming:hsw */
9852 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9856 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9857 tmp &= ~(0xFF << 24);
9858 tmp |= (0x12 << 24);
9859 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9861 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9863 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9865 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9867 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9869 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9870 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9871 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9873 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9874 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9875 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9877 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9880 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9882 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9885 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9887 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9890 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9892 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9895 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9897 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9898 tmp &= ~(0xFF << 16);
9899 tmp |= (0x1C << 16);
9900 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9902 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9903 tmp &= ~(0xFF << 16);
9904 tmp |= (0x1C << 16);
9905 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9907 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9909 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9911 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9913 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9915 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9916 tmp &= ~(0xF << 28);
9918 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9920 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9921 tmp &= ~(0xF << 28);
9923 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9926 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9927 * Programming" based on the parameters passed:
9928 * - Sequence to enable CLKOUT_DP
9929 * - Sequence to enable CLKOUT_DP without spread
9930 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9932 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9933 bool with_spread, bool with_fdi)
9937 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9938 "FDI requires downspread\n"))
9940 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9941 with_fdi, "LP PCH doesn't have FDI\n"))
9944 mutex_lock(&dev_priv->sb_lock);
9946 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9947 tmp &= ~SBI_SSCCTL_DISABLE;
9948 tmp |= SBI_SSCCTL_PATHALT;
9949 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9954 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9955 tmp &= ~SBI_SSCCTL_PATHALT;
9956 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9959 lpt_reset_fdi_mphy(dev_priv);
9960 lpt_program_fdi_mphy(dev_priv);
9964 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9965 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9966 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9967 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9969 mutex_unlock(&dev_priv->sb_lock);
9972 /* Sequence to disable CLKOUT_DP */
9973 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9977 mutex_lock(&dev_priv->sb_lock);
9979 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9980 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9981 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9982 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9984 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9985 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9986 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9987 tmp |= SBI_SSCCTL_PATHALT;
9988 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9991 tmp |= SBI_SSCCTL_DISABLE;
9992 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9995 mutex_unlock(&dev_priv->sb_lock);
9998 #define BEND_IDX(steps) ((50 + (steps)) / 5)
10000 static const u16 sscdivintphase[] = {
10001 [BEND_IDX( 50)] = 0x3B23,
10002 [BEND_IDX( 45)] = 0x3B23,
10003 [BEND_IDX( 40)] = 0x3C23,
10004 [BEND_IDX( 35)] = 0x3C23,
10005 [BEND_IDX( 30)] = 0x3D23,
10006 [BEND_IDX( 25)] = 0x3D23,
10007 [BEND_IDX( 20)] = 0x3E23,
10008 [BEND_IDX( 15)] = 0x3E23,
10009 [BEND_IDX( 10)] = 0x3F23,
10010 [BEND_IDX( 5)] = 0x3F23,
10011 [BEND_IDX( 0)] = 0x0025,
10012 [BEND_IDX( -5)] = 0x0025,
10013 [BEND_IDX(-10)] = 0x0125,
10014 [BEND_IDX(-15)] = 0x0125,
10015 [BEND_IDX(-20)] = 0x0225,
10016 [BEND_IDX(-25)] = 0x0225,
10017 [BEND_IDX(-30)] = 0x0325,
10018 [BEND_IDX(-35)] = 0x0325,
10019 [BEND_IDX(-40)] = 0x0425,
10020 [BEND_IDX(-45)] = 0x0425,
10021 [BEND_IDX(-50)] = 0x0525,
10026 * steps -50 to 50 inclusive, in steps of 5
10027 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
10028 * change in clock period = -(steps / 10) * 5.787 ps
10030 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
10033 int idx = BEND_IDX(steps);
10035 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
10038 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
10041 mutex_lock(&dev_priv->sb_lock);
10043 if (steps % 10 != 0)
10047 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
10049 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
10051 tmp |= sscdivintphase[idx];
10052 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
10054 mutex_unlock(&dev_priv->sb_lock);
10059 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
10061 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10062 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
10064 if ((ctl & SPLL_PLL_ENABLE) == 0)
10067 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
10068 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10071 if (IS_BROADWELL(dev_priv) &&
10072 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
10078 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
10079 enum intel_dpll_id id)
10081 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
10082 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
10084 if ((ctl & WRPLL_PLL_ENABLE) == 0)
10087 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
10090 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
10091 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
10092 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
10098 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
10100 struct intel_encoder *encoder;
10101 bool has_fdi = false;
10103 for_each_intel_encoder(&dev_priv->drm, encoder) {
10104 switch (encoder->type) {
10105 case INTEL_OUTPUT_ANALOG:
10114 * The BIOS may have decided to use the PCH SSC
10115 * reference so we must not disable it until the
10116 * relevant PLLs have stopped relying on it. We'll
10117 * just leave the PCH SSC reference enabled in case
10118 * any active PLL is using it. It will get disabled
10119 * after runtime suspend if we don't have FDI.
10121 * TODO: Move the whole reference clock handling
10122 * to the modeset sequence proper so that we can
10123 * actually enable/disable/reconfigure these things
10124 * safely. To do that we need to introduce a real
10125 * clock hierarchy. That would also allow us to do
10126 * clock bending finally.
10128 dev_priv->pch_ssc_use = 0;
10130 if (spll_uses_pch_ssc(dev_priv)) {
10131 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
10132 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
10135 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
10136 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
10137 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
10140 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
10141 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
10142 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
10145 if (dev_priv->pch_ssc_use)
10149 lpt_bend_clkout_dp(dev_priv, 0);
10150 lpt_enable_clkout_dp(dev_priv, true, true);
10152 lpt_disable_clkout_dp(dev_priv);
10157 * Initialize reference clocks when the driver loads
10159 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10161 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10162 ilk_init_pch_refclk(dev_priv);
10163 else if (HAS_PCH_LPT(dev_priv))
10164 lpt_init_pch_refclk(dev_priv);
10167 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10169 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10170 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10171 enum pipe pipe = crtc->pipe;
10176 switch (crtc_state->pipe_bpp) {
10178 val |= PIPECONF_6BPC;
10181 val |= PIPECONF_8BPC;
10184 val |= PIPECONF_10BPC;
10187 val |= PIPECONF_12BPC;
10190 /* Case prevented by intel_choose_pipe_bpp_dither. */
10194 if (crtc_state->dither)
10195 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10197 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10198 val |= PIPECONF_INTERLACED_ILK;
10200 val |= PIPECONF_PROGRESSIVE;
10203 * This would end up with an odd purple hue over
10204 * the entire display. Make sure we don't do it.
10206 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10207 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10209 if (crtc_state->limited_color_range &&
10210 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
10211 val |= PIPECONF_COLOR_RANGE_SELECT;
10213 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10214 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10216 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10218 val |= PIPECONF_FRAME_START_DELAY(0);
10220 intel_de_write(dev_priv, PIPECONF(pipe), val);
10221 intel_de_posting_read(dev_priv, PIPECONF(pipe));
10224 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10226 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10227 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10228 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10231 if (IS_HASWELL(dev_priv) && crtc_state->dither)
10232 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10234 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10235 val |= PIPECONF_INTERLACED_ILK;
10237 val |= PIPECONF_PROGRESSIVE;
10239 if (IS_HASWELL(dev_priv) &&
10240 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10241 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10243 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10244 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10247 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10249 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10250 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10253 switch (crtc_state->pipe_bpp) {
10255 val |= PIPEMISC_DITHER_6_BPC;
10258 val |= PIPEMISC_DITHER_8_BPC;
10261 val |= PIPEMISC_DITHER_10_BPC;
10264 val |= PIPEMISC_DITHER_12_BPC;
10267 MISSING_CASE(crtc_state->pipe_bpp);
10271 if (crtc_state->dither)
10272 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10274 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10275 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10276 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10278 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10279 val |= PIPEMISC_YUV420_ENABLE |
10280 PIPEMISC_YUV420_MODE_FULL_BLEND;
10282 if (INTEL_GEN(dev_priv) >= 11 &&
10283 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10284 BIT(PLANE_CURSOR))) == 0)
10285 val |= PIPEMISC_HDR_MODE_PRECISION;
10287 if (INTEL_GEN(dev_priv) >= 12)
10288 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10290 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10293 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10295 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10298 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10300 switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10301 case PIPEMISC_DITHER_6_BPC:
10303 case PIPEMISC_DITHER_8_BPC:
10305 case PIPEMISC_DITHER_10_BPC:
10307 case PIPEMISC_DITHER_12_BPC:
10315 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10318 * Account for spread spectrum to avoid
10319 * oversubscribing the link. Max center spread
10320 * is 2.5%; use 5% for safety's sake.
10322 u32 bps = target_clock * bpp * 21 / 20;
10323 return DIV_ROUND_UP(bps, link_bw * 8);
10326 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10328 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10331 static void ilk_compute_dpll(struct intel_crtc *crtc,
10332 struct intel_crtc_state *crtc_state,
10333 struct dpll *reduced_clock)
10335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10339 /* Enable autotuning of the PLL clock (if permissible) */
10341 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10342 if ((intel_panel_use_ssc(dev_priv) &&
10343 dev_priv->vbt.lvds_ssc_freq == 100000) ||
10344 (HAS_PCH_IBX(dev_priv) &&
10345 intel_is_dual_link_lvds(dev_priv)))
10347 } else if (crtc_state->sdvo_tv_clock) {
10351 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10353 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10356 if (reduced_clock) {
10357 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10359 if (reduced_clock->m < factor * reduced_clock->n)
10367 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10368 dpll |= DPLLB_MODE_LVDS;
10370 dpll |= DPLLB_MODE_DAC_SERIAL;
10372 dpll |= (crtc_state->pixel_multiplier - 1)
10373 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10375 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10376 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10377 dpll |= DPLL_SDVO_HIGH_SPEED;
10379 if (intel_crtc_has_dp_encoder(crtc_state))
10380 dpll |= DPLL_SDVO_HIGH_SPEED;
10383 * The high speed IO clock is only really required for
10384 * SDVO/HDMI/DP, but we also enable it for CRT to make it
10385 * possible to share the DPLL between CRT and HDMI. Enabling
10386 * the clock needlessly does no real harm, except use up a
10387 * bit of power potentially.
10389 * We'll limit this to IVB with 3 pipes, since it has only two
10390 * DPLLs and so DPLL sharing is the only way to get three pipes
10391 * driving PCH ports at the same time. On SNB we could do this,
10392 * and potentially avoid enabling the second DPLL, but it's not
10393 * clear if it''s a win or loss power wise. No point in doing
10394 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10396 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10397 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10398 dpll |= DPLL_SDVO_HIGH_SPEED;
10400 /* compute bitmask from p1 value */
10401 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10403 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10405 switch (crtc_state->dpll.p2) {
10407 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10410 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10413 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10416 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10420 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10421 intel_panel_use_ssc(dev_priv))
10422 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10424 dpll |= PLL_REF_INPUT_DREFCLK;
10426 dpll |= DPLL_VCO_ENABLE;
10428 crtc_state->dpll_hw_state.dpll = dpll;
10429 crtc_state->dpll_hw_state.fp0 = fp;
10430 crtc_state->dpll_hw_state.fp1 = fp2;
10433 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10434 struct intel_crtc_state *crtc_state)
10436 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10437 struct intel_atomic_state *state =
10438 to_intel_atomic_state(crtc_state->uapi.state);
10439 const struct intel_limit *limit;
10440 int refclk = 120000;
10442 memset(&crtc_state->dpll_hw_state, 0,
10443 sizeof(crtc_state->dpll_hw_state));
10445 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10446 if (!crtc_state->has_pch_encoder)
10449 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10450 if (intel_panel_use_ssc(dev_priv)) {
10451 drm_dbg_kms(&dev_priv->drm,
10452 "using SSC reference clock of %d kHz\n",
10453 dev_priv->vbt.lvds_ssc_freq);
10454 refclk = dev_priv->vbt.lvds_ssc_freq;
10457 if (intel_is_dual_link_lvds(dev_priv)) {
10458 if (refclk == 100000)
10459 limit = &ilk_limits_dual_lvds_100m;
10461 limit = &ilk_limits_dual_lvds;
10463 if (refclk == 100000)
10464 limit = &ilk_limits_single_lvds_100m;
10466 limit = &ilk_limits_single_lvds;
10469 limit = &ilk_limits_dac;
10472 if (!crtc_state->clock_set &&
10473 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10474 refclk, NULL, &crtc_state->dpll)) {
10475 drm_err(&dev_priv->drm,
10476 "Couldn't find PLL settings for mode!\n");
10480 ilk_compute_dpll(crtc, crtc_state, NULL);
10482 if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10483 drm_dbg_kms(&dev_priv->drm,
10484 "failed to find PLL for pipe %c\n",
10485 pipe_name(crtc->pipe));
10492 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10493 struct intel_link_m_n *m_n)
10495 struct drm_device *dev = crtc->base.dev;
10496 struct drm_i915_private *dev_priv = to_i915(dev);
10497 enum pipe pipe = crtc->pipe;
10499 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10500 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10501 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10503 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10504 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10505 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10508 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10509 enum transcoder transcoder,
10510 struct intel_link_m_n *m_n,
10511 struct intel_link_m_n *m2_n2)
10513 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10514 enum pipe pipe = crtc->pipe;
10516 if (INTEL_GEN(dev_priv) >= 5) {
10517 m_n->link_m = intel_de_read(dev_priv,
10518 PIPE_LINK_M1(transcoder));
10519 m_n->link_n = intel_de_read(dev_priv,
10520 PIPE_LINK_N1(transcoder));
10521 m_n->gmch_m = intel_de_read(dev_priv,
10522 PIPE_DATA_M1(transcoder))
10524 m_n->gmch_n = intel_de_read(dev_priv,
10525 PIPE_DATA_N1(transcoder));
10526 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10527 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10529 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10530 m2_n2->link_m = intel_de_read(dev_priv,
10531 PIPE_LINK_M2(transcoder));
10532 m2_n2->link_n = intel_de_read(dev_priv,
10533 PIPE_LINK_N2(transcoder));
10534 m2_n2->gmch_m = intel_de_read(dev_priv,
10535 PIPE_DATA_M2(transcoder))
10537 m2_n2->gmch_n = intel_de_read(dev_priv,
10538 PIPE_DATA_N2(transcoder));
10539 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10540 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10543 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10544 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10545 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10547 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10548 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10549 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10553 void intel_dp_get_m_n(struct intel_crtc *crtc,
10554 struct intel_crtc_state *pipe_config)
10556 if (pipe_config->has_pch_encoder)
10557 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10559 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10560 &pipe_config->dp_m_n,
10561 &pipe_config->dp_m2_n2);
10564 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10565 struct intel_crtc_state *pipe_config)
10567 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10568 &pipe_config->fdi_m_n, NULL);
10571 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
10574 drm_rect_init(&crtc_state->pch_pfit.dst,
10575 pos >> 16, pos & 0xffff,
10576 size >> 16, size & 0xffff);
10579 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
10581 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10582 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10583 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
10587 /* find scaler attached to this pipe */
10588 for (i = 0; i < crtc->num_scalers; i++) {
10589 u32 ctl, pos, size;
10591 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10592 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
10596 crtc_state->pch_pfit.enabled = true;
10598 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
10599 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
10601 ilk_get_pfit_pos_size(crtc_state, pos, size);
10603 scaler_state->scalers[i].in_use = true;
10607 scaler_state->scaler_id = id;
10609 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10611 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10615 skl_get_initial_plane_config(struct intel_crtc *crtc,
10616 struct intel_initial_plane_config *plane_config)
10618 struct drm_device *dev = crtc->base.dev;
10619 struct drm_i915_private *dev_priv = to_i915(dev);
10620 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10621 enum plane_id plane_id = plane->id;
10623 u32 val, base, offset, stride_mult, tiling, alpha;
10624 int fourcc, pixel_format;
10625 unsigned int aligned_height;
10626 struct drm_framebuffer *fb;
10627 struct intel_framebuffer *intel_fb;
10629 if (!plane->get_hw_state(plane, &pipe))
10632 drm_WARN_ON(dev, pipe != crtc->pipe);
10634 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10636 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10640 fb = &intel_fb->base;
10644 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10646 if (INTEL_GEN(dev_priv) >= 11)
10647 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10649 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10651 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10652 alpha = intel_de_read(dev_priv,
10653 PLANE_COLOR_CTL(pipe, plane_id));
10654 alpha &= PLANE_COLOR_ALPHA_MASK;
10656 alpha = val & PLANE_CTL_ALPHA_MASK;
10659 fourcc = skl_format_to_fourcc(pixel_format,
10660 val & PLANE_CTL_ORDER_RGBX, alpha);
10661 fb->format = drm_format_info(fourcc);
10663 tiling = val & PLANE_CTL_TILED_MASK;
10665 case PLANE_CTL_TILED_LINEAR:
10666 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10668 case PLANE_CTL_TILED_X:
10669 plane_config->tiling = I915_TILING_X;
10670 fb->modifier = I915_FORMAT_MOD_X_TILED;
10672 case PLANE_CTL_TILED_Y:
10673 plane_config->tiling = I915_TILING_Y;
10674 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10675 fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10676 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10677 I915_FORMAT_MOD_Y_TILED_CCS;
10678 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10679 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10681 fb->modifier = I915_FORMAT_MOD_Y_TILED;
10683 case PLANE_CTL_TILED_YF:
10684 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10685 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10687 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10690 MISSING_CASE(tiling);
10695 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10696 * while i915 HW rotation is clockwise, thats why this swapping.
10698 switch (val & PLANE_CTL_ROTATE_MASK) {
10699 case PLANE_CTL_ROTATE_0:
10700 plane_config->rotation = DRM_MODE_ROTATE_0;
10702 case PLANE_CTL_ROTATE_90:
10703 plane_config->rotation = DRM_MODE_ROTATE_270;
10705 case PLANE_CTL_ROTATE_180:
10706 plane_config->rotation = DRM_MODE_ROTATE_180;
10708 case PLANE_CTL_ROTATE_270:
10709 plane_config->rotation = DRM_MODE_ROTATE_90;
10713 if (INTEL_GEN(dev_priv) >= 10 &&
10714 val & PLANE_CTL_FLIP_HORIZONTAL)
10715 plane_config->rotation |= DRM_MODE_REFLECT_X;
10717 /* 90/270 degree rotation would require extra work */
10718 if (drm_rotation_90_or_270(plane_config->rotation))
10721 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10722 plane_config->base = base;
10724 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10726 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10727 fb->height = ((val >> 16) & 0xffff) + 1;
10728 fb->width = ((val >> 0) & 0xffff) + 1;
10730 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10731 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10732 fb->pitches[0] = (val & 0x3ff) * stride_mult;
10734 aligned_height = intel_fb_align_height(fb, 0, fb->height);
10736 plane_config->size = fb->pitches[0] * aligned_height;
10738 drm_dbg_kms(&dev_priv->drm,
10739 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10740 crtc->base.name, plane->base.name, fb->width, fb->height,
10741 fb->format->cpp[0] * 8, base, fb->pitches[0],
10742 plane_config->size);
10744 plane_config->fb = intel_fb;
10751 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
10753 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10755 u32 ctl, pos, size;
10757 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10758 if ((ctl & PF_ENABLE) == 0)
10761 crtc_state->pch_pfit.enabled = true;
10763 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
10764 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
10766 ilk_get_pfit_pos_size(crtc_state, pos, size);
10769 * We currently do not free assignements of panel fitters on
10770 * ivb/hsw (since we don't use the higher upscaling modes which
10771 * differentiates them) so just WARN about this case for now.
10773 drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&
10774 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
10777 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10778 struct intel_crtc_state *pipe_config)
10780 struct drm_device *dev = crtc->base.dev;
10781 struct drm_i915_private *dev_priv = to_i915(dev);
10782 enum intel_display_power_domain power_domain;
10783 intel_wakeref_t wakeref;
10787 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10788 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10792 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10793 pipe_config->shared_dpll = NULL;
10796 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10797 if (!(tmp & PIPECONF_ENABLE))
10800 switch (tmp & PIPECONF_BPC_MASK) {
10801 case PIPECONF_6BPC:
10802 pipe_config->pipe_bpp = 18;
10804 case PIPECONF_8BPC:
10805 pipe_config->pipe_bpp = 24;
10807 case PIPECONF_10BPC:
10808 pipe_config->pipe_bpp = 30;
10810 case PIPECONF_12BPC:
10811 pipe_config->pipe_bpp = 36;
10817 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10818 pipe_config->limited_color_range = true;
10820 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10821 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10822 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10823 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10826 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10830 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10831 PIPECONF_GAMMA_MODE_SHIFT;
10833 pipe_config->csc_mode = intel_de_read(dev_priv,
10834 PIPE_CSC_MODE(crtc->pipe));
10836 i9xx_get_pipe_color_config(pipe_config);
10837 intel_color_get_config(pipe_config);
10839 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10840 struct intel_shared_dpll *pll;
10841 enum intel_dpll_id pll_id;
10843 pipe_config->has_pch_encoder = true;
10845 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10846 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10847 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10849 ilk_get_fdi_m_n_config(crtc, pipe_config);
10851 if (HAS_PCH_IBX(dev_priv)) {
10853 * The pipe->pch transcoder and pch transcoder->pll
10854 * mapping is fixed.
10856 pll_id = (enum intel_dpll_id) crtc->pipe;
10858 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10859 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10860 pll_id = DPLL_ID_PCH_PLL_B;
10862 pll_id= DPLL_ID_PCH_PLL_A;
10865 pipe_config->shared_dpll =
10866 intel_get_shared_dpll_by_id(dev_priv, pll_id);
10867 pll = pipe_config->shared_dpll;
10869 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10870 &pipe_config->dpll_hw_state));
10872 tmp = pipe_config->dpll_hw_state.dpll;
10873 pipe_config->pixel_multiplier =
10874 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10875 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10877 ilk_pch_clock_get(crtc, pipe_config);
10879 pipe_config->pixel_multiplier = 1;
10882 intel_get_transcoder_timings(crtc, pipe_config);
10883 intel_get_pipe_src_size(crtc, pipe_config);
10885 ilk_get_pfit_config(pipe_config);
10890 intel_display_power_put(dev_priv, power_domain, wakeref);
10895 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10896 struct intel_crtc_state *crtc_state)
10898 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10899 struct intel_atomic_state *state =
10900 to_intel_atomic_state(crtc_state->uapi.state);
10902 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10903 INTEL_GEN(dev_priv) >= 11) {
10904 struct intel_encoder *encoder =
10905 intel_get_crtc_new_encoder(state, crtc_state);
10907 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10908 drm_dbg_kms(&dev_priv->drm,
10909 "failed to find PLL for pipe %c\n",
10910 pipe_name(crtc->pipe));
10918 static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10919 struct intel_crtc_state *pipe_config)
10921 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10922 enum phy phy = intel_port_to_phy(dev_priv, port);
10923 enum intel_dpll_id id;
10926 clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10927 id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy);
10929 if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
10932 pipe_config->icl_port_dplls[port_dpll_id].pll =
10933 intel_get_shared_dpll_by_id(dev_priv, id);
10935 icl_set_active_port_dpll(pipe_config, port_dpll_id);
10938 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10939 struct intel_crtc_state *pipe_config)
10941 enum intel_dpll_id id;
10944 temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10945 id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10947 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10950 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10953 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10954 struct intel_crtc_state *pipe_config)
10956 enum phy phy = intel_port_to_phy(dev_priv, port);
10957 enum icl_port_dpll_id port_dpll_id;
10958 enum intel_dpll_id id;
10961 if (intel_phy_is_combo(dev_priv, phy)) {
10964 if (IS_ROCKETLAKE(dev_priv)) {
10965 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10966 shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10968 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10969 shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10972 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
10973 id = temp >> shift;
10974 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10975 } else if (intel_phy_is_tc(dev_priv, phy)) {
10976 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10978 if (clk_sel == DDI_CLK_SEL_MG) {
10979 id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10981 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10983 drm_WARN_ON(&dev_priv->drm,
10984 clk_sel < DDI_CLK_SEL_TBT_162);
10985 id = DPLL_ID_ICL_TBTPLL;
10986 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10989 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10993 pipe_config->icl_port_dplls[port_dpll_id].pll =
10994 intel_get_shared_dpll_by_id(dev_priv, id);
10996 icl_set_active_port_dpll(pipe_config, port_dpll_id);
10999 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
11001 struct intel_crtc_state *pipe_config)
11003 enum intel_dpll_id id;
11007 id = DPLL_ID_SKL_DPLL0;
11010 id = DPLL_ID_SKL_DPLL1;
11013 id = DPLL_ID_SKL_DPLL2;
11016 drm_err(&dev_priv->drm, "Incorrect port type\n");
11020 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11023 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11024 struct intel_crtc_state *pipe_config)
11026 enum intel_dpll_id id;
11029 temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
11030 id = temp >> (port * 3 + 1);
11032 if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
11035 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11038 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
11039 struct intel_crtc_state *pipe_config)
11041 enum intel_dpll_id id;
11042 u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
11044 switch (ddi_pll_sel) {
11045 case PORT_CLK_SEL_WRPLL1:
11046 id = DPLL_ID_WRPLL1;
11048 case PORT_CLK_SEL_WRPLL2:
11049 id = DPLL_ID_WRPLL2;
11051 case PORT_CLK_SEL_SPLL:
11054 case PORT_CLK_SEL_LCPLL_810:
11055 id = DPLL_ID_LCPLL_810;
11057 case PORT_CLK_SEL_LCPLL_1350:
11058 id = DPLL_ID_LCPLL_1350;
11060 case PORT_CLK_SEL_LCPLL_2700:
11061 id = DPLL_ID_LCPLL_2700;
11064 MISSING_CASE(ddi_pll_sel);
11066 case PORT_CLK_SEL_NONE:
11070 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
11073 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
11074 struct intel_crtc_state *pipe_config,
11075 u64 *power_domain_mask,
11076 intel_wakeref_t *wakerefs)
11078 struct drm_device *dev = crtc->base.dev;
11079 struct drm_i915_private *dev_priv = to_i915(dev);
11080 enum intel_display_power_domain power_domain;
11081 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
11082 unsigned long enabled_panel_transcoders = 0;
11083 enum transcoder panel_transcoder;
11084 intel_wakeref_t wf;
11087 if (INTEL_GEN(dev_priv) >= 11)
11088 panel_transcoder_mask |=
11089 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
11092 * The pipe->transcoder mapping is fixed with the exception of the eDP
11093 * and DSI transcoders handled below.
11095 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
11098 * XXX: Do intel_display_power_get_if_enabled before reading this (for
11099 * consistency and less surprising code; it's in always on power).
11101 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
11102 panel_transcoder_mask) {
11103 bool force_thru = false;
11104 enum pipe trans_pipe;
11106 tmp = intel_de_read(dev_priv,
11107 TRANS_DDI_FUNC_CTL(panel_transcoder));
11108 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
11112 * Log all enabled ones, only use the first one.
11114 * FIXME: This won't work for two separate DSI displays.
11116 enabled_panel_transcoders |= BIT(panel_transcoder);
11117 if (enabled_panel_transcoders != BIT(panel_transcoder))
11120 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
11123 "unknown pipe linked to transcoder %s\n",
11124 transcoder_name(panel_transcoder));
11126 case TRANS_DDI_EDP_INPUT_A_ONOFF:
11129 case TRANS_DDI_EDP_INPUT_A_ON:
11130 trans_pipe = PIPE_A;
11132 case TRANS_DDI_EDP_INPUT_B_ONOFF:
11133 trans_pipe = PIPE_B;
11135 case TRANS_DDI_EDP_INPUT_C_ONOFF:
11136 trans_pipe = PIPE_C;
11138 case TRANS_DDI_EDP_INPUT_D_ONOFF:
11139 trans_pipe = PIPE_D;
11143 if (trans_pipe == crtc->pipe) {
11144 pipe_config->cpu_transcoder = panel_transcoder;
11145 pipe_config->pch_pfit.force_thru = force_thru;
11150 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
11152 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
11153 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
11155 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
11156 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11158 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11162 wakerefs[power_domain] = wf;
11163 *power_domain_mask |= BIT_ULL(power_domain);
11165 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
11167 return tmp & PIPECONF_ENABLE;
11170 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
11171 struct intel_crtc_state *pipe_config,
11172 u64 *power_domain_mask,
11173 intel_wakeref_t *wakerefs)
11175 struct drm_device *dev = crtc->base.dev;
11176 struct drm_i915_private *dev_priv = to_i915(dev);
11177 enum intel_display_power_domain power_domain;
11178 enum transcoder cpu_transcoder;
11179 intel_wakeref_t wf;
11183 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
11184 if (port == PORT_A)
11185 cpu_transcoder = TRANSCODER_DSI_A;
11187 cpu_transcoder = TRANSCODER_DSI_C;
11189 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11190 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
11192 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11196 wakerefs[power_domain] = wf;
11197 *power_domain_mask |= BIT_ULL(power_domain);
11200 * The PLL needs to be enabled with a valid divider
11201 * configuration, otherwise accessing DSI registers will hang
11202 * the machine. See BSpec North Display Engine
11203 * registers/MIPI[BXT]. We can break out here early, since we
11204 * need the same DSI PLL to be enabled for both DSI ports.
11206 if (!bxt_dsi_pll_is_enabled(dev_priv))
11209 /* XXX: this works for video mode only */
11210 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11211 if (!(tmp & DPI_ENABLE))
11214 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11215 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11218 pipe_config->cpu_transcoder = cpu_transcoder;
11222 return transcoder_is_dsi(pipe_config->cpu_transcoder);
11225 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11226 struct intel_crtc_state *pipe_config)
11228 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11229 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11230 struct intel_shared_dpll *pll;
11234 if (transcoder_is_dsi(cpu_transcoder)) {
11235 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11238 tmp = intel_de_read(dev_priv,
11239 TRANS_DDI_FUNC_CTL(cpu_transcoder));
11240 if (INTEL_GEN(dev_priv) >= 12)
11241 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11243 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11246 if (IS_DG1(dev_priv))
11247 dg1_get_ddi_pll(dev_priv, port, pipe_config);
11248 else if (INTEL_GEN(dev_priv) >= 11)
11249 icl_get_ddi_pll(dev_priv, port, pipe_config);
11250 else if (IS_CANNONLAKE(dev_priv))
11251 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11252 else if (IS_GEN9_BC(dev_priv))
11253 skl_get_ddi_pll(dev_priv, port, pipe_config);
11254 else if (IS_GEN9_LP(dev_priv))
11255 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11257 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11259 pll = pipe_config->shared_dpll;
11261 drm_WARN_ON(&dev_priv->drm,
11262 !pll->info->funcs->get_hw_state(dev_priv, pll,
11263 &pipe_config->dpll_hw_state));
11267 * Haswell has only FDI/PCH transcoder A. It is which is connected to
11268 * DDI E. So just check whether this pipe is wired to DDI E and whether
11269 * the PCH transcoder is on.
11271 if (INTEL_GEN(dev_priv) < 9 &&
11272 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11273 pipe_config->has_pch_encoder = true;
11275 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11276 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11277 FDI_DP_PORT_WIDTH_SHIFT) + 1;
11279 ilk_get_fdi_m_n_config(crtc, pipe_config);
11283 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11284 struct intel_crtc_state *pipe_config)
11286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11287 intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11288 enum intel_display_power_domain power_domain;
11289 u64 power_domain_mask;
11293 pipe_config->master_transcoder = INVALID_TRANSCODER;
11295 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11296 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11300 wakerefs[power_domain] = wf;
11301 power_domain_mask = BIT_ULL(power_domain);
11303 pipe_config->shared_dpll = NULL;
11305 active = hsw_get_transcoder_state(crtc, pipe_config,
11306 &power_domain_mask, wakerefs);
11308 if (IS_GEN9_LP(dev_priv) &&
11309 bxt_get_dsi_transcoder_state(crtc, pipe_config,
11310 &power_domain_mask, wakerefs)) {
11311 drm_WARN_ON(&dev_priv->drm, active);
11318 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11319 INTEL_GEN(dev_priv) >= 11) {
11320 hsw_get_ddi_port_state(crtc, pipe_config);
11321 intel_get_transcoder_timings(crtc, pipe_config);
11324 intel_get_pipe_src_size(crtc, pipe_config);
11326 if (IS_HASWELL(dev_priv)) {
11327 u32 tmp = intel_de_read(dev_priv,
11328 PIPECONF(pipe_config->cpu_transcoder));
11330 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11331 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11333 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11335 pipe_config->output_format =
11336 bdw_get_pipemisc_output_format(crtc);
11339 pipe_config->gamma_mode = intel_de_read(dev_priv,
11340 GAMMA_MODE(crtc->pipe));
11342 pipe_config->csc_mode = intel_de_read(dev_priv,
11343 PIPE_CSC_MODE(crtc->pipe));
11345 if (INTEL_GEN(dev_priv) >= 9) {
11346 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11348 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11349 pipe_config->gamma_enable = true;
11351 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11352 pipe_config->csc_enable = true;
11354 i9xx_get_pipe_color_config(pipe_config);
11357 intel_color_get_config(pipe_config);
11359 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11360 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11361 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11362 pipe_config->ips_linetime =
11363 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11365 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11366 drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11368 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11370 wakerefs[power_domain] = wf;
11371 power_domain_mask |= BIT_ULL(power_domain);
11373 if (INTEL_GEN(dev_priv) >= 9)
11374 skl_get_pfit_config(pipe_config);
11376 ilk_get_pfit_config(pipe_config);
11379 if (hsw_crtc_supports_ips(crtc)) {
11380 if (IS_HASWELL(dev_priv))
11381 pipe_config->ips_enabled = intel_de_read(dev_priv,
11382 IPS_CTL) & IPS_ENABLE;
11385 * We cannot readout IPS state on broadwell, set to
11386 * true so we can set it to a defined state on first
11389 pipe_config->ips_enabled = true;
11393 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11394 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11395 pipe_config->pixel_multiplier =
11396 intel_de_read(dev_priv,
11397 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11399 pipe_config->pixel_multiplier = 1;
11403 for_each_power_domain(power_domain, power_domain_mask)
11404 intel_display_power_put(dev_priv,
11405 power_domain, wakerefs[power_domain]);
11410 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
11412 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11413 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
11415 if (!i915->display.get_pipe_config(crtc, crtc_state))
11418 crtc_state->hw.active = true;
11423 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11425 struct drm_i915_private *dev_priv =
11426 to_i915(plane_state->uapi.plane->dev);
11427 const struct drm_framebuffer *fb = plane_state->hw.fb;
11428 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11431 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11432 base = sg_dma_address(obj->mm.pages->sgl);
11434 base = intel_plane_ggtt_offset(plane_state);
11436 return base + plane_state->color_plane[0].offset;
11439 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11441 int x = plane_state->uapi.dst.x1;
11442 int y = plane_state->uapi.dst.y1;
11446 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11449 pos |= x << CURSOR_X_SHIFT;
11452 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11455 pos |= y << CURSOR_Y_SHIFT;
11460 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11462 const struct drm_mode_config *config =
11463 &plane_state->uapi.plane->dev->mode_config;
11464 int width = drm_rect_width(&plane_state->uapi.dst);
11465 int height = drm_rect_height(&plane_state->uapi.dst);
11467 return width > 0 && width <= config->cursor_width &&
11468 height > 0 && height <= config->cursor_height;
11471 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11473 struct drm_i915_private *dev_priv =
11474 to_i915(plane_state->uapi.plane->dev);
11475 unsigned int rotation = plane_state->hw.rotation;
11480 ret = intel_plane_compute_gtt(plane_state);
11484 if (!plane_state->uapi.visible)
11487 src_x = plane_state->uapi.src.x1 >> 16;
11488 src_y = plane_state->uapi.src.y1 >> 16;
11490 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11491 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11494 if (src_x != 0 || src_y != 0) {
11495 drm_dbg_kms(&dev_priv->drm,
11496 "Arbitrary cursor panning not supported\n");
11501 * Put the final coordinates back so that the src
11502 * coordinate checks will see the right values.
11504 drm_rect_translate_to(&plane_state->uapi.src,
11505 src_x << 16, src_y << 16);
11507 /* ILK+ do this automagically in hardware */
11508 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11509 const struct drm_framebuffer *fb = plane_state->hw.fb;
11510 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11511 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11513 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11516 plane_state->color_plane[0].offset = offset;
11517 plane_state->color_plane[0].x = src_x;
11518 plane_state->color_plane[0].y = src_y;
11523 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11524 struct intel_plane_state *plane_state)
11526 const struct drm_framebuffer *fb = plane_state->hw.fb;
11527 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11530 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11531 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11535 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11537 DRM_PLANE_HELPER_NO_SCALING,
11538 DRM_PLANE_HELPER_NO_SCALING,
11543 /* Use the unclipped src/dst rectangles, which we program to hw */
11544 plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11545 plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11547 ret = intel_cursor_check_surface(plane_state);
11551 if (!plane_state->uapi.visible)
11554 ret = intel_plane_check_src_coordinates(plane_state);
11561 static unsigned int
11562 i845_cursor_max_stride(struct intel_plane *plane,
11563 u32 pixel_format, u64 modifier,
11564 unsigned int rotation)
11569 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11573 if (crtc_state->gamma_enable)
11574 cntl |= CURSOR_GAMMA_ENABLE;
11579 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11580 const struct intel_plane_state *plane_state)
11582 return CURSOR_ENABLE |
11583 CURSOR_FORMAT_ARGB |
11584 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11587 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11589 int width = drm_rect_width(&plane_state->uapi.dst);
11592 * 845g/865g are only limited by the width of their cursors,
11593 * the height is arbitrary up to the precision of the register.
11595 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11598 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11599 struct intel_plane_state *plane_state)
11601 const struct drm_framebuffer *fb = plane_state->hw.fb;
11602 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11605 ret = intel_check_cursor(crtc_state, plane_state);
11609 /* if we want to turn off the cursor ignore width and height */
11613 /* Check for which cursor types we support */
11614 if (!i845_cursor_size_ok(plane_state)) {
11615 drm_dbg_kms(&i915->drm,
11616 "Cursor dimension %dx%d not supported\n",
11617 drm_rect_width(&plane_state->uapi.dst),
11618 drm_rect_height(&plane_state->uapi.dst));
11622 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11623 plane_state->color_plane[0].stride != fb->pitches[0]);
11625 switch (fb->pitches[0]) {
11632 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11637 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11642 static void i845_update_cursor(struct intel_plane *plane,
11643 const struct intel_crtc_state *crtc_state,
11644 const struct intel_plane_state *plane_state)
11646 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11647 u32 cntl = 0, base = 0, pos = 0, size = 0;
11648 unsigned long irqflags;
11650 if (plane_state && plane_state->uapi.visible) {
11651 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11652 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11654 cntl = plane_state->ctl |
11655 i845_cursor_ctl_crtc(crtc_state);
11657 size = (height << 12) | width;
11659 base = intel_cursor_base(plane_state);
11660 pos = intel_cursor_position(plane_state);
11663 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11665 /* On these chipsets we can only modify the base/size/stride
11666 * whilst the cursor is disabled.
11668 if (plane->cursor.base != base ||
11669 plane->cursor.size != size ||
11670 plane->cursor.cntl != cntl) {
11671 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11672 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11673 intel_de_write_fw(dev_priv, CURSIZE, size);
11674 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11675 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11677 plane->cursor.base = base;
11678 plane->cursor.size = size;
11679 plane->cursor.cntl = cntl;
11681 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11684 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11687 static void i845_disable_cursor(struct intel_plane *plane,
11688 const struct intel_crtc_state *crtc_state)
11690 i845_update_cursor(plane, crtc_state, NULL);
11693 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11696 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11697 enum intel_display_power_domain power_domain;
11698 intel_wakeref_t wakeref;
11701 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11702 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11706 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11710 intel_display_power_put(dev_priv, power_domain, wakeref);
11715 static unsigned int
11716 i9xx_cursor_max_stride(struct intel_plane *plane,
11717 u32 pixel_format, u64 modifier,
11718 unsigned int rotation)
11720 return plane->base.dev->mode_config.cursor_width * 4;
11723 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11725 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11726 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11729 if (INTEL_GEN(dev_priv) >= 11)
11732 if (crtc_state->gamma_enable)
11733 cntl = MCURSOR_GAMMA_ENABLE;
11735 if (crtc_state->csc_enable)
11736 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11738 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11739 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11744 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11745 const struct intel_plane_state *plane_state)
11747 struct drm_i915_private *dev_priv =
11748 to_i915(plane_state->uapi.plane->dev);
11751 if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11752 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11754 switch (drm_rect_width(&plane_state->uapi.dst)) {
11756 cntl |= MCURSOR_MODE_64_ARGB_AX;
11759 cntl |= MCURSOR_MODE_128_ARGB_AX;
11762 cntl |= MCURSOR_MODE_256_ARGB_AX;
11765 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11769 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11770 cntl |= MCURSOR_ROTATE_180;
11775 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11777 struct drm_i915_private *dev_priv =
11778 to_i915(plane_state->uapi.plane->dev);
11779 int width = drm_rect_width(&plane_state->uapi.dst);
11780 int height = drm_rect_height(&plane_state->uapi.dst);
11782 if (!intel_cursor_size_ok(plane_state))
11785 /* Cursor width is limited to a few power-of-two sizes */
11796 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11797 * height from 8 lines up to the cursor width, when the
11798 * cursor is not rotated. Everything else requires square
11801 if (HAS_CUR_FBC(dev_priv) &&
11802 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11803 if (height < 8 || height > width)
11806 if (height != width)
11813 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11814 struct intel_plane_state *plane_state)
11816 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11817 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11818 const struct drm_framebuffer *fb = plane_state->hw.fb;
11819 enum pipe pipe = plane->pipe;
11822 ret = intel_check_cursor(crtc_state, plane_state);
11826 /* if we want to turn off the cursor ignore width and height */
11830 /* Check for which cursor types we support */
11831 if (!i9xx_cursor_size_ok(plane_state)) {
11832 drm_dbg(&dev_priv->drm,
11833 "Cursor dimension %dx%d not supported\n",
11834 drm_rect_width(&plane_state->uapi.dst),
11835 drm_rect_height(&plane_state->uapi.dst));
11839 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11840 plane_state->color_plane[0].stride != fb->pitches[0]);
11842 if (fb->pitches[0] !=
11843 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11844 drm_dbg_kms(&dev_priv->drm,
11845 "Invalid cursor stride (%u) (cursor width %d)\n",
11847 drm_rect_width(&plane_state->uapi.dst));
11852 * There's something wrong with the cursor on CHV pipe C.
11853 * If it straddles the left edge of the screen then
11854 * moving it away from the edge or disabling it often
11855 * results in a pipe underrun, and often that can lead to
11856 * dead pipe (constant underrun reported, and it scans
11857 * out just a solid color). To recover from that, the
11858 * display power well must be turned off and on again.
11859 * Refuse the put the cursor into that compromised position.
11861 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11862 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11863 drm_dbg_kms(&dev_priv->drm,
11864 "CHV cursor C not allowed to straddle the left screen edge\n");
11868 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11873 static void i9xx_update_cursor(struct intel_plane *plane,
11874 const struct intel_crtc_state *crtc_state,
11875 const struct intel_plane_state *plane_state)
11877 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11878 enum pipe pipe = plane->pipe;
11879 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11880 unsigned long irqflags;
11882 if (plane_state && plane_state->uapi.visible) {
11883 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11884 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11886 cntl = plane_state->ctl |
11887 i9xx_cursor_ctl_crtc(crtc_state);
11889 if (width != height)
11890 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11892 base = intel_cursor_base(plane_state);
11893 pos = intel_cursor_position(plane_state);
11896 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11899 * On some platforms writing CURCNTR first will also
11900 * cause CURPOS to be armed by the CURBASE write.
11901 * Without the CURCNTR write the CURPOS write would
11902 * arm itself. Thus we always update CURCNTR before
11905 * On other platforms CURPOS always requires the
11906 * CURBASE write to arm the update. Additonally
11907 * a write to any of the cursor register will cancel
11908 * an already armed cursor update. Thus leaving out
11909 * the CURBASE write after CURPOS could lead to a
11910 * cursor that doesn't appear to move, or even change
11911 * shape. Thus we always write CURBASE.
11913 * The other registers are armed by by the CURBASE write
11914 * except when the plane is getting enabled at which time
11915 * the CURCNTR write arms the update.
11918 if (INTEL_GEN(dev_priv) >= 9)
11919 skl_write_cursor_wm(plane, crtc_state);
11921 if (!needs_modeset(crtc_state))
11922 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
11924 if (plane->cursor.base != base ||
11925 plane->cursor.size != fbc_ctl ||
11926 plane->cursor.cntl != cntl) {
11927 if (HAS_CUR_FBC(dev_priv))
11928 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11930 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11931 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11932 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11934 plane->cursor.base = base;
11935 plane->cursor.size = fbc_ctl;
11936 plane->cursor.cntl = cntl;
11938 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11939 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11942 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11945 static void i9xx_disable_cursor(struct intel_plane *plane,
11946 const struct intel_crtc_state *crtc_state)
11948 i9xx_update_cursor(plane, crtc_state, NULL);
11951 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11954 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11955 enum intel_display_power_domain power_domain;
11956 intel_wakeref_t wakeref;
11961 * Not 100% correct for planes that can move between pipes,
11962 * but that's only the case for gen2-3 which don't have any
11963 * display power wells.
11965 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11966 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11970 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11972 ret = val & MCURSOR_MODE;
11974 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11975 *pipe = plane->pipe;
11977 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11978 MCURSOR_PIPE_SELECT_SHIFT;
11980 intel_display_power_put(dev_priv, power_domain, wakeref);
11985 /* VESA 640x480x72Hz mode to set on the pipe */
11986 static const struct drm_display_mode load_detect_mode = {
11987 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11988 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11991 struct drm_framebuffer *
11992 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11993 struct drm_mode_fb_cmd2 *mode_cmd)
11995 struct intel_framebuffer *intel_fb;
11998 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
12000 return ERR_PTR(-ENOMEM);
12002 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
12006 return &intel_fb->base;
12010 return ERR_PTR(ret);
12013 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
12014 struct drm_crtc *crtc)
12016 struct drm_plane *plane;
12017 struct drm_plane_state *plane_state;
12020 ret = drm_atomic_add_affected_planes(state, crtc);
12024 for_each_new_plane_in_state(state, plane, plane_state, i) {
12025 if (plane_state->crtc != crtc)
12028 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
12032 drm_atomic_set_fb_for_plane(plane_state, NULL);
12038 int intel_get_load_detect_pipe(struct drm_connector *connector,
12039 struct intel_load_detect_pipe *old,
12040 struct drm_modeset_acquire_ctx *ctx)
12042 struct intel_crtc *intel_crtc;
12043 struct intel_encoder *intel_encoder =
12044 intel_attached_encoder(to_intel_connector(connector));
12045 struct drm_crtc *possible_crtc;
12046 struct drm_encoder *encoder = &intel_encoder->base;
12047 struct drm_crtc *crtc = NULL;
12048 struct drm_device *dev = encoder->dev;
12049 struct drm_i915_private *dev_priv = to_i915(dev);
12050 struct drm_mode_config *config = &dev->mode_config;
12051 struct drm_atomic_state *state = NULL, *restore_state = NULL;
12052 struct drm_connector_state *connector_state;
12053 struct intel_crtc_state *crtc_state;
12056 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12057 connector->base.id, connector->name,
12058 encoder->base.id, encoder->name);
12060 old->restore_state = NULL;
12062 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
12065 * Algorithm gets a little messy:
12067 * - if the connector already has an assigned crtc, use it (but make
12068 * sure it's on first)
12070 * - try to find the first unused crtc that can drive this connector,
12071 * and use that if we find one
12074 /* See if we already have a CRTC for this connector */
12075 if (connector->state->crtc) {
12076 crtc = connector->state->crtc;
12078 ret = drm_modeset_lock(&crtc->mutex, ctx);
12082 /* Make sure the crtc and connector are running */
12086 /* Find an unused one (if possible) */
12087 for_each_crtc(dev, possible_crtc) {
12089 if (!(encoder->possible_crtcs & (1 << i)))
12092 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
12096 if (possible_crtc->state->enable) {
12097 drm_modeset_unlock(&possible_crtc->mutex);
12101 crtc = possible_crtc;
12106 * If we didn't find an unused CRTC, don't use any.
12109 drm_dbg_kms(&dev_priv->drm,
12110 "no pipe available for load-detect\n");
12116 intel_crtc = to_intel_crtc(crtc);
12118 state = drm_atomic_state_alloc(dev);
12119 restore_state = drm_atomic_state_alloc(dev);
12120 if (!state || !restore_state) {
12125 state->acquire_ctx = ctx;
12126 restore_state->acquire_ctx = ctx;
12128 connector_state = drm_atomic_get_connector_state(state, connector);
12129 if (IS_ERR(connector_state)) {
12130 ret = PTR_ERR(connector_state);
12134 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
12138 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12139 if (IS_ERR(crtc_state)) {
12140 ret = PTR_ERR(crtc_state);
12144 crtc_state->uapi.active = true;
12146 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12147 &load_detect_mode);
12151 ret = intel_modeset_disable_planes(state, crtc);
12155 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12157 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12159 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12161 drm_dbg_kms(&dev_priv->drm,
12162 "Failed to create a copy of old state to restore: %i\n",
12167 ret = drm_atomic_commit(state);
12169 drm_dbg_kms(&dev_priv->drm,
12170 "failed to set mode on load-detect pipe\n");
12174 old->restore_state = restore_state;
12175 drm_atomic_state_put(state);
12177 /* let the connector get through one full cycle before testing */
12178 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12183 drm_atomic_state_put(state);
12186 if (restore_state) {
12187 drm_atomic_state_put(restore_state);
12188 restore_state = NULL;
12191 if (ret == -EDEADLK)
12197 void intel_release_load_detect_pipe(struct drm_connector *connector,
12198 struct intel_load_detect_pipe *old,
12199 struct drm_modeset_acquire_ctx *ctx)
12201 struct intel_encoder *intel_encoder =
12202 intel_attached_encoder(to_intel_connector(connector));
12203 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12204 struct drm_encoder *encoder = &intel_encoder->base;
12205 struct drm_atomic_state *state = old->restore_state;
12208 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12209 connector->base.id, connector->name,
12210 encoder->base.id, encoder->name);
12215 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12217 drm_dbg_kms(&i915->drm,
12218 "Couldn't release load detect pipe: %i\n", ret);
12219 drm_atomic_state_put(state);
12222 static int i9xx_pll_refclk(struct drm_device *dev,
12223 const struct intel_crtc_state *pipe_config)
12225 struct drm_i915_private *dev_priv = to_i915(dev);
12226 u32 dpll = pipe_config->dpll_hw_state.dpll;
12228 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12229 return dev_priv->vbt.lvds_ssc_freq;
12230 else if (HAS_PCH_SPLIT(dev_priv))
12232 else if (!IS_GEN(dev_priv, 2))
12238 /* Returns the clock of the currently programmed mode of the given pipe. */
12239 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12240 struct intel_crtc_state *pipe_config)
12242 struct drm_device *dev = crtc->base.dev;
12243 struct drm_i915_private *dev_priv = to_i915(dev);
12244 enum pipe pipe = crtc->pipe;
12245 u32 dpll = pipe_config->dpll_hw_state.dpll;
12249 int refclk = i9xx_pll_refclk(dev, pipe_config);
12251 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12252 fp = pipe_config->dpll_hw_state.fp0;
12254 fp = pipe_config->dpll_hw_state.fp1;
12256 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12257 if (IS_PINEVIEW(dev_priv)) {
12258 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12259 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12261 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12262 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12265 if (!IS_GEN(dev_priv, 2)) {
12266 if (IS_PINEVIEW(dev_priv))
12267 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12268 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12270 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12271 DPLL_FPA01_P1_POST_DIV_SHIFT);
12273 switch (dpll & DPLL_MODE_MASK) {
12274 case DPLLB_MODE_DAC_SERIAL:
12275 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12278 case DPLLB_MODE_LVDS:
12279 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12283 drm_dbg_kms(&dev_priv->drm,
12284 "Unknown DPLL mode %08x in programmed "
12285 "mode\n", (int)(dpll & DPLL_MODE_MASK));
12289 if (IS_PINEVIEW(dev_priv))
12290 port_clock = pnv_calc_dpll_params(refclk, &clock);
12292 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12294 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12296 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12299 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12300 DPLL_FPA01_P1_POST_DIV_SHIFT);
12302 if (lvds & LVDS_CLKB_POWER_UP)
12307 if (dpll & PLL_P1_DIVIDE_BY_TWO)
12310 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12311 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12313 if (dpll & PLL_P2_DIVIDE_BY_4)
12319 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12323 * This value includes pixel_multiplier. We will use
12324 * port_clock to compute adjusted_mode.crtc_clock in the
12325 * encoder's get_config() function.
12327 pipe_config->port_clock = port_clock;
12330 int intel_dotclock_calculate(int link_freq,
12331 const struct intel_link_m_n *m_n)
12334 * The calculation for the data clock is:
12335 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12336 * But we want to avoid losing precison if possible, so:
12337 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12339 * and the link clock is simpler:
12340 * link_clock = (m * link_clock) / n
12346 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12349 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12350 struct intel_crtc_state *pipe_config)
12352 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12354 /* read out port_clock from the DPLL */
12355 i9xx_crtc_clock_get(crtc, pipe_config);
12358 * In case there is an active pipe without active ports,
12359 * we may need some idea for the dotclock anyway.
12360 * Calculate one based on the FDI configuration.
12362 pipe_config->hw.adjusted_mode.crtc_clock =
12363 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12364 &pipe_config->fdi_m_n);
12367 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12368 struct intel_crtc *crtc)
12370 memset(crtc_state, 0, sizeof(*crtc_state));
12372 __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12374 crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12375 crtc_state->master_transcoder = INVALID_TRANSCODER;
12376 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12377 crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12378 crtc_state->scaler_state.scaler_id = -1;
12379 crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12382 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12384 struct intel_crtc_state *crtc_state;
12386 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12389 intel_crtc_state_reset(crtc_state, crtc);
12394 /* Returns the currently programmed mode of the given encoder. */
12395 struct drm_display_mode *
12396 intel_encoder_current_mode(struct intel_encoder *encoder)
12398 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12399 struct intel_crtc_state *crtc_state;
12400 struct drm_display_mode *mode;
12401 struct intel_crtc *crtc;
12404 if (!encoder->get_hw_state(encoder, &pipe))
12407 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12409 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12413 crtc_state = intel_crtc_state_alloc(crtc);
12419 if (!intel_crtc_get_pipe_config(crtc_state)) {
12425 intel_encoder_get_config(encoder, crtc_state);
12427 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
12434 static void intel_crtc_destroy(struct drm_crtc *crtc)
12436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12438 drm_crtc_cleanup(crtc);
12443 * intel_wm_need_update - Check whether watermarks need updating
12444 * @cur: current plane state
12445 * @new: new plane state
12447 * Check current plane state versus the new one to determine whether
12448 * watermarks need to be recalculated.
12450 * Returns true or false.
12452 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12453 struct intel_plane_state *new)
12455 /* Update watermarks on tiling or size changes. */
12456 if (new->uapi.visible != cur->uapi.visible)
12459 if (!cur->hw.fb || !new->hw.fb)
12462 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12463 cur->hw.rotation != new->hw.rotation ||
12464 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12465 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12466 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12467 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12473 static bool needs_scaling(const struct intel_plane_state *state)
12475 int src_w = drm_rect_width(&state->uapi.src) >> 16;
12476 int src_h = drm_rect_height(&state->uapi.src) >> 16;
12477 int dst_w = drm_rect_width(&state->uapi.dst);
12478 int dst_h = drm_rect_height(&state->uapi.dst);
12480 return (src_w != dst_w || src_h != dst_h);
12483 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12484 struct intel_crtc_state *crtc_state,
12485 const struct intel_plane_state *old_plane_state,
12486 struct intel_plane_state *plane_state)
12488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12489 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12491 bool mode_changed = needs_modeset(crtc_state);
12492 bool was_crtc_enabled = old_crtc_state->hw.active;
12493 bool is_crtc_enabled = crtc_state->hw.active;
12494 bool turn_off, turn_on, visible, was_visible;
12497 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12498 ret = skl_update_scaler_plane(crtc_state, plane_state);
12503 was_visible = old_plane_state->uapi.visible;
12504 visible = plane_state->uapi.visible;
12506 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12507 was_visible = false;
12510 * Visibility is calculated as if the crtc was on, but
12511 * after scaler setup everything depends on it being off
12512 * when the crtc isn't active.
12514 * FIXME this is wrong for watermarks. Watermarks should also
12515 * be computed as if the pipe would be active. Perhaps move
12516 * per-plane wm computation to the .check_plane() hook, and
12517 * only combine the results from all planes in the current place?
12519 if (!is_crtc_enabled) {
12520 intel_plane_set_invisible(crtc_state, plane_state);
12524 if (!was_visible && !visible)
12527 turn_off = was_visible && (!visible || mode_changed);
12528 turn_on = visible && (!was_visible || mode_changed);
12530 drm_dbg_atomic(&dev_priv->drm,
12531 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12532 crtc->base.base.id, crtc->base.name,
12533 plane->base.base.id, plane->base.name,
12534 was_visible, visible,
12535 turn_off, turn_on, mode_changed);
12538 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12539 crtc_state->update_wm_pre = true;
12541 /* must disable cxsr around plane enable/disable */
12542 if (plane->id != PLANE_CURSOR)
12543 crtc_state->disable_cxsr = true;
12544 } else if (turn_off) {
12545 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12546 crtc_state->update_wm_post = true;
12548 /* must disable cxsr around plane enable/disable */
12549 if (plane->id != PLANE_CURSOR)
12550 crtc_state->disable_cxsr = true;
12551 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12552 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12553 /* FIXME bollocks */
12554 crtc_state->update_wm_pre = true;
12555 crtc_state->update_wm_post = true;
12559 if (visible || was_visible)
12560 crtc_state->fb_bits |= plane->frontbuffer_bit;
12563 * ILK/SNB DVSACNTR/Sprite Enable
12564 * IVB SPR_CTL/Sprite Enable
12565 * "When in Self Refresh Big FIFO mode, a write to enable the
12566 * plane will be internally buffered and delayed while Big FIFO
12567 * mode is exiting."
12569 * Which means that enabling the sprite can take an extra frame
12570 * when we start in big FIFO mode (LP1+). Thus we need to drop
12571 * down to LP0 and wait for vblank in order to make sure the
12572 * sprite gets enabled on the next vblank after the register write.
12573 * Doing otherwise would risk enabling the sprite one frame after
12574 * we've already signalled flip completion. We can resume LP1+
12575 * once the sprite has been enabled.
12578 * WaCxSRDisabledForSpriteScaling:ivb
12579 * IVB SPR_SCALE/Scaling Enable
12580 * "Low Power watermarks must be disabled for at least one
12581 * frame before enabling sprite scaling, and kept disabled
12582 * until sprite scaling is disabled."
12584 * ILK/SNB DVSASCALE/Scaling Enable
12585 * "When in Self Refresh Big FIFO mode, scaling enable will be
12586 * masked off while Big FIFO mode is exiting."
12588 * Despite the w/a only being listed for IVB we assume that
12589 * the ILK/SNB note has similar ramifications, hence we apply
12590 * the w/a on all three platforms.
12592 * With experimental results seems this is needed also for primary
12593 * plane, not only sprite plane.
12595 if (plane->id != PLANE_CURSOR &&
12596 (IS_GEN_RANGE(dev_priv, 5, 6) ||
12597 IS_IVYBRIDGE(dev_priv)) &&
12598 (turn_on || (!needs_scaling(old_plane_state) &&
12599 needs_scaling(plane_state))))
12600 crtc_state->disable_lp_wm = true;
12605 static bool encoders_cloneable(const struct intel_encoder *a,
12606 const struct intel_encoder *b)
12608 /* masks could be asymmetric, so check both ways */
12609 return a == b || (a->cloneable & (1 << b->type) &&
12610 b->cloneable & (1 << a->type));
12613 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12614 struct intel_crtc *crtc,
12615 struct intel_encoder *encoder)
12617 struct intel_encoder *source_encoder;
12618 struct drm_connector *connector;
12619 struct drm_connector_state *connector_state;
12622 for_each_new_connector_in_state(state, connector, connector_state, i) {
12623 if (connector_state->crtc != &crtc->base)
12627 to_intel_encoder(connector_state->best_encoder);
12628 if (!encoders_cloneable(encoder, source_encoder))
12635 static int icl_add_linked_planes(struct intel_atomic_state *state)
12637 struct intel_plane *plane, *linked;
12638 struct intel_plane_state *plane_state, *linked_plane_state;
12641 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12642 linked = plane_state->planar_linked_plane;
12647 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12648 if (IS_ERR(linked_plane_state))
12649 return PTR_ERR(linked_plane_state);
12651 drm_WARN_ON(state->base.dev,
12652 linked_plane_state->planar_linked_plane != plane);
12653 drm_WARN_ON(state->base.dev,
12654 linked_plane_state->planar_slave == plane_state->planar_slave);
12660 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12662 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12663 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12664 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12665 struct intel_plane *plane, *linked;
12666 struct intel_plane_state *plane_state;
12669 if (INTEL_GEN(dev_priv) < 11)
12673 * Destroy all old plane links and make the slave plane invisible
12674 * in the crtc_state->active_planes mask.
12676 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12677 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12680 plane_state->planar_linked_plane = NULL;
12681 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12682 crtc_state->active_planes &= ~BIT(plane->id);
12683 crtc_state->update_planes |= BIT(plane->id);
12686 plane_state->planar_slave = false;
12689 if (!crtc_state->nv12_planes)
12692 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12693 struct intel_plane_state *linked_state = NULL;
12695 if (plane->pipe != crtc->pipe ||
12696 !(crtc_state->nv12_planes & BIT(plane->id)))
12699 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12700 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
12703 if (crtc_state->active_planes & BIT(linked->id))
12706 linked_state = intel_atomic_get_plane_state(state, linked);
12707 if (IS_ERR(linked_state))
12708 return PTR_ERR(linked_state);
12713 if (!linked_state) {
12714 drm_dbg_kms(&dev_priv->drm,
12715 "Need %d free Y planes for planar YUV\n",
12716 hweight8(crtc_state->nv12_planes));
12721 plane_state->planar_linked_plane = linked;
12723 linked_state->planar_slave = true;
12724 linked_state->planar_linked_plane = plane;
12725 crtc_state->active_planes |= BIT(linked->id);
12726 crtc_state->update_planes |= BIT(linked->id);
12727 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12728 linked->base.name, plane->base.name);
12730 /* Copy parameters to slave plane */
12731 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12732 linked_state->color_ctl = plane_state->color_ctl;
12733 linked_state->view = plane_state->view;
12734 memcpy(linked_state->color_plane, plane_state->color_plane,
12735 sizeof(linked_state->color_plane));
12737 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12738 linked_state->uapi.src = plane_state->uapi.src;
12739 linked_state->uapi.dst = plane_state->uapi.dst;
12741 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12742 if (linked->id == PLANE_SPRITE5)
12743 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12744 else if (linked->id == PLANE_SPRITE4)
12745 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12746 else if (linked->id == PLANE_SPRITE3)
12747 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
12748 else if (linked->id == PLANE_SPRITE2)
12749 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
12751 MISSING_CASE(linked->id);
12758 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12760 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12761 struct intel_atomic_state *state =
12762 to_intel_atomic_state(new_crtc_state->uapi.state);
12763 const struct intel_crtc_state *old_crtc_state =
12764 intel_atomic_get_old_crtc_state(state, crtc);
12766 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12769 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12771 const struct drm_display_mode *adjusted_mode =
12772 &crtc_state->hw.adjusted_mode;
12775 if (!crtc_state->hw.enable)
12778 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12779 adjusted_mode->crtc_clock);
12781 return min(linetime_wm, 0x1ff);
12784 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12785 const struct intel_cdclk_state *cdclk_state)
12787 const struct drm_display_mode *adjusted_mode =
12788 &crtc_state->hw.adjusted_mode;
12791 if (!crtc_state->hw.enable)
12794 linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12795 cdclk_state->logical.cdclk);
12797 return min(linetime_wm, 0x1ff);
12800 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12802 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12803 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12804 const struct drm_display_mode *adjusted_mode =
12805 &crtc_state->hw.adjusted_mode;
12808 if (!crtc_state->hw.enable)
12811 linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12812 crtc_state->pixel_rate);
12814 /* Display WA #1135: BXT:ALL GLK:ALL */
12815 if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12818 return min(linetime_wm, 0x1ff);
12821 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12822 struct intel_crtc *crtc)
12824 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12825 struct intel_crtc_state *crtc_state =
12826 intel_atomic_get_new_crtc_state(state, crtc);
12827 const struct intel_cdclk_state *cdclk_state;
12829 if (INTEL_GEN(dev_priv) >= 9)
12830 crtc_state->linetime = skl_linetime_wm(crtc_state);
12832 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12834 if (!hsw_crtc_supports_ips(crtc))
12837 cdclk_state = intel_atomic_get_cdclk_state(state);
12838 if (IS_ERR(cdclk_state))
12839 return PTR_ERR(cdclk_state);
12841 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12847 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12848 struct intel_crtc *crtc)
12850 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12851 struct intel_crtc_state *crtc_state =
12852 intel_atomic_get_new_crtc_state(state, crtc);
12853 bool mode_changed = needs_modeset(crtc_state);
12856 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12857 mode_changed && !crtc_state->hw.active)
12858 crtc_state->update_wm_post = true;
12860 if (mode_changed && crtc_state->hw.enable &&
12861 dev_priv->display.crtc_compute_clock &&
12862 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12863 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12869 * May need to update pipe gamma enable bits
12870 * when C8 planes are getting enabled/disabled.
12872 if (c8_planes_changed(crtc_state))
12873 crtc_state->uapi.color_mgmt_changed = true;
12875 if (mode_changed || crtc_state->update_pipe ||
12876 crtc_state->uapi.color_mgmt_changed) {
12877 ret = intel_color_check(crtc_state);
12882 if (dev_priv->display.compute_pipe_wm) {
12883 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12885 drm_dbg_kms(&dev_priv->drm,
12886 "Target pipe watermarks are invalid\n");
12891 if (dev_priv->display.compute_intermediate_wm) {
12892 if (drm_WARN_ON(&dev_priv->drm,
12893 !dev_priv->display.compute_pipe_wm))
12897 * Calculate 'intermediate' watermarks that satisfy both the
12898 * old state and the new state. We can program these
12901 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12903 drm_dbg_kms(&dev_priv->drm,
12904 "No valid intermediate pipe watermarks are possible\n");
12909 if (INTEL_GEN(dev_priv) >= 9) {
12910 if (mode_changed || crtc_state->update_pipe) {
12911 ret = skl_update_scaler_crtc(crtc_state);
12916 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12921 if (HAS_IPS(dev_priv)) {
12922 ret = hsw_compute_ips_config(crtc_state);
12927 if (INTEL_GEN(dev_priv) >= 9 ||
12928 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12929 ret = hsw_compute_linetime_wm(state, crtc);
12935 if (!mode_changed) {
12936 ret = intel_psr2_sel_fetch_update(state, crtc);
12944 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12946 struct intel_connector *connector;
12947 struct drm_connector_list_iter conn_iter;
12949 drm_connector_list_iter_begin(dev, &conn_iter);
12950 for_each_intel_connector_iter(connector, &conn_iter) {
12951 if (connector->base.state->crtc)
12952 drm_connector_put(&connector->base);
12954 if (connector->base.encoder) {
12955 connector->base.state->best_encoder =
12956 connector->base.encoder;
12957 connector->base.state->crtc =
12958 connector->base.encoder->crtc;
12960 drm_connector_get(&connector->base);
12962 connector->base.state->best_encoder = NULL;
12963 connector->base.state->crtc = NULL;
12966 drm_connector_list_iter_end(&conn_iter);
12970 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12971 struct intel_crtc_state *pipe_config)
12973 struct drm_connector *connector = conn_state->connector;
12974 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12975 const struct drm_display_info *info = &connector->display_info;
12978 switch (conn_state->max_bpc) {
12995 if (bpp < pipe_config->pipe_bpp) {
12996 drm_dbg_kms(&i915->drm,
12997 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12998 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12999 connector->base.id, connector->name,
13000 bpp, 3 * info->bpc,
13001 3 * conn_state->max_requested_bpc,
13002 pipe_config->pipe_bpp);
13004 pipe_config->pipe_bpp = bpp;
13011 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
13012 struct intel_crtc_state *pipe_config)
13014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13015 struct drm_atomic_state *state = pipe_config->uapi.state;
13016 struct drm_connector *connector;
13017 struct drm_connector_state *connector_state;
13020 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
13021 IS_CHERRYVIEW(dev_priv)))
13023 else if (INTEL_GEN(dev_priv) >= 5)
13028 pipe_config->pipe_bpp = bpp;
13030 /* Clamp display bpp to connector max bpp */
13031 for_each_new_connector_in_state(state, connector, connector_state, i) {
13034 if (connector_state->crtc != &crtc->base)
13037 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
13045 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
13046 const struct drm_display_mode *mode)
13048 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
13049 "type: 0x%x flags: 0x%x\n",
13051 mode->crtc_hdisplay, mode->crtc_hsync_start,
13052 mode->crtc_hsync_end, mode->crtc_htotal,
13053 mode->crtc_vdisplay, mode->crtc_vsync_start,
13054 mode->crtc_vsync_end, mode->crtc_vtotal,
13055 mode->type, mode->flags);
13059 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
13060 const char *id, unsigned int lane_count,
13061 const struct intel_link_m_n *m_n)
13063 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13065 drm_dbg_kms(&i915->drm,
13066 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
13068 m_n->gmch_m, m_n->gmch_n,
13069 m_n->link_m, m_n->link_n, m_n->tu);
13073 intel_dump_infoframe(struct drm_i915_private *dev_priv,
13074 const union hdmi_infoframe *frame)
13076 if (!drm_debug_enabled(DRM_UT_KMS))
13079 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
13083 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
13084 const struct drm_dp_vsc_sdp *vsc)
13086 if (!drm_debug_enabled(DRM_UT_KMS))
13089 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
13092 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
13094 static const char * const output_type_str[] = {
13095 OUTPUT_TYPE(UNUSED),
13096 OUTPUT_TYPE(ANALOG),
13100 OUTPUT_TYPE(TVOUT),
13106 OUTPUT_TYPE(DP_MST),
13111 static void snprintf_output_types(char *buf, size_t len,
13112 unsigned int output_types)
13119 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
13122 if ((output_types & BIT(i)) == 0)
13125 r = snprintf(str, len, "%s%s",
13126 str != buf ? "," : "", output_type_str[i]);
13132 output_types &= ~BIT(i);
13135 WARN_ON_ONCE(output_types != 0);
13138 static const char * const output_format_str[] = {
13139 [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
13140 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
13141 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
13142 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
13145 static const char *output_formats(enum intel_output_format format)
13147 if (format >= ARRAY_SIZE(output_format_str))
13148 format = INTEL_OUTPUT_FORMAT_INVALID;
13149 return output_format_str[format];
13152 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
13154 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
13155 struct drm_i915_private *i915 = to_i915(plane->base.dev);
13156 const struct drm_framebuffer *fb = plane_state->hw.fb;
13157 struct drm_format_name_buf format_name;
13160 drm_dbg_kms(&i915->drm,
13161 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
13162 plane->base.base.id, plane->base.name,
13163 yesno(plane_state->uapi.visible));
13167 drm_dbg_kms(&i915->drm,
13168 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s modifier = 0x%llx, visible: %s\n",
13169 plane->base.base.id, plane->base.name,
13170 fb->base.id, fb->width, fb->height,
13171 drm_get_format_name(fb->format->format, &format_name),
13172 fb->modifier, yesno(plane_state->uapi.visible));
13173 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13174 plane_state->hw.rotation, plane_state->scaler_id);
13175 if (plane_state->uapi.visible)
13176 drm_dbg_kms(&i915->drm,
13177 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13178 DRM_RECT_FP_ARG(&plane_state->uapi.src),
13179 DRM_RECT_ARG(&plane_state->uapi.dst));
13182 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13183 struct intel_atomic_state *state,
13184 const char *context)
13186 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13187 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13188 const struct intel_plane_state *plane_state;
13189 struct intel_plane *plane;
13193 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13194 crtc->base.base.id, crtc->base.name,
13195 yesno(pipe_config->hw.enable), context);
13197 if (!pipe_config->hw.enable)
13200 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13201 drm_dbg_kms(&dev_priv->drm,
13202 "active: %s, output_types: %s (0x%x), output format: %s\n",
13203 yesno(pipe_config->hw.active),
13204 buf, pipe_config->output_types,
13205 output_formats(pipe_config->output_format));
13207 drm_dbg_kms(&dev_priv->drm,
13208 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13209 transcoder_name(pipe_config->cpu_transcoder),
13210 pipe_config->pipe_bpp, pipe_config->dither);
13212 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13213 transcoder_name(pipe_config->mst_master_transcoder));
13215 drm_dbg_kms(&dev_priv->drm,
13216 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
13217 transcoder_name(pipe_config->master_transcoder),
13218 pipe_config->sync_mode_slaves_mask);
13220 if (pipe_config->has_pch_encoder)
13221 intel_dump_m_n_config(pipe_config, "fdi",
13222 pipe_config->fdi_lanes,
13223 &pipe_config->fdi_m_n);
13225 if (intel_crtc_has_dp_encoder(pipe_config)) {
13226 intel_dump_m_n_config(pipe_config, "dp m_n",
13227 pipe_config->lane_count, &pipe_config->dp_m_n);
13228 if (pipe_config->has_drrs)
13229 intel_dump_m_n_config(pipe_config, "dp m2_n2",
13230 pipe_config->lane_count,
13231 &pipe_config->dp_m2_n2);
13234 drm_dbg_kms(&dev_priv->drm,
13235 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13236 pipe_config->has_audio, pipe_config->has_infoframe,
13237 pipe_config->infoframes.enable);
13239 if (pipe_config->infoframes.enable &
13240 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13241 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13242 pipe_config->infoframes.gcp);
13243 if (pipe_config->infoframes.enable &
13244 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13245 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13246 if (pipe_config->infoframes.enable &
13247 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13248 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13249 if (pipe_config->infoframes.enable &
13250 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13251 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13252 if (pipe_config->infoframes.enable &
13253 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
13254 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13255 if (pipe_config->infoframes.enable &
13256 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
13257 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
13258 if (pipe_config->infoframes.enable &
13259 intel_hdmi_infoframe_enable(DP_SDP_VSC))
13260 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
13262 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13263 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13264 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13265 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13266 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
13267 drm_dbg_kms(&dev_priv->drm,
13268 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13269 pipe_config->port_clock,
13270 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13271 pipe_config->pixel_rate);
13273 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13274 pipe_config->linetime, pipe_config->ips_linetime);
13276 if (INTEL_GEN(dev_priv) >= 9)
13277 drm_dbg_kms(&dev_priv->drm,
13278 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13280 pipe_config->scaler_state.scaler_users,
13281 pipe_config->scaler_state.scaler_id);
13283 if (HAS_GMCH(dev_priv))
13284 drm_dbg_kms(&dev_priv->drm,
13285 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13286 pipe_config->gmch_pfit.control,
13287 pipe_config->gmch_pfit.pgm_ratios,
13288 pipe_config->gmch_pfit.lvds_border_bits);
13290 drm_dbg_kms(&dev_priv->drm,
13291 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
13292 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
13293 enableddisabled(pipe_config->pch_pfit.enabled),
13294 yesno(pipe_config->pch_pfit.force_thru));
13296 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13297 pipe_config->ips_enabled, pipe_config->double_wide);
13299 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13301 if (IS_CHERRYVIEW(dev_priv))
13302 drm_dbg_kms(&dev_priv->drm,
13303 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13304 pipe_config->cgm_mode, pipe_config->gamma_mode,
13305 pipe_config->gamma_enable, pipe_config->csc_enable);
13307 drm_dbg_kms(&dev_priv->drm,
13308 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13309 pipe_config->csc_mode, pipe_config->gamma_mode,
13310 pipe_config->gamma_enable, pipe_config->csc_enable);
13312 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
13313 pipe_config->hw.degamma_lut ?
13314 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
13315 pipe_config->hw.gamma_lut ?
13316 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
13322 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13323 if (plane->pipe == crtc->pipe)
13324 intel_dump_plane_state(plane_state);
13328 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13330 struct drm_device *dev = state->base.dev;
13331 struct drm_connector *connector;
13332 struct drm_connector_list_iter conn_iter;
13333 unsigned int used_ports = 0;
13334 unsigned int used_mst_ports = 0;
13338 * We're going to peek into connector->state,
13339 * hence connection_mutex must be held.
13341 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13344 * Walk the connector list instead of the encoder
13345 * list to detect the problem on ddi platforms
13346 * where there's just one encoder per digital port.
13348 drm_connector_list_iter_begin(dev, &conn_iter);
13349 drm_for_each_connector_iter(connector, &conn_iter) {
13350 struct drm_connector_state *connector_state;
13351 struct intel_encoder *encoder;
13354 drm_atomic_get_new_connector_state(&state->base,
13356 if (!connector_state)
13357 connector_state = connector->state;
13359 if (!connector_state->best_encoder)
13362 encoder = to_intel_encoder(connector_state->best_encoder);
13364 drm_WARN_ON(dev, !connector_state->crtc);
13366 switch (encoder->type) {
13367 case INTEL_OUTPUT_DDI:
13368 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13371 case INTEL_OUTPUT_DP:
13372 case INTEL_OUTPUT_HDMI:
13373 case INTEL_OUTPUT_EDP:
13374 /* the same port mustn't appear more than once */
13375 if (used_ports & BIT(encoder->port))
13378 used_ports |= BIT(encoder->port);
13380 case INTEL_OUTPUT_DP_MST:
13382 1 << encoder->port;
13388 drm_connector_list_iter_end(&conn_iter);
13390 /* can't mix MST and SST/HDMI on the same port */
13391 if (used_ports & used_mst_ports)
13398 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13400 intel_crtc_copy_color_blobs(crtc_state);
13404 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13406 crtc_state->hw.enable = crtc_state->uapi.enable;
13407 crtc_state->hw.active = crtc_state->uapi.active;
13408 crtc_state->hw.mode = crtc_state->uapi.mode;
13409 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13410 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
13411 intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13414 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13416 crtc_state->uapi.enable = crtc_state->hw.enable;
13417 crtc_state->uapi.active = crtc_state->hw.active;
13418 drm_WARN_ON(crtc_state->uapi.crtc->dev,
13419 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13421 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13422 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
13424 /* copy color blobs to uapi */
13425 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13426 crtc_state->hw.degamma_lut);
13427 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13428 crtc_state->hw.gamma_lut);
13429 drm_property_replace_blob(&crtc_state->uapi.ctm,
13430 crtc_state->hw.ctm);
13434 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13436 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13437 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13438 struct intel_crtc_state *saved_state;
13440 saved_state = intel_crtc_state_alloc(crtc);
13444 /* free the old crtc_state->hw members */
13445 intel_crtc_free_hw_state(crtc_state);
13447 /* FIXME: before the switch to atomic started, a new pipe_config was
13448 * kzalloc'd. Code that depends on any field being zero should be
13449 * fixed, so that the crtc_state can be safely duplicated. For now,
13450 * only fields that are know to not cause problems are preserved. */
13452 saved_state->uapi = crtc_state->uapi;
13453 saved_state->scaler_state = crtc_state->scaler_state;
13454 saved_state->shared_dpll = crtc_state->shared_dpll;
13455 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13456 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13457 sizeof(saved_state->icl_port_dplls));
13458 saved_state->crc_enabled = crtc_state->crc_enabled;
13459 if (IS_G4X(dev_priv) ||
13460 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13461 saved_state->wm = crtc_state->wm;
13463 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13464 kfree(saved_state);
13466 intel_crtc_copy_uapi_to_hw_state(crtc_state);
13472 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13474 struct drm_crtc *crtc = pipe_config->uapi.crtc;
13475 struct drm_atomic_state *state = pipe_config->uapi.state;
13476 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13477 struct drm_connector *connector;
13478 struct drm_connector_state *connector_state;
13479 int base_bpp, ret, i;
13482 pipe_config->cpu_transcoder =
13483 (enum transcoder) to_intel_crtc(crtc)->pipe;
13486 * Sanitize sync polarity flags based on requested ones. If neither
13487 * positive or negative polarity is requested, treat this as meaning
13488 * negative polarity.
13490 if (!(pipe_config->hw.adjusted_mode.flags &
13491 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13492 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13494 if (!(pipe_config->hw.adjusted_mode.flags &
13495 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13496 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13498 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13503 base_bpp = pipe_config->pipe_bpp;
13506 * Determine the real pipe dimensions. Note that stereo modes can
13507 * increase the actual pipe size due to the frame doubling and
13508 * insertion of additional space for blanks between the frame. This
13509 * is stored in the crtc timings. We use the requested mode to do this
13510 * computation to clearly distinguish it from the adjusted mode, which
13511 * can be changed by the connectors in the below retry loop.
13513 drm_mode_get_hv_timing(&pipe_config->hw.mode,
13514 &pipe_config->pipe_src_w,
13515 &pipe_config->pipe_src_h);
13517 for_each_new_connector_in_state(state, connector, connector_state, i) {
13518 struct intel_encoder *encoder =
13519 to_intel_encoder(connector_state->best_encoder);
13521 if (connector_state->crtc != crtc)
13524 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13525 drm_dbg_kms(&i915->drm,
13526 "rejecting invalid cloning configuration\n");
13531 * Determine output_types before calling the .compute_config()
13532 * hooks so that the hooks can use this information safely.
13534 if (encoder->compute_output_type)
13535 pipe_config->output_types |=
13536 BIT(encoder->compute_output_type(encoder, pipe_config,
13539 pipe_config->output_types |= BIT(encoder->type);
13543 /* Ensure the port clock defaults are reset when retrying. */
13544 pipe_config->port_clock = 0;
13545 pipe_config->pixel_multiplier = 1;
13547 /* Fill in default crtc timings, allow encoders to overwrite them. */
13548 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13549 CRTC_STEREO_DOUBLE);
13551 /* Pass our mode to the connectors and the CRTC to give them a chance to
13552 * adjust it according to limitations or connector properties, and also
13553 * a chance to reject the mode entirely.
13555 for_each_new_connector_in_state(state, connector, connector_state, i) {
13556 struct intel_encoder *encoder =
13557 to_intel_encoder(connector_state->best_encoder);
13559 if (connector_state->crtc != crtc)
13562 ret = encoder->compute_config(encoder, pipe_config,
13565 if (ret != -EDEADLK)
13566 drm_dbg_kms(&i915->drm,
13567 "Encoder config failure: %d\n",
13573 /* Set default port clock if not overwritten by the encoder. Needs to be
13574 * done afterwards in case the encoder adjusts the mode. */
13575 if (!pipe_config->port_clock)
13576 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13577 * pipe_config->pixel_multiplier;
13579 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13580 if (ret == -EDEADLK)
13583 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13587 if (ret == RETRY) {
13588 if (drm_WARN(&i915->drm, !retry,
13589 "loop in pipe configuration computation\n"))
13592 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13594 goto encoder_retry;
13597 /* Dithering seems to not pass-through bits correctly when it should, so
13598 * only enable it on 6bpc panels and when its not a compliance
13599 * test requesting 6bpc video pattern.
13601 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13602 !pipe_config->dither_force_disable;
13603 drm_dbg_kms(&i915->drm,
13604 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13605 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13611 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13613 struct intel_atomic_state *state =
13614 to_intel_atomic_state(crtc_state->uapi.state);
13615 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13616 struct drm_connector_state *conn_state;
13617 struct drm_connector *connector;
13620 for_each_new_connector_in_state(&state->base, connector,
13622 struct intel_encoder *encoder =
13623 to_intel_encoder(conn_state->best_encoder);
13626 if (conn_state->crtc != &crtc->base ||
13627 !encoder->compute_config_late)
13630 ret = encoder->compute_config_late(encoder, crtc_state,
13639 bool intel_fuzzy_clock_check(int clock1, int clock2)
13643 if (clock1 == clock2)
13646 if (!clock1 || !clock2)
13649 diff = abs(clock1 - clock2);
13651 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13658 intel_compare_m_n(unsigned int m, unsigned int n,
13659 unsigned int m2, unsigned int n2,
13662 if (m == m2 && n == n2)
13665 if (exact || !m || !n || !m2 || !n2)
13668 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13675 } else if (n < n2) {
13685 return intel_fuzzy_clock_check(m, m2);
13689 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13690 const struct intel_link_m_n *m2_n2,
13693 return m_n->tu == m2_n2->tu &&
13694 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13695 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13696 intel_compare_m_n(m_n->link_m, m_n->link_n,
13697 m2_n2->link_m, m2_n2->link_n, exact);
13701 intel_compare_infoframe(const union hdmi_infoframe *a,
13702 const union hdmi_infoframe *b)
13704 return memcmp(a, b, sizeof(*a)) == 0;
13708 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
13709 const struct drm_dp_vsc_sdp *b)
13711 return memcmp(a, b, sizeof(*a)) == 0;
13715 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13716 bool fastset, const char *name,
13717 const union hdmi_infoframe *a,
13718 const union hdmi_infoframe *b)
13721 if (!drm_debug_enabled(DRM_UT_KMS))
13724 drm_dbg_kms(&dev_priv->drm,
13725 "fastset mismatch in %s infoframe\n", name);
13726 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13727 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13728 drm_dbg_kms(&dev_priv->drm, "found:\n");
13729 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13731 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13732 drm_err(&dev_priv->drm, "expected:\n");
13733 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13734 drm_err(&dev_priv->drm, "found:\n");
13735 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13740 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
13741 bool fastset, const char *name,
13742 const struct drm_dp_vsc_sdp *a,
13743 const struct drm_dp_vsc_sdp *b)
13746 if (!drm_debug_enabled(DRM_UT_KMS))
13749 drm_dbg_kms(&dev_priv->drm,
13750 "fastset mismatch in %s dp sdp\n", name);
13751 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13752 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
13753 drm_dbg_kms(&dev_priv->drm, "found:\n");
13754 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
13756 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
13757 drm_err(&dev_priv->drm, "expected:\n");
13758 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
13759 drm_err(&dev_priv->drm, "found:\n");
13760 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
13764 static void __printf(4, 5)
13765 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13766 const char *name, const char *format, ...)
13768 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13769 struct va_format vaf;
13772 va_start(args, format);
13777 drm_dbg_kms(&i915->drm,
13778 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13779 crtc->base.base.id, crtc->base.name, name, &vaf);
13781 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13782 crtc->base.base.id, crtc->base.name, name, &vaf);
13787 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13789 if (dev_priv->params.fastboot != -1)
13790 return dev_priv->params.fastboot;
13792 /* Enable fastboot by default on Skylake and newer */
13793 if (INTEL_GEN(dev_priv) >= 9)
13796 /* Enable fastboot by default on VLV and CHV */
13797 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13800 /* Disabled by default on all others */
13805 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13806 const struct intel_crtc_state *pipe_config,
13809 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13810 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13813 bool fixup_inherited = fastset &&
13814 current_config->inherited && !pipe_config->inherited;
13816 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13817 drm_dbg_kms(&dev_priv->drm,
13818 "initial modeset and fastboot not set\n");
13822 #define PIPE_CONF_CHECK_X(name) do { \
13823 if (current_config->name != pipe_config->name) { \
13824 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13825 "(expected 0x%08x, found 0x%08x)", \
13826 current_config->name, \
13827 pipe_config->name); \
13832 #define PIPE_CONF_CHECK_I(name) do { \
13833 if (current_config->name != pipe_config->name) { \
13834 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13835 "(expected %i, found %i)", \
13836 current_config->name, \
13837 pipe_config->name); \
13842 #define PIPE_CONF_CHECK_BOOL(name) do { \
13843 if (current_config->name != pipe_config->name) { \
13844 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13845 "(expected %s, found %s)", \
13846 yesno(current_config->name), \
13847 yesno(pipe_config->name)); \
13853 * Checks state where we only read out the enabling, but not the entire
13854 * state itself (like full infoframes or ELD for audio). These states
13855 * require a full modeset on bootup to fix up.
13857 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13858 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13859 PIPE_CONF_CHECK_BOOL(name); \
13861 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13862 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13863 yesno(current_config->name), \
13864 yesno(pipe_config->name)); \
13869 #define PIPE_CONF_CHECK_P(name) do { \
13870 if (current_config->name != pipe_config->name) { \
13871 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13872 "(expected %p, found %p)", \
13873 current_config->name, \
13874 pipe_config->name); \
13879 #define PIPE_CONF_CHECK_M_N(name) do { \
13880 if (!intel_compare_link_m_n(¤t_config->name, \
13881 &pipe_config->name,\
13883 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13884 "(expected tu %i gmch %i/%i link %i/%i, " \
13885 "found tu %i, gmch %i/%i link %i/%i)", \
13886 current_config->name.tu, \
13887 current_config->name.gmch_m, \
13888 current_config->name.gmch_n, \
13889 current_config->name.link_m, \
13890 current_config->name.link_n, \
13891 pipe_config->name.tu, \
13892 pipe_config->name.gmch_m, \
13893 pipe_config->name.gmch_n, \
13894 pipe_config->name.link_m, \
13895 pipe_config->name.link_n); \
13900 /* This is required for BDW+ where there is only one set of registers for
13901 * switching between high and low RR.
13902 * This macro can be used whenever a comparison has to be made between one
13903 * hw state and multiple sw state variables.
13905 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13906 if (!intel_compare_link_m_n(¤t_config->name, \
13907 &pipe_config->name, !fastset) && \
13908 !intel_compare_link_m_n(¤t_config->alt_name, \
13909 &pipe_config->name, !fastset)) { \
13910 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13911 "(expected tu %i gmch %i/%i link %i/%i, " \
13912 "or tu %i gmch %i/%i link %i/%i, " \
13913 "found tu %i, gmch %i/%i link %i/%i)", \
13914 current_config->name.tu, \
13915 current_config->name.gmch_m, \
13916 current_config->name.gmch_n, \
13917 current_config->name.link_m, \
13918 current_config->name.link_n, \
13919 current_config->alt_name.tu, \
13920 current_config->alt_name.gmch_m, \
13921 current_config->alt_name.gmch_n, \
13922 current_config->alt_name.link_m, \
13923 current_config->alt_name.link_n, \
13924 pipe_config->name.tu, \
13925 pipe_config->name.gmch_m, \
13926 pipe_config->name.gmch_n, \
13927 pipe_config->name.link_m, \
13928 pipe_config->name.link_n); \
13933 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13934 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13935 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13936 "(%x) (expected %i, found %i)", \
13938 current_config->name & (mask), \
13939 pipe_config->name & (mask)); \
13944 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13945 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13946 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13947 "(expected %i, found %i)", \
13948 current_config->name, \
13949 pipe_config->name); \
13954 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13955 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
13956 &pipe_config->infoframes.name)) { \
13957 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13958 ¤t_config->infoframes.name, \
13959 &pipe_config->infoframes.name); \
13964 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
13965 if (!current_config->has_psr && !pipe_config->has_psr && \
13966 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
13967 &pipe_config->infoframes.name)) { \
13968 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
13969 ¤t_config->infoframes.name, \
13970 &pipe_config->infoframes.name); \
13975 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13976 if (current_config->name1 != pipe_config->name1) { \
13977 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13978 "(expected %i, found %i, won't compare lut values)", \
13979 current_config->name1, \
13980 pipe_config->name1); \
13983 if (!intel_color_lut_equal(current_config->name2, \
13984 pipe_config->name2, pipe_config->name1, \
13985 bit_precision)) { \
13986 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13987 "hw_state doesn't match sw_state"); \
13993 #define PIPE_CONF_QUIRK(quirk) \
13994 ((current_config->quirks | pipe_config->quirks) & (quirk))
13996 PIPE_CONF_CHECK_I(cpu_transcoder);
13998 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13999 PIPE_CONF_CHECK_I(fdi_lanes);
14000 PIPE_CONF_CHECK_M_N(fdi_m_n);
14002 PIPE_CONF_CHECK_I(lane_count);
14003 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
14005 if (INTEL_GEN(dev_priv) < 8) {
14006 PIPE_CONF_CHECK_M_N(dp_m_n);
14008 if (current_config->has_drrs)
14009 PIPE_CONF_CHECK_M_N(dp_m2_n2);
14011 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
14013 PIPE_CONF_CHECK_X(output_types);
14015 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
14016 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
14017 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
14018 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
14019 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
14020 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
14022 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
14023 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
14024 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
14025 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
14026 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
14027 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
14029 PIPE_CONF_CHECK_I(pixel_multiplier);
14030 PIPE_CONF_CHECK_I(output_format);
14031 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
14032 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
14033 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14034 PIPE_CONF_CHECK_BOOL(limited_color_range);
14036 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
14037 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
14038 PIPE_CONF_CHECK_BOOL(has_infoframe);
14039 PIPE_CONF_CHECK_BOOL(fec_enable);
14041 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
14043 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14044 DRM_MODE_FLAG_INTERLACE);
14046 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
14047 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14048 DRM_MODE_FLAG_PHSYNC);
14049 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14050 DRM_MODE_FLAG_NHSYNC);
14051 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14052 DRM_MODE_FLAG_PVSYNC);
14053 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
14054 DRM_MODE_FLAG_NVSYNC);
14057 PIPE_CONF_CHECK_X(gmch_pfit.control);
14058 /* pfit ratios are autocomputed by the hw on gen4+ */
14059 if (INTEL_GEN(dev_priv) < 4)
14060 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
14061 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
14064 * Changing the EDP transcoder input mux
14065 * (A_ONOFF vs. A_ON) requires a full modeset.
14067 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
14070 PIPE_CONF_CHECK_I(pipe_src_w);
14071 PIPE_CONF_CHECK_I(pipe_src_h);
14073 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
14074 if (current_config->pch_pfit.enabled) {
14075 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
14076 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
14077 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
14078 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
14081 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
14082 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
14084 PIPE_CONF_CHECK_X(gamma_mode);
14085 if (IS_CHERRYVIEW(dev_priv))
14086 PIPE_CONF_CHECK_X(cgm_mode);
14088 PIPE_CONF_CHECK_X(csc_mode);
14089 PIPE_CONF_CHECK_BOOL(gamma_enable);
14090 PIPE_CONF_CHECK_BOOL(csc_enable);
14092 PIPE_CONF_CHECK_I(linetime);
14093 PIPE_CONF_CHECK_I(ips_linetime);
14095 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
14097 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
14100 PIPE_CONF_CHECK_BOOL(double_wide);
14102 PIPE_CONF_CHECK_P(shared_dpll);
14103 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
14104 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
14105 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
14106 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
14107 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
14108 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
14109 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
14110 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
14111 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
14112 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
14113 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
14114 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
14115 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
14116 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
14117 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
14118 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
14119 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
14120 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
14121 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
14122 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
14123 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
14124 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
14125 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
14126 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
14127 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
14128 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
14129 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
14130 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
14131 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
14132 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
14133 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
14135 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
14136 PIPE_CONF_CHECK_X(dsi_pll.div);
14138 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
14139 PIPE_CONF_CHECK_I(pipe_bpp);
14141 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
14142 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
14144 PIPE_CONF_CHECK_I(min_voltage_level);
14146 PIPE_CONF_CHECK_X(infoframes.enable);
14147 PIPE_CONF_CHECK_X(infoframes.gcp);
14148 PIPE_CONF_CHECK_INFOFRAME(avi);
14149 PIPE_CONF_CHECK_INFOFRAME(spd);
14150 PIPE_CONF_CHECK_INFOFRAME(hdmi);
14151 PIPE_CONF_CHECK_INFOFRAME(drm);
14152 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
14154 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
14155 PIPE_CONF_CHECK_I(master_transcoder);
14157 PIPE_CONF_CHECK_I(dsc.compression_enable);
14158 PIPE_CONF_CHECK_I(dsc.dsc_split);
14159 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
14161 PIPE_CONF_CHECK_I(mst_master_transcoder);
14163 #undef PIPE_CONF_CHECK_X
14164 #undef PIPE_CONF_CHECK_I
14165 #undef PIPE_CONF_CHECK_BOOL
14166 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
14167 #undef PIPE_CONF_CHECK_P
14168 #undef PIPE_CONF_CHECK_FLAGS
14169 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
14170 #undef PIPE_CONF_CHECK_COLOR_LUT
14171 #undef PIPE_CONF_QUIRK
14176 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
14177 const struct intel_crtc_state *pipe_config)
14179 if (pipe_config->has_pch_encoder) {
14180 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
14181 &pipe_config->fdi_m_n);
14182 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
14185 * FDI already provided one idea for the dotclock.
14186 * Yell if the encoder disagrees.
14188 drm_WARN(&dev_priv->drm,
14189 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
14190 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
14191 fdi_dotclock, dotclock);
14195 static void verify_wm_state(struct intel_crtc *crtc,
14196 struct intel_crtc_state *new_crtc_state)
14198 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14199 struct skl_hw_state {
14200 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
14201 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
14202 struct skl_pipe_wm wm;
14204 struct skl_pipe_wm *sw_wm;
14205 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
14206 u8 hw_enabled_slices;
14207 const enum pipe pipe = crtc->pipe;
14208 int plane, level, max_level = ilk_wm_max_level(dev_priv);
14210 if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
14213 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
14217 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
14218 sw_wm = &new_crtc_state->wm.skl.optimal;
14220 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
14222 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
14224 if (INTEL_GEN(dev_priv) >= 11 &&
14225 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
14226 drm_err(&dev_priv->drm,
14227 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14228 dev_priv->dbuf.enabled_slices,
14229 hw_enabled_slices);
14232 for_each_universal_plane(dev_priv, pipe, plane) {
14233 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14235 hw_plane_wm = &hw->wm.planes[plane];
14236 sw_plane_wm = &sw_wm->planes[plane];
14239 for (level = 0; level <= max_level; level++) {
14240 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14241 &sw_plane_wm->wm[level]) ||
14242 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14243 &sw_plane_wm->sagv_wm0)))
14246 drm_err(&dev_priv->drm,
14247 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14248 pipe_name(pipe), plane + 1, level,
14249 sw_plane_wm->wm[level].plane_en,
14250 sw_plane_wm->wm[level].plane_res_b,
14251 sw_plane_wm->wm[level].plane_res_l,
14252 hw_plane_wm->wm[level].plane_en,
14253 hw_plane_wm->wm[level].plane_res_b,
14254 hw_plane_wm->wm[level].plane_res_l);
14257 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14258 &sw_plane_wm->trans_wm)) {
14259 drm_err(&dev_priv->drm,
14260 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14261 pipe_name(pipe), plane + 1,
14262 sw_plane_wm->trans_wm.plane_en,
14263 sw_plane_wm->trans_wm.plane_res_b,
14264 sw_plane_wm->trans_wm.plane_res_l,
14265 hw_plane_wm->trans_wm.plane_en,
14266 hw_plane_wm->trans_wm.plane_res_b,
14267 hw_plane_wm->trans_wm.plane_res_l);
14271 hw_ddb_entry = &hw->ddb_y[plane];
14272 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14274 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14275 drm_err(&dev_priv->drm,
14276 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14277 pipe_name(pipe), plane + 1,
14278 sw_ddb_entry->start, sw_ddb_entry->end,
14279 hw_ddb_entry->start, hw_ddb_entry->end);
14285 * If the cursor plane isn't active, we may not have updated it's ddb
14286 * allocation. In that case since the ddb allocation will be updated
14287 * once the plane becomes visible, we can skip this check
14290 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14292 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14293 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14296 for (level = 0; level <= max_level; level++) {
14297 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14298 &sw_plane_wm->wm[level]) ||
14299 (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
14300 &sw_plane_wm->sagv_wm0)))
14303 drm_err(&dev_priv->drm,
14304 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14305 pipe_name(pipe), level,
14306 sw_plane_wm->wm[level].plane_en,
14307 sw_plane_wm->wm[level].plane_res_b,
14308 sw_plane_wm->wm[level].plane_res_l,
14309 hw_plane_wm->wm[level].plane_en,
14310 hw_plane_wm->wm[level].plane_res_b,
14311 hw_plane_wm->wm[level].plane_res_l);
14314 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14315 &sw_plane_wm->trans_wm)) {
14316 drm_err(&dev_priv->drm,
14317 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14319 sw_plane_wm->trans_wm.plane_en,
14320 sw_plane_wm->trans_wm.plane_res_b,
14321 sw_plane_wm->trans_wm.plane_res_l,
14322 hw_plane_wm->trans_wm.plane_en,
14323 hw_plane_wm->trans_wm.plane_res_b,
14324 hw_plane_wm->trans_wm.plane_res_l);
14328 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14329 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14331 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14332 drm_err(&dev_priv->drm,
14333 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14335 sw_ddb_entry->start, sw_ddb_entry->end,
14336 hw_ddb_entry->start, hw_ddb_entry->end);
14344 verify_connector_state(struct intel_atomic_state *state,
14345 struct intel_crtc *crtc)
14347 struct drm_connector *connector;
14348 struct drm_connector_state *new_conn_state;
14351 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14352 struct drm_encoder *encoder = connector->encoder;
14353 struct intel_crtc_state *crtc_state = NULL;
14355 if (new_conn_state->crtc != &crtc->base)
14359 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14361 intel_connector_verify_state(crtc_state, new_conn_state);
14363 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14364 "connector's atomic encoder doesn't match legacy encoder\n");
14369 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14371 struct intel_encoder *encoder;
14372 struct drm_connector *connector;
14373 struct drm_connector_state *old_conn_state, *new_conn_state;
14376 for_each_intel_encoder(&dev_priv->drm, encoder) {
14377 bool enabled = false, found = false;
14380 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14381 encoder->base.base.id,
14382 encoder->base.name);
14384 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14385 new_conn_state, i) {
14386 if (old_conn_state->best_encoder == &encoder->base)
14389 if (new_conn_state->best_encoder != &encoder->base)
14391 found = enabled = true;
14393 I915_STATE_WARN(new_conn_state->crtc !=
14394 encoder->base.crtc,
14395 "connector's crtc doesn't match encoder crtc\n");
14401 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14402 "encoder's enabled state mismatch "
14403 "(expected %i, found %i)\n",
14404 !!encoder->base.crtc, enabled);
14406 if (!encoder->base.crtc) {
14409 active = encoder->get_hw_state(encoder, &pipe);
14410 I915_STATE_WARN(active,
14411 "encoder detached but still enabled on pipe %c.\n",
14418 verify_crtc_state(struct intel_crtc *crtc,
14419 struct intel_crtc_state *old_crtc_state,
14420 struct intel_crtc_state *new_crtc_state)
14422 struct drm_device *dev = crtc->base.dev;
14423 struct drm_i915_private *dev_priv = to_i915(dev);
14424 struct intel_encoder *encoder;
14425 struct intel_crtc_state *pipe_config = old_crtc_state;
14426 struct drm_atomic_state *state = old_crtc_state->uapi.state;
14428 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14429 intel_crtc_free_hw_state(old_crtc_state);
14430 intel_crtc_state_reset(old_crtc_state, crtc);
14431 old_crtc_state->uapi.state = state;
14433 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14436 pipe_config->hw.enable = new_crtc_state->hw.enable;
14438 intel_crtc_get_pipe_config(pipe_config);
14440 /* we keep both pipes enabled on 830 */
14441 if (IS_I830(dev_priv) && pipe_config->hw.active)
14442 pipe_config->hw.active = new_crtc_state->hw.active;
14444 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
14445 "crtc active state doesn't match with hw state "
14446 "(expected %i, found %i)\n",
14447 new_crtc_state->hw.active, pipe_config->hw.active);
14449 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14450 "transitional active state does not match atomic hw state "
14451 "(expected %i, found %i)\n",
14452 new_crtc_state->hw.active, crtc->active);
14454 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14458 active = encoder->get_hw_state(encoder, &pipe);
14459 I915_STATE_WARN(active != new_crtc_state->hw.active,
14460 "[ENCODER:%i] active %i with crtc active %i\n",
14461 encoder->base.base.id, active,
14462 new_crtc_state->hw.active);
14464 I915_STATE_WARN(active && crtc->pipe != pipe,
14465 "Encoder connected to wrong pipe %c\n",
14469 intel_encoder_get_config(encoder, pipe_config);
14472 intel_crtc_compute_pixel_rate(pipe_config);
14474 if (!new_crtc_state->hw.active)
14477 intel_pipe_config_sanity_check(dev_priv, pipe_config);
14479 if (!intel_pipe_config_compare(new_crtc_state,
14480 pipe_config, false)) {
14481 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14482 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14483 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14488 intel_verify_planes(struct intel_atomic_state *state)
14490 struct intel_plane *plane;
14491 const struct intel_plane_state *plane_state;
14494 for_each_new_intel_plane_in_state(state, plane,
14496 assert_plane(plane, plane_state->planar_slave ||
14497 plane_state->uapi.visible);
14501 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14502 struct intel_shared_dpll *pll,
14503 struct intel_crtc *crtc,
14504 struct intel_crtc_state *new_crtc_state)
14506 struct intel_dpll_hw_state dpll_hw_state;
14507 unsigned int crtc_mask;
14510 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14512 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14514 active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14516 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14517 I915_STATE_WARN(!pll->on && pll->active_mask,
14518 "pll in active use but not on in sw tracking\n");
14519 I915_STATE_WARN(pll->on && !pll->active_mask,
14520 "pll is on but not used by any active crtc\n");
14521 I915_STATE_WARN(pll->on != active,
14522 "pll on state mismatch (expected %i, found %i)\n",
14527 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14528 "more active pll users than references: %x vs %x\n",
14529 pll->active_mask, pll->state.crtc_mask);
14534 crtc_mask = drm_crtc_mask(&crtc->base);
14536 if (new_crtc_state->hw.active)
14537 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14538 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14539 pipe_name(crtc->pipe), pll->active_mask);
14541 I915_STATE_WARN(pll->active_mask & crtc_mask,
14542 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14543 pipe_name(crtc->pipe), pll->active_mask);
14545 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14546 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14547 crtc_mask, pll->state.crtc_mask);
14549 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14551 sizeof(dpll_hw_state)),
14552 "pll hw state mismatch\n");
14556 verify_shared_dpll_state(struct intel_crtc *crtc,
14557 struct intel_crtc_state *old_crtc_state,
14558 struct intel_crtc_state *new_crtc_state)
14560 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14562 if (new_crtc_state->shared_dpll)
14563 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14565 if (old_crtc_state->shared_dpll &&
14566 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14567 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14568 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14570 I915_STATE_WARN(pll->active_mask & crtc_mask,
14571 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14572 pipe_name(crtc->pipe));
14573 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14574 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14575 pipe_name(crtc->pipe));
14580 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14581 struct intel_atomic_state *state,
14582 struct intel_crtc_state *old_crtc_state,
14583 struct intel_crtc_state *new_crtc_state)
14585 if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14588 verify_wm_state(crtc, new_crtc_state);
14589 verify_connector_state(state, crtc);
14590 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14591 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14595 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14599 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14600 verify_single_dpll_state(dev_priv,
14601 &dev_priv->dpll.shared_dplls[i],
14606 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14607 struct intel_atomic_state *state)
14609 verify_encoder_state(dev_priv, state);
14610 verify_connector_state(state, NULL);
14611 verify_disabled_dpll_state(dev_priv);
14615 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14617 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14618 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14619 const struct drm_display_mode *adjusted_mode =
14620 &crtc_state->hw.adjusted_mode;
14622 drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14624 crtc->mode_flags = crtc_state->mode_flags;
14627 * The scanline counter increments at the leading edge of hsync.
14629 * On most platforms it starts counting from vtotal-1 on the
14630 * first active line. That means the scanline counter value is
14631 * always one less than what we would expect. Ie. just after
14632 * start of vblank, which also occurs at start of hsync (on the
14633 * last active line), the scanline counter will read vblank_start-1.
14635 * On gen2 the scanline counter starts counting from 1 instead
14636 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14637 * to keep the value positive), instead of adding one.
14639 * On HSW+ the behaviour of the scanline counter depends on the output
14640 * type. For DP ports it behaves like most other platforms, but on HDMI
14641 * there's an extra 1 line difference. So we need to add two instead of
14642 * one to the value.
14644 * On VLV/CHV DSI the scanline counter would appear to increment
14645 * approx. 1/3 of a scanline before start of vblank. Unfortunately
14646 * that means we can't tell whether we're in vblank or not while
14647 * we're on that particular line. We must still set scanline_offset
14648 * to 1 so that the vblank timestamps come out correct when we query
14649 * the scanline counter from within the vblank interrupt handler.
14650 * However if queried just before the start of vblank we'll get an
14651 * answer that's slightly in the future.
14653 if (IS_GEN(dev_priv, 2)) {
14656 vtotal = adjusted_mode->crtc_vtotal;
14657 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14660 crtc->scanline_offset = vtotal - 1;
14661 } else if (HAS_DDI(dev_priv) &&
14662 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14663 crtc->scanline_offset = 2;
14665 crtc->scanline_offset = 1;
14669 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14671 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14672 struct intel_crtc_state *new_crtc_state;
14673 struct intel_crtc *crtc;
14676 if (!dev_priv->display.crtc_compute_clock)
14679 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14680 if (!needs_modeset(new_crtc_state))
14683 intel_release_shared_dplls(state, crtc);
14688 * This implements the workaround described in the "notes" section of the mode
14689 * set sequence documentation. When going from no pipes or single pipe to
14690 * multiple pipes, and planes are enabled after the pipe, we need to wait at
14691 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14693 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14695 struct intel_crtc_state *crtc_state;
14696 struct intel_crtc *crtc;
14697 struct intel_crtc_state *first_crtc_state = NULL;
14698 struct intel_crtc_state *other_crtc_state = NULL;
14699 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14702 /* look at all crtc's that are going to be enabled in during modeset */
14703 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14704 if (!crtc_state->hw.active ||
14705 !needs_modeset(crtc_state))
14708 if (first_crtc_state) {
14709 other_crtc_state = crtc_state;
14712 first_crtc_state = crtc_state;
14713 first_pipe = crtc->pipe;
14717 /* No workaround needed? */
14718 if (!first_crtc_state)
14721 /* w/a possibly needed, check how many crtc's are already enabled. */
14722 for_each_intel_crtc(state->base.dev, crtc) {
14723 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14724 if (IS_ERR(crtc_state))
14725 return PTR_ERR(crtc_state);
14727 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14729 if (!crtc_state->hw.active ||
14730 needs_modeset(crtc_state))
14733 /* 2 or more enabled crtcs means no need for w/a */
14734 if (enabled_pipe != INVALID_PIPE)
14737 enabled_pipe = crtc->pipe;
14740 if (enabled_pipe != INVALID_PIPE)
14741 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14742 else if (other_crtc_state)
14743 other_crtc_state->hsw_workaround_pipe = first_pipe;
14748 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14751 const struct intel_crtc_state *crtc_state;
14752 struct intel_crtc *crtc;
14755 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14756 if (crtc_state->hw.active)
14757 active_pipes |= BIT(crtc->pipe);
14759 active_pipes &= ~BIT(crtc->pipe);
14762 return active_pipes;
14765 static int intel_modeset_checks(struct intel_atomic_state *state)
14767 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14769 state->modeset = true;
14771 if (IS_HASWELL(dev_priv))
14772 return hsw_mode_set_planes_workaround(state);
14778 * Handle calculation of various watermark data at the end of the atomic check
14779 * phase. The code here should be run after the per-crtc and per-plane 'check'
14780 * handlers to ensure that all derived state has been updated.
14782 static int calc_watermark_data(struct intel_atomic_state *state)
14784 struct drm_device *dev = state->base.dev;
14785 struct drm_i915_private *dev_priv = to_i915(dev);
14787 /* Is there platform-specific watermark information to calculate? */
14788 if (dev_priv->display.compute_global_watermarks)
14789 return dev_priv->display.compute_global_watermarks(state);
14794 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14795 struct intel_crtc_state *new_crtc_state)
14797 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14800 new_crtc_state->uapi.mode_changed = false;
14801 new_crtc_state->update_pipe = true;
14804 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14805 struct intel_crtc_state *new_crtc_state)
14808 * If we're not doing the full modeset we want to
14809 * keep the current M/N values as they may be
14810 * sufficiently different to the computed values
14811 * to cause problems.
14813 * FIXME: should really copy more fuzzy state here
14815 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14816 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14817 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14818 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14821 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14822 struct intel_crtc *crtc,
14825 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14826 struct intel_plane *plane;
14828 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14829 struct intel_plane_state *plane_state;
14831 if ((plane_ids_mask & BIT(plane->id)) == 0)
14834 plane_state = intel_atomic_get_plane_state(state, plane);
14835 if (IS_ERR(plane_state))
14836 return PTR_ERR(plane_state);
14842 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14844 /* See {hsw,vlv,ivb}_plane_ratio() */
14845 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14846 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14847 IS_IVYBRIDGE(dev_priv) || (INTEL_GEN(dev_priv) >= 11);
14850 static int intel_atomic_check_planes(struct intel_atomic_state *state)
14852 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14853 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14854 struct intel_plane_state *plane_state;
14855 struct intel_plane *plane;
14856 struct intel_crtc *crtc;
14859 ret = icl_add_linked_planes(state);
14863 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14864 ret = intel_plane_atomic_check(state, plane);
14866 drm_dbg_atomic(&dev_priv->drm,
14867 "[PLANE:%d:%s] atomic driver check failed\n",
14868 plane->base.base.id, plane->base.name);
14873 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14874 new_crtc_state, i) {
14875 u8 old_active_planes, new_active_planes;
14877 ret = icl_check_nv12_planes(new_crtc_state);
14882 * On some platforms the number of active planes affects
14883 * the planes' minimum cdclk calculation. Add such planes
14884 * to the state before we compute the minimum cdclk.
14886 if (!active_planes_affects_min_cdclk(dev_priv))
14889 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14890 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14893 * Not only the number of planes, but if the plane configuration had
14894 * changed might already mean we need to recompute min CDCLK,
14895 * because different planes might consume different amount of Dbuf bandwidth
14896 * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor
14898 if (old_active_planes == new_active_planes)
14901 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14909 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
14910 bool *need_cdclk_calc)
14912 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14913 const struct intel_cdclk_state *old_cdclk_state;
14914 const struct intel_cdclk_state *new_cdclk_state;
14915 struct intel_plane_state *plane_state;
14916 struct intel_bw_state *new_bw_state;
14917 struct intel_plane *plane;
14923 * active_planes bitmask has been updated, and potentially
14924 * affected planes are part of the state. We can now
14925 * compute the minimum cdclk for each plane.
14927 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14928 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14933 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
14934 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14936 if (new_cdclk_state &&
14937 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
14938 *need_cdclk_calc = true;
14940 ret = dev_priv->display.bw_calc_min_cdclk(state);
14944 new_bw_state = intel_atomic_get_new_bw_state(state);
14946 if (!new_cdclk_state || !new_bw_state)
14949 for_each_pipe(dev_priv, pipe) {
14950 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
14953 * Currently do this change only if we need to increase
14955 if (new_bw_state->min_cdclk > min_cdclk)
14956 *need_cdclk_calc = true;
14962 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14964 struct intel_crtc_state *crtc_state;
14965 struct intel_crtc *crtc;
14968 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14969 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14972 ret = intel_crtc_atomic_check(state, crtc);
14974 drm_dbg_atomic(&i915->drm,
14975 "[CRTC:%d:%s] atomic driver check failed\n",
14976 crtc->base.base.id, crtc->base.name);
14984 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14987 const struct intel_crtc_state *new_crtc_state;
14988 struct intel_crtc *crtc;
14991 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14992 if (new_crtc_state->hw.enable &&
14993 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14994 needs_modeset(new_crtc_state))
15002 * DOC: asynchronous flip implementation
15004 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
15005 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
15006 * Correspondingly, support is currently added for primary plane only.
15008 * Async flip can only change the plane surface address, so anything else
15009 * changing is rejected from the intel_atomic_check_async() function.
15010 * Once this check is cleared, flip done interrupt is enabled using
15011 * the skl_enable_flip_done() function.
15013 * As soon as the surface address register is written, flip done interrupt is
15014 * generated and the requested events are sent to the usersapce in the interrupt
15015 * handler itself. The timestamp and sequence sent during the flip done event
15016 * correspond to the last vblank and have no relation to the actual time when
15017 * the flip done event was sent.
15019 static int intel_atomic_check_async(struct intel_atomic_state *state)
15021 struct drm_i915_private *i915 = to_i915(state->base.dev);
15022 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15023 const struct intel_plane_state *new_plane_state, *old_plane_state;
15024 struct intel_crtc *crtc;
15025 struct intel_plane *plane;
15028 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15029 new_crtc_state, i) {
15030 if (needs_modeset(new_crtc_state)) {
15031 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
15035 if (!new_crtc_state->hw.active) {
15036 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
15039 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
15040 drm_dbg_kms(&i915->drm,
15041 "Active planes cannot be changed during async flip\n");
15046 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15047 new_plane_state, i) {
15049 * TODO: Async flip is only supported through the page flip IOCTL
15050 * as of now. So support currently added for primary plane only.
15051 * Support for other planes on platforms on which supports
15052 * this(vlv/chv and icl+) should be added when async flip is
15053 * enabled in the atomic IOCTL path.
15055 if (plane->id != PLANE_PRIMARY)
15059 * FIXME: This check is kept generic for all platforms.
15060 * Need to verify this for all gen9 and gen10 platforms to enable
15061 * this selectively if required.
15063 switch (new_plane_state->hw.fb->modifier) {
15064 case I915_FORMAT_MOD_X_TILED:
15065 case I915_FORMAT_MOD_Y_TILED:
15066 case I915_FORMAT_MOD_Yf_TILED:
15069 drm_dbg_kms(&i915->drm,
15070 "Linear memory/CCS does not support async flips\n");
15074 if (old_plane_state->color_plane[0].stride !=
15075 new_plane_state->color_plane[0].stride) {
15076 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
15080 if (old_plane_state->hw.fb->modifier !=
15081 new_plane_state->hw.fb->modifier) {
15082 drm_dbg_kms(&i915->drm,
15083 "Framebuffer modifiers cannot be changed in async flip\n");
15087 if (old_plane_state->hw.fb->format !=
15088 new_plane_state->hw.fb->format) {
15089 drm_dbg_kms(&i915->drm,
15090 "Framebuffer format cannot be changed in async flip\n");
15094 if (old_plane_state->hw.rotation !=
15095 new_plane_state->hw.rotation) {
15096 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
15100 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
15101 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
15102 drm_dbg_kms(&i915->drm,
15103 "Plane size/co-ordinates cannot be changed in async flip\n");
15107 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
15108 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
15112 if (old_plane_state->hw.pixel_blend_mode !=
15113 new_plane_state->hw.pixel_blend_mode) {
15114 drm_dbg_kms(&i915->drm,
15115 "Pixel blend mode cannot be changed in async flip\n");
15119 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
15120 drm_dbg_kms(&i915->drm,
15121 "Color encoding cannot be changed in async flip\n");
15125 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
15126 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
15135 * intel_atomic_check - validate state object
15137 * @_state: state to validate
15139 static int intel_atomic_check(struct drm_device *dev,
15140 struct drm_atomic_state *_state)
15142 struct drm_i915_private *dev_priv = to_i915(dev);
15143 struct intel_atomic_state *state = to_intel_atomic_state(_state);
15144 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15145 struct intel_crtc *crtc;
15147 bool any_ms = false;
15149 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15150 new_crtc_state, i) {
15151 if (new_crtc_state->inherited != old_crtc_state->inherited)
15152 new_crtc_state->uapi.mode_changed = true;
15155 ret = drm_atomic_helper_check_modeset(dev, &state->base);
15159 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15160 new_crtc_state, i) {
15161 if (!needs_modeset(new_crtc_state)) {
15163 intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
15168 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
15172 if (!new_crtc_state->hw.enable)
15175 ret = intel_modeset_pipe_config(new_crtc_state);
15180 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15181 new_crtc_state, i) {
15182 if (!needs_modeset(new_crtc_state))
15185 ret = intel_modeset_pipe_config_late(new_crtc_state);
15189 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
15193 * Check if fastset is allowed by external dependencies like other
15194 * pipes and transcoders.
15196 * Right now it only forces a fullmodeset when the MST master
15197 * transcoder did not changed but the pipe of the master transcoder
15198 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
15199 * in case of port synced crtcs, if one of the synced crtcs
15200 * needs a full modeset, all other synced crtcs should be
15201 * forced a full modeset.
15203 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15204 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
15207 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
15208 enum transcoder master = new_crtc_state->mst_master_transcoder;
15210 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
15211 new_crtc_state->uapi.mode_changed = true;
15212 new_crtc_state->update_pipe = false;
15216 if (is_trans_port_sync_mode(new_crtc_state)) {
15217 u8 trans = new_crtc_state->sync_mode_slaves_mask;
15219 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
15220 trans |= BIT(new_crtc_state->master_transcoder);
15222 if (intel_cpu_transcoders_need_modeset(state, trans)) {
15223 new_crtc_state->uapi.mode_changed = true;
15224 new_crtc_state->update_pipe = false;
15229 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15230 new_crtc_state, i) {
15231 if (needs_modeset(new_crtc_state)) {
15236 if (!new_crtc_state->update_pipe)
15239 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
15242 if (any_ms && !check_digital_port_conflicts(state)) {
15243 drm_dbg_kms(&dev_priv->drm,
15244 "rejecting conflicting digital port configuration\n");
15249 ret = drm_dp_mst_atomic_check(&state->base);
15253 ret = intel_atomic_check_planes(state);
15258 * distrust_bios_wm will force a full dbuf recomputation
15259 * but the hardware state will only get updated accordingly
15260 * if state->modeset==true. Hence distrust_bios_wm==true &&
15261 * state->modeset==false is an invalid combination which
15262 * would cause the hardware and software dbuf state to get
15263 * out of sync. We must prevent that.
15265 * FIXME clean up this mess and introduce better
15266 * state tracking for dbuf.
15268 if (dev_priv->wm.distrust_bios_wm)
15271 intel_fbc_choose_crtc(dev_priv, state);
15272 ret = calc_watermark_data(state);
15276 ret = intel_bw_atomic_check(state);
15280 ret = intel_atomic_check_cdclk(state, &any_ms);
15285 ret = intel_modeset_checks(state);
15289 ret = intel_modeset_calc_cdclk(state);
15293 intel_modeset_clear_plls(state);
15296 ret = intel_atomic_check_crtcs(state);
15300 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15301 new_crtc_state, i) {
15302 if (new_crtc_state->uapi.async_flip) {
15303 ret = intel_atomic_check_async(state);
15308 if (!needs_modeset(new_crtc_state) &&
15309 !new_crtc_state->update_pipe)
15312 intel_dump_pipe_config(new_crtc_state, state,
15313 needs_modeset(new_crtc_state) ?
15314 "[modeset]" : "[fastset]");
15320 if (ret == -EDEADLK)
15324 * FIXME would probably be nice to know which crtc specifically
15325 * caused the failure, in cases where we can pinpoint it.
15327 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15329 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
15334 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
15336 struct intel_crtc_state *crtc_state;
15337 struct intel_crtc *crtc;
15340 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
15344 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
15345 bool mode_changed = needs_modeset(crtc_state);
15347 if (mode_changed || crtc_state->update_pipe ||
15348 crtc_state->uapi.color_mgmt_changed) {
15349 intel_dsb_prepare(crtc_state);
15356 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
15358 struct drm_device *dev = crtc->base.dev;
15359 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
15361 if (!vblank->max_vblank_count)
15362 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
15364 return crtc->base.funcs->get_vblank_counter(&crtc->base);
15367 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
15368 struct intel_crtc_state *crtc_state)
15370 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15372 if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
15373 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15375 if (crtc_state->has_pch_encoder) {
15376 enum pipe pch_transcoder =
15377 intel_crtc_pch_transcoder(crtc);
15379 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
15383 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
15384 const struct intel_crtc_state *new_crtc_state)
15386 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15387 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15390 * Update pipe size and adjust fitter if needed: the reason for this is
15391 * that in compute_mode_changes we check the native mode (not the pfit
15392 * mode) to see if we can flip rather than do a full mode set. In the
15393 * fastboot case, we'll flip, but if we don't update the pipesrc and
15394 * pfit state, we'll end up with a big fb scanned out into the wrong
15397 intel_set_pipe_src_size(new_crtc_state);
15399 /* on skylake this is done by detaching scalers */
15400 if (INTEL_GEN(dev_priv) >= 9) {
15401 skl_detach_scalers(new_crtc_state);
15403 if (new_crtc_state->pch_pfit.enabled)
15404 skl_pfit_enable(new_crtc_state);
15405 } else if (HAS_PCH_SPLIT(dev_priv)) {
15406 if (new_crtc_state->pch_pfit.enabled)
15407 ilk_pfit_enable(new_crtc_state);
15408 else if (old_crtc_state->pch_pfit.enabled)
15409 ilk_pfit_disable(old_crtc_state);
15413 * The register is supposedly single buffered so perhaps
15414 * not 100% correct to do this here. But SKL+ calculate
15415 * this based on the adjust pixel rate so pfit changes do
15416 * affect it and so it must be updated for fastsets.
15417 * HSW/BDW only really need this here for fastboot, after
15418 * that the value should not change without a full modeset.
15420 if (INTEL_GEN(dev_priv) >= 9 ||
15421 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
15422 hsw_set_linetime_wm(new_crtc_state);
15424 if (INTEL_GEN(dev_priv) >= 11)
15425 icl_set_pipe_chicken(crtc);
15428 static void commit_pipe_config(struct intel_atomic_state *state,
15429 struct intel_crtc *crtc)
15431 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15432 const struct intel_crtc_state *old_crtc_state =
15433 intel_atomic_get_old_crtc_state(state, crtc);
15434 const struct intel_crtc_state *new_crtc_state =
15435 intel_atomic_get_new_crtc_state(state, crtc);
15436 bool modeset = needs_modeset(new_crtc_state);
15439 * During modesets pipe configuration was programmed as the
15440 * CRTC was enabled.
15443 if (new_crtc_state->uapi.color_mgmt_changed ||
15444 new_crtc_state->update_pipe)
15445 intel_color_commit(new_crtc_state);
15447 if (INTEL_GEN(dev_priv) >= 9)
15448 skl_detach_scalers(new_crtc_state);
15450 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15451 bdw_set_pipemisc(new_crtc_state);
15453 if (new_crtc_state->update_pipe)
15454 intel_pipe_fastset(old_crtc_state, new_crtc_state);
15456 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
15459 if (dev_priv->display.atomic_update_watermarks)
15460 dev_priv->display.atomic_update_watermarks(state, crtc);
15463 static void intel_enable_crtc(struct intel_atomic_state *state,
15464 struct intel_crtc *crtc)
15466 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15467 const struct intel_crtc_state *new_crtc_state =
15468 intel_atomic_get_new_crtc_state(state, crtc);
15470 if (!needs_modeset(new_crtc_state))
15473 intel_crtc_update_active_timings(new_crtc_state);
15475 dev_priv->display.crtc_enable(state, crtc);
15477 /* vblanks work again, re-enable pipe CRC. */
15478 intel_crtc_enable_pipe_crc(crtc);
15481 static void intel_update_crtc(struct intel_atomic_state *state,
15482 struct intel_crtc *crtc)
15484 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15485 const struct intel_crtc_state *old_crtc_state =
15486 intel_atomic_get_old_crtc_state(state, crtc);
15487 struct intel_crtc_state *new_crtc_state =
15488 intel_atomic_get_new_crtc_state(state, crtc);
15489 bool modeset = needs_modeset(new_crtc_state);
15492 if (new_crtc_state->preload_luts &&
15493 (new_crtc_state->uapi.color_mgmt_changed ||
15494 new_crtc_state->update_pipe))
15495 intel_color_load_luts(new_crtc_state);
15497 intel_pre_plane_update(state, crtc);
15499 if (new_crtc_state->update_pipe)
15500 intel_encoders_update_pipe(state, crtc);
15503 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15504 intel_fbc_disable(crtc);
15506 intel_fbc_enable(state, crtc);
15508 /* Perform vblank evasion around commit operation */
15509 intel_pipe_update_start(new_crtc_state);
15511 commit_pipe_config(state, crtc);
15513 if (INTEL_GEN(dev_priv) >= 9)
15514 skl_update_planes_on_crtc(state, crtc);
15516 i9xx_update_planes_on_crtc(state, crtc);
15518 intel_pipe_update_end(new_crtc_state);
15521 * We usually enable FIFO underrun interrupts as part of the
15522 * CRTC enable sequence during modesets. But when we inherit a
15523 * valid pipe configuration from the BIOS we need to take care
15524 * of enabling them on the CRTC's first fastset.
15526 if (new_crtc_state->update_pipe && !modeset &&
15527 old_crtc_state->inherited)
15528 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15532 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15533 struct intel_crtc_state *old_crtc_state,
15534 struct intel_crtc_state *new_crtc_state,
15535 struct intel_crtc *crtc)
15537 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15539 intel_crtc_disable_planes(state, crtc);
15542 * We need to disable pipe CRC before disabling the pipe,
15543 * or we race against vblank off.
15545 intel_crtc_disable_pipe_crc(crtc);
15547 dev_priv->display.crtc_disable(state, crtc);
15548 crtc->active = false;
15549 intel_fbc_disable(crtc);
15550 intel_disable_shared_dpll(old_crtc_state);
15552 /* FIXME unify this for all platforms */
15553 if (!new_crtc_state->hw.active &&
15554 !HAS_GMCH(dev_priv) &&
15555 dev_priv->display.initial_watermarks)
15556 dev_priv->display.initial_watermarks(state, crtc);
15559 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15561 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15562 struct intel_crtc *crtc;
15566 /* Only disable port sync and MST slaves */
15567 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15568 new_crtc_state, i) {
15569 if (!needs_modeset(new_crtc_state))
15572 if (!old_crtc_state->hw.active)
15575 /* In case of Transcoder port Sync master slave CRTCs can be
15576 * assigned in any order and we need to make sure that
15577 * slave CRTCs are disabled first and then master CRTC since
15578 * Slave vblanks are masked till Master Vblanks.
15580 if (!is_trans_port_sync_slave(old_crtc_state) &&
15581 !intel_dp_mst_is_slave_trans(old_crtc_state))
15584 intel_pre_plane_update(state, crtc);
15585 intel_old_crtc_state_disables(state, old_crtc_state,
15586 new_crtc_state, crtc);
15587 handled |= BIT(crtc->pipe);
15590 /* Disable everything else left on */
15591 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15592 new_crtc_state, i) {
15593 if (!needs_modeset(new_crtc_state) ||
15594 (handled & BIT(crtc->pipe)))
15597 intel_pre_plane_update(state, crtc);
15598 if (old_crtc_state->hw.active)
15599 intel_old_crtc_state_disables(state, old_crtc_state,
15600 new_crtc_state, crtc);
15604 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15606 struct intel_crtc_state *new_crtc_state;
15607 struct intel_crtc *crtc;
15610 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15611 if (!new_crtc_state->hw.active)
15614 intel_enable_crtc(state, crtc);
15615 intel_update_crtc(state, crtc);
15619 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15621 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15622 struct intel_crtc *crtc;
15623 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15624 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15625 u8 update_pipes = 0, modeset_pipes = 0;
15628 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15629 enum pipe pipe = crtc->pipe;
15631 if (!new_crtc_state->hw.active)
15634 /* ignore allocations for crtc's that have been turned off. */
15635 if (!needs_modeset(new_crtc_state)) {
15636 entries[pipe] = old_crtc_state->wm.skl.ddb;
15637 update_pipes |= BIT(pipe);
15639 modeset_pipes |= BIT(pipe);
15644 * Whenever the number of active pipes changes, we need to make sure we
15645 * update the pipes in the right order so that their ddb allocations
15646 * never overlap with each other between CRTC updates. Otherwise we'll
15647 * cause pipe underruns and other bad stuff.
15649 * So first lets enable all pipes that do not need a fullmodeset as
15650 * those don't have any external dependency.
15652 while (update_pipes) {
15653 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15654 new_crtc_state, i) {
15655 enum pipe pipe = crtc->pipe;
15657 if ((update_pipes & BIT(pipe)) == 0)
15660 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15661 entries, I915_MAX_PIPES, pipe))
15664 entries[pipe] = new_crtc_state->wm.skl.ddb;
15665 update_pipes &= ~BIT(pipe);
15667 intel_update_crtc(state, crtc);
15670 * If this is an already active pipe, it's DDB changed,
15671 * and this isn't the last pipe that needs updating
15672 * then we need to wait for a vblank to pass for the
15673 * new ddb allocation to take effect.
15675 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15676 &old_crtc_state->wm.skl.ddb) &&
15677 (update_pipes | modeset_pipes))
15678 intel_wait_for_vblank(dev_priv, pipe);
15682 update_pipes = modeset_pipes;
15685 * Enable all pipes that needs a modeset and do not depends on other
15688 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15689 enum pipe pipe = crtc->pipe;
15691 if ((modeset_pipes & BIT(pipe)) == 0)
15694 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15695 is_trans_port_sync_master(new_crtc_state))
15698 modeset_pipes &= ~BIT(pipe);
15700 intel_enable_crtc(state, crtc);
15704 * Then we enable all remaining pipes that depend on other
15705 * pipes: MST slaves and port sync masters.
15707 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15708 enum pipe pipe = crtc->pipe;
15710 if ((modeset_pipes & BIT(pipe)) == 0)
15713 modeset_pipes &= ~BIT(pipe);
15715 intel_enable_crtc(state, crtc);
15719 * Finally we do the plane updates/etc. for all pipes that got enabled.
15721 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15722 enum pipe pipe = crtc->pipe;
15724 if ((update_pipes & BIT(pipe)) == 0)
15727 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15728 entries, I915_MAX_PIPES, pipe));
15730 entries[pipe] = new_crtc_state->wm.skl.ddb;
15731 update_pipes &= ~BIT(pipe);
15733 intel_update_crtc(state, crtc);
15736 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15737 drm_WARN_ON(&dev_priv->drm, update_pipes);
15740 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15742 struct intel_atomic_state *state, *next;
15743 struct llist_node *freed;
15745 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15746 llist_for_each_entry_safe(state, next, freed, freed)
15747 drm_atomic_state_put(&state->base);
15750 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15752 struct drm_i915_private *dev_priv =
15753 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15755 intel_atomic_helper_free_state(dev_priv);
15758 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15760 struct wait_queue_entry wait_fence, wait_reset;
15761 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15763 init_wait_entry(&wait_fence, 0);
15764 init_wait_entry(&wait_reset, 0);
15766 prepare_to_wait(&intel_state->commit_ready.wait,
15767 &wait_fence, TASK_UNINTERRUPTIBLE);
15768 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15769 I915_RESET_MODESET),
15770 &wait_reset, TASK_UNINTERRUPTIBLE);
15773 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15774 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15779 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15780 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15781 I915_RESET_MODESET),
15785 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
15787 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15788 struct intel_crtc *crtc;
15791 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15793 intel_dsb_cleanup(old_crtc_state);
15796 static void intel_atomic_cleanup_work(struct work_struct *work)
15798 struct intel_atomic_state *state =
15799 container_of(work, struct intel_atomic_state, base.commit_work);
15800 struct drm_i915_private *i915 = to_i915(state->base.dev);
15802 intel_cleanup_dsbs(state);
15803 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
15804 drm_atomic_helper_commit_cleanup_done(&state->base);
15805 drm_atomic_state_put(&state->base);
15807 intel_atomic_helper_free_state(i915);
15810 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15812 struct drm_device *dev = state->base.dev;
15813 struct drm_i915_private *dev_priv = to_i915(dev);
15814 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15815 struct intel_crtc *crtc;
15816 u64 put_domains[I915_MAX_PIPES] = {};
15817 intel_wakeref_t wakeref = 0;
15820 intel_atomic_commit_fence_wait(state);
15822 drm_atomic_helper_wait_for_dependencies(&state->base);
15824 if (state->modeset)
15825 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15827 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15828 new_crtc_state, i) {
15829 if (needs_modeset(new_crtc_state) ||
15830 new_crtc_state->update_pipe) {
15832 put_domains[crtc->pipe] =
15833 modeset_get_crtc_power_domains(new_crtc_state);
15837 intel_commit_modeset_disables(state);
15839 /* FIXME: Eventually get rid of our crtc->config pointer */
15840 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15841 crtc->config = new_crtc_state;
15843 if (state->modeset) {
15844 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15846 intel_set_cdclk_pre_plane_update(state);
15848 intel_modeset_verify_disabled(dev_priv, state);
15851 intel_sagv_pre_plane_update(state);
15853 /* Complete the events for pipes that have now been disabled */
15854 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15855 bool modeset = needs_modeset(new_crtc_state);
15857 /* Complete events for now disable pipes here. */
15858 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15859 spin_lock_irq(&dev->event_lock);
15860 drm_crtc_send_vblank_event(&crtc->base,
15861 new_crtc_state->uapi.event);
15862 spin_unlock_irq(&dev->event_lock);
15864 new_crtc_state->uapi.event = NULL;
15868 if (state->modeset)
15869 intel_encoders_update_prepare(state);
15871 intel_dbuf_pre_plane_update(state);
15873 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15874 if (new_crtc_state->uapi.async_flip)
15875 skl_enable_flip_done(crtc);
15878 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15879 dev_priv->display.commit_modeset_enables(state);
15881 if (state->modeset) {
15882 intel_encoders_update_complete(state);
15884 intel_set_cdclk_post_plane_update(state);
15887 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15888 * already, but still need the state for the delayed optimization. To
15890 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15891 * - schedule that vblank worker _before_ calling hw_done
15892 * - at the start of commit_tail, cancel it _synchrously
15893 * - switch over to the vblank wait helper in the core after that since
15894 * we don't need out special handling any more.
15896 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15898 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15899 if (new_crtc_state->uapi.async_flip)
15900 skl_disable_flip_done(crtc);
15902 if (new_crtc_state->hw.active &&
15903 !needs_modeset(new_crtc_state) &&
15904 !new_crtc_state->preload_luts &&
15905 (new_crtc_state->uapi.color_mgmt_changed ||
15906 new_crtc_state->update_pipe))
15907 intel_color_load_luts(new_crtc_state);
15911 * Now that the vblank has passed, we can go ahead and program the
15912 * optimal watermarks on platforms that need two-step watermark
15915 * TODO: Move this (and other cleanup) to an async worker eventually.
15917 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15918 new_crtc_state, i) {
15920 * Gen2 reports pipe underruns whenever all planes are disabled.
15921 * So re-enable underrun reporting after some planes get enabled.
15923 * We do this before .optimize_watermarks() so that we have a
15924 * chance of catching underruns with the intermediate watermarks
15925 * vs. the new plane configuration.
15927 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15928 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15930 if (dev_priv->display.optimize_watermarks)
15931 dev_priv->display.optimize_watermarks(state, crtc);
15934 intel_dbuf_post_plane_update(state);
15936 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15937 intel_post_plane_update(state, crtc);
15939 if (put_domains[i])
15940 modeset_put_power_domains(dev_priv, put_domains[i]);
15942 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15945 * DSB cleanup is done in cleanup_work aligning with framebuffer
15946 * cleanup. So copy and reset the dsb structure to sync with
15947 * commit_done and later do dsb cleanup in cleanup_work.
15949 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
15952 /* Underruns don't always raise interrupts, so check manually */
15953 intel_check_cpu_fifo_underruns(dev_priv);
15954 intel_check_pch_fifo_underruns(dev_priv);
15956 if (state->modeset)
15957 intel_verify_planes(state);
15959 intel_sagv_post_plane_update(state);
15961 drm_atomic_helper_commit_hw_done(&state->base);
15963 if (state->modeset) {
15964 /* As one of the primary mmio accessors, KMS has a high
15965 * likelihood of triggering bugs in unclaimed access. After we
15966 * finish modesetting, see if an error has been flagged, and if
15967 * so enable debugging for the next modeset - and hope we catch
15970 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15971 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15973 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15976 * Defer the cleanup of the old state to a separate worker to not
15977 * impede the current task (userspace for blocking modesets) that
15978 * are executed inline. For out-of-line asynchronous modesets/flips,
15979 * deferring to a new worker seems overkill, but we would place a
15980 * schedule point (cond_resched()) here anyway to keep latencies
15983 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15984 queue_work(system_highpri_wq, &state->base.commit_work);
15987 static void intel_atomic_commit_work(struct work_struct *work)
15989 struct intel_atomic_state *state =
15990 container_of(work, struct intel_atomic_state, base.commit_work);
15992 intel_atomic_commit_tail(state);
15995 static int __i915_sw_fence_call
15996 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15997 enum i915_sw_fence_notify notify)
15999 struct intel_atomic_state *state =
16000 container_of(fence, struct intel_atomic_state, commit_ready);
16003 case FENCE_COMPLETE:
16004 /* we do blocking waits in the worker, nothing to do here */
16008 struct intel_atomic_helper *helper =
16009 &to_i915(state->base.dev)->atomic_helper;
16011 if (llist_add(&state->freed, &helper->free_list))
16012 schedule_work(&helper->free_work);
16017 return NOTIFY_DONE;
16020 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
16022 struct intel_plane_state *old_plane_state, *new_plane_state;
16023 struct intel_plane *plane;
16026 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
16027 new_plane_state, i)
16028 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16029 to_intel_frontbuffer(new_plane_state->hw.fb),
16030 plane->frontbuffer_bit);
16033 static int intel_atomic_commit(struct drm_device *dev,
16034 struct drm_atomic_state *_state,
16037 struct intel_atomic_state *state = to_intel_atomic_state(_state);
16038 struct drm_i915_private *dev_priv = to_i915(dev);
16041 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
16043 drm_atomic_state_get(&state->base);
16044 i915_sw_fence_init(&state->commit_ready,
16045 intel_atomic_commit_ready);
16048 * The intel_legacy_cursor_update() fast path takes care
16049 * of avoiding the vblank waits for simple cursor
16050 * movement and flips. For cursor on/off and size changes,
16051 * we want to perform the vblank waits so that watermark
16052 * updates happen during the correct frames. Gen9+ have
16053 * double buffered watermarks and so shouldn't need this.
16055 * Unset state->legacy_cursor_update before the call to
16056 * drm_atomic_helper_setup_commit() because otherwise
16057 * drm_atomic_helper_wait_for_flip_done() is a noop and
16058 * we get FIFO underruns because we didn't wait
16061 * FIXME doing watermarks and fb cleanup from a vblank worker
16062 * (assuming we had any) would solve these problems.
16064 if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
16065 struct intel_crtc_state *new_crtc_state;
16066 struct intel_crtc *crtc;
16069 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16070 if (new_crtc_state->wm.need_postvbl_update ||
16071 new_crtc_state->update_wm_post)
16072 state->base.legacy_cursor_update = false;
16075 ret = intel_atomic_prepare_commit(state);
16077 drm_dbg_atomic(&dev_priv->drm,
16078 "Preparing state failed with %i\n", ret);
16079 i915_sw_fence_commit(&state->commit_ready);
16080 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16084 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
16086 ret = drm_atomic_helper_swap_state(&state->base, true);
16088 intel_atomic_swap_global_state(state);
16091 struct intel_crtc_state *new_crtc_state;
16092 struct intel_crtc *crtc;
16095 i915_sw_fence_commit(&state->commit_ready);
16097 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
16098 intel_dsb_cleanup(new_crtc_state);
16100 drm_atomic_helper_cleanup_planes(dev, &state->base);
16101 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
16104 dev_priv->wm.distrust_bios_wm = false;
16105 intel_shared_dpll_swap_state(state);
16106 intel_atomic_track_fbs(state);
16108 drm_atomic_state_get(&state->base);
16109 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
16111 i915_sw_fence_commit(&state->commit_ready);
16112 if (nonblock && state->modeset) {
16113 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
16114 } else if (nonblock) {
16115 queue_work(dev_priv->flip_wq, &state->base.commit_work);
16117 if (state->modeset)
16118 flush_workqueue(dev_priv->modeset_wq);
16119 intel_atomic_commit_tail(state);
16125 struct wait_rps_boost {
16126 struct wait_queue_entry wait;
16128 struct drm_crtc *crtc;
16129 struct i915_request *request;
16132 static int do_rps_boost(struct wait_queue_entry *_wait,
16133 unsigned mode, int sync, void *key)
16135 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
16136 struct i915_request *rq = wait->request;
16139 * If we missed the vblank, but the request is already running it
16140 * is reasonable to assume that it will complete before the next
16141 * vblank without our intervention, so leave RPS alone.
16143 if (!i915_request_started(rq))
16144 intel_rps_boost(rq);
16145 i915_request_put(rq);
16147 drm_crtc_vblank_put(wait->crtc);
16149 list_del(&wait->wait.entry);
16154 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
16155 struct dma_fence *fence)
16157 struct wait_rps_boost *wait;
16159 if (!dma_fence_is_i915(fence))
16162 if (INTEL_GEN(to_i915(crtc->dev)) < 6)
16165 if (drm_crtc_vblank_get(crtc))
16168 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
16170 drm_crtc_vblank_put(crtc);
16174 wait->request = to_request(dma_fence_get(fence));
16177 wait->wait.func = do_rps_boost;
16178 wait->wait.flags = 0;
16180 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
16183 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
16185 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
16186 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16187 struct drm_framebuffer *fb = plane_state->hw.fb;
16188 struct i915_vma *vma;
16190 if (plane->id == PLANE_CURSOR &&
16191 INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
16192 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
16193 const int align = intel_cursor_alignment(dev_priv);
16196 err = i915_gem_object_attach_phys(obj, align);
16201 vma = intel_pin_and_fence_fb_obj(fb,
16202 &plane_state->view,
16203 intel_plane_uses_fence(plane_state),
16204 &plane_state->flags);
16206 return PTR_ERR(vma);
16208 plane_state->vma = vma;
16213 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
16215 struct i915_vma *vma;
16217 vma = fetch_and_zero(&old_plane_state->vma);
16219 intel_unpin_fb_vma(vma, old_plane_state->flags);
16222 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
16224 struct i915_sched_attr attr = {
16225 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
16228 i915_gem_object_wait_priority(obj, 0, &attr);
16232 * intel_prepare_plane_fb - Prepare fb for usage on plane
16233 * @_plane: drm plane to prepare for
16234 * @_new_plane_state: the plane state being prepared
16236 * Prepares a framebuffer for usage on a display plane. Generally this
16237 * involves pinning the underlying object and updating the frontbuffer tracking
16238 * bits. Some older platforms need special physical address handling for
16241 * Returns 0 on success, negative error code on failure.
16244 intel_prepare_plane_fb(struct drm_plane *_plane,
16245 struct drm_plane_state *_new_plane_state)
16247 struct intel_plane *plane = to_intel_plane(_plane);
16248 struct intel_plane_state *new_plane_state =
16249 to_intel_plane_state(_new_plane_state);
16250 struct intel_atomic_state *state =
16251 to_intel_atomic_state(new_plane_state->uapi.state);
16252 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16253 const struct intel_plane_state *old_plane_state =
16254 intel_atomic_get_old_plane_state(state, plane);
16255 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
16256 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
16260 const struct intel_crtc_state *crtc_state =
16261 intel_atomic_get_new_crtc_state(state,
16262 to_intel_crtc(old_plane_state->hw.crtc));
16264 /* Big Hammer, we also need to ensure that any pending
16265 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
16266 * current scanout is retired before unpinning the old
16267 * framebuffer. Note that we rely on userspace rendering
16268 * into the buffer attached to the pipe they are waiting
16269 * on. If not, userspace generates a GPU hang with IPEHR
16270 * point to the MI_WAIT_FOR_EVENT.
16272 * This should only fail upon a hung GPU, in which case we
16273 * can safely continue.
16275 if (needs_modeset(crtc_state)) {
16276 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16277 old_obj->base.resv, NULL,
16285 if (new_plane_state->uapi.fence) { /* explicit fencing */
16286 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
16287 new_plane_state->uapi.fence,
16288 i915_fence_timeout(dev_priv),
16297 ret = i915_gem_object_pin_pages(obj);
16301 ret = intel_plane_pin_fb(new_plane_state);
16303 i915_gem_object_unpin_pages(obj);
16307 fb_obj_bump_render_priority(obj);
16308 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16310 if (!new_plane_state->uapi.fence) { /* implicit fencing */
16311 struct dma_fence *fence;
16313 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16314 obj->base.resv, NULL,
16316 i915_fence_timeout(dev_priv),
16321 fence = dma_resv_get_excl_rcu(obj->base.resv);
16323 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16325 dma_fence_put(fence);
16328 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16329 new_plane_state->uapi.fence);
16333 * We declare pageflips to be interactive and so merit a small bias
16334 * towards upclocking to deliver the frame on time. By only changing
16335 * the RPS thresholds to sample more regularly and aim for higher
16336 * clocks we can hopefully deliver low power workloads (like kodi)
16337 * that are not quite steady state without resorting to forcing
16338 * maximum clocks following a vblank miss (see do_rps_boost()).
16340 if (!state->rps_interactive) {
16341 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16342 state->rps_interactive = true;
16348 intel_plane_unpin_fb(new_plane_state);
16354 * intel_cleanup_plane_fb - Cleans up an fb after plane use
16355 * @plane: drm plane to clean up for
16356 * @_old_plane_state: the state from the previous modeset
16358 * Cleans up a framebuffer that has just been removed from a plane.
16361 intel_cleanup_plane_fb(struct drm_plane *plane,
16362 struct drm_plane_state *_old_plane_state)
16364 struct intel_plane_state *old_plane_state =
16365 to_intel_plane_state(_old_plane_state);
16366 struct intel_atomic_state *state =
16367 to_intel_atomic_state(old_plane_state->uapi.state);
16368 struct drm_i915_private *dev_priv = to_i915(plane->dev);
16369 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16374 if (state->rps_interactive) {
16375 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16376 state->rps_interactive = false;
16379 /* Should only be called after a successful intel_prepare_plane_fb()! */
16380 intel_plane_unpin_fb(old_plane_state);
16384 * intel_plane_destroy - destroy a plane
16385 * @plane: plane to destroy
16387 * Common destruction function for all types of planes (primary, cursor,
16390 void intel_plane_destroy(struct drm_plane *plane)
16392 drm_plane_cleanup(plane);
16393 kfree(to_intel_plane(plane));
16396 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16397 u32 format, u64 modifier)
16399 switch (modifier) {
16400 case DRM_FORMAT_MOD_LINEAR:
16401 case I915_FORMAT_MOD_X_TILED:
16408 case DRM_FORMAT_C8:
16409 case DRM_FORMAT_RGB565:
16410 case DRM_FORMAT_XRGB1555:
16411 case DRM_FORMAT_XRGB8888:
16412 return modifier == DRM_FORMAT_MOD_LINEAR ||
16413 modifier == I915_FORMAT_MOD_X_TILED;
16419 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16420 u32 format, u64 modifier)
16422 switch (modifier) {
16423 case DRM_FORMAT_MOD_LINEAR:
16424 case I915_FORMAT_MOD_X_TILED:
16431 case DRM_FORMAT_C8:
16432 case DRM_FORMAT_RGB565:
16433 case DRM_FORMAT_XRGB8888:
16434 case DRM_FORMAT_XBGR8888:
16435 case DRM_FORMAT_ARGB8888:
16436 case DRM_FORMAT_ABGR8888:
16437 case DRM_FORMAT_XRGB2101010:
16438 case DRM_FORMAT_XBGR2101010:
16439 case DRM_FORMAT_ARGB2101010:
16440 case DRM_FORMAT_ABGR2101010:
16441 case DRM_FORMAT_XBGR16161616F:
16442 return modifier == DRM_FORMAT_MOD_LINEAR ||
16443 modifier == I915_FORMAT_MOD_X_TILED;
16449 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16450 u32 format, u64 modifier)
16452 return modifier == DRM_FORMAT_MOD_LINEAR &&
16453 format == DRM_FORMAT_ARGB8888;
16456 static const struct drm_plane_funcs i965_plane_funcs = {
16457 .update_plane = drm_atomic_helper_update_plane,
16458 .disable_plane = drm_atomic_helper_disable_plane,
16459 .destroy = intel_plane_destroy,
16460 .atomic_duplicate_state = intel_plane_duplicate_state,
16461 .atomic_destroy_state = intel_plane_destroy_state,
16462 .format_mod_supported = i965_plane_format_mod_supported,
16465 static const struct drm_plane_funcs i8xx_plane_funcs = {
16466 .update_plane = drm_atomic_helper_update_plane,
16467 .disable_plane = drm_atomic_helper_disable_plane,
16468 .destroy = intel_plane_destroy,
16469 .atomic_duplicate_state = intel_plane_duplicate_state,
16470 .atomic_destroy_state = intel_plane_destroy_state,
16471 .format_mod_supported = i8xx_plane_format_mod_supported,
16475 intel_legacy_cursor_update(struct drm_plane *_plane,
16476 struct drm_crtc *_crtc,
16477 struct drm_framebuffer *fb,
16478 int crtc_x, int crtc_y,
16479 unsigned int crtc_w, unsigned int crtc_h,
16480 u32 src_x, u32 src_y,
16481 u32 src_w, u32 src_h,
16482 struct drm_modeset_acquire_ctx *ctx)
16484 struct intel_plane *plane = to_intel_plane(_plane);
16485 struct intel_crtc *crtc = to_intel_crtc(_crtc);
16486 struct intel_plane_state *old_plane_state =
16487 to_intel_plane_state(plane->base.state);
16488 struct intel_plane_state *new_plane_state;
16489 struct intel_crtc_state *crtc_state =
16490 to_intel_crtc_state(crtc->base.state);
16491 struct intel_crtc_state *new_crtc_state;
16495 * When crtc is inactive or there is a modeset pending,
16496 * wait for it to complete in the slowpath
16498 if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16499 crtc_state->update_pipe)
16503 * Don't do an async update if there is an outstanding commit modifying
16504 * the plane. This prevents our async update's changes from getting
16505 * overridden by a previous synchronous update's state.
16507 if (old_plane_state->uapi.commit &&
16508 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16512 * If any parameters change that may affect watermarks,
16513 * take the slowpath. Only changing fb or position should be
16516 if (old_plane_state->uapi.crtc != &crtc->base ||
16517 old_plane_state->uapi.src_w != src_w ||
16518 old_plane_state->uapi.src_h != src_h ||
16519 old_plane_state->uapi.crtc_w != crtc_w ||
16520 old_plane_state->uapi.crtc_h != crtc_h ||
16521 !old_plane_state->uapi.fb != !fb)
16524 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16525 if (!new_plane_state)
16528 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16529 if (!new_crtc_state) {
16534 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16536 new_plane_state->uapi.src_x = src_x;
16537 new_plane_state->uapi.src_y = src_y;
16538 new_plane_state->uapi.src_w = src_w;
16539 new_plane_state->uapi.src_h = src_h;
16540 new_plane_state->uapi.crtc_x = crtc_x;
16541 new_plane_state->uapi.crtc_y = crtc_y;
16542 new_plane_state->uapi.crtc_w = crtc_w;
16543 new_plane_state->uapi.crtc_h = crtc_h;
16545 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16547 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16548 old_plane_state, new_plane_state);
16552 ret = intel_plane_pin_fb(new_plane_state);
16556 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16558 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16559 to_intel_frontbuffer(new_plane_state->hw.fb),
16560 plane->frontbuffer_bit);
16562 /* Swap plane state */
16563 plane->base.state = &new_plane_state->uapi;
16566 * We cannot swap crtc_state as it may be in use by an atomic commit or
16567 * page flip that's running simultaneously. If we swap crtc_state and
16568 * destroy the old state, we will cause a use-after-free there.
16570 * Only update active_planes, which is needed for our internal
16571 * bookkeeping. Either value will do the right thing when updating
16572 * planes atomically. If the cursor was part of the atomic update then
16573 * we would have taken the slowpath.
16575 crtc_state->active_planes = new_crtc_state->active_planes;
16577 if (new_plane_state->uapi.visible)
16578 intel_update_plane(plane, crtc_state, new_plane_state);
16580 intel_disable_plane(plane, crtc_state);
16582 intel_plane_unpin_fb(old_plane_state);
16585 if (new_crtc_state)
16586 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16588 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16590 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16594 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16595 crtc_x, crtc_y, crtc_w, crtc_h,
16596 src_x, src_y, src_w, src_h, ctx);
16599 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16600 .update_plane = intel_legacy_cursor_update,
16601 .disable_plane = drm_atomic_helper_disable_plane,
16602 .destroy = intel_plane_destroy,
16603 .atomic_duplicate_state = intel_plane_duplicate_state,
16604 .atomic_destroy_state = intel_plane_destroy_state,
16605 .format_mod_supported = intel_cursor_format_mod_supported,
16608 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16609 enum i9xx_plane_id i9xx_plane)
16611 if (!HAS_FBC(dev_priv))
16614 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16615 return i9xx_plane == PLANE_A; /* tied to pipe A */
16616 else if (IS_IVYBRIDGE(dev_priv))
16617 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16618 i9xx_plane == PLANE_C;
16619 else if (INTEL_GEN(dev_priv) >= 4)
16620 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16622 return i9xx_plane == PLANE_A;
16625 static struct intel_plane *
16626 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16628 struct intel_plane *plane;
16629 const struct drm_plane_funcs *plane_funcs;
16630 unsigned int supported_rotations;
16631 const u32 *formats;
16635 if (INTEL_GEN(dev_priv) >= 9)
16636 return skl_universal_plane_create(dev_priv, pipe,
16639 plane = intel_plane_alloc();
16643 plane->pipe = pipe;
16645 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16646 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16648 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
16649 INTEL_NUM_PIPES(dev_priv) == 2)
16650 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16652 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16653 plane->id = PLANE_PRIMARY;
16654 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16656 plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16657 if (plane->has_fbc) {
16658 struct intel_fbc *fbc = &dev_priv->fbc;
16660 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16663 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16664 formats = vlv_primary_formats;
16665 num_formats = ARRAY_SIZE(vlv_primary_formats);
16666 } else if (INTEL_GEN(dev_priv) >= 4) {
16668 * WaFP16GammaEnabling:ivb
16669 * "Workaround : When using the 64-bit format, the plane
16670 * output on each color channel has one quarter amplitude.
16671 * It can be brought up to full amplitude by using pipe
16672 * gamma correction or pipe color space conversion to
16673 * multiply the plane output by four."
16675 * There is no dedicated plane gamma for the primary plane,
16676 * and using the pipe gamma/csc could conflict with other
16677 * planes, so we choose not to expose fp16 on IVB primary
16678 * planes. HSW primary planes no longer have this problem.
16680 if (IS_IVYBRIDGE(dev_priv)) {
16681 formats = ivb_primary_formats;
16682 num_formats = ARRAY_SIZE(ivb_primary_formats);
16684 formats = i965_primary_formats;
16685 num_formats = ARRAY_SIZE(i965_primary_formats);
16688 formats = i8xx_primary_formats;
16689 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16692 if (INTEL_GEN(dev_priv) >= 4)
16693 plane_funcs = &i965_plane_funcs;
16695 plane_funcs = &i8xx_plane_funcs;
16697 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16698 plane->min_cdclk = vlv_plane_min_cdclk;
16699 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16700 plane->min_cdclk = hsw_plane_min_cdclk;
16701 else if (IS_IVYBRIDGE(dev_priv))
16702 plane->min_cdclk = ivb_plane_min_cdclk;
16704 plane->min_cdclk = i9xx_plane_min_cdclk;
16706 plane->max_stride = i9xx_plane_max_stride;
16707 plane->update_plane = i9xx_update_plane;
16708 plane->disable_plane = i9xx_disable_plane;
16709 plane->get_hw_state = i9xx_plane_get_hw_state;
16710 plane->check_plane = i9xx_plane_check;
16712 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16713 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16715 formats, num_formats,
16716 i9xx_format_modifiers,
16717 DRM_PLANE_TYPE_PRIMARY,
16718 "primary %c", pipe_name(pipe));
16720 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16722 formats, num_formats,
16723 i9xx_format_modifiers,
16724 DRM_PLANE_TYPE_PRIMARY,
16726 plane_name(plane->i9xx_plane));
16730 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16731 supported_rotations =
16732 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16733 DRM_MODE_REFLECT_X;
16734 } else if (INTEL_GEN(dev_priv) >= 4) {
16735 supported_rotations =
16736 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16738 supported_rotations = DRM_MODE_ROTATE_0;
16741 if (INTEL_GEN(dev_priv) >= 4)
16742 drm_plane_create_rotation_property(&plane->base,
16744 supported_rotations);
16747 drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16749 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16754 intel_plane_free(plane);
16756 return ERR_PTR(ret);
16759 static struct intel_plane *
16760 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16763 struct intel_plane *cursor;
16766 cursor = intel_plane_alloc();
16767 if (IS_ERR(cursor))
16770 cursor->pipe = pipe;
16771 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16772 cursor->id = PLANE_CURSOR;
16773 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16775 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16776 cursor->max_stride = i845_cursor_max_stride;
16777 cursor->update_plane = i845_update_cursor;
16778 cursor->disable_plane = i845_disable_cursor;
16779 cursor->get_hw_state = i845_cursor_get_hw_state;
16780 cursor->check_plane = i845_check_cursor;
16782 cursor->max_stride = i9xx_cursor_max_stride;
16783 cursor->update_plane = i9xx_update_cursor;
16784 cursor->disable_plane = i9xx_disable_cursor;
16785 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16786 cursor->check_plane = i9xx_check_cursor;
16789 cursor->cursor.base = ~0;
16790 cursor->cursor.cntl = ~0;
16792 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16793 cursor->cursor.size = ~0;
16795 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16796 0, &intel_cursor_plane_funcs,
16797 intel_cursor_formats,
16798 ARRAY_SIZE(intel_cursor_formats),
16799 cursor_format_modifiers,
16800 DRM_PLANE_TYPE_CURSOR,
16801 "cursor %c", pipe_name(pipe));
16805 if (INTEL_GEN(dev_priv) >= 4)
16806 drm_plane_create_rotation_property(&cursor->base,
16808 DRM_MODE_ROTATE_0 |
16809 DRM_MODE_ROTATE_180);
16811 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16812 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16814 if (INTEL_GEN(dev_priv) >= 12)
16815 drm_plane_enable_fb_damage_clips(&cursor->base);
16817 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16822 intel_plane_free(cursor);
16824 return ERR_PTR(ret);
16827 #define INTEL_CRTC_FUNCS \
16828 .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16829 .set_config = drm_atomic_helper_set_config, \
16830 .destroy = intel_crtc_destroy, \
16831 .page_flip = drm_atomic_helper_page_flip, \
16832 .atomic_duplicate_state = intel_crtc_duplicate_state, \
16833 .atomic_destroy_state = intel_crtc_destroy_state, \
16834 .set_crc_source = intel_crtc_set_crc_source, \
16835 .verify_crc_source = intel_crtc_verify_crc_source, \
16836 .get_crc_sources = intel_crtc_get_crc_sources
16838 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16841 .get_vblank_counter = g4x_get_vblank_counter,
16842 .enable_vblank = bdw_enable_vblank,
16843 .disable_vblank = bdw_disable_vblank,
16844 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16847 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16850 .get_vblank_counter = g4x_get_vblank_counter,
16851 .enable_vblank = ilk_enable_vblank,
16852 .disable_vblank = ilk_disable_vblank,
16853 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16856 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16859 .get_vblank_counter = g4x_get_vblank_counter,
16860 .enable_vblank = i965_enable_vblank,
16861 .disable_vblank = i965_disable_vblank,
16862 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16865 static const struct drm_crtc_funcs i965_crtc_funcs = {
16868 .get_vblank_counter = i915_get_vblank_counter,
16869 .enable_vblank = i965_enable_vblank,
16870 .disable_vblank = i965_disable_vblank,
16871 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16874 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16877 .get_vblank_counter = i915_get_vblank_counter,
16878 .enable_vblank = i915gm_enable_vblank,
16879 .disable_vblank = i915gm_disable_vblank,
16880 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16883 static const struct drm_crtc_funcs i915_crtc_funcs = {
16886 .get_vblank_counter = i915_get_vblank_counter,
16887 .enable_vblank = i8xx_enable_vblank,
16888 .disable_vblank = i8xx_disable_vblank,
16889 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16892 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16895 /* no hw vblank counter */
16896 .enable_vblank = i8xx_enable_vblank,
16897 .disable_vblank = i8xx_disable_vblank,
16898 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16901 static struct intel_crtc *intel_crtc_alloc(void)
16903 struct intel_crtc_state *crtc_state;
16904 struct intel_crtc *crtc;
16906 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16908 return ERR_PTR(-ENOMEM);
16910 crtc_state = intel_crtc_state_alloc(crtc);
16913 return ERR_PTR(-ENOMEM);
16916 crtc->base.state = &crtc_state->uapi;
16917 crtc->config = crtc_state;
16922 static void intel_crtc_free(struct intel_crtc *crtc)
16924 intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16928 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16930 struct intel_plane *plane;
16932 for_each_intel_plane(&dev_priv->drm, plane) {
16933 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16936 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16940 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16942 struct intel_plane *primary, *cursor;
16943 const struct drm_crtc_funcs *funcs;
16944 struct intel_crtc *crtc;
16947 crtc = intel_crtc_alloc();
16949 return PTR_ERR(crtc);
16952 crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16954 primary = intel_primary_plane_create(dev_priv, pipe);
16955 if (IS_ERR(primary)) {
16956 ret = PTR_ERR(primary);
16959 crtc->plane_ids_mask |= BIT(primary->id);
16961 for_each_sprite(dev_priv, pipe, sprite) {
16962 struct intel_plane *plane;
16964 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16965 if (IS_ERR(plane)) {
16966 ret = PTR_ERR(plane);
16969 crtc->plane_ids_mask |= BIT(plane->id);
16972 cursor = intel_cursor_plane_create(dev_priv, pipe);
16973 if (IS_ERR(cursor)) {
16974 ret = PTR_ERR(cursor);
16977 crtc->plane_ids_mask |= BIT(cursor->id);
16979 if (HAS_GMCH(dev_priv)) {
16980 if (IS_CHERRYVIEW(dev_priv) ||
16981 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16982 funcs = &g4x_crtc_funcs;
16983 else if (IS_GEN(dev_priv, 4))
16984 funcs = &i965_crtc_funcs;
16985 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16986 funcs = &i915gm_crtc_funcs;
16987 else if (IS_GEN(dev_priv, 3))
16988 funcs = &i915_crtc_funcs;
16990 funcs = &i8xx_crtc_funcs;
16992 if (INTEL_GEN(dev_priv) >= 8)
16993 funcs = &bdw_crtc_funcs;
16995 funcs = &ilk_crtc_funcs;
16998 ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16999 &primary->base, &cursor->base,
17000 funcs, "pipe %c", pipe_name(pipe));
17004 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
17005 dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
17006 dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
17008 if (INTEL_GEN(dev_priv) < 9) {
17009 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
17011 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
17012 dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
17013 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
17016 if (INTEL_GEN(dev_priv) >= 10)
17017 drm_crtc_create_scaling_filter_property(&crtc->base,
17018 BIT(DRM_SCALING_FILTER_DEFAULT) |
17019 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
17021 intel_color_init(crtc);
17023 intel_crtc_crc_init(crtc);
17025 drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
17030 intel_crtc_free(crtc);
17035 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
17036 struct drm_file *file)
17038 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
17039 struct drm_crtc *drmmode_crtc;
17040 struct intel_crtc *crtc;
17042 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
17046 crtc = to_intel_crtc(drmmode_crtc);
17047 pipe_from_crtc_id->pipe = crtc->pipe;
17052 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
17054 struct drm_device *dev = encoder->base.dev;
17055 struct intel_encoder *source_encoder;
17056 u32 possible_clones = 0;
17058 for_each_intel_encoder(dev, source_encoder) {
17059 if (encoders_cloneable(encoder, source_encoder))
17060 possible_clones |= drm_encoder_mask(&source_encoder->base);
17063 return possible_clones;
17066 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
17068 struct drm_device *dev = encoder->base.dev;
17069 struct intel_crtc *crtc;
17070 u32 possible_crtcs = 0;
17072 for_each_intel_crtc(dev, crtc) {
17073 if (encoder->pipe_mask & BIT(crtc->pipe))
17074 possible_crtcs |= drm_crtc_mask(&crtc->base);
17077 return possible_crtcs;
17080 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
17082 if (!IS_MOBILE(dev_priv))
17085 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
17088 if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
17094 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
17096 if (INTEL_GEN(dev_priv) >= 9)
17099 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
17102 if (HAS_PCH_LPT_H(dev_priv) &&
17103 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
17106 /* DDI E can't be used if DDI A requires 4 lanes */
17107 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
17110 if (!dev_priv->vbt.int_crt_support)
17116 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
17121 if (HAS_DDI(dev_priv))
17124 * This w/a is needed at least on CPT/PPT, but to be sure apply it
17125 * everywhere where registers can be write protected.
17127 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17132 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
17133 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
17135 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
17136 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
17140 static void intel_pps_init(struct drm_i915_private *dev_priv)
17142 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
17143 dev_priv->pps_mmio_base = PCH_PPS_BASE;
17144 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
17145 dev_priv->pps_mmio_base = VLV_PPS_BASE;
17147 dev_priv->pps_mmio_base = PPS_BASE;
17149 intel_pps_unlock_regs_wa(dev_priv);
17152 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
17154 struct intel_encoder *encoder;
17155 bool dpd_is_edp = false;
17157 intel_pps_init(dev_priv);
17159 if (!HAS_DISPLAY(dev_priv))
17162 if (IS_ROCKETLAKE(dev_priv)) {
17163 intel_ddi_init(dev_priv, PORT_A);
17164 intel_ddi_init(dev_priv, PORT_B);
17165 intel_ddi_init(dev_priv, PORT_TC1);
17166 intel_ddi_init(dev_priv, PORT_TC2);
17167 } else if (INTEL_GEN(dev_priv) >= 12) {
17168 intel_ddi_init(dev_priv, PORT_A);
17169 intel_ddi_init(dev_priv, PORT_B);
17170 intel_ddi_init(dev_priv, PORT_TC1);
17171 intel_ddi_init(dev_priv, PORT_TC2);
17172 intel_ddi_init(dev_priv, PORT_TC3);
17173 intel_ddi_init(dev_priv, PORT_TC4);
17174 intel_ddi_init(dev_priv, PORT_TC5);
17175 intel_ddi_init(dev_priv, PORT_TC6);
17176 icl_dsi_init(dev_priv);
17177 } else if (IS_JSL_EHL(dev_priv)) {
17178 intel_ddi_init(dev_priv, PORT_A);
17179 intel_ddi_init(dev_priv, PORT_B);
17180 intel_ddi_init(dev_priv, PORT_C);
17181 intel_ddi_init(dev_priv, PORT_D);
17182 icl_dsi_init(dev_priv);
17183 } else if (IS_GEN(dev_priv, 11)) {
17184 intel_ddi_init(dev_priv, PORT_A);
17185 intel_ddi_init(dev_priv, PORT_B);
17186 intel_ddi_init(dev_priv, PORT_C);
17187 intel_ddi_init(dev_priv, PORT_D);
17188 intel_ddi_init(dev_priv, PORT_E);
17190 * On some ICL SKUs port F is not present. No strap bits for
17191 * this, so rely on VBT.
17192 * Work around broken VBTs on SKUs known to have no port F.
17194 if (IS_ICL_WITH_PORT_F(dev_priv) &&
17195 intel_bios_is_port_present(dev_priv, PORT_F))
17196 intel_ddi_init(dev_priv, PORT_F);
17198 icl_dsi_init(dev_priv);
17199 } else if (IS_GEN9_LP(dev_priv)) {
17201 * FIXME: Broxton doesn't support port detection via the
17202 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
17203 * detect the ports.
17205 intel_ddi_init(dev_priv, PORT_A);
17206 intel_ddi_init(dev_priv, PORT_B);
17207 intel_ddi_init(dev_priv, PORT_C);
17209 vlv_dsi_init(dev_priv);
17210 } else if (HAS_DDI(dev_priv)) {
17213 if (intel_ddi_crt_present(dev_priv))
17214 intel_crt_init(dev_priv);
17217 * Haswell uses DDI functions to detect digital outputs.
17218 * On SKL pre-D0 the strap isn't connected, so we assume
17221 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
17222 /* WaIgnoreDDIAStrap: skl */
17223 if (found || IS_GEN9_BC(dev_priv))
17224 intel_ddi_init(dev_priv, PORT_A);
17226 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
17228 found = intel_de_read(dev_priv, SFUSE_STRAP);
17230 if (found & SFUSE_STRAP_DDIB_DETECTED)
17231 intel_ddi_init(dev_priv, PORT_B);
17232 if (found & SFUSE_STRAP_DDIC_DETECTED)
17233 intel_ddi_init(dev_priv, PORT_C);
17234 if (found & SFUSE_STRAP_DDID_DETECTED)
17235 intel_ddi_init(dev_priv, PORT_D);
17236 if (found & SFUSE_STRAP_DDIF_DETECTED)
17237 intel_ddi_init(dev_priv, PORT_F);
17239 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
17241 if (IS_GEN9_BC(dev_priv) &&
17242 intel_bios_is_port_present(dev_priv, PORT_E))
17243 intel_ddi_init(dev_priv, PORT_E);
17245 } else if (HAS_PCH_SPLIT(dev_priv)) {
17249 * intel_edp_init_connector() depends on this completing first,
17250 * to prevent the registration of both eDP and LVDS and the
17251 * incorrect sharing of the PPS.
17253 intel_lvds_init(dev_priv);
17254 intel_crt_init(dev_priv);
17256 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
17258 if (ilk_has_edp_a(dev_priv))
17259 intel_dp_init(dev_priv, DP_A, PORT_A);
17261 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
17262 /* PCH SDVOB multiplex with HDMIB */
17263 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
17265 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
17266 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
17267 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
17270 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
17271 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
17273 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
17274 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
17276 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
17277 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
17279 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
17280 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
17281 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
17282 bool has_edp, has_port;
17284 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
17285 intel_crt_init(dev_priv);
17288 * The DP_DETECTED bit is the latched state of the DDC
17289 * SDA pin at boot. However since eDP doesn't require DDC
17290 * (no way to plug in a DP->HDMI dongle) the DDC pins for
17291 * eDP ports may have been muxed to an alternate function.
17292 * Thus we can't rely on the DP_DETECTED bit alone to detect
17293 * eDP ports. Consult the VBT as well as DP_DETECTED to
17294 * detect eDP ports.
17296 * Sadly the straps seem to be missing sometimes even for HDMI
17297 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
17298 * and VBT for the presence of the port. Additionally we can't
17299 * trust the port type the VBT declares as we've seen at least
17300 * HDMI ports that the VBT claim are DP or eDP.
17302 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
17303 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
17304 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
17305 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
17306 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
17307 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
17309 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
17310 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
17311 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
17312 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
17313 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
17314 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
17316 if (IS_CHERRYVIEW(dev_priv)) {
17318 * eDP not supported on port D,
17319 * so no need to worry about it
17321 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17322 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17323 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17324 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17325 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17328 vlv_dsi_init(dev_priv);
17329 } else if (IS_PINEVIEW(dev_priv)) {
17330 intel_lvds_init(dev_priv);
17331 intel_crt_init(dev_priv);
17332 } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17333 bool found = false;
17335 if (IS_MOBILE(dev_priv))
17336 intel_lvds_init(dev_priv);
17338 intel_crt_init(dev_priv);
17340 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17341 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17342 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17343 if (!found && IS_G4X(dev_priv)) {
17344 drm_dbg_kms(&dev_priv->drm,
17345 "probing HDMI on SDVOB\n");
17346 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17349 if (!found && IS_G4X(dev_priv))
17350 intel_dp_init(dev_priv, DP_B, PORT_B);
17353 /* Before G4X SDVOC doesn't have its own detect register */
17355 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17356 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17357 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17360 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17362 if (IS_G4X(dev_priv)) {
17363 drm_dbg_kms(&dev_priv->drm,
17364 "probing HDMI on SDVOC\n");
17365 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17367 if (IS_G4X(dev_priv))
17368 intel_dp_init(dev_priv, DP_C, PORT_C);
17371 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17372 intel_dp_init(dev_priv, DP_D, PORT_D);
17374 if (SUPPORTS_TV(dev_priv))
17375 intel_tv_init(dev_priv);
17376 } else if (IS_GEN(dev_priv, 2)) {
17377 if (IS_I85X(dev_priv))
17378 intel_lvds_init(dev_priv);
17380 intel_crt_init(dev_priv);
17381 intel_dvo_init(dev_priv);
17384 intel_psr_init(dev_priv);
17386 for_each_intel_encoder(&dev_priv->drm, encoder) {
17387 encoder->base.possible_crtcs =
17388 intel_encoder_possible_crtcs(encoder);
17389 encoder->base.possible_clones =
17390 intel_encoder_possible_clones(encoder);
17393 intel_init_pch_refclk(dev_priv);
17395 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17398 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17400 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17402 drm_framebuffer_cleanup(fb);
17403 intel_frontbuffer_put(intel_fb->frontbuffer);
17408 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17409 struct drm_file *file,
17410 unsigned int *handle)
17412 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17413 struct drm_i915_private *i915 = to_i915(obj->base.dev);
17415 if (obj->userptr.mm) {
17416 drm_dbg(&i915->drm,
17417 "attempting to use a userptr for a framebuffer, denied\n");
17421 return drm_gem_handle_create(file, &obj->base, handle);
17424 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17425 struct drm_file *file,
17426 unsigned flags, unsigned color,
17427 struct drm_clip_rect *clips,
17428 unsigned num_clips)
17430 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17432 i915_gem_object_flush_if_display(obj);
17433 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17438 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17439 .destroy = intel_user_framebuffer_destroy,
17440 .create_handle = intel_user_framebuffer_create_handle,
17441 .dirty = intel_user_framebuffer_dirty,
17444 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17445 struct drm_i915_gem_object *obj,
17446 struct drm_mode_fb_cmd2 *mode_cmd)
17448 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17449 struct drm_framebuffer *fb = &intel_fb->base;
17451 unsigned int tiling, stride;
17455 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17456 if (!intel_fb->frontbuffer)
17459 i915_gem_object_lock(obj, NULL);
17460 tiling = i915_gem_object_get_tiling(obj);
17461 stride = i915_gem_object_get_stride(obj);
17462 i915_gem_object_unlock(obj);
17464 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17466 * If there's a fence, enforce that
17467 * the fb modifier and tiling mode match.
17469 if (tiling != I915_TILING_NONE &&
17470 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17471 drm_dbg_kms(&dev_priv->drm,
17472 "tiling_mode doesn't match fb modifier\n");
17476 if (tiling == I915_TILING_X) {
17477 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17478 } else if (tiling == I915_TILING_Y) {
17479 drm_dbg_kms(&dev_priv->drm,
17480 "No Y tiling for legacy addfb\n");
17485 if (!drm_any_plane_has_format(&dev_priv->drm,
17486 mode_cmd->pixel_format,
17487 mode_cmd->modifier[0])) {
17488 struct drm_format_name_buf format_name;
17490 drm_dbg_kms(&dev_priv->drm,
17491 "unsupported pixel format %s / modifier 0x%llx\n",
17492 drm_get_format_name(mode_cmd->pixel_format,
17494 mode_cmd->modifier[0]);
17499 * gen2/3 display engine uses the fence if present,
17500 * so the tiling mode must match the fb modifier exactly.
17502 if (INTEL_GEN(dev_priv) < 4 &&
17503 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17504 drm_dbg_kms(&dev_priv->drm,
17505 "tiling_mode must match fb modifier exactly on gen2/3\n");
17509 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17510 mode_cmd->modifier[0]);
17511 if (mode_cmd->pitches[0] > max_stride) {
17512 drm_dbg_kms(&dev_priv->drm,
17513 "%s pitch (%u) must be at most %d\n",
17514 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17515 "tiled" : "linear",
17516 mode_cmd->pitches[0], max_stride);
17521 * If there's a fence, enforce that
17522 * the fb pitch and fence stride match.
17524 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17525 drm_dbg_kms(&dev_priv->drm,
17526 "pitch (%d) must match tiling stride (%d)\n",
17527 mode_cmd->pitches[0], stride);
17531 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17532 if (mode_cmd->offsets[0] != 0) {
17533 drm_dbg_kms(&dev_priv->drm,
17534 "plane 0 offset (0x%08x) must be 0\n",
17535 mode_cmd->offsets[0]);
17539 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17541 for (i = 0; i < fb->format->num_planes; i++) {
17542 u32 stride_alignment;
17544 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17545 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17550 stride_alignment = intel_fb_stride_alignment(fb, i);
17551 if (fb->pitches[i] & (stride_alignment - 1)) {
17552 drm_dbg_kms(&dev_priv->drm,
17553 "plane %d pitch (%d) must be at least %u byte aligned\n",
17554 i, fb->pitches[i], stride_alignment);
17558 if (is_gen12_ccs_plane(fb, i)) {
17559 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17561 if (fb->pitches[i] != ccs_aux_stride) {
17562 drm_dbg_kms(&dev_priv->drm,
17563 "ccs aux plane %d pitch (%d) must be %d\n",
17565 fb->pitches[i], ccs_aux_stride);
17570 fb->obj[i] = &obj->base;
17573 ret = intel_fill_fb_info(dev_priv, fb);
17577 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17579 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17586 intel_frontbuffer_put(intel_fb->frontbuffer);
17590 static struct drm_framebuffer *
17591 intel_user_framebuffer_create(struct drm_device *dev,
17592 struct drm_file *filp,
17593 const struct drm_mode_fb_cmd2 *user_mode_cmd)
17595 struct drm_framebuffer *fb;
17596 struct drm_i915_gem_object *obj;
17597 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17599 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17601 return ERR_PTR(-ENOENT);
17603 fb = intel_framebuffer_create(obj, &mode_cmd);
17604 i915_gem_object_put(obj);
17609 static enum drm_mode_status
17610 intel_mode_valid(struct drm_device *dev,
17611 const struct drm_display_mode *mode)
17613 struct drm_i915_private *dev_priv = to_i915(dev);
17614 int hdisplay_max, htotal_max;
17615 int vdisplay_max, vtotal_max;
17618 * Can't reject DBLSCAN here because Xorg ddxen can add piles
17619 * of DBLSCAN modes to the output's mode list when they detect
17620 * the scaling mode property on the connector. And they don't
17621 * ask the kernel to validate those modes in any way until
17622 * modeset time at which point the client gets a protocol error.
17623 * So in order to not upset those clients we silently ignore the
17624 * DBLSCAN flag on such connectors. For other connectors we will
17625 * reject modes with the DBLSCAN flag in encoder->compute_config().
17626 * And we always reject DBLSCAN modes in connector->mode_valid()
17627 * as we never want such modes on the connector's mode list.
17630 if (mode->vscan > 1)
17631 return MODE_NO_VSCAN;
17633 if (mode->flags & DRM_MODE_FLAG_HSKEW)
17634 return MODE_H_ILLEGAL;
17636 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17637 DRM_MODE_FLAG_NCSYNC |
17638 DRM_MODE_FLAG_PCSYNC))
17641 if (mode->flags & (DRM_MODE_FLAG_BCAST |
17642 DRM_MODE_FLAG_PIXMUX |
17643 DRM_MODE_FLAG_CLKDIV2))
17646 /* Transcoder timing limits */
17647 if (INTEL_GEN(dev_priv) >= 11) {
17648 hdisplay_max = 16384;
17649 vdisplay_max = 8192;
17650 htotal_max = 16384;
17652 } else if (INTEL_GEN(dev_priv) >= 9 ||
17653 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17654 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17655 vdisplay_max = 4096;
17658 } else if (INTEL_GEN(dev_priv) >= 3) {
17659 hdisplay_max = 4096;
17660 vdisplay_max = 4096;
17664 hdisplay_max = 2048;
17665 vdisplay_max = 2048;
17670 if (mode->hdisplay > hdisplay_max ||
17671 mode->hsync_start > htotal_max ||
17672 mode->hsync_end > htotal_max ||
17673 mode->htotal > htotal_max)
17674 return MODE_H_ILLEGAL;
17676 if (mode->vdisplay > vdisplay_max ||
17677 mode->vsync_start > vtotal_max ||
17678 mode->vsync_end > vtotal_max ||
17679 mode->vtotal > vtotal_max)
17680 return MODE_V_ILLEGAL;
17682 if (INTEL_GEN(dev_priv) >= 5) {
17683 if (mode->hdisplay < 64 ||
17684 mode->htotal - mode->hdisplay < 32)
17685 return MODE_H_ILLEGAL;
17687 if (mode->vtotal - mode->vdisplay < 5)
17688 return MODE_V_ILLEGAL;
17690 if (mode->htotal - mode->hdisplay < 32)
17691 return MODE_H_ILLEGAL;
17693 if (mode->vtotal - mode->vdisplay < 3)
17694 return MODE_V_ILLEGAL;
17700 enum drm_mode_status
17701 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17702 const struct drm_display_mode *mode)
17704 int plane_width_max, plane_height_max;
17707 * intel_mode_valid() should be
17708 * sufficient on older platforms.
17710 if (INTEL_GEN(dev_priv) < 9)
17714 * Most people will probably want a fullscreen
17715 * plane so let's not advertize modes that are
17716 * too big for that.
17718 if (INTEL_GEN(dev_priv) >= 11) {
17719 plane_width_max = 5120;
17720 plane_height_max = 4320;
17722 plane_width_max = 5120;
17723 plane_height_max = 4096;
17726 if (mode->hdisplay > plane_width_max)
17727 return MODE_H_ILLEGAL;
17729 if (mode->vdisplay > plane_height_max)
17730 return MODE_V_ILLEGAL;
17735 static const struct drm_mode_config_funcs intel_mode_funcs = {
17736 .fb_create = intel_user_framebuffer_create,
17737 .get_format_info = intel_get_format_info,
17738 .output_poll_changed = intel_fbdev_output_poll_changed,
17739 .mode_valid = intel_mode_valid,
17740 .atomic_check = intel_atomic_check,
17741 .atomic_commit = intel_atomic_commit,
17742 .atomic_state_alloc = intel_atomic_state_alloc,
17743 .atomic_state_clear = intel_atomic_state_clear,
17744 .atomic_state_free = intel_atomic_state_free,
17748 * intel_init_display_hooks - initialize the display modesetting hooks
17749 * @dev_priv: device private
17751 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17753 intel_init_cdclk_hooks(dev_priv);
17755 if (INTEL_GEN(dev_priv) >= 9) {
17756 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17757 dev_priv->display.get_initial_plane_config =
17758 skl_get_initial_plane_config;
17759 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17760 dev_priv->display.crtc_enable = hsw_crtc_enable;
17761 dev_priv->display.crtc_disable = hsw_crtc_disable;
17762 } else if (HAS_DDI(dev_priv)) {
17763 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17764 dev_priv->display.get_initial_plane_config =
17765 i9xx_get_initial_plane_config;
17766 dev_priv->display.crtc_compute_clock =
17767 hsw_crtc_compute_clock;
17768 dev_priv->display.crtc_enable = hsw_crtc_enable;
17769 dev_priv->display.crtc_disable = hsw_crtc_disable;
17770 } else if (HAS_PCH_SPLIT(dev_priv)) {
17771 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17772 dev_priv->display.get_initial_plane_config =
17773 i9xx_get_initial_plane_config;
17774 dev_priv->display.crtc_compute_clock =
17775 ilk_crtc_compute_clock;
17776 dev_priv->display.crtc_enable = ilk_crtc_enable;
17777 dev_priv->display.crtc_disable = ilk_crtc_disable;
17778 } else if (IS_CHERRYVIEW(dev_priv)) {
17779 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17780 dev_priv->display.get_initial_plane_config =
17781 i9xx_get_initial_plane_config;
17782 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17783 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17784 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17785 } else if (IS_VALLEYVIEW(dev_priv)) {
17786 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17787 dev_priv->display.get_initial_plane_config =
17788 i9xx_get_initial_plane_config;
17789 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17790 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17791 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17792 } else if (IS_G4X(dev_priv)) {
17793 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17794 dev_priv->display.get_initial_plane_config =
17795 i9xx_get_initial_plane_config;
17796 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17797 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17798 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17799 } else if (IS_PINEVIEW(dev_priv)) {
17800 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17801 dev_priv->display.get_initial_plane_config =
17802 i9xx_get_initial_plane_config;
17803 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17804 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17805 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17806 } else if (!IS_GEN(dev_priv, 2)) {
17807 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17808 dev_priv->display.get_initial_plane_config =
17809 i9xx_get_initial_plane_config;
17810 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17811 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17812 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17814 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17815 dev_priv->display.get_initial_plane_config =
17816 i9xx_get_initial_plane_config;
17817 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17818 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17819 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17822 if (IS_GEN(dev_priv, 5)) {
17823 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17824 } else if (IS_GEN(dev_priv, 6)) {
17825 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17826 } else if (IS_IVYBRIDGE(dev_priv)) {
17827 /* FIXME: detect B0+ stepping and use auto training */
17828 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17831 if (INTEL_GEN(dev_priv) >= 9)
17832 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17834 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17838 void intel_modeset_init_hw(struct drm_i915_private *i915)
17840 struct intel_cdclk_state *cdclk_state =
17841 to_intel_cdclk_state(i915->cdclk.obj.state);
17842 struct intel_dbuf_state *dbuf_state =
17843 to_intel_dbuf_state(i915->dbuf.obj.state);
17845 intel_update_cdclk(i915);
17846 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17847 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17849 dbuf_state->enabled_slices = i915->dbuf.enabled_slices;
17852 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17854 struct drm_plane *plane;
17855 struct intel_crtc *crtc;
17857 for_each_intel_crtc(state->dev, crtc) {
17858 struct intel_crtc_state *crtc_state;
17860 crtc_state = intel_atomic_get_crtc_state(state, crtc);
17861 if (IS_ERR(crtc_state))
17862 return PTR_ERR(crtc_state);
17864 if (crtc_state->hw.active) {
17866 * Preserve the inherited flag to avoid
17867 * taking the full modeset path.
17869 crtc_state->inherited = true;
17873 drm_for_each_plane(plane, state->dev) {
17874 struct drm_plane_state *plane_state;
17876 plane_state = drm_atomic_get_plane_state(state, plane);
17877 if (IS_ERR(plane_state))
17878 return PTR_ERR(plane_state);
17885 * Calculate what we think the watermarks should be for the state we've read
17886 * out of the hardware and then immediately program those watermarks so that
17887 * we ensure the hardware settings match our internal state.
17889 * We can calculate what we think WM's should be by creating a duplicate of the
17890 * current state (which was constructed during hardware readout) and running it
17891 * through the atomic check code to calculate new watermark values in the
17894 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17896 struct drm_atomic_state *state;
17897 struct intel_atomic_state *intel_state;
17898 struct intel_crtc *crtc;
17899 struct intel_crtc_state *crtc_state;
17900 struct drm_modeset_acquire_ctx ctx;
17904 /* Only supported on platforms that use atomic watermark design */
17905 if (!dev_priv->display.optimize_watermarks)
17908 state = drm_atomic_state_alloc(&dev_priv->drm);
17909 if (drm_WARN_ON(&dev_priv->drm, !state))
17912 intel_state = to_intel_atomic_state(state);
17914 drm_modeset_acquire_init(&ctx, 0);
17917 state->acquire_ctx = &ctx;
17920 * Hardware readout is the only time we don't want to calculate
17921 * intermediate watermarks (since we don't trust the current
17924 if (!HAS_GMCH(dev_priv))
17925 intel_state->skip_intermediate_wm = true;
17927 ret = sanitize_watermarks_add_affected(state);
17931 ret = intel_atomic_check(&dev_priv->drm, state);
17935 /* Write calculated watermark values back */
17936 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17937 crtc_state->wm.need_postvbl_update = true;
17938 dev_priv->display.optimize_watermarks(intel_state, crtc);
17940 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17944 if (ret == -EDEADLK) {
17945 drm_atomic_state_clear(state);
17946 drm_modeset_backoff(&ctx);
17951 * If we fail here, it means that the hardware appears to be
17952 * programmed in a way that shouldn't be possible, given our
17953 * understanding of watermark requirements. This might mean a
17954 * mistake in the hardware readout code or a mistake in the
17955 * watermark calculations for a given platform. Raise a WARN
17956 * so that this is noticeable.
17958 * If this actually happens, we'll have to just leave the
17959 * BIOS-programmed watermarks untouched and hope for the best.
17961 drm_WARN(&dev_priv->drm, ret,
17962 "Could not determine valid watermarks for inherited state\n");
17964 drm_atomic_state_put(state);
17966 drm_modeset_drop_locks(&ctx);
17967 drm_modeset_acquire_fini(&ctx);
17970 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17972 if (IS_GEN(dev_priv, 5)) {
17974 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17976 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17977 } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17978 dev_priv->fdi_pll_freq = 270000;
17983 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17986 static int intel_initial_commit(struct drm_device *dev)
17988 struct drm_atomic_state *state = NULL;
17989 struct drm_modeset_acquire_ctx ctx;
17990 struct intel_crtc *crtc;
17993 state = drm_atomic_state_alloc(dev);
17997 drm_modeset_acquire_init(&ctx, 0);
18000 state->acquire_ctx = &ctx;
18002 for_each_intel_crtc(dev, crtc) {
18003 struct intel_crtc_state *crtc_state =
18004 intel_atomic_get_crtc_state(state, crtc);
18006 if (IS_ERR(crtc_state)) {
18007 ret = PTR_ERR(crtc_state);
18011 if (crtc_state->hw.active) {
18012 struct intel_encoder *encoder;
18015 * We've not yet detected sink capabilities
18016 * (audio,infoframes,etc.) and thus we don't want to
18017 * force a full state recomputation yet. We want that to
18018 * happen only for the first real commit from userspace.
18019 * So preserve the inherited flag for the time being.
18021 crtc_state->inherited = true;
18023 ret = drm_atomic_add_affected_planes(state, &crtc->base);
18028 * FIXME hack to force a LUT update to avoid the
18029 * plane update forcing the pipe gamma on without
18030 * having a proper LUT loaded. Remove once we
18031 * have readout for pipe gamma enable.
18033 crtc_state->uapi.color_mgmt_changed = true;
18035 for_each_intel_encoder_mask(dev, encoder,
18036 crtc_state->uapi.encoder_mask) {
18037 if (encoder->initial_fastset_check &&
18038 !encoder->initial_fastset_check(encoder, crtc_state)) {
18039 ret = drm_atomic_add_affected_connectors(state,
18048 ret = drm_atomic_commit(state);
18051 if (ret == -EDEADLK) {
18052 drm_atomic_state_clear(state);
18053 drm_modeset_backoff(&ctx);
18057 drm_atomic_state_put(state);
18059 drm_modeset_drop_locks(&ctx);
18060 drm_modeset_acquire_fini(&ctx);
18065 static void intel_mode_config_init(struct drm_i915_private *i915)
18067 struct drm_mode_config *mode_config = &i915->drm.mode_config;
18069 drm_mode_config_init(&i915->drm);
18070 INIT_LIST_HEAD(&i915->global_obj_list);
18072 mode_config->min_width = 0;
18073 mode_config->min_height = 0;
18075 mode_config->preferred_depth = 24;
18076 mode_config->prefer_shadow = 1;
18078 mode_config->allow_fb_modifiers = true;
18080 mode_config->funcs = &intel_mode_funcs;
18082 if (INTEL_GEN(i915) >= 9)
18083 mode_config->async_page_flip = true;
18086 * Maximum framebuffer dimensions, chosen to match
18087 * the maximum render engine surface size on gen4+.
18089 if (INTEL_GEN(i915) >= 7) {
18090 mode_config->max_width = 16384;
18091 mode_config->max_height = 16384;
18092 } else if (INTEL_GEN(i915) >= 4) {
18093 mode_config->max_width = 8192;
18094 mode_config->max_height = 8192;
18095 } else if (IS_GEN(i915, 3)) {
18096 mode_config->max_width = 4096;
18097 mode_config->max_height = 4096;
18099 mode_config->max_width = 2048;
18100 mode_config->max_height = 2048;
18103 if (IS_I845G(i915) || IS_I865G(i915)) {
18104 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
18105 mode_config->cursor_height = 1023;
18106 } else if (IS_I830(i915) || IS_I85X(i915) ||
18107 IS_I915G(i915) || IS_I915GM(i915)) {
18108 mode_config->cursor_width = 64;
18109 mode_config->cursor_height = 64;
18111 mode_config->cursor_width = 256;
18112 mode_config->cursor_height = 256;
18116 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
18118 intel_atomic_global_obj_cleanup(i915);
18119 drm_mode_config_cleanup(&i915->drm);
18122 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
18124 if (plane_config->fb) {
18125 struct drm_framebuffer *fb = &plane_config->fb->base;
18127 /* We may only have the stub and not a full framebuffer */
18128 if (drm_framebuffer_read_refcount(fb))
18129 drm_framebuffer_put(fb);
18134 if (plane_config->vma)
18135 i915_vma_put(plane_config->vma);
18138 /* part #1: call before irq install */
18139 int intel_modeset_init_noirq(struct drm_i915_private *i915)
18143 if (i915_inject_probe_failure(i915))
18146 if (HAS_DISPLAY(i915)) {
18147 ret = drm_vblank_init(&i915->drm,
18148 INTEL_NUM_PIPES(i915));
18153 intel_bios_init(i915);
18155 ret = intel_vga_register(i915);
18159 /* FIXME: completely on the wrong abstraction layer */
18160 intel_power_domains_init_hw(i915, false);
18162 intel_csr_ucode_init(i915);
18164 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
18165 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
18166 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
18168 intel_mode_config_init(i915);
18170 ret = intel_cdclk_init(i915);
18172 goto cleanup_vga_client_pw_domain_csr;
18174 ret = intel_dbuf_init(i915);
18176 goto cleanup_vga_client_pw_domain_csr;
18178 ret = intel_bw_init(i915);
18180 goto cleanup_vga_client_pw_domain_csr;
18182 init_llist_head(&i915->atomic_helper.free_list);
18183 INIT_WORK(&i915->atomic_helper.free_work,
18184 intel_atomic_helper_free_state_worker);
18186 intel_init_quirks(i915);
18188 intel_fbc_init(i915);
18192 cleanup_vga_client_pw_domain_csr:
18193 intel_csr_ucode_fini(i915);
18194 intel_power_domains_driver_remove(i915);
18195 intel_vga_unregister(i915);
18197 intel_bios_driver_remove(i915);
18202 /* part #2: call after irq install, but before gem init */
18203 int intel_modeset_init_nogem(struct drm_i915_private *i915)
18205 struct drm_device *dev = &i915->drm;
18207 struct intel_crtc *crtc;
18210 intel_init_pm(i915);
18212 intel_panel_sanitize_ssc(i915);
18214 intel_gmbus_setup(i915);
18216 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
18217 INTEL_NUM_PIPES(i915),
18218 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
18220 if (HAS_DISPLAY(i915)) {
18221 for_each_pipe(i915, pipe) {
18222 ret = intel_crtc_init(i915, pipe);
18224 intel_mode_config_cleanup(i915);
18230 intel_plane_possible_crtcs_init(i915);
18231 intel_shared_dpll_init(dev);
18232 intel_update_fdi_pll_freq(i915);
18234 intel_update_czclk(i915);
18235 intel_modeset_init_hw(i915);
18237 intel_hdcp_component_init(i915);
18239 if (i915->max_cdclk_freq == 0)
18240 intel_update_max_cdclk(i915);
18243 * If the platform has HTI, we need to find out whether it has reserved
18244 * any display resources before we create our display outputs.
18246 if (INTEL_INFO(i915)->display.has_hti)
18247 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
18249 /* Just disable it once at startup */
18250 intel_vga_disable(i915);
18251 intel_setup_outputs(i915);
18253 drm_modeset_lock_all(dev);
18254 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
18255 drm_modeset_unlock_all(dev);
18257 for_each_intel_crtc(dev, crtc) {
18258 struct intel_initial_plane_config plane_config = {};
18264 * Note that reserving the BIOS fb up front prevents us
18265 * from stuffing other stolen allocations like the ring
18266 * on top. This prevents some ugliness at boot time, and
18267 * can even allow for smooth boot transitions if the BIOS
18268 * fb is large enough for the active pipe configuration.
18270 i915->display.get_initial_plane_config(crtc, &plane_config);
18273 * If the fb is shared between multiple heads, we'll
18274 * just get the first one.
18276 intel_find_initial_plane_obj(crtc, &plane_config);
18278 plane_config_fini(&plane_config);
18282 * Make sure hardware watermarks really match the state we read out.
18283 * Note that we need to do this after reconstructing the BIOS fb's
18284 * since the watermark calculation done here will use pstate->fb.
18286 if (!HAS_GMCH(i915))
18287 sanitize_watermarks(i915);
18290 * Force all active planes to recompute their states. So that on
18291 * mode_setcrtc after probe, all the intel_plane_state variables
18292 * are already calculated and there is no assert_plane warnings
18295 ret = intel_initial_commit(dev);
18297 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18302 /* part #3: call after gem init */
18303 int intel_modeset_init(struct drm_i915_private *i915)
18307 if (!HAS_DISPLAY(i915))
18310 intel_overlay_setup(i915);
18312 ret = intel_fbdev_init(&i915->drm);
18316 /* Only enable hotplug handling once the fbdev is fully set up. */
18317 intel_hpd_init(i915);
18318 intel_hpd_poll_disable(i915);
18320 intel_init_ipc(i915);
18325 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18327 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18328 /* 640x480@60Hz, ~25175 kHz */
18329 struct dpll clock = {
18339 drm_WARN_ON(&dev_priv->drm,
18340 i9xx_calc_dpll_params(48000, &clock) != 25154);
18342 drm_dbg_kms(&dev_priv->drm,
18343 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
18344 pipe_name(pipe), clock.vco, clock.dot);
18346 fp = i9xx_dpll_compute_fp(&clock);
18347 dpll = DPLL_DVO_2X_MODE |
18348 DPLL_VGA_MODE_DIS |
18349 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
18350 PLL_P2_DIVIDE_BY_4 |
18351 PLL_REF_INPUT_DREFCLK |
18354 intel_de_write(dev_priv, FP0(pipe), fp);
18355 intel_de_write(dev_priv, FP1(pipe), fp);
18357 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
18358 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
18359 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
18360 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
18361 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
18362 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
18363 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
18366 * Apparently we need to have VGA mode enabled prior to changing
18367 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
18368 * dividers, even though the register value does change.
18370 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
18371 intel_de_write(dev_priv, DPLL(pipe), dpll);
18373 /* Wait for the clocks to stabilize. */
18374 intel_de_posting_read(dev_priv, DPLL(pipe));
18377 /* The pixel multiplier can only be updated once the
18378 * DPLL is enabled and the clocks are stable.
18380 * So write it again.
18382 intel_de_write(dev_priv, DPLL(pipe), dpll);
18384 /* We do this three times for luck */
18385 for (i = 0; i < 3 ; i++) {
18386 intel_de_write(dev_priv, DPLL(pipe), dpll);
18387 intel_de_posting_read(dev_priv, DPLL(pipe));
18388 udelay(150); /* wait for warmup */
18391 intel_de_write(dev_priv, PIPECONF(pipe),
18392 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
18393 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18395 intel_wait_for_pipe_scanline_moving(crtc);
18398 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
18400 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18402 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18405 drm_WARN_ON(&dev_priv->drm,
18406 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18407 DISPLAY_PLANE_ENABLE);
18408 drm_WARN_ON(&dev_priv->drm,
18409 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18410 DISPLAY_PLANE_ENABLE);
18411 drm_WARN_ON(&dev_priv->drm,
18412 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18413 DISPLAY_PLANE_ENABLE);
18414 drm_WARN_ON(&dev_priv->drm,
18415 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18416 drm_WARN_ON(&dev_priv->drm,
18417 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18419 intel_de_write(dev_priv, PIPECONF(pipe), 0);
18420 intel_de_posting_read(dev_priv, PIPECONF(pipe));
18422 intel_wait_for_pipe_scanline_stopped(crtc);
18424 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18425 intel_de_posting_read(dev_priv, DPLL(pipe));
18429 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18431 struct intel_crtc *crtc;
18433 if (INTEL_GEN(dev_priv) >= 4)
18436 for_each_intel_crtc(&dev_priv->drm, crtc) {
18437 struct intel_plane *plane =
18438 to_intel_plane(crtc->base.primary);
18439 struct intel_crtc *plane_crtc;
18442 if (!plane->get_hw_state(plane, &pipe))
18445 if (pipe == crtc->pipe)
18448 drm_dbg_kms(&dev_priv->drm,
18449 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18450 plane->base.base.id, plane->base.name);
18452 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18453 intel_plane_disable_noatomic(plane_crtc, plane);
18457 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18459 struct drm_device *dev = crtc->base.dev;
18460 struct intel_encoder *encoder;
18462 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18468 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18470 struct drm_device *dev = encoder->base.dev;
18471 struct intel_connector *connector;
18473 for_each_connector_on_encoder(dev, &encoder->base, connector)
18479 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18480 enum pipe pch_transcoder)
18482 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18483 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18486 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18489 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18490 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18492 if (INTEL_GEN(dev_priv) >= 9 ||
18493 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18494 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18497 if (transcoder_is_dsi(cpu_transcoder))
18500 val = intel_de_read(dev_priv, reg);
18501 val &= ~HSW_FRAME_START_DELAY_MASK;
18502 val |= HSW_FRAME_START_DELAY(0);
18503 intel_de_write(dev_priv, reg, val);
18505 i915_reg_t reg = PIPECONF(cpu_transcoder);
18508 val = intel_de_read(dev_priv, reg);
18509 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18510 val |= PIPECONF_FRAME_START_DELAY(0);
18511 intel_de_write(dev_priv, reg, val);
18514 if (!crtc_state->has_pch_encoder)
18517 if (HAS_PCH_IBX(dev_priv)) {
18518 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18521 val = intel_de_read(dev_priv, reg);
18522 val &= ~TRANS_FRAME_START_DELAY_MASK;
18523 val |= TRANS_FRAME_START_DELAY(0);
18524 intel_de_write(dev_priv, reg, val);
18526 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18527 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18530 val = intel_de_read(dev_priv, reg);
18531 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18532 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18533 intel_de_write(dev_priv, reg, val);
18537 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18538 struct drm_modeset_acquire_ctx *ctx)
18540 struct drm_device *dev = crtc->base.dev;
18541 struct drm_i915_private *dev_priv = to_i915(dev);
18542 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18544 if (crtc_state->hw.active) {
18545 struct intel_plane *plane;
18547 /* Clear any frame start delays used for debugging left by the BIOS */
18548 intel_sanitize_frame_start_delay(crtc_state);
18550 /* Disable everything but the primary plane */
18551 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18552 const struct intel_plane_state *plane_state =
18553 to_intel_plane_state(plane->base.state);
18555 if (plane_state->uapi.visible &&
18556 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18557 intel_plane_disable_noatomic(crtc, plane);
18561 * Disable any background color set by the BIOS, but enable the
18562 * gamma and CSC to match how we program our planes.
18564 if (INTEL_GEN(dev_priv) >= 9)
18565 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18566 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18569 /* Adjust the state of the output pipe according to whether we
18570 * have active connectors/encoders. */
18571 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18572 intel_crtc_disable_noatomic(crtc, ctx);
18574 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18576 * We start out with underrun reporting disabled to avoid races.
18577 * For correct bookkeeping mark this on active crtcs.
18579 * Also on gmch platforms we dont have any hardware bits to
18580 * disable the underrun reporting. Which means we need to start
18581 * out with underrun reporting disabled also on inactive pipes,
18582 * since otherwise we'll complain about the garbage we read when
18583 * e.g. coming up after runtime pm.
18585 * No protection against concurrent access is required - at
18586 * worst a fifo underrun happens which also sets this to false.
18588 crtc->cpu_fifo_underrun_disabled = true;
18590 * We track the PCH trancoder underrun reporting state
18591 * within the crtc. With crtc for pipe A housing the underrun
18592 * reporting state for PCH transcoder A, crtc for pipe B housing
18593 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18594 * and marking underrun reporting as disabled for the non-existing
18595 * PCH transcoders B and C would prevent enabling the south
18596 * error interrupt (see cpt_can_enable_serr_int()).
18598 if (has_pch_trancoder(dev_priv, crtc->pipe))
18599 crtc->pch_fifo_underrun_disabled = true;
18603 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18605 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18608 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18609 * the hardware when a high res displays plugged in. DPLL P
18610 * divider is zero, and the pipe timings are bonkers. We'll
18611 * try to disable everything in that case.
18613 * FIXME would be nice to be able to sanitize this state
18614 * without several WARNs, but for now let's take the easy
18617 return IS_GEN(dev_priv, 6) &&
18618 crtc_state->hw.active &&
18619 crtc_state->shared_dpll &&
18620 crtc_state->port_clock == 0;
18623 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18625 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18626 struct intel_connector *connector;
18627 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18628 struct intel_crtc_state *crtc_state = crtc ?
18629 to_intel_crtc_state(crtc->base.state) : NULL;
18631 /* We need to check both for a crtc link (meaning that the
18632 * encoder is active and trying to read from a pipe) and the
18633 * pipe itself being active. */
18634 bool has_active_crtc = crtc_state &&
18635 crtc_state->hw.active;
18637 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18638 drm_dbg_kms(&dev_priv->drm,
18639 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18640 pipe_name(crtc->pipe));
18641 has_active_crtc = false;
18644 connector = intel_encoder_find_connector(encoder);
18645 if (connector && !has_active_crtc) {
18646 drm_dbg_kms(&dev_priv->drm,
18647 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18648 encoder->base.base.id,
18649 encoder->base.name);
18651 /* Connector is active, but has no active pipe. This is
18652 * fallout from our resume register restoring. Disable
18653 * the encoder manually again. */
18655 struct drm_encoder *best_encoder;
18657 drm_dbg_kms(&dev_priv->drm,
18658 "[ENCODER:%d:%s] manually disabled\n",
18659 encoder->base.base.id,
18660 encoder->base.name);
18662 /* avoid oopsing in case the hooks consult best_encoder */
18663 best_encoder = connector->base.state->best_encoder;
18664 connector->base.state->best_encoder = &encoder->base;
18666 /* FIXME NULL atomic state passed! */
18667 if (encoder->disable)
18668 encoder->disable(NULL, encoder, crtc_state,
18669 connector->base.state);
18670 if (encoder->post_disable)
18671 encoder->post_disable(NULL, encoder, crtc_state,
18672 connector->base.state);
18674 connector->base.state->best_encoder = best_encoder;
18676 encoder->base.crtc = NULL;
18678 /* Inconsistent output/port/pipe state happens presumably due to
18679 * a bug in one of the get_hw_state functions. Or someplace else
18680 * in our code, like the register restore mess on resume. Clamp
18681 * things to off as a safer default. */
18683 connector->base.dpms = DRM_MODE_DPMS_OFF;
18684 connector->base.encoder = NULL;
18687 /* notify opregion of the sanitized encoder state */
18688 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18690 if (INTEL_GEN(dev_priv) >= 11)
18691 icl_sanitize_encoder_pll_mapping(encoder);
18694 /* FIXME read out full plane state for all planes */
18695 static void readout_plane_state(struct drm_i915_private *dev_priv)
18697 struct intel_plane *plane;
18698 struct intel_crtc *crtc;
18700 for_each_intel_plane(&dev_priv->drm, plane) {
18701 struct intel_plane_state *plane_state =
18702 to_intel_plane_state(plane->base.state);
18703 struct intel_crtc_state *crtc_state;
18704 enum pipe pipe = PIPE_A;
18707 visible = plane->get_hw_state(plane, &pipe);
18709 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18710 crtc_state = to_intel_crtc_state(crtc->base.state);
18712 intel_set_plane_visible(crtc_state, plane_state, visible);
18714 drm_dbg_kms(&dev_priv->drm,
18715 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18716 plane->base.base.id, plane->base.name,
18717 enableddisabled(visible), pipe_name(pipe));
18720 for_each_intel_crtc(&dev_priv->drm, crtc) {
18721 struct intel_crtc_state *crtc_state =
18722 to_intel_crtc_state(crtc->base.state);
18724 fixup_active_planes(crtc_state);
18728 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18730 struct drm_i915_private *dev_priv = to_i915(dev);
18731 struct intel_cdclk_state *cdclk_state =
18732 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18733 struct intel_dbuf_state *dbuf_state =
18734 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
18736 struct intel_crtc *crtc;
18737 struct intel_encoder *encoder;
18738 struct intel_connector *connector;
18739 struct drm_connector_list_iter conn_iter;
18740 u8 active_pipes = 0;
18742 for_each_intel_crtc(dev, crtc) {
18743 struct intel_crtc_state *crtc_state =
18744 to_intel_crtc_state(crtc->base.state);
18746 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18747 intel_crtc_free_hw_state(crtc_state);
18748 intel_crtc_state_reset(crtc_state, crtc);
18750 intel_crtc_get_pipe_config(crtc_state);
18752 crtc_state->hw.enable = crtc_state->hw.active;
18754 crtc->base.enabled = crtc_state->hw.enable;
18755 crtc->active = crtc_state->hw.active;
18757 if (crtc_state->hw.active)
18758 active_pipes |= BIT(crtc->pipe);
18760 drm_dbg_kms(&dev_priv->drm,
18761 "[CRTC:%d:%s] hw state readout: %s\n",
18762 crtc->base.base.id, crtc->base.name,
18763 enableddisabled(crtc_state->hw.active));
18766 dev_priv->active_pipes = cdclk_state->active_pipes =
18767 dbuf_state->active_pipes = active_pipes;
18769 readout_plane_state(dev_priv);
18771 intel_dpll_readout_hw_state(dev_priv);
18773 for_each_intel_encoder(dev, encoder) {
18776 if (encoder->get_hw_state(encoder, &pipe)) {
18777 struct intel_crtc_state *crtc_state;
18779 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18780 crtc_state = to_intel_crtc_state(crtc->base.state);
18782 encoder->base.crtc = &crtc->base;
18783 intel_encoder_get_config(encoder, crtc_state);
18784 if (encoder->sync_state)
18785 encoder->sync_state(encoder, crtc_state);
18787 encoder->base.crtc = NULL;
18790 drm_dbg_kms(&dev_priv->drm,
18791 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18792 encoder->base.base.id, encoder->base.name,
18793 enableddisabled(encoder->base.crtc),
18797 drm_connector_list_iter_begin(dev, &conn_iter);
18798 for_each_intel_connector_iter(connector, &conn_iter) {
18799 if (connector->get_hw_state(connector)) {
18800 struct intel_crtc_state *crtc_state;
18801 struct intel_crtc *crtc;
18803 connector->base.dpms = DRM_MODE_DPMS_ON;
18805 encoder = intel_attached_encoder(connector);
18806 connector->base.encoder = &encoder->base;
18808 crtc = to_intel_crtc(encoder->base.crtc);
18809 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18811 if (crtc_state && crtc_state->hw.active) {
18813 * This has to be done during hardware readout
18814 * because anything calling .crtc_disable may
18815 * rely on the connector_mask being accurate.
18817 crtc_state->uapi.connector_mask |=
18818 drm_connector_mask(&connector->base);
18819 crtc_state->uapi.encoder_mask |=
18820 drm_encoder_mask(&encoder->base);
18823 connector->base.dpms = DRM_MODE_DPMS_OFF;
18824 connector->base.encoder = NULL;
18826 drm_dbg_kms(&dev_priv->drm,
18827 "[CONNECTOR:%d:%s] hw state readout: %s\n",
18828 connector->base.base.id, connector->base.name,
18829 enableddisabled(connector->base.encoder));
18831 drm_connector_list_iter_end(&conn_iter);
18833 for_each_intel_crtc(dev, crtc) {
18834 struct intel_bw_state *bw_state =
18835 to_intel_bw_state(dev_priv->bw_obj.state);
18836 struct intel_crtc_state *crtc_state =
18837 to_intel_crtc_state(crtc->base.state);
18838 struct intel_plane *plane;
18841 if (crtc_state->hw.active) {
18842 struct drm_display_mode *mode = &crtc_state->hw.mode;
18844 intel_mode_from_crtc_timings(&crtc_state->hw.adjusted_mode,
18845 &crtc_state->hw.adjusted_mode);
18847 *mode = crtc_state->hw.adjusted_mode;
18848 mode->hdisplay = crtc_state->pipe_src_w;
18849 mode->vdisplay = crtc_state->pipe_src_h;
18852 * The initial mode needs to be set in order to keep
18853 * the atomic core happy. It wants a valid mode if the
18854 * crtc's enabled, so we do the above call.
18856 * But we don't set all the derived state fully, hence
18857 * set a flag to indicate that a full recalculation is
18858 * needed on the next commit.
18860 crtc_state->inherited = true;
18862 intel_crtc_compute_pixel_rate(crtc_state);
18864 intel_crtc_update_active_timings(crtc_state);
18866 intel_crtc_copy_hw_to_uapi_state(crtc_state);
18869 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18870 const struct intel_plane_state *plane_state =
18871 to_intel_plane_state(plane->base.state);
18874 * FIXME don't have the fb yet, so can't
18875 * use intel_plane_data_rate() :(
18877 if (plane_state->uapi.visible)
18878 crtc_state->data_rate[plane->id] =
18879 4 * crtc_state->pixel_rate;
18881 * FIXME don't have the fb yet, so can't
18882 * use plane->min_cdclk() :(
18884 if (plane_state->uapi.visible && plane->min_cdclk) {
18885 if (crtc_state->double_wide ||
18886 INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18887 crtc_state->min_cdclk[plane->id] =
18888 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18890 crtc_state->min_cdclk[plane->id] =
18891 crtc_state->pixel_rate;
18893 drm_dbg_kms(&dev_priv->drm,
18894 "[PLANE:%d:%s] min_cdclk %d kHz\n",
18895 plane->base.base.id, plane->base.name,
18896 crtc_state->min_cdclk[plane->id]);
18899 if (crtc_state->hw.active) {
18900 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18901 if (drm_WARN_ON(dev, min_cdclk < 0))
18905 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18906 cdclk_state->min_voltage_level[crtc->pipe] =
18907 crtc_state->min_voltage_level;
18909 intel_bw_crtc_update(bw_state, crtc_state);
18911 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18916 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18918 struct intel_encoder *encoder;
18920 for_each_intel_encoder(&dev_priv->drm, encoder) {
18921 struct intel_crtc_state *crtc_state;
18923 if (!encoder->get_power_domains)
18927 * MST-primary and inactive encoders don't have a crtc state
18928 * and neither of these require any power domain references.
18930 if (!encoder->base.crtc)
18933 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18934 encoder->get_power_domains(encoder, crtc_state);
18938 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18941 * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18942 * Also known as Wa_14010480278.
18944 if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18945 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18946 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18948 if (IS_HASWELL(dev_priv)) {
18950 * WaRsPkgCStateDisplayPMReq:hsw
18951 * System hang if this isn't done before disabling all planes!
18953 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18954 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18957 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
18958 /* Display WA #1142:kbl,cfl,cml */
18959 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
18960 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
18961 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
18962 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
18963 KBL_ARB_FILL_SPARE_14);
18967 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18968 enum port port, i915_reg_t hdmi_reg)
18970 u32 val = intel_de_read(dev_priv, hdmi_reg);
18972 if (val & SDVO_ENABLE ||
18973 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18976 drm_dbg_kms(&dev_priv->drm,
18977 "Sanitizing transcoder select for HDMI %c\n",
18980 val &= ~SDVO_PIPE_SEL_MASK;
18981 val |= SDVO_PIPE_SEL(PIPE_A);
18983 intel_de_write(dev_priv, hdmi_reg, val);
18986 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18987 enum port port, i915_reg_t dp_reg)
18989 u32 val = intel_de_read(dev_priv, dp_reg);
18991 if (val & DP_PORT_EN ||
18992 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18995 drm_dbg_kms(&dev_priv->drm,
18996 "Sanitizing transcoder select for DP %c\n",
18999 val &= ~DP_PIPE_SEL_MASK;
19000 val |= DP_PIPE_SEL(PIPE_A);
19002 intel_de_write(dev_priv, dp_reg, val);
19005 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
19008 * The BIOS may select transcoder B on some of the PCH
19009 * ports even it doesn't enable the port. This would trip
19010 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
19011 * Sanitize the transcoder select bits to prevent that. We
19012 * assume that the BIOS never actually enabled the port,
19013 * because if it did we'd actually have to toggle the port
19014 * on and back off to make the transcoder A select stick
19015 * (see. intel_dp_link_down(), intel_disable_hdmi(),
19016 * intel_disable_sdvo()).
19018 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
19019 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
19020 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
19022 /* PCH SDVOB multiplex with HDMIB */
19023 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
19024 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
19025 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
19028 /* Scan out the current hw modeset state,
19029 * and sanitizes it to the current state
19032 intel_modeset_setup_hw_state(struct drm_device *dev,
19033 struct drm_modeset_acquire_ctx *ctx)
19035 struct drm_i915_private *dev_priv = to_i915(dev);
19036 struct intel_encoder *encoder;
19037 struct intel_crtc *crtc;
19038 intel_wakeref_t wakeref;
19040 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
19042 intel_early_display_was(dev_priv);
19043 intel_modeset_readout_hw_state(dev);
19045 /* HW state is read out, now we need to sanitize this mess. */
19047 /* Sanitize the TypeC port mode upfront, encoders depend on this */
19048 for_each_intel_encoder(dev, encoder) {
19049 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
19051 /* We need to sanitize only the MST primary port. */
19052 if (encoder->type != INTEL_OUTPUT_DP_MST &&
19053 intel_phy_is_tc(dev_priv, phy))
19054 intel_tc_port_sanitize(enc_to_dig_port(encoder));
19057 get_encoder_power_domains(dev_priv);
19059 if (HAS_PCH_IBX(dev_priv))
19060 ibx_sanitize_pch_ports(dev_priv);
19063 * intel_sanitize_plane_mapping() may need to do vblank
19064 * waits, so we need vblank interrupts restored beforehand.
19066 for_each_intel_crtc(&dev_priv->drm, crtc) {
19067 struct intel_crtc_state *crtc_state =
19068 to_intel_crtc_state(crtc->base.state);
19070 drm_crtc_vblank_reset(&crtc->base);
19072 if (crtc_state->hw.active)
19073 intel_crtc_vblank_on(crtc_state);
19076 intel_sanitize_plane_mapping(dev_priv);
19078 for_each_intel_encoder(dev, encoder)
19079 intel_sanitize_encoder(encoder);
19081 for_each_intel_crtc(&dev_priv->drm, crtc) {
19082 struct intel_crtc_state *crtc_state =
19083 to_intel_crtc_state(crtc->base.state);
19085 intel_sanitize_crtc(crtc, ctx);
19086 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
19089 intel_modeset_update_connector_atomic_state(dev);
19091 intel_dpll_sanitize_state(dev_priv);
19093 if (IS_G4X(dev_priv)) {
19094 g4x_wm_get_hw_state(dev_priv);
19095 g4x_wm_sanitize(dev_priv);
19096 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
19097 vlv_wm_get_hw_state(dev_priv);
19098 vlv_wm_sanitize(dev_priv);
19099 } else if (INTEL_GEN(dev_priv) >= 9) {
19100 skl_wm_get_hw_state(dev_priv);
19101 } else if (HAS_PCH_SPLIT(dev_priv)) {
19102 ilk_wm_get_hw_state(dev_priv);
19105 for_each_intel_crtc(dev, crtc) {
19106 struct intel_crtc_state *crtc_state =
19107 to_intel_crtc_state(crtc->base.state);
19110 put_domains = modeset_get_crtc_power_domains(crtc_state);
19111 if (drm_WARN_ON(dev, put_domains))
19112 modeset_put_power_domains(dev_priv, put_domains);
19115 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
19118 void intel_display_resume(struct drm_device *dev)
19120 struct drm_i915_private *dev_priv = to_i915(dev);
19121 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
19122 struct drm_modeset_acquire_ctx ctx;
19125 dev_priv->modeset_restore_state = NULL;
19127 state->acquire_ctx = &ctx;
19129 drm_modeset_acquire_init(&ctx, 0);
19132 ret = drm_modeset_lock_all_ctx(dev, &ctx);
19133 if (ret != -EDEADLK)
19136 drm_modeset_backoff(&ctx);
19140 ret = __intel_display_resume(dev, state, &ctx);
19142 intel_enable_ipc(dev_priv);
19143 drm_modeset_drop_locks(&ctx);
19144 drm_modeset_acquire_fini(&ctx);
19147 drm_err(&dev_priv->drm,
19148 "Restoring old state failed with %i\n", ret);
19150 drm_atomic_state_put(state);
19153 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
19155 struct intel_connector *connector;
19156 struct drm_connector_list_iter conn_iter;
19158 /* Kill all the work that may have been queued by hpd. */
19159 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
19160 for_each_intel_connector_iter(connector, &conn_iter) {
19161 if (connector->modeset_retry_work.func)
19162 cancel_work_sync(&connector->modeset_retry_work);
19163 if (connector->hdcp.shim) {
19164 cancel_delayed_work_sync(&connector->hdcp.check_work);
19165 cancel_work_sync(&connector->hdcp.prop_work);
19168 drm_connector_list_iter_end(&conn_iter);
19171 /* part #1: call before irq uninstall */
19172 void intel_modeset_driver_remove(struct drm_i915_private *i915)
19174 flush_workqueue(i915->flip_wq);
19175 flush_workqueue(i915->modeset_wq);
19177 flush_work(&i915->atomic_helper.free_work);
19178 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
19181 /* part #2: call after irq uninstall */
19182 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
19185 * Due to the hpd irq storm handling the hotplug work can re-arm the
19186 * poll handlers. Hence disable polling after hpd handling is shut down.
19188 intel_hpd_poll_fini(i915);
19191 * MST topology needs to be suspended so we don't have any calls to
19192 * fbdev after it's finalized. MST will be destroyed later as part of
19193 * drm_mode_config_cleanup()
19195 intel_dp_mst_suspend(i915);
19197 /* poll work can call into fbdev, hence clean that up afterwards */
19198 intel_fbdev_fini(i915);
19200 intel_unregister_dsm_handler();
19202 intel_fbc_global_disable(i915);
19204 /* flush any delayed tasks or pending work */
19205 flush_scheduled_work();
19207 intel_hdcp_component_fini(i915);
19209 intel_mode_config_cleanup(i915);
19211 intel_overlay_cleanup(i915);
19213 intel_gmbus_teardown(i915);
19215 destroy_workqueue(i915->flip_wq);
19216 destroy_workqueue(i915->modeset_wq);
19218 intel_fbc_cleanup_cfb(i915);
19221 /* part #3: call after gem init */
19222 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
19224 intel_csr_ucode_fini(i915);
19226 intel_power_domains_driver_remove(i915);
19228 intel_vga_unregister(i915);
19230 intel_bios_driver_remove(i915);
19233 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
19235 struct intel_display_error_state {
19237 u32 power_well_driver;
19239 struct intel_cursor_error_state {
19244 } cursor[I915_MAX_PIPES];
19246 struct intel_pipe_error_state {
19247 bool power_domain_on;
19250 } pipe[I915_MAX_PIPES];
19252 struct intel_plane_error_state {
19260 } plane[I915_MAX_PIPES];
19262 struct intel_transcoder_error_state {
19264 bool power_domain_on;
19265 enum transcoder cpu_transcoder;
19278 struct intel_display_error_state *
19279 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
19281 struct intel_display_error_state *error;
19282 int transcoders[] = {
19291 BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
19293 if (!HAS_DISPLAY(dev_priv))
19296 error = kzalloc(sizeof(*error), GFP_ATOMIC);
19300 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19301 error->power_well_driver = intel_de_read(dev_priv,
19302 HSW_PWR_WELL_CTL2);
19304 for_each_pipe(dev_priv, i) {
19305 error->pipe[i].power_domain_on =
19306 __intel_display_power_is_enabled(dev_priv,
19307 POWER_DOMAIN_PIPE(i));
19308 if (!error->pipe[i].power_domain_on)
19311 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
19312 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
19313 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
19315 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
19316 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
19317 if (INTEL_GEN(dev_priv) <= 3) {
19318 error->plane[i].size = intel_de_read(dev_priv,
19320 error->plane[i].pos = intel_de_read(dev_priv,
19323 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19324 error->plane[i].addr = intel_de_read(dev_priv,
19326 if (INTEL_GEN(dev_priv) >= 4) {
19327 error->plane[i].surface = intel_de_read(dev_priv,
19329 error->plane[i].tile_offset = intel_de_read(dev_priv,
19333 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
19335 if (HAS_GMCH(dev_priv))
19336 error->pipe[i].stat = intel_de_read(dev_priv,
19340 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19341 enum transcoder cpu_transcoder = transcoders[i];
19343 if (!HAS_TRANSCODER(dev_priv, cpu_transcoder))
19346 error->transcoder[i].available = true;
19347 error->transcoder[i].power_domain_on =
19348 __intel_display_power_is_enabled(dev_priv,
19349 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
19350 if (!error->transcoder[i].power_domain_on)
19353 error->transcoder[i].cpu_transcoder = cpu_transcoder;
19355 error->transcoder[i].conf = intel_de_read(dev_priv,
19356 PIPECONF(cpu_transcoder));
19357 error->transcoder[i].htotal = intel_de_read(dev_priv,
19358 HTOTAL(cpu_transcoder));
19359 error->transcoder[i].hblank = intel_de_read(dev_priv,
19360 HBLANK(cpu_transcoder));
19361 error->transcoder[i].hsync = intel_de_read(dev_priv,
19362 HSYNC(cpu_transcoder));
19363 error->transcoder[i].vtotal = intel_de_read(dev_priv,
19364 VTOTAL(cpu_transcoder));
19365 error->transcoder[i].vblank = intel_de_read(dev_priv,
19366 VBLANK(cpu_transcoder));
19367 error->transcoder[i].vsync = intel_de_read(dev_priv,
19368 VSYNC(cpu_transcoder));
19374 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
19377 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
19378 struct intel_display_error_state *error)
19380 struct drm_i915_private *dev_priv = m->i915;
19386 err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
19387 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
19388 err_printf(m, "PWR_WELL_CTL2: %08x\n",
19389 error->power_well_driver);
19390 for_each_pipe(dev_priv, i) {
19391 err_printf(m, "Pipe [%d]:\n", i);
19392 err_printf(m, " Power: %s\n",
19393 onoff(error->pipe[i].power_domain_on));
19394 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
19395 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
19397 err_printf(m, "Plane [%d]:\n", i);
19398 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
19399 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
19400 if (INTEL_GEN(dev_priv) <= 3) {
19401 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
19402 err_printf(m, " POS: %08x\n", error->plane[i].pos);
19404 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
19405 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
19406 if (INTEL_GEN(dev_priv) >= 4) {
19407 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
19408 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
19411 err_printf(m, "Cursor [%d]:\n", i);
19412 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
19413 err_printf(m, " POS: %08x\n", error->cursor[i].position);
19414 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
19417 for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
19418 if (!error->transcoder[i].available)
19421 err_printf(m, "CPU transcoder: %s\n",
19422 transcoder_name(error->transcoder[i].cpu_transcoder));
19423 err_printf(m, " Power: %s\n",
19424 onoff(error->transcoder[i].power_domain_on));
19425 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
19426 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
19427 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
19428 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
19429 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
19430 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
19431 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);