2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <acpi/video.h>
28 #include <linux/i2c.h>
29 #include <linux/input.h>
30 #include <linux/intel-iommu.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/dma-resv.h>
34 #include <linux/slab.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_damage_helper.h>
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_edid.h>
42 #include <drm/drm_fourcc.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/drm_rect.h>
47 #include "display/intel_audio.h"
48 #include "display/intel_crt.h"
49 #include "display/intel_ddi.h"
50 #include "display/intel_display_debugfs.h"
51 #include "display/intel_dp.h"
52 #include "display/intel_dp_mst.h"
53 #include "display/intel_dpll.h"
54 #include "display/intel_dpll_mgr.h"
55 #include "display/intel_dsi.h"
56 #include "display/intel_dvo.h"
57 #include "display/intel_fb.h"
58 #include "display/intel_gmbus.h"
59 #include "display/intel_hdmi.h"
60 #include "display/intel_lvds.h"
61 #include "display/intel_sdvo.h"
62 #include "display/intel_snps_phy.h"
63 #include "display/intel_tv.h"
64 #include "display/intel_vdsc.h"
65 #include "display/intel_vrr.h"
67 #include "gem/i915_gem_lmem.h"
68 #include "gem/i915_gem_object.h"
70 #include "gt/intel_rps.h"
71 #include "gt/gen8_ppgtt.h"
76 #include "intel_acpi.h"
77 #include "intel_atomic.h"
78 #include "intel_atomic_plane.h"
80 #include "intel_cdclk.h"
81 #include "intel_color.h"
82 #include "intel_crtc.h"
84 #include "intel_display_types.h"
85 #include "intel_dmc.h"
86 #include "intel_dp_link_training.h"
87 #include "intel_dpt.h"
88 #include "intel_fbc.h"
89 #include "intel_fdi.h"
90 #include "intel_fbdev.h"
91 #include "intel_fifo_underrun.h"
92 #include "intel_frontbuffer.h"
93 #include "intel_hdcp.h"
94 #include "intel_hotplug.h"
95 #include "intel_overlay.h"
96 #include "intel_pipe_crc.h"
98 #include "intel_pps.h"
99 #include "intel_psr.h"
100 #include "intel_quirks.h"
101 #include "intel_sideband.h"
102 #include "intel_sprite.h"
103 #include "intel_tc.h"
104 #include "intel_vga.h"
105 #include "i9xx_plane.h"
106 #include "skl_scaler.h"
107 #include "skl_universal_plane.h"
109 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
110 struct intel_crtc_state *pipe_config);
111 static void ilk_pch_clock_get(struct intel_crtc *crtc,
112 struct intel_crtc_state *pipe_config);
114 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
115 struct drm_i915_gem_object *obj,
116 struct drm_mode_fb_cmd2 *mode_cmd);
117 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
118 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
119 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
120 const struct intel_link_m_n *m_n,
121 const struct intel_link_m_n *m2_n2);
122 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
123 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
124 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
125 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
126 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
127 static void intel_modeset_setup_hw_state(struct drm_device *dev,
128 struct drm_modeset_acquire_ctx *ctx);
130 /* returns HPLL frequency in kHz */
131 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
133 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
135 /* Obtain SKU information */
136 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
137 CCK_FUSE_HPLL_FREQ_MASK;
139 return vco_freq[hpll_freq] * 1000;
142 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
143 const char *name, u32 reg, int ref_freq)
148 val = vlv_cck_read(dev_priv, reg);
149 divider = val & CCK_FREQUENCY_VALUES;
151 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
152 (divider << CCK_FREQUENCY_STATUS_SHIFT),
153 "%s change in progress\n", name);
155 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
158 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
159 const char *name, u32 reg)
163 vlv_cck_get(dev_priv);
165 if (dev_priv->hpll_freq == 0)
166 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
168 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
170 vlv_cck_put(dev_priv);
175 static void intel_update_czclk(struct drm_i915_private *dev_priv)
177 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
180 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
181 CCK_CZ_CLOCK_CONTROL);
183 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
184 dev_priv->czclk_freq);
187 /* WA Display #0827: Gen9:all */
189 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
192 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
193 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
195 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
196 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
199 /* Wa_2006604312:icl,ehl */
201 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
205 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
206 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
208 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
209 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
213 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
215 return crtc_state->master_transcoder != INVALID_TRANSCODER;
219 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
221 return crtc_state->sync_mode_slaves_mask != 0;
225 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
227 return is_trans_port_sync_master(crtc_state) ||
228 is_trans_port_sync_slave(crtc_state);
231 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
234 i915_reg_t reg = PIPEDSL(pipe);
238 if (DISPLAY_VER(dev_priv) == 2)
239 line_mask = DSL_LINEMASK_GEN2;
241 line_mask = DSL_LINEMASK_GEN3;
243 line1 = intel_de_read(dev_priv, reg) & line_mask;
245 line2 = intel_de_read(dev_priv, reg) & line_mask;
247 return line1 != line2;
250 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
252 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
253 enum pipe pipe = crtc->pipe;
255 /* Wait for the display line to settle/start moving */
256 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
257 drm_err(&dev_priv->drm,
258 "pipe %c scanline %s wait timed out\n",
259 pipe_name(pipe), onoff(state));
262 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
264 wait_for_pipe_scanline_moving(crtc, false);
267 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
269 wait_for_pipe_scanline_moving(crtc, true);
273 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
275 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
276 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
278 if (DISPLAY_VER(dev_priv) >= 4) {
279 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
280 i915_reg_t reg = PIPECONF(cpu_transcoder);
282 /* Wait for the Pipe State to go off */
283 if (intel_de_wait_for_clear(dev_priv, reg,
284 I965_PIPECONF_ACTIVE, 100))
285 drm_WARN(&dev_priv->drm, 1,
286 "pipe_off wait timed out\n");
288 intel_wait_for_pipe_scanline_stopped(crtc);
292 /* Only for pre-ILK configs */
293 void assert_pll(struct drm_i915_private *dev_priv,
294 enum pipe pipe, bool state)
299 val = intel_de_read(dev_priv, DPLL(pipe));
300 cur_state = !!(val & DPLL_VCO_ENABLE);
301 I915_STATE_WARN(cur_state != state,
302 "PLL state assertion failure (expected %s, current %s)\n",
303 onoff(state), onoff(cur_state));
306 /* XXX: the dsi pll is shared between MIPI DSI ports */
307 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
312 vlv_cck_get(dev_priv);
313 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
314 vlv_cck_put(dev_priv);
316 cur_state = val & DSI_PLL_VCO_EN;
317 I915_STATE_WARN(cur_state != state,
318 "DSI PLL state assertion failure (expected %s, current %s)\n",
319 onoff(state), onoff(cur_state));
322 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
323 enum pipe pipe, bool state)
327 if (HAS_DDI(dev_priv)) {
329 * DDI does not have a specific FDI_TX register.
331 * FDI is never fed from EDP transcoder
332 * so pipe->transcoder cast is fine here.
334 enum transcoder cpu_transcoder = (enum transcoder)pipe;
335 u32 val = intel_de_read(dev_priv,
336 TRANS_DDI_FUNC_CTL(cpu_transcoder));
337 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
339 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
340 cur_state = !!(val & FDI_TX_ENABLE);
342 I915_STATE_WARN(cur_state != state,
343 "FDI TX state assertion failure (expected %s, current %s)\n",
344 onoff(state), onoff(cur_state));
346 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
347 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
349 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
350 enum pipe pipe, bool state)
355 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
356 cur_state = !!(val & FDI_RX_ENABLE);
357 I915_STATE_WARN(cur_state != state,
358 "FDI RX state assertion failure (expected %s, current %s)\n",
359 onoff(state), onoff(cur_state));
361 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
362 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
364 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
369 /* ILK FDI PLL is always enabled */
370 if (IS_IRONLAKE(dev_priv))
373 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
374 if (HAS_DDI(dev_priv))
377 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
378 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
381 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
382 enum pipe pipe, bool state)
387 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
388 cur_state = !!(val & FDI_RX_PLL_ENABLE);
389 I915_STATE_WARN(cur_state != state,
390 "FDI RX PLL assertion failure (expected %s, current %s)\n",
391 onoff(state), onoff(cur_state));
394 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
398 enum pipe panel_pipe = INVALID_PIPE;
401 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
404 if (HAS_PCH_SPLIT(dev_priv)) {
407 pp_reg = PP_CONTROL(0);
408 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
411 case PANEL_PORT_SELECT_LVDS:
412 intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
414 case PANEL_PORT_SELECT_DPA:
415 g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
417 case PANEL_PORT_SELECT_DPC:
418 g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
420 case PANEL_PORT_SELECT_DPD:
421 g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
424 MISSING_CASE(port_sel);
427 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
428 /* presumably write lock depends on pipe, not port select */
429 pp_reg = PP_CONTROL(pipe);
434 pp_reg = PP_CONTROL(0);
435 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
437 drm_WARN_ON(&dev_priv->drm,
438 port_sel != PANEL_PORT_SELECT_LVDS);
439 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
442 val = intel_de_read(dev_priv, pp_reg);
443 if (!(val & PANEL_POWER_ON) ||
444 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
447 I915_STATE_WARN(panel_pipe == pipe && locked,
448 "panel assertion failure, pipe %c regs locked\n",
452 void assert_pipe(struct drm_i915_private *dev_priv,
453 enum transcoder cpu_transcoder, bool state)
456 enum intel_display_power_domain power_domain;
457 intel_wakeref_t wakeref;
459 /* we keep both pipes enabled on 830 */
460 if (IS_I830(dev_priv))
463 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
464 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
466 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
467 cur_state = !!(val & PIPECONF_ENABLE);
469 intel_display_power_put(dev_priv, power_domain, wakeref);
474 I915_STATE_WARN(cur_state != state,
475 "transcoder %s assertion failure (expected %s, current %s)\n",
476 transcoder_name(cpu_transcoder),
477 onoff(state), onoff(cur_state));
480 static void assert_plane(struct intel_plane *plane, bool state)
485 cur_state = plane->get_hw_state(plane, &pipe);
487 I915_STATE_WARN(cur_state != state,
488 "%s assertion failure (expected %s, current %s)\n",
489 plane->base.name, onoff(state), onoff(cur_state));
492 #define assert_plane_enabled(p) assert_plane(p, true)
493 #define assert_plane_disabled(p) assert_plane(p, false)
495 static void assert_planes_disabled(struct intel_crtc *crtc)
497 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
498 struct intel_plane *plane;
500 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
501 assert_plane_disabled(plane);
504 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
510 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
511 enabled = !!(val & TRANS_ENABLE);
512 I915_STATE_WARN(enabled,
513 "transcoder assertion failed, should be off on pipe %c but is still active\n",
517 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
518 enum pipe pipe, enum port port,
524 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
526 I915_STATE_WARN(state && port_pipe == pipe,
527 "PCH DP %c enabled on transcoder %c, should be disabled\n",
528 port_name(port), pipe_name(pipe));
530 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
531 "IBX PCH DP %c still using transcoder B\n",
535 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
536 enum pipe pipe, enum port port,
542 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
544 I915_STATE_WARN(state && port_pipe == pipe,
545 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
546 port_name(port), pipe_name(pipe));
548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
549 "IBX PCH HDMI %c still using transcoder B\n",
553 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
558 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
559 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
560 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
562 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
564 "PCH VGA enabled on transcoder %c, should be disabled\n",
567 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
569 "PCH LVDS enabled on transcoder %c, should be disabled\n",
572 /* PCH SDVOB multiplex with HDMIB */
573 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
574 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
575 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
578 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
579 struct intel_digital_port *dig_port,
580 unsigned int expected_mask)
585 switch (dig_port->base.port) {
587 port_mask = DPLL_PORTB_READY_MASK;
591 port_mask = DPLL_PORTC_READY_MASK;
596 port_mask = DPLL_PORTD_READY_MASK;
597 dpll_reg = DPIO_PHY_STATUS;
603 if (intel_de_wait_for_register(dev_priv, dpll_reg,
604 port_mask, expected_mask, 1000))
605 drm_WARN(&dev_priv->drm, 1,
606 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
607 dig_port->base.base.base.id, dig_port->base.base.name,
608 intel_de_read(dev_priv, dpll_reg) & port_mask,
612 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
614 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
615 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
616 enum pipe pipe = crtc->pipe;
618 u32 val, pipeconf_val;
620 /* Make sure PCH DPLL is enabled */
621 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
623 /* FDI must be feeding us bits for PCH ports */
624 assert_fdi_tx_enabled(dev_priv, pipe);
625 assert_fdi_rx_enabled(dev_priv, pipe);
627 if (HAS_PCH_CPT(dev_priv)) {
628 reg = TRANS_CHICKEN2(pipe);
629 val = intel_de_read(dev_priv, reg);
631 * Workaround: Set the timing override bit
632 * before enabling the pch transcoder.
634 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
635 /* Configure frame start delay to match the CPU */
636 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
637 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
638 intel_de_write(dev_priv, reg, val);
641 reg = PCH_TRANSCONF(pipe);
642 val = intel_de_read(dev_priv, reg);
643 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
645 if (HAS_PCH_IBX(dev_priv)) {
646 /* Configure frame start delay to match the CPU */
647 val &= ~TRANS_FRAME_START_DELAY_MASK;
648 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
651 * Make the BPC in transcoder be consistent with
652 * that in pipeconf reg. For HDMI we must use 8bpc
653 * here for both 8bpc and 12bpc.
655 val &= ~PIPECONF_BPC_MASK;
656 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
657 val |= PIPECONF_8BPC;
659 val |= pipeconf_val & PIPECONF_BPC_MASK;
662 val &= ~TRANS_INTERLACE_MASK;
663 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
664 if (HAS_PCH_IBX(dev_priv) &&
665 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
666 val |= TRANS_LEGACY_INTERLACED_ILK;
668 val |= TRANS_INTERLACED;
670 val |= TRANS_PROGRESSIVE;
673 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
674 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
675 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
679 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
680 enum transcoder cpu_transcoder)
682 u32 val, pipeconf_val;
684 /* FDI must be feeding us bits for PCH ports */
685 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
686 assert_fdi_rx_enabled(dev_priv, PIPE_A);
688 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
689 /* Workaround: set timing override bit. */
690 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
691 /* Configure frame start delay to match the CPU */
692 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
693 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
694 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
697 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
699 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
700 PIPECONF_INTERLACED_ILK)
701 val |= TRANS_INTERLACED;
703 val |= TRANS_PROGRESSIVE;
705 intel_de_write(dev_priv, LPT_TRANSCONF, val);
706 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
707 TRANS_STATE_ENABLE, 100))
708 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
711 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
717 /* FDI relies on the transcoder */
718 assert_fdi_tx_disabled(dev_priv, pipe);
719 assert_fdi_rx_disabled(dev_priv, pipe);
721 /* Ports must be off as well */
722 assert_pch_ports_disabled(dev_priv, pipe);
724 reg = PCH_TRANSCONF(pipe);
725 val = intel_de_read(dev_priv, reg);
726 val &= ~TRANS_ENABLE;
727 intel_de_write(dev_priv, reg, val);
728 /* wait for PCH transcoder off, transcoder state */
729 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
730 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
733 if (HAS_PCH_CPT(dev_priv)) {
734 /* Workaround: Clear the timing override chicken bit again. */
735 reg = TRANS_CHICKEN2(pipe);
736 val = intel_de_read(dev_priv, reg);
737 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
738 intel_de_write(dev_priv, reg, val);
742 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
746 val = intel_de_read(dev_priv, LPT_TRANSCONF);
747 val &= ~TRANS_ENABLE;
748 intel_de_write(dev_priv, LPT_TRANSCONF, val);
749 /* wait for PCH transcoder off, transcoder state */
750 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
751 TRANS_STATE_ENABLE, 50))
752 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
754 /* Workaround: clear timing override bit. */
755 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
756 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
757 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
760 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
762 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
764 if (HAS_PCH_LPT(dev_priv))
770 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
772 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
774 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
775 enum pipe pipe = crtc->pipe;
779 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
781 assert_planes_disabled(crtc);
784 * A pipe without a PLL won't actually be able to drive bits from
785 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
788 if (HAS_GMCH(dev_priv)) {
789 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
790 assert_dsi_pll_enabled(dev_priv);
792 assert_pll_enabled(dev_priv, pipe);
794 if (new_crtc_state->has_pch_encoder) {
795 /* if driving the PCH, we need FDI enabled */
796 assert_fdi_rx_pll_enabled(dev_priv,
797 intel_crtc_pch_transcoder(crtc));
798 assert_fdi_tx_pll_enabled(dev_priv,
799 (enum pipe) cpu_transcoder);
801 /* FIXME: assert CPU port conditions for SNB+ */
804 /* Wa_22012358565:adl-p */
805 if (DISPLAY_VER(dev_priv) == 13)
806 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
807 0, PIPE_ARB_USE_PROG_SLOTS);
809 reg = PIPECONF(cpu_transcoder);
810 val = intel_de_read(dev_priv, reg);
811 if (val & PIPECONF_ENABLE) {
812 /* we keep both pipes enabled on 830 */
813 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
817 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
818 intel_de_posting_read(dev_priv, reg);
821 * Until the pipe starts PIPEDSL reads will return a stale value,
822 * which causes an apparent vblank timestamp jump when PIPEDSL
823 * resets to its proper value. That also messes up the frame count
824 * when it's derived from the timestamps. So let's wait for the
825 * pipe to start properly before we call drm_crtc_vblank_on()
827 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
828 intel_wait_for_pipe_scanline_moving(crtc);
831 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
833 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
834 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
835 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
836 enum pipe pipe = crtc->pipe;
840 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
843 * Make sure planes won't keep trying to pump pixels to us,
844 * or we might hang the display.
846 assert_planes_disabled(crtc);
848 reg = PIPECONF(cpu_transcoder);
849 val = intel_de_read(dev_priv, reg);
850 if ((val & PIPECONF_ENABLE) == 0)
854 * Double wide has implications for planes
855 * so best keep it disabled when not needed.
857 if (old_crtc_state->double_wide)
858 val &= ~PIPECONF_DOUBLE_WIDE;
860 /* Don't disable pipe or pipe PLLs if needed */
861 if (!IS_I830(dev_priv))
862 val &= ~PIPECONF_ENABLE;
864 if (DISPLAY_VER(dev_priv) >= 12)
865 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
866 FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
868 intel_de_write(dev_priv, reg, val);
869 if ((val & PIPECONF_ENABLE) == 0)
870 intel_wait_for_pipe_off(old_crtc_state);
874 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
877 return info->is_yuv &&
878 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
882 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
884 struct drm_i915_private *dev_priv = to_i915(fb->dev);
885 unsigned int cpp = fb->format->cpp[color_plane];
887 switch (fb->modifier) {
888 case DRM_FORMAT_MOD_LINEAR:
889 return intel_tile_size(dev_priv);
890 case I915_FORMAT_MOD_X_TILED:
891 if (DISPLAY_VER(dev_priv) == 2)
895 case I915_FORMAT_MOD_Y_TILED_CCS:
896 if (is_ccs_plane(fb, color_plane))
899 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
900 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
901 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
902 if (is_ccs_plane(fb, color_plane))
905 case I915_FORMAT_MOD_Y_TILED:
906 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
910 case I915_FORMAT_MOD_Yf_TILED_CCS:
911 if (is_ccs_plane(fb, color_plane))
914 case I915_FORMAT_MOD_Yf_TILED:
930 MISSING_CASE(fb->modifier);
936 intel_fb_align_height(const struct drm_framebuffer *fb,
937 int color_plane, unsigned int height)
939 unsigned int tile_height = intel_tile_height(fb, color_plane);
941 return ALIGN(height, tile_height);
944 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
946 unsigned int size = 0;
949 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
950 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
955 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
957 unsigned int size = 0;
960 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
961 size += rem_info->plane[i].dst_stride * rem_info->plane[i].height;
966 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
968 if (DISPLAY_VER(dev_priv) >= 9)
970 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
971 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
973 else if (DISPLAY_VER(dev_priv) >= 4)
979 static bool has_async_flips(struct drm_i915_private *i915)
981 return DISPLAY_VER(i915) >= 5;
984 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
987 struct drm_i915_private *dev_priv = to_i915(fb->dev);
989 if (intel_fb_uses_dpt(fb))
992 /* AUX_DIST needs only 4K alignment */
993 if (is_ccs_plane(fb, color_plane))
996 if (is_semiplanar_uv_plane(fb, color_plane)) {
998 * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
999 * alignment for linear UV planes on all platforms.
1001 if (DISPLAY_VER(dev_priv) >= 12) {
1002 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
1003 return intel_linear_alignment(dev_priv);
1005 return intel_tile_row_size(fb, color_plane);
1011 drm_WARN_ON(&dev_priv->drm, color_plane != 0);
1013 switch (fb->modifier) {
1014 case DRM_FORMAT_MOD_LINEAR:
1015 return intel_linear_alignment(dev_priv);
1016 case I915_FORMAT_MOD_X_TILED:
1017 if (has_async_flips(dev_priv))
1020 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1021 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1022 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1024 case I915_FORMAT_MOD_Y_TILED_CCS:
1025 case I915_FORMAT_MOD_Yf_TILED_CCS:
1026 case I915_FORMAT_MOD_Y_TILED:
1027 case I915_FORMAT_MOD_Yf_TILED:
1028 return 1 * 1024 * 1024;
1030 MISSING_CASE(fb->modifier);
1035 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
1037 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1038 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1040 return DISPLAY_VER(dev_priv) < 4 ||
1042 plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
1045 static struct i915_vma *
1046 intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
1047 const struct i915_ggtt_view *view,
1049 unsigned long *out_flags,
1050 struct i915_address_space *vm)
1052 struct drm_device *dev = fb->dev;
1053 struct drm_i915_private *dev_priv = to_i915(dev);
1054 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1055 struct i915_vma *vma;
1059 if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
1060 return ERR_PTR(-EINVAL);
1062 alignment = 4096 * 512;
1064 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1066 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1072 vma = i915_vma_instance(obj, vm, view);
1076 if (i915_vma_misplaced(vma, 0, alignment, 0)) {
1077 ret = i915_vma_unbind(vma);
1084 ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
1090 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
1092 i915_gem_object_flush_if_display(obj);
1096 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1102 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1104 const struct i915_ggtt_view *view,
1106 unsigned long *out_flags)
1108 struct drm_device *dev = fb->dev;
1109 struct drm_i915_private *dev_priv = to_i915(dev);
1110 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1111 intel_wakeref_t wakeref;
1112 struct i915_gem_ww_ctx ww;
1113 struct i915_vma *vma;
1114 unsigned int pinctl;
1118 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
1119 return ERR_PTR(-EINVAL);
1122 alignment = intel_cursor_alignment(dev_priv);
1124 alignment = intel_surf_alignment(fb, 0);
1125 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
1126 return ERR_PTR(-EINVAL);
1128 /* Note that the w/a also requires 64 PTE of padding following the
1129 * bo. We currently fill all unused PTE with the shadow page and so
1130 * we should always have valid PTE following the scanout preventing
1133 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
1134 alignment = 256 * 1024;
1137 * Global gtt pte registers are special registers which actually forward
1138 * writes to a chunk of system memory. Which means that there is no risk
1139 * that the register values disappear as soon as we call
1140 * intel_runtime_pm_put(), so it is correct to wrap only the
1141 * pin/unpin/fence and not more.
1143 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1145 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
1148 * Valleyview is definitely limited to scanning out the first
1149 * 512MiB. Lets presume this behaviour was inherited from the
1150 * g4x display engine and that all earlier gen are similarly
1151 * limited. Testing suggests that it is a little more
1152 * complicated than this. For example, Cherryview appears quite
1153 * happy to scanout from anywhere within its global aperture.
1156 if (HAS_GMCH(dev_priv))
1157 pinctl |= PIN_MAPPABLE;
1159 i915_gem_ww_ctx_init(&ww, true);
1161 ret = i915_gem_object_lock(obj, &ww);
1162 if (!ret && phys_cursor)
1163 ret = i915_gem_object_attach_phys(obj, alignment);
1164 else if (!ret && HAS_LMEM(dev_priv))
1165 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM);
1166 /* TODO: Do we need to sync when migration becomes async? */
1168 ret = i915_gem_object_pin_pages(obj);
1173 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
1181 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
1183 * Install a fence for tiled scan-out. Pre-i965 always needs a
1184 * fence, whereas 965+ only requires a fence if using
1185 * framebuffer compression. For simplicity, we always, when
1186 * possible, install a fence as the cost is not that onerous.
1188 * If we fail to fence the tiled scanout, then either the
1189 * modeset will reject the change (which is highly unlikely as
1190 * the affected systems, all but one, do not have unmappable
1191 * space) or we will not be able to enable full powersaving
1192 * techniques (also likely not to apply due to various limits
1193 * FBC and the like impose on the size of the buffer, which
1194 * presumably we violated anyway with this unmappable buffer).
1195 * Anyway, it is presumably better to stumble onwards with
1196 * something and try to run the system in a "less than optimal"
1197 * mode that matches the user configuration.
1199 ret = i915_vma_pin_fence(vma);
1200 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) {
1201 i915_vma_unpin(vma);
1207 *out_flags |= PLANE_HAS_FENCE;
1213 i915_gem_object_unpin_pages(obj);
1215 if (ret == -EDEADLK) {
1216 ret = i915_gem_ww_ctx_backoff(&ww);
1220 i915_gem_ww_ctx_fini(&ww);
1224 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
1225 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1229 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
1231 if (flags & PLANE_HAS_FENCE)
1232 i915_vma_unpin_fence(vma);
1233 i915_vma_unpin(vma);
1238 * Convert the x/y offsets into a linear offset.
1239 * Only valid with 0/180 degree rotation, which is fine since linear
1240 * offset is only used with linear buffers on pre-hsw and tiled buffers
1241 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
1243 u32 intel_fb_xy_to_linear(int x, int y,
1244 const struct intel_plane_state *state,
1247 const struct drm_framebuffer *fb = state->hw.fb;
1248 unsigned int cpp = fb->format->cpp[color_plane];
1249 unsigned int pitch = state->view.color_plane[color_plane].stride;
1251 return y * pitch + x * cpp;
1255 * Add the x/y offsets derived from fb->offsets[] to the user
1256 * specified plane src x/y offsets. The resulting x/y offsets
1257 * specify the start of scanout from the beginning of the gtt mapping.
1259 void intel_add_fb_offsets(int *x, int *y,
1260 const struct intel_plane_state *state,
1264 *x += state->view.color_plane[color_plane].x;
1265 *y += state->view.color_plane[color_plane].y;
1268 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
1270 switch (fb_modifier) {
1271 case I915_FORMAT_MOD_X_TILED:
1272 return I915_TILING_X;
1273 case I915_FORMAT_MOD_Y_TILED:
1274 case I915_FORMAT_MOD_Y_TILED_CCS:
1275 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1276 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1277 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1278 return I915_TILING_Y;
1280 return I915_TILING_NONE;
1285 * From the Sky Lake PRM:
1286 * "The Color Control Surface (CCS) contains the compression status of
1287 * the cache-line pairs. The compression state of the cache-line pair
1288 * is specified by 2 bits in the CCS. Each CCS cache-line represents
1289 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
1290 * cache-line-pairs. CCS is always Y tiled."
1292 * Since cache line pairs refers to horizontally adjacent cache lines,
1293 * each cache line in the CCS corresponds to an area of 32x16 cache
1294 * lines on the main surface. Since each pixel is 4 bytes, this gives
1295 * us a ratio of one byte in the CCS for each 8x16 pixels in the
1298 static const struct drm_format_info skl_ccs_formats[] = {
1299 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1300 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1301 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1302 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
1303 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1304 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1305 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1306 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
1310 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
1311 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
1312 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
1313 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
1316 static const struct drm_format_info gen12_ccs_formats[] = {
1317 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
1318 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1319 .hsub = 1, .vsub = 1, },
1320 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
1321 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1322 .hsub = 1, .vsub = 1, },
1323 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
1324 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1325 .hsub = 1, .vsub = 1, .has_alpha = true },
1326 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
1327 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1328 .hsub = 1, .vsub = 1, .has_alpha = true },
1329 { .format = DRM_FORMAT_YUYV, .num_planes = 2,
1330 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1331 .hsub = 2, .vsub = 1, .is_yuv = true },
1332 { .format = DRM_FORMAT_YVYU, .num_planes = 2,
1333 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1334 .hsub = 2, .vsub = 1, .is_yuv = true },
1335 { .format = DRM_FORMAT_UYVY, .num_planes = 2,
1336 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1337 .hsub = 2, .vsub = 1, .is_yuv = true },
1338 { .format = DRM_FORMAT_VYUY, .num_planes = 2,
1339 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1340 .hsub = 2, .vsub = 1, .is_yuv = true },
1341 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
1342 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
1343 .hsub = 1, .vsub = 1, .is_yuv = true },
1344 { .format = DRM_FORMAT_NV12, .num_planes = 4,
1345 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
1346 .hsub = 2, .vsub = 2, .is_yuv = true },
1347 { .format = DRM_FORMAT_P010, .num_planes = 4,
1348 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1349 .hsub = 2, .vsub = 2, .is_yuv = true },
1350 { .format = DRM_FORMAT_P012, .num_planes = 4,
1351 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1352 .hsub = 2, .vsub = 2, .is_yuv = true },
1353 { .format = DRM_FORMAT_P016, .num_planes = 4,
1354 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
1355 .hsub = 2, .vsub = 2, .is_yuv = true },
1359 * Same as gen12_ccs_formats[] above, but with additional surface used
1360 * to pass Clear Color information in plane 2 with 64 bits of data.
1362 static const struct drm_format_info gen12_ccs_cc_formats[] = {
1363 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
1364 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1365 .hsub = 1, .vsub = 1, },
1366 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
1367 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1368 .hsub = 1, .vsub = 1, },
1369 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
1370 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1371 .hsub = 1, .vsub = 1, .has_alpha = true },
1372 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
1373 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
1374 .hsub = 1, .vsub = 1, .has_alpha = true },
1377 static const struct drm_format_info *
1378 lookup_format_info(const struct drm_format_info formats[],
1379 int num_formats, u32 format)
1383 for (i = 0; i < num_formats; i++) {
1384 if (formats[i].format == format)
1391 static const struct drm_format_info *
1392 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
1394 switch (cmd->modifier[0]) {
1395 case I915_FORMAT_MOD_Y_TILED_CCS:
1396 case I915_FORMAT_MOD_Yf_TILED_CCS:
1397 return lookup_format_info(skl_ccs_formats,
1398 ARRAY_SIZE(skl_ccs_formats),
1400 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1401 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1402 return lookup_format_info(gen12_ccs_formats,
1403 ARRAY_SIZE(gen12_ccs_formats),
1405 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1406 return lookup_format_info(gen12_ccs_cc_formats,
1407 ARRAY_SIZE(gen12_ccs_cc_formats),
1414 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
1416 return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
1420 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
1421 u32 pixel_format, u64 modifier)
1423 struct intel_crtc *crtc;
1424 struct intel_plane *plane;
1426 if (!HAS_DISPLAY(dev_priv))
1430 * We assume the primary plane for pipe A has
1431 * the highest stride limits of them all,
1432 * if in case pipe A is disabled, use the first pipe from pipe_mask.
1434 crtc = intel_get_first_crtc(dev_priv);
1438 plane = to_intel_plane(crtc->base.primary);
1440 return plane->max_stride(plane, pixel_format, modifier,
1445 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1446 u32 pixel_format, u64 modifier)
1449 * Arbitrary limit for gen4+ chosen to match the
1450 * render engine max stride.
1452 * The new CCS hash mode makes remapping impossible
1454 if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
1455 intel_modifier_uses_dpt(dev_priv, modifier))
1456 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1457 else if (DISPLAY_VER(dev_priv) >= 7)
1464 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1466 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1469 if (is_surface_linear(fb, color_plane)) {
1470 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1475 * To make remapping with linear generally feasible
1476 * we need the stride to be page aligned.
1478 if (fb->pitches[color_plane] > max_stride &&
1479 !is_ccs_modifier(fb->modifier))
1480 return intel_tile_size(dev_priv);
1485 tile_width = intel_tile_width_bytes(fb, color_plane);
1486 if (is_ccs_modifier(fb->modifier)) {
1488 * Display WA #0531: skl,bxt,kbl,glk
1490 * Render decompression and plane width > 3840
1491 * combined with horizontal panning requires the
1492 * plane stride to be a multiple of 4. We'll just
1493 * require the entire fb to accommodate that to avoid
1494 * potential runtime errors at plane configuration time.
1496 if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
1497 color_plane == 0 && fb->width > 3840)
1500 * The main surface pitch must be padded to a multiple of four
1503 else if (DISPLAY_VER(dev_priv) >= 12)
1509 static struct i915_vma *
1510 initial_plane_vma(struct drm_i915_private *i915,
1511 struct intel_initial_plane_config *plane_config)
1513 struct drm_i915_gem_object *obj;
1514 struct i915_vma *vma;
1517 if (plane_config->size == 0)
1520 base = round_down(plane_config->base,
1521 I915_GTT_MIN_ALIGNMENT);
1522 size = round_up(plane_config->base + plane_config->size,
1523 I915_GTT_MIN_ALIGNMENT);
1527 * If the FB is too big, just don't use it since fbdev is not very
1528 * important and we should probably use that space with FBC or other
1531 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
1532 size * 2 > i915->stolen_usable_size)
1535 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
1540 * Mark it WT ahead of time to avoid changing the
1541 * cache_level during fbdev initialization. The
1542 * unbind there would get stuck waiting for rcu.
1544 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
1545 I915_CACHE_WT : I915_CACHE_NONE);
1547 switch (plane_config->tiling) {
1548 case I915_TILING_NONE:
1552 obj->tiling_and_stride =
1553 plane_config->fb->base.pitches[0] |
1554 plane_config->tiling;
1557 MISSING_CASE(plane_config->tiling);
1561 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1565 if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
1568 if (i915_gem_object_is_tiled(obj) &&
1569 !i915_vma_is_map_and_fenceable(vma))
1575 i915_gem_object_put(obj);
1580 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
1581 struct intel_initial_plane_config *plane_config)
1583 struct drm_device *dev = crtc->base.dev;
1584 struct drm_i915_private *dev_priv = to_i915(dev);
1585 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
1586 struct drm_framebuffer *fb = &plane_config->fb->base;
1587 struct i915_vma *vma;
1589 switch (fb->modifier) {
1590 case DRM_FORMAT_MOD_LINEAR:
1591 case I915_FORMAT_MOD_X_TILED:
1592 case I915_FORMAT_MOD_Y_TILED:
1595 drm_dbg(&dev_priv->drm,
1596 "Unsupported modifier for initial FB: 0x%llx\n",
1601 vma = initial_plane_vma(dev_priv, plane_config);
1605 mode_cmd.pixel_format = fb->format->format;
1606 mode_cmd.width = fb->width;
1607 mode_cmd.height = fb->height;
1608 mode_cmd.pitches[0] = fb->pitches[0];
1609 mode_cmd.modifier[0] = fb->modifier;
1610 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
1612 if (intel_framebuffer_init(to_intel_framebuffer(fb),
1613 vma->obj, &mode_cmd)) {
1614 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
1618 plane_config->vma = vma;
1627 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
1628 struct intel_plane_state *plane_state,
1631 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1633 plane_state->uapi.visible = visible;
1636 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
1638 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
1641 static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
1643 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1644 struct drm_plane *plane;
1647 * Active_planes aliases if multiple "primary" or cursor planes
1648 * have been used on the same (or wrong) pipe. plane_mask uses
1649 * unique ids, hence we can use that to reconstruct active_planes.
1651 crtc_state->enabled_planes = 0;
1652 crtc_state->active_planes = 0;
1654 drm_for_each_plane_mask(plane, &dev_priv->drm,
1655 crtc_state->uapi.plane_mask) {
1656 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
1657 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
1661 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
1662 struct intel_plane *plane)
1664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1665 struct intel_crtc_state *crtc_state =
1666 to_intel_crtc_state(crtc->base.state);
1667 struct intel_plane_state *plane_state =
1668 to_intel_plane_state(plane->base.state);
1670 drm_dbg_kms(&dev_priv->drm,
1671 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
1672 plane->base.base.id, plane->base.name,
1673 crtc->base.base.id, crtc->base.name);
1675 intel_set_plane_visible(crtc_state, plane_state, false);
1676 fixup_plane_bitmasks(crtc_state);
1677 crtc_state->data_rate[plane->id] = 0;
1678 crtc_state->min_cdclk[plane->id] = 0;
1680 if (plane->id == PLANE_PRIMARY)
1681 hsw_disable_ips(crtc_state);
1684 * Vblank time updates from the shadow to live plane control register
1685 * are blocked if the memory self-refresh mode is active at that
1686 * moment. So to make sure the plane gets truly disabled, disable
1687 * first the self-refresh mode. The self-refresh enable bit in turn
1688 * will be checked/applied by the HW only at the next frame start
1689 * event which is after the vblank start event, so we need to have a
1690 * wait-for-vblank between disabling the plane and the pipe.
1692 if (HAS_GMCH(dev_priv) &&
1693 intel_set_memory_cxsr(dev_priv, false))
1694 intel_wait_for_vblank(dev_priv, crtc->pipe);
1697 * Gen2 reports pipe underruns whenever all planes are disabled.
1698 * So disable underrun reporting before all the planes get disabled.
1700 if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
1701 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
1703 intel_disable_plane(plane, crtc_state);
1704 intel_wait_for_vblank(dev_priv, crtc->pipe);
1708 intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
1709 const struct intel_initial_plane_config *plane_config,
1710 struct drm_framebuffer **fb,
1711 struct i915_vma **vma)
1713 struct intel_crtc *crtc;
1715 for_each_intel_crtc(&i915->drm, crtc) {
1716 struct intel_crtc_state *crtc_state =
1717 to_intel_crtc_state(crtc->base.state);
1718 struct intel_plane *plane =
1719 to_intel_plane(crtc->base.primary);
1720 struct intel_plane_state *plane_state =
1721 to_intel_plane_state(plane->base.state);
1723 if (!crtc_state->uapi.active)
1726 if (!plane_state->ggtt_vma)
1729 if (intel_plane_ggtt_offset(plane_state) == plane_config->base) {
1730 *fb = plane_state->hw.fb;
1731 *vma = plane_state->ggtt_vma;
1740 intel_find_initial_plane_obj(struct intel_crtc *crtc,
1741 struct intel_initial_plane_config *plane_config)
1743 struct drm_device *dev = crtc->base.dev;
1744 struct drm_i915_private *dev_priv = to_i915(dev);
1745 struct intel_crtc_state *crtc_state =
1746 to_intel_crtc_state(crtc->base.state);
1747 struct intel_plane *plane =
1748 to_intel_plane(crtc->base.primary);
1749 struct intel_plane_state *plane_state =
1750 to_intel_plane_state(plane->base.state);
1751 struct drm_framebuffer *fb;
1752 struct i915_vma *vma;
1756 * Disable planes if get_initial_plane_config() failed.
1757 * Make sure things work if the surface base is not page aligned.
1759 if (!plane_config->fb)
1762 if (intel_alloc_initial_plane_obj(crtc, plane_config)) {
1763 fb = &plane_config->fb->base;
1764 vma = plane_config->vma;
1769 * Failed to alloc the obj, check to see if we should share
1770 * an fb with another CRTC instead
1772 if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma))
1776 * We've failed to reconstruct the BIOS FB. Current display state
1777 * indicates that the primary plane is visible, but has a NULL FB,
1778 * which will lead to problems later if we don't fix it up. The
1779 * simplest solution is to just disable the primary plane now and
1780 * pretend the BIOS never had it enabled.
1782 intel_plane_disable_noatomic(crtc, plane);
1783 if (crtc_state->bigjoiner) {
1784 struct intel_crtc *slave =
1785 crtc_state->bigjoiner_linked_crtc;
1786 intel_plane_disable_noatomic(slave, to_intel_plane(slave->base.primary));
1792 plane_state->uapi.rotation = plane_config->rotation;
1793 intel_fb_fill_view(to_intel_framebuffer(fb),
1794 plane_state->uapi.rotation, &plane_state->view);
1796 __i915_vma_pin(vma);
1797 plane_state->ggtt_vma = i915_vma_get(vma);
1798 if (intel_plane_uses_fence(plane_state) &&
1799 i915_vma_pin_fence(vma) == 0 && vma->fence)
1800 plane_state->flags |= PLANE_HAS_FENCE;
1802 plane_state->uapi.src_x = 0;
1803 plane_state->uapi.src_y = 0;
1804 plane_state->uapi.src_w = fb->width << 16;
1805 plane_state->uapi.src_h = fb->height << 16;
1807 plane_state->uapi.crtc_x = 0;
1808 plane_state->uapi.crtc_y = 0;
1809 plane_state->uapi.crtc_w = fb->width;
1810 plane_state->uapi.crtc_h = fb->height;
1812 if (plane_config->tiling)
1813 dev_priv->preserve_bios_swizzle = true;
1815 plane_state->uapi.fb = fb;
1816 drm_framebuffer_get(fb);
1818 plane_state->uapi.crtc = &crtc->base;
1819 intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc);
1821 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
1823 atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits);
1827 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
1831 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
1832 plane_state->view.color_plane[0].offset, 0);
1838 __intel_display_resume(struct drm_device *dev,
1839 struct drm_atomic_state *state,
1840 struct drm_modeset_acquire_ctx *ctx)
1842 struct drm_crtc_state *crtc_state;
1843 struct drm_crtc *crtc;
1846 intel_modeset_setup_hw_state(dev, ctx);
1847 intel_vga_redisable(to_i915(dev));
1853 * We've duplicated the state, pointers to the old state are invalid.
1855 * Don't attempt to use the old state until we commit the duplicated state.
1857 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
1859 * Force recalculation even if we restore
1860 * current state. With fast modeset this may not result
1861 * in a modeset when the state is compatible.
1863 crtc_state->mode_changed = true;
1866 /* ignore any reset values/BIOS leftovers in the WM registers */
1867 if (!HAS_GMCH(to_i915(dev)))
1868 to_intel_atomic_state(state)->skip_intermediate_wm = true;
1870 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
1872 drm_WARN_ON(dev, ret == -EDEADLK);
1876 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
1878 return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
1879 intel_has_gpu_reset(&dev_priv->gt));
1882 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
1884 struct drm_device *dev = &dev_priv->drm;
1885 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
1886 struct drm_atomic_state *state;
1889 if (!HAS_DISPLAY(dev_priv))
1892 /* reset doesn't touch the display */
1893 if (!dev_priv->params.force_reset_modeset_test &&
1894 !gpu_reset_clobbers_display(dev_priv))
1897 /* We have a modeset vs reset deadlock, defensively unbreak it. */
1898 set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
1899 smp_mb__after_atomic();
1900 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
1902 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
1903 drm_dbg_kms(&dev_priv->drm,
1904 "Modeset potentially stuck, unbreaking through wedging\n");
1905 intel_gt_set_wedged(&dev_priv->gt);
1909 * Need mode_config.mutex so that we don't
1910 * trample ongoing ->detect() and whatnot.
1912 mutex_lock(&dev->mode_config.mutex);
1913 drm_modeset_acquire_init(ctx, 0);
1915 ret = drm_modeset_lock_all_ctx(dev, ctx);
1916 if (ret != -EDEADLK)
1919 drm_modeset_backoff(ctx);
1922 * Disabling the crtcs gracefully seems nicer. Also the
1923 * g33 docs say we should at least disable all the planes.
1925 state = drm_atomic_helper_duplicate_state(dev, ctx);
1926 if (IS_ERR(state)) {
1927 ret = PTR_ERR(state);
1928 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
1933 ret = drm_atomic_helper_disable_all(dev, ctx);
1935 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
1937 drm_atomic_state_put(state);
1941 dev_priv->modeset_restore_state = state;
1942 state->acquire_ctx = ctx;
1945 void intel_display_finish_reset(struct drm_i915_private *dev_priv)
1947 struct drm_device *dev = &dev_priv->drm;
1948 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
1949 struct drm_atomic_state *state;
1952 if (!HAS_DISPLAY(dev_priv))
1955 /* reset doesn't touch the display */
1956 if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
1959 state = fetch_and_zero(&dev_priv->modeset_restore_state);
1963 /* reset doesn't touch the display */
1964 if (!gpu_reset_clobbers_display(dev_priv)) {
1965 /* for testing only restore the display */
1966 ret = __intel_display_resume(dev, state, ctx);
1968 drm_err(&dev_priv->drm,
1969 "Restoring old state failed with %i\n", ret);
1972 * The display has been reset as well,
1973 * so need a full re-initialization.
1975 intel_pps_unlock_regs_wa(dev_priv);
1976 intel_modeset_init_hw(dev_priv);
1977 intel_init_clock_gating(dev_priv);
1978 intel_hpd_init(dev_priv);
1980 ret = __intel_display_resume(dev, state, ctx);
1982 drm_err(&dev_priv->drm,
1983 "Restoring old state failed with %i\n", ret);
1985 intel_hpd_poll_disable(dev_priv);
1988 drm_atomic_state_put(state);
1990 drm_modeset_drop_locks(ctx);
1991 drm_modeset_acquire_fini(ctx);
1992 mutex_unlock(&dev->mode_config.mutex);
1994 clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
1997 static bool underrun_recovery_supported(const struct intel_crtc_state *crtc_state)
1999 if (crtc_state->pch_pfit.enabled &&
2000 (crtc_state->pipe_src_w > drm_rect_width(&crtc_state->pch_pfit.dst) ||
2001 crtc_state->pipe_src_h > drm_rect_height(&crtc_state->pch_pfit.dst) ||
2002 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420))
2005 if (crtc_state->dsc.compression_enable)
2008 if (crtc_state->has_psr2)
2011 if (crtc_state->splitter.enable)
2017 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
2019 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2020 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2021 enum pipe pipe = crtc->pipe;
2024 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
2027 * Display WA #1153: icl
2028 * enable hardware to bypass the alpha math
2029 * and rounding for per-pixel values 00 and 0xff
2031 tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
2033 * Display WA # 1605353570: icl
2034 * Set the pixel rounding bit to 1 for allowing
2035 * passthrough of Frame buffer pixels unmodified
2038 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
2040 if (IS_DG2(dev_priv)) {
2042 * Underrun recovery must always be disabled on DG2. However
2043 * the chicken bit meaning is inverted compared to other
2046 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
2047 } else if (DISPLAY_VER(dev_priv) >= 13) {
2048 if (underrun_recovery_supported(crtc_state))
2049 tmp &= ~UNDERRUN_RECOVERY_DISABLE_ADLP;
2051 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
2054 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
2057 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
2059 struct drm_crtc *crtc;
2062 drm_for_each_crtc(crtc, &dev_priv->drm) {
2063 struct drm_crtc_commit *commit;
2064 spin_lock(&crtc->commit_lock);
2065 commit = list_first_entry_or_null(&crtc->commit_list,
2066 struct drm_crtc_commit, commit_entry);
2067 cleanup_done = commit ?
2068 try_wait_for_completion(&commit->cleanup_done) : true;
2069 spin_unlock(&crtc->commit_lock);
2074 drm_crtc_wait_one_vblank(crtc);
2082 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
2086 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
2088 mutex_lock(&dev_priv->sb_lock);
2090 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2091 temp |= SBI_SSCCTL_DISABLE;
2092 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2094 mutex_unlock(&dev_priv->sb_lock);
2097 /* Program iCLKIP clock to the desired frequency */
2098 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
2100 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2101 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2102 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
2103 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2106 lpt_disable_iclkip(dev_priv);
2108 /* The iCLK virtual clock root frequency is in MHz,
2109 * but the adjusted_mode->crtc_clock in in KHz. To get the
2110 * divisors, it is necessary to divide one by another, so we
2111 * convert the virtual clock precision to KHz here for higher
2114 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
2115 u32 iclk_virtual_root_freq = 172800 * 1000;
2116 u32 iclk_pi_range = 64;
2117 u32 desired_divisor;
2119 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2121 divsel = (desired_divisor / iclk_pi_range) - 2;
2122 phaseinc = desired_divisor % iclk_pi_range;
2125 * Near 20MHz is a corner case which is
2126 * out of range for the 7-bit divisor
2132 /* This should not happen with any sane values */
2133 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2134 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2135 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
2136 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2138 drm_dbg_kms(&dev_priv->drm,
2139 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2140 clock, auxdiv, divsel, phasedir, phaseinc);
2142 mutex_lock(&dev_priv->sb_lock);
2144 /* Program SSCDIVINTPHASE6 */
2145 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2146 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2147 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2148 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2149 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2150 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2151 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2152 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2154 /* Program SSCAUXDIV */
2155 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2156 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2157 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2158 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2160 /* Enable modulator and associated divider */
2161 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2162 temp &= ~SBI_SSCCTL_DISABLE;
2163 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2165 mutex_unlock(&dev_priv->sb_lock);
2167 /* Wait for initialization time */
2170 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2173 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
2175 u32 divsel, phaseinc, auxdiv;
2176 u32 iclk_virtual_root_freq = 172800 * 1000;
2177 u32 iclk_pi_range = 64;
2178 u32 desired_divisor;
2181 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
2184 mutex_lock(&dev_priv->sb_lock);
2186 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2187 if (temp & SBI_SSCCTL_DISABLE) {
2188 mutex_unlock(&dev_priv->sb_lock);
2192 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2193 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
2194 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
2195 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
2196 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
2198 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2199 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
2200 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
2202 mutex_unlock(&dev_priv->sb_lock);
2204 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
2206 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
2207 desired_divisor << auxdiv);
2210 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
2211 enum pipe pch_transcoder)
2213 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2214 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2215 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2217 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
2218 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
2219 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
2220 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
2221 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
2222 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
2224 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
2225 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2226 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
2227 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
2228 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
2229 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
2230 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2231 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
2234 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
2238 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
2239 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
2242 drm_WARN_ON(&dev_priv->drm,
2243 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
2245 drm_WARN_ON(&dev_priv->drm,
2246 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
2249 temp &= ~FDI_BC_BIFURCATION_SELECT;
2251 temp |= FDI_BC_BIFURCATION_SELECT;
2253 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
2254 enable ? "en" : "dis");
2255 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
2256 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
2259 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
2261 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2264 switch (crtc->pipe) {
2268 if (crtc_state->fdi_lanes > 2)
2269 cpt_set_fdi_bc_bifurcation(dev_priv, false);
2271 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2275 cpt_set_fdi_bc_bifurcation(dev_priv, true);
2284 * Finds the encoder associated with the given CRTC. This can only be
2285 * used when we know that the CRTC isn't feeding multiple encoders!
2287 struct intel_encoder *
2288 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
2289 const struct intel_crtc_state *crtc_state)
2291 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2292 const struct drm_connector_state *connector_state;
2293 const struct drm_connector *connector;
2294 struct intel_encoder *encoder = NULL;
2295 int num_encoders = 0;
2298 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
2299 if (connector_state->crtc != &crtc->base)
2302 encoder = to_intel_encoder(connector_state->best_encoder);
2306 drm_WARN(encoder->base.dev, num_encoders != 1,
2307 "%d encoders for pipe %c\n",
2308 num_encoders, pipe_name(crtc->pipe));
2314 * Enable PCH resources required for PCH ports:
2316 * - FDI training & RX/TX
2317 * - update transcoder timings
2318 * - DP transcoding bits
2321 static void ilk_pch_enable(const struct intel_atomic_state *state,
2322 const struct intel_crtc_state *crtc_state)
2324 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2325 struct drm_device *dev = crtc->base.dev;
2326 struct drm_i915_private *dev_priv = to_i915(dev);
2327 enum pipe pipe = crtc->pipe;
2330 assert_pch_transcoder_disabled(dev_priv, pipe);
2332 if (IS_IVYBRIDGE(dev_priv))
2333 ivb_update_fdi_bc_bifurcation(crtc_state);
2335 /* Write the TU size bits before fdi link training, so that error
2336 * detection works. */
2337 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
2338 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2340 /* For PCH output, training FDI link */
2341 dev_priv->display.fdi_link_train(crtc, crtc_state);
2343 /* We need to program the right clock selection before writing the pixel
2344 * mutliplier into the DPLL. */
2345 if (HAS_PCH_CPT(dev_priv)) {
2348 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
2349 temp |= TRANS_DPLL_ENABLE(pipe);
2350 sel = TRANS_DPLLB_SEL(pipe);
2351 if (crtc_state->shared_dpll ==
2352 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
2356 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
2359 /* XXX: pch pll's can be enabled any time before we enable the PCH
2360 * transcoder, and we actually should do this to not upset any PCH
2361 * transcoder that already use the clock when we share it.
2363 * Note that enable_shared_dpll tries to do the right thing, but
2364 * get_shared_dpll unconditionally resets the pll - we need that to have
2365 * the right LVDS enable sequence. */
2366 intel_enable_shared_dpll(crtc_state);
2368 /* set transcoder timing, panel must allow it */
2369 assert_panel_unlocked(dev_priv, pipe);
2370 ilk_pch_transcoder_set_timings(crtc_state, pipe);
2372 intel_fdi_normal_train(crtc);
2374 /* For PCH DP, enable TRANS_DP_CTL */
2375 if (HAS_PCH_CPT(dev_priv) &&
2376 intel_crtc_has_dp_encoder(crtc_state)) {
2377 const struct drm_display_mode *adjusted_mode =
2378 &crtc_state->hw.adjusted_mode;
2379 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2380 i915_reg_t reg = TRANS_DP_CTL(pipe);
2383 temp = intel_de_read(dev_priv, reg);
2384 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2385 TRANS_DP_SYNC_MASK |
2387 temp |= TRANS_DP_OUTPUT_ENABLE;
2388 temp |= bpc << 9; /* same format but at 11:9 */
2390 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2391 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2392 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2393 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2395 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
2396 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
2397 temp |= TRANS_DP_PORT_SEL(port);
2399 intel_de_write(dev_priv, reg, temp);
2402 ilk_enable_pch_transcoder(crtc_state);
2405 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
2407 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2408 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2409 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2411 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
2413 lpt_program_iclkip(crtc_state);
2415 /* Set transcoder timing. */
2416 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
2418 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
2421 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
2424 i915_reg_t dslreg = PIPEDSL(pipe);
2427 temp = intel_de_read(dev_priv, dslreg);
2429 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
2430 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
2431 drm_err(&dev_priv->drm,
2432 "mode set failed: pipe %c stuck\n",
2437 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
2439 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2440 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2441 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
2442 enum pipe pipe = crtc->pipe;
2443 int width = drm_rect_width(dst);
2444 int height = drm_rect_height(dst);
2448 if (!crtc_state->pch_pfit.enabled)
2451 /* Force use of hard-coded filter coefficients
2452 * as some pre-programmed values are broken,
2455 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
2456 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
2457 PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
2459 intel_de_write(dev_priv, PF_CTL(pipe), PF_ENABLE |
2461 intel_de_write(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
2462 intel_de_write(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
2465 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
2467 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2468 struct drm_device *dev = crtc->base.dev;
2469 struct drm_i915_private *dev_priv = to_i915(dev);
2471 if (!crtc_state->ips_enabled)
2475 * We can only enable IPS after we enable a plane and wait for a vblank
2476 * This function is called from post_plane_update, which is run after
2479 drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
2481 if (IS_BROADWELL(dev_priv)) {
2482 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
2483 IPS_ENABLE | IPS_PCODE_CONTROL));
2484 /* Quoting Art Runyan: "its not safe to expect any particular
2485 * value in IPS_CTL bit 31 after enabling IPS through the
2486 * mailbox." Moreover, the mailbox may return a bogus state,
2487 * so we need to just enable it and continue on.
2490 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
2491 /* The bit only becomes 1 in the next vblank, so this wait here
2492 * is essentially intel_wait_for_vblank. If we don't have this
2493 * and don't wait for vblanks until the end of crtc_enable, then
2494 * the HW state readout code will complain that the expected
2495 * IPS_CTL value is not the one we read. */
2496 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
2497 drm_err(&dev_priv->drm,
2498 "Timed out waiting for IPS enable\n");
2502 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
2504 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2505 struct drm_device *dev = crtc->base.dev;
2506 struct drm_i915_private *dev_priv = to_i915(dev);
2508 if (!crtc_state->ips_enabled)
2511 if (IS_BROADWELL(dev_priv)) {
2513 sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
2515 * Wait for PCODE to finish disabling IPS. The BSpec specified
2516 * 42ms timeout value leads to occasional timeouts so use 100ms
2519 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
2520 drm_err(&dev_priv->drm,
2521 "Timed out waiting for IPS disable\n");
2523 intel_de_write(dev_priv, IPS_CTL, 0);
2524 intel_de_posting_read(dev_priv, IPS_CTL);
2527 /* We need to wait for a vblank before we can disable the plane. */
2528 intel_wait_for_vblank(dev_priv, crtc->pipe);
2531 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
2534 (void) intel_overlay_switch_off(crtc->overlay);
2536 /* Let userspace switch the overlay on again. In most cases userspace
2537 * has to recompute where to put it anyway.
2541 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
2542 const struct intel_crtc_state *new_crtc_state)
2544 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2545 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2547 if (!old_crtc_state->ips_enabled)
2550 if (intel_crtc_needs_modeset(new_crtc_state))
2554 * Workaround : Do not read or write the pipe palette/gamma data while
2555 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
2557 * Disable IPS before we program the LUT.
2559 if (IS_HASWELL(dev_priv) &&
2560 (new_crtc_state->uapi.color_mgmt_changed ||
2561 new_crtc_state->update_pipe) &&
2562 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2565 return !new_crtc_state->ips_enabled;
2568 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
2569 const struct intel_crtc_state *new_crtc_state)
2571 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2574 if (!new_crtc_state->ips_enabled)
2577 if (intel_crtc_needs_modeset(new_crtc_state))
2581 * Workaround : Do not read or write the pipe palette/gamma data while
2582 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
2584 * Re-enable IPS after the LUT has been programmed.
2586 if (IS_HASWELL(dev_priv) &&
2587 (new_crtc_state->uapi.color_mgmt_changed ||
2588 new_crtc_state->update_pipe) &&
2589 new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2593 * We can't read out IPS on broadwell, assume the worst and
2594 * forcibly enable IPS on the first fastset.
2596 if (new_crtc_state->update_pipe && old_crtc_state->inherited)
2599 return !old_crtc_state->ips_enabled;
2602 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
2604 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2606 if (!crtc_state->nv12_planes)
2609 /* WA Display #0827: Gen9:all */
2610 if (DISPLAY_VER(dev_priv) == 9)
2616 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
2618 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2620 /* Wa_2006604312:icl,ehl */
2621 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
2627 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
2628 const struct intel_crtc_state *new_crtc_state)
2630 return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
2631 new_crtc_state->active_planes;
2634 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
2635 const struct intel_crtc_state *new_crtc_state)
2637 return old_crtc_state->active_planes &&
2638 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
2641 static void intel_post_plane_update(struct intel_atomic_state *state,
2642 struct intel_crtc *crtc)
2644 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2645 const struct intel_crtc_state *old_crtc_state =
2646 intel_atomic_get_old_crtc_state(state, crtc);
2647 const struct intel_crtc_state *new_crtc_state =
2648 intel_atomic_get_new_crtc_state(state, crtc);
2649 enum pipe pipe = crtc->pipe;
2651 intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
2653 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
2654 intel_update_watermarks(crtc);
2656 if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
2657 hsw_enable_ips(new_crtc_state);
2659 intel_fbc_post_update(state, crtc);
2661 if (needs_nv12_wa(old_crtc_state) &&
2662 !needs_nv12_wa(new_crtc_state))
2663 skl_wa_827(dev_priv, pipe, false);
2665 if (needs_scalerclk_wa(old_crtc_state) &&
2666 !needs_scalerclk_wa(new_crtc_state))
2667 icl_wa_scalerclkgating(dev_priv, pipe, false);
2670 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
2671 struct intel_crtc *crtc)
2673 const struct intel_crtc_state *crtc_state =
2674 intel_atomic_get_new_crtc_state(state, crtc);
2675 u8 update_planes = crtc_state->update_planes;
2676 const struct intel_plane_state *plane_state;
2677 struct intel_plane *plane;
2680 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2681 if (plane->enable_flip_done &&
2682 plane->pipe == crtc->pipe &&
2683 update_planes & BIT(plane->id))
2684 plane->enable_flip_done(plane);
2688 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
2689 struct intel_crtc *crtc)
2691 const struct intel_crtc_state *crtc_state =
2692 intel_atomic_get_new_crtc_state(state, crtc);
2693 u8 update_planes = crtc_state->update_planes;
2694 const struct intel_plane_state *plane_state;
2695 struct intel_plane *plane;
2698 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2699 if (plane->disable_flip_done &&
2700 plane->pipe == crtc->pipe &&
2701 update_planes & BIT(plane->id))
2702 plane->disable_flip_done(plane);
2706 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
2707 struct intel_crtc *crtc)
2709 struct drm_i915_private *i915 = to_i915(state->base.dev);
2710 const struct intel_crtc_state *old_crtc_state =
2711 intel_atomic_get_old_crtc_state(state, crtc);
2712 const struct intel_crtc_state *new_crtc_state =
2713 intel_atomic_get_new_crtc_state(state, crtc);
2714 u8 update_planes = new_crtc_state->update_planes;
2715 const struct intel_plane_state *old_plane_state;
2716 struct intel_plane *plane;
2717 bool need_vbl_wait = false;
2720 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
2721 if (plane->need_async_flip_disable_wa &&
2722 plane->pipe == crtc->pipe &&
2723 update_planes & BIT(plane->id)) {
2725 * Apart from the async flip bit we want to
2726 * preserve the old state for the plane.
2728 plane->async_flip(plane, old_crtc_state,
2729 old_plane_state, false);
2730 need_vbl_wait = true;
2735 intel_wait_for_vblank(i915, crtc->pipe);
2738 static void intel_pre_plane_update(struct intel_atomic_state *state,
2739 struct intel_crtc *crtc)
2741 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2742 const struct intel_crtc_state *old_crtc_state =
2743 intel_atomic_get_old_crtc_state(state, crtc);
2744 const struct intel_crtc_state *new_crtc_state =
2745 intel_atomic_get_new_crtc_state(state, crtc);
2746 enum pipe pipe = crtc->pipe;
2748 if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
2749 hsw_disable_ips(old_crtc_state);
2751 if (intel_fbc_pre_update(state, crtc))
2752 intel_wait_for_vblank(dev_priv, pipe);
2754 /* Display WA 827 */
2755 if (!needs_nv12_wa(old_crtc_state) &&
2756 needs_nv12_wa(new_crtc_state))
2757 skl_wa_827(dev_priv, pipe, true);
2759 /* Wa_2006604312:icl,ehl */
2760 if (!needs_scalerclk_wa(old_crtc_state) &&
2761 needs_scalerclk_wa(new_crtc_state))
2762 icl_wa_scalerclkgating(dev_priv, pipe, true);
2765 * Vblank time updates from the shadow to live plane control register
2766 * are blocked if the memory self-refresh mode is active at that
2767 * moment. So to make sure the plane gets truly disabled, disable
2768 * first the self-refresh mode. The self-refresh enable bit in turn
2769 * will be checked/applied by the HW only at the next frame start
2770 * event which is after the vblank start event, so we need to have a
2771 * wait-for-vblank between disabling the plane and the pipe.
2773 if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
2774 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
2775 intel_wait_for_vblank(dev_priv, pipe);
2778 * IVB workaround: must disable low power watermarks for at least
2779 * one frame before enabling scaling. LP watermarks can be re-enabled
2780 * when scaling is disabled.
2782 * WaCxSRDisabledForSpriteScaling:ivb
2784 if (old_crtc_state->hw.active &&
2785 new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
2786 intel_wait_for_vblank(dev_priv, pipe);
2789 * If we're doing a modeset we don't need to do any
2790 * pre-vblank watermark programming here.
2792 if (!intel_crtc_needs_modeset(new_crtc_state)) {
2794 * For platforms that support atomic watermarks, program the
2795 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
2796 * will be the intermediate values that are safe for both pre- and
2797 * post- vblank; when vblank happens, the 'active' values will be set
2798 * to the final 'target' values and we'll do this again to get the
2799 * optimal watermarks. For gen9+ platforms, the values we program here
2800 * will be the final target values which will get automatically latched
2801 * at vblank time; no further programming will be necessary.
2803 * If a platform hasn't been transitioned to atomic watermarks yet,
2804 * we'll continue to update watermarks the old way, if flags tell
2807 if (dev_priv->display.initial_watermarks)
2808 dev_priv->display.initial_watermarks(state, crtc);
2809 else if (new_crtc_state->update_wm_pre)
2810 intel_update_watermarks(crtc);
2814 * Gen2 reports pipe underruns whenever all planes are disabled.
2815 * So disable underrun reporting before all the planes get disabled.
2817 * We do this after .initial_watermarks() so that we have a
2818 * chance of catching underruns with the intermediate watermarks
2819 * vs. the old plane configuration.
2821 if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
2822 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2825 * WA for platforms where async address update enable bit
2826 * is double buffered and only latched at start of vblank.
2828 if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
2829 intel_crtc_async_flip_disable_wa(state, crtc);
2832 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
2833 struct intel_crtc *crtc)
2835 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2836 const struct intel_crtc_state *new_crtc_state =
2837 intel_atomic_get_new_crtc_state(state, crtc);
2838 unsigned int update_mask = new_crtc_state->update_planes;
2839 const struct intel_plane_state *old_plane_state;
2840 struct intel_plane *plane;
2841 unsigned fb_bits = 0;
2844 intel_crtc_dpms_overlay_disable(crtc);
2846 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
2847 if (crtc->pipe != plane->pipe ||
2848 !(update_mask & BIT(plane->id)))
2851 intel_disable_plane(plane, new_crtc_state);
2853 if (old_plane_state->uapi.visible)
2854 fb_bits |= plane->frontbuffer_bit;
2857 intel_frontbuffer_flip(dev_priv, fb_bits);
2861 * intel_connector_primary_encoder - get the primary encoder for a connector
2862 * @connector: connector for which to return the encoder
2864 * Returns the primary encoder for a connector. There is a 1:1 mapping from
2865 * all connectors to their encoder, except for DP-MST connectors which have
2866 * both a virtual and a primary encoder. These DP-MST primary encoders can be
2867 * pointed to by as many DP-MST connectors as there are pipes.
2869 static struct intel_encoder *
2870 intel_connector_primary_encoder(struct intel_connector *connector)
2872 struct intel_encoder *encoder;
2874 if (connector->mst_port)
2875 return &dp_to_dig_port(connector->mst_port)->base;
2877 encoder = intel_attached_encoder(connector);
2878 drm_WARN_ON(connector->base.dev, !encoder);
2883 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
2885 struct drm_connector_state *new_conn_state;
2886 struct drm_connector *connector;
2889 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
2891 struct intel_connector *intel_connector;
2892 struct intel_encoder *encoder;
2893 struct intel_crtc *crtc;
2895 if (!intel_connector_needs_modeset(state, connector))
2898 intel_connector = to_intel_connector(connector);
2899 encoder = intel_connector_primary_encoder(intel_connector);
2900 if (!encoder->update_prepare)
2903 crtc = new_conn_state->crtc ?
2904 to_intel_crtc(new_conn_state->crtc) : NULL;
2905 encoder->update_prepare(state, encoder, crtc);
2909 static void intel_encoders_update_complete(struct intel_atomic_state *state)
2911 struct drm_connector_state *new_conn_state;
2912 struct drm_connector *connector;
2915 for_each_new_connector_in_state(&state->base, connector, new_conn_state,
2917 struct intel_connector *intel_connector;
2918 struct intel_encoder *encoder;
2919 struct intel_crtc *crtc;
2921 if (!intel_connector_needs_modeset(state, connector))
2924 intel_connector = to_intel_connector(connector);
2925 encoder = intel_connector_primary_encoder(intel_connector);
2926 if (!encoder->update_complete)
2929 crtc = new_conn_state->crtc ?
2930 to_intel_crtc(new_conn_state->crtc) : NULL;
2931 encoder->update_complete(state, encoder, crtc);
2935 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
2936 struct intel_crtc *crtc)
2938 const struct intel_crtc_state *crtc_state =
2939 intel_atomic_get_new_crtc_state(state, crtc);
2940 const struct drm_connector_state *conn_state;
2941 struct drm_connector *conn;
2944 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2945 struct intel_encoder *encoder =
2946 to_intel_encoder(conn_state->best_encoder);
2948 if (conn_state->crtc != &crtc->base)
2951 if (encoder->pre_pll_enable)
2952 encoder->pre_pll_enable(state, encoder,
2953 crtc_state, conn_state);
2957 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
2958 struct intel_crtc *crtc)
2960 const struct intel_crtc_state *crtc_state =
2961 intel_atomic_get_new_crtc_state(state, crtc);
2962 const struct drm_connector_state *conn_state;
2963 struct drm_connector *conn;
2966 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2967 struct intel_encoder *encoder =
2968 to_intel_encoder(conn_state->best_encoder);
2970 if (conn_state->crtc != &crtc->base)
2973 if (encoder->pre_enable)
2974 encoder->pre_enable(state, encoder,
2975 crtc_state, conn_state);
2979 static void intel_encoders_enable(struct intel_atomic_state *state,
2980 struct intel_crtc *crtc)
2982 const struct intel_crtc_state *crtc_state =
2983 intel_atomic_get_new_crtc_state(state, crtc);
2984 const struct drm_connector_state *conn_state;
2985 struct drm_connector *conn;
2988 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2989 struct intel_encoder *encoder =
2990 to_intel_encoder(conn_state->best_encoder);
2992 if (conn_state->crtc != &crtc->base)
2995 if (encoder->enable)
2996 encoder->enable(state, encoder,
2997 crtc_state, conn_state);
2998 intel_opregion_notify_encoder(encoder, true);
3002 static void intel_encoders_pre_disable(struct intel_atomic_state *state,
3003 struct intel_crtc *crtc)
3005 const struct intel_crtc_state *old_crtc_state =
3006 intel_atomic_get_old_crtc_state(state, crtc);
3007 const struct drm_connector_state *old_conn_state;
3008 struct drm_connector *conn;
3011 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3012 struct intel_encoder *encoder =
3013 to_intel_encoder(old_conn_state->best_encoder);
3015 if (old_conn_state->crtc != &crtc->base)
3018 if (encoder->pre_disable)
3019 encoder->pre_disable(state, encoder, old_crtc_state,
3024 static void intel_encoders_disable(struct intel_atomic_state *state,
3025 struct intel_crtc *crtc)
3027 const struct intel_crtc_state *old_crtc_state =
3028 intel_atomic_get_old_crtc_state(state, crtc);
3029 const struct drm_connector_state *old_conn_state;
3030 struct drm_connector *conn;
3033 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3034 struct intel_encoder *encoder =
3035 to_intel_encoder(old_conn_state->best_encoder);
3037 if (old_conn_state->crtc != &crtc->base)
3040 intel_opregion_notify_encoder(encoder, false);
3041 if (encoder->disable)
3042 encoder->disable(state, encoder,
3043 old_crtc_state, old_conn_state);
3047 static void intel_encoders_post_disable(struct intel_atomic_state *state,
3048 struct intel_crtc *crtc)
3050 const struct intel_crtc_state *old_crtc_state =
3051 intel_atomic_get_old_crtc_state(state, crtc);
3052 const struct drm_connector_state *old_conn_state;
3053 struct drm_connector *conn;
3056 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3057 struct intel_encoder *encoder =
3058 to_intel_encoder(old_conn_state->best_encoder);
3060 if (old_conn_state->crtc != &crtc->base)
3063 if (encoder->post_disable)
3064 encoder->post_disable(state, encoder,
3065 old_crtc_state, old_conn_state);
3069 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
3070 struct intel_crtc *crtc)
3072 const struct intel_crtc_state *old_crtc_state =
3073 intel_atomic_get_old_crtc_state(state, crtc);
3074 const struct drm_connector_state *old_conn_state;
3075 struct drm_connector *conn;
3078 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
3079 struct intel_encoder *encoder =
3080 to_intel_encoder(old_conn_state->best_encoder);
3082 if (old_conn_state->crtc != &crtc->base)
3085 if (encoder->post_pll_disable)
3086 encoder->post_pll_disable(state, encoder,
3087 old_crtc_state, old_conn_state);
3091 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
3092 struct intel_crtc *crtc)
3094 const struct intel_crtc_state *crtc_state =
3095 intel_atomic_get_new_crtc_state(state, crtc);
3096 const struct drm_connector_state *conn_state;
3097 struct drm_connector *conn;
3100 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3101 struct intel_encoder *encoder =
3102 to_intel_encoder(conn_state->best_encoder);
3104 if (conn_state->crtc != &crtc->base)
3107 if (encoder->update_pipe)
3108 encoder->update_pipe(state, encoder,
3109 crtc_state, conn_state);
3113 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
3115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3116 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3118 plane->disable_plane(plane, crtc_state);
3121 static void ilk_crtc_enable(struct intel_atomic_state *state,
3122 struct intel_crtc *crtc)
3124 const struct intel_crtc_state *new_crtc_state =
3125 intel_atomic_get_new_crtc_state(state, crtc);
3126 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3127 enum pipe pipe = crtc->pipe;
3129 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3133 * Sometimes spurious CPU pipe underruns happen during FDI
3134 * training, at least with VGA+HDMI cloning. Suppress them.
3136 * On ILK we get an occasional spurious CPU pipe underruns
3137 * between eDP port A enable and vdd enable. Also PCH port
3138 * enable seems to result in the occasional CPU pipe underrun.
3140 * Spurious PCH underruns also occur during PCH enabling.
3142 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3143 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3145 if (new_crtc_state->has_pch_encoder)
3146 intel_prepare_shared_dpll(new_crtc_state);
3148 if (intel_crtc_has_dp_encoder(new_crtc_state))
3149 intel_dp_set_m_n(new_crtc_state, M1_N1);
3151 intel_set_transcoder_timings(new_crtc_state);
3152 intel_set_pipe_src_size(new_crtc_state);
3154 if (new_crtc_state->has_pch_encoder)
3155 intel_cpu_transcoder_set_m_n(new_crtc_state,
3156 &new_crtc_state->fdi_m_n, NULL);
3158 ilk_set_pipeconf(new_crtc_state);
3160 crtc->active = true;
3162 intel_encoders_pre_enable(state, crtc);
3164 if (new_crtc_state->has_pch_encoder) {
3165 /* Note: FDI PLL enabling _must_ be done before we enable the
3166 * cpu pipes, hence this is separate from all the other fdi/pch
3168 ilk_fdi_pll_enable(new_crtc_state);
3170 assert_fdi_tx_disabled(dev_priv, pipe);
3171 assert_fdi_rx_disabled(dev_priv, pipe);
3174 ilk_pfit_enable(new_crtc_state);
3177 * On ILK+ LUT must be loaded before the pipe is running but with
3180 intel_color_load_luts(new_crtc_state);
3181 intel_color_commit(new_crtc_state);
3182 /* update DSPCNTR to configure gamma for pipe bottom color */
3183 intel_disable_primary_plane(new_crtc_state);
3185 if (dev_priv->display.initial_watermarks)
3186 dev_priv->display.initial_watermarks(state, crtc);
3187 intel_enable_pipe(new_crtc_state);
3189 if (new_crtc_state->has_pch_encoder)
3190 ilk_pch_enable(state, new_crtc_state);
3192 intel_crtc_vblank_on(new_crtc_state);
3194 intel_encoders_enable(state, crtc);
3196 if (HAS_PCH_CPT(dev_priv))
3197 cpt_verify_modeset(dev_priv, pipe);
3200 * Must wait for vblank to avoid spurious PCH FIFO underruns.
3201 * And a second vblank wait is needed at least on ILK with
3202 * some interlaced HDMI modes. Let's do the double wait always
3203 * in case there are more corner cases we don't know about.
3205 if (new_crtc_state->has_pch_encoder) {
3206 intel_wait_for_vblank(dev_priv, pipe);
3207 intel_wait_for_vblank(dev_priv, pipe);
3209 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3210 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3213 /* IPS only exists on ULT machines and is tied to pipe A. */
3214 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3216 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
3219 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
3220 enum pipe pipe, bool apply)
3222 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
3223 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
3230 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
3233 static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
3235 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3236 enum pipe pipe = crtc->pipe;
3239 /* Wa_22010947358:adl-p */
3240 if (IS_ALDERLAKE_P(dev_priv))
3241 val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
3243 val = MBUS_DBOX_A_CREDIT(2);
3245 if (DISPLAY_VER(dev_priv) >= 12) {
3246 val |= MBUS_DBOX_BW_CREDIT(2);
3247 val |= MBUS_DBOX_B_CREDIT(12);
3249 val |= MBUS_DBOX_BW_CREDIT(1);
3250 val |= MBUS_DBOX_B_CREDIT(8);
3253 intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
3256 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
3258 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3259 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3261 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
3262 HSW_LINETIME(crtc_state->linetime) |
3263 HSW_IPS_LINETIME(crtc_state->ips_linetime));
3266 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
3268 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3269 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3270 i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
3273 val = intel_de_read(dev_priv, reg);
3274 val &= ~HSW_FRAME_START_DELAY_MASK;
3275 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
3276 intel_de_write(dev_priv, reg, val);
3279 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
3280 const struct intel_crtc_state *crtc_state)
3282 struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
3283 struct drm_i915_private *dev_priv = to_i915(master->base.dev);
3284 struct intel_crtc_state *master_crtc_state;
3285 struct drm_connector_state *conn_state;
3286 struct drm_connector *conn;
3287 struct intel_encoder *encoder = NULL;
3290 if (crtc_state->bigjoiner_slave)
3291 master = crtc_state->bigjoiner_linked_crtc;
3293 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
3295 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3296 if (conn_state->crtc != &master->base)
3299 encoder = to_intel_encoder(conn_state->best_encoder);
3303 if (!crtc_state->bigjoiner_slave) {
3304 /* need to enable VDSC, which we skipped in pre-enable */
3305 intel_dsc_enable(encoder, crtc_state);
3308 * Enable sequence steps 1-7 on bigjoiner master
3310 intel_encoders_pre_pll_enable(state, master);
3311 if (master_crtc_state->shared_dpll)
3312 intel_enable_shared_dpll(master_crtc_state);
3313 intel_encoders_pre_enable(state, master);
3315 /* and DSC on slave */
3316 intel_dsc_enable(NULL, crtc_state);
3319 if (DISPLAY_VER(dev_priv) >= 13)
3320 intel_uncompressed_joiner_enable(crtc_state);
3323 static void hsw_crtc_enable(struct intel_atomic_state *state,
3324 struct intel_crtc *crtc)
3326 const struct intel_crtc_state *new_crtc_state =
3327 intel_atomic_get_new_crtc_state(state, crtc);
3328 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3329 enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
3330 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
3331 bool psl_clkgate_wa;
3333 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3336 if (!new_crtc_state->bigjoiner) {
3337 intel_encoders_pre_pll_enable(state, crtc);
3339 if (new_crtc_state->shared_dpll)
3340 intel_enable_shared_dpll(new_crtc_state);
3342 intel_encoders_pre_enable(state, crtc);
3344 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
3347 intel_set_pipe_src_size(new_crtc_state);
3348 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
3349 bdw_set_pipemisc(new_crtc_state);
3351 if (!new_crtc_state->bigjoiner_slave && !transcoder_is_dsi(cpu_transcoder)) {
3352 intel_set_transcoder_timings(new_crtc_state);
3354 if (cpu_transcoder != TRANSCODER_EDP)
3355 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
3356 new_crtc_state->pixel_multiplier - 1);
3358 if (new_crtc_state->has_pch_encoder)
3359 intel_cpu_transcoder_set_m_n(new_crtc_state,
3360 &new_crtc_state->fdi_m_n, NULL);
3362 hsw_set_frame_start_delay(new_crtc_state);
3365 if (!transcoder_is_dsi(cpu_transcoder))
3366 hsw_set_pipeconf(new_crtc_state);
3368 crtc->active = true;
3370 /* Display WA #1180: WaDisableScalarClockGating: glk */
3371 psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
3372 new_crtc_state->pch_pfit.enabled;
3374 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
3376 if (DISPLAY_VER(dev_priv) >= 9)
3377 skl_pfit_enable(new_crtc_state);
3379 ilk_pfit_enable(new_crtc_state);
3382 * On ILK+ LUT must be loaded before the pipe is running but with
3385 intel_color_load_luts(new_crtc_state);
3386 intel_color_commit(new_crtc_state);
3387 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
3388 if (DISPLAY_VER(dev_priv) < 9)
3389 intel_disable_primary_plane(new_crtc_state);
3391 hsw_set_linetime_wm(new_crtc_state);
3393 if (DISPLAY_VER(dev_priv) >= 11)
3394 icl_set_pipe_chicken(new_crtc_state);
3396 if (dev_priv->display.initial_watermarks)
3397 dev_priv->display.initial_watermarks(state, crtc);
3399 if (DISPLAY_VER(dev_priv) >= 11) {
3400 const struct intel_dbuf_state *dbuf_state =
3401 intel_atomic_get_new_dbuf_state(state);
3403 icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
3406 if (new_crtc_state->bigjoiner_slave)
3407 intel_crtc_vblank_on(new_crtc_state);
3409 intel_encoders_enable(state, crtc);
3411 if (psl_clkgate_wa) {
3412 intel_wait_for_vblank(dev_priv, pipe);
3413 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
3416 /* If we change the relative order between pipe/planes enabling, we need
3417 * to change the workaround. */
3418 hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
3419 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
3420 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
3421 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
3425 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
3427 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3428 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3429 enum pipe pipe = crtc->pipe;
3431 /* To avoid upsetting the power well on haswell only disable the pfit if
3432 * it's in use. The hw state code will make sure we get this right. */
3433 if (!old_crtc_state->pch_pfit.enabled)
3436 intel_de_write(dev_priv, PF_CTL(pipe), 0);
3437 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
3438 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
3441 static void ilk_crtc_disable(struct intel_atomic_state *state,
3442 struct intel_crtc *crtc)
3444 const struct intel_crtc_state *old_crtc_state =
3445 intel_atomic_get_old_crtc_state(state, crtc);
3446 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3447 enum pipe pipe = crtc->pipe;
3450 * Sometimes spurious CPU pipe underruns happen when the
3451 * pipe is already disabled, but FDI RX/TX is still enabled.
3452 * Happens at least with VGA+HDMI cloning. Suppress them.
3454 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3455 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
3457 intel_encoders_disable(state, crtc);
3459 intel_crtc_vblank_off(old_crtc_state);
3461 intel_disable_pipe(old_crtc_state);
3463 ilk_pfit_disable(old_crtc_state);
3465 if (old_crtc_state->has_pch_encoder)
3466 ilk_fdi_disable(crtc);
3468 intel_encoders_post_disable(state, crtc);
3470 if (old_crtc_state->has_pch_encoder) {
3471 ilk_disable_pch_transcoder(dev_priv, pipe);
3473 if (HAS_PCH_CPT(dev_priv)) {
3477 /* disable TRANS_DP_CTL */
3478 reg = TRANS_DP_CTL(pipe);
3479 temp = intel_de_read(dev_priv, reg);
3480 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3481 TRANS_DP_PORT_SEL_MASK);
3482 temp |= TRANS_DP_PORT_SEL_NONE;
3483 intel_de_write(dev_priv, reg, temp);
3485 /* disable DPLL_SEL */
3486 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
3487 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3488 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
3491 ilk_fdi_pll_disable(crtc);
3494 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3495 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
3498 static void hsw_crtc_disable(struct intel_atomic_state *state,
3499 struct intel_crtc *crtc)
3502 * FIXME collapse everything to one hook.
3503 * Need care with mst->ddi interactions.
3505 intel_encoders_disable(state, crtc);
3506 intel_encoders_post_disable(state, crtc);
3509 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
3511 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3512 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3514 if (!crtc_state->gmch_pfit.control)
3518 * The panel fitter should only be adjusted whilst the pipe is disabled,
3519 * according to register description and PRM.
3521 drm_WARN_ON(&dev_priv->drm,
3522 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
3523 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
3525 intel_de_write(dev_priv, PFIT_PGM_RATIOS,
3526 crtc_state->gmch_pfit.pgm_ratios);
3527 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
3529 /* Border color in case we don't scale up to the full screen. Black by
3530 * default, change to something else for debugging. */
3531 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
3534 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
3536 if (phy == PHY_NONE)
3538 else if (IS_DG2(dev_priv))
3540 * DG2 outputs labelled as "combo PHY" in the bspec use
3541 * SNPS PHYs with completely different programming,
3542 * hence we always return false here.
3545 else if (IS_ALDERLAKE_S(dev_priv))
3546 return phy <= PHY_E;
3547 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
3548 return phy <= PHY_D;
3549 else if (IS_JSL_EHL(dev_priv))
3550 return phy <= PHY_C;
3551 else if (DISPLAY_VER(dev_priv) >= 11)
3552 return phy <= PHY_B;
3557 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
3559 if (IS_DG2(dev_priv))
3560 /* DG2's "TC1" output uses a SNPS PHY */
3562 else if (IS_ALDERLAKE_P(dev_priv))
3563 return phy >= PHY_F && phy <= PHY_I;
3564 else if (IS_TIGERLAKE(dev_priv))
3565 return phy >= PHY_D && phy <= PHY_I;
3566 else if (IS_ICELAKE(dev_priv))
3567 return phy >= PHY_C && phy <= PHY_F;
3572 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
3574 if (phy == PHY_NONE)
3576 else if (IS_DG2(dev_priv))
3578 * All four "combo" ports and the TC1 port (PHY E) use
3581 return phy <= PHY_E;
3586 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
3588 if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
3589 return PHY_D + port - PORT_D_XELPD;
3590 else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
3591 return PHY_F + port - PORT_TC1;
3592 else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
3593 return PHY_B + port - PORT_TC1;
3594 else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
3595 return PHY_C + port - PORT_TC1;
3596 else if (IS_JSL_EHL(i915) && port == PORT_D)
3599 return PHY_A + port - PORT_A;
3602 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
3604 if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
3605 return TC_PORT_NONE;
3607 if (DISPLAY_VER(dev_priv) >= 12)
3608 return TC_PORT_1 + port - PORT_TC1;
3610 return TC_PORT_1 + port - PORT_C;
3613 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
3617 return POWER_DOMAIN_PORT_DDI_A_LANES;
3619 return POWER_DOMAIN_PORT_DDI_B_LANES;
3621 return POWER_DOMAIN_PORT_DDI_C_LANES;
3623 return POWER_DOMAIN_PORT_DDI_D_LANES;
3625 return POWER_DOMAIN_PORT_DDI_E_LANES;
3627 return POWER_DOMAIN_PORT_DDI_F_LANES;
3629 return POWER_DOMAIN_PORT_DDI_G_LANES;
3631 return POWER_DOMAIN_PORT_DDI_H_LANES;
3633 return POWER_DOMAIN_PORT_DDI_I_LANES;
3636 return POWER_DOMAIN_PORT_OTHER;
3640 enum intel_display_power_domain
3641 intel_aux_power_domain(struct intel_digital_port *dig_port)
3643 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3644 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
3646 if (intel_phy_is_tc(dev_priv, phy) &&
3647 dig_port->tc_mode == TC_PORT_TBT_ALT) {
3648 switch (dig_port->aux_ch) {
3650 return POWER_DOMAIN_AUX_C_TBT;
3652 return POWER_DOMAIN_AUX_D_TBT;
3654 return POWER_DOMAIN_AUX_E_TBT;
3656 return POWER_DOMAIN_AUX_F_TBT;
3658 return POWER_DOMAIN_AUX_G_TBT;
3660 return POWER_DOMAIN_AUX_H_TBT;
3662 return POWER_DOMAIN_AUX_I_TBT;
3664 MISSING_CASE(dig_port->aux_ch);
3665 return POWER_DOMAIN_AUX_C_TBT;
3669 return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
3673 * Converts aux_ch to power_domain without caring about TBT ports for that use
3674 * intel_aux_power_domain()
3676 enum intel_display_power_domain
3677 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
3681 return POWER_DOMAIN_AUX_A;
3683 return POWER_DOMAIN_AUX_B;
3685 return POWER_DOMAIN_AUX_C;
3687 return POWER_DOMAIN_AUX_D;
3689 return POWER_DOMAIN_AUX_E;
3691 return POWER_DOMAIN_AUX_F;
3693 return POWER_DOMAIN_AUX_G;
3695 return POWER_DOMAIN_AUX_H;
3697 return POWER_DOMAIN_AUX_I;
3699 MISSING_CASE(aux_ch);
3700 return POWER_DOMAIN_AUX_A;
3704 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
3706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3707 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3708 struct drm_encoder *encoder;
3709 enum pipe pipe = crtc->pipe;
3711 enum transcoder transcoder = crtc_state->cpu_transcoder;
3713 if (!crtc_state->hw.active)
3716 mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
3717 mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
3718 if (crtc_state->pch_pfit.enabled ||
3719 crtc_state->pch_pfit.force_thru)
3720 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
3722 drm_for_each_encoder_mask(encoder, &dev_priv->drm,
3723 crtc_state->uapi.encoder_mask) {
3724 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3726 mask |= BIT_ULL(intel_encoder->power_domain);
3729 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
3730 mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
3732 if (crtc_state->shared_dpll)
3733 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
3735 if (crtc_state->dsc.compression_enable)
3736 mask |= BIT_ULL(intel_dsc_power_domain(crtc_state));
3742 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
3744 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3745 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3746 enum intel_display_power_domain domain;
3747 u64 domains, new_domains, old_domains;
3749 domains = get_crtc_power_domains(crtc_state);
3751 new_domains = domains & ~crtc->enabled_power_domains.mask;
3752 old_domains = crtc->enabled_power_domains.mask & ~domains;
3754 for_each_power_domain(domain, new_domains)
3755 intel_display_power_get_in_set(dev_priv,
3756 &crtc->enabled_power_domains,
3762 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
3765 intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
3766 &crtc->enabled_power_domains,
3770 static void valleyview_crtc_enable(struct intel_atomic_state *state,
3771 struct intel_crtc *crtc)
3773 const struct intel_crtc_state *new_crtc_state =
3774 intel_atomic_get_new_crtc_state(state, crtc);
3775 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3776 enum pipe pipe = crtc->pipe;
3778 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3781 if (intel_crtc_has_dp_encoder(new_crtc_state))
3782 intel_dp_set_m_n(new_crtc_state, M1_N1);
3784 intel_set_transcoder_timings(new_crtc_state);
3785 intel_set_pipe_src_size(new_crtc_state);
3787 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
3788 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
3789 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
3792 i9xx_set_pipeconf(new_crtc_state);
3794 crtc->active = true;
3796 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3798 intel_encoders_pre_pll_enable(state, crtc);
3800 if (IS_CHERRYVIEW(dev_priv)) {
3801 chv_prepare_pll(crtc, new_crtc_state);
3802 chv_enable_pll(crtc, new_crtc_state);
3804 vlv_prepare_pll(crtc, new_crtc_state);
3805 vlv_enable_pll(crtc, new_crtc_state);
3808 intel_encoders_pre_enable(state, crtc);
3810 i9xx_pfit_enable(new_crtc_state);
3812 intel_color_load_luts(new_crtc_state);
3813 intel_color_commit(new_crtc_state);
3814 /* update DSPCNTR to configure gamma for pipe bottom color */
3815 intel_disable_primary_plane(new_crtc_state);
3817 dev_priv->display.initial_watermarks(state, crtc);
3818 intel_enable_pipe(new_crtc_state);
3820 intel_crtc_vblank_on(new_crtc_state);
3822 intel_encoders_enable(state, crtc);
3825 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
3827 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3828 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3830 intel_de_write(dev_priv, FP0(crtc->pipe),
3831 crtc_state->dpll_hw_state.fp0);
3832 intel_de_write(dev_priv, FP1(crtc->pipe),
3833 crtc_state->dpll_hw_state.fp1);
3836 static void i9xx_crtc_enable(struct intel_atomic_state *state,
3837 struct intel_crtc *crtc)
3839 const struct intel_crtc_state *new_crtc_state =
3840 intel_atomic_get_new_crtc_state(state, crtc);
3841 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3842 enum pipe pipe = crtc->pipe;
3844 if (drm_WARN_ON(&dev_priv->drm, crtc->active))
3847 i9xx_set_pll_dividers(new_crtc_state);
3849 if (intel_crtc_has_dp_encoder(new_crtc_state))
3850 intel_dp_set_m_n(new_crtc_state, M1_N1);
3852 intel_set_transcoder_timings(new_crtc_state);
3853 intel_set_pipe_src_size(new_crtc_state);
3855 i9xx_set_pipeconf(new_crtc_state);
3857 crtc->active = true;
3859 if (DISPLAY_VER(dev_priv) != 2)
3860 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3862 intel_encoders_pre_enable(state, crtc);
3864 i9xx_enable_pll(crtc, new_crtc_state);
3866 i9xx_pfit_enable(new_crtc_state);
3868 intel_color_load_luts(new_crtc_state);
3869 intel_color_commit(new_crtc_state);
3870 /* update DSPCNTR to configure gamma for pipe bottom color */
3871 intel_disable_primary_plane(new_crtc_state);
3873 if (dev_priv->display.initial_watermarks)
3874 dev_priv->display.initial_watermarks(state, crtc);
3876 intel_update_watermarks(crtc);
3877 intel_enable_pipe(new_crtc_state);
3879 intel_crtc_vblank_on(new_crtc_state);
3881 intel_encoders_enable(state, crtc);
3883 /* prevents spurious underruns */
3884 if (DISPLAY_VER(dev_priv) == 2)
3885 intel_wait_for_vblank(dev_priv, pipe);
3888 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
3890 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3891 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3893 if (!old_crtc_state->gmch_pfit.control)
3896 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3898 drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
3899 intel_de_read(dev_priv, PFIT_CONTROL));
3900 intel_de_write(dev_priv, PFIT_CONTROL, 0);
3903 static void i9xx_crtc_disable(struct intel_atomic_state *state,
3904 struct intel_crtc *crtc)
3906 struct intel_crtc_state *old_crtc_state =
3907 intel_atomic_get_old_crtc_state(state, crtc);
3908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3909 enum pipe pipe = crtc->pipe;
3912 * On gen2 planes are double buffered but the pipe isn't, so we must
3913 * wait for planes to fully turn off before disabling the pipe.
3915 if (DISPLAY_VER(dev_priv) == 2)
3916 intel_wait_for_vblank(dev_priv, pipe);
3918 intel_encoders_disable(state, crtc);
3920 intel_crtc_vblank_off(old_crtc_state);
3922 intel_disable_pipe(old_crtc_state);
3924 i9xx_pfit_disable(old_crtc_state);
3926 intel_encoders_post_disable(state, crtc);
3928 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
3929 if (IS_CHERRYVIEW(dev_priv))
3930 chv_disable_pll(dev_priv, pipe);
3931 else if (IS_VALLEYVIEW(dev_priv))
3932 vlv_disable_pll(dev_priv, pipe);
3934 i9xx_disable_pll(old_crtc_state);
3937 intel_encoders_post_pll_disable(state, crtc);
3939 if (DISPLAY_VER(dev_priv) != 2)
3940 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
3942 if (!dev_priv->display.initial_watermarks)
3943 intel_update_watermarks(crtc);
3945 /* clock the pipe down to 640x480@60 to potentially save power */
3946 if (IS_I830(dev_priv))
3947 i830_enable_pipe(dev_priv, pipe);
3950 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
3951 struct drm_modeset_acquire_ctx *ctx)
3953 struct intel_encoder *encoder;
3954 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3955 struct intel_bw_state *bw_state =
3956 to_intel_bw_state(dev_priv->bw_obj.state);
3957 struct intel_cdclk_state *cdclk_state =
3958 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
3959 struct intel_dbuf_state *dbuf_state =
3960 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
3961 struct intel_crtc_state *crtc_state =
3962 to_intel_crtc_state(crtc->base.state);
3963 struct intel_plane *plane;
3964 struct drm_atomic_state *state;
3965 struct intel_crtc_state *temp_crtc_state;
3966 enum pipe pipe = crtc->pipe;
3969 if (!crtc_state->hw.active)
3972 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
3973 const struct intel_plane_state *plane_state =
3974 to_intel_plane_state(plane->base.state);
3976 if (plane_state->uapi.visible)
3977 intel_plane_disable_noatomic(crtc, plane);
3980 state = drm_atomic_state_alloc(&dev_priv->drm);
3982 drm_dbg_kms(&dev_priv->drm,
3983 "failed to disable [CRTC:%d:%s], out of memory",
3984 crtc->base.base.id, crtc->base.name);
3988 state->acquire_ctx = ctx;
3990 /* Everything's already locked, -EDEADLK can't happen. */
3991 temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
3992 ret = drm_atomic_add_affected_connectors(state, &crtc->base);
3994 drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
3996 dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
3998 drm_atomic_state_put(state);
4000 drm_dbg_kms(&dev_priv->drm,
4001 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
4002 crtc->base.base.id, crtc->base.name);
4004 crtc->active = false;
4005 crtc->base.enabled = false;
4007 drm_WARN_ON(&dev_priv->drm,
4008 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
4009 crtc_state->uapi.active = false;
4010 crtc_state->uapi.connector_mask = 0;
4011 crtc_state->uapi.encoder_mask = 0;
4012 intel_crtc_free_hw_state(crtc_state);
4013 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
4015 for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
4016 encoder->base.crtc = NULL;
4018 intel_fbc_disable(crtc);
4019 intel_update_watermarks(crtc);
4020 intel_disable_shared_dpll(crtc_state);
4022 intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
4024 dev_priv->active_pipes &= ~BIT(pipe);
4025 cdclk_state->min_cdclk[pipe] = 0;
4026 cdclk_state->min_voltage_level[pipe] = 0;
4027 cdclk_state->active_pipes &= ~BIT(pipe);
4029 dbuf_state->active_pipes &= ~BIT(pipe);
4031 bw_state->data_rate[pipe] = 0;
4032 bw_state->num_active_planes[pipe] = 0;
4036 * turn all crtc's off, but do not adjust state
4037 * This has to be paired with a call to intel_modeset_setup_hw_state.
4039 int intel_display_suspend(struct drm_device *dev)
4041 struct drm_i915_private *dev_priv = to_i915(dev);
4042 struct drm_atomic_state *state;
4045 if (!HAS_DISPLAY(dev_priv))
4048 state = drm_atomic_helper_suspend(dev);
4049 ret = PTR_ERR_OR_ZERO(state);
4051 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4054 dev_priv->modeset_restore_state = state;
4058 void intel_encoder_destroy(struct drm_encoder *encoder)
4060 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4062 drm_encoder_cleanup(encoder);
4063 kfree(intel_encoder);
4066 /* Cross check the actual hw state with our own modeset state tracking (and it's
4067 * internal consistency). */
4068 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
4069 struct drm_connector_state *conn_state)
4071 struct intel_connector *connector = to_intel_connector(conn_state->connector);
4072 struct drm_i915_private *i915 = to_i915(connector->base.dev);
4074 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
4075 connector->base.base.id, connector->base.name);
4077 if (connector->get_hw_state(connector)) {
4078 struct intel_encoder *encoder = intel_attached_encoder(connector);
4080 I915_STATE_WARN(!crtc_state,
4081 "connector enabled without attached crtc\n");
4086 I915_STATE_WARN(!crtc_state->hw.active,
4087 "connector is active, but attached crtc isn't\n");
4089 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
4092 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
4093 "atomic encoder doesn't match attached encoder\n");
4095 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
4096 "attached encoder crtc differs from connector crtc\n");
4098 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
4099 "attached crtc is active, but connector isn't\n");
4100 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
4101 "best encoder set without crtc!\n");
4105 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
4107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4108 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4110 /* IPS only exists on ULT machines and is tied to pipe A. */
4111 if (!hsw_crtc_supports_ips(crtc))
4114 if (!dev_priv->params.enable_ips)
4117 if (crtc_state->pipe_bpp > 24)
4121 * We compare against max which means we must take
4122 * the increased cdclk requirement into account when
4123 * calculating the new cdclk.
4125 * Should measure whether using a lower cdclk w/o IPS
4127 if (IS_BROADWELL(dev_priv) &&
4128 crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
4134 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
4136 struct drm_i915_private *dev_priv =
4137 to_i915(crtc_state->uapi.crtc->dev);
4138 struct intel_atomic_state *state =
4139 to_intel_atomic_state(crtc_state->uapi.state);
4141 crtc_state->ips_enabled = false;
4143 if (!hsw_crtc_state_ips_capable(crtc_state))
4147 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4148 * enabled and disabled dynamically based on package C states,
4149 * user space can't make reliable use of the CRCs, so let's just
4150 * completely disable it.
4152 if (crtc_state->crc_enabled)
4155 /* IPS should be fine as long as at least one plane is enabled. */
4156 if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
4159 if (IS_BROADWELL(dev_priv)) {
4160 const struct intel_cdclk_state *cdclk_state;
4162 cdclk_state = intel_atomic_get_cdclk_state(state);
4163 if (IS_ERR(cdclk_state))
4164 return PTR_ERR(cdclk_state);
4166 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
4167 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
4171 crtc_state->ips_enabled = true;
4176 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
4178 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4180 /* GDG double wide on either pipe, otherwise pipe A only */
4181 return DISPLAY_VER(dev_priv) < 4 &&
4182 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
4185 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
4187 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
4188 struct drm_rect src;
4191 * We only use IF-ID interlacing. If we ever use
4192 * PF-ID we'll need to adjust the pixel_rate here.
4195 if (!crtc_state->pch_pfit.enabled)
4198 drm_rect_init(&src, 0, 0,
4199 crtc_state->pipe_src_w << 16,
4200 crtc_state->pipe_src_h << 16);
4202 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
4206 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
4207 const struct drm_display_mode *timings)
4209 mode->hdisplay = timings->crtc_hdisplay;
4210 mode->htotal = timings->crtc_htotal;
4211 mode->hsync_start = timings->crtc_hsync_start;
4212 mode->hsync_end = timings->crtc_hsync_end;
4214 mode->vdisplay = timings->crtc_vdisplay;
4215 mode->vtotal = timings->crtc_vtotal;
4216 mode->vsync_start = timings->crtc_vsync_start;
4217 mode->vsync_end = timings->crtc_vsync_end;
4219 mode->flags = timings->flags;
4220 mode->type = DRM_MODE_TYPE_DRIVER;
4222 mode->clock = timings->crtc_clock;
4224 drm_mode_set_name(mode);
4227 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
4229 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4231 if (HAS_GMCH(dev_priv))
4232 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
4233 crtc_state->pixel_rate =
4234 crtc_state->hw.pipe_mode.crtc_clock;
4236 crtc_state->pixel_rate =
4237 ilk_pipe_pixel_rate(crtc_state);
4240 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
4242 struct drm_display_mode *mode = &crtc_state->hw.mode;
4243 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4244 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4246 drm_mode_copy(pipe_mode, adjusted_mode);
4248 if (crtc_state->bigjoiner) {
4250 * transcoder is programmed to the full mode,
4251 * but pipe timings are half of the transcoder mode
4253 pipe_mode->crtc_hdisplay /= 2;
4254 pipe_mode->crtc_hblank_start /= 2;
4255 pipe_mode->crtc_hblank_end /= 2;
4256 pipe_mode->crtc_hsync_start /= 2;
4257 pipe_mode->crtc_hsync_end /= 2;
4258 pipe_mode->crtc_htotal /= 2;
4259 pipe_mode->crtc_clock /= 2;
4262 if (crtc_state->splitter.enable) {
4263 int n = crtc_state->splitter.link_count;
4264 int overlap = crtc_state->splitter.pixel_overlap;
4267 * eDP MSO uses segment timings from EDID for transcoder
4268 * timings, but full mode for everything else.
4270 * h_full = (h_segment - pixel_overlap) * link_count
4272 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4273 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4274 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4275 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4276 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4277 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4278 pipe_mode->crtc_clock *= n;
4280 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4281 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
4283 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4284 intel_mode_from_crtc_timings(adjusted_mode, adjusted_mode);
4287 intel_crtc_compute_pixel_rate(crtc_state);
4289 drm_mode_copy(mode, adjusted_mode);
4290 mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner;
4291 mode->vdisplay = crtc_state->pipe_src_h;
4294 static void intel_encoder_get_config(struct intel_encoder *encoder,
4295 struct intel_crtc_state *crtc_state)
4297 encoder->get_config(encoder, crtc_state);
4299 intel_crtc_readout_derived_state(crtc_state);
4302 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4303 struct intel_crtc_state *pipe_config)
4305 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4306 struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
4307 int clock_limit = dev_priv->max_dotclk_freq;
4309 drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
4311 /* Adjust pipe_mode for bigjoiner, with half the horizontal mode */
4312 if (pipe_config->bigjoiner) {
4313 pipe_mode->crtc_clock /= 2;
4314 pipe_mode->crtc_hdisplay /= 2;
4315 pipe_mode->crtc_hblank_start /= 2;
4316 pipe_mode->crtc_hblank_end /= 2;
4317 pipe_mode->crtc_hsync_start /= 2;
4318 pipe_mode->crtc_hsync_end /= 2;
4319 pipe_mode->crtc_htotal /= 2;
4320 pipe_config->pipe_src_w /= 2;
4323 if (pipe_config->splitter.enable) {
4324 int n = pipe_config->splitter.link_count;
4325 int overlap = pipe_config->splitter.pixel_overlap;
4327 pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) * n;
4328 pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - overlap) * n;
4329 pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - overlap) * n;
4330 pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - overlap) * n;
4331 pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - overlap) * n;
4332 pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n;
4333 pipe_mode->crtc_clock *= n;
4336 intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
4338 if (DISPLAY_VER(dev_priv) < 4) {
4339 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
4342 * Enable double wide mode when the dot clock
4343 * is > 90% of the (display) core speed.
4345 if (intel_crtc_supports_double_wide(crtc) &&
4346 pipe_mode->crtc_clock > clock_limit) {
4347 clock_limit = dev_priv->max_dotclk_freq;
4348 pipe_config->double_wide = true;
4352 if (pipe_mode->crtc_clock > clock_limit) {
4353 drm_dbg_kms(&dev_priv->drm,
4354 "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
4355 pipe_mode->crtc_clock, clock_limit,
4356 yesno(pipe_config->double_wide));
4361 * Pipe horizontal size must be even in:
4363 * - LVDS dual channel mode
4364 * - Double wide pipe
4366 if (pipe_config->pipe_src_w & 1) {
4367 if (pipe_config->double_wide) {
4368 drm_dbg_kms(&dev_priv->drm,
4369 "Odd pipe source width not supported with double wide pipe\n");
4373 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
4374 intel_is_dual_link_lvds(dev_priv)) {
4375 drm_dbg_kms(&dev_priv->drm,
4376 "Odd pipe source width not supported with dual link LVDS\n");
4381 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4382 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4384 if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
4385 pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
4388 intel_crtc_compute_pixel_rate(pipe_config);
4390 if (pipe_config->has_pch_encoder)
4391 return ilk_fdi_compute_config(crtc, pipe_config);
4397 intel_reduce_m_n_ratio(u32 *num, u32 *den)
4399 while (*num > DATA_LINK_M_N_MASK ||
4400 *den > DATA_LINK_M_N_MASK) {
4406 static void compute_m_n(unsigned int m, unsigned int n,
4407 u32 *ret_m, u32 *ret_n,
4411 * Several DP dongles in particular seem to be fussy about
4412 * too large link M/N values. Give N value as 0x8000 that
4413 * should be acceptable by specific devices. 0x8000 is the
4414 * specified fixed N value for asynchronous clock mode,
4415 * which the devices expect also in synchronous clock mode.
4418 *ret_n = DP_LINK_CONSTANT_N_VALUE;
4420 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4422 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
4423 intel_reduce_m_n_ratio(ret_m, ret_n);
4427 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
4428 int pixel_clock, int link_clock,
4429 struct intel_link_m_n *m_n,
4430 bool constant_n, bool fec_enable)
4432 u32 data_clock = bits_per_pixel * pixel_clock;
4435 data_clock = intel_dp_mode_to_fec_clock(data_clock);
4438 compute_m_n(data_clock,
4439 link_clock * nlanes * 8,
4440 &m_n->gmch_m, &m_n->gmch_n,
4443 compute_m_n(pixel_clock, link_clock,
4444 &m_n->link_m, &m_n->link_n,
4448 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
4451 * There may be no VBT; and if the BIOS enabled SSC we can
4452 * just keep using it to avoid unnecessary flicker. Whereas if the
4453 * BIOS isn't using it, don't assume it will work even if the VBT
4454 * indicates as much.
4456 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
4457 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
4461 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
4462 drm_dbg_kms(&dev_priv->drm,
4463 "SSC %s by BIOS, overriding VBT which says %s\n",
4464 enableddisabled(bios_lvds_use_ssc),
4465 enableddisabled(dev_priv->vbt.lvds_use_ssc));
4466 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
4471 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
4472 const struct intel_link_m_n *m_n)
4474 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4475 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4476 enum pipe pipe = crtc->pipe;
4478 intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
4479 TU_SIZE(m_n->tu) | m_n->gmch_m);
4480 intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4481 intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4482 intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4485 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
4486 enum transcoder transcoder)
4488 if (IS_HASWELL(dev_priv))
4489 return transcoder == TRANSCODER_EDP;
4492 * Strictly speaking some registers are available before
4493 * gen7, but we only support DRRS on gen7+
4495 return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
4498 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
4499 const struct intel_link_m_n *m_n,
4500 const struct intel_link_m_n *m2_n2)
4502 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4503 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4504 enum pipe pipe = crtc->pipe;
4505 enum transcoder transcoder = crtc_state->cpu_transcoder;
4507 if (DISPLAY_VER(dev_priv) >= 5) {
4508 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
4509 TU_SIZE(m_n->tu) | m_n->gmch_m);
4510 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
4512 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
4514 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
4517 * M2_N2 registers are set only if DRRS is supported
4518 * (to make sure the registers are not unnecessarily accessed).
4520 if (m2_n2 && crtc_state->has_drrs &&
4521 transcoder_has_m2_n2(dev_priv, transcoder)) {
4522 intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
4523 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
4524 intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
4526 intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
4528 intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
4532 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
4533 TU_SIZE(m_n->tu) | m_n->gmch_m);
4534 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4535 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
4536 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
4540 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
4542 const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
4543 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4546 dp_m_n = &crtc_state->dp_m_n;
4547 dp_m2_n2 = &crtc_state->dp_m2_n2;
4548 } else if (m_n == M2_N2) {
4551 * M2_N2 registers are not supported. Hence m2_n2 divider value
4552 * needs to be programmed into M1_N1.
4554 dp_m_n = &crtc_state->dp_m2_n2;
4556 drm_err(&i915->drm, "Unsupported divider value\n");
4560 if (crtc_state->has_pch_encoder)
4561 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
4563 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
4566 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
4568 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4569 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4570 enum pipe pipe = crtc->pipe;
4571 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4572 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
4573 u32 crtc_vtotal, crtc_vblank_end;
4576 /* We need to be careful not to changed the adjusted mode, for otherwise
4577 * the hw state checker will get angry at the mismatch. */
4578 crtc_vtotal = adjusted_mode->crtc_vtotal;
4579 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4581 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4582 /* the chip adds 2 halflines automatically */
4584 crtc_vblank_end -= 1;
4586 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
4587 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
4589 vsyncshift = adjusted_mode->crtc_hsync_start -
4590 adjusted_mode->crtc_htotal / 2;
4592 vsyncshift += adjusted_mode->crtc_htotal;
4595 if (DISPLAY_VER(dev_priv) > 3)
4596 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
4599 intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
4600 (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
4601 intel_de_write(dev_priv, HBLANK(cpu_transcoder),
4602 (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
4603 intel_de_write(dev_priv, HSYNC(cpu_transcoder),
4604 (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
4606 intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
4607 (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
4608 intel_de_write(dev_priv, VBLANK(cpu_transcoder),
4609 (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
4610 intel_de_write(dev_priv, VSYNC(cpu_transcoder),
4611 (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
4613 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4614 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4615 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4617 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
4618 (pipe == PIPE_B || pipe == PIPE_C))
4619 intel_de_write(dev_priv, VTOTAL(pipe),
4620 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
4624 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
4626 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4627 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4628 enum pipe pipe = crtc->pipe;
4630 /* pipesrc controls the size that is scaled from, which should
4631 * always be the user's requested size.
4633 intel_de_write(dev_priv, PIPESRC(pipe),
4634 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
4637 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
4639 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4640 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4642 if (DISPLAY_VER(dev_priv) == 2)
4645 if (DISPLAY_VER(dev_priv) >= 9 ||
4646 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4647 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
4649 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
4652 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
4653 struct intel_crtc_state *pipe_config)
4655 struct drm_device *dev = crtc->base.dev;
4656 struct drm_i915_private *dev_priv = to_i915(dev);
4657 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4660 tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
4661 pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4662 pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4664 if (!transcoder_is_dsi(cpu_transcoder)) {
4665 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
4666 pipe_config->hw.adjusted_mode.crtc_hblank_start =
4668 pipe_config->hw.adjusted_mode.crtc_hblank_end =
4669 ((tmp >> 16) & 0xffff) + 1;
4671 tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
4672 pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4673 pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4675 tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
4676 pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4677 pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4679 if (!transcoder_is_dsi(cpu_transcoder)) {
4680 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
4681 pipe_config->hw.adjusted_mode.crtc_vblank_start =
4683 pipe_config->hw.adjusted_mode.crtc_vblank_end =
4684 ((tmp >> 16) & 0xffff) + 1;
4686 tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
4687 pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4688 pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4690 if (intel_pipe_is_interlaced(pipe_config)) {
4691 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4692 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
4693 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
4697 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
4698 struct intel_crtc_state *pipe_config)
4700 struct drm_device *dev = crtc->base.dev;
4701 struct drm_i915_private *dev_priv = to_i915(dev);
4704 tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
4705 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4706 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4709 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
4711 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4712 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4717 /* we keep both pipes enabled on 830 */
4718 if (IS_I830(dev_priv))
4719 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
4721 if (crtc_state->double_wide)
4722 pipeconf |= PIPECONF_DOUBLE_WIDE;
4724 /* only g4x and later have fancy bpc/dither controls */
4725 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4726 IS_CHERRYVIEW(dev_priv)) {
4727 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4728 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
4729 pipeconf |= PIPECONF_DITHER_EN |
4730 PIPECONF_DITHER_TYPE_SP;
4732 switch (crtc_state->pipe_bpp) {
4734 pipeconf |= PIPECONF_6BPC;
4737 pipeconf |= PIPECONF_8BPC;
4740 pipeconf |= PIPECONF_10BPC;
4743 /* Case prevented by intel_choose_pipe_bpp_dither. */
4748 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
4749 if (DISPLAY_VER(dev_priv) < 4 ||
4750 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
4751 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4753 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
4755 pipeconf |= PIPECONF_PROGRESSIVE;
4758 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
4759 crtc_state->limited_color_range)
4760 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4762 pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
4764 pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
4766 intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
4767 intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
4770 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
4772 if (IS_I830(dev_priv))
4775 return DISPLAY_VER(dev_priv) >= 4 ||
4776 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
4779 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
4781 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4782 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4785 if (!i9xx_has_pfit(dev_priv))
4788 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
4789 if (!(tmp & PFIT_ENABLE))
4792 /* Check whether the pfit is attached to our pipe. */
4793 if (DISPLAY_VER(dev_priv) < 4) {
4794 if (crtc->pipe != PIPE_B)
4797 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4801 crtc_state->gmch_pfit.control = tmp;
4802 crtc_state->gmch_pfit.pgm_ratios =
4803 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
4806 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
4807 struct intel_crtc_state *pipe_config)
4809 struct drm_device *dev = crtc->base.dev;
4810 struct drm_i915_private *dev_priv = to_i915(dev);
4811 enum pipe pipe = crtc->pipe;
4814 int refclk = 100000;
4816 /* In case of DSI, DPLL will not be used */
4817 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
4820 vlv_dpio_get(dev_priv);
4821 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
4822 vlv_dpio_put(dev_priv);
4824 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
4825 clock.m2 = mdiv & DPIO_M2DIV_MASK;
4826 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
4827 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
4828 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
4830 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
4833 static void chv_crtc_clock_get(struct intel_crtc *crtc,
4834 struct intel_crtc_state *pipe_config)
4836 struct drm_device *dev = crtc->base.dev;
4837 struct drm_i915_private *dev_priv = to_i915(dev);
4838 enum pipe pipe = crtc->pipe;
4839 enum dpio_channel port = vlv_pipe_to_channel(pipe);
4841 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
4842 int refclk = 100000;
4844 /* In case of DSI, DPLL will not be used */
4845 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
4848 vlv_dpio_get(dev_priv);
4849 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
4850 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
4851 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
4852 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
4853 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
4854 vlv_dpio_put(dev_priv);
4856 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
4857 clock.m2 = (pll_dw0 & 0xff) << 22;
4858 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
4859 clock.m2 |= pll_dw2 & 0x3fffff;
4860 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
4861 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
4862 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
4864 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
4867 static enum intel_output_format
4868 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
4870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4873 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
4875 if (tmp & PIPEMISC_YUV420_ENABLE) {
4876 /* We support 4:2:0 in full blend mode only */
4877 drm_WARN_ON(&dev_priv->drm,
4878 (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
4880 return INTEL_OUTPUT_FORMAT_YCBCR420;
4881 } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
4882 return INTEL_OUTPUT_FORMAT_YCBCR444;
4884 return INTEL_OUTPUT_FORMAT_RGB;
4888 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
4890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4891 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
4892 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4893 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4896 tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4898 if (tmp & DISPPLANE_GAMMA_ENABLE)
4899 crtc_state->gamma_enable = true;
4901 if (!HAS_GMCH(dev_priv) &&
4902 tmp & DISPPLANE_PIPE_CSC_ENABLE)
4903 crtc_state->csc_enable = true;
4906 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4907 struct intel_crtc_state *pipe_config)
4909 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4910 enum intel_display_power_domain power_domain;
4911 intel_wakeref_t wakeref;
4915 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
4916 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4920 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
4921 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4922 pipe_config->shared_dpll = NULL;
4926 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
4927 if (!(tmp & PIPECONF_ENABLE))
4930 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4931 IS_CHERRYVIEW(dev_priv)) {
4932 switch (tmp & PIPECONF_BPC_MASK) {
4934 pipe_config->pipe_bpp = 18;
4937 pipe_config->pipe_bpp = 24;
4939 case PIPECONF_10BPC:
4940 pipe_config->pipe_bpp = 30;
4947 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
4948 (tmp & PIPECONF_COLOR_RANGE_SELECT))
4949 pipe_config->limited_color_range = true;
4951 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
4952 PIPECONF_GAMMA_MODE_SHIFT;
4954 if (IS_CHERRYVIEW(dev_priv))
4955 pipe_config->cgm_mode = intel_de_read(dev_priv,
4956 CGM_PIPE_MODE(crtc->pipe));
4958 i9xx_get_pipe_color_config(pipe_config);
4959 intel_color_get_config(pipe_config);
4961 if (DISPLAY_VER(dev_priv) < 4)
4962 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
4964 intel_get_transcoder_timings(crtc, pipe_config);
4965 intel_get_pipe_src_size(crtc, pipe_config);
4967 i9xx_get_pfit_config(pipe_config);
4969 if (DISPLAY_VER(dev_priv) >= 4) {
4970 /* No way to read it out on pipes B and C */
4971 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
4972 tmp = dev_priv->chv_dpll_md[crtc->pipe];
4974 tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
4975 pipe_config->pixel_multiplier =
4976 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4977 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4978 pipe_config->dpll_hw_state.dpll_md = tmp;
4979 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4980 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
4981 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
4982 pipe_config->pixel_multiplier =
4983 ((tmp & SDVO_MULTIPLIER_MASK)
4984 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4986 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4987 * port and will be fixed up in the encoder->get_config
4989 pipe_config->pixel_multiplier = 1;
4991 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
4993 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
4994 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
4996 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
4999 /* Mask out read-only status bits. */
5000 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5001 DPLL_PORTC_READY_MASK |
5002 DPLL_PORTB_READY_MASK);
5005 if (IS_CHERRYVIEW(dev_priv))
5006 chv_crtc_clock_get(crtc, pipe_config);
5007 else if (IS_VALLEYVIEW(dev_priv))
5008 vlv_crtc_clock_get(crtc, pipe_config);
5010 i9xx_crtc_clock_get(crtc, pipe_config);
5013 * Normally the dotclock is filled in by the encoder .get_config()
5014 * but in case the pipe is enabled w/o any ports we need a sane
5017 pipe_config->hw.adjusted_mode.crtc_clock =
5018 pipe_config->port_clock / pipe_config->pixel_multiplier;
5023 intel_display_power_put(dev_priv, power_domain, wakeref);
5028 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
5030 struct intel_encoder *encoder;
5033 bool has_lvds = false;
5034 bool has_cpu_edp = false;
5035 bool has_panel = false;
5036 bool has_ck505 = false;
5037 bool can_ssc = false;
5038 bool using_ssc_source = false;
5040 /* We need to take the global config into account */
5041 for_each_intel_encoder(&dev_priv->drm, encoder) {
5042 switch (encoder->type) {
5043 case INTEL_OUTPUT_LVDS:
5047 case INTEL_OUTPUT_EDP:
5049 if (encoder->port == PORT_A)
5057 if (HAS_PCH_IBX(dev_priv)) {
5058 has_ck505 = dev_priv->vbt.display_clock_mode;
5059 can_ssc = has_ck505;
5065 /* Check if any DPLLs are using the SSC source */
5066 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
5067 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
5069 if (!(temp & DPLL_VCO_ENABLE))
5072 if ((temp & PLL_REF_INPUT_MASK) ==
5073 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5074 using_ssc_source = true;
5079 drm_dbg_kms(&dev_priv->drm,
5080 "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
5081 has_panel, has_lvds, has_ck505, using_ssc_source);
5083 /* Ironlake: try to setup display ref clock before DPLL
5084 * enabling. This is only under driver's control after
5085 * PCH B stepping, previous chipset stepping should be
5086 * ignoring this setting.
5088 val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
5090 /* As we must carefully and slowly disable/enable each source in turn,
5091 * compute the final state we want first and check if we need to
5092 * make any changes at all.
5095 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5097 final |= DREF_NONSPREAD_CK505_ENABLE;
5099 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5101 final &= ~DREF_SSC_SOURCE_MASK;
5102 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5103 final &= ~DREF_SSC1_ENABLE;
5106 final |= DREF_SSC_SOURCE_ENABLE;
5108 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5109 final |= DREF_SSC1_ENABLE;
5112 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5113 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5115 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5117 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5118 } else if (using_ssc_source) {
5119 final |= DREF_SSC_SOURCE_ENABLE;
5120 final |= DREF_SSC1_ENABLE;
5126 /* Always enable nonspread source */
5127 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5130 val |= DREF_NONSPREAD_CK505_ENABLE;
5132 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5135 val &= ~DREF_SSC_SOURCE_MASK;
5136 val |= DREF_SSC_SOURCE_ENABLE;
5138 /* SSC must be turned on before enabling the CPU output */
5139 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5140 drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
5141 val |= DREF_SSC1_ENABLE;
5143 val &= ~DREF_SSC1_ENABLE;
5145 /* Get SSC going before enabling the outputs */
5146 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5147 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5150 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5152 /* Enable CPU source on CPU attached eDP */
5154 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5155 drm_dbg_kms(&dev_priv->drm,
5156 "Using SSC on eDP\n");
5157 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5159 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5161 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5163 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5164 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5167 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
5169 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5171 /* Turn off CPU output */
5172 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5174 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5175 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5178 if (!using_ssc_source) {
5179 drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
5181 /* Turn off the SSC source */
5182 val &= ~DREF_SSC_SOURCE_MASK;
5183 val |= DREF_SSC_SOURCE_DISABLE;
5186 val &= ~DREF_SSC1_ENABLE;
5188 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
5189 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
5194 BUG_ON(val != final);
5197 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5201 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5202 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5203 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5205 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5206 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5207 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
5209 tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
5210 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5211 intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
5213 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
5214 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5215 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
5218 /* WaMPhyProgramming:hsw */
5219 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5223 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5224 tmp &= ~(0xFF << 24);
5225 tmp |= (0x12 << 24);
5226 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5228 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5230 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5232 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5234 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5236 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5237 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5238 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5240 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5241 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5242 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5244 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5247 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5249 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5252 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5254 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5257 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5259 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5262 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5264 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5265 tmp &= ~(0xFF << 16);
5266 tmp |= (0x1C << 16);
5267 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5269 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5270 tmp &= ~(0xFF << 16);
5271 tmp |= (0x1C << 16);
5272 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5274 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5276 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5278 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5280 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5282 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5283 tmp &= ~(0xF << 28);
5285 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5287 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5288 tmp &= ~(0xF << 28);
5290 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5293 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5294 * Programming" based on the parameters passed:
5295 * - Sequence to enable CLKOUT_DP
5296 * - Sequence to enable CLKOUT_DP without spread
5297 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5299 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
5300 bool with_spread, bool with_fdi)
5304 if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
5305 "FDI requires downspread\n"))
5307 if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
5308 with_fdi, "LP PCH doesn't have FDI\n"))
5311 mutex_lock(&dev_priv->sb_lock);
5313 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5314 tmp &= ~SBI_SSCCTL_DISABLE;
5315 tmp |= SBI_SSCCTL_PATHALT;
5316 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5321 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5322 tmp &= ~SBI_SSCCTL_PATHALT;
5323 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5326 lpt_reset_fdi_mphy(dev_priv);
5327 lpt_program_fdi_mphy(dev_priv);
5331 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5332 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5333 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5334 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5336 mutex_unlock(&dev_priv->sb_lock);
5339 /* Sequence to disable CLKOUT_DP */
5340 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
5344 mutex_lock(&dev_priv->sb_lock);
5346 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
5347 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5348 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5349 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5351 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5352 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5353 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5354 tmp |= SBI_SSCCTL_PATHALT;
5355 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5358 tmp |= SBI_SSCCTL_DISABLE;
5359 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5362 mutex_unlock(&dev_priv->sb_lock);
5365 #define BEND_IDX(steps) ((50 + (steps)) / 5)
5367 static const u16 sscdivintphase[] = {
5368 [BEND_IDX( 50)] = 0x3B23,
5369 [BEND_IDX( 45)] = 0x3B23,
5370 [BEND_IDX( 40)] = 0x3C23,
5371 [BEND_IDX( 35)] = 0x3C23,
5372 [BEND_IDX( 30)] = 0x3D23,
5373 [BEND_IDX( 25)] = 0x3D23,
5374 [BEND_IDX( 20)] = 0x3E23,
5375 [BEND_IDX( 15)] = 0x3E23,
5376 [BEND_IDX( 10)] = 0x3F23,
5377 [BEND_IDX( 5)] = 0x3F23,
5378 [BEND_IDX( 0)] = 0x0025,
5379 [BEND_IDX( -5)] = 0x0025,
5380 [BEND_IDX(-10)] = 0x0125,
5381 [BEND_IDX(-15)] = 0x0125,
5382 [BEND_IDX(-20)] = 0x0225,
5383 [BEND_IDX(-25)] = 0x0225,
5384 [BEND_IDX(-30)] = 0x0325,
5385 [BEND_IDX(-35)] = 0x0325,
5386 [BEND_IDX(-40)] = 0x0425,
5387 [BEND_IDX(-45)] = 0x0425,
5388 [BEND_IDX(-50)] = 0x0525,
5393 * steps -50 to 50 inclusive, in steps of 5
5394 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
5395 * change in clock period = -(steps / 10) * 5.787 ps
5397 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
5400 int idx = BEND_IDX(steps);
5402 if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
5405 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
5408 mutex_lock(&dev_priv->sb_lock);
5410 if (steps % 10 != 0)
5414 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
5416 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
5418 tmp |= sscdivintphase[idx];
5419 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
5421 mutex_unlock(&dev_priv->sb_lock);
5426 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
5428 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
5429 u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
5431 if ((ctl & SPLL_PLL_ENABLE) == 0)
5434 if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
5435 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
5438 if (IS_BROADWELL(dev_priv) &&
5439 (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
5445 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
5446 enum intel_dpll_id id)
5448 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
5449 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
5451 if ((ctl & WRPLL_PLL_ENABLE) == 0)
5454 if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
5457 if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
5458 (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
5459 (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
5465 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
5467 struct intel_encoder *encoder;
5468 bool has_fdi = false;
5470 for_each_intel_encoder(&dev_priv->drm, encoder) {
5471 switch (encoder->type) {
5472 case INTEL_OUTPUT_ANALOG:
5481 * The BIOS may have decided to use the PCH SSC
5482 * reference so we must not disable it until the
5483 * relevant PLLs have stopped relying on it. We'll
5484 * just leave the PCH SSC reference enabled in case
5485 * any active PLL is using it. It will get disabled
5486 * after runtime suspend if we don't have FDI.
5488 * TODO: Move the whole reference clock handling
5489 * to the modeset sequence proper so that we can
5490 * actually enable/disable/reconfigure these things
5491 * safely. To do that we need to introduce a real
5492 * clock hierarchy. That would also allow us to do
5493 * clock bending finally.
5495 dev_priv->pch_ssc_use = 0;
5497 if (spll_uses_pch_ssc(dev_priv)) {
5498 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
5499 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
5502 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
5503 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
5504 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
5507 if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
5508 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
5509 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
5512 if (dev_priv->pch_ssc_use)
5516 lpt_bend_clkout_dp(dev_priv, 0);
5517 lpt_enable_clkout_dp(dev_priv, true, true);
5519 lpt_disable_clkout_dp(dev_priv);
5524 * Initialize reference clocks when the driver loads
5526 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
5528 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
5529 ilk_init_pch_refclk(dev_priv);
5530 else if (HAS_PCH_LPT(dev_priv))
5531 lpt_init_pch_refclk(dev_priv);
5534 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
5536 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5537 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5538 enum pipe pipe = crtc->pipe;
5543 switch (crtc_state->pipe_bpp) {
5545 val |= PIPECONF_6BPC;
5548 val |= PIPECONF_8BPC;
5551 val |= PIPECONF_10BPC;
5554 val |= PIPECONF_12BPC;
5557 /* Case prevented by intel_choose_pipe_bpp_dither. */
5561 if (crtc_state->dither)
5562 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5564 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5565 val |= PIPECONF_INTERLACED_ILK;
5567 val |= PIPECONF_PROGRESSIVE;
5570 * This would end up with an odd purple hue over
5571 * the entire display. Make sure we don't do it.
5573 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
5574 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
5576 if (crtc_state->limited_color_range &&
5577 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
5578 val |= PIPECONF_COLOR_RANGE_SELECT;
5580 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
5581 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
5583 val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
5585 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
5587 intel_de_write(dev_priv, PIPECONF(pipe), val);
5588 intel_de_posting_read(dev_priv, PIPECONF(pipe));
5591 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
5593 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5594 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5595 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5598 if (IS_HASWELL(dev_priv) && crtc_state->dither)
5599 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5601 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5602 val |= PIPECONF_INTERLACED_ILK;
5604 val |= PIPECONF_PROGRESSIVE;
5606 if (IS_HASWELL(dev_priv) &&
5607 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
5608 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
5610 intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
5611 intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
5614 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
5616 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5617 const struct intel_crtc_scaler_state *scaler_state =
5618 &crtc_state->scaler_state;
5620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5624 switch (crtc_state->pipe_bpp) {
5626 val |= PIPEMISC_6_BPC;
5629 val |= PIPEMISC_8_BPC;
5632 val |= PIPEMISC_10_BPC;
5635 /* Port output 12BPC defined for ADLP+ */
5636 if (DISPLAY_VER(dev_priv) > 12)
5637 val |= PIPEMISC_12_BPC_ADLP;
5640 MISSING_CASE(crtc_state->pipe_bpp);
5644 if (crtc_state->dither)
5645 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
5647 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
5648 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
5649 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
5651 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5652 val |= PIPEMISC_YUV420_ENABLE |
5653 PIPEMISC_YUV420_MODE_FULL_BLEND;
5655 if (DISPLAY_VER(dev_priv) >= 11 &&
5656 (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
5657 BIT(PLANE_CURSOR))) == 0)
5658 val |= PIPEMISC_HDR_MODE_PRECISION;
5660 if (DISPLAY_VER(dev_priv) >= 12)
5661 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
5663 if (IS_ALDERLAKE_P(dev_priv)) {
5664 bool scaler_in_use = false;
5666 for (i = 0; i < crtc->num_scalers; i++) {
5667 if (!scaler_state->scalers[i].in_use)
5670 scaler_in_use = true;
5674 intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
5675 PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
5676 scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
5677 PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
5680 intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
5683 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
5685 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5688 tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
5690 switch (tmp & PIPEMISC_BPC_MASK) {
5691 case PIPEMISC_6_BPC:
5693 case PIPEMISC_8_BPC:
5695 case PIPEMISC_10_BPC:
5698 * PORT OUTPUT 12 BPC defined for ADLP+.
5701 * For previous platforms with DSI interface, bits 5:7
5702 * are used for storing pipe_bpp irrespective of dithering.
5703 * Since the value of 12 BPC is not defined for these bits
5704 * on older platforms, need to find a workaround for 12 BPC
5705 * MIPI DSI HW readout.
5707 case PIPEMISC_12_BPC_ADLP:
5708 if (DISPLAY_VER(dev_priv) > 12)
5717 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
5720 * Account for spread spectrum to avoid
5721 * oversubscribing the link. Max center spread
5722 * is 2.5%; use 5% for safety's sake.
5724 u32 bps = target_clock * bpp * 21 / 20;
5725 return DIV_ROUND_UP(bps, link_bw * 8);
5728 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5729 struct intel_link_m_n *m_n)
5731 struct drm_device *dev = crtc->base.dev;
5732 struct drm_i915_private *dev_priv = to_i915(dev);
5733 enum pipe pipe = crtc->pipe;
5735 m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
5736 m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
5737 m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
5739 m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
5740 m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
5741 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5744 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5745 enum transcoder transcoder,
5746 struct intel_link_m_n *m_n,
5747 struct intel_link_m_n *m2_n2)
5749 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5750 enum pipe pipe = crtc->pipe;
5752 if (DISPLAY_VER(dev_priv) >= 5) {
5753 m_n->link_m = intel_de_read(dev_priv,
5754 PIPE_LINK_M1(transcoder));
5755 m_n->link_n = intel_de_read(dev_priv,
5756 PIPE_LINK_N1(transcoder));
5757 m_n->gmch_m = intel_de_read(dev_priv,
5758 PIPE_DATA_M1(transcoder))
5760 m_n->gmch_n = intel_de_read(dev_priv,
5761 PIPE_DATA_N1(transcoder));
5762 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
5763 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5765 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
5766 m2_n2->link_m = intel_de_read(dev_priv,
5767 PIPE_LINK_M2(transcoder));
5768 m2_n2->link_n = intel_de_read(dev_priv,
5769 PIPE_LINK_N2(transcoder));
5770 m2_n2->gmch_m = intel_de_read(dev_priv,
5771 PIPE_DATA_M2(transcoder))
5773 m2_n2->gmch_n = intel_de_read(dev_priv,
5774 PIPE_DATA_N2(transcoder));
5775 m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
5776 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5779 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
5780 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
5781 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
5783 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
5784 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
5785 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5789 void intel_dp_get_m_n(struct intel_crtc *crtc,
5790 struct intel_crtc_state *pipe_config)
5792 if (pipe_config->has_pch_encoder)
5793 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5795 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5796 &pipe_config->dp_m_n,
5797 &pipe_config->dp_m2_n2);
5800 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
5801 struct intel_crtc_state *pipe_config)
5803 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5804 &pipe_config->fdi_m_n, NULL);
5807 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
5810 drm_rect_init(&crtc_state->pch_pfit.dst,
5811 pos >> 16, pos & 0xffff,
5812 size >> 16, size & 0xffff);
5815 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
5817 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5818 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5819 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
5823 /* find scaler attached to this pipe */
5824 for (i = 0; i < crtc->num_scalers; i++) {
5827 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
5828 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
5832 crtc_state->pch_pfit.enabled = true;
5834 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
5835 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
5837 ilk_get_pfit_pos_size(crtc_state, pos, size);
5839 scaler_state->scalers[i].in_use = true;
5843 scaler_state->scaler_id = id;
5845 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
5847 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
5850 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
5852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5856 ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
5857 if ((ctl & PF_ENABLE) == 0)
5860 crtc_state->pch_pfit.enabled = true;
5862 pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
5863 size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
5865 ilk_get_pfit_pos_size(crtc_state, pos, size);
5868 * We currently do not free assignements of panel fitters on
5869 * ivb/hsw (since we don't use the higher upscaling modes which
5870 * differentiates them) so just WARN about this case for now.
5872 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
5873 (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
5876 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
5877 struct intel_crtc_state *pipe_config)
5879 struct drm_device *dev = crtc->base.dev;
5880 struct drm_i915_private *dev_priv = to_i915(dev);
5881 enum intel_display_power_domain power_domain;
5882 intel_wakeref_t wakeref;
5886 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
5887 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
5891 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5892 pipe_config->shared_dpll = NULL;
5895 tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
5896 if (!(tmp & PIPECONF_ENABLE))
5899 switch (tmp & PIPECONF_BPC_MASK) {
5901 pipe_config->pipe_bpp = 18;
5904 pipe_config->pipe_bpp = 24;
5906 case PIPECONF_10BPC:
5907 pipe_config->pipe_bpp = 30;
5909 case PIPECONF_12BPC:
5910 pipe_config->pipe_bpp = 36;
5916 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
5917 pipe_config->limited_color_range = true;
5919 switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
5920 case PIPECONF_OUTPUT_COLORSPACE_YUV601:
5921 case PIPECONF_OUTPUT_COLORSPACE_YUV709:
5922 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
5925 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
5929 pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
5930 PIPECONF_GAMMA_MODE_SHIFT;
5932 pipe_config->csc_mode = intel_de_read(dev_priv,
5933 PIPE_CSC_MODE(crtc->pipe));
5935 i9xx_get_pipe_color_config(pipe_config);
5936 intel_color_get_config(pipe_config);
5938 if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5939 struct intel_shared_dpll *pll;
5940 enum intel_dpll_id pll_id;
5943 pipe_config->has_pch_encoder = true;
5945 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
5946 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5947 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5949 ilk_get_fdi_m_n_config(crtc, pipe_config);
5951 if (HAS_PCH_IBX(dev_priv)) {
5953 * The pipe->pch transcoder and pch transcoder->pll
5956 pll_id = (enum intel_dpll_id) crtc->pipe;
5958 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5959 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5960 pll_id = DPLL_ID_PCH_PLL_B;
5962 pll_id= DPLL_ID_PCH_PLL_A;
5965 pipe_config->shared_dpll =
5966 intel_get_shared_dpll_by_id(dev_priv, pll_id);
5967 pll = pipe_config->shared_dpll;
5969 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
5970 &pipe_config->dpll_hw_state);
5971 drm_WARN_ON(dev, !pll_active);
5973 tmp = pipe_config->dpll_hw_state.dpll;
5974 pipe_config->pixel_multiplier =
5975 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5976 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5978 ilk_pch_clock_get(crtc, pipe_config);
5980 pipe_config->pixel_multiplier = 1;
5983 intel_get_transcoder_timings(crtc, pipe_config);
5984 intel_get_pipe_src_size(crtc, pipe_config);
5986 ilk_get_pfit_config(pipe_config);
5991 intel_display_power_put(dev_priv, power_domain, wakeref);
5996 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
5997 struct intel_crtc_state *pipe_config,
5998 struct intel_display_power_domain_set *power_domain_set)
6000 struct drm_device *dev = crtc->base.dev;
6001 struct drm_i915_private *dev_priv = to_i915(dev);
6002 unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP);
6003 unsigned long enabled_panel_transcoders = 0;
6004 enum transcoder panel_transcoder;
6007 if (DISPLAY_VER(dev_priv) >= 11)
6008 panel_transcoder_mask |=
6009 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
6012 * The pipe->transcoder mapping is fixed with the exception of the eDP
6013 * and DSI transcoders handled below.
6015 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6018 * XXX: Do intel_display_power_get_if_enabled before reading this (for
6019 * consistency and less surprising code; it's in always on power).
6021 for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,
6022 panel_transcoder_mask) {
6023 bool force_thru = false;
6024 enum pipe trans_pipe;
6026 tmp = intel_de_read(dev_priv,
6027 TRANS_DDI_FUNC_CTL(panel_transcoder));
6028 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6032 * Log all enabled ones, only use the first one.
6034 * FIXME: This won't work for two separate DSI displays.
6036 enabled_panel_transcoders |= BIT(panel_transcoder);
6037 if (enabled_panel_transcoders != BIT(panel_transcoder))
6040 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6043 "unknown pipe linked to transcoder %s\n",
6044 transcoder_name(panel_transcoder));
6046 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6049 case TRANS_DDI_EDP_INPUT_A_ON:
6050 trans_pipe = PIPE_A;
6052 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6053 trans_pipe = PIPE_B;
6055 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6056 trans_pipe = PIPE_C;
6058 case TRANS_DDI_EDP_INPUT_D_ONOFF:
6059 trans_pipe = PIPE_D;
6063 if (trans_pipe == crtc->pipe) {
6064 pipe_config->cpu_transcoder = panel_transcoder;
6065 pipe_config->pch_pfit.force_thru = force_thru;
6070 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
6072 drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
6073 enabled_panel_transcoders != BIT(TRANSCODER_EDP));
6075 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6076 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6079 tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
6081 return tmp & PIPECONF_ENABLE;
6084 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
6085 struct intel_crtc_state *pipe_config,
6086 struct intel_display_power_domain_set *power_domain_set)
6088 struct drm_device *dev = crtc->base.dev;
6089 struct drm_i915_private *dev_priv = to_i915(dev);
6090 enum transcoder cpu_transcoder;
6094 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
6096 cpu_transcoder = TRANSCODER_DSI_A;
6098 cpu_transcoder = TRANSCODER_DSI_C;
6100 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
6101 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6105 * The PLL needs to be enabled with a valid divider
6106 * configuration, otherwise accessing DSI registers will hang
6107 * the machine. See BSpec North Display Engine
6108 * registers/MIPI[BXT]. We can break out here early, since we
6109 * need the same DSI PLL to be enabled for both DSI ports.
6111 if (!bxt_dsi_pll_is_enabled(dev_priv))
6114 /* XXX: this works for video mode only */
6115 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
6116 if (!(tmp & DPI_ENABLE))
6119 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
6120 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
6123 pipe_config->cpu_transcoder = cpu_transcoder;
6127 return transcoder_is_dsi(pipe_config->cpu_transcoder);
6130 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
6131 struct intel_crtc_state *pipe_config)
6133 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6134 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6138 if (transcoder_is_dsi(cpu_transcoder)) {
6139 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
6142 tmp = intel_de_read(dev_priv,
6143 TRANS_DDI_FUNC_CTL(cpu_transcoder));
6144 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
6146 if (DISPLAY_VER(dev_priv) >= 12)
6147 port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6149 port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
6153 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6154 * DDI E. So just check whether this pipe is wired to DDI E and whether
6155 * the PCH transcoder is on.
6157 if (DISPLAY_VER(dev_priv) < 9 &&
6158 (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
6159 pipe_config->has_pch_encoder = true;
6161 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
6162 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6163 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6165 ilk_get_fdi_m_n_config(crtc, pipe_config);
6169 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
6170 struct intel_crtc_state *pipe_config)
6172 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6173 struct intel_display_power_domain_set power_domain_set = { };
6177 if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6178 POWER_DOMAIN_PIPE(crtc->pipe)))
6181 pipe_config->shared_dpll = NULL;
6183 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
6185 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
6186 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
6187 drm_WARN_ON(&dev_priv->drm, active);
6191 intel_dsc_get_config(pipe_config);
6192 if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config->dsc.compression_enable)
6193 intel_uncompressed_joiner_get_config(pipe_config);
6196 /* bigjoiner slave doesn't enable transcoder */
6197 if (!pipe_config->bigjoiner_slave)
6201 pipe_config->pixel_multiplier = 1;
6203 /* we cannot read out most state, so don't bother.. */
6204 pipe_config->quirks |= PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE;
6205 } else if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
6206 DISPLAY_VER(dev_priv) >= 11) {
6207 hsw_get_ddi_port_state(crtc, pipe_config);
6208 intel_get_transcoder_timings(crtc, pipe_config);
6211 if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
6212 intel_vrr_get_config(crtc, pipe_config);
6214 intel_get_pipe_src_size(crtc, pipe_config);
6216 if (IS_HASWELL(dev_priv)) {
6217 u32 tmp = intel_de_read(dev_priv,
6218 PIPECONF(pipe_config->cpu_transcoder));
6220 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
6221 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
6223 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
6225 pipe_config->output_format =
6226 bdw_get_pipemisc_output_format(crtc);
6229 pipe_config->gamma_mode = intel_de_read(dev_priv,
6230 GAMMA_MODE(crtc->pipe));
6232 pipe_config->csc_mode = intel_de_read(dev_priv,
6233 PIPE_CSC_MODE(crtc->pipe));
6235 if (DISPLAY_VER(dev_priv) >= 9) {
6236 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
6238 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
6239 pipe_config->gamma_enable = true;
6241 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
6242 pipe_config->csc_enable = true;
6244 i9xx_get_pipe_color_config(pipe_config);
6247 intel_color_get_config(pipe_config);
6249 tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
6250 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
6251 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6252 pipe_config->ips_linetime =
6253 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
6255 if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
6256 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
6257 if (DISPLAY_VER(dev_priv) >= 9)
6258 skl_get_pfit_config(pipe_config);
6260 ilk_get_pfit_config(pipe_config);
6263 if (hsw_crtc_supports_ips(crtc)) {
6264 if (IS_HASWELL(dev_priv))
6265 pipe_config->ips_enabled = intel_de_read(dev_priv,
6266 IPS_CTL) & IPS_ENABLE;
6269 * We cannot readout IPS state on broadwell, set to
6270 * true so we can set it to a defined state on first
6273 pipe_config->ips_enabled = true;
6277 if (pipe_config->bigjoiner_slave) {
6278 /* Cannot be read out as a slave, set to 0. */
6279 pipe_config->pixel_multiplier = 0;
6280 } else if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
6281 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
6282 pipe_config->pixel_multiplier =
6283 intel_de_read(dev_priv,
6284 PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
6286 pipe_config->pixel_multiplier = 1;
6290 intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
6295 static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
6297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6298 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6300 if (!i915->display.get_pipe_config(crtc, crtc_state))
6303 crtc_state->hw.active = true;
6305 intel_crtc_readout_derived_state(crtc_state);
6310 /* VESA 640x480x72Hz mode to set on the pipe */
6311 static const struct drm_display_mode load_detect_mode = {
6312 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6313 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6316 struct drm_framebuffer *
6317 intel_framebuffer_create(struct drm_i915_gem_object *obj,
6318 struct drm_mode_fb_cmd2 *mode_cmd)
6320 struct intel_framebuffer *intel_fb;
6323 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6325 return ERR_PTR(-ENOMEM);
6327 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
6331 return &intel_fb->base;
6335 return ERR_PTR(ret);
6338 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
6339 struct drm_crtc *crtc)
6341 struct drm_plane *plane;
6342 struct drm_plane_state *plane_state;
6345 ret = drm_atomic_add_affected_planes(state, crtc);
6349 for_each_new_plane_in_state(state, plane, plane_state, i) {
6350 if (plane_state->crtc != crtc)
6353 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
6357 drm_atomic_set_fb_for_plane(plane_state, NULL);
6363 int intel_get_load_detect_pipe(struct drm_connector *connector,
6364 struct intel_load_detect_pipe *old,
6365 struct drm_modeset_acquire_ctx *ctx)
6367 struct intel_encoder *encoder =
6368 intel_attached_encoder(to_intel_connector(connector));
6369 struct intel_crtc *possible_crtc;
6370 struct intel_crtc *crtc = NULL;
6371 struct drm_device *dev = encoder->base.dev;
6372 struct drm_i915_private *dev_priv = to_i915(dev);
6373 struct drm_mode_config *config = &dev->mode_config;
6374 struct drm_atomic_state *state = NULL, *restore_state = NULL;
6375 struct drm_connector_state *connector_state;
6376 struct intel_crtc_state *crtc_state;
6379 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6380 connector->base.id, connector->name,
6381 encoder->base.base.id, encoder->base.name);
6383 old->restore_state = NULL;
6385 drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
6388 * Algorithm gets a little messy:
6390 * - if the connector already has an assigned crtc, use it (but make
6391 * sure it's on first)
6393 * - try to find the first unused crtc that can drive this connector,
6394 * and use that if we find one
6397 /* See if we already have a CRTC for this connector */
6398 if (connector->state->crtc) {
6399 crtc = to_intel_crtc(connector->state->crtc);
6401 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6405 /* Make sure the crtc and connector are running */
6409 /* Find an unused one (if possible) */
6410 for_each_intel_crtc(dev, possible_crtc) {
6411 if (!(encoder->base.possible_crtcs &
6412 drm_crtc_mask(&possible_crtc->base)))
6415 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
6419 if (possible_crtc->base.state->enable) {
6420 drm_modeset_unlock(&possible_crtc->base.mutex);
6424 crtc = possible_crtc;
6429 * If we didn't find an unused CRTC, don't use any.
6432 drm_dbg_kms(&dev_priv->drm,
6433 "no pipe available for load-detect\n");
6439 state = drm_atomic_state_alloc(dev);
6440 restore_state = drm_atomic_state_alloc(dev);
6441 if (!state || !restore_state) {
6446 state->acquire_ctx = ctx;
6447 restore_state->acquire_ctx = ctx;
6449 connector_state = drm_atomic_get_connector_state(state, connector);
6450 if (IS_ERR(connector_state)) {
6451 ret = PTR_ERR(connector_state);
6455 ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
6459 crtc_state = intel_atomic_get_crtc_state(state, crtc);
6460 if (IS_ERR(crtc_state)) {
6461 ret = PTR_ERR(crtc_state);
6465 crtc_state->uapi.active = true;
6467 ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
6472 ret = intel_modeset_disable_planes(state, &crtc->base);
6476 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
6478 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));
6480 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
6482 drm_dbg_kms(&dev_priv->drm,
6483 "Failed to create a copy of old state to restore: %i\n",
6488 ret = drm_atomic_commit(state);
6490 drm_dbg_kms(&dev_priv->drm,
6491 "failed to set mode on load-detect pipe\n");
6495 old->restore_state = restore_state;
6496 drm_atomic_state_put(state);
6498 /* let the connector get through one full cycle before testing */
6499 intel_wait_for_vblank(dev_priv, crtc->pipe);
6504 drm_atomic_state_put(state);
6507 if (restore_state) {
6508 drm_atomic_state_put(restore_state);
6509 restore_state = NULL;
6512 if (ret == -EDEADLK)
6518 void intel_release_load_detect_pipe(struct drm_connector *connector,
6519 struct intel_load_detect_pipe *old,
6520 struct drm_modeset_acquire_ctx *ctx)
6522 struct intel_encoder *intel_encoder =
6523 intel_attached_encoder(to_intel_connector(connector));
6524 struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
6525 struct drm_encoder *encoder = &intel_encoder->base;
6526 struct drm_atomic_state *state = old->restore_state;
6529 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6530 connector->base.id, connector->name,
6531 encoder->base.id, encoder->name);
6536 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
6538 drm_dbg_kms(&i915->drm,
6539 "Couldn't release load detect pipe: %i\n", ret);
6540 drm_atomic_state_put(state);
6543 static int i9xx_pll_refclk(struct drm_device *dev,
6544 const struct intel_crtc_state *pipe_config)
6546 struct drm_i915_private *dev_priv = to_i915(dev);
6547 u32 dpll = pipe_config->dpll_hw_state.dpll;
6549 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
6550 return dev_priv->vbt.lvds_ssc_freq;
6551 else if (HAS_PCH_SPLIT(dev_priv))
6553 else if (DISPLAY_VER(dev_priv) != 2)
6559 /* Returns the clock of the currently programmed mode of the given pipe. */
6560 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6561 struct intel_crtc_state *pipe_config)
6563 struct drm_device *dev = crtc->base.dev;
6564 struct drm_i915_private *dev_priv = to_i915(dev);
6565 enum pipe pipe = crtc->pipe;
6566 u32 dpll = pipe_config->dpll_hw_state.dpll;
6570 int refclk = i9xx_pll_refclk(dev, pipe_config);
6572 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6573 fp = pipe_config->dpll_hw_state.fp0;
6575 fp = pipe_config->dpll_hw_state.fp1;
6577 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6578 if (IS_PINEVIEW(dev_priv)) {
6579 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6580 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6582 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6583 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6586 if (DISPLAY_VER(dev_priv) != 2) {
6587 if (IS_PINEVIEW(dev_priv))
6588 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6589 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6591 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6592 DPLL_FPA01_P1_POST_DIV_SHIFT);
6594 switch (dpll & DPLL_MODE_MASK) {
6595 case DPLLB_MODE_DAC_SERIAL:
6596 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6599 case DPLLB_MODE_LVDS:
6600 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6604 drm_dbg_kms(&dev_priv->drm,
6605 "Unknown DPLL mode %08x in programmed "
6606 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6610 if (IS_PINEVIEW(dev_priv))
6611 port_clock = pnv_calc_dpll_params(refclk, &clock);
6613 port_clock = i9xx_calc_dpll_params(refclk, &clock);
6615 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
6617 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
6620 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6621 DPLL_FPA01_P1_POST_DIV_SHIFT);
6623 if (lvds & LVDS_CLKB_POWER_UP)
6628 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6631 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6632 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6634 if (dpll & PLL_P2_DIVIDE_BY_4)
6640 port_clock = i9xx_calc_dpll_params(refclk, &clock);
6644 * This value includes pixel_multiplier. We will use
6645 * port_clock to compute adjusted_mode.crtc_clock in the
6646 * encoder's get_config() function.
6648 pipe_config->port_clock = port_clock;
6651 int intel_dotclock_calculate(int link_freq,
6652 const struct intel_link_m_n *m_n)
6655 * The calculation for the data clock is:
6656 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
6657 * But we want to avoid losing precison if possible, so:
6658 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
6660 * and the link clock is simpler:
6661 * link_clock = (m * link_clock) / n
6667 return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
6670 static void ilk_pch_clock_get(struct intel_crtc *crtc,
6671 struct intel_crtc_state *pipe_config)
6673 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6675 /* read out port_clock from the DPLL */
6676 i9xx_crtc_clock_get(crtc, pipe_config);
6679 * In case there is an active pipe without active ports,
6680 * we may need some idea for the dotclock anyway.
6681 * Calculate one based on the FDI configuration.
6683 pipe_config->hw.adjusted_mode.crtc_clock =
6684 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
6685 &pipe_config->fdi_m_n);
6688 /* Returns the currently programmed mode of the given encoder. */
6689 struct drm_display_mode *
6690 intel_encoder_current_mode(struct intel_encoder *encoder)
6692 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6693 struct intel_crtc_state *crtc_state;
6694 struct drm_display_mode *mode;
6695 struct intel_crtc *crtc;
6698 if (!encoder->get_hw_state(encoder, &pipe))
6701 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6703 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6707 crtc_state = intel_crtc_state_alloc(crtc);
6713 if (!intel_crtc_get_pipe_config(crtc_state)) {
6719 intel_encoder_get_config(encoder, crtc_state);
6721 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
6729 * intel_wm_need_update - Check whether watermarks need updating
6730 * @cur: current plane state
6731 * @new: new plane state
6733 * Check current plane state versus the new one to determine whether
6734 * watermarks need to be recalculated.
6736 * Returns true or false.
6738 static bool intel_wm_need_update(const struct intel_plane_state *cur,
6739 struct intel_plane_state *new)
6741 /* Update watermarks on tiling or size changes. */
6742 if (new->uapi.visible != cur->uapi.visible)
6745 if (!cur->hw.fb || !new->hw.fb)
6748 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
6749 cur->hw.rotation != new->hw.rotation ||
6750 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
6751 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
6752 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
6753 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
6759 static bool needs_scaling(const struct intel_plane_state *state)
6761 int src_w = drm_rect_width(&state->uapi.src) >> 16;
6762 int src_h = drm_rect_height(&state->uapi.src) >> 16;
6763 int dst_w = drm_rect_width(&state->uapi.dst);
6764 int dst_h = drm_rect_height(&state->uapi.dst);
6766 return (src_w != dst_w || src_h != dst_h);
6769 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
6770 struct intel_crtc_state *crtc_state,
6771 const struct intel_plane_state *old_plane_state,
6772 struct intel_plane_state *plane_state)
6774 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6775 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
6776 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6777 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
6778 bool was_crtc_enabled = old_crtc_state->hw.active;
6779 bool is_crtc_enabled = crtc_state->hw.active;
6780 bool turn_off, turn_on, visible, was_visible;
6783 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
6784 ret = skl_update_scaler_plane(crtc_state, plane_state);
6789 was_visible = old_plane_state->uapi.visible;
6790 visible = plane_state->uapi.visible;
6792 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
6793 was_visible = false;
6796 * Visibility is calculated as if the crtc was on, but
6797 * after scaler setup everything depends on it being off
6798 * when the crtc isn't active.
6800 * FIXME this is wrong for watermarks. Watermarks should also
6801 * be computed as if the pipe would be active. Perhaps move
6802 * per-plane wm computation to the .check_plane() hook, and
6803 * only combine the results from all planes in the current place?
6805 if (!is_crtc_enabled) {
6806 intel_plane_set_invisible(crtc_state, plane_state);
6810 if (!was_visible && !visible)
6813 turn_off = was_visible && (!visible || mode_changed);
6814 turn_on = visible && (!was_visible || mode_changed);
6816 drm_dbg_atomic(&dev_priv->drm,
6817 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
6818 crtc->base.base.id, crtc->base.name,
6819 plane->base.base.id, plane->base.name,
6820 was_visible, visible,
6821 turn_off, turn_on, mode_changed);
6824 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
6825 crtc_state->update_wm_pre = true;
6827 /* must disable cxsr around plane enable/disable */
6828 if (plane->id != PLANE_CURSOR)
6829 crtc_state->disable_cxsr = true;
6830 } else if (turn_off) {
6831 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
6832 crtc_state->update_wm_post = true;
6834 /* must disable cxsr around plane enable/disable */
6835 if (plane->id != PLANE_CURSOR)
6836 crtc_state->disable_cxsr = true;
6837 } else if (intel_wm_need_update(old_plane_state, plane_state)) {
6838 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
6839 /* FIXME bollocks */
6840 crtc_state->update_wm_pre = true;
6841 crtc_state->update_wm_post = true;
6845 if (visible || was_visible)
6846 crtc_state->fb_bits |= plane->frontbuffer_bit;
6849 * ILK/SNB DVSACNTR/Sprite Enable
6850 * IVB SPR_CTL/Sprite Enable
6851 * "When in Self Refresh Big FIFO mode, a write to enable the
6852 * plane will be internally buffered and delayed while Big FIFO
6855 * Which means that enabling the sprite can take an extra frame
6856 * when we start in big FIFO mode (LP1+). Thus we need to drop
6857 * down to LP0 and wait for vblank in order to make sure the
6858 * sprite gets enabled on the next vblank after the register write.
6859 * Doing otherwise would risk enabling the sprite one frame after
6860 * we've already signalled flip completion. We can resume LP1+
6861 * once the sprite has been enabled.
6864 * WaCxSRDisabledForSpriteScaling:ivb
6865 * IVB SPR_SCALE/Scaling Enable
6866 * "Low Power watermarks must be disabled for at least one
6867 * frame before enabling sprite scaling, and kept disabled
6868 * until sprite scaling is disabled."
6870 * ILK/SNB DVSASCALE/Scaling Enable
6871 * "When in Self Refresh Big FIFO mode, scaling enable will be
6872 * masked off while Big FIFO mode is exiting."
6874 * Despite the w/a only being listed for IVB we assume that
6875 * the ILK/SNB note has similar ramifications, hence we apply
6876 * the w/a on all three platforms.
6878 * With experimental results seems this is needed also for primary
6879 * plane, not only sprite plane.
6881 if (plane->id != PLANE_CURSOR &&
6882 (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
6883 IS_IVYBRIDGE(dev_priv)) &&
6884 (turn_on || (!needs_scaling(old_plane_state) &&
6885 needs_scaling(plane_state))))
6886 crtc_state->disable_lp_wm = true;
6891 static bool encoders_cloneable(const struct intel_encoder *a,
6892 const struct intel_encoder *b)
6894 /* masks could be asymmetric, so check both ways */
6895 return a == b || (a->cloneable & (1 << b->type) &&
6896 b->cloneable & (1 << a->type));
6899 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
6900 struct intel_crtc *crtc,
6901 struct intel_encoder *encoder)
6903 struct intel_encoder *source_encoder;
6904 struct drm_connector *connector;
6905 struct drm_connector_state *connector_state;
6908 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
6909 if (connector_state->crtc != &crtc->base)
6913 to_intel_encoder(connector_state->best_encoder);
6914 if (!encoders_cloneable(encoder, source_encoder))
6921 static int icl_add_linked_planes(struct intel_atomic_state *state)
6923 struct intel_plane *plane, *linked;
6924 struct intel_plane_state *plane_state, *linked_plane_state;
6927 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6928 linked = plane_state->planar_linked_plane;
6933 linked_plane_state = intel_atomic_get_plane_state(state, linked);
6934 if (IS_ERR(linked_plane_state))
6935 return PTR_ERR(linked_plane_state);
6937 drm_WARN_ON(state->base.dev,
6938 linked_plane_state->planar_linked_plane != plane);
6939 drm_WARN_ON(state->base.dev,
6940 linked_plane_state->planar_slave == plane_state->planar_slave);
6946 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
6948 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6949 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6950 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
6951 struct intel_plane *plane, *linked;
6952 struct intel_plane_state *plane_state;
6955 if (DISPLAY_VER(dev_priv) < 11)
6959 * Destroy all old plane links and make the slave plane invisible
6960 * in the crtc_state->active_planes mask.
6962 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6963 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
6966 plane_state->planar_linked_plane = NULL;
6967 if (plane_state->planar_slave && !plane_state->uapi.visible) {
6968 crtc_state->enabled_planes &= ~BIT(plane->id);
6969 crtc_state->active_planes &= ~BIT(plane->id);
6970 crtc_state->update_planes |= BIT(plane->id);
6973 plane_state->planar_slave = false;
6976 if (!crtc_state->nv12_planes)
6979 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6980 struct intel_plane_state *linked_state = NULL;
6982 if (plane->pipe != crtc->pipe ||
6983 !(crtc_state->nv12_planes & BIT(plane->id)))
6986 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
6987 if (!icl_is_nv12_y_plane(dev_priv, linked->id))
6990 if (crtc_state->active_planes & BIT(linked->id))
6993 linked_state = intel_atomic_get_plane_state(state, linked);
6994 if (IS_ERR(linked_state))
6995 return PTR_ERR(linked_state);
7000 if (!linked_state) {
7001 drm_dbg_kms(&dev_priv->drm,
7002 "Need %d free Y planes for planar YUV\n",
7003 hweight8(crtc_state->nv12_planes));
7008 plane_state->planar_linked_plane = linked;
7010 linked_state->planar_slave = true;
7011 linked_state->planar_linked_plane = plane;
7012 crtc_state->enabled_planes |= BIT(linked->id);
7013 crtc_state->active_planes |= BIT(linked->id);
7014 crtc_state->update_planes |= BIT(linked->id);
7015 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
7016 linked->base.name, plane->base.name);
7018 /* Copy parameters to slave plane */
7019 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
7020 linked_state->color_ctl = plane_state->color_ctl;
7021 linked_state->view = plane_state->view;
7023 intel_plane_copy_hw_state(linked_state, plane_state);
7024 linked_state->uapi.src = plane_state->uapi.src;
7025 linked_state->uapi.dst = plane_state->uapi.dst;
7027 if (icl_is_hdr_plane(dev_priv, plane->id)) {
7028 if (linked->id == PLANE_SPRITE5)
7029 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
7030 else if (linked->id == PLANE_SPRITE4)
7031 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
7032 else if (linked->id == PLANE_SPRITE3)
7033 plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
7034 else if (linked->id == PLANE_SPRITE2)
7035 plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
7037 MISSING_CASE(linked->id);
7044 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
7046 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7047 struct intel_atomic_state *state =
7048 to_intel_atomic_state(new_crtc_state->uapi.state);
7049 const struct intel_crtc_state *old_crtc_state =
7050 intel_atomic_get_old_crtc_state(state, crtc);
7052 return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
7055 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
7057 const struct drm_display_mode *pipe_mode =
7058 &crtc_state->hw.pipe_mode;
7061 if (!crtc_state->hw.enable)
7064 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7065 pipe_mode->crtc_clock);
7067 return min(linetime_wm, 0x1ff);
7070 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
7071 const struct intel_cdclk_state *cdclk_state)
7073 const struct drm_display_mode *pipe_mode =
7074 &crtc_state->hw.pipe_mode;
7077 if (!crtc_state->hw.enable)
7080 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
7081 cdclk_state->logical.cdclk);
7083 return min(linetime_wm, 0x1ff);
7086 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
7088 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7089 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7090 const struct drm_display_mode *pipe_mode =
7091 &crtc_state->hw.pipe_mode;
7094 if (!crtc_state->hw.enable)
7097 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
7098 crtc_state->pixel_rate);
7100 /* Display WA #1135: BXT:ALL GLK:ALL */
7101 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
7102 dev_priv->ipc_enabled)
7105 return min(linetime_wm, 0x1ff);
7108 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
7109 struct intel_crtc *crtc)
7111 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7112 struct intel_crtc_state *crtc_state =
7113 intel_atomic_get_new_crtc_state(state, crtc);
7114 const struct intel_cdclk_state *cdclk_state;
7116 if (DISPLAY_VER(dev_priv) >= 9)
7117 crtc_state->linetime = skl_linetime_wm(crtc_state);
7119 crtc_state->linetime = hsw_linetime_wm(crtc_state);
7121 if (!hsw_crtc_supports_ips(crtc))
7124 cdclk_state = intel_atomic_get_cdclk_state(state);
7125 if (IS_ERR(cdclk_state))
7126 return PTR_ERR(cdclk_state);
7128 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
7134 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
7135 struct intel_crtc *crtc)
7137 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7138 struct intel_crtc_state *crtc_state =
7139 intel_atomic_get_new_crtc_state(state, crtc);
7140 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
7143 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
7144 mode_changed && !crtc_state->hw.active)
7145 crtc_state->update_wm_post = true;
7147 if (mode_changed && crtc_state->hw.enable &&
7148 dev_priv->display.crtc_compute_clock &&
7149 !crtc_state->bigjoiner_slave &&
7150 !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
7151 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
7157 * May need to update pipe gamma enable bits
7158 * when C8 planes are getting enabled/disabled.
7160 if (c8_planes_changed(crtc_state))
7161 crtc_state->uapi.color_mgmt_changed = true;
7163 if (mode_changed || crtc_state->update_pipe ||
7164 crtc_state->uapi.color_mgmt_changed) {
7165 ret = intel_color_check(crtc_state);
7170 if (dev_priv->display.compute_pipe_wm) {
7171 ret = dev_priv->display.compute_pipe_wm(state, crtc);
7173 drm_dbg_kms(&dev_priv->drm,
7174 "Target pipe watermarks are invalid\n");
7180 if (dev_priv->display.compute_intermediate_wm) {
7181 if (drm_WARN_ON(&dev_priv->drm,
7182 !dev_priv->display.compute_pipe_wm))
7186 * Calculate 'intermediate' watermarks that satisfy both the
7187 * old state and the new state. We can program these
7190 ret = dev_priv->display.compute_intermediate_wm(state, crtc);
7192 drm_dbg_kms(&dev_priv->drm,
7193 "No valid intermediate pipe watermarks are possible\n");
7198 if (DISPLAY_VER(dev_priv) >= 9) {
7199 if (mode_changed || crtc_state->update_pipe) {
7200 ret = skl_update_scaler_crtc(crtc_state);
7205 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
7210 if (HAS_IPS(dev_priv)) {
7211 ret = hsw_compute_ips_config(crtc_state);
7216 if (DISPLAY_VER(dev_priv) >= 9 ||
7217 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7218 ret = hsw_compute_linetime_wm(state, crtc);
7224 if (!mode_changed) {
7225 ret = intel_psr2_sel_fetch_update(state, crtc);
7233 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
7235 struct intel_connector *connector;
7236 struct drm_connector_list_iter conn_iter;
7238 drm_connector_list_iter_begin(dev, &conn_iter);
7239 for_each_intel_connector_iter(connector, &conn_iter) {
7240 struct drm_connector_state *conn_state = connector->base.state;
7241 struct intel_encoder *encoder =
7242 to_intel_encoder(connector->base.encoder);
7244 if (conn_state->crtc)
7245 drm_connector_put(&connector->base);
7248 struct intel_crtc *crtc =
7249 to_intel_crtc(encoder->base.crtc);
7250 const struct intel_crtc_state *crtc_state =
7251 to_intel_crtc_state(crtc->base.state);
7253 conn_state->best_encoder = &encoder->base;
7254 conn_state->crtc = &crtc->base;
7255 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
7257 drm_connector_get(&connector->base);
7259 conn_state->best_encoder = NULL;
7260 conn_state->crtc = NULL;
7263 drm_connector_list_iter_end(&conn_iter);
7267 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
7268 struct intel_crtc_state *pipe_config)
7270 struct drm_connector *connector = conn_state->connector;
7271 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7272 const struct drm_display_info *info = &connector->display_info;
7275 switch (conn_state->max_bpc) {
7289 MISSING_CASE(conn_state->max_bpc);
7293 if (bpp < pipe_config->pipe_bpp) {
7294 drm_dbg_kms(&i915->drm,
7295 "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
7296 "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
7297 connector->base.id, connector->name,
7299 3 * conn_state->max_requested_bpc,
7300 pipe_config->pipe_bpp);
7302 pipe_config->pipe_bpp = bpp;
7309 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7310 struct intel_crtc_state *pipe_config)
7312 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7313 struct drm_atomic_state *state = pipe_config->uapi.state;
7314 struct drm_connector *connector;
7315 struct drm_connector_state *connector_state;
7318 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7319 IS_CHERRYVIEW(dev_priv)))
7321 else if (DISPLAY_VER(dev_priv) >= 5)
7326 pipe_config->pipe_bpp = bpp;
7328 /* Clamp display bpp to connector max bpp */
7329 for_each_new_connector_in_state(state, connector, connector_state, i) {
7332 if (connector_state->crtc != &crtc->base)
7335 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
7343 static void intel_dump_crtc_timings(struct drm_i915_private *i915,
7344 const struct drm_display_mode *mode)
7346 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
7347 "type: 0x%x flags: 0x%x\n",
7349 mode->crtc_hdisplay, mode->crtc_hsync_start,
7350 mode->crtc_hsync_end, mode->crtc_htotal,
7351 mode->crtc_vdisplay, mode->crtc_vsync_start,
7352 mode->crtc_vsync_end, mode->crtc_vtotal,
7353 mode->type, mode->flags);
7357 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
7358 const char *id, unsigned int lane_count,
7359 const struct intel_link_m_n *m_n)
7361 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7363 drm_dbg_kms(&i915->drm,
7364 "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7366 m_n->gmch_m, m_n->gmch_n,
7367 m_n->link_m, m_n->link_n, m_n->tu);
7371 intel_dump_infoframe(struct drm_i915_private *dev_priv,
7372 const union hdmi_infoframe *frame)
7374 if (!drm_debug_enabled(DRM_UT_KMS))
7377 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
7381 intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
7382 const struct drm_dp_vsc_sdp *vsc)
7384 if (!drm_debug_enabled(DRM_UT_KMS))
7387 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
7390 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
7392 static const char * const output_type_str[] = {
7393 OUTPUT_TYPE(UNUSED),
7394 OUTPUT_TYPE(ANALOG),
7404 OUTPUT_TYPE(DP_MST),
7409 static void snprintf_output_types(char *buf, size_t len,
7410 unsigned int output_types)
7417 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
7420 if ((output_types & BIT(i)) == 0)
7423 r = snprintf(str, len, "%s%s",
7424 str != buf ? "," : "", output_type_str[i]);
7430 output_types &= ~BIT(i);
7433 WARN_ON_ONCE(output_types != 0);
7436 static const char * const output_format_str[] = {
7437 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
7438 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
7439 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
7442 static const char *output_formats(enum intel_output_format format)
7444 if (format >= ARRAY_SIZE(output_format_str))
7446 return output_format_str[format];
7449 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
7451 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
7452 struct drm_i915_private *i915 = to_i915(plane->base.dev);
7453 const struct drm_framebuffer *fb = plane_state->hw.fb;
7456 drm_dbg_kms(&i915->drm,
7457 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
7458 plane->base.base.id, plane->base.name,
7459 yesno(plane_state->uapi.visible));
7463 drm_dbg_kms(&i915->drm,
7464 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
7465 plane->base.base.id, plane->base.name,
7466 fb->base.id, fb->width, fb->height, &fb->format->format,
7467 fb->modifier, yesno(plane_state->uapi.visible));
7468 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
7469 plane_state->hw.rotation, plane_state->scaler_id);
7470 if (plane_state->uapi.visible)
7471 drm_dbg_kms(&i915->drm,
7472 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
7473 DRM_RECT_FP_ARG(&plane_state->uapi.src),
7474 DRM_RECT_ARG(&plane_state->uapi.dst));
7477 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
7478 struct intel_atomic_state *state,
7479 const char *context)
7481 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
7482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7483 const struct intel_plane_state *plane_state;
7484 struct intel_plane *plane;
7488 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
7489 crtc->base.base.id, crtc->base.name,
7490 yesno(pipe_config->hw.enable), context);
7492 if (!pipe_config->hw.enable)
7495 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
7496 drm_dbg_kms(&dev_priv->drm,
7497 "active: %s, output_types: %s (0x%x), output format: %s\n",
7498 yesno(pipe_config->hw.active),
7499 buf, pipe_config->output_types,
7500 output_formats(pipe_config->output_format));
7502 drm_dbg_kms(&dev_priv->drm,
7503 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
7504 transcoder_name(pipe_config->cpu_transcoder),
7505 pipe_config->pipe_bpp, pipe_config->dither);
7507 drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
7508 transcoder_name(pipe_config->mst_master_transcoder));
7510 drm_dbg_kms(&dev_priv->drm,
7511 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
7512 transcoder_name(pipe_config->master_transcoder),
7513 pipe_config->sync_mode_slaves_mask);
7515 drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s\n",
7516 pipe_config->bigjoiner_slave ? "slave" :
7517 pipe_config->bigjoiner ? "master" : "no");
7519 drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
7520 enableddisabled(pipe_config->splitter.enable),
7521 pipe_config->splitter.link_count,
7522 pipe_config->splitter.pixel_overlap);
7524 if (pipe_config->has_pch_encoder)
7525 intel_dump_m_n_config(pipe_config, "fdi",
7526 pipe_config->fdi_lanes,
7527 &pipe_config->fdi_m_n);
7529 if (intel_crtc_has_dp_encoder(pipe_config)) {
7530 intel_dump_m_n_config(pipe_config, "dp m_n",
7531 pipe_config->lane_count, &pipe_config->dp_m_n);
7532 if (pipe_config->has_drrs)
7533 intel_dump_m_n_config(pipe_config, "dp m2_n2",
7534 pipe_config->lane_count,
7535 &pipe_config->dp_m2_n2);
7538 drm_dbg_kms(&dev_priv->drm,
7539 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
7540 pipe_config->has_audio, pipe_config->has_infoframe,
7541 pipe_config->infoframes.enable);
7543 if (pipe_config->infoframes.enable &
7544 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
7545 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
7546 pipe_config->infoframes.gcp);
7547 if (pipe_config->infoframes.enable &
7548 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
7549 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
7550 if (pipe_config->infoframes.enable &
7551 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
7552 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
7553 if (pipe_config->infoframes.enable &
7554 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
7555 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
7556 if (pipe_config->infoframes.enable &
7557 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
7558 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
7559 if (pipe_config->infoframes.enable &
7560 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
7561 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
7562 if (pipe_config->infoframes.enable &
7563 intel_hdmi_infoframe_enable(DP_SDP_VSC))
7564 intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
7566 drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
7567 yesno(pipe_config->vrr.enable),
7568 pipe_config->vrr.vmin, pipe_config->vrr.vmax,
7569 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
7570 pipe_config->vrr.flipline,
7571 intel_vrr_vmin_vblank_start(pipe_config),
7572 intel_vrr_vmax_vblank_start(pipe_config));
7574 drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
7575 drm_mode_debug_printmodeline(&pipe_config->hw.mode);
7576 drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
7577 drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
7578 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
7579 drm_dbg_kms(&dev_priv->drm, "pipe mode:\n");
7580 drm_mode_debug_printmodeline(&pipe_config->hw.pipe_mode);
7581 intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
7582 drm_dbg_kms(&dev_priv->drm,
7583 "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
7584 pipe_config->port_clock,
7585 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
7586 pipe_config->pixel_rate);
7588 drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
7589 pipe_config->linetime, pipe_config->ips_linetime);
7591 if (DISPLAY_VER(dev_priv) >= 9)
7592 drm_dbg_kms(&dev_priv->drm,
7593 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
7595 pipe_config->scaler_state.scaler_users,
7596 pipe_config->scaler_state.scaler_id);
7598 if (HAS_GMCH(dev_priv))
7599 drm_dbg_kms(&dev_priv->drm,
7600 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7601 pipe_config->gmch_pfit.control,
7602 pipe_config->gmch_pfit.pgm_ratios,
7603 pipe_config->gmch_pfit.lvds_border_bits);
7605 drm_dbg_kms(&dev_priv->drm,
7606 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
7607 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
7608 enableddisabled(pipe_config->pch_pfit.enabled),
7609 yesno(pipe_config->pch_pfit.force_thru));
7611 drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
7612 pipe_config->ips_enabled, pipe_config->double_wide);
7614 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
7616 if (IS_CHERRYVIEW(dev_priv))
7617 drm_dbg_kms(&dev_priv->drm,
7618 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
7619 pipe_config->cgm_mode, pipe_config->gamma_mode,
7620 pipe_config->gamma_enable, pipe_config->csc_enable);
7622 drm_dbg_kms(&dev_priv->drm,
7623 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
7624 pipe_config->csc_mode, pipe_config->gamma_mode,
7625 pipe_config->gamma_enable, pipe_config->csc_enable);
7627 drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
7628 pipe_config->hw.degamma_lut ?
7629 drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
7630 pipe_config->hw.gamma_lut ?
7631 drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
7637 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7638 if (plane->pipe == crtc->pipe)
7639 intel_dump_plane_state(plane_state);
7643 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
7645 struct drm_device *dev = state->base.dev;
7646 struct drm_connector *connector;
7647 struct drm_connector_list_iter conn_iter;
7648 unsigned int used_ports = 0;
7649 unsigned int used_mst_ports = 0;
7653 * We're going to peek into connector->state,
7654 * hence connection_mutex must be held.
7656 drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
7659 * Walk the connector list instead of the encoder
7660 * list to detect the problem on ddi platforms
7661 * where there's just one encoder per digital port.
7663 drm_connector_list_iter_begin(dev, &conn_iter);
7664 drm_for_each_connector_iter(connector, &conn_iter) {
7665 struct drm_connector_state *connector_state;
7666 struct intel_encoder *encoder;
7669 drm_atomic_get_new_connector_state(&state->base,
7671 if (!connector_state)
7672 connector_state = connector->state;
7674 if (!connector_state->best_encoder)
7677 encoder = to_intel_encoder(connector_state->best_encoder);
7679 drm_WARN_ON(dev, !connector_state->crtc);
7681 switch (encoder->type) {
7682 case INTEL_OUTPUT_DDI:
7683 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
7686 case INTEL_OUTPUT_DP:
7687 case INTEL_OUTPUT_HDMI:
7688 case INTEL_OUTPUT_EDP:
7689 /* the same port mustn't appear more than once */
7690 if (used_ports & BIT(encoder->port))
7693 used_ports |= BIT(encoder->port);
7695 case INTEL_OUTPUT_DP_MST:
7703 drm_connector_list_iter_end(&conn_iter);
7705 /* can't mix MST and SST/HDMI on the same port */
7706 if (used_ports & used_mst_ports)
7713 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
7714 struct intel_crtc_state *crtc_state)
7716 const struct intel_crtc_state *from_crtc_state = crtc_state;
7718 if (crtc_state->bigjoiner_slave) {
7719 from_crtc_state = intel_atomic_get_new_crtc_state(state,
7720 crtc_state->bigjoiner_linked_crtc);
7722 /* No need to copy state if the master state is unchanged */
7723 if (!from_crtc_state)
7727 intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
7731 intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
7732 struct intel_crtc_state *crtc_state)
7734 crtc_state->hw.enable = crtc_state->uapi.enable;
7735 crtc_state->hw.active = crtc_state->uapi.active;
7736 crtc_state->hw.mode = crtc_state->uapi.mode;
7737 crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
7738 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
7740 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
7743 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
7745 if (crtc_state->bigjoiner_slave)
7748 crtc_state->uapi.enable = crtc_state->hw.enable;
7749 crtc_state->uapi.active = crtc_state->hw.active;
7750 drm_WARN_ON(crtc_state->uapi.crtc->dev,
7751 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
7753 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
7754 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
7756 /* copy color blobs to uapi */
7757 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
7758 crtc_state->hw.degamma_lut);
7759 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
7760 crtc_state->hw.gamma_lut);
7761 drm_property_replace_blob(&crtc_state->uapi.ctm,
7762 crtc_state->hw.ctm);
7766 copy_bigjoiner_crtc_state(struct intel_crtc_state *crtc_state,
7767 const struct intel_crtc_state *from_crtc_state)
7769 struct intel_crtc_state *saved_state;
7770 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7772 saved_state = kmemdup(from_crtc_state, sizeof(*saved_state), GFP_KERNEL);
7776 saved_state->uapi = crtc_state->uapi;
7777 saved_state->scaler_state = crtc_state->scaler_state;
7778 saved_state->shared_dpll = crtc_state->shared_dpll;
7779 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
7780 saved_state->crc_enabled = crtc_state->crc_enabled;
7782 intel_crtc_free_hw_state(crtc_state);
7783 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
7786 /* Re-init hw state */
7787 memset(&crtc_state->hw, 0, sizeof(saved_state->hw));
7788 crtc_state->hw.enable = from_crtc_state->hw.enable;
7789 crtc_state->hw.active = from_crtc_state->hw.active;
7790 crtc_state->hw.pipe_mode = from_crtc_state->hw.pipe_mode;
7791 crtc_state->hw.adjusted_mode = from_crtc_state->hw.adjusted_mode;
7794 crtc_state->uapi.mode_changed = from_crtc_state->uapi.mode_changed;
7795 crtc_state->uapi.connectors_changed = from_crtc_state->uapi.connectors_changed;
7796 crtc_state->uapi.active_changed = from_crtc_state->uapi.active_changed;
7797 crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0;
7798 crtc_state->bigjoiner_linked_crtc = to_intel_crtc(from_crtc_state->uapi.crtc);
7799 crtc_state->bigjoiner_slave = true;
7800 crtc_state->cpu_transcoder = (enum transcoder)crtc->pipe;
7801 crtc_state->has_audio = false;
7807 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
7808 struct intel_crtc_state *crtc_state)
7810 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7811 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7812 struct intel_crtc_state *saved_state;
7814 saved_state = intel_crtc_state_alloc(crtc);
7818 /* free the old crtc_state->hw members */
7819 intel_crtc_free_hw_state(crtc_state);
7821 /* FIXME: before the switch to atomic started, a new pipe_config was
7822 * kzalloc'd. Code that depends on any field being zero should be
7823 * fixed, so that the crtc_state can be safely duplicated. For now,
7824 * only fields that are know to not cause problems are preserved. */
7826 saved_state->uapi = crtc_state->uapi;
7827 saved_state->scaler_state = crtc_state->scaler_state;
7828 saved_state->shared_dpll = crtc_state->shared_dpll;
7829 saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
7830 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
7831 sizeof(saved_state->icl_port_dplls));
7832 saved_state->crc_enabled = crtc_state->crc_enabled;
7833 if (IS_G4X(dev_priv) ||
7834 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7835 saved_state->wm = crtc_state->wm;
7837 memcpy(crtc_state, saved_state, sizeof(*crtc_state));
7840 intel_crtc_copy_uapi_to_hw_state(state, crtc_state);
7846 intel_modeset_pipe_config(struct intel_atomic_state *state,
7847 struct intel_crtc_state *pipe_config)
7849 struct drm_crtc *crtc = pipe_config->uapi.crtc;
7850 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
7851 struct drm_connector *connector;
7852 struct drm_connector_state *connector_state;
7853 int base_bpp, ret, i;
7856 pipe_config->cpu_transcoder =
7857 (enum transcoder) to_intel_crtc(crtc)->pipe;
7860 * Sanitize sync polarity flags based on requested ones. If neither
7861 * positive or negative polarity is requested, treat this as meaning
7862 * negative polarity.
7864 if (!(pipe_config->hw.adjusted_mode.flags &
7865 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
7866 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
7868 if (!(pipe_config->hw.adjusted_mode.flags &
7869 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
7870 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
7872 ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7877 base_bpp = pipe_config->pipe_bpp;
7880 * Determine the real pipe dimensions. Note that stereo modes can
7881 * increase the actual pipe size due to the frame doubling and
7882 * insertion of additional space for blanks between the frame. This
7883 * is stored in the crtc timings. We use the requested mode to do this
7884 * computation to clearly distinguish it from the adjusted mode, which
7885 * can be changed by the connectors in the below retry loop.
7887 drm_mode_get_hv_timing(&pipe_config->hw.mode,
7888 &pipe_config->pipe_src_w,
7889 &pipe_config->pipe_src_h);
7891 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
7892 struct intel_encoder *encoder =
7893 to_intel_encoder(connector_state->best_encoder);
7895 if (connector_state->crtc != crtc)
7898 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
7899 drm_dbg_kms(&i915->drm,
7900 "rejecting invalid cloning configuration\n");
7905 * Determine output_types before calling the .compute_config()
7906 * hooks so that the hooks can use this information safely.
7908 if (encoder->compute_output_type)
7909 pipe_config->output_types |=
7910 BIT(encoder->compute_output_type(encoder, pipe_config,
7913 pipe_config->output_types |= BIT(encoder->type);
7917 /* Ensure the port clock defaults are reset when retrying. */
7918 pipe_config->port_clock = 0;
7919 pipe_config->pixel_multiplier = 1;
7921 /* Fill in default crtc timings, allow encoders to overwrite them. */
7922 drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
7923 CRTC_STEREO_DOUBLE);
7925 /* Pass our mode to the connectors and the CRTC to give them a chance to
7926 * adjust it according to limitations or connector properties, and also
7927 * a chance to reject the mode entirely.
7929 for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
7930 struct intel_encoder *encoder =
7931 to_intel_encoder(connector_state->best_encoder);
7933 if (connector_state->crtc != crtc)
7936 ret = encoder->compute_config(encoder, pipe_config,
7939 if (ret != -EDEADLK)
7940 drm_dbg_kms(&i915->drm,
7941 "Encoder config failure: %d\n",
7947 /* Set default port clock if not overwritten by the encoder. Needs to be
7948 * done afterwards in case the encoder adjusts the mode. */
7949 if (!pipe_config->port_clock)
7950 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
7951 * pipe_config->pixel_multiplier;
7953 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7954 if (ret == -EDEADLK)
7957 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
7961 if (ret == I915_DISPLAY_CONFIG_RETRY) {
7962 if (drm_WARN(&i915->drm, !retry,
7963 "loop in pipe configuration computation\n"))
7966 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
7971 /* Dithering seems to not pass-through bits correctly when it should, so
7972 * only enable it on 6bpc panels and when its not a compliance
7973 * test requesting 6bpc video pattern.
7975 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
7976 !pipe_config->dither_force_disable;
7977 drm_dbg_kms(&i915->drm,
7978 "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
7979 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7985 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
7987 struct intel_atomic_state *state =
7988 to_intel_atomic_state(crtc_state->uapi.state);
7989 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7990 struct drm_connector_state *conn_state;
7991 struct drm_connector *connector;
7994 for_each_new_connector_in_state(&state->base, connector,
7996 struct intel_encoder *encoder =
7997 to_intel_encoder(conn_state->best_encoder);
8000 if (conn_state->crtc != &crtc->base ||
8001 !encoder->compute_config_late)
8004 ret = encoder->compute_config_late(encoder, crtc_state,
8013 bool intel_fuzzy_clock_check(int clock1, int clock2)
8017 if (clock1 == clock2)
8020 if (!clock1 || !clock2)
8023 diff = abs(clock1 - clock2);
8025 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8032 intel_compare_m_n(unsigned int m, unsigned int n,
8033 unsigned int m2, unsigned int n2,
8036 if (m == m2 && n == n2)
8039 if (exact || !m || !n || !m2 || !n2)
8042 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
8049 } else if (n < n2) {
8059 return intel_fuzzy_clock_check(m, m2);
8063 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
8064 const struct intel_link_m_n *m2_n2,
8067 return m_n->tu == m2_n2->tu &&
8068 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
8069 m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
8070 intel_compare_m_n(m_n->link_m, m_n->link_n,
8071 m2_n2->link_m, m2_n2->link_n, exact);
8075 intel_compare_infoframe(const union hdmi_infoframe *a,
8076 const union hdmi_infoframe *b)
8078 return memcmp(a, b, sizeof(*a)) == 0;
8082 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
8083 const struct drm_dp_vsc_sdp *b)
8085 return memcmp(a, b, sizeof(*a)) == 0;
8089 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
8090 bool fastset, const char *name,
8091 const union hdmi_infoframe *a,
8092 const union hdmi_infoframe *b)
8095 if (!drm_debug_enabled(DRM_UT_KMS))
8098 drm_dbg_kms(&dev_priv->drm,
8099 "fastset mismatch in %s infoframe\n", name);
8100 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8101 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
8102 drm_dbg_kms(&dev_priv->drm, "found:\n");
8103 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
8105 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
8106 drm_err(&dev_priv->drm, "expected:\n");
8107 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
8108 drm_err(&dev_priv->drm, "found:\n");
8109 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
8114 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
8115 bool fastset, const char *name,
8116 const struct drm_dp_vsc_sdp *a,
8117 const struct drm_dp_vsc_sdp *b)
8120 if (!drm_debug_enabled(DRM_UT_KMS))
8123 drm_dbg_kms(&dev_priv->drm,
8124 "fastset mismatch in %s dp sdp\n", name);
8125 drm_dbg_kms(&dev_priv->drm, "expected:\n");
8126 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
8127 drm_dbg_kms(&dev_priv->drm, "found:\n");
8128 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
8130 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
8131 drm_err(&dev_priv->drm, "expected:\n");
8132 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
8133 drm_err(&dev_priv->drm, "found:\n");
8134 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
8138 static void __printf(4, 5)
8139 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
8140 const char *name, const char *format, ...)
8142 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
8143 struct va_format vaf;
8146 va_start(args, format);
8151 drm_dbg_kms(&i915->drm,
8152 "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
8153 crtc->base.base.id, crtc->base.name, name, &vaf);
8155 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
8156 crtc->base.base.id, crtc->base.name, name, &vaf);
8161 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
8163 if (dev_priv->params.fastboot != -1)
8164 return dev_priv->params.fastboot;
8166 /* Enable fastboot by default on Skylake and newer */
8167 if (DISPLAY_VER(dev_priv) >= 9)
8170 /* Enable fastboot by default on VLV and CHV */
8171 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8174 /* Disabled by default on all others */
8179 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
8180 const struct intel_crtc_state *pipe_config,
8183 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
8184 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
8187 bool fixup_inherited = fastset &&
8188 current_config->inherited && !pipe_config->inherited;
8190 if (fixup_inherited && !fastboot_enabled(dev_priv)) {
8191 drm_dbg_kms(&dev_priv->drm,
8192 "initial modeset and fastboot not set\n");
8196 #define PIPE_CONF_CHECK_X(name) do { \
8197 if (current_config->name != pipe_config->name) { \
8198 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8199 "(expected 0x%08x, found 0x%08x)", \
8200 current_config->name, \
8201 pipe_config->name); \
8206 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
8207 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
8208 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8209 "(expected 0x%08x, found 0x%08x)", \
8210 current_config->name & (mask), \
8211 pipe_config->name & (mask)); \
8216 #define PIPE_CONF_CHECK_I(name) do { \
8217 if (current_config->name != pipe_config->name) { \
8218 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8219 "(expected %i, found %i)", \
8220 current_config->name, \
8221 pipe_config->name); \
8226 #define PIPE_CONF_CHECK_BOOL(name) do { \
8227 if (current_config->name != pipe_config->name) { \
8228 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8229 "(expected %s, found %s)", \
8230 yesno(current_config->name), \
8231 yesno(pipe_config->name)); \
8237 * Checks state where we only read out the enabling, but not the entire
8238 * state itself (like full infoframes or ELD for audio). These states
8239 * require a full modeset on bootup to fix up.
8241 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
8242 if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
8243 PIPE_CONF_CHECK_BOOL(name); \
8245 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8246 "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
8247 yesno(current_config->name), \
8248 yesno(pipe_config->name)); \
8253 #define PIPE_CONF_CHECK_P(name) do { \
8254 if (current_config->name != pipe_config->name) { \
8255 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8256 "(expected %p, found %p)", \
8257 current_config->name, \
8258 pipe_config->name); \
8263 #define PIPE_CONF_CHECK_M_N(name) do { \
8264 if (!intel_compare_link_m_n(¤t_config->name, \
8265 &pipe_config->name,\
8267 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8268 "(expected tu %i gmch %i/%i link %i/%i, " \
8269 "found tu %i, gmch %i/%i link %i/%i)", \
8270 current_config->name.tu, \
8271 current_config->name.gmch_m, \
8272 current_config->name.gmch_n, \
8273 current_config->name.link_m, \
8274 current_config->name.link_n, \
8275 pipe_config->name.tu, \
8276 pipe_config->name.gmch_m, \
8277 pipe_config->name.gmch_n, \
8278 pipe_config->name.link_m, \
8279 pipe_config->name.link_n); \
8284 /* This is required for BDW+ where there is only one set of registers for
8285 * switching between high and low RR.
8286 * This macro can be used whenever a comparison has to be made between one
8287 * hw state and multiple sw state variables.
8289 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
8290 if (!intel_compare_link_m_n(¤t_config->name, \
8291 &pipe_config->name, !fastset) && \
8292 !intel_compare_link_m_n(¤t_config->alt_name, \
8293 &pipe_config->name, !fastset)) { \
8294 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8295 "(expected tu %i gmch %i/%i link %i/%i, " \
8296 "or tu %i gmch %i/%i link %i/%i, " \
8297 "found tu %i, gmch %i/%i link %i/%i)", \
8298 current_config->name.tu, \
8299 current_config->name.gmch_m, \
8300 current_config->name.gmch_n, \
8301 current_config->name.link_m, \
8302 current_config->name.link_n, \
8303 current_config->alt_name.tu, \
8304 current_config->alt_name.gmch_m, \
8305 current_config->alt_name.gmch_n, \
8306 current_config->alt_name.link_m, \
8307 current_config->alt_name.link_n, \
8308 pipe_config->name.tu, \
8309 pipe_config->name.gmch_m, \
8310 pipe_config->name.gmch_n, \
8311 pipe_config->name.link_m, \
8312 pipe_config->name.link_n); \
8317 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
8318 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8319 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8320 "(%x) (expected %i, found %i)", \
8322 current_config->name & (mask), \
8323 pipe_config->name & (mask)); \
8328 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
8329 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8330 pipe_config_mismatch(fastset, crtc, __stringify(name), \
8331 "(expected %i, found %i)", \
8332 current_config->name, \
8333 pipe_config->name); \
8338 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
8339 if (!intel_compare_infoframe(¤t_config->infoframes.name, \
8340 &pipe_config->infoframes.name)) { \
8341 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
8342 ¤t_config->infoframes.name, \
8343 &pipe_config->infoframes.name); \
8348 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
8349 if (!current_config->has_psr && !pipe_config->has_psr && \
8350 !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \
8351 &pipe_config->infoframes.name)) { \
8352 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
8353 ¤t_config->infoframes.name, \
8354 &pipe_config->infoframes.name); \
8359 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
8360 if (current_config->name1 != pipe_config->name1) { \
8361 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
8362 "(expected %i, found %i, won't compare lut values)", \
8363 current_config->name1, \
8364 pipe_config->name1); \
8367 if (!intel_color_lut_equal(current_config->name2, \
8368 pipe_config->name2, pipe_config->name1, \
8370 pipe_config_mismatch(fastset, crtc, __stringify(name2), \
8371 "hw_state doesn't match sw_state"); \
8377 #define PIPE_CONF_QUIRK(quirk) \
8378 ((current_config->quirks | pipe_config->quirks) & (quirk))
8380 PIPE_CONF_CHECK_I(cpu_transcoder);
8382 PIPE_CONF_CHECK_BOOL(has_pch_encoder);
8383 PIPE_CONF_CHECK_I(fdi_lanes);
8384 PIPE_CONF_CHECK_M_N(fdi_m_n);
8386 PIPE_CONF_CHECK_I(lane_count);
8387 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
8389 if (DISPLAY_VER(dev_priv) < 8) {
8390 PIPE_CONF_CHECK_M_N(dp_m_n);
8392 if (current_config->has_drrs)
8393 PIPE_CONF_CHECK_M_N(dp_m2_n2);
8395 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
8397 PIPE_CONF_CHECK_X(output_types);
8399 /* FIXME do the readout properly and get rid of this quirk */
8400 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8401 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
8402 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
8403 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
8404 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
8405 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
8406 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
8408 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
8409 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
8410 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
8411 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
8412 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
8413 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
8415 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
8416 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
8417 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
8418 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
8419 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
8420 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
8422 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
8423 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
8424 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
8425 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
8426 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
8427 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
8429 PIPE_CONF_CHECK_I(pixel_multiplier);
8431 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8432 DRM_MODE_FLAG_INTERLACE);
8434 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8435 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8436 DRM_MODE_FLAG_PHSYNC);
8437 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8438 DRM_MODE_FLAG_NHSYNC);
8439 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8440 DRM_MODE_FLAG_PVSYNC);
8441 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
8442 DRM_MODE_FLAG_NVSYNC);
8446 PIPE_CONF_CHECK_I(output_format);
8447 PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
8448 if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
8449 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8450 PIPE_CONF_CHECK_BOOL(limited_color_range);
8452 PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
8453 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
8454 PIPE_CONF_CHECK_BOOL(has_infoframe);
8455 /* FIXME do the readout properly and get rid of this quirk */
8456 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
8457 PIPE_CONF_CHECK_BOOL(fec_enable);
8459 PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
8461 PIPE_CONF_CHECK_X(gmch_pfit.control);
8462 /* pfit ratios are autocomputed by the hw on gen4+ */
8463 if (DISPLAY_VER(dev_priv) < 4)
8464 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
8465 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
8468 * Changing the EDP transcoder input mux
8469 * (A_ONOFF vs. A_ON) requires a full modeset.
8471 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
8474 PIPE_CONF_CHECK_I(pipe_src_w);
8475 PIPE_CONF_CHECK_I(pipe_src_h);
8477 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
8478 if (current_config->pch_pfit.enabled) {
8479 PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
8480 PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
8481 PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
8482 PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
8485 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
8486 /* FIXME do the readout properly and get rid of this quirk */
8487 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE))
8488 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
8490 PIPE_CONF_CHECK_X(gamma_mode);
8491 if (IS_CHERRYVIEW(dev_priv))
8492 PIPE_CONF_CHECK_X(cgm_mode);
8494 PIPE_CONF_CHECK_X(csc_mode);
8495 PIPE_CONF_CHECK_BOOL(gamma_enable);
8496 PIPE_CONF_CHECK_BOOL(csc_enable);
8498 PIPE_CONF_CHECK_I(linetime);
8499 PIPE_CONF_CHECK_I(ips_linetime);
8501 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
8503 PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
8505 PIPE_CONF_CHECK_BOOL(has_psr);
8506 PIPE_CONF_CHECK_BOOL(has_psr2);
8507 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
8508 PIPE_CONF_CHECK_I(dc3co_exitline);
8511 PIPE_CONF_CHECK_BOOL(double_wide);
8513 if (dev_priv->dpll.mgr)
8514 PIPE_CONF_CHECK_P(shared_dpll);
8516 /* FIXME do the readout properly and get rid of this quirk */
8517 if (dev_priv->dpll.mgr && !PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8518 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8519 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8520 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8521 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8522 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
8523 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
8524 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
8525 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
8526 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
8527 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
8528 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
8529 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
8530 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
8531 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
8532 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
8533 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
8534 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
8535 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
8536 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
8537 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
8538 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
8539 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
8540 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
8541 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
8542 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
8543 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
8544 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
8545 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
8546 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
8547 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
8548 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
8551 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
8552 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
8553 PIPE_CONF_CHECK_X(dsi_pll.div);
8555 if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
8556 PIPE_CONF_CHECK_I(pipe_bpp);
8558 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
8559 PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
8560 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8562 PIPE_CONF_CHECK_I(min_voltage_level);
8565 if (fastset && (current_config->has_psr || pipe_config->has_psr))
8566 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
8567 ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
8569 PIPE_CONF_CHECK_X(infoframes.enable);
8571 PIPE_CONF_CHECK_X(infoframes.gcp);
8572 PIPE_CONF_CHECK_INFOFRAME(avi);
8573 PIPE_CONF_CHECK_INFOFRAME(spd);
8574 PIPE_CONF_CHECK_INFOFRAME(hdmi);
8575 PIPE_CONF_CHECK_INFOFRAME(drm);
8576 PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
8578 PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
8579 PIPE_CONF_CHECK_I(master_transcoder);
8580 PIPE_CONF_CHECK_BOOL(bigjoiner);
8581 PIPE_CONF_CHECK_BOOL(bigjoiner_slave);
8582 PIPE_CONF_CHECK_P(bigjoiner_linked_crtc);
8584 PIPE_CONF_CHECK_I(dsc.compression_enable);
8585 PIPE_CONF_CHECK_I(dsc.dsc_split);
8586 PIPE_CONF_CHECK_I(dsc.compressed_bpp);
8588 PIPE_CONF_CHECK_BOOL(splitter.enable);
8589 PIPE_CONF_CHECK_I(splitter.link_count);
8590 PIPE_CONF_CHECK_I(splitter.pixel_overlap);
8592 PIPE_CONF_CHECK_I(mst_master_transcoder);
8594 PIPE_CONF_CHECK_BOOL(vrr.enable);
8595 PIPE_CONF_CHECK_I(vrr.vmin);
8596 PIPE_CONF_CHECK_I(vrr.vmax);
8597 PIPE_CONF_CHECK_I(vrr.flipline);
8598 PIPE_CONF_CHECK_I(vrr.pipeline_full);
8599 PIPE_CONF_CHECK_I(vrr.guardband);
8601 #undef PIPE_CONF_CHECK_X
8602 #undef PIPE_CONF_CHECK_I
8603 #undef PIPE_CONF_CHECK_BOOL
8604 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
8605 #undef PIPE_CONF_CHECK_P
8606 #undef PIPE_CONF_CHECK_FLAGS
8607 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8608 #undef PIPE_CONF_CHECK_COLOR_LUT
8609 #undef PIPE_CONF_QUIRK
8614 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
8615 const struct intel_crtc_state *pipe_config)
8617 if (pipe_config->has_pch_encoder) {
8618 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
8619 &pipe_config->fdi_m_n);
8620 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
8623 * FDI already provided one idea for the dotclock.
8624 * Yell if the encoder disagrees.
8626 drm_WARN(&dev_priv->drm,
8627 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
8628 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8629 fdi_dotclock, dotclock);
8633 static void verify_wm_state(struct intel_crtc *crtc,
8634 struct intel_crtc_state *new_crtc_state)
8636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8637 struct skl_hw_state {
8638 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
8639 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
8640 struct skl_pipe_wm wm;
8642 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
8643 int level, max_level = ilk_wm_max_level(dev_priv);
8644 struct intel_plane *plane;
8645 u8 hw_enabled_slices;
8647 if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
8650 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
8654 skl_pipe_wm_get_hw_state(crtc, &hw->wm);
8656 skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
8658 hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
8660 if (DISPLAY_VER(dev_priv) >= 11 &&
8661 hw_enabled_slices != dev_priv->dbuf.enabled_slices)
8662 drm_err(&dev_priv->drm,
8663 "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
8664 dev_priv->dbuf.enabled_slices,
8667 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
8668 const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
8669 const struct skl_wm_level *hw_wm_level, *sw_wm_level;
8672 for (level = 0; level <= max_level; level++) {
8673 hw_wm_level = &hw->wm.planes[plane->id].wm[level];
8674 sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
8676 if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
8679 drm_err(&dev_priv->drm,
8680 "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8681 plane->base.base.id, plane->base.name, level,
8682 sw_wm_level->enable,
8683 sw_wm_level->blocks,
8685 hw_wm_level->enable,
8686 hw_wm_level->blocks,
8687 hw_wm_level->lines);
8690 hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
8691 sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
8693 if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8694 drm_err(&dev_priv->drm,
8695 "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8696 plane->base.base.id, plane->base.name,
8697 sw_wm_level->enable,
8698 sw_wm_level->blocks,
8700 hw_wm_level->enable,
8701 hw_wm_level->blocks,
8702 hw_wm_level->lines);
8705 hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
8706 sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
8708 if (HAS_HW_SAGV_WM(dev_priv) &&
8709 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8710 drm_err(&dev_priv->drm,
8711 "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8712 plane->base.base.id, plane->base.name,
8713 sw_wm_level->enable,
8714 sw_wm_level->blocks,
8716 hw_wm_level->enable,
8717 hw_wm_level->blocks,
8718 hw_wm_level->lines);
8721 hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
8722 sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
8724 if (HAS_HW_SAGV_WM(dev_priv) &&
8725 !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
8726 drm_err(&dev_priv->drm,
8727 "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
8728 plane->base.base.id, plane->base.name,
8729 sw_wm_level->enable,
8730 sw_wm_level->blocks,
8732 hw_wm_level->enable,
8733 hw_wm_level->blocks,
8734 hw_wm_level->lines);
8738 hw_ddb_entry = &hw->ddb_y[plane->id];
8739 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
8741 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
8742 drm_err(&dev_priv->drm,
8743 "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
8744 plane->base.base.id, plane->base.name,
8745 sw_ddb_entry->start, sw_ddb_entry->end,
8746 hw_ddb_entry->start, hw_ddb_entry->end);
8754 verify_connector_state(struct intel_atomic_state *state,
8755 struct intel_crtc *crtc)
8757 struct drm_connector *connector;
8758 struct drm_connector_state *new_conn_state;
8761 for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
8762 struct drm_encoder *encoder = connector->encoder;
8763 struct intel_crtc_state *crtc_state = NULL;
8765 if (new_conn_state->crtc != &crtc->base)
8769 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
8771 intel_connector_verify_state(crtc_state, new_conn_state);
8773 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
8774 "connector's atomic encoder doesn't match legacy encoder\n");
8779 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
8781 struct intel_encoder *encoder;
8782 struct drm_connector *connector;
8783 struct drm_connector_state *old_conn_state, *new_conn_state;
8786 for_each_intel_encoder(&dev_priv->drm, encoder) {
8787 bool enabled = false, found = false;
8790 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
8791 encoder->base.base.id,
8792 encoder->base.name);
8794 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
8795 new_conn_state, i) {
8796 if (old_conn_state->best_encoder == &encoder->base)
8799 if (new_conn_state->best_encoder != &encoder->base)
8801 found = enabled = true;
8803 I915_STATE_WARN(new_conn_state->crtc !=
8805 "connector's crtc doesn't match encoder crtc\n");
8811 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8812 "encoder's enabled state mismatch "
8813 "(expected %i, found %i)\n",
8814 !!encoder->base.crtc, enabled);
8816 if (!encoder->base.crtc) {
8819 active = encoder->get_hw_state(encoder, &pipe);
8820 I915_STATE_WARN(active,
8821 "encoder detached but still enabled on pipe %c.\n",
8828 verify_crtc_state(struct intel_crtc *crtc,
8829 struct intel_crtc_state *old_crtc_state,
8830 struct intel_crtc_state *new_crtc_state)
8832 struct drm_device *dev = crtc->base.dev;
8833 struct drm_i915_private *dev_priv = to_i915(dev);
8834 struct intel_encoder *encoder;
8835 struct intel_crtc_state *pipe_config = old_crtc_state;
8836 struct drm_atomic_state *state = old_crtc_state->uapi.state;
8837 struct intel_crtc *master = crtc;
8839 __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
8840 intel_crtc_free_hw_state(old_crtc_state);
8841 intel_crtc_state_reset(old_crtc_state, crtc);
8842 old_crtc_state->uapi.state = state;
8844 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
8847 pipe_config->hw.enable = new_crtc_state->hw.enable;
8849 intel_crtc_get_pipe_config(pipe_config);
8851 /* we keep both pipes enabled on 830 */
8852 if (IS_I830(dev_priv) && pipe_config->hw.active)
8853 pipe_config->hw.active = new_crtc_state->hw.active;
8855 I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
8856 "crtc active state doesn't match with hw state "
8857 "(expected %i, found %i)\n",
8858 new_crtc_state->hw.active, pipe_config->hw.active);
8860 I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
8861 "transitional active state does not match atomic hw state "
8862 "(expected %i, found %i)\n",
8863 new_crtc_state->hw.active, crtc->active);
8865 if (new_crtc_state->bigjoiner_slave)
8866 master = new_crtc_state->bigjoiner_linked_crtc;
8868 for_each_encoder_on_crtc(dev, &master->base, encoder) {
8872 active = encoder->get_hw_state(encoder, &pipe);
8873 I915_STATE_WARN(active != new_crtc_state->hw.active,
8874 "[ENCODER:%i] active %i with crtc active %i\n",
8875 encoder->base.base.id, active,
8876 new_crtc_state->hw.active);
8878 I915_STATE_WARN(active && master->pipe != pipe,
8879 "Encoder connected to wrong pipe %c\n",
8883 intel_encoder_get_config(encoder, pipe_config);
8886 if (!new_crtc_state->hw.active)
8889 if (new_crtc_state->bigjoiner_slave)
8890 /* No PLLs set for slave */
8891 pipe_config->shared_dpll = NULL;
8893 intel_pipe_config_sanity_check(dev_priv, pipe_config);
8895 if (!intel_pipe_config_compare(new_crtc_state,
8896 pipe_config, false)) {
8897 I915_STATE_WARN(1, "pipe state doesn't match!\n");
8898 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
8899 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
8904 intel_verify_planes(struct intel_atomic_state *state)
8906 struct intel_plane *plane;
8907 const struct intel_plane_state *plane_state;
8910 for_each_new_intel_plane_in_state(state, plane,
8912 assert_plane(plane, plane_state->planar_slave ||
8913 plane_state->uapi.visible);
8917 verify_single_dpll_state(struct drm_i915_private *dev_priv,
8918 struct intel_shared_dpll *pll,
8919 struct intel_crtc *crtc,
8920 struct intel_crtc_state *new_crtc_state)
8922 struct intel_dpll_hw_state dpll_hw_state;
8926 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8928 drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
8930 active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
8932 if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
8933 I915_STATE_WARN(!pll->on && pll->active_mask,
8934 "pll in active use but not on in sw tracking\n");
8935 I915_STATE_WARN(pll->on && !pll->active_mask,
8936 "pll is on but not used by any active pipe\n");
8937 I915_STATE_WARN(pll->on != active,
8938 "pll on state mismatch (expected %i, found %i)\n",
8943 I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
8944 "more active pll users than references: 0x%x vs 0x%x\n",
8945 pll->active_mask, pll->state.pipe_mask);
8950 pipe_mask = BIT(crtc->pipe);
8952 if (new_crtc_state->hw.active)
8953 I915_STATE_WARN(!(pll->active_mask & pipe_mask),
8954 "pll active mismatch (expected pipe %c in active mask 0x%x)\n",
8955 pipe_name(crtc->pipe), pll->active_mask);
8957 I915_STATE_WARN(pll->active_mask & pipe_mask,
8958 "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
8959 pipe_name(crtc->pipe), pll->active_mask);
8961 I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
8962 "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
8963 pipe_mask, pll->state.pipe_mask);
8965 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
8967 sizeof(dpll_hw_state)),
8968 "pll hw state mismatch\n");
8972 verify_shared_dpll_state(struct intel_crtc *crtc,
8973 struct intel_crtc_state *old_crtc_state,
8974 struct intel_crtc_state *new_crtc_state)
8976 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8978 if (new_crtc_state->shared_dpll)
8979 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
8981 if (old_crtc_state->shared_dpll &&
8982 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
8983 u8 pipe_mask = BIT(crtc->pipe);
8984 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
8986 I915_STATE_WARN(pll->active_mask & pipe_mask,
8987 "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
8988 pipe_name(crtc->pipe), pll->active_mask);
8989 I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
8990 "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
8991 pipe_name(crtc->pipe), pll->state.pipe_mask);
8996 verify_mpllb_state(struct intel_atomic_state *state,
8997 struct intel_crtc_state *new_crtc_state)
8999 struct drm_i915_private *i915 = to_i915(state->base.dev);
9000 struct intel_mpllb_state mpllb_hw_state = { 0 };
9001 struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
9002 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
9003 struct intel_encoder *encoder;
9008 if (!new_crtc_state->hw.active)
9011 if (new_crtc_state->bigjoiner_slave)
9014 encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
9015 intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
9017 #define MPLLB_CHECK(name) do { \
9018 if (mpllb_sw_state->name != mpllb_hw_state.name) { \
9019 pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \
9020 "(expected 0x%08x, found 0x%08x)", \
9021 mpllb_sw_state->name, \
9022 mpllb_hw_state.name); \
9026 MPLLB_CHECK(mpllb_cp);
9027 MPLLB_CHECK(mpllb_div);
9028 MPLLB_CHECK(mpllb_div2);
9029 MPLLB_CHECK(mpllb_fracn1);
9030 MPLLB_CHECK(mpllb_fracn2);
9031 MPLLB_CHECK(mpllb_sscen);
9032 MPLLB_CHECK(mpllb_sscstep);
9035 * ref_control is handled by the hardware/firemware and never
9036 * programmed by the software, but the proper values are supplied
9037 * in the bspec for verification purposes.
9039 MPLLB_CHECK(ref_control);
9045 intel_modeset_verify_crtc(struct intel_crtc *crtc,
9046 struct intel_atomic_state *state,
9047 struct intel_crtc_state *old_crtc_state,
9048 struct intel_crtc_state *new_crtc_state)
9050 if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
9053 verify_wm_state(crtc, new_crtc_state);
9054 verify_connector_state(state, crtc);
9055 verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
9056 verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
9057 verify_mpllb_state(state, new_crtc_state);
9061 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
9065 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
9066 verify_single_dpll_state(dev_priv,
9067 &dev_priv->dpll.shared_dplls[i],
9072 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
9073 struct intel_atomic_state *state)
9075 verify_encoder_state(dev_priv, state);
9076 verify_connector_state(state, NULL);
9077 verify_disabled_dpll_state(dev_priv);
9080 int intel_modeset_all_pipes(struct intel_atomic_state *state)
9082 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9083 struct intel_crtc *crtc;
9086 * Add all pipes to the state, and force
9087 * a modeset on all the active ones.
9089 for_each_intel_crtc(&dev_priv->drm, crtc) {
9090 struct intel_crtc_state *crtc_state;
9093 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9094 if (IS_ERR(crtc_state))
9095 return PTR_ERR(crtc_state);
9097 if (!crtc_state->hw.active ||
9098 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
9101 crtc_state->uapi.mode_changed = true;
9103 ret = drm_atomic_add_affected_connectors(&state->base,
9108 ret = intel_atomic_add_affected_planes(state, crtc);
9112 crtc_state->update_planes |= crtc_state->active_planes;
9119 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
9121 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9122 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9123 struct drm_display_mode adjusted_mode =
9124 crtc_state->hw.adjusted_mode;
9126 if (crtc_state->vrr.enable) {
9127 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
9128 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
9129 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
9130 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
9133 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
9135 crtc->mode_flags = crtc_state->mode_flags;
9138 * The scanline counter increments at the leading edge of hsync.
9140 * On most platforms it starts counting from vtotal-1 on the
9141 * first active line. That means the scanline counter value is
9142 * always one less than what we would expect. Ie. just after
9143 * start of vblank, which also occurs at start of hsync (on the
9144 * last active line), the scanline counter will read vblank_start-1.
9146 * On gen2 the scanline counter starts counting from 1 instead
9147 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
9148 * to keep the value positive), instead of adding one.
9150 * On HSW+ the behaviour of the scanline counter depends on the output
9151 * type. For DP ports it behaves like most other platforms, but on HDMI
9152 * there's an extra 1 line difference. So we need to add two instead of
9155 * On VLV/CHV DSI the scanline counter would appear to increment
9156 * approx. 1/3 of a scanline before start of vblank. Unfortunately
9157 * that means we can't tell whether we're in vblank or not while
9158 * we're on that particular line. We must still set scanline_offset
9159 * to 1 so that the vblank timestamps come out correct when we query
9160 * the scanline counter from within the vblank interrupt handler.
9161 * However if queried just before the start of vblank we'll get an
9162 * answer that's slightly in the future.
9164 if (DISPLAY_VER(dev_priv) == 2) {
9167 vtotal = adjusted_mode.crtc_vtotal;
9168 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9171 crtc->scanline_offset = vtotal - 1;
9172 } else if (HAS_DDI(dev_priv) &&
9173 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
9174 crtc->scanline_offset = 2;
9176 crtc->scanline_offset = 1;
9180 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
9182 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9183 struct intel_crtc_state *new_crtc_state;
9184 struct intel_crtc *crtc;
9187 if (!dev_priv->display.crtc_compute_clock)
9190 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9191 if (!intel_crtc_needs_modeset(new_crtc_state))
9194 intel_release_shared_dplls(state, crtc);
9199 * This implements the workaround described in the "notes" section of the mode
9200 * set sequence documentation. When going from no pipes or single pipe to
9201 * multiple pipes, and planes are enabled after the pipe, we need to wait at
9202 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
9204 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
9206 struct intel_crtc_state *crtc_state;
9207 struct intel_crtc *crtc;
9208 struct intel_crtc_state *first_crtc_state = NULL;
9209 struct intel_crtc_state *other_crtc_state = NULL;
9210 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
9213 /* look at all crtc's that are going to be enabled in during modeset */
9214 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9215 if (!crtc_state->hw.active ||
9216 !intel_crtc_needs_modeset(crtc_state))
9219 if (first_crtc_state) {
9220 other_crtc_state = crtc_state;
9223 first_crtc_state = crtc_state;
9224 first_pipe = crtc->pipe;
9228 /* No workaround needed? */
9229 if (!first_crtc_state)
9232 /* w/a possibly needed, check how many crtc's are already enabled. */
9233 for_each_intel_crtc(state->base.dev, crtc) {
9234 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
9235 if (IS_ERR(crtc_state))
9236 return PTR_ERR(crtc_state);
9238 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
9240 if (!crtc_state->hw.active ||
9241 intel_crtc_needs_modeset(crtc_state))
9244 /* 2 or more enabled crtcs means no need for w/a */
9245 if (enabled_pipe != INVALID_PIPE)
9248 enabled_pipe = crtc->pipe;
9251 if (enabled_pipe != INVALID_PIPE)
9252 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
9253 else if (other_crtc_state)
9254 other_crtc_state->hsw_workaround_pipe = first_pipe;
9259 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
9262 const struct intel_crtc_state *crtc_state;
9263 struct intel_crtc *crtc;
9266 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9267 if (crtc_state->hw.active)
9268 active_pipes |= BIT(crtc->pipe);
9270 active_pipes &= ~BIT(crtc->pipe);
9273 return active_pipes;
9276 static int intel_modeset_checks(struct intel_atomic_state *state)
9278 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9280 state->modeset = true;
9282 if (IS_HASWELL(dev_priv))
9283 return hsw_mode_set_planes_workaround(state);
9289 * Handle calculation of various watermark data at the end of the atomic check
9290 * phase. The code here should be run after the per-crtc and per-plane 'check'
9291 * handlers to ensure that all derived state has been updated.
9293 static int calc_watermark_data(struct intel_atomic_state *state)
9295 struct drm_device *dev = state->base.dev;
9296 struct drm_i915_private *dev_priv = to_i915(dev);
9298 /* Is there platform-specific watermark information to calculate? */
9299 if (dev_priv->display.compute_global_watermarks)
9300 return dev_priv->display.compute_global_watermarks(state);
9305 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
9306 struct intel_crtc_state *new_crtc_state)
9308 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
9311 new_crtc_state->uapi.mode_changed = false;
9312 new_crtc_state->update_pipe = true;
9315 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
9316 struct intel_crtc_state *new_crtc_state)
9319 * If we're not doing the full modeset we want to
9320 * keep the current M/N values as they may be
9321 * sufficiently different to the computed values
9322 * to cause problems.
9324 * FIXME: should really copy more fuzzy state here
9326 new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
9327 new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
9328 new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
9329 new_crtc_state->has_drrs = old_crtc_state->has_drrs;
9332 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
9333 struct intel_crtc *crtc,
9336 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9337 struct intel_plane *plane;
9339 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
9340 struct intel_plane_state *plane_state;
9342 if ((plane_ids_mask & BIT(plane->id)) == 0)
9345 plane_state = intel_atomic_get_plane_state(state, plane);
9346 if (IS_ERR(plane_state))
9347 return PTR_ERR(plane_state);
9353 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
9354 struct intel_crtc *crtc)
9356 const struct intel_crtc_state *old_crtc_state =
9357 intel_atomic_get_old_crtc_state(state, crtc);
9358 const struct intel_crtc_state *new_crtc_state =
9359 intel_atomic_get_new_crtc_state(state, crtc);
9361 return intel_crtc_add_planes_to_state(state, crtc,
9362 old_crtc_state->enabled_planes |
9363 new_crtc_state->enabled_planes);
9366 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
9368 /* See {hsw,vlv,ivb}_plane_ratio() */
9369 return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
9370 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9371 IS_IVYBRIDGE(dev_priv);
9374 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
9375 struct intel_crtc *crtc,
9376 struct intel_crtc *other)
9378 const struct intel_plane_state *plane_state;
9379 struct intel_plane *plane;
9383 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9384 if (plane->pipe == crtc->pipe)
9385 plane_ids |= BIT(plane->id);
9388 return intel_crtc_add_planes_to_state(state, other, plane_ids);
9391 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
9393 const struct intel_crtc_state *crtc_state;
9394 struct intel_crtc *crtc;
9397 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9400 if (!crtc_state->bigjoiner)
9403 ret = intel_crtc_add_bigjoiner_planes(state, crtc,
9404 crtc_state->bigjoiner_linked_crtc);
9412 static int intel_atomic_check_planes(struct intel_atomic_state *state)
9414 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9415 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9416 struct intel_plane_state *plane_state;
9417 struct intel_plane *plane;
9418 struct intel_crtc *crtc;
9421 ret = icl_add_linked_planes(state);
9425 ret = intel_bigjoiner_add_affected_planes(state);
9429 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9430 ret = intel_plane_atomic_check(state, plane);
9432 drm_dbg_atomic(&dev_priv->drm,
9433 "[PLANE:%d:%s] atomic driver check failed\n",
9434 plane->base.base.id, plane->base.name);
9439 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9440 new_crtc_state, i) {
9441 u8 old_active_planes, new_active_planes;
9443 ret = icl_check_nv12_planes(new_crtc_state);
9448 * On some platforms the number of active planes affects
9449 * the planes' minimum cdclk calculation. Add such planes
9450 * to the state before we compute the minimum cdclk.
9452 if (!active_planes_affects_min_cdclk(dev_priv))
9455 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9456 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
9458 if (hweight8(old_active_planes) == hweight8(new_active_planes))
9461 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
9469 static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
9470 bool *need_cdclk_calc)
9472 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9473 const struct intel_cdclk_state *old_cdclk_state;
9474 const struct intel_cdclk_state *new_cdclk_state;
9475 struct intel_plane_state *plane_state;
9476 struct intel_bw_state *new_bw_state;
9477 struct intel_plane *plane;
9483 * active_planes bitmask has been updated, and potentially
9484 * affected planes are part of the state. We can now
9485 * compute the minimum cdclk for each plane.
9487 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
9488 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
9493 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
9494 new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
9496 if (new_cdclk_state &&
9497 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
9498 *need_cdclk_calc = true;
9500 ret = dev_priv->display.bw_calc_min_cdclk(state);
9504 new_bw_state = intel_atomic_get_new_bw_state(state);
9506 if (!new_cdclk_state || !new_bw_state)
9509 for_each_pipe(dev_priv, pipe) {
9510 min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk);
9513 * Currently do this change only if we need to increase
9515 if (new_bw_state->min_cdclk > min_cdclk)
9516 *need_cdclk_calc = true;
9522 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
9524 struct intel_crtc_state *crtc_state;
9525 struct intel_crtc *crtc;
9528 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9529 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
9532 ret = intel_crtc_atomic_check(state, crtc);
9534 drm_dbg_atomic(&i915->drm,
9535 "[CRTC:%d:%s] atomic driver check failed\n",
9536 crtc->base.base.id, crtc->base.name);
9544 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
9547 const struct intel_crtc_state *new_crtc_state;
9548 struct intel_crtc *crtc;
9551 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9552 if (new_crtc_state->hw.enable &&
9553 transcoders & BIT(new_crtc_state->cpu_transcoder) &&
9554 intel_crtc_needs_modeset(new_crtc_state))
9561 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
9562 struct intel_crtc *crtc,
9563 struct intel_crtc_state *old_crtc_state,
9564 struct intel_crtc_state *new_crtc_state)
9566 struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
9567 struct intel_crtc *slave, *master;
9569 /* slave being enabled, is master is still claiming this crtc? */
9570 if (old_crtc_state->bigjoiner_slave) {
9572 master = old_crtc_state->bigjoiner_linked_crtc;
9573 master_crtc_state = intel_atomic_get_new_crtc_state(state, master);
9574 if (!master_crtc_state || !intel_crtc_needs_modeset(master_crtc_state))
9578 if (!new_crtc_state->bigjoiner)
9581 slave = intel_dsc_get_bigjoiner_secondary(crtc);
9583 DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration requires "
9584 "CRTC + 1 to be used, doesn't exist\n",
9585 crtc->base.base.id, crtc->base.name);
9589 new_crtc_state->bigjoiner_linked_crtc = slave;
9590 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
9592 if (IS_ERR(slave_crtc_state))
9593 return PTR_ERR(slave_crtc_state);
9595 /* master being enabled, slave was already configured? */
9596 if (slave_crtc_state->uapi.enable)
9599 DRM_DEBUG_KMS("[CRTC:%d:%s] Used as slave for big joiner\n",
9600 slave->base.base.id, slave->base.name);
9602 return copy_bigjoiner_crtc_state(slave_crtc_state, new_crtc_state);
9605 DRM_DEBUG_KMS("[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
9606 "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
9607 slave->base.base.id, slave->base.name,
9608 master->base.base.id, master->base.name);
9612 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
9613 struct intel_crtc_state *master_crtc_state)
9615 struct intel_crtc_state *slave_crtc_state =
9616 intel_atomic_get_new_crtc_state(state, master_crtc_state->bigjoiner_linked_crtc);
9618 slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
9619 slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave = false;
9620 slave_crtc_state->bigjoiner_linked_crtc = master_crtc_state->bigjoiner_linked_crtc = NULL;
9621 intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
9625 * DOC: asynchronous flip implementation
9627 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
9628 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
9629 * Correspondingly, support is currently added for primary plane only.
9631 * Async flip can only change the plane surface address, so anything else
9632 * changing is rejected from the intel_atomic_check_async() function.
9633 * Once this check is cleared, flip done interrupt is enabled using
9634 * the intel_crtc_enable_flip_done() function.
9636 * As soon as the surface address register is written, flip done interrupt is
9637 * generated and the requested events are sent to the usersapce in the interrupt
9638 * handler itself. The timestamp and sequence sent during the flip done event
9639 * correspond to the last vblank and have no relation to the actual time when
9640 * the flip done event was sent.
9642 static int intel_atomic_check_async(struct intel_atomic_state *state)
9644 struct drm_i915_private *i915 = to_i915(state->base.dev);
9645 const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9646 const struct intel_plane_state *new_plane_state, *old_plane_state;
9647 struct intel_crtc *crtc;
9648 struct intel_plane *plane;
9651 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9652 new_crtc_state, i) {
9653 if (intel_crtc_needs_modeset(new_crtc_state)) {
9654 drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
9658 if (!new_crtc_state->hw.active) {
9659 drm_dbg_kms(&i915->drm, "CRTC inactive\n");
9662 if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
9663 drm_dbg_kms(&i915->drm,
9664 "Active planes cannot be changed during async flip\n");
9669 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
9670 new_plane_state, i) {
9672 * TODO: Async flip is only supported through the page flip IOCTL
9673 * as of now. So support currently added for primary plane only.
9674 * Support for other planes on platforms on which supports
9675 * this(vlv/chv and icl+) should be added when async flip is
9676 * enabled in the atomic IOCTL path.
9678 if (!plane->async_flip)
9682 * FIXME: This check is kept generic for all platforms.
9683 * Need to verify this for all gen9 platforms to enable
9684 * this selectively if required.
9686 switch (new_plane_state->hw.fb->modifier) {
9687 case I915_FORMAT_MOD_X_TILED:
9688 case I915_FORMAT_MOD_Y_TILED:
9689 case I915_FORMAT_MOD_Yf_TILED:
9692 drm_dbg_kms(&i915->drm,
9693 "Linear memory/CCS does not support async flips\n");
9697 if (old_plane_state->view.color_plane[0].stride !=
9698 new_plane_state->view.color_plane[0].stride) {
9699 drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
9703 if (old_plane_state->hw.fb->modifier !=
9704 new_plane_state->hw.fb->modifier) {
9705 drm_dbg_kms(&i915->drm,
9706 "Framebuffer modifiers cannot be changed in async flip\n");
9710 if (old_plane_state->hw.fb->format !=
9711 new_plane_state->hw.fb->format) {
9712 drm_dbg_kms(&i915->drm,
9713 "Framebuffer format cannot be changed in async flip\n");
9717 if (old_plane_state->hw.rotation !=
9718 new_plane_state->hw.rotation) {
9719 drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
9723 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
9724 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
9725 drm_dbg_kms(&i915->drm,
9726 "Plane size/co-ordinates cannot be changed in async flip\n");
9730 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
9731 drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
9735 if (old_plane_state->hw.pixel_blend_mode !=
9736 new_plane_state->hw.pixel_blend_mode) {
9737 drm_dbg_kms(&i915->drm,
9738 "Pixel blend mode cannot be changed in async flip\n");
9742 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
9743 drm_dbg_kms(&i915->drm,
9744 "Color encoding cannot be changed in async flip\n");
9748 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
9749 drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
9757 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
9759 struct intel_crtc_state *crtc_state;
9760 struct intel_crtc *crtc;
9763 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9764 struct intel_crtc_state *linked_crtc_state;
9765 struct intel_crtc *linked_crtc;
9768 if (!crtc_state->bigjoiner)
9771 linked_crtc = crtc_state->bigjoiner_linked_crtc;
9772 linked_crtc_state = intel_atomic_get_crtc_state(&state->base, linked_crtc);
9773 if (IS_ERR(linked_crtc_state))
9774 return PTR_ERR(linked_crtc_state);
9776 if (!intel_crtc_needs_modeset(crtc_state))
9779 linked_crtc_state->uapi.mode_changed = true;
9781 ret = drm_atomic_add_affected_connectors(&state->base,
9782 &linked_crtc->base);
9786 ret = intel_atomic_add_affected_planes(state, linked_crtc);
9791 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
9792 /* Kill old bigjoiner link, we may re-establish afterwards */
9793 if (intel_crtc_needs_modeset(crtc_state) &&
9794 crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)
9795 kill_bigjoiner_slave(state, crtc_state);
9802 * intel_atomic_check - validate state object
9804 * @_state: state to validate
9806 static int intel_atomic_check(struct drm_device *dev,
9807 struct drm_atomic_state *_state)
9809 struct drm_i915_private *dev_priv = to_i915(dev);
9810 struct intel_atomic_state *state = to_intel_atomic_state(_state);
9811 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
9812 struct intel_crtc *crtc;
9814 bool any_ms = false;
9816 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9817 new_crtc_state, i) {
9818 if (new_crtc_state->inherited != old_crtc_state->inherited)
9819 new_crtc_state->uapi.mode_changed = true;
9822 intel_vrr_check_modeset(state);
9824 ret = drm_atomic_helper_check_modeset(dev, &state->base);
9828 ret = intel_bigjoiner_add_affected_crtcs(state);
9832 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9833 new_crtc_state, i) {
9834 if (!intel_crtc_needs_modeset(new_crtc_state)) {
9836 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, new_crtc_state);
9841 if (!new_crtc_state->uapi.enable) {
9842 if (!new_crtc_state->bigjoiner_slave) {
9843 intel_crtc_copy_uapi_to_hw_state(state, new_crtc_state);
9849 ret = intel_crtc_prepare_cleared_state(state, new_crtc_state);
9853 ret = intel_modeset_pipe_config(state, new_crtc_state);
9857 ret = intel_atomic_check_bigjoiner(state, crtc, old_crtc_state,
9863 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9864 new_crtc_state, i) {
9865 if (!intel_crtc_needs_modeset(new_crtc_state))
9868 ret = intel_modeset_pipe_config_late(new_crtc_state);
9872 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
9876 * Check if fastset is allowed by external dependencies like other
9877 * pipes and transcoders.
9879 * Right now it only forces a fullmodeset when the MST master
9880 * transcoder did not changed but the pipe of the master transcoder
9881 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
9882 * in case of port synced crtcs, if one of the synced crtcs
9883 * needs a full modeset, all other synced crtcs should be
9884 * forced a full modeset.
9886 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
9887 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
9890 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
9891 enum transcoder master = new_crtc_state->mst_master_transcoder;
9893 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
9894 new_crtc_state->uapi.mode_changed = true;
9895 new_crtc_state->update_pipe = false;
9899 if (is_trans_port_sync_mode(new_crtc_state)) {
9900 u8 trans = new_crtc_state->sync_mode_slaves_mask;
9902 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
9903 trans |= BIT(new_crtc_state->master_transcoder);
9905 if (intel_cpu_transcoders_need_modeset(state, trans)) {
9906 new_crtc_state->uapi.mode_changed = true;
9907 new_crtc_state->update_pipe = false;
9911 if (new_crtc_state->bigjoiner) {
9912 struct intel_crtc_state *linked_crtc_state =
9913 intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc);
9915 if (intel_crtc_needs_modeset(linked_crtc_state)) {
9916 new_crtc_state->uapi.mode_changed = true;
9917 new_crtc_state->update_pipe = false;
9922 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9923 new_crtc_state, i) {
9924 if (intel_crtc_needs_modeset(new_crtc_state)) {
9929 if (!new_crtc_state->update_pipe)
9932 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
9935 if (any_ms && !check_digital_port_conflicts(state)) {
9936 drm_dbg_kms(&dev_priv->drm,
9937 "rejecting conflicting digital port configuration\n");
9942 ret = drm_dp_mst_atomic_check(&state->base);
9946 ret = intel_atomic_check_planes(state);
9950 intel_fbc_choose_crtc(dev_priv, state);
9951 ret = calc_watermark_data(state);
9955 ret = intel_bw_atomic_check(state);
9959 ret = intel_atomic_check_cdclk(state, &any_ms);
9963 if (intel_any_crtc_needs_modeset(state))
9967 ret = intel_modeset_checks(state);
9971 ret = intel_modeset_calc_cdclk(state);
9975 intel_modeset_clear_plls(state);
9978 ret = intel_atomic_check_crtcs(state);
9982 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
9983 new_crtc_state, i) {
9984 if (new_crtc_state->uapi.async_flip) {
9985 ret = intel_atomic_check_async(state);
9990 if (!intel_crtc_needs_modeset(new_crtc_state) &&
9991 !new_crtc_state->update_pipe)
9994 intel_dump_pipe_config(new_crtc_state, state,
9995 intel_crtc_needs_modeset(new_crtc_state) ?
9996 "[modeset]" : "[fastset]");
10002 if (ret == -EDEADLK)
10006 * FIXME would probably be nice to know which crtc specifically
10007 * caused the failure, in cases where we can pinpoint it.
10009 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10011 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
10016 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
10018 struct intel_crtc_state *crtc_state;
10019 struct intel_crtc *crtc;
10022 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
10026 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
10027 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
10029 if (mode_changed || crtc_state->update_pipe ||
10030 crtc_state->uapi.color_mgmt_changed) {
10031 intel_dsb_prepare(crtc_state);
10038 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
10039 struct intel_crtc_state *crtc_state)
10041 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10043 if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
10044 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10046 if (crtc_state->has_pch_encoder) {
10047 enum pipe pch_transcoder =
10048 intel_crtc_pch_transcoder(crtc);
10050 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
10054 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
10055 const struct intel_crtc_state *new_crtc_state)
10057 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
10058 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10061 * Update pipe size and adjust fitter if needed: the reason for this is
10062 * that in compute_mode_changes we check the native mode (not the pfit
10063 * mode) to see if we can flip rather than do a full mode set. In the
10064 * fastboot case, we'll flip, but if we don't update the pipesrc and
10065 * pfit state, we'll end up with a big fb scanned out into the wrong
10068 intel_set_pipe_src_size(new_crtc_state);
10070 /* on skylake this is done by detaching scalers */
10071 if (DISPLAY_VER(dev_priv) >= 9) {
10072 if (new_crtc_state->pch_pfit.enabled)
10073 skl_pfit_enable(new_crtc_state);
10074 } else if (HAS_PCH_SPLIT(dev_priv)) {
10075 if (new_crtc_state->pch_pfit.enabled)
10076 ilk_pfit_enable(new_crtc_state);
10077 else if (old_crtc_state->pch_pfit.enabled)
10078 ilk_pfit_disable(old_crtc_state);
10082 * The register is supposedly single buffered so perhaps
10083 * not 100% correct to do this here. But SKL+ calculate
10084 * this based on the adjust pixel rate so pfit changes do
10085 * affect it and so it must be updated for fastsets.
10086 * HSW/BDW only really need this here for fastboot, after
10087 * that the value should not change without a full modeset.
10089 if (DISPLAY_VER(dev_priv) >= 9 ||
10090 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
10091 hsw_set_linetime_wm(new_crtc_state);
10093 if (DISPLAY_VER(dev_priv) >= 11)
10094 icl_set_pipe_chicken(new_crtc_state);
10097 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
10098 struct intel_crtc *crtc)
10100 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10101 const struct intel_crtc_state *old_crtc_state =
10102 intel_atomic_get_old_crtc_state(state, crtc);
10103 const struct intel_crtc_state *new_crtc_state =
10104 intel_atomic_get_new_crtc_state(state, crtc);
10105 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10108 * During modesets pipe configuration was programmed as the
10109 * CRTC was enabled.
10112 if (new_crtc_state->uapi.color_mgmt_changed ||
10113 new_crtc_state->update_pipe)
10114 intel_color_commit(new_crtc_state);
10116 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
10117 bdw_set_pipemisc(new_crtc_state);
10119 if (new_crtc_state->update_pipe)
10120 intel_pipe_fastset(old_crtc_state, new_crtc_state);
10122 intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
10125 if (dev_priv->display.atomic_update_watermarks)
10126 dev_priv->display.atomic_update_watermarks(state, crtc);
10129 static void commit_pipe_post_planes(struct intel_atomic_state *state,
10130 struct intel_crtc *crtc)
10132 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10133 const struct intel_crtc_state *new_crtc_state =
10134 intel_atomic_get_new_crtc_state(state, crtc);
10137 * Disable the scaler(s) after the plane(s) so that we don't
10138 * get a catastrophic underrun even if the two operations
10139 * end up happening in two different frames.
10141 if (DISPLAY_VER(dev_priv) >= 9 &&
10142 !intel_crtc_needs_modeset(new_crtc_state))
10143 skl_detach_scalers(new_crtc_state);
10146 static void intel_enable_crtc(struct intel_atomic_state *state,
10147 struct intel_crtc *crtc)
10149 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10150 const struct intel_crtc_state *new_crtc_state =
10151 intel_atomic_get_new_crtc_state(state, crtc);
10153 if (!intel_crtc_needs_modeset(new_crtc_state))
10156 intel_crtc_update_active_timings(new_crtc_state);
10158 dev_priv->display.crtc_enable(state, crtc);
10160 if (new_crtc_state->bigjoiner_slave)
10163 /* vblanks work again, re-enable pipe CRC. */
10164 intel_crtc_enable_pipe_crc(crtc);
10167 static void intel_update_crtc(struct intel_atomic_state *state,
10168 struct intel_crtc *crtc)
10170 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10171 const struct intel_crtc_state *old_crtc_state =
10172 intel_atomic_get_old_crtc_state(state, crtc);
10173 struct intel_crtc_state *new_crtc_state =
10174 intel_atomic_get_new_crtc_state(state, crtc);
10175 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10178 if (new_crtc_state->preload_luts &&
10179 (new_crtc_state->uapi.color_mgmt_changed ||
10180 new_crtc_state->update_pipe))
10181 intel_color_load_luts(new_crtc_state);
10183 intel_pre_plane_update(state, crtc);
10185 if (new_crtc_state->update_pipe)
10186 intel_encoders_update_pipe(state, crtc);
10189 if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
10190 intel_fbc_disable(crtc);
10192 intel_fbc_enable(state, crtc);
10194 /* Perform vblank evasion around commit operation */
10195 intel_pipe_update_start(new_crtc_state);
10197 commit_pipe_pre_planes(state, crtc);
10199 if (DISPLAY_VER(dev_priv) >= 9)
10200 skl_update_planes_on_crtc(state, crtc);
10202 i9xx_update_planes_on_crtc(state, crtc);
10204 commit_pipe_post_planes(state, crtc);
10206 intel_pipe_update_end(new_crtc_state);
10209 * We usually enable FIFO underrun interrupts as part of the
10210 * CRTC enable sequence during modesets. But when we inherit a
10211 * valid pipe configuration from the BIOS we need to take care
10212 * of enabling them on the CRTC's first fastset.
10214 if (new_crtc_state->update_pipe && !modeset &&
10215 old_crtc_state->inherited)
10216 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
10219 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
10220 struct intel_crtc_state *old_crtc_state,
10221 struct intel_crtc_state *new_crtc_state,
10222 struct intel_crtc *crtc)
10224 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10226 drm_WARN_ON(&dev_priv->drm, old_crtc_state->bigjoiner_slave);
10228 intel_encoders_pre_disable(state, crtc);
10230 intel_crtc_disable_planes(state, crtc);
10233 * We still need special handling for disabling bigjoiner master
10234 * and slaves since for slave we do not have encoder or plls
10235 * so we dont need to disable those.
10237 if (old_crtc_state->bigjoiner) {
10238 intel_crtc_disable_planes(state,
10239 old_crtc_state->bigjoiner_linked_crtc);
10240 old_crtc_state->bigjoiner_linked_crtc->active = false;
10244 * We need to disable pipe CRC before disabling the pipe,
10245 * or we race against vblank off.
10247 intel_crtc_disable_pipe_crc(crtc);
10249 dev_priv->display.crtc_disable(state, crtc);
10250 crtc->active = false;
10251 intel_fbc_disable(crtc);
10252 intel_disable_shared_dpll(old_crtc_state);
10254 /* FIXME unify this for all platforms */
10255 if (!new_crtc_state->hw.active &&
10256 !HAS_GMCH(dev_priv) &&
10257 dev_priv->display.initial_watermarks)
10258 dev_priv->display.initial_watermarks(state, crtc);
10261 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
10263 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10264 struct intel_crtc *crtc;
10268 /* Only disable port sync and MST slaves */
10269 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10270 new_crtc_state, i) {
10271 if (!intel_crtc_needs_modeset(new_crtc_state) || old_crtc_state->bigjoiner)
10274 if (!old_crtc_state->hw.active)
10277 /* In case of Transcoder port Sync master slave CRTCs can be
10278 * assigned in any order and we need to make sure that
10279 * slave CRTCs are disabled first and then master CRTC since
10280 * Slave vblanks are masked till Master Vblanks.
10282 if (!is_trans_port_sync_slave(old_crtc_state) &&
10283 !intel_dp_mst_is_slave_trans(old_crtc_state))
10286 intel_pre_plane_update(state, crtc);
10287 intel_old_crtc_state_disables(state, old_crtc_state,
10288 new_crtc_state, crtc);
10289 handled |= BIT(crtc->pipe);
10292 /* Disable everything else left on */
10293 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10294 new_crtc_state, i) {
10295 if (!intel_crtc_needs_modeset(new_crtc_state) ||
10296 (handled & BIT(crtc->pipe)) ||
10297 old_crtc_state->bigjoiner_slave)
10300 intel_pre_plane_update(state, crtc);
10301 if (old_crtc_state->bigjoiner) {
10302 struct intel_crtc *slave =
10303 old_crtc_state->bigjoiner_linked_crtc;
10305 intel_pre_plane_update(state, slave);
10308 if (old_crtc_state->hw.active)
10309 intel_old_crtc_state_disables(state, old_crtc_state,
10310 new_crtc_state, crtc);
10314 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
10316 struct intel_crtc_state *new_crtc_state;
10317 struct intel_crtc *crtc;
10320 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10321 if (!new_crtc_state->hw.active)
10324 intel_enable_crtc(state, crtc);
10325 intel_update_crtc(state, crtc);
10329 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
10331 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
10332 struct intel_crtc *crtc;
10333 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10334 struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
10335 u8 update_pipes = 0, modeset_pipes = 0;
10338 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10339 enum pipe pipe = crtc->pipe;
10341 if (!new_crtc_state->hw.active)
10344 /* ignore allocations for crtc's that have been turned off. */
10345 if (!intel_crtc_needs_modeset(new_crtc_state)) {
10346 entries[pipe] = old_crtc_state->wm.skl.ddb;
10347 update_pipes |= BIT(pipe);
10349 modeset_pipes |= BIT(pipe);
10354 * Whenever the number of active pipes changes, we need to make sure we
10355 * update the pipes in the right order so that their ddb allocations
10356 * never overlap with each other between CRTC updates. Otherwise we'll
10357 * cause pipe underruns and other bad stuff.
10359 * So first lets enable all pipes that do not need a fullmodeset as
10360 * those don't have any external dependency.
10362 while (update_pipes) {
10363 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10364 new_crtc_state, i) {
10365 enum pipe pipe = crtc->pipe;
10367 if ((update_pipes & BIT(pipe)) == 0)
10370 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10371 entries, I915_MAX_PIPES, pipe))
10374 entries[pipe] = new_crtc_state->wm.skl.ddb;
10375 update_pipes &= ~BIT(pipe);
10377 intel_update_crtc(state, crtc);
10380 * If this is an already active pipe, it's DDB changed,
10381 * and this isn't the last pipe that needs updating
10382 * then we need to wait for a vblank to pass for the
10383 * new ddb allocation to take effect.
10385 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
10386 &old_crtc_state->wm.skl.ddb) &&
10387 (update_pipes | modeset_pipes))
10388 intel_wait_for_vblank(dev_priv, pipe);
10392 update_pipes = modeset_pipes;
10395 * Enable all pipes that needs a modeset and do not depends on other
10398 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10399 enum pipe pipe = crtc->pipe;
10401 if ((modeset_pipes & BIT(pipe)) == 0)
10404 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
10405 is_trans_port_sync_master(new_crtc_state) ||
10406 (new_crtc_state->bigjoiner && !new_crtc_state->bigjoiner_slave))
10409 modeset_pipes &= ~BIT(pipe);
10411 intel_enable_crtc(state, crtc);
10415 * Then we enable all remaining pipes that depend on other
10416 * pipes: MST slaves and port sync masters, big joiner master
10418 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10419 enum pipe pipe = crtc->pipe;
10421 if ((modeset_pipes & BIT(pipe)) == 0)
10424 modeset_pipes &= ~BIT(pipe);
10426 intel_enable_crtc(state, crtc);
10430 * Finally we do the plane updates/etc. for all pipes that got enabled.
10432 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10433 enum pipe pipe = crtc->pipe;
10435 if ((update_pipes & BIT(pipe)) == 0)
10438 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
10439 entries, I915_MAX_PIPES, pipe));
10441 entries[pipe] = new_crtc_state->wm.skl.ddb;
10442 update_pipes &= ~BIT(pipe);
10444 intel_update_crtc(state, crtc);
10447 drm_WARN_ON(&dev_priv->drm, modeset_pipes);
10448 drm_WARN_ON(&dev_priv->drm, update_pipes);
10451 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
10453 struct intel_atomic_state *state, *next;
10454 struct llist_node *freed;
10456 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
10457 llist_for_each_entry_safe(state, next, freed, freed)
10458 drm_atomic_state_put(&state->base);
10461 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
10463 struct drm_i915_private *dev_priv =
10464 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
10466 intel_atomic_helper_free_state(dev_priv);
10469 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
10471 struct wait_queue_entry wait_fence, wait_reset;
10472 struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
10474 init_wait_entry(&wait_fence, 0);
10475 init_wait_entry(&wait_reset, 0);
10477 prepare_to_wait(&intel_state->commit_ready.wait,
10478 &wait_fence, TASK_UNINTERRUPTIBLE);
10479 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10480 I915_RESET_MODESET),
10481 &wait_reset, TASK_UNINTERRUPTIBLE);
10484 if (i915_sw_fence_done(&intel_state->commit_ready) ||
10485 test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
10490 finish_wait(&intel_state->commit_ready.wait, &wait_fence);
10491 finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
10492 I915_RESET_MODESET),
10496 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
10498 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
10499 struct intel_crtc *crtc;
10502 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10504 intel_dsb_cleanup(old_crtc_state);
10507 static void intel_atomic_cleanup_work(struct work_struct *work)
10509 struct intel_atomic_state *state =
10510 container_of(work, struct intel_atomic_state, base.commit_work);
10511 struct drm_i915_private *i915 = to_i915(state->base.dev);
10513 intel_cleanup_dsbs(state);
10514 drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
10515 drm_atomic_helper_commit_cleanup_done(&state->base);
10516 drm_atomic_state_put(&state->base);
10518 intel_atomic_helper_free_state(i915);
10521 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
10523 struct drm_i915_private *i915 = to_i915(state->base.dev);
10524 struct intel_plane *plane;
10525 struct intel_plane_state *plane_state;
10528 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
10529 struct drm_framebuffer *fb = plane_state->hw.fb;
10533 fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
10537 * The layout of the fast clear color value expected by HW
10538 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2):
10539 * - 4 x 4 bytes per-channel value
10540 * (in surface type specific float/int format provided by the fb user)
10541 * - 8 bytes native color value used by the display
10542 * (converted/written by GPU during a fast clear operation using the
10543 * above per-channel values)
10545 * The commit's FB prepare hook already ensured that FB obj is pinned and the
10546 * caller made sure that the object is synced wrt. the related color clear value
10549 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
10550 fb->offsets[2] + 16,
10551 &plane_state->ccval,
10552 sizeof(plane_state->ccval));
10553 /* The above could only fail if the FB obj has an unexpected backing store type. */
10554 drm_WARN_ON(&i915->drm, ret);
10558 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
10560 struct drm_device *dev = state->base.dev;
10561 struct drm_i915_private *dev_priv = to_i915(dev);
10562 struct intel_crtc_state *new_crtc_state, *old_crtc_state;
10563 struct intel_crtc *crtc;
10564 u64 put_domains[I915_MAX_PIPES] = {};
10565 intel_wakeref_t wakeref = 0;
10568 intel_atomic_commit_fence_wait(state);
10570 drm_atomic_helper_wait_for_dependencies(&state->base);
10572 if (state->modeset)
10573 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
10575 intel_atomic_prepare_plane_clear_colors(state);
10577 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10578 new_crtc_state, i) {
10579 if (intel_crtc_needs_modeset(new_crtc_state) ||
10580 new_crtc_state->update_pipe) {
10582 put_domains[crtc->pipe] =
10583 modeset_get_crtc_power_domains(new_crtc_state);
10587 intel_commit_modeset_disables(state);
10589 /* FIXME: Eventually get rid of our crtc->config pointer */
10590 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10591 crtc->config = new_crtc_state;
10593 if (state->modeset) {
10594 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
10596 intel_set_cdclk_pre_plane_update(state);
10598 intel_modeset_verify_disabled(dev_priv, state);
10601 intel_sagv_pre_plane_update(state);
10603 /* Complete the events for pipes that have now been disabled */
10604 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10605 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
10607 /* Complete events for now disable pipes here. */
10608 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
10609 spin_lock_irq(&dev->event_lock);
10610 drm_crtc_send_vblank_event(&crtc->base,
10611 new_crtc_state->uapi.event);
10612 spin_unlock_irq(&dev->event_lock);
10614 new_crtc_state->uapi.event = NULL;
10618 if (state->modeset)
10619 intel_encoders_update_prepare(state);
10621 intel_dbuf_pre_plane_update(state);
10623 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10624 if (new_crtc_state->uapi.async_flip)
10625 intel_crtc_enable_flip_done(state, crtc);
10628 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10629 dev_priv->display.commit_modeset_enables(state);
10631 if (state->modeset) {
10632 intel_encoders_update_complete(state);
10634 intel_set_cdclk_post_plane_update(state);
10637 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
10638 * already, but still need the state for the delayed optimization. To
10640 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
10641 * - schedule that vblank worker _before_ calling hw_done
10642 * - at the start of commit_tail, cancel it _synchrously
10643 * - switch over to the vblank wait helper in the core after that since
10644 * we don't need out special handling any more.
10646 drm_atomic_helper_wait_for_flip_done(dev, &state->base);
10648 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
10649 if (new_crtc_state->uapi.async_flip)
10650 intel_crtc_disable_flip_done(state, crtc);
10652 if (new_crtc_state->hw.active &&
10653 !intel_crtc_needs_modeset(new_crtc_state) &&
10654 !new_crtc_state->preload_luts &&
10655 (new_crtc_state->uapi.color_mgmt_changed ||
10656 new_crtc_state->update_pipe))
10657 intel_color_load_luts(new_crtc_state);
10661 * Now that the vblank has passed, we can go ahead and program the
10662 * optimal watermarks on platforms that need two-step watermark
10665 * TODO: Move this (and other cleanup) to an async worker eventually.
10667 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
10668 new_crtc_state, i) {
10670 * Gen2 reports pipe underruns whenever all planes are disabled.
10671 * So re-enable underrun reporting after some planes get enabled.
10673 * We do this before .optimize_watermarks() so that we have a
10674 * chance of catching underruns with the intermediate watermarks
10675 * vs. the new plane configuration.
10677 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
10678 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
10680 if (dev_priv->display.optimize_watermarks)
10681 dev_priv->display.optimize_watermarks(state, crtc);
10684 intel_dbuf_post_plane_update(state);
10686 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10687 intel_post_plane_update(state, crtc);
10689 modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
10691 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
10694 * DSB cleanup is done in cleanup_work aligning with framebuffer
10695 * cleanup. So copy and reset the dsb structure to sync with
10696 * commit_done and later do dsb cleanup in cleanup_work.
10698 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
10701 /* Underruns don't always raise interrupts, so check manually */
10702 intel_check_cpu_fifo_underruns(dev_priv);
10703 intel_check_pch_fifo_underruns(dev_priv);
10705 if (state->modeset)
10706 intel_verify_planes(state);
10708 intel_sagv_post_plane_update(state);
10710 drm_atomic_helper_commit_hw_done(&state->base);
10712 if (state->modeset) {
10713 /* As one of the primary mmio accessors, KMS has a high
10714 * likelihood of triggering bugs in unclaimed access. After we
10715 * finish modesetting, see if an error has been flagged, and if
10716 * so enable debugging for the next modeset - and hope we catch
10719 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
10720 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
10722 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10725 * Defer the cleanup of the old state to a separate worker to not
10726 * impede the current task (userspace for blocking modesets) that
10727 * are executed inline. For out-of-line asynchronous modesets/flips,
10728 * deferring to a new worker seems overkill, but we would place a
10729 * schedule point (cond_resched()) here anyway to keep latencies
10732 INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
10733 queue_work(system_highpri_wq, &state->base.commit_work);
10736 static void intel_atomic_commit_work(struct work_struct *work)
10738 struct intel_atomic_state *state =
10739 container_of(work, struct intel_atomic_state, base.commit_work);
10741 intel_atomic_commit_tail(state);
10744 static int __i915_sw_fence_call
10745 intel_atomic_commit_ready(struct i915_sw_fence *fence,
10746 enum i915_sw_fence_notify notify)
10748 struct intel_atomic_state *state =
10749 container_of(fence, struct intel_atomic_state, commit_ready);
10752 case FENCE_COMPLETE:
10753 /* we do blocking waits in the worker, nothing to do here */
10757 struct intel_atomic_helper *helper =
10758 &to_i915(state->base.dev)->atomic_helper;
10760 if (llist_add(&state->freed, &helper->free_list))
10761 schedule_work(&helper->free_work);
10766 return NOTIFY_DONE;
10769 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
10771 struct intel_plane_state *old_plane_state, *new_plane_state;
10772 struct intel_plane *plane;
10775 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
10776 new_plane_state, i)
10777 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
10778 to_intel_frontbuffer(new_plane_state->hw.fb),
10779 plane->frontbuffer_bit);
10782 static int intel_atomic_commit(struct drm_device *dev,
10783 struct drm_atomic_state *_state,
10786 struct intel_atomic_state *state = to_intel_atomic_state(_state);
10787 struct drm_i915_private *dev_priv = to_i915(dev);
10790 state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
10792 drm_atomic_state_get(&state->base);
10793 i915_sw_fence_init(&state->commit_ready,
10794 intel_atomic_commit_ready);
10797 * The intel_legacy_cursor_update() fast path takes care
10798 * of avoiding the vblank waits for simple cursor
10799 * movement and flips. For cursor on/off and size changes,
10800 * we want to perform the vblank waits so that watermark
10801 * updates happen during the correct frames. Gen9+ have
10802 * double buffered watermarks and so shouldn't need this.
10804 * Unset state->legacy_cursor_update before the call to
10805 * drm_atomic_helper_setup_commit() because otherwise
10806 * drm_atomic_helper_wait_for_flip_done() is a noop and
10807 * we get FIFO underruns because we didn't wait
10810 * FIXME doing watermarks and fb cleanup from a vblank worker
10811 * (assuming we had any) would solve these problems.
10813 if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
10814 struct intel_crtc_state *new_crtc_state;
10815 struct intel_crtc *crtc;
10818 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10819 if (new_crtc_state->wm.need_postvbl_update ||
10820 new_crtc_state->update_wm_post)
10821 state->base.legacy_cursor_update = false;
10824 ret = intel_atomic_prepare_commit(state);
10826 drm_dbg_atomic(&dev_priv->drm,
10827 "Preparing state failed with %i\n", ret);
10828 i915_sw_fence_commit(&state->commit_ready);
10829 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10833 ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
10835 ret = drm_atomic_helper_swap_state(&state->base, true);
10837 intel_atomic_swap_global_state(state);
10840 struct intel_crtc_state *new_crtc_state;
10841 struct intel_crtc *crtc;
10844 i915_sw_fence_commit(&state->commit_ready);
10846 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
10847 intel_dsb_cleanup(new_crtc_state);
10849 drm_atomic_helper_cleanup_planes(dev, &state->base);
10850 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
10853 intel_shared_dpll_swap_state(state);
10854 intel_atomic_track_fbs(state);
10856 drm_atomic_state_get(&state->base);
10857 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
10859 i915_sw_fence_commit(&state->commit_ready);
10860 if (nonblock && state->modeset) {
10861 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
10862 } else if (nonblock) {
10863 queue_work(dev_priv->flip_wq, &state->base.commit_work);
10865 if (state->modeset)
10866 flush_workqueue(dev_priv->modeset_wq);
10867 intel_atomic_commit_tail(state);
10873 struct wait_rps_boost {
10874 struct wait_queue_entry wait;
10876 struct drm_crtc *crtc;
10877 struct i915_request *request;
10880 static int do_rps_boost(struct wait_queue_entry *_wait,
10881 unsigned mode, int sync, void *key)
10883 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
10884 struct i915_request *rq = wait->request;
10887 * If we missed the vblank, but the request is already running it
10888 * is reasonable to assume that it will complete before the next
10889 * vblank without our intervention, so leave RPS alone.
10891 if (!i915_request_started(rq))
10892 intel_rps_boost(rq);
10893 i915_request_put(rq);
10895 drm_crtc_vblank_put(wait->crtc);
10897 list_del(&wait->wait.entry);
10902 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
10903 struct dma_fence *fence)
10905 struct wait_rps_boost *wait;
10907 if (!dma_fence_is_i915(fence))
10910 if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
10913 if (drm_crtc_vblank_get(crtc))
10916 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
10918 drm_crtc_vblank_put(crtc);
10922 wait->request = to_request(dma_fence_get(fence));
10925 wait->wait.func = do_rps_boost;
10926 wait->wait.flags = 0;
10928 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
10931 int intel_plane_pin_fb(struct intel_plane_state *plane_state)
10933 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
10934 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
10935 struct drm_framebuffer *fb = plane_state->hw.fb;
10936 struct i915_vma *vma;
10938 plane->id == PLANE_CURSOR &&
10939 INTEL_INFO(dev_priv)->display.cursor_needs_physical;
10941 if (!intel_fb_uses_dpt(fb)) {
10942 vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
10943 &plane_state->view.gtt,
10944 intel_plane_uses_fence(plane_state),
10945 &plane_state->flags);
10947 return PTR_ERR(vma);
10949 plane_state->ggtt_vma = vma;
10951 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10953 vma = intel_dpt_pin(intel_fb->dpt_vm);
10955 return PTR_ERR(vma);
10957 plane_state->ggtt_vma = vma;
10959 vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
10960 &plane_state->flags, intel_fb->dpt_vm);
10962 intel_dpt_unpin(intel_fb->dpt_vm);
10963 plane_state->ggtt_vma = NULL;
10964 return PTR_ERR(vma);
10967 plane_state->dpt_vma = vma;
10969 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
10975 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
10977 struct drm_framebuffer *fb = old_plane_state->hw.fb;
10978 struct i915_vma *vma;
10980 if (!intel_fb_uses_dpt(fb)) {
10981 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
10983 intel_unpin_fb_vma(vma, old_plane_state->flags);
10985 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10987 vma = fetch_and_zero(&old_plane_state->dpt_vma);
10989 intel_unpin_fb_vma(vma, old_plane_state->flags);
10991 vma = fetch_and_zero(&old_plane_state->ggtt_vma);
10993 intel_dpt_unpin(intel_fb->dpt_vm);
10998 * intel_prepare_plane_fb - Prepare fb for usage on plane
10999 * @_plane: drm plane to prepare for
11000 * @_new_plane_state: the plane state being prepared
11002 * Prepares a framebuffer for usage on a display plane. Generally this
11003 * involves pinning the underlying object and updating the frontbuffer tracking
11004 * bits. Some older platforms need special physical address handling for
11007 * Returns 0 on success, negative error code on failure.
11010 intel_prepare_plane_fb(struct drm_plane *_plane,
11011 struct drm_plane_state *_new_plane_state)
11013 struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
11014 struct intel_plane *plane = to_intel_plane(_plane);
11015 struct intel_plane_state *new_plane_state =
11016 to_intel_plane_state(_new_plane_state);
11017 struct intel_atomic_state *state =
11018 to_intel_atomic_state(new_plane_state->uapi.state);
11019 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11020 const struct intel_plane_state *old_plane_state =
11021 intel_atomic_get_old_plane_state(state, plane);
11022 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
11023 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
11027 const struct intel_crtc_state *crtc_state =
11028 intel_atomic_get_new_crtc_state(state,
11029 to_intel_crtc(old_plane_state->hw.crtc));
11031 /* Big Hammer, we also need to ensure that any pending
11032 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
11033 * current scanout is retired before unpinning the old
11034 * framebuffer. Note that we rely on userspace rendering
11035 * into the buffer attached to the pipe they are waiting
11036 * on. If not, userspace generates a GPU hang with IPEHR
11037 * point to the MI_WAIT_FOR_EVENT.
11039 * This should only fail upon a hung GPU, in which case we
11040 * can safely continue.
11042 if (intel_crtc_needs_modeset(crtc_state)) {
11043 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11044 old_obj->base.resv, NULL,
11052 if (new_plane_state->uapi.fence) { /* explicit fencing */
11053 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
11055 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
11056 new_plane_state->uapi.fence,
11057 i915_fence_timeout(dev_priv),
11067 ret = intel_plane_pin_fb(new_plane_state);
11071 i915_gem_object_wait_priority(obj, 0, &attr);
11072 i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
11074 if (!new_plane_state->uapi.fence) { /* implicit fencing */
11075 struct dma_fence *fence;
11077 ret = i915_sw_fence_await_reservation(&state->commit_ready,
11078 obj->base.resv, NULL,
11080 i915_fence_timeout(dev_priv),
11085 fence = dma_resv_get_excl_unlocked(obj->base.resv);
11087 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11089 dma_fence_put(fence);
11092 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
11093 new_plane_state->uapi.fence);
11097 * We declare pageflips to be interactive and so merit a small bias
11098 * towards upclocking to deliver the frame on time. By only changing
11099 * the RPS thresholds to sample more regularly and aim for higher
11100 * clocks we can hopefully deliver low power workloads (like kodi)
11101 * that are not quite steady state without resorting to forcing
11102 * maximum clocks following a vblank miss (see do_rps_boost()).
11104 if (!state->rps_interactive) {
11105 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
11106 state->rps_interactive = true;
11112 intel_plane_unpin_fb(new_plane_state);
11118 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11119 * @plane: drm plane to clean up for
11120 * @_old_plane_state: the state from the previous modeset
11122 * Cleans up a framebuffer that has just been removed from a plane.
11125 intel_cleanup_plane_fb(struct drm_plane *plane,
11126 struct drm_plane_state *_old_plane_state)
11128 struct intel_plane_state *old_plane_state =
11129 to_intel_plane_state(_old_plane_state);
11130 struct intel_atomic_state *state =
11131 to_intel_atomic_state(old_plane_state->uapi.state);
11132 struct drm_i915_private *dev_priv = to_i915(plane->dev);
11133 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
11138 if (state->rps_interactive) {
11139 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
11140 state->rps_interactive = false;
11143 /* Should only be called after a successful intel_prepare_plane_fb()! */
11144 intel_plane_unpin_fb(old_plane_state);
11148 * intel_plane_destroy - destroy a plane
11149 * @plane: plane to destroy
11151 * Common destruction function for all types of planes (primary, cursor,
11154 void intel_plane_destroy(struct drm_plane *plane)
11156 drm_plane_cleanup(plane);
11157 kfree(to_intel_plane(plane));
11160 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
11162 struct intel_plane *plane;
11164 for_each_intel_plane(&dev_priv->drm, plane) {
11165 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
11168 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
11173 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
11174 struct drm_file *file)
11176 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11177 struct drm_crtc *drmmode_crtc;
11178 struct intel_crtc *crtc;
11180 drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
11184 crtc = to_intel_crtc(drmmode_crtc);
11185 pipe_from_crtc_id->pipe = crtc->pipe;
11190 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
11192 struct drm_device *dev = encoder->base.dev;
11193 struct intel_encoder *source_encoder;
11194 u32 possible_clones = 0;
11196 for_each_intel_encoder(dev, source_encoder) {
11197 if (encoders_cloneable(encoder, source_encoder))
11198 possible_clones |= drm_encoder_mask(&source_encoder->base);
11201 return possible_clones;
11204 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
11206 struct drm_device *dev = encoder->base.dev;
11207 struct intel_crtc *crtc;
11208 u32 possible_crtcs = 0;
11210 for_each_intel_crtc(dev, crtc) {
11211 if (encoder->pipe_mask & BIT(crtc->pipe))
11212 possible_crtcs |= drm_crtc_mask(&crtc->base);
11215 return possible_crtcs;
11218 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
11220 if (!IS_MOBILE(dev_priv))
11223 if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
11226 if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
11232 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
11234 if (DISPLAY_VER(dev_priv) >= 9)
11237 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
11240 if (HAS_PCH_LPT_H(dev_priv) &&
11241 intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
11244 /* DDI E can't be used if DDI A requires 4 lanes */
11245 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
11248 if (!dev_priv->vbt.int_crt_support)
11254 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
11256 struct intel_encoder *encoder;
11257 bool dpd_is_edp = false;
11259 intel_pps_unlock_regs_wa(dev_priv);
11261 if (!HAS_DISPLAY(dev_priv))
11264 if (IS_DG2(dev_priv)) {
11265 intel_ddi_init(dev_priv, PORT_A);
11266 intel_ddi_init(dev_priv, PORT_B);
11267 intel_ddi_init(dev_priv, PORT_C);
11268 intel_ddi_init(dev_priv, PORT_D_XELPD);
11269 } else if (IS_ALDERLAKE_P(dev_priv)) {
11270 intel_ddi_init(dev_priv, PORT_A);
11271 intel_ddi_init(dev_priv, PORT_B);
11272 intel_ddi_init(dev_priv, PORT_TC1);
11273 intel_ddi_init(dev_priv, PORT_TC2);
11274 intel_ddi_init(dev_priv, PORT_TC3);
11275 intel_ddi_init(dev_priv, PORT_TC4);
11276 } else if (IS_ALDERLAKE_S(dev_priv)) {
11277 intel_ddi_init(dev_priv, PORT_A);
11278 intel_ddi_init(dev_priv, PORT_TC1);
11279 intel_ddi_init(dev_priv, PORT_TC2);
11280 intel_ddi_init(dev_priv, PORT_TC3);
11281 intel_ddi_init(dev_priv, PORT_TC4);
11282 } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
11283 intel_ddi_init(dev_priv, PORT_A);
11284 intel_ddi_init(dev_priv, PORT_B);
11285 intel_ddi_init(dev_priv, PORT_TC1);
11286 intel_ddi_init(dev_priv, PORT_TC2);
11287 } else if (DISPLAY_VER(dev_priv) >= 12) {
11288 intel_ddi_init(dev_priv, PORT_A);
11289 intel_ddi_init(dev_priv, PORT_B);
11290 intel_ddi_init(dev_priv, PORT_TC1);
11291 intel_ddi_init(dev_priv, PORT_TC2);
11292 intel_ddi_init(dev_priv, PORT_TC3);
11293 intel_ddi_init(dev_priv, PORT_TC4);
11294 intel_ddi_init(dev_priv, PORT_TC5);
11295 intel_ddi_init(dev_priv, PORT_TC6);
11296 icl_dsi_init(dev_priv);
11297 } else if (IS_JSL_EHL(dev_priv)) {
11298 intel_ddi_init(dev_priv, PORT_A);
11299 intel_ddi_init(dev_priv, PORT_B);
11300 intel_ddi_init(dev_priv, PORT_C);
11301 intel_ddi_init(dev_priv, PORT_D);
11302 icl_dsi_init(dev_priv);
11303 } else if (DISPLAY_VER(dev_priv) == 11) {
11304 intel_ddi_init(dev_priv, PORT_A);
11305 intel_ddi_init(dev_priv, PORT_B);
11306 intel_ddi_init(dev_priv, PORT_C);
11307 intel_ddi_init(dev_priv, PORT_D);
11308 intel_ddi_init(dev_priv, PORT_E);
11309 intel_ddi_init(dev_priv, PORT_F);
11310 icl_dsi_init(dev_priv);
11311 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
11312 intel_ddi_init(dev_priv, PORT_A);
11313 intel_ddi_init(dev_priv, PORT_B);
11314 intel_ddi_init(dev_priv, PORT_C);
11315 vlv_dsi_init(dev_priv);
11316 } else if (DISPLAY_VER(dev_priv) >= 9) {
11317 intel_ddi_init(dev_priv, PORT_A);
11318 intel_ddi_init(dev_priv, PORT_B);
11319 intel_ddi_init(dev_priv, PORT_C);
11320 intel_ddi_init(dev_priv, PORT_D);
11321 intel_ddi_init(dev_priv, PORT_E);
11322 } else if (HAS_DDI(dev_priv)) {
11325 if (intel_ddi_crt_present(dev_priv))
11326 intel_crt_init(dev_priv);
11328 /* Haswell uses DDI functions to detect digital outputs. */
11329 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
11331 intel_ddi_init(dev_priv, PORT_A);
11333 found = intel_de_read(dev_priv, SFUSE_STRAP);
11334 if (found & SFUSE_STRAP_DDIB_DETECTED)
11335 intel_ddi_init(dev_priv, PORT_B);
11336 if (found & SFUSE_STRAP_DDIC_DETECTED)
11337 intel_ddi_init(dev_priv, PORT_C);
11338 if (found & SFUSE_STRAP_DDID_DETECTED)
11339 intel_ddi_init(dev_priv, PORT_D);
11340 if (found & SFUSE_STRAP_DDIF_DETECTED)
11341 intel_ddi_init(dev_priv, PORT_F);
11342 } else if (HAS_PCH_SPLIT(dev_priv)) {
11346 * intel_edp_init_connector() depends on this completing first,
11347 * to prevent the registration of both eDP and LVDS and the
11348 * incorrect sharing of the PPS.
11350 intel_lvds_init(dev_priv);
11351 intel_crt_init(dev_priv);
11353 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
11355 if (ilk_has_edp_a(dev_priv))
11356 g4x_dp_init(dev_priv, DP_A, PORT_A);
11358 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
11359 /* PCH SDVOB multiplex with HDMIB */
11360 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
11362 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
11363 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
11364 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
11367 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
11368 g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
11370 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
11371 g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
11373 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
11374 g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
11376 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
11377 g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
11378 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
11379 bool has_edp, has_port;
11381 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
11382 intel_crt_init(dev_priv);
11385 * The DP_DETECTED bit is the latched state of the DDC
11386 * SDA pin at boot. However since eDP doesn't require DDC
11387 * (no way to plug in a DP->HDMI dongle) the DDC pins for
11388 * eDP ports may have been muxed to an alternate function.
11389 * Thus we can't rely on the DP_DETECTED bit alone to detect
11390 * eDP ports. Consult the VBT as well as DP_DETECTED to
11391 * detect eDP ports.
11393 * Sadly the straps seem to be missing sometimes even for HDMI
11394 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
11395 * and VBT for the presence of the port. Additionally we can't
11396 * trust the port type the VBT declares as we've seen at least
11397 * HDMI ports that the VBT claim are DP or eDP.
11399 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
11400 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
11401 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
11402 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
11403 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
11404 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
11406 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
11407 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
11408 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
11409 has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
11410 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
11411 g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
11413 if (IS_CHERRYVIEW(dev_priv)) {
11415 * eDP not supported on port D,
11416 * so no need to worry about it
11418 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
11419 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
11420 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
11421 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
11422 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
11425 vlv_dsi_init(dev_priv);
11426 } else if (IS_PINEVIEW(dev_priv)) {
11427 intel_lvds_init(dev_priv);
11428 intel_crt_init(dev_priv);
11429 } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
11430 bool found = false;
11432 if (IS_MOBILE(dev_priv))
11433 intel_lvds_init(dev_priv);
11435 intel_crt_init(dev_priv);
11437 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11438 drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
11439 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
11440 if (!found && IS_G4X(dev_priv)) {
11441 drm_dbg_kms(&dev_priv->drm,
11442 "probing HDMI on SDVOB\n");
11443 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
11446 if (!found && IS_G4X(dev_priv))
11447 g4x_dp_init(dev_priv, DP_B, PORT_B);
11450 /* Before G4X SDVOC doesn't have its own detect register */
11452 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
11453 drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
11454 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
11457 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
11459 if (IS_G4X(dev_priv)) {
11460 drm_dbg_kms(&dev_priv->drm,
11461 "probing HDMI on SDVOC\n");
11462 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
11464 if (IS_G4X(dev_priv))
11465 g4x_dp_init(dev_priv, DP_C, PORT_C);
11468 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
11469 g4x_dp_init(dev_priv, DP_D, PORT_D);
11471 if (SUPPORTS_TV(dev_priv))
11472 intel_tv_init(dev_priv);
11473 } else if (DISPLAY_VER(dev_priv) == 2) {
11474 if (IS_I85X(dev_priv))
11475 intel_lvds_init(dev_priv);
11477 intel_crt_init(dev_priv);
11478 intel_dvo_init(dev_priv);
11481 for_each_intel_encoder(&dev_priv->drm, encoder) {
11482 encoder->base.possible_crtcs =
11483 intel_encoder_possible_crtcs(encoder);
11484 encoder->base.possible_clones =
11485 intel_encoder_possible_clones(encoder);
11488 intel_init_pch_refclk(dev_priv);
11490 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
11493 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11495 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11497 drm_framebuffer_cleanup(fb);
11499 if (intel_fb_uses_dpt(fb))
11500 intel_dpt_destroy(intel_fb->dpt_vm);
11502 intel_frontbuffer_put(intel_fb->frontbuffer);
11507 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11508 struct drm_file *file,
11509 unsigned int *handle)
11511 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11512 struct drm_i915_private *i915 = to_i915(obj->base.dev);
11514 if (i915_gem_object_is_userptr(obj)) {
11515 drm_dbg(&i915->drm,
11516 "attempting to use a userptr for a framebuffer, denied\n");
11520 return drm_gem_handle_create(file, &obj->base, handle);
11523 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
11524 struct drm_file *file,
11525 unsigned flags, unsigned color,
11526 struct drm_clip_rect *clips,
11527 unsigned num_clips)
11529 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11531 i915_gem_object_flush_if_display(obj);
11532 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
11537 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11538 .destroy = intel_user_framebuffer_destroy,
11539 .create_handle = intel_user_framebuffer_create_handle,
11540 .dirty = intel_user_framebuffer_dirty,
11543 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
11544 struct drm_i915_gem_object *obj,
11545 struct drm_mode_fb_cmd2 *mode_cmd)
11547 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
11548 struct drm_framebuffer *fb = &intel_fb->base;
11550 unsigned int tiling, stride;
11554 intel_fb->frontbuffer = intel_frontbuffer_get(obj);
11555 if (!intel_fb->frontbuffer)
11558 i915_gem_object_lock(obj, NULL);
11559 tiling = i915_gem_object_get_tiling(obj);
11560 stride = i915_gem_object_get_stride(obj);
11561 i915_gem_object_unlock(obj);
11563 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
11565 * If there's a fence, enforce that
11566 * the fb modifier and tiling mode match.
11568 if (tiling != I915_TILING_NONE &&
11569 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11570 drm_dbg_kms(&dev_priv->drm,
11571 "tiling_mode doesn't match fb modifier\n");
11575 if (tiling == I915_TILING_X) {
11576 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
11577 } else if (tiling == I915_TILING_Y) {
11578 drm_dbg_kms(&dev_priv->drm,
11579 "No Y tiling for legacy addfb\n");
11584 if (!drm_any_plane_has_format(&dev_priv->drm,
11585 mode_cmd->pixel_format,
11586 mode_cmd->modifier[0])) {
11587 drm_dbg_kms(&dev_priv->drm,
11588 "unsupported pixel format %p4cc / modifier 0x%llx\n",
11589 &mode_cmd->pixel_format, mode_cmd->modifier[0]);
11594 * gen2/3 display engine uses the fence if present,
11595 * so the tiling mode must match the fb modifier exactly.
11597 if (DISPLAY_VER(dev_priv) < 4 &&
11598 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
11599 drm_dbg_kms(&dev_priv->drm,
11600 "tiling_mode must match fb modifier exactly on gen2/3\n");
11604 max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
11605 mode_cmd->modifier[0]);
11606 if (mode_cmd->pitches[0] > max_stride) {
11607 drm_dbg_kms(&dev_priv->drm,
11608 "%s pitch (%u) must be at most %d\n",
11609 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
11610 "tiled" : "linear",
11611 mode_cmd->pitches[0], max_stride);
11616 * If there's a fence, enforce that
11617 * the fb pitch and fence stride match.
11619 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
11620 drm_dbg_kms(&dev_priv->drm,
11621 "pitch (%d) must match tiling stride (%d)\n",
11622 mode_cmd->pitches[0], stride);
11626 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11627 if (mode_cmd->offsets[0] != 0) {
11628 drm_dbg_kms(&dev_priv->drm,
11629 "plane 0 offset (0x%08x) must be 0\n",
11630 mode_cmd->offsets[0]);
11634 drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
11636 for (i = 0; i < fb->format->num_planes; i++) {
11637 u32 stride_alignment;
11639 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
11640 drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
11645 stride_alignment = intel_fb_stride_alignment(fb, i);
11646 if (fb->pitches[i] & (stride_alignment - 1)) {
11647 drm_dbg_kms(&dev_priv->drm,
11648 "plane %d pitch (%d) must be at least %u byte aligned\n",
11649 i, fb->pitches[i], stride_alignment);
11653 if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
11654 int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
11656 if (fb->pitches[i] != ccs_aux_stride) {
11657 drm_dbg_kms(&dev_priv->drm,
11658 "ccs aux plane %d pitch (%d) must be %d\n",
11660 fb->pitches[i], ccs_aux_stride);
11665 /* TODO: Add POT stride remapping support for CCS formats as well. */
11666 if (IS_ALDERLAKE_P(dev_priv) &&
11667 mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
11668 !intel_fb_needs_pot_stride_remap(intel_fb) &&
11669 !is_power_of_2(mode_cmd->pitches[i])) {
11670 drm_dbg_kms(&dev_priv->drm,
11671 "plane %d pitch (%d) must be power of two for tiled buffers\n",
11672 i, mode_cmd->pitches[i]);
11676 fb->obj[i] = &obj->base;
11679 ret = intel_fill_fb_info(dev_priv, intel_fb);
11683 if (intel_fb_uses_dpt(fb)) {
11684 struct i915_address_space *vm;
11686 vm = intel_dpt_create(intel_fb);
11692 intel_fb->dpt_vm = vm;
11695 ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
11697 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
11704 intel_frontbuffer_put(intel_fb->frontbuffer);
11708 static struct drm_framebuffer *
11709 intel_user_framebuffer_create(struct drm_device *dev,
11710 struct drm_file *filp,
11711 const struct drm_mode_fb_cmd2 *user_mode_cmd)
11713 struct drm_framebuffer *fb;
11714 struct drm_i915_gem_object *obj;
11715 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
11716 struct drm_i915_private *i915;
11718 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
11720 return ERR_PTR(-ENOENT);
11722 /* object is backed with LMEM for discrete */
11723 i915 = to_i915(obj->base.dev);
11724 if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM)) {
11725 /* object is "remote", not in local memory */
11726 i915_gem_object_put(obj);
11727 return ERR_PTR(-EREMOTE);
11730 fb = intel_framebuffer_create(obj, &mode_cmd);
11731 i915_gem_object_put(obj);
11736 static enum drm_mode_status
11737 intel_mode_valid(struct drm_device *dev,
11738 const struct drm_display_mode *mode)
11740 struct drm_i915_private *dev_priv = to_i915(dev);
11741 int hdisplay_max, htotal_max;
11742 int vdisplay_max, vtotal_max;
11745 * Can't reject DBLSCAN here because Xorg ddxen can add piles
11746 * of DBLSCAN modes to the output's mode list when they detect
11747 * the scaling mode property on the connector. And they don't
11748 * ask the kernel to validate those modes in any way until
11749 * modeset time at which point the client gets a protocol error.
11750 * So in order to not upset those clients we silently ignore the
11751 * DBLSCAN flag on such connectors. For other connectors we will
11752 * reject modes with the DBLSCAN flag in encoder->compute_config().
11753 * And we always reject DBLSCAN modes in connector->mode_valid()
11754 * as we never want such modes on the connector's mode list.
11757 if (mode->vscan > 1)
11758 return MODE_NO_VSCAN;
11760 if (mode->flags & DRM_MODE_FLAG_HSKEW)
11761 return MODE_H_ILLEGAL;
11763 if (mode->flags & (DRM_MODE_FLAG_CSYNC |
11764 DRM_MODE_FLAG_NCSYNC |
11765 DRM_MODE_FLAG_PCSYNC))
11768 if (mode->flags & (DRM_MODE_FLAG_BCAST |
11769 DRM_MODE_FLAG_PIXMUX |
11770 DRM_MODE_FLAG_CLKDIV2))
11773 /* Transcoder timing limits */
11774 if (DISPLAY_VER(dev_priv) >= 11) {
11775 hdisplay_max = 16384;
11776 vdisplay_max = 8192;
11777 htotal_max = 16384;
11779 } else if (DISPLAY_VER(dev_priv) >= 9 ||
11780 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
11781 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
11782 vdisplay_max = 4096;
11785 } else if (DISPLAY_VER(dev_priv) >= 3) {
11786 hdisplay_max = 4096;
11787 vdisplay_max = 4096;
11791 hdisplay_max = 2048;
11792 vdisplay_max = 2048;
11797 if (mode->hdisplay > hdisplay_max ||
11798 mode->hsync_start > htotal_max ||
11799 mode->hsync_end > htotal_max ||
11800 mode->htotal > htotal_max)
11801 return MODE_H_ILLEGAL;
11803 if (mode->vdisplay > vdisplay_max ||
11804 mode->vsync_start > vtotal_max ||
11805 mode->vsync_end > vtotal_max ||
11806 mode->vtotal > vtotal_max)
11807 return MODE_V_ILLEGAL;
11809 if (DISPLAY_VER(dev_priv) >= 5) {
11810 if (mode->hdisplay < 64 ||
11811 mode->htotal - mode->hdisplay < 32)
11812 return MODE_H_ILLEGAL;
11814 if (mode->vtotal - mode->vdisplay < 5)
11815 return MODE_V_ILLEGAL;
11817 if (mode->htotal - mode->hdisplay < 32)
11818 return MODE_H_ILLEGAL;
11820 if (mode->vtotal - mode->vdisplay < 3)
11821 return MODE_V_ILLEGAL;
11827 enum drm_mode_status
11828 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
11829 const struct drm_display_mode *mode,
11832 int plane_width_max, plane_height_max;
11835 * intel_mode_valid() should be
11836 * sufficient on older platforms.
11838 if (DISPLAY_VER(dev_priv) < 9)
11842 * Most people will probably want a fullscreen
11843 * plane so let's not advertize modes that are
11844 * too big for that.
11846 if (DISPLAY_VER(dev_priv) >= 11) {
11847 plane_width_max = 5120 << bigjoiner;
11848 plane_height_max = 4320;
11850 plane_width_max = 5120;
11851 plane_height_max = 4096;
11854 if (mode->hdisplay > plane_width_max)
11855 return MODE_H_ILLEGAL;
11857 if (mode->vdisplay > plane_height_max)
11858 return MODE_V_ILLEGAL;
11863 static const struct drm_mode_config_funcs intel_mode_funcs = {
11864 .fb_create = intel_user_framebuffer_create,
11865 .get_format_info = intel_get_format_info,
11866 .output_poll_changed = intel_fbdev_output_poll_changed,
11867 .mode_valid = intel_mode_valid,
11868 .atomic_check = intel_atomic_check,
11869 .atomic_commit = intel_atomic_commit,
11870 .atomic_state_alloc = intel_atomic_state_alloc,
11871 .atomic_state_clear = intel_atomic_state_clear,
11872 .atomic_state_free = intel_atomic_state_free,
11876 * intel_init_display_hooks - initialize the display modesetting hooks
11877 * @dev_priv: device private
11879 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
11881 if (!HAS_DISPLAY(dev_priv))
11884 intel_init_cdclk_hooks(dev_priv);
11885 intel_init_audio_hooks(dev_priv);
11887 intel_dpll_init_clock_hook(dev_priv);
11889 if (DISPLAY_VER(dev_priv) >= 9) {
11890 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
11891 dev_priv->display.crtc_enable = hsw_crtc_enable;
11892 dev_priv->display.crtc_disable = hsw_crtc_disable;
11893 } else if (HAS_DDI(dev_priv)) {
11894 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
11895 dev_priv->display.crtc_enable = hsw_crtc_enable;
11896 dev_priv->display.crtc_disable = hsw_crtc_disable;
11897 } else if (HAS_PCH_SPLIT(dev_priv)) {
11898 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
11899 dev_priv->display.crtc_enable = ilk_crtc_enable;
11900 dev_priv->display.crtc_disable = ilk_crtc_disable;
11901 } else if (IS_CHERRYVIEW(dev_priv) ||
11902 IS_VALLEYVIEW(dev_priv)) {
11903 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11904 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11905 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11907 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11908 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11909 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11912 intel_fdi_init_hook(dev_priv);
11914 if (DISPLAY_VER(dev_priv) >= 9) {
11915 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
11916 dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
11918 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
11919 dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
11924 void intel_modeset_init_hw(struct drm_i915_private *i915)
11926 struct intel_cdclk_state *cdclk_state;
11928 if (!HAS_DISPLAY(i915))
11931 cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
11933 intel_update_cdclk(i915);
11934 intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
11935 cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
11938 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
11940 struct drm_plane *plane;
11941 struct intel_crtc *crtc;
11943 for_each_intel_crtc(state->dev, crtc) {
11944 struct intel_crtc_state *crtc_state;
11946 crtc_state = intel_atomic_get_crtc_state(state, crtc);
11947 if (IS_ERR(crtc_state))
11948 return PTR_ERR(crtc_state);
11950 if (crtc_state->hw.active) {
11952 * Preserve the inherited flag to avoid
11953 * taking the full modeset path.
11955 crtc_state->inherited = true;
11959 drm_for_each_plane(plane, state->dev) {
11960 struct drm_plane_state *plane_state;
11962 plane_state = drm_atomic_get_plane_state(state, plane);
11963 if (IS_ERR(plane_state))
11964 return PTR_ERR(plane_state);
11971 * Calculate what we think the watermarks should be for the state we've read
11972 * out of the hardware and then immediately program those watermarks so that
11973 * we ensure the hardware settings match our internal state.
11975 * We can calculate what we think WM's should be by creating a duplicate of the
11976 * current state (which was constructed during hardware readout) and running it
11977 * through the atomic check code to calculate new watermark values in the
11980 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
11982 struct drm_atomic_state *state;
11983 struct intel_atomic_state *intel_state;
11984 struct intel_crtc *crtc;
11985 struct intel_crtc_state *crtc_state;
11986 struct drm_modeset_acquire_ctx ctx;
11990 /* Only supported on platforms that use atomic watermark design */
11991 if (!dev_priv->display.optimize_watermarks)
11994 state = drm_atomic_state_alloc(&dev_priv->drm);
11995 if (drm_WARN_ON(&dev_priv->drm, !state))
11998 intel_state = to_intel_atomic_state(state);
12000 drm_modeset_acquire_init(&ctx, 0);
12003 state->acquire_ctx = &ctx;
12006 * Hardware readout is the only time we don't want to calculate
12007 * intermediate watermarks (since we don't trust the current
12010 if (!HAS_GMCH(dev_priv))
12011 intel_state->skip_intermediate_wm = true;
12013 ret = sanitize_watermarks_add_affected(state);
12017 ret = intel_atomic_check(&dev_priv->drm, state);
12021 /* Write calculated watermark values back */
12022 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
12023 crtc_state->wm.need_postvbl_update = true;
12024 dev_priv->display.optimize_watermarks(intel_state, crtc);
12026 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
12030 if (ret == -EDEADLK) {
12031 drm_atomic_state_clear(state);
12032 drm_modeset_backoff(&ctx);
12037 * If we fail here, it means that the hardware appears to be
12038 * programmed in a way that shouldn't be possible, given our
12039 * understanding of watermark requirements. This might mean a
12040 * mistake in the hardware readout code or a mistake in the
12041 * watermark calculations for a given platform. Raise a WARN
12042 * so that this is noticeable.
12044 * If this actually happens, we'll have to just leave the
12045 * BIOS-programmed watermarks untouched and hope for the best.
12047 drm_WARN(&dev_priv->drm, ret,
12048 "Could not determine valid watermarks for inherited state\n");
12050 drm_atomic_state_put(state);
12052 drm_modeset_drop_locks(&ctx);
12053 drm_modeset_acquire_fini(&ctx);
12056 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
12058 if (IS_IRONLAKE(dev_priv)) {
12060 intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
12062 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
12063 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
12064 dev_priv->fdi_pll_freq = 270000;
12069 drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
12072 static int intel_initial_commit(struct drm_device *dev)
12074 struct drm_atomic_state *state = NULL;
12075 struct drm_modeset_acquire_ctx ctx;
12076 struct intel_crtc *crtc;
12079 state = drm_atomic_state_alloc(dev);
12083 drm_modeset_acquire_init(&ctx, 0);
12086 state->acquire_ctx = &ctx;
12088 for_each_intel_crtc(dev, crtc) {
12089 struct intel_crtc_state *crtc_state =
12090 intel_atomic_get_crtc_state(state, crtc);
12092 if (IS_ERR(crtc_state)) {
12093 ret = PTR_ERR(crtc_state);
12097 if (crtc_state->hw.active) {
12098 struct intel_encoder *encoder;
12101 * We've not yet detected sink capabilities
12102 * (audio,infoframes,etc.) and thus we don't want to
12103 * force a full state recomputation yet. We want that to
12104 * happen only for the first real commit from userspace.
12105 * So preserve the inherited flag for the time being.
12107 crtc_state->inherited = true;
12109 ret = drm_atomic_add_affected_planes(state, &crtc->base);
12114 * FIXME hack to force a LUT update to avoid the
12115 * plane update forcing the pipe gamma on without
12116 * having a proper LUT loaded. Remove once we
12117 * have readout for pipe gamma enable.
12119 crtc_state->uapi.color_mgmt_changed = true;
12121 for_each_intel_encoder_mask(dev, encoder,
12122 crtc_state->uapi.encoder_mask) {
12123 if (encoder->initial_fastset_check &&
12124 !encoder->initial_fastset_check(encoder, crtc_state)) {
12125 ret = drm_atomic_add_affected_connectors(state,
12134 ret = drm_atomic_commit(state);
12137 if (ret == -EDEADLK) {
12138 drm_atomic_state_clear(state);
12139 drm_modeset_backoff(&ctx);
12143 drm_atomic_state_put(state);
12145 drm_modeset_drop_locks(&ctx);
12146 drm_modeset_acquire_fini(&ctx);
12151 static void intel_mode_config_init(struct drm_i915_private *i915)
12153 struct drm_mode_config *mode_config = &i915->drm.mode_config;
12155 drm_mode_config_init(&i915->drm);
12156 INIT_LIST_HEAD(&i915->global_obj_list);
12158 mode_config->min_width = 0;
12159 mode_config->min_height = 0;
12161 mode_config->preferred_depth = 24;
12162 mode_config->prefer_shadow = 1;
12164 mode_config->funcs = &intel_mode_funcs;
12166 mode_config->async_page_flip = has_async_flips(i915);
12169 * Maximum framebuffer dimensions, chosen to match
12170 * the maximum render engine surface size on gen4+.
12172 if (DISPLAY_VER(i915) >= 7) {
12173 mode_config->max_width = 16384;
12174 mode_config->max_height = 16384;
12175 } else if (DISPLAY_VER(i915) >= 4) {
12176 mode_config->max_width = 8192;
12177 mode_config->max_height = 8192;
12178 } else if (DISPLAY_VER(i915) == 3) {
12179 mode_config->max_width = 4096;
12180 mode_config->max_height = 4096;
12182 mode_config->max_width = 2048;
12183 mode_config->max_height = 2048;
12186 if (IS_I845G(i915) || IS_I865G(i915)) {
12187 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
12188 mode_config->cursor_height = 1023;
12189 } else if (IS_I830(i915) || IS_I85X(i915) ||
12190 IS_I915G(i915) || IS_I915GM(i915)) {
12191 mode_config->cursor_width = 64;
12192 mode_config->cursor_height = 64;
12194 mode_config->cursor_width = 256;
12195 mode_config->cursor_height = 256;
12199 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
12201 intel_atomic_global_obj_cleanup(i915);
12202 drm_mode_config_cleanup(&i915->drm);
12205 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
12207 if (plane_config->fb) {
12208 struct drm_framebuffer *fb = &plane_config->fb->base;
12210 /* We may only have the stub and not a full framebuffer */
12211 if (drm_framebuffer_read_refcount(fb))
12212 drm_framebuffer_put(fb);
12217 if (plane_config->vma)
12218 i915_vma_put(plane_config->vma);
12221 /* part #1: call before irq install */
12222 int intel_modeset_init_noirq(struct drm_i915_private *i915)
12226 if (i915_inject_probe_failure(i915))
12229 if (HAS_DISPLAY(i915)) {
12230 ret = drm_vblank_init(&i915->drm,
12231 INTEL_NUM_PIPES(i915));
12236 intel_bios_init(i915);
12238 ret = intel_vga_register(i915);
12242 /* FIXME: completely on the wrong abstraction layer */
12243 intel_power_domains_init_hw(i915, false);
12245 if (!HAS_DISPLAY(i915))
12248 intel_dmc_ucode_init(i915);
12250 i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
12251 i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
12252 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
12254 i915->framestart_delay = 1; /* 1-4 */
12256 i915->window2_delay = 0; /* No DSB so no window2 delay */
12258 intel_mode_config_init(i915);
12260 ret = intel_cdclk_init(i915);
12262 goto cleanup_vga_client_pw_domain_dmc;
12264 ret = intel_dbuf_init(i915);
12266 goto cleanup_vga_client_pw_domain_dmc;
12268 ret = intel_bw_init(i915);
12270 goto cleanup_vga_client_pw_domain_dmc;
12272 init_llist_head(&i915->atomic_helper.free_list);
12273 INIT_WORK(&i915->atomic_helper.free_work,
12274 intel_atomic_helper_free_state_worker);
12276 intel_init_quirks(i915);
12278 intel_fbc_init(i915);
12282 cleanup_vga_client_pw_domain_dmc:
12283 intel_dmc_ucode_fini(i915);
12284 intel_power_domains_driver_remove(i915);
12285 intel_vga_unregister(i915);
12287 intel_bios_driver_remove(i915);
12292 /* part #2: call after irq install, but before gem init */
12293 int intel_modeset_init_nogem(struct drm_i915_private *i915)
12295 struct drm_device *dev = &i915->drm;
12297 struct intel_crtc *crtc;
12300 if (!HAS_DISPLAY(i915))
12303 intel_init_pm(i915);
12305 intel_panel_sanitize_ssc(i915);
12307 intel_pps_setup(i915);
12309 intel_gmbus_setup(i915);
12311 drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
12312 INTEL_NUM_PIPES(i915),
12313 INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
12315 for_each_pipe(i915, pipe) {
12316 ret = intel_crtc_init(i915, pipe);
12318 intel_mode_config_cleanup(i915);
12323 intel_plane_possible_crtcs_init(i915);
12324 intel_shared_dpll_init(dev);
12325 intel_update_fdi_pll_freq(i915);
12327 intel_update_czclk(i915);
12328 intel_modeset_init_hw(i915);
12329 intel_dpll_update_ref_clks(i915);
12331 intel_hdcp_component_init(i915);
12333 if (i915->max_cdclk_freq == 0)
12334 intel_update_max_cdclk(i915);
12337 * If the platform has HTI, we need to find out whether it has reserved
12338 * any display resources before we create our display outputs.
12340 if (INTEL_INFO(i915)->display.has_hti)
12341 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
12343 /* Just disable it once at startup */
12344 intel_vga_disable(i915);
12345 intel_setup_outputs(i915);
12347 drm_modeset_lock_all(dev);
12348 intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
12349 drm_modeset_unlock_all(dev);
12351 for_each_intel_crtc(dev, crtc) {
12352 struct intel_initial_plane_config plane_config = {};
12354 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
12358 * Note that reserving the BIOS fb up front prevents us
12359 * from stuffing other stolen allocations like the ring
12360 * on top. This prevents some ugliness at boot time, and
12361 * can even allow for smooth boot transitions if the BIOS
12362 * fb is large enough for the active pipe configuration.
12364 i915->display.get_initial_plane_config(crtc, &plane_config);
12367 * If the fb is shared between multiple heads, we'll
12368 * just get the first one.
12370 intel_find_initial_plane_obj(crtc, &plane_config);
12372 plane_config_fini(&plane_config);
12376 * Make sure hardware watermarks really match the state we read out.
12377 * Note that we need to do this after reconstructing the BIOS fb's
12378 * since the watermark calculation done here will use pstate->fb.
12380 if (!HAS_GMCH(i915))
12381 sanitize_watermarks(i915);
12386 /* part #3: call after gem init */
12387 int intel_modeset_init(struct drm_i915_private *i915)
12391 if (!HAS_DISPLAY(i915))
12395 * Force all active planes to recompute their states. So that on
12396 * mode_setcrtc after probe, all the intel_plane_state variables
12397 * are already calculated and there is no assert_plane warnings
12400 ret = intel_initial_commit(&i915->drm);
12402 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
12404 intel_overlay_setup(i915);
12406 ret = intel_fbdev_init(&i915->drm);
12410 /* Only enable hotplug handling once the fbdev is fully set up. */
12411 intel_hpd_init(i915);
12412 intel_hpd_poll_disable(i915);
12414 intel_init_ipc(i915);
12419 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12421 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12422 /* 640x480@60Hz, ~25175 kHz */
12423 struct dpll clock = {
12433 drm_WARN_ON(&dev_priv->drm,
12434 i9xx_calc_dpll_params(48000, &clock) != 25154);
12436 drm_dbg_kms(&dev_priv->drm,
12437 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
12438 pipe_name(pipe), clock.vco, clock.dot);
12440 fp = i9xx_dpll_compute_fp(&clock);
12441 dpll = DPLL_DVO_2X_MODE |
12442 DPLL_VGA_MODE_DIS |
12443 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
12444 PLL_P2_DIVIDE_BY_4 |
12445 PLL_REF_INPUT_DREFCLK |
12448 intel_de_write(dev_priv, FP0(pipe), fp);
12449 intel_de_write(dev_priv, FP1(pipe), fp);
12451 intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
12452 intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
12453 intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
12454 intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
12455 intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
12456 intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
12457 intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
12460 * Apparently we need to have VGA mode enabled prior to changing
12461 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
12462 * dividers, even though the register value does change.
12464 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
12465 intel_de_write(dev_priv, DPLL(pipe), dpll);
12467 /* Wait for the clocks to stabilize. */
12468 intel_de_posting_read(dev_priv, DPLL(pipe));
12471 /* The pixel multiplier can only be updated once the
12472 * DPLL is enabled and the clocks are stable.
12474 * So write it again.
12476 intel_de_write(dev_priv, DPLL(pipe), dpll);
12478 /* We do this three times for luck */
12479 for (i = 0; i < 3 ; i++) {
12480 intel_de_write(dev_priv, DPLL(pipe), dpll);
12481 intel_de_posting_read(dev_priv, DPLL(pipe));
12482 udelay(150); /* wait for warmup */
12485 intel_de_write(dev_priv, PIPECONF(pipe),
12486 PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
12487 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12489 intel_wait_for_pipe_scanline_moving(crtc);
12492 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
12494 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12496 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
12499 drm_WARN_ON(&dev_priv->drm,
12500 intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
12501 DISPLAY_PLANE_ENABLE);
12502 drm_WARN_ON(&dev_priv->drm,
12503 intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
12504 DISPLAY_PLANE_ENABLE);
12505 drm_WARN_ON(&dev_priv->drm,
12506 intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
12507 DISPLAY_PLANE_ENABLE);
12508 drm_WARN_ON(&dev_priv->drm,
12509 intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
12510 drm_WARN_ON(&dev_priv->drm,
12511 intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
12513 intel_de_write(dev_priv, PIPECONF(pipe), 0);
12514 intel_de_posting_read(dev_priv, PIPECONF(pipe));
12516 intel_wait_for_pipe_scanline_stopped(crtc);
12518 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
12519 intel_de_posting_read(dev_priv, DPLL(pipe));
12523 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
12525 struct intel_crtc *crtc;
12527 if (DISPLAY_VER(dev_priv) >= 4)
12530 for_each_intel_crtc(&dev_priv->drm, crtc) {
12531 struct intel_plane *plane =
12532 to_intel_plane(crtc->base.primary);
12533 struct intel_crtc *plane_crtc;
12536 if (!plane->get_hw_state(plane, &pipe))
12539 if (pipe == crtc->pipe)
12542 drm_dbg_kms(&dev_priv->drm,
12543 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
12544 plane->base.base.id, plane->base.name);
12546 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12547 intel_plane_disable_noatomic(plane_crtc, plane);
12551 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
12553 struct drm_device *dev = crtc->base.dev;
12554 struct intel_encoder *encoder;
12556 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
12562 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
12564 struct drm_device *dev = encoder->base.dev;
12565 struct intel_connector *connector;
12567 for_each_connector_on_encoder(dev, &encoder->base, connector)
12573 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
12574 enum pipe pch_transcoder)
12576 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
12577 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
12580 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
12582 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12583 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12584 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
12586 if (DISPLAY_VER(dev_priv) >= 9 ||
12587 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12588 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
12591 if (transcoder_is_dsi(cpu_transcoder))
12594 val = intel_de_read(dev_priv, reg);
12595 val &= ~HSW_FRAME_START_DELAY_MASK;
12596 val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12597 intel_de_write(dev_priv, reg, val);
12599 i915_reg_t reg = PIPECONF(cpu_transcoder);
12602 val = intel_de_read(dev_priv, reg);
12603 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
12604 val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12605 intel_de_write(dev_priv, reg, val);
12608 if (!crtc_state->has_pch_encoder)
12611 if (HAS_PCH_IBX(dev_priv)) {
12612 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
12615 val = intel_de_read(dev_priv, reg);
12616 val &= ~TRANS_FRAME_START_DELAY_MASK;
12617 val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12618 intel_de_write(dev_priv, reg, val);
12620 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
12621 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
12624 val = intel_de_read(dev_priv, reg);
12625 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
12626 val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
12627 intel_de_write(dev_priv, reg, val);
12631 static void intel_sanitize_crtc(struct intel_crtc *crtc,
12632 struct drm_modeset_acquire_ctx *ctx)
12634 struct drm_device *dev = crtc->base.dev;
12635 struct drm_i915_private *dev_priv = to_i915(dev);
12636 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
12638 if (crtc_state->hw.active) {
12639 struct intel_plane *plane;
12641 /* Clear any frame start delays used for debugging left by the BIOS */
12642 intel_sanitize_frame_start_delay(crtc_state);
12644 /* Disable everything but the primary plane */
12645 for_each_intel_plane_on_crtc(dev, crtc, plane) {
12646 const struct intel_plane_state *plane_state =
12647 to_intel_plane_state(plane->base.state);
12649 if (plane_state->uapi.visible &&
12650 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
12651 intel_plane_disable_noatomic(crtc, plane);
12655 * Disable any background color set by the BIOS, but enable the
12656 * gamma and CSC to match how we program our planes.
12658 if (DISPLAY_VER(dev_priv) >= 9)
12659 intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
12660 SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
12663 /* Adjust the state of the output pipe according to whether we
12664 * have active connectors/encoders. */
12665 if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
12666 !crtc_state->bigjoiner_slave)
12667 intel_crtc_disable_noatomic(crtc, ctx);
12669 if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
12671 * We start out with underrun reporting disabled to avoid races.
12672 * For correct bookkeeping mark this on active crtcs.
12674 * Also on gmch platforms we dont have any hardware bits to
12675 * disable the underrun reporting. Which means we need to start
12676 * out with underrun reporting disabled also on inactive pipes,
12677 * since otherwise we'll complain about the garbage we read when
12678 * e.g. coming up after runtime pm.
12680 * No protection against concurrent access is required - at
12681 * worst a fifo underrun happens which also sets this to false.
12683 crtc->cpu_fifo_underrun_disabled = true;
12685 * We track the PCH trancoder underrun reporting state
12686 * within the crtc. With crtc for pipe A housing the underrun
12687 * reporting state for PCH transcoder A, crtc for pipe B housing
12688 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
12689 * and marking underrun reporting as disabled for the non-existing
12690 * PCH transcoders B and C would prevent enabling the south
12691 * error interrupt (see cpt_can_enable_serr_int()).
12693 if (has_pch_trancoder(dev_priv, crtc->pipe))
12694 crtc->pch_fifo_underrun_disabled = true;
12698 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
12700 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
12703 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
12704 * the hardware when a high res displays plugged in. DPLL P
12705 * divider is zero, and the pipe timings are bonkers. We'll
12706 * try to disable everything in that case.
12708 * FIXME would be nice to be able to sanitize this state
12709 * without several WARNs, but for now let's take the easy
12712 return IS_SANDYBRIDGE(dev_priv) &&
12713 crtc_state->hw.active &&
12714 crtc_state->shared_dpll &&
12715 crtc_state->port_clock == 0;
12718 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12721 struct intel_connector *connector;
12722 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
12723 struct intel_crtc_state *crtc_state = crtc ?
12724 to_intel_crtc_state(crtc->base.state) : NULL;
12726 /* We need to check both for a crtc link (meaning that the
12727 * encoder is active and trying to read from a pipe) and the
12728 * pipe itself being active. */
12729 bool has_active_crtc = crtc_state &&
12730 crtc_state->hw.active;
12732 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
12733 drm_dbg_kms(&dev_priv->drm,
12734 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
12735 pipe_name(crtc->pipe));
12736 has_active_crtc = false;
12739 connector = intel_encoder_find_connector(encoder);
12740 if (connector && !has_active_crtc) {
12741 drm_dbg_kms(&dev_priv->drm,
12742 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12743 encoder->base.base.id,
12744 encoder->base.name);
12746 /* Connector is active, but has no active pipe. This is
12747 * fallout from our resume register restoring. Disable
12748 * the encoder manually again. */
12750 struct drm_encoder *best_encoder;
12752 drm_dbg_kms(&dev_priv->drm,
12753 "[ENCODER:%d:%s] manually disabled\n",
12754 encoder->base.base.id,
12755 encoder->base.name);
12757 /* avoid oopsing in case the hooks consult best_encoder */
12758 best_encoder = connector->base.state->best_encoder;
12759 connector->base.state->best_encoder = &encoder->base;
12761 /* FIXME NULL atomic state passed! */
12762 if (encoder->disable)
12763 encoder->disable(NULL, encoder, crtc_state,
12764 connector->base.state);
12765 if (encoder->post_disable)
12766 encoder->post_disable(NULL, encoder, crtc_state,
12767 connector->base.state);
12769 connector->base.state->best_encoder = best_encoder;
12771 encoder->base.crtc = NULL;
12773 /* Inconsistent output/port/pipe state happens presumably due to
12774 * a bug in one of the get_hw_state functions. Or someplace else
12775 * in our code, like the register restore mess on resume. Clamp
12776 * things to off as a safer default. */
12778 connector->base.dpms = DRM_MODE_DPMS_OFF;
12779 connector->base.encoder = NULL;
12782 /* notify opregion of the sanitized encoder state */
12783 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
12785 if (HAS_DDI(dev_priv))
12786 intel_ddi_sanitize_encoder_pll_mapping(encoder);
12789 /* FIXME read out full plane state for all planes */
12790 static void readout_plane_state(struct drm_i915_private *dev_priv)
12792 struct intel_plane *plane;
12793 struct intel_crtc *crtc;
12795 for_each_intel_plane(&dev_priv->drm, plane) {
12796 struct intel_plane_state *plane_state =
12797 to_intel_plane_state(plane->base.state);
12798 struct intel_crtc_state *crtc_state;
12799 enum pipe pipe = PIPE_A;
12802 visible = plane->get_hw_state(plane, &pipe);
12804 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12805 crtc_state = to_intel_crtc_state(crtc->base.state);
12807 intel_set_plane_visible(crtc_state, plane_state, visible);
12809 drm_dbg_kms(&dev_priv->drm,
12810 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
12811 plane->base.base.id, plane->base.name,
12812 enableddisabled(visible), pipe_name(pipe));
12815 for_each_intel_crtc(&dev_priv->drm, crtc) {
12816 struct intel_crtc_state *crtc_state =
12817 to_intel_crtc_state(crtc->base.state);
12819 fixup_plane_bitmasks(crtc_state);
12823 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12825 struct drm_i915_private *dev_priv = to_i915(dev);
12826 struct intel_cdclk_state *cdclk_state =
12827 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
12828 struct intel_dbuf_state *dbuf_state =
12829 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
12831 struct intel_crtc *crtc;
12832 struct intel_encoder *encoder;
12833 struct intel_connector *connector;
12834 struct drm_connector_list_iter conn_iter;
12835 u8 active_pipes = 0;
12837 for_each_intel_crtc(dev, crtc) {
12838 struct intel_crtc_state *crtc_state =
12839 to_intel_crtc_state(crtc->base.state);
12841 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
12842 intel_crtc_free_hw_state(crtc_state);
12843 intel_crtc_state_reset(crtc_state, crtc);
12845 intel_crtc_get_pipe_config(crtc_state);
12847 crtc_state->hw.enable = crtc_state->hw.active;
12849 crtc->base.enabled = crtc_state->hw.enable;
12850 crtc->active = crtc_state->hw.active;
12852 if (crtc_state->hw.active)
12853 active_pipes |= BIT(crtc->pipe);
12855 drm_dbg_kms(&dev_priv->drm,
12856 "[CRTC:%d:%s] hw state readout: %s\n",
12857 crtc->base.base.id, crtc->base.name,
12858 enableddisabled(crtc_state->hw.active));
12861 dev_priv->active_pipes = cdclk_state->active_pipes =
12862 dbuf_state->active_pipes = active_pipes;
12864 readout_plane_state(dev_priv);
12866 for_each_intel_encoder(dev, encoder) {
12867 struct intel_crtc_state *crtc_state = NULL;
12871 if (encoder->get_hw_state(encoder, &pipe)) {
12872 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12873 crtc_state = to_intel_crtc_state(crtc->base.state);
12875 encoder->base.crtc = &crtc->base;
12876 intel_encoder_get_config(encoder, crtc_state);
12878 /* read out to slave crtc as well for bigjoiner */
12879 if (crtc_state->bigjoiner) {
12880 /* encoder should read be linked to bigjoiner master */
12881 WARN_ON(crtc_state->bigjoiner_slave);
12883 crtc = crtc_state->bigjoiner_linked_crtc;
12884 crtc_state = to_intel_crtc_state(crtc->base.state);
12885 intel_encoder_get_config(encoder, crtc_state);
12888 encoder->base.crtc = NULL;
12891 if (encoder->sync_state)
12892 encoder->sync_state(encoder, crtc_state);
12894 drm_dbg_kms(&dev_priv->drm,
12895 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12896 encoder->base.base.id, encoder->base.name,
12897 enableddisabled(encoder->base.crtc),
12901 intel_dpll_readout_hw_state(dev_priv);
12903 drm_connector_list_iter_begin(dev, &conn_iter);
12904 for_each_intel_connector_iter(connector, &conn_iter) {
12905 if (connector->get_hw_state(connector)) {
12906 struct intel_crtc_state *crtc_state;
12907 struct intel_crtc *crtc;
12909 connector->base.dpms = DRM_MODE_DPMS_ON;
12911 encoder = intel_attached_encoder(connector);
12912 connector->base.encoder = &encoder->base;
12914 crtc = to_intel_crtc(encoder->base.crtc);
12915 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
12917 if (crtc_state && crtc_state->hw.active) {
12919 * This has to be done during hardware readout
12920 * because anything calling .crtc_disable may
12921 * rely on the connector_mask being accurate.
12923 crtc_state->uapi.connector_mask |=
12924 drm_connector_mask(&connector->base);
12925 crtc_state->uapi.encoder_mask |=
12926 drm_encoder_mask(&encoder->base);
12929 connector->base.dpms = DRM_MODE_DPMS_OFF;
12930 connector->base.encoder = NULL;
12932 drm_dbg_kms(&dev_priv->drm,
12933 "[CONNECTOR:%d:%s] hw state readout: %s\n",
12934 connector->base.base.id, connector->base.name,
12935 enableddisabled(connector->base.encoder));
12937 drm_connector_list_iter_end(&conn_iter);
12939 for_each_intel_crtc(dev, crtc) {
12940 struct intel_bw_state *bw_state =
12941 to_intel_bw_state(dev_priv->bw_obj.state);
12942 struct intel_crtc_state *crtc_state =
12943 to_intel_crtc_state(crtc->base.state);
12944 struct intel_plane *plane;
12947 if (crtc_state->bigjoiner_slave)
12950 if (crtc_state->hw.active) {
12952 * The initial mode needs to be set in order to keep
12953 * the atomic core happy. It wants a valid mode if the
12954 * crtc's enabled, so we do the above call.
12956 * But we don't set all the derived state fully, hence
12957 * set a flag to indicate that a full recalculation is
12958 * needed on the next commit.
12960 crtc_state->inherited = true;
12962 intel_crtc_update_active_timings(crtc_state);
12964 intel_crtc_copy_hw_to_uapi_state(crtc_state);
12967 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
12968 const struct intel_plane_state *plane_state =
12969 to_intel_plane_state(plane->base.state);
12972 * FIXME don't have the fb yet, so can't
12973 * use intel_plane_data_rate() :(
12975 if (plane_state->uapi.visible)
12976 crtc_state->data_rate[plane->id] =
12977 4 * crtc_state->pixel_rate;
12979 * FIXME don't have the fb yet, so can't
12980 * use plane->min_cdclk() :(
12982 if (plane_state->uapi.visible && plane->min_cdclk) {
12983 if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
12984 crtc_state->min_cdclk[plane->id] =
12985 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
12987 crtc_state->min_cdclk[plane->id] =
12988 crtc_state->pixel_rate;
12990 drm_dbg_kms(&dev_priv->drm,
12991 "[PLANE:%d:%s] min_cdclk %d kHz\n",
12992 plane->base.base.id, plane->base.name,
12993 crtc_state->min_cdclk[plane->id]);
12996 if (crtc_state->hw.active) {
12997 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
12998 if (drm_WARN_ON(dev, min_cdclk < 0))
13002 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
13003 cdclk_state->min_voltage_level[crtc->pipe] =
13004 crtc_state->min_voltage_level;
13006 intel_bw_crtc_update(bw_state, crtc_state);
13008 intel_pipe_config_sanity_check(dev_priv, crtc_state);
13010 /* discard our incomplete slave state, copy it from master */
13011 if (crtc_state->bigjoiner && crtc_state->hw.active) {
13012 struct intel_crtc *slave = crtc_state->bigjoiner_linked_crtc;
13013 struct intel_crtc_state *slave_crtc_state =
13014 to_intel_crtc_state(slave->base.state);
13016 copy_bigjoiner_crtc_state(slave_crtc_state, crtc_state);
13017 slave->base.mode = crtc->base.mode;
13019 cdclk_state->min_cdclk[slave->pipe] = min_cdclk;
13020 cdclk_state->min_voltage_level[slave->pipe] =
13021 crtc_state->min_voltage_level;
13023 for_each_intel_plane_on_crtc(&dev_priv->drm, slave, plane) {
13024 const struct intel_plane_state *plane_state =
13025 to_intel_plane_state(plane->base.state);
13028 * FIXME don't have the fb yet, so can't
13029 * use intel_plane_data_rate() :(
13031 if (plane_state->uapi.visible)
13032 crtc_state->data_rate[plane->id] =
13033 4 * crtc_state->pixel_rate;
13035 crtc_state->data_rate[plane->id] = 0;
13038 intel_bw_crtc_update(bw_state, slave_crtc_state);
13039 drm_calc_timestamping_constants(&slave->base,
13040 &slave_crtc_state->hw.adjusted_mode);
13046 get_encoder_power_domains(struct drm_i915_private *dev_priv)
13048 struct intel_encoder *encoder;
13050 for_each_intel_encoder(&dev_priv->drm, encoder) {
13051 struct intel_crtc_state *crtc_state;
13053 if (!encoder->get_power_domains)
13057 * MST-primary and inactive encoders don't have a crtc state
13058 * and neither of these require any power domain references.
13060 if (!encoder->base.crtc)
13063 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
13064 encoder->get_power_domains(encoder, crtc_state);
13068 static void intel_early_display_was(struct drm_i915_private *dev_priv)
13071 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
13072 * Also known as Wa_14010480278.
13074 if (IS_DISPLAY_VER(dev_priv, 10, 12))
13075 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
13076 intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
13078 if (IS_HASWELL(dev_priv)) {
13080 * WaRsPkgCStateDisplayPMReq:hsw
13081 * System hang if this isn't done before disabling all planes!
13083 intel_de_write(dev_priv, CHICKEN_PAR1_1,
13084 intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
13087 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
13088 /* Display WA #1142:kbl,cfl,cml */
13089 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
13090 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
13091 intel_de_rmw(dev_priv, CHICKEN_MISC_2,
13092 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
13093 KBL_ARB_FILL_SPARE_14);
13097 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
13098 enum port port, i915_reg_t hdmi_reg)
13100 u32 val = intel_de_read(dev_priv, hdmi_reg);
13102 if (val & SDVO_ENABLE ||
13103 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
13106 drm_dbg_kms(&dev_priv->drm,
13107 "Sanitizing transcoder select for HDMI %c\n",
13110 val &= ~SDVO_PIPE_SEL_MASK;
13111 val |= SDVO_PIPE_SEL(PIPE_A);
13113 intel_de_write(dev_priv, hdmi_reg, val);
13116 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
13117 enum port port, i915_reg_t dp_reg)
13119 u32 val = intel_de_read(dev_priv, dp_reg);
13121 if (val & DP_PORT_EN ||
13122 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
13125 drm_dbg_kms(&dev_priv->drm,
13126 "Sanitizing transcoder select for DP %c\n",
13129 val &= ~DP_PIPE_SEL_MASK;
13130 val |= DP_PIPE_SEL(PIPE_A);
13132 intel_de_write(dev_priv, dp_reg, val);
13135 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
13138 * The BIOS may select transcoder B on some of the PCH
13139 * ports even it doesn't enable the port. This would trip
13140 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
13141 * Sanitize the transcoder select bits to prevent that. We
13142 * assume that the BIOS never actually enabled the port,
13143 * because if it did we'd actually have to toggle the port
13144 * on and back off to make the transcoder A select stick
13145 * (see. intel_dp_link_down(), intel_disable_hdmi(),
13146 * intel_disable_sdvo()).
13148 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
13149 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
13150 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
13152 /* PCH SDVOB multiplex with HDMIB */
13153 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
13154 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
13155 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
13158 /* Scan out the current hw modeset state,
13159 * and sanitizes it to the current state
13162 intel_modeset_setup_hw_state(struct drm_device *dev,
13163 struct drm_modeset_acquire_ctx *ctx)
13165 struct drm_i915_private *dev_priv = to_i915(dev);
13166 struct intel_encoder *encoder;
13167 struct intel_crtc *crtc;
13168 intel_wakeref_t wakeref;
13170 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
13172 intel_early_display_was(dev_priv);
13173 intel_modeset_readout_hw_state(dev);
13175 /* HW state is read out, now we need to sanitize this mess. */
13176 get_encoder_power_domains(dev_priv);
13178 if (HAS_PCH_IBX(dev_priv))
13179 ibx_sanitize_pch_ports(dev_priv);
13182 * intel_sanitize_plane_mapping() may need to do vblank
13183 * waits, so we need vblank interrupts restored beforehand.
13185 for_each_intel_crtc(&dev_priv->drm, crtc) {
13186 struct intel_crtc_state *crtc_state =
13187 to_intel_crtc_state(crtc->base.state);
13189 drm_crtc_vblank_reset(&crtc->base);
13191 if (crtc_state->hw.active)
13192 intel_crtc_vblank_on(crtc_state);
13195 intel_sanitize_plane_mapping(dev_priv);
13197 for_each_intel_encoder(dev, encoder)
13198 intel_sanitize_encoder(encoder);
13200 for_each_intel_crtc(&dev_priv->drm, crtc) {
13201 struct intel_crtc_state *crtc_state =
13202 to_intel_crtc_state(crtc->base.state);
13204 intel_sanitize_crtc(crtc, ctx);
13205 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
13208 intel_modeset_update_connector_atomic_state(dev);
13210 intel_dpll_sanitize_state(dev_priv);
13212 if (IS_G4X(dev_priv)) {
13213 g4x_wm_get_hw_state(dev_priv);
13214 g4x_wm_sanitize(dev_priv);
13215 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
13216 vlv_wm_get_hw_state(dev_priv);
13217 vlv_wm_sanitize(dev_priv);
13218 } else if (DISPLAY_VER(dev_priv) >= 9) {
13219 skl_wm_get_hw_state(dev_priv);
13220 skl_wm_sanitize(dev_priv);
13221 } else if (HAS_PCH_SPLIT(dev_priv)) {
13222 ilk_wm_get_hw_state(dev_priv);
13225 for_each_intel_crtc(dev, crtc) {
13226 struct intel_crtc_state *crtc_state =
13227 to_intel_crtc_state(crtc->base.state);
13230 put_domains = modeset_get_crtc_power_domains(crtc_state);
13231 if (drm_WARN_ON(dev, put_domains))
13232 modeset_put_crtc_power_domains(crtc, put_domains);
13235 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
13238 void intel_display_resume(struct drm_device *dev)
13240 struct drm_i915_private *dev_priv = to_i915(dev);
13241 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
13242 struct drm_modeset_acquire_ctx ctx;
13245 if (!HAS_DISPLAY(dev_priv))
13248 dev_priv->modeset_restore_state = NULL;
13250 state->acquire_ctx = &ctx;
13252 drm_modeset_acquire_init(&ctx, 0);
13255 ret = drm_modeset_lock_all_ctx(dev, &ctx);
13256 if (ret != -EDEADLK)
13259 drm_modeset_backoff(&ctx);
13263 ret = __intel_display_resume(dev, state, &ctx);
13265 intel_enable_ipc(dev_priv);
13266 drm_modeset_drop_locks(&ctx);
13267 drm_modeset_acquire_fini(&ctx);
13270 drm_err(&dev_priv->drm,
13271 "Restoring old state failed with %i\n", ret);
13273 drm_atomic_state_put(state);
13276 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
13278 struct intel_connector *connector;
13279 struct drm_connector_list_iter conn_iter;
13281 /* Kill all the work that may have been queued by hpd. */
13282 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
13283 for_each_intel_connector_iter(connector, &conn_iter) {
13284 if (connector->modeset_retry_work.func)
13285 cancel_work_sync(&connector->modeset_retry_work);
13286 if (connector->hdcp.shim) {
13287 cancel_delayed_work_sync(&connector->hdcp.check_work);
13288 cancel_work_sync(&connector->hdcp.prop_work);
13291 drm_connector_list_iter_end(&conn_iter);
13294 /* part #1: call before irq uninstall */
13295 void intel_modeset_driver_remove(struct drm_i915_private *i915)
13297 if (!HAS_DISPLAY(i915))
13300 flush_workqueue(i915->flip_wq);
13301 flush_workqueue(i915->modeset_wq);
13303 flush_work(&i915->atomic_helper.free_work);
13304 drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
13307 /* part #2: call after irq uninstall */
13308 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
13310 if (!HAS_DISPLAY(i915))
13314 * Due to the hpd irq storm handling the hotplug work can re-arm the
13315 * poll handlers. Hence disable polling after hpd handling is shut down.
13317 intel_hpd_poll_fini(i915);
13320 * MST topology needs to be suspended so we don't have any calls to
13321 * fbdev after it's finalized. MST will be destroyed later as part of
13322 * drm_mode_config_cleanup()
13324 intel_dp_mst_suspend(i915);
13326 /* poll work can call into fbdev, hence clean that up afterwards */
13327 intel_fbdev_fini(i915);
13329 intel_unregister_dsm_handler();
13331 intel_fbc_global_disable(i915);
13333 /* flush any delayed tasks or pending work */
13334 flush_scheduled_work();
13336 intel_hdcp_component_fini(i915);
13338 intel_mode_config_cleanup(i915);
13340 intel_overlay_cleanup(i915);
13342 intel_gmbus_teardown(i915);
13344 destroy_workqueue(i915->flip_wq);
13345 destroy_workqueue(i915->modeset_wq);
13347 intel_fbc_cleanup_cfb(i915);
13350 /* part #3: call after gem init */
13351 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
13353 intel_dmc_ucode_fini(i915);
13355 intel_power_domains_driver_remove(i915);
13357 intel_vga_unregister(i915);
13359 intel_bios_driver_remove(i915);
13362 void intel_display_driver_register(struct drm_i915_private *i915)
13364 if (!HAS_DISPLAY(i915))
13367 intel_display_debugfs_register(i915);
13369 /* Must be done after probing outputs */
13370 intel_opregion_register(i915);
13371 acpi_video_register();
13373 intel_audio_init(i915);
13376 * Some ports require correctly set-up hpd registers for
13377 * detection to work properly (leading to ghost connected
13378 * connector status), e.g. VGA on gm45. Hence we can only set
13379 * up the initial fbdev config after hpd irqs are fully
13380 * enabled. We do it last so that the async config cannot run
13381 * before the connectors are registered.
13383 intel_fbdev_initial_config_async(&i915->drm);
13386 * We need to coordinate the hotplugs with the asynchronous
13387 * fbdev configuration, for which we use the
13388 * fbdev->async_cookie.
13390 drm_kms_helper_poll_init(&i915->drm);
13393 void intel_display_driver_unregister(struct drm_i915_private *i915)
13395 if (!HAS_DISPLAY(i915))
13398 intel_fbdev_unregister(i915);
13399 intel_audio_deinit(i915);
13402 * After flushing the fbdev (incl. a late async config which
13403 * will have delayed queuing of a hotplug event), then flush
13404 * the hotplug events.
13406 drm_kms_helper_poll_fini(&i915->drm);
13407 drm_atomic_helper_shutdown(&i915->drm);
13409 acpi_video_unregister();
13410 intel_opregion_unregister(i915);