drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_backlight.h"
  33 #include "intel_combo_phy.h"
  34 #include "intel_connector.h"
  35 #include "intel_crtc.h"
  36 #include "intel_ddi.h"
  37 #include "intel_ddi_buf_trans.h"
  38 #include "intel_de.h"
  39 #include "intel_display_types.h"
  40 #include "intel_dp.h"
  41 #include "intel_dp_link_training.h"
  42 #include "intel_dp_mst.h"
  43 #include "intel_dpio_phy.h"
  44 #include "intel_drrs.h"
  45 #include "intel_dsi.h"
  46 #include "intel_fdi.h"
  47 #include "intel_fifo_underrun.h"
  48 #include "intel_gmbus.h"
  49 #include "intel_hdcp.h"
  50 #include "intel_hdmi.h"
  51 #include "intel_hotplug.h"
  52 #include "intel_lspcon.h"
  53 #include "intel_pps.h"
  54 #include "intel_psr.h"
  55 #include "intel_snps_phy.h"
  56 #include "intel_sprite.h"
  57 #include "intel_tc.h"
  58 #include "intel_vdsc.h"
  59 #include "intel_vrr.h"
  60 #include "skl_scaler.h"
  61 #include "skl_universal_plane.h"
  62
  63 static const u8 index_to_dp_signal_levels[] = {
  64         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  67         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  68         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  69         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  70         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  71         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  72         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  73         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  74 };
  75
  76 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  77                                 const struct intel_crtc_state *crtc_state)
  78 {
  79         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  80         int n_entries, level, default_entry;
  81
  82         n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry);
  83         if (n_entries == 0)
  84                 return 0;
  85         level = intel_bios_hdmi_level_shift(encoder);
  86         if (level < 0)
  87                 level = default_entry;
  88
  89         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
  90                 level = n_entries - 1;
  91
  92         return level;
  93 }
  94
  95 /*
  96  * Starting with Haswell, DDI port buffers must be programmed with correct
  97  * values in advance. This function programs the correct values for
  98  * DP/eDP/FDI use cases.
  99  */
 100 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 101                                 const struct intel_crtc_state *crtc_state)
 102 {
 103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 104         u32 iboost_bit = 0;
 105         int i, n_entries;
 106         enum port port = encoder->port;
 107         const struct intel_ddi_buf_trans *ddi_translations;
 108
 109         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 110         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 111                 return;
 112
 113         /* If we're boosting the current, set bit 31 of trans1 */
 114         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
 115             intel_bios_encoder_dp_boost_level(encoder->devdata))
 116                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 117
 118         for (i = 0; i < n_entries; i++) {
 119                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 120                                ddi_translations->entries[i].hsw.trans1 | iboost_bit);
 121                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 122                                ddi_translations->entries[i].hsw.trans2);
 123         }
 124 }
 125
 126 /*
 127  * Starting with Haswell, DDI port buffers must be programmed with correct
 128  * values in advance. This function programs the correct values for
 129  * HDMI/DVI use cases.
 130  */
 131 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 132                                          const struct intel_crtc_state *crtc_state,
 133                                          int level)
 134 {
 135         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 136         u32 iboost_bit = 0;
 137         int n_entries;
 138         enum port port = encoder->port;
 139         const struct intel_ddi_buf_trans *ddi_translations;
 140
 141         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 142         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 143                 return;
 144         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 145                 level = n_entries - 1;
 146
 147         /* If we're boosting the current, set bit 31 of trans1 */
 148         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
 149             intel_bios_encoder_hdmi_boost_level(encoder->devdata))
 150                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 151
 152         /* Entry 9 is for HDMI: */
 153         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 154                        ddi_translations->entries[level].hsw.trans1 | iboost_bit);
 155         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 156                        ddi_translations->entries[level].hsw.trans2);
 157 }
 158
 159 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 160                              enum port port)
 161 {
 162         if (IS_BROXTON(dev_priv)) {
 163                 udelay(16);
 164                 return;
 165         }
 166
 167         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 168                          DDI_BUF_IS_IDLE), 8))
 169                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 170                         port_name(port));
 171 }
 172
 173 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 174                                       enum port port)
 175 {
 176         int ret;
 177
 178         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 179         if (DISPLAY_VER(dev_priv) < 10) {
 180                 usleep_range(518, 1000);
 181                 return;
 182         }
 183
 184         ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 185                           DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);
 186
 187         if (ret)
 188                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 189                         port_name(port));
 190 }
 191
 192 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 193 {
 194         switch (pll->info->id) {
 195         case DPLL_ID_WRPLL1:
 196                 return PORT_CLK_SEL_WRPLL1;
 197         case DPLL_ID_WRPLL2:
 198                 return PORT_CLK_SEL_WRPLL2;
 199         case DPLL_ID_SPLL:
 200                 return PORT_CLK_SEL_SPLL;
 201         case DPLL_ID_LCPLL_810:
 202                 return PORT_CLK_SEL_LCPLL_810;
 203         case DPLL_ID_LCPLL_1350:
 204                 return PORT_CLK_SEL_LCPLL_1350;
 205         case DPLL_ID_LCPLL_2700:
 206                 return PORT_CLK_SEL_LCPLL_2700;
 207         default:
 208                 MISSING_CASE(pll->info->id);
 209                 return PORT_CLK_SEL_NONE;
 210         }
 211 }
 212
 213 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 214                                   const struct intel_crtc_state *crtc_state)
 215 {
 216         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 217         int clock = crtc_state->port_clock;
 218         const enum intel_dpll_id id = pll->info->id;
 219
 220         switch (id) {
 221         default:
 222                 /*
 223                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 224                  * here, so do warn if this get passed in
 225                  */
 226                 MISSING_CASE(id);
 227                 return DDI_CLK_SEL_NONE;
 228         case DPLL_ID_ICL_TBTPLL:
 229                 switch (clock) {
 230                 case 162000:
 231                         return DDI_CLK_SEL_TBT_162;
 232                 case 270000:
 233                         return DDI_CLK_SEL_TBT_270;
 234                 case 540000:
 235                         return DDI_CLK_SEL_TBT_540;
 236                 case 810000:
 237                         return DDI_CLK_SEL_TBT_810;
 238                 default:
 239                         MISSING_CASE(clock);
 240                         return DDI_CLK_SEL_NONE;
 241                 }
 242         case DPLL_ID_ICL_MGPLL1:
 243         case DPLL_ID_ICL_MGPLL2:
 244         case DPLL_ID_ICL_MGPLL3:
 245         case DPLL_ID_ICL_MGPLL4:
 246         case DPLL_ID_TGL_MGPLL5:
 247         case DPLL_ID_TGL_MGPLL6:
 248                 return DDI_CLK_SEL_MG;
 249         }
 250 }
 251
 252 static u32 ddi_buf_phy_link_rate(int port_clock)
 253 {
 254         switch (port_clock) {
 255         case 162000:
 256                 return DDI_BUF_PHY_LINK_RATE(0);
 257         case 216000:
 258                 return DDI_BUF_PHY_LINK_RATE(4);
 259         case 243000:
 260                 return DDI_BUF_PHY_LINK_RATE(5);
 261         case 270000:
 262                 return DDI_BUF_PHY_LINK_RATE(1);
 263         case 324000:
 264                 return DDI_BUF_PHY_LINK_RATE(6);
 265         case 432000:
 266                 return DDI_BUF_PHY_LINK_RATE(7);
 267         case 540000:
 268                 return DDI_BUF_PHY_LINK_RATE(2);
 269         case 810000:
 270                 return DDI_BUF_PHY_LINK_RATE(3);
 271         default:
 272                 MISSING_CASE(port_clock);
 273                 return DDI_BUF_PHY_LINK_RATE(0);
 274         }
 275 }
 276
 277 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 278                                       const struct intel_crtc_state *crtc_state)
 279 {
 280         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 281         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 282         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 283         enum phy phy = intel_port_to_phy(i915, encoder->port);
 284
 285         intel_dp->DP = dig_port->saved_port_bits |
 286                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 287         intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 288
 289         if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
 290                 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 291                 if (dig_port->tc_mode != TC_PORT_TBT_ALT)
 292                         intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 293         }
 294 }
 295
 296 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 297                                  enum port port)
 298 {
 299         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 300
 301         switch (val) {
 302         case DDI_CLK_SEL_NONE:
 303                 return 0;
 304         case DDI_CLK_SEL_TBT_162:
 305                 return 162000;
 306         case DDI_CLK_SEL_TBT_270:
 307                 return 270000;
 308         case DDI_CLK_SEL_TBT_540:
 309                 return 540000;
 310         case DDI_CLK_SEL_TBT_810:
 311                 return 810000;
 312         default:
 313                 MISSING_CASE(val);
 314                 return 0;
 315         }
 316 }
 317
 318 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 319 {
 320         int dotclock;
 321
 322         if (pipe_config->has_pch_encoder)
 323                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 324                                                     &pipe_config->fdi_m_n);
 325         else if (intel_crtc_has_dp_encoder(pipe_config))
 326                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 327                                                     &pipe_config->dp_m_n);
 328         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
 329                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
 330         else
 331                 dotclock = pipe_config->port_clock;
 332
 333         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
 334             !intel_crtc_has_dp_encoder(pipe_config))
 335                 dotclock *= 2;
 336
 337         if (pipe_config->pixel_multiplier)
 338                 dotclock /= pipe_config->pixel_multiplier;
 339
 340         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
 341 }
 342
 343 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 344                           const struct drm_connector_state *conn_state)
 345 {
 346         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 347         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 348         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 349         u32 temp;
 350
 351         if (!intel_crtc_has_dp_encoder(crtc_state))
 352                 return;
 353
 354         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 355
 356         temp = DP_MSA_MISC_SYNC_CLOCK;
 357
 358         switch (crtc_state->pipe_bpp) {
 359         case 18:
 360                 temp |= DP_MSA_MISC_6_BPC;
 361                 break;
 362         case 24:
 363                 temp |= DP_MSA_MISC_8_BPC;
 364                 break;
 365         case 30:
 366                 temp |= DP_MSA_MISC_10_BPC;
 367                 break;
 368         case 36:
 369                 temp |= DP_MSA_MISC_12_BPC;
 370                 break;
 371         default:
 372                 MISSING_CASE(crtc_state->pipe_bpp);
 373                 break;
 374         }
 375
 376         /* nonsense combination */
 377         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 378                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 379
 380         if (crtc_state->limited_color_range)
 381                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 382
 383         /*
 384          * As per DP 1.2 spec section 2.3.4.3 while sending
 385          * YCBCR 444 signals we should program MSA MISC1/0 fields with
 386          * colorspace information.
 387          */
 388         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 389                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 390
 391         /*
 392          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 393          * of Color Encoding Format and Content Color Gamut] while sending
 394          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 395          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 396          */
 397         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 398                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 399
 400         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 401 }
 402
 403 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 404 {
 405         if (master_transcoder == TRANSCODER_EDP)
 406                 return 0;
 407         else
 408                 return master_transcoder + 1;
 409 }
 410
 411 static void
 412 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
 413                                 const struct intel_crtc_state *crtc_state)
 414 {
 415         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 416         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 417         u32 val = 0;
 418
 419         if (intel_dp_is_uhbr(crtc_state))
 420                 val = TRANS_DP2_128B132B_CHANNEL_CODING;
 421
 422         intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
 423 }
 424
 425 /*
 426  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 427  *
 428  * Only intended to be used by intel_ddi_enable_transcoder_func() and
 429  * intel_ddi_config_transcoder_func().
 430  */
 431 static u32
 432 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 433                                       const struct intel_crtc_state *crtc_state)
 434 {
 435         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 436         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 437         enum pipe pipe = crtc->pipe;
 438         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 439         enum port port = encoder->port;
 440         u32 temp;
 441
 442         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 443         temp = TRANS_DDI_FUNC_ENABLE;
 444         if (DISPLAY_VER(dev_priv) >= 12)
 445                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 446         else
 447                 temp |= TRANS_DDI_SELECT_PORT(port);
 448
 449         switch (crtc_state->pipe_bpp) {
 450         case 18:
 451                 temp |= TRANS_DDI_BPC_6;
 452                 break;
 453         case 24:
 454                 temp |= TRANS_DDI_BPC_8;
 455                 break;
 456         case 30:
 457                 temp |= TRANS_DDI_BPC_10;
 458                 break;
 459         case 36:
 460                 temp |= TRANS_DDI_BPC_12;
 461                 break;
 462         default:
 463                 BUG();
 464         }
 465
 466         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 467                 temp |= TRANS_DDI_PVSYNC;
 468         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 469                 temp |= TRANS_DDI_PHSYNC;
 470
 471         if (cpu_transcoder == TRANSCODER_EDP) {
 472                 switch (pipe) {
 473                 case PIPE_A:
 474                         /* On Haswell, can only use the always-on power well for
 475                          * eDP when not using the panel fitter, and when not
 476                          * using motion blur mitigation (which we don't
 477                          * support). */
 478                         if (crtc_state->pch_pfit.force_thru)
 479                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 480                         else
 481                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 482                         break;
 483                 case PIPE_B:
 484                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 485                         break;
 486                 case PIPE_C:
 487                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 488                         break;
 489                 default:
 490                         BUG();
 491                         break;
 492                 }
 493         }
 494
 495         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 496                 if (crtc_state->has_hdmi_sink)
 497                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 498                 else
 499                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 500
 501                 if (crtc_state->hdmi_scrambling)
 502                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
 503                 if (crtc_state->hdmi_high_tmds_clock_ratio)
 504                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 505         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 506                 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 507                 temp |= (crtc_state->fdi_lanes - 1) << 1;
 508         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 509                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 510                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 511
 512                 if (DISPLAY_VER(dev_priv) >= 12) {
 513                         enum transcoder master;
 514
 515                         master = crtc_state->mst_master_transcoder;
 516                         drm_WARN_ON(&dev_priv->drm,
 517                                     master == INVALID_TRANSCODER);
 518                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 519                 }
 520         } else {
 521                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 522                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 523         }
 524
 525         if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
 526             crtc_state->master_transcoder != INVALID_TRANSCODER) {
 527                 u8 master_select =
 528                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 529
 530                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 531                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 532         }
 533
 534         return temp;
 535 }
 536
 537 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 538                                       const struct intel_crtc_state *crtc_state)
 539 {
 540         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 541         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 542         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 543
 544         if (DISPLAY_VER(dev_priv) >= 11) {
 545                 enum transcoder master_transcoder = crtc_state->master_transcoder;
 546                 u32 ctl2 = 0;
 547
 548                 if (master_transcoder != INVALID_TRANSCODER) {
 549                         u8 master_select =
 550                                 bdw_trans_port_sync_master_select(master_transcoder);
 551
 552                         ctl2 |= PORT_SYNC_MODE_ENABLE |
 553                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
 554                 }
 555
 556                 intel_de_write(dev_priv,
 557                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 558         }
 559
 560         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 561                        intel_ddi_transcoder_func_reg_val_get(encoder,
 562                                                              crtc_state));
 563 }
 564
 565 /*
 566  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 567  * bit.
 568  */
 569 static void
 570 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 571                                  const struct intel_crtc_state *crtc_state)
 572 {
 573         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 574         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 575         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 576         u32 ctl;
 577
 578         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 579         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 580         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 581 }
 582
 583 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 584 {
 585         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 586         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 587         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 588         u32 ctl;
 589
 590         if (DISPLAY_VER(dev_priv) >= 11)
 591                 intel_de_write(dev_priv,
 592                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 593
 594         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 595
 596         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 597
 598         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 599
 600         if (IS_DISPLAY_VER(dev_priv, 8, 10))
 601                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 602                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 603
 604         if (DISPLAY_VER(dev_priv) >= 12) {
 605                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
 606                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 607                                  TRANS_DDI_MODE_SELECT_MASK);
 608                 }
 609         } else {
 610                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 611         }
 612
 613         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 614
 615         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
 616             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 617                 drm_dbg_kms(&dev_priv->drm,
 618                             "Quirk Increase DDI disabled time\n");
 619                 /* Quirk time at 100ms for reliable operation */
 620                 msleep(100);
 621         }
 622 }
 623
 624 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 625                                enum transcoder cpu_transcoder,
 626                                bool enable, u32 hdcp_mask)
 627 {
 628         struct drm_device *dev = intel_encoder->base.dev;
 629         struct drm_i915_private *dev_priv = to_i915(dev);
 630         intel_wakeref_t wakeref;
 631         int ret = 0;
 632         u32 tmp;
 633
 634         wakeref = intel_display_power_get_if_enabled(dev_priv,
 635                                                      intel_encoder->power_domain);
 636         if (drm_WARN_ON(dev, !wakeref))
 637                 return -ENXIO;
 638
 639         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 640         if (enable)
 641                 tmp |= hdcp_mask;
 642         else
 643                 tmp &= ~hdcp_mask;
 644         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
 645         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 646         return ret;
 647 }
 648
 649 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 650 {
 651         struct drm_device *dev = intel_connector->base.dev;
 652         struct drm_i915_private *dev_priv = to_i915(dev);
 653         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 654         int type = intel_connector->base.connector_type;
 655         enum port port = encoder->port;
 656         enum transcoder cpu_transcoder;
 657         intel_wakeref_t wakeref;
 658         enum pipe pipe = 0;
 659         u32 tmp;
 660         bool ret;
 661
 662         wakeref = intel_display_power_get_if_enabled(dev_priv,
 663                                                      encoder->power_domain);
 664         if (!wakeref)
 665                 return false;
 666
 667         if (!encoder->get_hw_state(encoder, &pipe)) {
 668                 ret = false;
 669                 goto out;
 670         }
 671
 672         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 673                 cpu_transcoder = TRANSCODER_EDP;
 674         else
 675                 cpu_transcoder = (enum transcoder) pipe;
 676
 677         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 678
 679         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 680         case TRANS_DDI_MODE_SELECT_HDMI:
 681         case TRANS_DDI_MODE_SELECT_DVI:
 682                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
 683                 break;
 684
 685         case TRANS_DDI_MODE_SELECT_DP_SST:
 686                 ret = type == DRM_MODE_CONNECTOR_eDP ||
 687                       type == DRM_MODE_CONNECTOR_DisplayPort;
 688                 break;
 689
 690         case TRANS_DDI_MODE_SELECT_DP_MST:
 691                 /* if the transcoder is in MST state then
 692                  * connector isn't connected */
 693                 ret = false;
 694                 break;
 695
 696         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
 697                 ret = type == DRM_MODE_CONNECTOR_VGA;
 698                 break;
 699
 700         default:
 701                 ret = false;
 702                 break;
 703         }
 704
 705 out:
 706         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 707
 708         return ret;
 709 }
 710
 711 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 712                                         u8 *pipe_mask, bool *is_dp_mst)
 713 {
 714         struct drm_device *dev = encoder->base.dev;
 715         struct drm_i915_private *dev_priv = to_i915(dev);
 716         enum port port = encoder->port;
 717         intel_wakeref_t wakeref;
 718         enum pipe p;
 719         u32 tmp;
 720         u8 mst_pipe_mask;
 721
 722         *pipe_mask = 0;
 723         *is_dp_mst = false;
 724
 725         wakeref = intel_display_power_get_if_enabled(dev_priv,
 726                                                      encoder->power_domain);
 727         if (!wakeref)
 728                 return;
 729
 730         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 731         if (!(tmp & DDI_BUF_CTL_ENABLE))
 732                 goto out;
 733
 734         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 735                 tmp = intel_de_read(dev_priv,
 736                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 737
 738                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 739                 default:
 740                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 741                         fallthrough;
 742                 case TRANS_DDI_EDP_INPUT_A_ON:
 743                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 744                         *pipe_mask = BIT(PIPE_A);
 745                         break;
 746                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
 747                         *pipe_mask = BIT(PIPE_B);
 748                         break;
 749                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
 750                         *pipe_mask = BIT(PIPE_C);
 751                         break;
 752                 }
 753
 754                 goto out;
 755         }
 756
 757         mst_pipe_mask = 0;
 758         for_each_pipe(dev_priv, p) {
 759                 enum transcoder cpu_transcoder = (enum transcoder)p;
 760                 unsigned int port_mask, ddi_select;
 761                 intel_wakeref_t trans_wakeref;
 762
 763                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 764                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 765                 if (!trans_wakeref)
 766                         continue;
 767
 768                 if (DISPLAY_VER(dev_priv) >= 12) {
 769                         port_mask = TGL_TRANS_DDI_PORT_MASK;
 770                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 771                 } else {
 772                         port_mask = TRANS_DDI_PORT_MASK;
 773                         ddi_select = TRANS_DDI_SELECT_PORT(port);
 774                 }
 775
 776                 tmp = intel_de_read(dev_priv,
 777                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
 778                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 779                                         trans_wakeref);
 780
 781                 if ((tmp & port_mask) != ddi_select)
 782                         continue;
 783
 784                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
 785                     TRANS_DDI_MODE_SELECT_DP_MST)
 786                         mst_pipe_mask |= BIT(p);
 787
 788                 *pipe_mask |= BIT(p);
 789         }
 790
 791         if (!*pipe_mask)
 792                 drm_dbg_kms(&dev_priv->drm,
 793                             "No pipe for [ENCODER:%d:%s] found\n",
 794                             encoder->base.base.id, encoder->base.name);
 795
 796         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 797                 drm_dbg_kms(&dev_priv->drm,
 798                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 799                             encoder->base.base.id, encoder->base.name,
 800                             *pipe_mask);
 801                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
 802         }
 803
 804         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 805                 drm_dbg_kms(&dev_priv->drm,
 806                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 807                             encoder->base.base.id, encoder->base.name,
 808                             *pipe_mask, mst_pipe_mask);
 809         else
 810                 *is_dp_mst = mst_pipe_mask;
 811
 812 out:
 813         if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
 814                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 815                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 816                             BXT_PHY_LANE_POWERDOWN_ACK |
 817                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 818                         drm_err(&dev_priv->drm,
 819                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 820                                 encoder->base.base.id, encoder->base.name, tmp);
 821         }
 822
 823         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 824 }
 825
 826 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 827                             enum pipe *pipe)
 828 {
 829         u8 pipe_mask;
 830         bool is_mst;
 831
 832         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 833
 834         if (is_mst || !pipe_mask)
 835                 return false;
 836
 837         *pipe = ffs(pipe_mask) - 1;
 838
 839         return true;
 840 }
 841
 842 static enum intel_display_power_domain
 843 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 844 {
 845         /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 846          * DC states enabled at the same time, while for driver initiated AUX
 847          * transfers we need the same AUX IOs to be powered but with DC states
 848          * disabled. Accordingly use the AUX power domain here which leaves DC
 849          * states enabled.
 850          * However, for non-A AUX ports the corresponding non-EDP transcoders
 851          * would have already enabled power well 2 and DC_OFF. This means we can
 852          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
 853          * specific AUX_IO reference without powering up any extra wells.
 854          * Note that PSR is enabled only on Port A even though this function
 855          * returns the correct domain for other ports too.
 856          */
 857         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
 858                                               intel_aux_power_domain(dig_port);
 859 }
 860
 861 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 862                                         struct intel_crtc_state *crtc_state)
 863 {
 864         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 865         struct intel_digital_port *dig_port;
 866         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 867
 868         /*
 869          * TODO: Add support for MST encoders. Atm, the following should never
 870          * happen since fake-MST encoders don't set their get_power_domains()
 871          * hook.
 872          */
 873         if (drm_WARN_ON(&dev_priv->drm,
 874                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 875                 return;
 876
 877         dig_port = enc_to_dig_port(encoder);
 878
 879         if (!intel_phy_is_tc(dev_priv, phy) ||
 880             dig_port->tc_mode != TC_PORT_TBT_ALT) {
 881                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 882                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 883                                                                    dig_port->ddi_io_power_domain);
 884         }
 885
 886         /*
 887          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
 888          * ports.
 889          */
 890         if (intel_crtc_has_dp_encoder(crtc_state) ||
 891             intel_phy_is_tc(dev_priv, phy)) {
 892                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 893                 dig_port->aux_wakeref =
 894                         intel_display_power_get(dev_priv,
 895                                                 intel_ddi_main_link_aux_domain(dig_port));
 896         }
 897 }
 898
 899 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
 900                                  const struct intel_crtc_state *crtc_state)
 901 {
 902         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 903         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 904         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 905         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 906         u32 val;
 907
 908         if (cpu_transcoder != TRANSCODER_EDP) {
 909                 if (DISPLAY_VER(dev_priv) >= 13)
 910                         val = TGL_TRANS_CLK_SEL_PORT(phy);
 911                 else if (DISPLAY_VER(dev_priv) >= 12)
 912                         val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
 913                 else
 914                         val = TRANS_CLK_SEL_PORT(encoder->port);
 915
 916                 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 917         }
 918 }
 919
 920 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 921 {
 922         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 923         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 924
 925         if (cpu_transcoder != TRANSCODER_EDP) {
 926                 if (DISPLAY_VER(dev_priv) >= 12)
 927                         intel_de_write(dev_priv,
 928                                        TRANS_CLK_SEL(cpu_transcoder),
 929                                        TGL_TRANS_CLK_SEL_DISABLED);
 930                 else
 931                         intel_de_write(dev_priv,
 932                                        TRANS_CLK_SEL(cpu_transcoder),
 933                                        TRANS_CLK_SEL_DISABLED);
 934         }
 935 }
 936
 937 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 938                                 enum port port, u8 iboost)
 939 {
 940         u32 tmp;
 941
 942         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
 943         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
 944         if (iboost)
 945                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
 946         else
 947                 tmp |= BALANCE_LEG_DISABLE(port);
 948         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
 949 }
 950
 951 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 952                                const struct intel_crtc_state *crtc_state,
 953                                int level)
 954 {
 955         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 956         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 957         u8 iboost;
 958
 959         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 960                 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata);
 961         else
 962                 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata);
 963
 964         if (iboost == 0) {
 965                 const struct intel_ddi_buf_trans *ddi_translations;
 966                 int n_entries;
 967
 968                 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 969                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 970                         return;
 971                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
 972                         level = n_entries - 1;
 973
 974                 iboost = ddi_translations->entries[level].hsw.i_boost;
 975         }
 976
 977         /* Make sure that the requested I_boost is valid */
 978         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
 979                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
 980                 return;
 981         }
 982
 983         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
 984
 985         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
 986                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
 987 }
 988
 989 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 990                                     const struct intel_crtc_state *crtc_state,
 991                                     int level)
 992 {
 993         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 994         const struct intel_ddi_buf_trans *ddi_translations;
 995         enum port port = encoder->port;
 996         int n_entries;
 997
 998         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 999         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1000                 return;
1001         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1002                 level = n_entries - 1;
1003
1004         bxt_ddi_phy_set_signal_level(dev_priv, port,
1005                                      ddi_translations->entries[level].bxt.margin,
1006                                      ddi_translations->entries[level].bxt.scale,
1007                                      ddi_translations->entries[level].bxt.enable,
1008                                      ddi_translations->entries[level].bxt.deemphasis);
1009 }
1010
1011 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1012                                    const struct intel_crtc_state *crtc_state)
1013 {
1014         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1015         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1016         int n_entries;
1017
1018         encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1019
1020         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1021                 n_entries = 1;
1022         if (drm_WARN_ON(&dev_priv->drm,
1023                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1024                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1025
1026         return index_to_dp_signal_levels[n_entries - 1] &
1027                 DP_TRAIN_VOLTAGE_SWING_MASK;
1028 }
1029
1030 /*
1031  * We assume that the full set of pre-emphasis values can be
1032  * used on all DDI platforms. Should that change we need to
1033  * rethink this code.
1034  */
1035 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1036 {
1037         return DP_TRAIN_PRE_EMPH_LEVEL_3;
1038 }
1039
1040 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1041                                          const struct intel_crtc_state *crtc_state,
1042                                          int level)
1043 {
1044         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1045         const struct intel_ddi_buf_trans *ddi_translations;
1046         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1047         int n_entries, ln;
1048         u32 val;
1049
1050         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1051         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1052                 return;
1053         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1054                 level = n_entries - 1;
1055
1056         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1057                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1058
1059                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1060                 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
1061                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1062                              intel_dp->hobl_active ? val : 0);
1063         }
1064
1065         /* Set PORT_TX_DW5 */
1066         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1067         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1068                   TAP2_DISABLE | TAP3_DISABLE);
1069         val |= SCALING_MODE_SEL(0x2);
1070         val |= RTERM_SELECT(0x6);
1071         val |= TAP3_DISABLE;
1072         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1073
1074         /* Program PORT_TX_DW2 */
1075         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
1076         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
1077                  RCOMP_SCALAR_MASK);
1078         val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
1079         val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
1080         /* Program Rcomp scalar for every table entry */
1081         val |= RCOMP_SCALAR(0x98);
1082         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
1083
1084         /* Program PORT_TX_DW4 */
1085         /* We cannot write to GRP. It would overwrite individual loadgen. */
1086         for (ln = 0; ln <= 3; ln++) {
1087                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1088                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
1089                          CURSOR_COEFF_MASK);
1090                 val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
1091                 val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
1092                 val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
1093                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1094         }
1095
1096         /* Program PORT_TX_DW7 */
1097         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
1098         val &= ~N_SCALAR_MASK;
1099         val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
1100         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
1101 }
1102
1103 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1104                                               const struct intel_crtc_state *crtc_state,
1105                                               int level)
1106 {
1107         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1108         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1109         int width, rate, ln;
1110         u32 val;
1111
1112         width = crtc_state->lane_count;
1113         rate = crtc_state->port_clock;
1114
1115         /*
1116          * 1. If port type is eDP or DP,
1117          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1118          * else clear to 0b.
1119          */
1120         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
1121         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1122                 val &= ~COMMON_KEEPER_EN;
1123         else
1124                 val |= COMMON_KEEPER_EN;
1125         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1126
1127         /* 2. Program loadgen select */
1128         /*
1129          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
1130          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1131          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1132          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1133          */
1134         for (ln = 0; ln <= 3; ln++) {
1135                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
1136                 val &= ~LOADGEN_SELECT;
1137
1138                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
1139                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
1140                         val |= LOADGEN_SELECT;
1141                 }
1142                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
1143         }
1144
1145         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1146         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
1147         val |= SUS_CLOCK_CONFIG;
1148         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
1149
1150         /* 4. Clear training enable to change swing values */
1151         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1152         val &= ~TX_TRAINING_EN;
1153         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1154
1155         /* 5. Program swing and de-emphasis */
1156         icl_ddi_combo_vswing_program(encoder, crtc_state, level);
1157
1158         /* 6. Set training enable to trigger update */
1159         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
1160         val |= TX_TRAINING_EN;
1161         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1162 }
1163
1164 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1165                                            const struct intel_crtc_state *crtc_state,
1166                                            int level)
1167 {
1168         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1169         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1170         const struct intel_ddi_buf_trans *ddi_translations;
1171         int n_entries, ln;
1172         u32 val;
1173
1174         if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1175                 return;
1176
1177         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1178         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1179                 return;
1180         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1181                 level = n_entries - 1;
1182
1183         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
1184         for (ln = 0; ln < 2; ln++) {
1185                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
1186                 val &= ~CRI_USE_FS32;
1187                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
1188
1189                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
1190                 val &= ~CRI_USE_FS32;
1191                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
1192         }
1193
1194         /* Program MG_TX_SWINGCTRL with values from vswing table */
1195         for (ln = 0; ln < 2; ln++) {
1196                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
1197                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1198                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1199                         ddi_translations->entries[level].mg.cri_txdeemph_override_17_12);
1200                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
1201
1202                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
1203                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
1204                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
1205                         ddi_translations->entries[level].mg.cri_txdeemph_override_17_12);
1206                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
1207         }
1208
1209         /* Program MG_TX_DRVCTRL with values from vswing table */
1210         for (ln = 0; ln < 2; ln++) {
1211                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
1212                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1213                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1214                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1215                         ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) |
1216                         CRI_TXDEEMPH_OVERRIDE_11_6(
1217                                 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) |
1218                         CRI_TXDEEMPH_OVERRIDE_EN;
1219                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
1220
1221                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
1222                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1223                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
1224                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
1225                         ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) |
1226                         CRI_TXDEEMPH_OVERRIDE_11_6(
1227                                 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) |
1228                         CRI_TXDEEMPH_OVERRIDE_EN;
1229                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
1230
1231                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1232         }
1233
1234         /*
1235          * Program MG_CLKHUB<LN, port being used> with value from frequency table
1236          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1237          * values from table for which TX1 and TX2 enabled.
1238          */
1239         for (ln = 0; ln < 2; ln++) {
1240                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
1241                 if (crtc_state->port_clock < 300000)
1242                         val |= CFG_LOW_RATE_LKREN_EN;
1243                 else
1244                         val &= ~CFG_LOW_RATE_LKREN_EN;
1245                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
1246         }
1247
1248         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1249         for (ln = 0; ln < 2; ln++) {
1250                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
1251                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1252                 if (crtc_state->port_clock <= 500000) {
1253                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1254                 } else {
1255                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1256                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1257                 }
1258                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
1259
1260                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
1261                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
1262                 if (crtc_state->port_clock <= 500000) {
1263                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
1264                 } else {
1265                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
1266                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
1267                 }
1268                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
1269         }
1270
1271         /* Program MG_TX_PISO_READLOAD with values from vswing table */
1272         for (ln = 0; ln < 2; ln++) {
1273                 val = intel_de_read(dev_priv,
1274                                     MG_TX1_PISO_READLOAD(ln, tc_port));
1275                 val |= CRI_CALCINIT;
1276                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1277                                val);
1278
1279                 val = intel_de_read(dev_priv,
1280                                     MG_TX2_PISO_READLOAD(ln, tc_port));
1281                 val |= CRI_CALCINIT;
1282                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1283                                val);
1284         }
1285 }
1286
1287 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
1288                                     const struct intel_crtc_state *crtc_state,
1289                                     int level)
1290 {
1291         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1292         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1293
1294         if (intel_phy_is_combo(dev_priv, phy))
1295                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1296         else
1297                 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1298 }
1299
1300 static void
1301 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
1302                                 const struct intel_crtc_state *crtc_state,
1303                                 int level)
1304 {
1305         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1306         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1307         const struct intel_ddi_buf_trans *ddi_translations;
1308         u32 val, dpcnt_mask, dpcnt_val;
1309         int n_entries, ln;
1310
1311         if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
1312                 return;
1313
1314         ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1315         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1316                 return;
1317         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1318                 level = n_entries - 1;
1319
1320         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
1321                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1322                       DKL_TX_VSWING_CONTROL_MASK);
1323         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control);
1324         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control);
1325         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control);
1326
1327         for (ln = 0; ln < 2; ln++) {
1328                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1329                                HIP_INDEX_VAL(tc_port, ln));
1330
1331                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
1332
1333                 /* All the registers are RMW */
1334                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
1335                 val &= ~dpcnt_mask;
1336                 val |= dpcnt_val;
1337                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
1338
1339                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
1340                 val &= ~dpcnt_mask;
1341                 val |= dpcnt_val;
1342                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
1343
1344                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
1345                 val &= ~DKL_TX_DP20BITMODE;
1346                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
1347
1348                 if ((intel_crtc_has_dp_encoder(crtc_state) &&
1349                      crtc_state->port_clock == 162000) ||
1350                     (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1351                      crtc_state->port_clock == 594000))
1352                         val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
1353                 else
1354                         val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
1355         }
1356 }
1357
1358 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
1359                                     const struct intel_crtc_state *crtc_state,
1360                                     int level)
1361 {
1362         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1363         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1364
1365         if (intel_phy_is_combo(dev_priv, phy))
1366                 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1367         else
1368                 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1369 }
1370
1371 static int translate_signal_level(struct intel_dp *intel_dp,
1372                                   u8 signal_levels)
1373 {
1374         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1375         int i;
1376
1377         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1378                 if (index_to_dp_signal_levels[i] == signal_levels)
1379                         return i;
1380         }
1381
1382         drm_WARN(&i915->drm, 1,
1383                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1384                  signal_levels);
1385
1386         return 0;
1387 }
1388
1389 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1390                               const struct intel_crtc_state *crtc_state)
1391 {
1392         u8 train_set = intel_dp->train_set[0];
1393         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1394                                         DP_TRAIN_PRE_EMPHASIS_MASK);
1395
1396         return translate_signal_level(intel_dp, signal_levels);
1397 }
1398
1399 static void
1400 dg2_set_signal_levels(struct intel_dp *intel_dp,
1401                       const struct intel_crtc_state *crtc_state)
1402 {
1403         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1404         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1405
1406         intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
1407 }
1408
1409 static void
1410 tgl_set_signal_levels(struct intel_dp *intel_dp,
1411                       const struct intel_crtc_state *crtc_state)
1412 {
1413         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1414         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1415
1416         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
1417 }
1418
1419 static void
1420 icl_set_signal_levels(struct intel_dp *intel_dp,
1421                       const struct intel_crtc_state *crtc_state)
1422 {
1423         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1424         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1425
1426         icl_ddi_vswing_sequence(encoder, crtc_state, level);
1427 }
1428
1429 static void
1430 bxt_set_signal_levels(struct intel_dp *intel_dp,
1431                       const struct intel_crtc_state *crtc_state)
1432 {
1433         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1434         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1435
1436         bxt_ddi_vswing_sequence(encoder, crtc_state, level);
1437 }
1438
1439 static void
1440 hsw_set_signal_levels(struct intel_dp *intel_dp,
1441                       const struct intel_crtc_state *crtc_state)
1442 {
1443         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1444         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1445         int level = intel_ddi_dp_level(intel_dp, crtc_state);
1446         enum port port = encoder->port;
1447         u32 signal_levels;
1448
1449         signal_levels = DDI_BUF_TRANS_SELECT(level);
1450
1451         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1452                     signal_levels);
1453
1454         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1455         intel_dp->DP |= signal_levels;
1456
1457         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
1458                 skl_ddi_set_iboost(encoder, crtc_state, level);
1459
1460         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1461         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1462 }
1463
1464 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1465                                   u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1466 {
1467         mutex_lock(&i915->dpll.lock);
1468
1469         intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1470
1471         /*
1472          * "This step and the step before must be
1473          *  done with separate register writes."
1474          */
1475         intel_de_rmw(i915, reg, clk_off, 0);
1476
1477         mutex_unlock(&i915->dpll.lock);
1478 }
1479
1480 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1481                                    u32 clk_off)
1482 {
1483         mutex_lock(&i915->dpll.lock);
1484
1485         intel_de_rmw(i915, reg, 0, clk_off);
1486
1487         mutex_unlock(&i915->dpll.lock);
1488 }
1489
1490 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1491                                       u32 clk_off)
1492 {
1493         return !(intel_de_read(i915, reg) & clk_off);
1494 }
1495
1496 static struct intel_shared_dpll *
1497 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1498                  u32 clk_sel_mask, u32 clk_sel_shift)
1499 {
1500         enum intel_dpll_id id;
1501
1502         id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1503
1504         return intel_get_shared_dpll_by_id(i915, id);
1505 }
1506
1507 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1508                                   const struct intel_crtc_state *crtc_state)
1509 {
1510         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1511         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1512         enum phy phy = intel_port_to_phy(i915, encoder->port);
1513
1514         if (drm_WARN_ON(&i915->drm, !pll))
1515                 return;
1516
1517         _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1518                               ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1519                               pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1520                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1521 }
1522
1523 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1524 {
1525         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1526         enum phy phy = intel_port_to_phy(i915, encoder->port);
1527
1528         _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1529                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1530 }
1531
1532 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1533 {
1534         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1535         enum phy phy = intel_port_to_phy(i915, encoder->port);
1536
1537         return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1538                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1539 }
1540
1541 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1542 {
1543         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1544         enum phy phy = intel_port_to_phy(i915, encoder->port);
1545
1546         return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1547                                 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1548                                 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1549 }
1550
1551 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1552                                  const struct intel_crtc_state *crtc_state)
1553 {
1554         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1555         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1556         enum phy phy = intel_port_to_phy(i915, encoder->port);
1557
1558         if (drm_WARN_ON(&i915->drm, !pll))
1559                 return;
1560
1561         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1562                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1563                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1564                               RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1565 }
1566
1567 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1568 {
1569         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1570         enum phy phy = intel_port_to_phy(i915, encoder->port);
1571
1572         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1573                                RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1574 }
1575
1576 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1577 {
1578         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1579         enum phy phy = intel_port_to_phy(i915, encoder->port);
1580
1581         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1582                                          RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1583 }
1584
1585 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1586 {
1587         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1588         enum phy phy = intel_port_to_phy(i915, encoder->port);
1589
1590         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1591                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1592                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1593 }
1594
1595 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1596                                  const struct intel_crtc_state *crtc_state)
1597 {
1598         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1599         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1600         enum phy phy = intel_port_to_phy(i915, encoder->port);
1601
1602         if (drm_WARN_ON(&i915->drm, !pll))
1603                 return;
1604
1605         /*
1606          * If we fail this, something went very wrong: first 2 PLLs should be
1607          * used by first 2 phys and last 2 PLLs by last phys
1608          */
1609         if (drm_WARN_ON(&i915->drm,
1610                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1611                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1612                 return;
1613
1614         _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1615                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1616                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1617                               DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1618 }
1619
1620 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1621 {
1622         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1623         enum phy phy = intel_port_to_phy(i915, encoder->port);
1624
1625         _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1626                                DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1627 }
1628
1629 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1630 {
1631         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1632         enum phy phy = intel_port_to_phy(i915, encoder->port);
1633
1634         return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1635                                          DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1636 }
1637
1638 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1639 {
1640         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1641         enum phy phy = intel_port_to_phy(i915, encoder->port);
1642         enum intel_dpll_id id;
1643         u32 val;
1644
1645         val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1646         val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1647         val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1648         id = val;
1649
1650         /*
1651          * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1652          * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1653          * bit for phy C and D.
1654          */
1655         if (phy >= PHY_C)
1656                 id += DPLL_ID_DG1_DPLL2;
1657
1658         return intel_get_shared_dpll_by_id(i915, id);
1659 }
1660
1661 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1662                                        const struct intel_crtc_state *crtc_state)
1663 {
1664         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1665         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1666         enum phy phy = intel_port_to_phy(i915, encoder->port);
1667
1668         if (drm_WARN_ON(&i915->drm, !pll))
1669                 return;
1670
1671         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1672                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1673                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1674                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1675 }
1676
1677 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1678 {
1679         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1680         enum phy phy = intel_port_to_phy(i915, encoder->port);
1681
1682         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1683                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1684 }
1685
1686 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1687 {
1688         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1689         enum phy phy = intel_port_to_phy(i915, encoder->port);
1690
1691         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1692                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1693 }
1694
1695 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1696 {
1697         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1698         enum phy phy = intel_port_to_phy(i915, encoder->port);
1699
1700         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1701                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1702                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1703 }
1704
1705 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1706                                     const struct intel_crtc_state *crtc_state)
1707 {
1708         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1709         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1710         enum port port = encoder->port;
1711
1712         if (drm_WARN_ON(&i915->drm, !pll))
1713                 return;
1714
1715         /*
1716          * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1717          *  MG does not exist, but the programming is required to ungate DDIC and DDID."
1718          */
1719         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1720
1721         icl_ddi_combo_enable_clock(encoder, crtc_state);
1722 }
1723
1724 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1725 {
1726         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1727         enum port port = encoder->port;
1728
1729         icl_ddi_combo_disable_clock(encoder);
1730
1731         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1732 }
1733
1734 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1735 {
1736         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1737         enum port port = encoder->port;
1738         u32 tmp;
1739
1740         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1741
1742         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1743                 return false;
1744
1745         return icl_ddi_combo_is_clock_enabled(encoder);
1746 }
1747
1748 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1749                                     const struct intel_crtc_state *crtc_state)
1750 {
1751         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1752         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1753         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1754         enum port port = encoder->port;
1755
1756         if (drm_WARN_ON(&i915->drm, !pll))
1757                 return;
1758
1759         intel_de_write(i915, DDI_CLK_SEL(port),
1760                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1761
1762         mutex_lock(&i915->dpll.lock);
1763
1764         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1765                      ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1766
1767         mutex_unlock(&i915->dpll.lock);
1768 }
1769
1770 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1771 {
1772         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1773         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1774         enum port port = encoder->port;
1775
1776         mutex_lock(&i915->dpll.lock);
1777
1778         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1779                      0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1780
1781         mutex_unlock(&i915->dpll.lock);
1782
1783         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1784 }
1785
1786 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1787 {
1788         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1789         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1790         enum port port = encoder->port;
1791         u32 tmp;
1792
1793         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1794
1795         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1796                 return false;
1797
1798         tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1799
1800         return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1801 }
1802
1803 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1804 {
1805         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1806         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1807         enum port port = encoder->port;
1808         enum intel_dpll_id id;
1809         u32 tmp;
1810
1811         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1812
1813         switch (tmp & DDI_CLK_SEL_MASK) {
1814         case DDI_CLK_SEL_TBT_162:
1815         case DDI_CLK_SEL_TBT_270:
1816         case DDI_CLK_SEL_TBT_540:
1817         case DDI_CLK_SEL_TBT_810:
1818                 id = DPLL_ID_ICL_TBTPLL;
1819                 break;
1820         case DDI_CLK_SEL_MG:
1821                 id = icl_tc_port_to_pll_id(tc_port);
1822                 break;
1823         default:
1824                 MISSING_CASE(tmp);
1825                 fallthrough;
1826         case DDI_CLK_SEL_NONE:
1827                 return NULL;
1828         }
1829
1830         return intel_get_shared_dpll_by_id(i915, id);
1831 }
1832
1833 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1834 {
1835         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1836         enum intel_dpll_id id;
1837
1838         switch (encoder->port) {
1839         case PORT_A:
1840                 id = DPLL_ID_SKL_DPLL0;
1841                 break;
1842         case PORT_B:
1843                 id = DPLL_ID_SKL_DPLL1;
1844                 break;
1845         case PORT_C:
1846                 id = DPLL_ID_SKL_DPLL2;
1847                 break;
1848         default:
1849                 MISSING_CASE(encoder->port);
1850                 return NULL;
1851         }
1852
1853         return intel_get_shared_dpll_by_id(i915, id);
1854 }
1855
1856 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1857                                  const struct intel_crtc_state *crtc_state)
1858 {
1859         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1860         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1861         enum port port = encoder->port;
1862
1863         if (drm_WARN_ON(&i915->drm, !pll))
1864                 return;
1865
1866         mutex_lock(&i915->dpll.lock);
1867
1868         intel_de_rmw(i915, DPLL_CTRL2,
1869                      DPLL_CTRL2_DDI_CLK_OFF(port) |
1870                      DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1871                      DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1872                      DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1873
1874         mutex_unlock(&i915->dpll.lock);
1875 }
1876
1877 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1878 {
1879         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1880         enum port port = encoder->port;
1881
1882         mutex_lock(&i915->dpll.lock);
1883
1884         intel_de_rmw(i915, DPLL_CTRL2,
1885                      0, DPLL_CTRL2_DDI_CLK_OFF(port));
1886
1887         mutex_unlock(&i915->dpll.lock);
1888 }
1889
1890 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1891 {
1892         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1893         enum port port = encoder->port;
1894
1895         /*
1896          * FIXME Not sure if the override affects both
1897          * the PLL selection and the CLK_OFF bit.
1898          */
1899         return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1900 }
1901
1902 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1903 {
1904         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1905         enum port port = encoder->port;
1906         enum intel_dpll_id id;
1907         u32 tmp;
1908
1909         tmp = intel_de_read(i915, DPLL_CTRL2);
1910
1911         /*
1912          * FIXME Not sure if the override affects both
1913          * the PLL selection and the CLK_OFF bit.
1914          */
1915         if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1916                 return NULL;
1917
1918         id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1919                 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1920
1921         return intel_get_shared_dpll_by_id(i915, id);
1922 }
1923
1924 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1925                           const struct intel_crtc_state *crtc_state)
1926 {
1927         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1928         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1929         enum port port = encoder->port;
1930
1931         if (drm_WARN_ON(&i915->drm, !pll))
1932                 return;
1933
1934         intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1935 }
1936
1937 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1938 {
1939         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1940         enum port port = encoder->port;
1941
1942         intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1943 }
1944
1945 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1946 {
1947         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1948         enum port port = encoder->port;
1949
1950         return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1951 }
1952
1953 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1954 {
1955         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1956         enum port port = encoder->port;
1957         enum intel_dpll_id id;
1958         u32 tmp;
1959
1960         tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1961
1962         switch (tmp & PORT_CLK_SEL_MASK) {
1963         case PORT_CLK_SEL_WRPLL1:
1964                 id = DPLL_ID_WRPLL1;
1965                 break;
1966         case PORT_CLK_SEL_WRPLL2:
1967                 id = DPLL_ID_WRPLL2;
1968                 break;
1969         case PORT_CLK_SEL_SPLL:
1970                 id = DPLL_ID_SPLL;
1971                 break;
1972         case PORT_CLK_SEL_LCPLL_810:
1973                 id = DPLL_ID_LCPLL_810;
1974                 break;
1975         case PORT_CLK_SEL_LCPLL_1350:
1976                 id = DPLL_ID_LCPLL_1350;
1977                 break;
1978         case PORT_CLK_SEL_LCPLL_2700:
1979                 id = DPLL_ID_LCPLL_2700;
1980                 break;
1981         default:
1982                 MISSING_CASE(tmp);
1983                 fallthrough;
1984         case PORT_CLK_SEL_NONE:
1985                 return NULL;
1986         }
1987
1988         return intel_get_shared_dpll_by_id(i915, id);
1989 }
1990
1991 void intel_ddi_enable_clock(struct intel_encoder *encoder,
1992                             const struct intel_crtc_state *crtc_state)
1993 {
1994         if (encoder->enable_clock)
1995                 encoder->enable_clock(encoder, crtc_state);
1996 }
1997
1998 static void intel_ddi_disable_clock(struct intel_encoder *encoder)
1999 {
2000         if (encoder->disable_clock)
2001                 encoder->disable_clock(encoder);
2002 }
2003
2004 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2005 {
2006         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2007         u32 port_mask;
2008         bool ddi_clk_needed;
2009
2010         /*
2011          * In case of DP MST, we sanitize the primary encoder only, not the
2012          * virtual ones.
2013          */
2014         if (encoder->type == INTEL_OUTPUT_DP_MST)
2015                 return;
2016
2017         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2018                 u8 pipe_mask;
2019                 bool is_mst;
2020
2021                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2022                 /*
2023                  * In the unlikely case that BIOS enables DP in MST mode, just
2024                  * warn since our MST HW readout is incomplete.
2025                  */
2026                 if (drm_WARN_ON(&i915->drm, is_mst))
2027                         return;
2028         }
2029
2030         port_mask = BIT(encoder->port);
2031         ddi_clk_needed = encoder->base.crtc;
2032
2033         if (encoder->type == INTEL_OUTPUT_DSI) {
2034                 struct intel_encoder *other_encoder;
2035
2036                 port_mask = intel_dsi_encoder_ports(encoder);
2037                 /*
2038                  * Sanity check that we haven't incorrectly registered another
2039                  * encoder using any of the ports of this DSI encoder.
2040                  */
2041                 for_each_intel_encoder(&i915->drm, other_encoder) {
2042                         if (other_encoder == encoder)
2043                                 continue;
2044
2045                         if (drm_WARN_ON(&i915->drm,
2046                                         port_mask & BIT(other_encoder->port)))
2047                                 return;
2048                 }
2049                 /*
2050                  * For DSI we keep the ddi clocks gated
2051                  * except during enable/disable sequence.
2052                  */
2053                 ddi_clk_needed = false;
2054         }
2055
2056         if (ddi_clk_needed || !encoder->is_clock_enabled ||
2057             !encoder->is_clock_enabled(encoder))
2058                 return;
2059
2060         drm_notice(&i915->drm,
2061                    "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2062                    encoder->base.base.id, encoder->base.name);
2063
2064         encoder->disable_clock(encoder);
2065 }
2066
2067 static void
2068 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2069                        const struct intel_crtc_state *crtc_state)
2070 {
2071         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2072         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2073         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2074         u32 ln0, ln1, pin_assignment;
2075         u8 width;
2076
2077         if (!intel_phy_is_tc(dev_priv, phy) ||
2078             dig_port->tc_mode == TC_PORT_TBT_ALT)
2079                 return;
2080
2081         if (DISPLAY_VER(dev_priv) >= 12) {
2082                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2083                                HIP_INDEX_VAL(tc_port, 0x0));
2084                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2085                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2086                                HIP_INDEX_VAL(tc_port, 0x1));
2087                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2088         } else {
2089                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2090                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2091         }
2092
2093         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2094         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2095
2096         /* DPPATC */
2097         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2098         width = crtc_state->lane_count;
2099
2100         switch (pin_assignment) {
2101         case 0x0:
2102                 drm_WARN_ON(&dev_priv->drm,
2103                             dig_port->tc_mode != TC_PORT_LEGACY);
2104                 if (width == 1) {
2105                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2106                 } else {
2107                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2108                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2109                 }
2110                 break;
2111         case 0x1:
2112                 if (width == 4) {
2113                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2114                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2115                 }
2116                 break;
2117         case 0x2:
2118                 if (width == 2) {
2119                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2120                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2121                 }
2122                 break;
2123         case 0x3:
2124         case 0x5:
2125                 if (width == 1) {
2126                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2127                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2128                 } else {
2129                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2130                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2131                 }
2132                 break;
2133         case 0x4:
2134         case 0x6:
2135                 if (width == 1) {
2136                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2137                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2138                 } else {
2139                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2140                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2141                 }
2142                 break;
2143         default:
2144                 MISSING_CASE(pin_assignment);
2145         }
2146
2147         if (DISPLAY_VER(dev_priv) >= 12) {
2148                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2149                                HIP_INDEX_VAL(tc_port, 0x0));
2150                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
2151                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2152                                HIP_INDEX_VAL(tc_port, 0x1));
2153                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
2154         } else {
2155                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2156                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2157         }
2158 }
2159
2160 static enum transcoder
2161 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2162 {
2163         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2164                 return crtc_state->mst_master_transcoder;
2165         else
2166                 return crtc_state->cpu_transcoder;
2167 }
2168
2169 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2170                          const struct intel_crtc_state *crtc_state)
2171 {
2172         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2173
2174         if (DISPLAY_VER(dev_priv) >= 12)
2175                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2176         else
2177                 return DP_TP_CTL(encoder->port);
2178 }
2179
2180 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2181                             const struct intel_crtc_state *crtc_state)
2182 {
2183         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2184
2185         if (DISPLAY_VER(dev_priv) >= 12)
2186                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2187         else
2188                 return DP_TP_STATUS(encoder->port);
2189 }
2190
2191 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2192                                                           const struct intel_crtc_state *crtc_state,
2193                                                           bool enable)
2194 {
2195         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2196
2197         if (!crtc_state->vrr.enable)
2198                 return;
2199
2200         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2201                                enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2202                 drm_dbg_kms(&i915->drm,
2203                             "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2204                             enabledisable(enable));
2205 }
2206
2207 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2208                                         const struct intel_crtc_state *crtc_state)
2209 {
2210         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2211
2212         if (!crtc_state->fec_enable)
2213                 return;
2214
2215         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2216                 drm_dbg_kms(&i915->drm,
2217                             "Failed to set FEC_READY in the sink\n");
2218 }
2219
2220 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2221                                  const struct intel_crtc_state *crtc_state)
2222 {
2223         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2224         struct intel_dp *intel_dp;
2225         u32 val;
2226
2227         if (!crtc_state->fec_enable)
2228                 return;
2229
2230         intel_dp = enc_to_intel_dp(encoder);
2231         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2232         val |= DP_TP_CTL_FEC_ENABLE;
2233         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2234 }
2235
2236 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2237                                         const struct intel_crtc_state *crtc_state)
2238 {
2239         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2240         struct intel_dp *intel_dp;
2241         u32 val;
2242
2243         if (!crtc_state->fec_enable)
2244                 return;
2245
2246         intel_dp = enc_to_intel_dp(encoder);
2247         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2248         val &= ~DP_TP_CTL_FEC_ENABLE;
2249         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2250         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2251 }
2252
2253 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2254                                      const struct intel_crtc_state *crtc_state)
2255 {
2256         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2257         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2258         enum phy phy = intel_port_to_phy(i915, encoder->port);
2259
2260         if (intel_phy_is_combo(i915, phy)) {
2261                 bool lane_reversal =
2262                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2263
2264                 intel_combo_phy_power_up_lanes(i915, phy, false,
2265                                                crtc_state->lane_count,
2266                                                lane_reversal);
2267         }
2268 }
2269
2270 /* Splitter enable for eDP MSO is limited to certain pipes. */
2271 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2272 {
2273         if (IS_ALDERLAKE_P(i915))
2274                 return BIT(PIPE_A) | BIT(PIPE_B);
2275         else
2276                 return BIT(PIPE_A);
2277 }
2278
2279 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2280                                      struct intel_crtc_state *pipe_config)
2281 {
2282         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2283         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2284         enum pipe pipe = crtc->pipe;
2285         u32 dss1;
2286
2287         if (!HAS_MSO(i915))
2288                 return;
2289
2290         dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2291
2292         pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2293         if (!pipe_config->splitter.enable)
2294                 return;
2295
2296         if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2297                 pipe_config->splitter.enable = false;
2298                 return;
2299         }
2300
2301         switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2302         default:
2303                 drm_WARN(&i915->drm, true,
2304                          "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2305                 fallthrough;
2306         case SPLITTER_CONFIGURATION_2_SEGMENT:
2307                 pipe_config->splitter.link_count = 2;
2308                 break;
2309         case SPLITTER_CONFIGURATION_4_SEGMENT:
2310                 pipe_config->splitter.link_count = 4;
2311                 break;
2312         }
2313
2314         pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2315 }
2316
2317 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2318 {
2319         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2320         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2321         enum pipe pipe = crtc->pipe;
2322         u32 dss1 = 0;
2323
2324         if (!HAS_MSO(i915))
2325                 return;
2326
2327         if (crtc_state->splitter.enable) {
2328                 dss1 |= SPLITTER_ENABLE;
2329                 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2330                 if (crtc_state->splitter.link_count == 2)
2331                         dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2332                 else
2333                         dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2334         }
2335
2336         intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2337                      SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2338                      OVERLAP_PIXELS_MASK, dss1);
2339 }
2340
2341 static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
2342                                   struct intel_encoder *encoder,
2343                                   const struct intel_crtc_state *crtc_state,
2344                                   const struct drm_connector_state *conn_state)
2345 {
2346         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2347         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2348         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2349         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2350         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2351         int level = intel_ddi_dp_level(intel_dp, crtc_state);
2352
2353         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
2354                                  crtc_state->lane_count);
2355
2356         /*
2357          * 1. Enable Power Wells
2358          *
2359          * This was handled at the beginning of intel_atomic_commit_tail(),
2360          * before we called down into this function.
2361          */
2362
2363         /* 2. Enable Panel Power if PPS is required */
2364         intel_pps_on(intel_dp);
2365
2366         /*
2367          * 3. Enable the port PLL.
2368          */
2369         intel_ddi_enable_clock(encoder, crtc_state);
2370
2371         /* 4. Enable IO power */
2372         if (!intel_phy_is_tc(dev_priv, phy) ||
2373             dig_port->tc_mode != TC_PORT_TBT_ALT)
2374                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2375                                                                    dig_port->ddi_io_power_domain);
2376
2377         /*
2378          * 5. The rest of the below are substeps under the bspec's "Enable and
2379          * Train Display Port" step.  Note that steps that are specific to
2380          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2381          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2382          * us when active_mst_links==0, so any steps designated for "single
2383          * stream or multi-stream master transcoder" can just be performed
2384          * unconditionally here.
2385          */
2386
2387         /*
2388          * 5.a Configure Transcoder Clock Select to direct the Port clock to the
2389          * Transcoder.
2390          */
2391         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2392
2393         /* 5.b Configure transcoder for DP 2.0 128b/132b */
2394         intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2395
2396         /*
2397          * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2398          * Transport Select
2399          */
2400         intel_ddi_config_transcoder_func(encoder, crtc_state);
2401
2402         /*
2403          * 5.d Configure & enable DP_TP_CTL with link training pattern 1
2404          * selected
2405          *
2406          * This will be handled by the intel_dp_start_link_train() farther
2407          * down this function.
2408          */
2409
2410         /* 5.e Configure voltage swing and related IO settings */
2411         intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2412
2413         /*
2414          * 5.f Configure and enable DDI_BUF_CTL
2415          * 5.g Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
2416          *     after 1200 us.
2417          *
2418          * We only configure what the register value will be here.  Actual
2419          * enabling happens during link training farther down.
2420          */
2421         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2422
2423         if (!is_mst)
2424                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2425
2426         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2427         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2428         /*
2429          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2430          * in the FEC_CONFIGURATION register to 1 before initiating link
2431          * training
2432          */
2433         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2434         intel_dp_check_frl_training(intel_dp);
2435         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2436
2437         /*
2438          * 5.h Follow DisplayPort specification training sequence (see notes for
2439          *     failure handling)
2440          * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2441          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2442          *     (timeout after 800 us)
2443          */
2444         intel_dp_start_link_train(intel_dp, crtc_state);
2445
2446         /* 5.j Set DP_TP_CTL link training to Normal */
2447         if (!is_trans_port_sync_mode(crtc_state))
2448                 intel_dp_stop_link_train(intel_dp, crtc_state);
2449
2450         /* 5.k Configure and enable FEC if needed */
2451         intel_ddi_enable_fec(encoder, crtc_state);
2452         intel_dsc_enable(encoder, crtc_state);
2453 }
2454
2455 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2456                                   struct intel_encoder *encoder,
2457                                   const struct intel_crtc_state *crtc_state,
2458                                   const struct drm_connector_state *conn_state)
2459 {
2460         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2461         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2462         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2463         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2464         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2465         int level = intel_ddi_dp_level(intel_dp, crtc_state);
2466
2467         intel_dp_set_link_params(intel_dp,
2468                                  crtc_state->port_clock,
2469                                  crtc_state->lane_count);
2470
2471         /*
2472          * 1. Enable Power Wells
2473          *
2474          * This was handled at the beginning of intel_atomic_commit_tail(),
2475          * before we called down into this function.
2476          */
2477
2478         /* 2. Enable Panel Power if PPS is required */
2479         intel_pps_on(intel_dp);
2480
2481         /*
2482          * 3. For non-TBT Type-C ports, set FIA lane count
2483          * (DFLEXDPSP.DPX4TXLATC)
2484          *
2485          * This was done before tgl_ddi_pre_enable_dp by
2486          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2487          */
2488
2489         /*
2490          * 4. Enable the port PLL.
2491          *
2492          * The PLL enabling itself was already done before this function by
2493          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2494          * configure the PLL to port mapping here.
2495          */
2496         intel_ddi_enable_clock(encoder, crtc_state);
2497
2498         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2499         if (!intel_phy_is_tc(dev_priv, phy) ||
2500             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2501                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2502                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2503                                                                    dig_port->ddi_io_power_domain);
2504         }
2505
2506         /* 6. Program DP_MODE */
2507         icl_program_mg_dp_mode(dig_port, crtc_state);
2508
2509         /*
2510          * 7. The rest of the below are substeps under the bspec's "Enable and
2511          * Train Display Port" step.  Note that steps that are specific to
2512          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2513          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2514          * us when active_mst_links==0, so any steps designated for "single
2515          * stream or multi-stream master transcoder" can just be performed
2516          * unconditionally here.
2517          */
2518
2519         /*
2520          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2521          * Transcoder.
2522          */
2523         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2524
2525         /*
2526          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2527          * Transport Select
2528          */
2529         intel_ddi_config_transcoder_func(encoder, crtc_state);
2530
2531         /*
2532          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2533          * selected
2534          *
2535          * This will be handled by the intel_dp_start_link_train() farther
2536          * down this function.
2537          */
2538
2539         /* 7.e Configure voltage swing and related IO settings */
2540         tgl_ddi_vswing_sequence(encoder, crtc_state, level);
2541
2542         /*
2543          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2544          * the used lanes of the DDI.
2545          */
2546         intel_ddi_power_up_lanes(encoder, crtc_state);
2547
2548         /*
2549          * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2550          */
2551         intel_ddi_mso_configure(crtc_state);
2552
2553         /*
2554          * 7.g Configure and enable DDI_BUF_CTL
2555          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
2556          *     after 500 us.
2557          *
2558          * We only configure what the register value will be here.  Actual
2559          * enabling happens during link training farther down.
2560          */
2561         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2562
2563         if (!is_mst)
2564                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2565
2566         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2567         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2568         /*
2569          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2570          * in the FEC_CONFIGURATION register to 1 before initiating link
2571          * training
2572          */
2573         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2574
2575         intel_dp_check_frl_training(intel_dp);
2576         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2577
2578         /*
2579          * 7.i Follow DisplayPort specification training sequence (see notes for
2580          *     failure handling)
2581          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2582          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2583          *     (timeout after 800 us)
2584          */
2585         intel_dp_start_link_train(intel_dp, crtc_state);
2586
2587         /* 7.k Set DP_TP_CTL link training to Normal */
2588         if (!is_trans_port_sync_mode(crtc_state))
2589                 intel_dp_stop_link_train(intel_dp, crtc_state);
2590
2591         /* 7.l Configure and enable FEC if needed */
2592         intel_ddi_enable_fec(encoder, crtc_state);
2593         if (!crtc_state->bigjoiner)
2594                 intel_dsc_enable(encoder, crtc_state);
2595 }
2596
2597 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2598                                   struct intel_encoder *encoder,
2599                                   const struct intel_crtc_state *crtc_state,
2600                                   const struct drm_connector_state *conn_state)
2601 {
2602         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2603         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2604         enum port port = encoder->port;
2605         enum phy phy = intel_port_to_phy(dev_priv, port);
2606         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2607         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2608         int level = intel_ddi_dp_level(intel_dp, crtc_state);
2609
2610         if (DISPLAY_VER(dev_priv) < 11)
2611                 drm_WARN_ON(&dev_priv->drm,
2612                             is_mst && (port == PORT_A || port == PORT_E));
2613         else
2614                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2615
2616         intel_dp_set_link_params(intel_dp,
2617                                  crtc_state->port_clock,
2618                                  crtc_state->lane_count);
2619
2620         intel_pps_on(intel_dp);
2621
2622         intel_ddi_enable_clock(encoder, crtc_state);
2623
2624         if (!intel_phy_is_tc(dev_priv, phy) ||
2625             dig_port->tc_mode != TC_PORT_TBT_ALT) {
2626                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2627                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2628                                                                    dig_port->ddi_io_power_domain);
2629         }
2630
2631         icl_program_mg_dp_mode(dig_port, crtc_state);
2632
2633         if (DISPLAY_VER(dev_priv) >= 11)
2634                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
2635         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2636                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
2637         else
2638                 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2639
2640         intel_ddi_power_up_lanes(encoder, crtc_state);
2641
2642         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2643         if (!is_mst)
2644                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2645         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2646         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2647                                               true);
2648         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2649         intel_dp_start_link_train(intel_dp, crtc_state);
2650         if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2651             !is_trans_port_sync_mode(crtc_state))
2652                 intel_dp_stop_link_train(intel_dp, crtc_state);
2653
2654         intel_ddi_enable_fec(encoder, crtc_state);
2655
2656         if (!is_mst)
2657                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2658
2659         if (!crtc_state->bigjoiner)
2660                 intel_dsc_enable(encoder, crtc_state);
2661 }
2662
2663 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2664                                     struct intel_encoder *encoder,
2665                                     const struct intel_crtc_state *crtc_state,
2666                                     const struct drm_connector_state *conn_state)
2667 {
2668         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2669
2670         if (IS_DG2(dev_priv))
2671                 dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2672         else if (DISPLAY_VER(dev_priv) >= 12)
2673                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2674         else
2675                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2676
2677         /* MST will call a setting of MSA after an allocating of Virtual Channel
2678          * from MST encoder pre_enable callback.
2679          */
2680         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
2681                 intel_ddi_set_dp_msa(crtc_state, conn_state);
2682
2683                 intel_dp_set_m_n(crtc_state, M1_N1);
2684         }
2685 }
2686
2687 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2688                                       struct intel_encoder *encoder,
2689                                       const struct intel_crtc_state *crtc_state,
2690                                       const struct drm_connector_state *conn_state)
2691 {
2692         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2693         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2694         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2695
2696         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2697         intel_ddi_enable_clock(encoder, crtc_state);
2698
2699         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2700         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2701                                                            dig_port->ddi_io_power_domain);
2702
2703         icl_program_mg_dp_mode(dig_port, crtc_state);
2704
2705         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2706
2707         dig_port->set_infoframes(encoder,
2708                                  crtc_state->has_infoframe,
2709                                  crtc_state, conn_state);
2710 }
2711
2712 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2713                                  struct intel_encoder *encoder,
2714                                  const struct intel_crtc_state *crtc_state,
2715                                  const struct drm_connector_state *conn_state)
2716 {
2717         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2718         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2719         enum pipe pipe = crtc->pipe;
2720
2721         /*
2722          * When called from DP MST code:
2723          * - conn_state will be NULL
2724          * - encoder will be the main encoder (ie. mst->primary)
2725          * - the main connector associated with this port
2726          *   won't be active or linked to a crtc
2727          * - crtc_state will be the state of the first stream to
2728          *   be activated on this port, and it may not be the same
2729          *   stream that will be deactivated last, but each stream
2730          *   should have a state that is identical when it comes to
2731          *   the DP link parameteres
2732          */
2733
2734         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2735
2736         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2737
2738         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2739                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2740                                           conn_state);
2741         } else {
2742                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2743
2744                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2745                                         conn_state);
2746
2747                 /* FIXME precompute everything properly */
2748                 /* FIXME how do we turn infoframes off again? */
2749                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2750                         dig_port->set_infoframes(encoder,
2751                                                  crtc_state->has_infoframe,
2752                                                  crtc_state, conn_state);
2753         }
2754 }
2755
2756 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2757                                   const struct intel_crtc_state *crtc_state)
2758 {
2759         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2760         enum port port = encoder->port;
2761         bool wait = false;
2762         u32 val;
2763
2764         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2765         if (val & DDI_BUF_CTL_ENABLE) {
2766                 val &= ~DDI_BUF_CTL_ENABLE;
2767                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2768                 wait = true;
2769         }
2770
2771         if (intel_crtc_has_dp_encoder(crtc_state)) {
2772                 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2773                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2774                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2775                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2776         }
2777
2778         /* Disable FEC in DP Sink */
2779         intel_ddi_disable_fec_state(encoder, crtc_state);
2780
2781         if (wait)
2782                 intel_wait_ddi_buf_idle(dev_priv, port);
2783 }
2784
2785 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2786                                       struct intel_encoder *encoder,
2787                                       const struct intel_crtc_state *old_crtc_state,
2788                                       const struct drm_connector_state *old_conn_state)
2789 {
2790         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2791         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2792         struct intel_dp *intel_dp = &dig_port->dp;
2793         bool is_mst = intel_crtc_has_type(old_crtc_state,
2794                                           INTEL_OUTPUT_DP_MST);
2795         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2796
2797         if (!is_mst)
2798                 intel_dp_set_infoframes(encoder, false,
2799                                         old_crtc_state, old_conn_state);
2800
2801         /*
2802          * Power down sink before disabling the port, otherwise we end
2803          * up getting interrupts from the sink on detecting link loss.
2804          */
2805         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2806
2807         if (DISPLAY_VER(dev_priv) >= 12) {
2808                 if (is_mst) {
2809                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2810                         u32 val;
2811
2812                         val = intel_de_read(dev_priv,
2813                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
2814                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
2815                                  TRANS_DDI_MODE_SELECT_MASK);
2816                         intel_de_write(dev_priv,
2817                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
2818                                        val);
2819                 }
2820         } else {
2821                 if (!is_mst)
2822                         intel_ddi_disable_pipe_clock(old_crtc_state);
2823         }
2824
2825         intel_disable_ddi_buf(encoder, old_crtc_state);
2826
2827         /*
2828          * From TGL spec: "If single stream or multi-stream master transcoder:
2829          * Configure Transcoder Clock select to direct no clock to the
2830          * transcoder"
2831          */
2832         if (DISPLAY_VER(dev_priv) >= 12)
2833                 intel_ddi_disable_pipe_clock(old_crtc_state);
2834
2835         intel_pps_vdd_on(intel_dp);
2836         intel_pps_off(intel_dp);
2837
2838         if (!intel_phy_is_tc(dev_priv, phy) ||
2839             dig_port->tc_mode != TC_PORT_TBT_ALT)
2840                 intel_display_power_put(dev_priv,
2841                                         dig_port->ddi_io_power_domain,
2842                                         fetch_and_zero(&dig_port->ddi_io_wakeref));
2843
2844         intel_ddi_disable_clock(encoder);
2845 }
2846
2847 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2848                                         struct intel_encoder *encoder,
2849                                         const struct intel_crtc_state *old_crtc_state,
2850                                         const struct drm_connector_state *old_conn_state)
2851 {
2852         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2853         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2854         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2855
2856         dig_port->set_infoframes(encoder, false,
2857                                  old_crtc_state, old_conn_state);
2858
2859         intel_ddi_disable_pipe_clock(old_crtc_state);
2860
2861         intel_disable_ddi_buf(encoder, old_crtc_state);
2862
2863         intel_display_power_put(dev_priv,
2864                                 dig_port->ddi_io_power_domain,
2865                                 fetch_and_zero(&dig_port->ddi_io_wakeref));
2866
2867         intel_ddi_disable_clock(encoder);
2868
2869         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2870 }
2871
2872 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2873                                    struct intel_encoder *encoder,
2874                                    const struct intel_crtc_state *old_crtc_state,
2875                                    const struct drm_connector_state *old_conn_state)
2876 {
2877         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2878         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2879         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2880         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2881
2882         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2883                 intel_crtc_vblank_off(old_crtc_state);
2884
2885                 intel_disable_transcoder(old_crtc_state);
2886
2887                 intel_vrr_disable(old_crtc_state);
2888
2889                 intel_ddi_disable_transcoder_func(old_crtc_state);
2890
2891                 intel_dsc_disable(old_crtc_state);
2892
2893                 if (DISPLAY_VER(dev_priv) >= 9)
2894                         skl_scaler_disable(old_crtc_state);
2895                 else
2896                         ilk_pfit_disable(old_crtc_state);
2897         }
2898
2899         if (old_crtc_state->bigjoiner_linked_crtc) {
2900                 struct intel_atomic_state *state =
2901                         to_intel_atomic_state(old_crtc_state->uapi.state);
2902                 struct intel_crtc *slave =
2903                         old_crtc_state->bigjoiner_linked_crtc;
2904                 const struct intel_crtc_state *old_slave_crtc_state =
2905                         intel_atomic_get_old_crtc_state(state, slave);
2906
2907                 intel_crtc_vblank_off(old_slave_crtc_state);
2908
2909                 intel_dsc_disable(old_slave_crtc_state);
2910                 skl_scaler_disable(old_slave_crtc_state);
2911         }
2912
2913         /*
2914          * When called from DP MST code:
2915          * - old_conn_state will be NULL
2916          * - encoder will be the main encoder (ie. mst->primary)
2917          * - the main connector associated with this port
2918          *   won't be active or linked to a crtc
2919          * - old_crtc_state will be the state of the last stream to
2920          *   be deactivated on this port, and it may not be the same
2921          *   stream that was activated last, but each stream
2922          *   should have a state that is identical when it comes to
2923          *   the DP link parameteres
2924          */
2925
2926         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2927                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
2928                                             old_conn_state);
2929         else
2930                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
2931                                           old_conn_state);
2932
2933         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
2934                 intel_display_power_put(dev_priv,
2935                                         intel_ddi_main_link_aux_domain(dig_port),
2936                                         fetch_and_zero(&dig_port->aux_wakeref));
2937
2938         if (is_tc_port)
2939                 intel_tc_port_put_link(dig_port);
2940 }
2941
2942 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
2943                                 struct intel_encoder *encoder,
2944                                 const struct intel_crtc_state *old_crtc_state,
2945                                 const struct drm_connector_state *old_conn_state)
2946 {
2947         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2948         u32 val;
2949
2950         /*
2951          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2952          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2953          * step 13 is the correct place for it. Step 18 is where it was
2954          * originally before the BUN.
2955          */
2956         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2957         val &= ~FDI_RX_ENABLE;
2958         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2959
2960         intel_disable_ddi_buf(encoder, old_crtc_state);
2961         intel_ddi_disable_clock(encoder);
2962
2963         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
2964         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2965         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2966         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
2967
2968         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2969         val &= ~FDI_PCDCLK;
2970         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2971
2972         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
2973         val &= ~FDI_RX_PLL_ENABLE;
2974         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
2975 }
2976
2977 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
2978                                             struct intel_encoder *encoder,
2979                                             const struct intel_crtc_state *crtc_state)
2980 {
2981         const struct drm_connector_state *conn_state;
2982         struct drm_connector *conn;
2983         int i;
2984
2985         if (!crtc_state->sync_mode_slaves_mask)
2986                 return;
2987
2988         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2989                 struct intel_encoder *slave_encoder =
2990                         to_intel_encoder(conn_state->best_encoder);
2991                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
2992                 const struct intel_crtc_state *slave_crtc_state;
2993
2994                 if (!slave_crtc)
2995                         continue;
2996
2997                 slave_crtc_state =
2998                         intel_atomic_get_new_crtc_state(state, slave_crtc);
2999
3000                 if (slave_crtc_state->master_transcoder !=
3001                     crtc_state->cpu_transcoder)
3002                         continue;
3003
3004                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
3005                                          slave_crtc_state);
3006         }
3007
3008         usleep_range(200, 400);
3009
3010         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
3011                                  crtc_state);
3012 }
3013
3014 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3015                                 struct intel_encoder *encoder,
3016                                 const struct intel_crtc_state *crtc_state,
3017                                 const struct drm_connector_state *conn_state)
3018 {
3019         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3020         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3021         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3022         enum port port = encoder->port;
3023
3024         if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
3025                 intel_dp_stop_link_train(intel_dp, crtc_state);
3026
3027         intel_edp_backlight_on(crtc_state, conn_state);
3028         intel_psr_enable(intel_dp, crtc_state, conn_state);
3029
3030         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
3031                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3032
3033         intel_drrs_enable(intel_dp, crtc_state);
3034
3035         if (crtc_state->has_audio)
3036                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3037
3038         trans_port_sync_stop_link_train(state, encoder, crtc_state);
3039 }
3040
3041 static i915_reg_t
3042 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3043                                enum port port)
3044 {
3045         static const enum transcoder trans[] = {
3046                 [PORT_A] = TRANSCODER_EDP,
3047                 [PORT_B] = TRANSCODER_A,
3048                 [PORT_C] = TRANSCODER_B,
3049                 [PORT_D] = TRANSCODER_C,
3050                 [PORT_E] = TRANSCODER_A,
3051         };
3052
3053         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
3054
3055         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3056                 port = PORT_A;
3057
3058         return CHICKEN_TRANS(trans[port]);
3059 }
3060
3061 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3062                                   struct intel_encoder *encoder,
3063                                   const struct intel_crtc_state *crtc_state,
3064                                   const struct drm_connector_state *conn_state)
3065 {
3066         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3067         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3068         struct drm_connector *connector = conn_state->connector;
3069         int level = intel_ddi_hdmi_level(encoder, crtc_state);
3070         enum port port = encoder->port;
3071
3072         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3073                                                crtc_state->hdmi_high_tmds_clock_ratio,
3074                                                crtc_state->hdmi_scrambling))
3075                 drm_dbg_kms(&dev_priv->drm,
3076                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3077                             connector->base.id, connector->name);
3078
3079         if (IS_DG2(dev_priv))
3080                 intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
3081         else if (DISPLAY_VER(dev_priv) >= 12)
3082                 tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3083         else if (DISPLAY_VER(dev_priv) == 11)
3084                 icl_ddi_vswing_sequence(encoder, crtc_state, level);
3085         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3086                 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3087         else
3088                 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level);
3089
3090         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
3091                 skl_ddi_set_iboost(encoder, crtc_state, level);
3092
3093         /* Display WA #1143: skl,kbl,cfl */
3094         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
3095                 /*
3096                  * For some reason these chicken bits have been
3097                  * stuffed into a transcoder register, event though
3098                  * the bits affect a specific DDI port rather than
3099                  * a specific transcoder.
3100                  */
3101                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3102                 u32 val;
3103
3104                 val = intel_de_read(dev_priv, reg);
3105
3106                 if (port == PORT_E)
3107                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3108                                 DDIE_TRAINING_OVERRIDE_VALUE;
3109                 else
3110                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3111                                 DDI_TRAINING_OVERRIDE_VALUE;
3112
3113                 intel_de_write(dev_priv, reg, val);
3114                 intel_de_posting_read(dev_priv, reg);
3115
3116                 udelay(1);
3117
3118                 if (port == PORT_E)
3119                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3120                                  DDIE_TRAINING_OVERRIDE_VALUE);
3121                 else
3122                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3123                                  DDI_TRAINING_OVERRIDE_VALUE);
3124
3125                 intel_de_write(dev_priv, reg, val);
3126         }
3127
3128         intel_ddi_power_up_lanes(encoder, crtc_state);
3129
3130         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3131          * are ignored so nothing special needs to be done besides
3132          * enabling the port.
3133          *
3134          * On ADL_P the PHY link rate and lane count must be programmed but
3135          * these are both 0 for HDMI.
3136          */
3137         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3138                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3139
3140         if (crtc_state->has_audio)
3141                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3142 }
3143
3144 static void intel_enable_ddi(struct intel_atomic_state *state,
3145                              struct intel_encoder *encoder,
3146                              const struct intel_crtc_state *crtc_state,
3147                              const struct drm_connector_state *conn_state)
3148 {
3149         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3150
3151         if (!crtc_state->bigjoiner_slave)
3152                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3153
3154         intel_vrr_enable(encoder, crtc_state);
3155
3156         intel_enable_transcoder(crtc_state);
3157
3158         intel_crtc_vblank_on(crtc_state);
3159
3160         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3161                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3162         else
3163                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3164
3165         /* Enable hdcp if it's desired */
3166         if (conn_state->content_protection ==
3167             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3168                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3169                                   crtc_state,
3170                                   (u8)conn_state->hdcp_content_type);
3171 }
3172
3173 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3174                                  struct intel_encoder *encoder,
3175                                  const struct intel_crtc_state *old_crtc_state,
3176                                  const struct drm_connector_state *old_conn_state)
3177 {
3178         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3179
3180         intel_dp->link_trained = false;
3181
3182         intel_edp_backlight_off(old_conn_state);
3183         /* Disable the decompression in DP Sink */
3184         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3185                                               false);
3186         /* Disable Ignore_MSA bit in DP Sink */
3187         intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
3188                                                       false);
3189 }
3190
3191 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3192                                    struct intel_encoder *encoder,
3193                                    const struct intel_crtc_state *old_crtc_state,
3194                                    const struct drm_connector_state *old_conn_state)
3195 {
3196         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3197         struct drm_connector *connector = old_conn_state->connector;
3198
3199         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3200                                                false, false))
3201                 drm_dbg_kms(&i915->drm,
3202                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3203                             connector->base.id, connector->name);
3204 }
3205
3206 static void intel_pre_disable_ddi(struct intel_atomic_state *state,
3207                                   struct intel_encoder *encoder,
3208                                   const struct intel_crtc_state *old_crtc_state,
3209                                   const struct drm_connector_state *old_conn_state)
3210 {
3211         struct intel_dp *intel_dp;
3212
3213         if (old_crtc_state->has_audio)
3214                 intel_audio_codec_disable(encoder, old_crtc_state,
3215                                           old_conn_state);
3216
3217         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3218                 return;
3219
3220         intel_dp = enc_to_intel_dp(encoder);
3221         intel_drrs_disable(intel_dp, old_crtc_state);
3222         intel_psr_disable(intel_dp, old_crtc_state);
3223 }
3224
3225 static void intel_disable_ddi(struct intel_atomic_state *state,
3226                               struct intel_encoder *encoder,
3227                               const struct intel_crtc_state *old_crtc_state,
3228                               const struct drm_connector_state *old_conn_state)
3229 {
3230         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3231
3232         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3233                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3234                                        old_conn_state);
3235         else
3236                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3237                                      old_conn_state);
3238 }
3239
3240 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3241                                      struct intel_encoder *encoder,
3242                                      const struct intel_crtc_state *crtc_state,
3243                                      const struct drm_connector_state *conn_state)
3244 {
3245         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3246
3247         intel_ddi_set_dp_msa(crtc_state, conn_state);
3248
3249         intel_psr_update(intel_dp, crtc_state, conn_state);
3250         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3251         intel_drrs_update(intel_dp, crtc_state);
3252
3253         intel_backlight_update(state, encoder, crtc_state, conn_state);
3254 }
3255
3256 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3257                            struct intel_encoder *encoder,
3258                            const struct intel_crtc_state *crtc_state,
3259                            const struct drm_connector_state *conn_state)
3260 {
3261
3262         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3263             !intel_encoder_is_mst(encoder))
3264                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3265                                          conn_state);
3266
3267         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3268 }
3269
3270 static void
3271 intel_ddi_update_prepare(struct intel_atomic_state *state,
3272                          struct intel_encoder *encoder,
3273                          struct intel_crtc *crtc)
3274 {
3275         struct intel_crtc_state *crtc_state =
3276                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3277         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3278
3279         drm_WARN_ON(state->base.dev, crtc && crtc->active);
3280
3281         intel_tc_port_get_link(enc_to_dig_port(encoder),
3282                                required_lanes);
3283         if (crtc_state && crtc_state->hw.active)
3284                 intel_update_active_dpll(state, crtc, encoder);
3285 }
3286
3287 static void
3288 intel_ddi_update_complete(struct intel_atomic_state *state,
3289                           struct intel_encoder *encoder,
3290                           struct intel_crtc *crtc)
3291 {
3292         intel_tc_port_put_link(enc_to_dig_port(encoder));
3293 }
3294
3295 static void
3296 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3297                          struct intel_encoder *encoder,
3298                          const struct intel_crtc_state *crtc_state,
3299                          const struct drm_connector_state *conn_state)
3300 {
3301         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3302         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3303         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3304         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3305
3306         if (is_tc_port)
3307                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3308
3309         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
3310                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
3311                 dig_port->aux_wakeref =
3312                         intel_display_power_get(dev_priv,
3313                                                 intel_ddi_main_link_aux_domain(dig_port));
3314         }
3315
3316         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
3317                 /*
3318                  * Program the lane count for static/dynamic connections on
3319                  * Type-C ports.  Skip this step for TBT.
3320                  */
3321                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3322         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3323                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3324                                                 crtc_state->lane_lat_optim_mask);
3325 }
3326
3327 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3328                                            const struct intel_crtc_state *crtc_state)
3329 {
3330         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3331         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3332         enum port port = encoder->port;
3333         u32 dp_tp_ctl, ddi_buf_ctl;
3334         bool wait = false;
3335
3336         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3337
3338         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3339                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3340                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3341                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3342                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3343                         wait = true;
3344                 }
3345
3346                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3347                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3348                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3349                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3350
3351                 if (wait)
3352                         intel_wait_ddi_buf_idle(dev_priv, port);
3353         }
3354
3355         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3356         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3357                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3358         } else {
3359                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3360                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3361                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3362         }
3363         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3364         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3365
3366         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3367         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3368         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3369
3370         intel_wait_ddi_buf_active(dev_priv, port);
3371 }
3372
3373 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3374                                      const struct intel_crtc_state *crtc_state,
3375                                      u8 dp_train_pat)
3376 {
3377         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3378         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3379         u32 temp;
3380
3381         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3382
3383         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3384         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3385         case DP_TRAINING_PATTERN_DISABLE:
3386                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3387                 break;
3388         case DP_TRAINING_PATTERN_1:
3389                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3390                 break;
3391         case DP_TRAINING_PATTERN_2:
3392                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3393                 break;
3394         case DP_TRAINING_PATTERN_3:
3395                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3396                 break;
3397         case DP_TRAINING_PATTERN_4:
3398                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3399                 break;
3400         }
3401
3402         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3403 }
3404
3405 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3406                                           const struct intel_crtc_state *crtc_state)
3407 {
3408         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3409         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3410         enum port port = encoder->port;
3411         u32 val;
3412
3413         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3414         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3415         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3416         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3417
3418         /*
3419          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3420          * reason we need to set idle transmission mode is to work around a HW
3421          * issue where we enable the pipe while not in idle link-training mode.
3422          * In this case there is requirement to wait for a minimum number of
3423          * idle patterns to be sent.
3424          */
3425         if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3426                 return;
3427
3428         if (intel_de_wait_for_set(dev_priv,
3429                                   dp_tp_status_reg(encoder, crtc_state),
3430                                   DP_TP_STATUS_IDLE_DONE, 1))
3431                 drm_err(&dev_priv->drm,
3432                         "Timed out waiting for DP idle patterns\n");
3433 }
3434
3435 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3436                                        enum transcoder cpu_transcoder)
3437 {
3438         if (cpu_transcoder == TRANSCODER_EDP)
3439                 return false;
3440
3441         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3442                 return false;
3443
3444         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3445                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3446 }
3447
3448 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3449                                          struct intel_crtc_state *crtc_state)
3450 {
3451         if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3452                 crtc_state->min_voltage_level = 2;
3453         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3454                 crtc_state->min_voltage_level = 3;
3455         else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3456                 crtc_state->min_voltage_level = 1;
3457 }
3458
3459 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3460                                                      enum transcoder cpu_transcoder)
3461 {
3462         u32 master_select;
3463
3464         if (DISPLAY_VER(dev_priv) >= 11) {
3465                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3466
3467                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3468                         return INVALID_TRANSCODER;
3469
3470                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3471         } else {
3472                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3473
3474                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3475                         return INVALID_TRANSCODER;
3476
3477                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3478         }
3479
3480         if (master_select == 0)
3481                 return TRANSCODER_EDP;
3482         else
3483                 return master_select - 1;
3484 }
3485
3486 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3487 {
3488         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3489         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3490                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3491         enum transcoder cpu_transcoder;
3492
3493         crtc_state->master_transcoder =
3494                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3495
3496         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3497                 enum intel_display_power_domain power_domain;
3498                 intel_wakeref_t trans_wakeref;
3499
3500                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3501                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3502                                                                    power_domain);
3503
3504                 if (!trans_wakeref)
3505                         continue;
3506
3507                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3508                     crtc_state->cpu_transcoder)
3509                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3510
3511                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3512         }
3513
3514         drm_WARN_ON(&dev_priv->drm,
3515                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
3516                     crtc_state->sync_mode_slaves_mask);
3517 }
3518
3519 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3520                                     struct intel_crtc_state *pipe_config)
3521 {
3522         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3523         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3524         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3525         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3526         u32 temp, flags = 0;
3527
3528         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3529         if (temp & TRANS_DDI_PHSYNC)
3530                 flags |= DRM_MODE_FLAG_PHSYNC;
3531         else
3532                 flags |= DRM_MODE_FLAG_NHSYNC;
3533         if (temp & TRANS_DDI_PVSYNC)
3534                 flags |= DRM_MODE_FLAG_PVSYNC;
3535         else
3536                 flags |= DRM_MODE_FLAG_NVSYNC;
3537
3538         pipe_config->hw.adjusted_mode.flags |= flags;
3539
3540         switch (temp & TRANS_DDI_BPC_MASK) {
3541         case TRANS_DDI_BPC_6:
3542                 pipe_config->pipe_bpp = 18;
3543                 break;
3544         case TRANS_DDI_BPC_8:
3545                 pipe_config->pipe_bpp = 24;
3546                 break;
3547         case TRANS_DDI_BPC_10:
3548                 pipe_config->pipe_bpp = 30;
3549                 break;
3550         case TRANS_DDI_BPC_12:
3551                 pipe_config->pipe_bpp = 36;
3552                 break;
3553         default:
3554                 break;
3555         }
3556
3557         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3558         case TRANS_DDI_MODE_SELECT_HDMI:
3559                 pipe_config->has_hdmi_sink = true;
3560
3561                 pipe_config->infoframes.enable |=
3562                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3563
3564                 if (pipe_config->infoframes.enable)
3565                         pipe_config->has_infoframe = true;
3566
3567                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3568                         pipe_config->hdmi_scrambling = true;
3569                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3570                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3571                 fallthrough;
3572         case TRANS_DDI_MODE_SELECT_DVI:
3573                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3574                 pipe_config->lane_count = 4;
3575                 break;
3576         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
3577                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3578                 break;
3579         case TRANS_DDI_MODE_SELECT_DP_SST:
3580                 if (encoder->type == INTEL_OUTPUT_EDP)
3581                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3582                 else
3583                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3584                 pipe_config->lane_count =
3585                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3586                 intel_dp_get_m_n(crtc, pipe_config);
3587
3588                 if (DISPLAY_VER(dev_priv) >= 11) {
3589                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3590
3591                         pipe_config->fec_enable =
3592                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3593
3594                         drm_dbg_kms(&dev_priv->drm,
3595                                     "[ENCODER:%d:%s] Fec status: %u\n",
3596                                     encoder->base.base.id, encoder->base.name,
3597                                     pipe_config->fec_enable);
3598                 }
3599
3600                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3601                         pipe_config->infoframes.enable |=
3602                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3603                 else
3604                         pipe_config->infoframes.enable |=
3605                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3606                 break;
3607         case TRANS_DDI_MODE_SELECT_DP_MST:
3608                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3609                 pipe_config->lane_count =
3610                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3611
3612                 if (DISPLAY_VER(dev_priv) >= 12)
3613                         pipe_config->mst_master_transcoder =
3614                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3615
3616                 intel_dp_get_m_n(crtc, pipe_config);
3617
3618                 pipe_config->infoframes.enable |=
3619                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3620                 break;
3621         default:
3622                 break;
3623         }
3624 }
3625
3626 static void intel_ddi_get_config(struct intel_encoder *encoder,
3627                                  struct intel_crtc_state *pipe_config)
3628 {
3629         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3630         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3631
3632         /* XXX: DSI transcoder paranoia */
3633         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3634                 return;
3635
3636         if (pipe_config->bigjoiner_slave) {
3637                 /* read out pipe settings from master */
3638                 enum transcoder save = pipe_config->cpu_transcoder;
3639
3640                 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
3641                 WARN_ON(pipe_config->output_types);
3642                 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
3643                 intel_ddi_read_func_ctl(encoder, pipe_config);
3644                 pipe_config->cpu_transcoder = save;
3645         } else {
3646                 intel_ddi_read_func_ctl(encoder, pipe_config);
3647         }
3648
3649         intel_ddi_mso_get_config(encoder, pipe_config);
3650
3651         pipe_config->has_audio =
3652                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3653
3654         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3655             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3656                 /*
3657                  * This is a big fat ugly hack.
3658                  *
3659                  * Some machines in UEFI boot mode provide us a VBT that has 18
3660                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3661                  * unknown we fail to light up. Yet the same BIOS boots up with
3662                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3663                  * max, not what it tells us to use.
3664                  *
3665                  * Note: This will still be broken if the eDP panel is not lit
3666                  * up by the BIOS, and thus we can't get the mode at module
3667                  * load.
3668                  */
3669                 drm_dbg_kms(&dev_priv->drm,
3670                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3671                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3672                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3673         }
3674
3675         if (!pipe_config->bigjoiner_slave)
3676                 ddi_dotclock_get(pipe_config);
3677
3678         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3679                 pipe_config->lane_lat_optim_mask =
3680                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3681
3682         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3683
3684         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3685
3686         intel_read_infoframe(encoder, pipe_config,
3687                              HDMI_INFOFRAME_TYPE_AVI,
3688                              &pipe_config->infoframes.avi);
3689         intel_read_infoframe(encoder, pipe_config,
3690                              HDMI_INFOFRAME_TYPE_SPD,
3691                              &pipe_config->infoframes.spd);
3692         intel_read_infoframe(encoder, pipe_config,
3693                              HDMI_INFOFRAME_TYPE_VENDOR,
3694                              &pipe_config->infoframes.hdmi);
3695         intel_read_infoframe(encoder, pipe_config,
3696                              HDMI_INFOFRAME_TYPE_DRM,
3697                              &pipe_config->infoframes.drm);
3698
3699         if (DISPLAY_VER(dev_priv) >= 8)
3700                 bdw_get_trans_port_sync_config(pipe_config);
3701
3702         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3703         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3704
3705         intel_psr_get_config(encoder, pipe_config);
3706 }
3707
3708 void intel_ddi_get_clock(struct intel_encoder *encoder,
3709                          struct intel_crtc_state *crtc_state,
3710                          struct intel_shared_dpll *pll)
3711 {
3712         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3713         enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3714         struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3715         bool pll_active;
3716
3717         if (drm_WARN_ON(&i915->drm, !pll))
3718                 return;
3719
3720         port_dpll->pll = pll;
3721         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3722         drm_WARN_ON(&i915->drm, !pll_active);
3723
3724         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3725
3726         crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3727                                                      &crtc_state->dpll_hw_state);
3728 }
3729
3730 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3731                                 struct intel_crtc_state *crtc_state)
3732 {
3733         intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3734         crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3735
3736         intel_ddi_get_config(encoder, crtc_state);
3737 }
3738
3739 static void adls_ddi_get_config(struct intel_encoder *encoder,
3740                                 struct intel_crtc_state *crtc_state)
3741 {
3742         intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3743         intel_ddi_get_config(encoder, crtc_state);
3744 }
3745
3746 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3747                                struct intel_crtc_state *crtc_state)
3748 {
3749         intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3750         intel_ddi_get_config(encoder, crtc_state);
3751 }
3752
3753 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3754                                struct intel_crtc_state *crtc_state)
3755 {
3756         intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3757         intel_ddi_get_config(encoder, crtc_state);
3758 }
3759
3760 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3761                                      struct intel_crtc_state *crtc_state)
3762 {
3763         intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3764         intel_ddi_get_config(encoder, crtc_state);
3765 }
3766
3767 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3768                                  struct intel_crtc_state *crtc_state,
3769                                  struct intel_shared_dpll *pll)
3770 {
3771         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3772         enum icl_port_dpll_id port_dpll_id;
3773         struct icl_port_dpll *port_dpll;
3774         bool pll_active;
3775
3776         if (drm_WARN_ON(&i915->drm, !pll))
3777                 return;
3778
3779         if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
3780                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3781         else
3782                 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3783
3784         port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3785
3786         port_dpll->pll = pll;
3787         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3788         drm_WARN_ON(&i915->drm, !pll_active);
3789
3790         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3791
3792         if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
3793                 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3794         else
3795                 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3796                                                              &crtc_state->dpll_hw_state);
3797 }
3798
3799 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3800                                   struct intel_crtc_state *crtc_state)
3801 {
3802         icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3803         intel_ddi_get_config(encoder, crtc_state);
3804 }
3805
3806 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3807                                struct intel_crtc_state *crtc_state)
3808 {
3809         intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3810         intel_ddi_get_config(encoder, crtc_state);
3811 }
3812
3813 static void skl_ddi_get_config(struct intel_encoder *encoder,
3814                                struct intel_crtc_state *crtc_state)
3815 {
3816         intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3817         intel_ddi_get_config(encoder, crtc_state);
3818 }
3819
3820 void hsw_ddi_get_config(struct intel_encoder *encoder,
3821                         struct intel_crtc_state *crtc_state)
3822 {
3823         intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3824         intel_ddi_get_config(encoder, crtc_state);
3825 }
3826
3827 static void intel_ddi_sync_state(struct intel_encoder *encoder,
3828                                  const struct intel_crtc_state *crtc_state)
3829 {
3830         if (intel_crtc_has_dp_encoder(crtc_state))
3831                 intel_dp_sync_state(encoder, crtc_state);
3832 }
3833
3834 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3835                                             struct intel_crtc_state *crtc_state)
3836 {
3837         if (intel_crtc_has_dp_encoder(crtc_state))
3838                 return intel_dp_initial_fastset_check(encoder, crtc_state);
3839
3840         return true;
3841 }
3842
3843 static enum intel_output_type
3844 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3845                               struct intel_crtc_state *crtc_state,
3846                               struct drm_connector_state *conn_state)
3847 {
3848         switch (conn_state->connector->connector_type) {
3849         case DRM_MODE_CONNECTOR_HDMIA:
3850                 return INTEL_OUTPUT_HDMI;
3851         case DRM_MODE_CONNECTOR_eDP:
3852                 return INTEL_OUTPUT_EDP;
3853         case DRM_MODE_CONNECTOR_DisplayPort:
3854                 return INTEL_OUTPUT_DP;
3855         default:
3856                 MISSING_CASE(conn_state->connector->connector_type);
3857                 return INTEL_OUTPUT_UNUSED;
3858         }
3859 }
3860
3861 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3862                                     struct intel_crtc_state *pipe_config,
3863                                     struct drm_connector_state *conn_state)
3864 {
3865         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3866         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3867         enum port port = encoder->port;
3868         int ret;
3869
3870         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3871                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3872
3873         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
3874                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3875         } else {
3876                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3877         }
3878
3879         if (ret)
3880                 return ret;
3881
3882         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3883             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3884                 pipe_config->pch_pfit.force_thru =
3885                         pipe_config->pch_pfit.enabled ||
3886                         pipe_config->crc_enabled;
3887
3888         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3889                 pipe_config->lane_lat_optim_mask =
3890                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3891
3892         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3893
3894         return 0;
3895 }
3896
3897 static bool mode_equal(const struct drm_display_mode *mode1,
3898                        const struct drm_display_mode *mode2)
3899 {
3900         return drm_mode_match(mode1, mode2,
3901                               DRM_MODE_MATCH_TIMINGS |
3902                               DRM_MODE_MATCH_FLAGS |
3903                               DRM_MODE_MATCH_3D_FLAGS) &&
3904                 mode1->clock == mode2->clock; /* we want an exact match */
3905 }
3906
3907 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3908                       const struct intel_link_m_n *m_n_2)
3909 {
3910         return m_n_1->tu == m_n_2->tu &&
3911                 m_n_1->gmch_m == m_n_2->gmch_m &&
3912                 m_n_1->gmch_n == m_n_2->gmch_n &&
3913                 m_n_1->link_m == m_n_2->link_m &&
3914                 m_n_1->link_n == m_n_2->link_n;
3915 }
3916
3917 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3918                                        const struct intel_crtc_state *crtc_state2)
3919 {
3920         return crtc_state1->hw.active && crtc_state2->hw.active &&
3921                 crtc_state1->output_types == crtc_state2->output_types &&
3922                 crtc_state1->output_format == crtc_state2->output_format &&
3923                 crtc_state1->lane_count == crtc_state2->lane_count &&
3924                 crtc_state1->port_clock == crtc_state2->port_clock &&
3925                 mode_equal(&crtc_state1->hw.adjusted_mode,
3926                            &crtc_state2->hw.adjusted_mode) &&
3927                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
3928 }
3929
3930 static u8
3931 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
3932                                 int tile_group_id)
3933 {
3934         struct drm_connector *connector;
3935         const struct drm_connector_state *conn_state;
3936         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
3937         struct intel_atomic_state *state =
3938                 to_intel_atomic_state(ref_crtc_state->uapi.state);
3939         u8 transcoders = 0;
3940         int i;
3941
3942         /*
3943          * We don't enable port sync on BDW due to missing w/as and
3944          * due to not having adjusted the modeset sequence appropriately.
3945          */
3946         if (DISPLAY_VER(dev_priv) < 9)
3947                 return 0;
3948
3949         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
3950                 return 0;
3951
3952         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
3953                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
3954                 const struct intel_crtc_state *crtc_state;
3955
3956                 if (!crtc)
3957                         continue;
3958
3959                 if (!connector->has_tile ||
3960                     connector->tile_group->id !=
3961                     tile_group_id)
3962                         continue;
3963                 crtc_state = intel_atomic_get_new_crtc_state(state,
3964                                                              crtc);
3965                 if (!crtcs_port_sync_compatible(ref_crtc_state,
3966                                                 crtc_state))
3967                         continue;
3968                 transcoders |= BIT(crtc_state->cpu_transcoder);
3969         }
3970
3971         return transcoders;
3972 }
3973
3974 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
3975                                          struct intel_crtc_state *crtc_state,
3976                                          struct drm_connector_state *conn_state)
3977 {
3978         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3979         struct drm_connector *connector = conn_state->connector;
3980         u8 port_sync_transcoders = 0;
3981
3982         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
3983                     encoder->base.base.id, encoder->base.name,
3984                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
3985
3986         if (connector->has_tile)
3987                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
3988                                                                         connector->tile_group->id);
3989
3990         /*
3991          * EDP Transcoders cannot be ensalved
3992          * make them a master always when present
3993          */
3994         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
3995                 crtc_state->master_transcoder = TRANSCODER_EDP;
3996         else
3997                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
3998
3999         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4000                 crtc_state->master_transcoder = INVALID_TRANSCODER;
4001                 crtc_state->sync_mode_slaves_mask =
4002                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4003         }
4004
4005         return 0;
4006 }
4007
4008 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4009 {
4010         struct drm_i915_private *i915 = to_i915(encoder->dev);
4011         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4012
4013         intel_dp_encoder_flush_work(encoder);
4014         intel_display_power_flush_work(i915);
4015
4016         drm_encoder_cleanup(encoder);
4017         if (dig_port)
4018                 kfree(dig_port->hdcp_port_data.streams);
4019         kfree(dig_port);
4020 }
4021
4022 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4023 {
4024         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4025
4026         intel_dp->reset_link_params = true;
4027
4028         intel_pps_encoder_reset(intel_dp);
4029 }
4030
4031 static const struct drm_encoder_funcs intel_ddi_funcs = {
4032         .reset = intel_ddi_encoder_reset,
4033         .destroy = intel_ddi_encoder_destroy,
4034 };
4035
4036 static struct intel_connector *
4037 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4038 {
4039         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4040         struct intel_connector *connector;
4041         enum port port = dig_port->base.port;
4042
4043         connector = intel_connector_alloc();
4044         if (!connector)
4045                 return NULL;
4046
4047         dig_port->dp.output_reg = DDI_BUF_CTL(port);
4048         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4049         dig_port->dp.set_link_train = intel_ddi_set_link_train;
4050         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4051
4052         if (IS_DG2(dev_priv))
4053                 dig_port->dp.set_signal_levels = dg2_set_signal_levels;
4054         else if (DISPLAY_VER(dev_priv) >= 12)
4055                 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4056         else if (DISPLAY_VER(dev_priv) >= 11)
4057                 dig_port->dp.set_signal_levels = icl_set_signal_levels;
4058         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4059                 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4060         else
4061                 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4062
4063         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4064         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4065
4066         if (!intel_dp_init_connector(dig_port, connector)) {
4067                 kfree(connector);
4068                 return NULL;
4069         }
4070
4071         return connector;
4072 }
4073
4074 static int modeset_pipe(struct drm_crtc *crtc,
4075                         struct drm_modeset_acquire_ctx *ctx)
4076 {
4077         struct drm_atomic_state *state;
4078         struct drm_crtc_state *crtc_state;
4079         int ret;
4080
4081         state = drm_atomic_state_alloc(crtc->dev);
4082         if (!state)
4083                 return -ENOMEM;
4084
4085         state->acquire_ctx = ctx;
4086
4087         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4088         if (IS_ERR(crtc_state)) {
4089                 ret = PTR_ERR(crtc_state);
4090                 goto out;
4091         }
4092
4093         crtc_state->connectors_changed = true;
4094
4095         ret = drm_atomic_commit(state);
4096 out:
4097         drm_atomic_state_put(state);
4098
4099         return ret;
4100 }
4101
4102 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4103                                  struct drm_modeset_acquire_ctx *ctx)
4104 {
4105         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4106         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4107         struct intel_connector *connector = hdmi->attached_connector;
4108         struct i2c_adapter *adapter =
4109                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4110         struct drm_connector_state *conn_state;
4111         struct intel_crtc_state *crtc_state;
4112         struct intel_crtc *crtc;
4113         u8 config;
4114         int ret;
4115
4116         if (!connector || connector->base.status != connector_status_connected)
4117                 return 0;
4118
4119         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4120                                ctx);
4121         if (ret)
4122                 return ret;
4123
4124         conn_state = connector->base.state;
4125
4126         crtc = to_intel_crtc(conn_state->crtc);
4127         if (!crtc)
4128                 return 0;
4129
4130         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4131         if (ret)
4132                 return ret;
4133
4134         crtc_state = to_intel_crtc_state(crtc->base.state);
4135
4136         drm_WARN_ON(&dev_priv->drm,
4137                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4138
4139         if (!crtc_state->hw.active)
4140                 return 0;
4141
4142         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4143             !crtc_state->hdmi_scrambling)
4144                 return 0;
4145
4146         if (conn_state->commit &&
4147             !try_wait_for_completion(&conn_state->commit->hw_done))
4148                 return 0;
4149
4150         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4151         if (ret < 0) {
4152                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4153                         ret);
4154                 return 0;
4155         }
4156
4157         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4158             crtc_state->hdmi_high_tmds_clock_ratio &&
4159             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4160             crtc_state->hdmi_scrambling)
4161                 return 0;
4162
4163         /*
4164          * HDMI 2.0 says that one should not send scrambled data
4165          * prior to configuring the sink scrambling, and that
4166          * TMDS clock/data transmission should be suspended when
4167          * changing the TMDS clock rate in the sink. So let's
4168          * just do a full modeset here, even though some sinks
4169          * would be perfectly happy if were to just reconfigure
4170          * the SCDC settings on the fly.
4171          */
4172         return modeset_pipe(&crtc->base, ctx);
4173 }
4174
4175 static enum intel_hotplug_state
4176 intel_ddi_hotplug(struct intel_encoder *encoder,
4177                   struct intel_connector *connector)
4178 {
4179         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4180         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4181         struct intel_dp *intel_dp = &dig_port->dp;
4182         enum phy phy = intel_port_to_phy(i915, encoder->port);
4183         bool is_tc = intel_phy_is_tc(i915, phy);
4184         struct drm_modeset_acquire_ctx ctx;
4185         enum intel_hotplug_state state;
4186         int ret;
4187
4188         if (intel_dp->compliance.test_active &&
4189             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
4190                 intel_dp_phy_test(encoder);
4191                 /* just do the PHY test and nothing else */
4192                 return INTEL_HOTPLUG_UNCHANGED;
4193         }
4194
4195         state = intel_encoder_hotplug(encoder, connector);
4196
4197         drm_modeset_acquire_init(&ctx, 0);
4198
4199         for (;;) {
4200                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4201                         ret = intel_hdmi_reset_link(encoder, &ctx);
4202                 else
4203                         ret = intel_dp_retrain_link(encoder, &ctx);
4204
4205                 if (ret == -EDEADLK) {
4206                         drm_modeset_backoff(&ctx);
4207                         continue;
4208                 }
4209
4210                 break;
4211         }
4212
4213         drm_modeset_drop_locks(&ctx);
4214         drm_modeset_acquire_fini(&ctx);
4215         drm_WARN(encoder->base.dev, ret,
4216                  "Acquiring modeset locks failed with %i\n", ret);
4217
4218         /*
4219          * Unpowered type-c dongles can take some time to boot and be
4220          * responsible, so here giving some time to those dongles to power up
4221          * and then retrying the probe.
4222          *
4223          * On many platforms the HDMI live state signal is known to be
4224          * unreliable, so we can't use it to detect if a sink is connected or
4225          * not. Instead we detect if it's connected based on whether we can
4226          * read the EDID or not. That in turn has a problem during disconnect,
4227          * since the HPD interrupt may be raised before the DDC lines get
4228          * disconnected (due to how the required length of DDC vs. HPD
4229          * connector pins are specified) and so we'll still be able to get a
4230          * valid EDID. To solve this schedule another detection cycle if this
4231          * time around we didn't detect any change in the sink's connection
4232          * status.
4233          *
4234          * Type-c connectors which get their HPD signal deasserted then
4235          * reasserted, without unplugging/replugging the sink from the
4236          * connector, introduce a delay until the AUX channel communication
4237          * becomes functional. Retry the detection for 5 seconds on type-c
4238          * connectors to account for this delay.
4239          */
4240         if (state == INTEL_HOTPLUG_UNCHANGED &&
4241             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4242             !dig_port->dp.is_mst)
4243                 state = INTEL_HOTPLUG_RETRY;
4244
4245         return state;
4246 }
4247
4248 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4249 {
4250         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4251         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4252
4253         return intel_de_read(dev_priv, SDEISR) & bit;
4254 }
4255
4256 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4257 {
4258         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4259         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4260
4261         return intel_de_read(dev_priv, DEISR) & bit;
4262 }
4263
4264 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4265 {
4266         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4267         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4268
4269         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4270 }
4271
4272 static struct intel_connector *
4273 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4274 {
4275         struct intel_connector *connector;
4276         enum port port = dig_port->base.port;
4277
4278         connector = intel_connector_alloc();
4279         if (!connector)
4280                 return NULL;
4281
4282         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4283         intel_hdmi_init_connector(dig_port, connector);
4284
4285         return connector;
4286 }
4287
4288 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4289 {
4290         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4291
4292         if (dig_port->base.port != PORT_A)
4293                 return false;
4294
4295         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4296                 return false;
4297
4298         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4299          *                     supported configuration
4300          */
4301         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4302                 return true;
4303
4304         return false;
4305 }
4306
4307 static int
4308 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4309 {
4310         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4311         enum port port = dig_port->base.port;
4312         int max_lanes = 4;
4313
4314         if (DISPLAY_VER(dev_priv) >= 11)
4315                 return max_lanes;
4316
4317         if (port == PORT_A || port == PORT_E) {
4318                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4319                         max_lanes = port == PORT_A ? 4 : 0;
4320                 else
4321                         /* Both A and E share 2 lanes */
4322                         max_lanes = 2;
4323         }
4324
4325         /*
4326          * Some BIOS might fail to set this bit on port A if eDP
4327          * wasn't lit up at boot.  Force this bit set when needed
4328          * so we use the proper lane count for our calculations.
4329          */
4330         if (intel_ddi_a_force_4_lanes(dig_port)) {
4331                 drm_dbg_kms(&dev_priv->drm,
4332                             "Forcing DDI_A_4_LANES for port A\n");
4333                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4334                 max_lanes = 4;
4335         }
4336
4337         return max_lanes;
4338 }
4339
4340 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4341 {
4342         return i915->hti_state & HDPORT_ENABLED &&
4343                i915->hti_state & HDPORT_DDI_USED(phy);
4344 }
4345
4346 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4347                                   enum port port)
4348 {
4349         if (port >= PORT_D_XELPD)
4350                 return HPD_PORT_D + port - PORT_D_XELPD;
4351         else if (port >= PORT_TC1)
4352                 return HPD_PORT_TC1 + port - PORT_TC1;
4353         else
4354                 return HPD_PORT_A + port - PORT_A;
4355 }
4356
4357 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4358                                 enum port port)
4359 {
4360         if (port >= PORT_TC1)
4361                 return HPD_PORT_C + port - PORT_TC1;
4362         else
4363                 return HPD_PORT_A + port - PORT_A;
4364 }
4365
4366 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4367                                 enum port port)
4368 {
4369         if (port >= PORT_TC1)
4370                 return HPD_PORT_TC1 + port - PORT_TC1;
4371         else
4372                 return HPD_PORT_A + port - PORT_A;
4373 }
4374
4375 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4376                                 enum port port)
4377 {
4378         if (HAS_PCH_TGP(dev_priv))
4379                 return tgl_hpd_pin(dev_priv, port);
4380
4381         if (port >= PORT_TC1)
4382                 return HPD_PORT_C + port - PORT_TC1;
4383         else
4384                 return HPD_PORT_A + port - PORT_A;
4385 }
4386
4387 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4388                                 enum port port)
4389 {
4390         if (port >= PORT_C)
4391                 return HPD_PORT_TC1 + port - PORT_C;
4392         else
4393                 return HPD_PORT_A + port - PORT_A;
4394 }
4395
4396 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4397                                 enum port port)
4398 {
4399         if (port == PORT_D)
4400                 return HPD_PORT_A;
4401
4402         if (HAS_PCH_MCC(dev_priv))
4403                 return icl_hpd_pin(dev_priv, port);
4404
4405         return HPD_PORT_A + port - PORT_A;
4406 }
4407
4408 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4409 {
4410         if (HAS_PCH_TGP(dev_priv))
4411                 return icl_hpd_pin(dev_priv, port);
4412
4413         return HPD_PORT_A + port - PORT_A;
4414 }
4415
4416 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4417 {
4418         if (DISPLAY_VER(i915) >= 12)
4419                 return port >= PORT_TC1;
4420         else if (DISPLAY_VER(i915) >= 11)
4421                 return port >= PORT_C;
4422         else
4423                 return false;
4424 }
4425
4426 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4427 {
4428         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4429         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4430         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4431         enum phy phy = intel_port_to_phy(i915, encoder->port);
4432
4433         intel_dp_encoder_suspend(encoder);
4434
4435         if (!intel_phy_is_tc(i915, phy))
4436                 return;
4437
4438         intel_tc_port_disconnect_phy(dig_port);
4439 }
4440
4441 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4442 {
4443         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4444         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4445         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4446         enum phy phy = intel_port_to_phy(i915, encoder->port);
4447
4448         intel_dp_encoder_shutdown(encoder);
4449
4450         if (!intel_phy_is_tc(i915, phy))
4451                 return;
4452
4453         intel_tc_port_disconnect_phy(dig_port);
4454 }
4455
4456 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4457 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4458
4459 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4460 {
4461         struct intel_digital_port *dig_port;
4462         struct intel_encoder *encoder;
4463         const struct intel_bios_encoder_data *devdata;
4464         bool init_hdmi, init_dp;
4465         enum phy phy = intel_port_to_phy(dev_priv, port);
4466
4467         /*
4468          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4469          * have taken over some of the PHYs and made them unavailable to the
4470          * driver.  In that case we should skip initializing the corresponding
4471          * outputs.
4472          */
4473         if (hti_uses_phy(dev_priv, phy)) {
4474                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4475                             port_name(port), phy_name(phy));
4476                 return;
4477         }
4478
4479         devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4480         if (!devdata) {
4481                 drm_dbg_kms(&dev_priv->drm,
4482                             "VBT says port %c is not present\n",
4483                             port_name(port));
4484                 return;
4485         }
4486
4487         init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4488                 intel_bios_encoder_supports_hdmi(devdata);
4489         init_dp = intel_bios_encoder_supports_dp(devdata);
4490
4491         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4492                 /*
4493                  * Lspcon device needs to be driven with DP connector
4494                  * with special detection sequence. So make sure DP
4495                  * is initialized before lspcon.
4496                  */
4497                 init_dp = true;
4498                 init_hdmi = false;
4499                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4500                             port_name(port));
4501         }
4502
4503         if (!init_dp && !init_hdmi) {
4504                 drm_dbg_kms(&dev_priv->drm,
4505                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4506                             port_name(port));
4507                 return;
4508         }
4509
4510         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4511         if (!dig_port)
4512                 return;
4513
4514         encoder = &dig_port->base;
4515         encoder->devdata = devdata;
4516
4517         if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4518                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4519                                  DRM_MODE_ENCODER_TMDS,
4520                                  "DDI %c/PHY %c",
4521                                  port_name(port - PORT_D_XELPD + PORT_D),
4522                                  phy_name(phy));
4523         } else if (DISPLAY_VER(dev_priv) >= 12) {
4524                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4525
4526                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4527                                  DRM_MODE_ENCODER_TMDS,
4528                                  "DDI %s%c/PHY %s%c",
4529                                  port >= PORT_TC1 ? "TC" : "",
4530                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4531                                  tc_port != TC_PORT_NONE ? "TC" : "",
4532                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4533         } else if (DISPLAY_VER(dev_priv) >= 11) {
4534                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4535
4536                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4537                                  DRM_MODE_ENCODER_TMDS,
4538                                  "DDI %c%s/PHY %s%c",
4539                                  port_name(port),
4540                                  port >= PORT_C ? " (TC)" : "",
4541                                  tc_port != TC_PORT_NONE ? "TC" : "",
4542                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4543         } else {
4544                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4545                                  DRM_MODE_ENCODER_TMDS,
4546                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4547         }
4548
4549         mutex_init(&dig_port->hdcp_mutex);
4550         dig_port->num_hdcp_streams = 0;
4551
4552         encoder->hotplug = intel_ddi_hotplug;
4553         encoder->compute_output_type = intel_ddi_compute_output_type;
4554         encoder->compute_config = intel_ddi_compute_config;
4555         encoder->compute_config_late = intel_ddi_compute_config_late;
4556         encoder->enable = intel_enable_ddi;
4557         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4558         encoder->pre_enable = intel_ddi_pre_enable;
4559         encoder->pre_disable = intel_pre_disable_ddi;
4560         encoder->disable = intel_disable_ddi;
4561         encoder->post_disable = intel_ddi_post_disable;
4562         encoder->update_pipe = intel_ddi_update_pipe;
4563         encoder->get_hw_state = intel_ddi_get_hw_state;
4564         encoder->sync_state = intel_ddi_sync_state;
4565         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4566         encoder->suspend = intel_ddi_encoder_suspend;
4567         encoder->shutdown = intel_ddi_encoder_shutdown;
4568         encoder->get_power_domains = intel_ddi_get_power_domains;
4569
4570         encoder->type = INTEL_OUTPUT_DDI;
4571         encoder->power_domain = intel_port_to_power_domain(port);
4572         encoder->port = port;
4573         encoder->cloneable = 0;
4574         encoder->pipe_mask = ~0;
4575
4576         if (IS_DG2(dev_priv)) {
4577                 encoder->enable_clock = intel_mpllb_enable;
4578                 encoder->disable_clock = intel_mpllb_disable;
4579                 encoder->get_config = dg2_ddi_get_config;
4580         } else if (IS_ALDERLAKE_S(dev_priv)) {
4581                 encoder->enable_clock = adls_ddi_enable_clock;
4582                 encoder->disable_clock = adls_ddi_disable_clock;
4583                 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4584                 encoder->get_config = adls_ddi_get_config;
4585         } else if (IS_ROCKETLAKE(dev_priv)) {
4586                 encoder->enable_clock = rkl_ddi_enable_clock;
4587                 encoder->disable_clock = rkl_ddi_disable_clock;
4588                 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4589                 encoder->get_config = rkl_ddi_get_config;
4590         } else if (IS_DG1(dev_priv)) {
4591                 encoder->enable_clock = dg1_ddi_enable_clock;
4592                 encoder->disable_clock = dg1_ddi_disable_clock;
4593                 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4594                 encoder->get_config = dg1_ddi_get_config;
4595         } else if (IS_JSL_EHL(dev_priv)) {
4596                 if (intel_ddi_is_tc(dev_priv, port)) {
4597                         encoder->enable_clock = jsl_ddi_tc_enable_clock;
4598                         encoder->disable_clock = jsl_ddi_tc_disable_clock;
4599                         encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4600                         encoder->get_config = icl_ddi_combo_get_config;
4601                 } else {
4602                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4603                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4604                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4605                         encoder->get_config = icl_ddi_combo_get_config;
4606                 }
4607         } else if (DISPLAY_VER(dev_priv) >= 11) {
4608                 if (intel_ddi_is_tc(dev_priv, port)) {
4609                         encoder->enable_clock = icl_ddi_tc_enable_clock;
4610                         encoder->disable_clock = icl_ddi_tc_disable_clock;
4611                         encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4612                         encoder->get_config = icl_ddi_tc_get_config;
4613                 } else {
4614                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4615                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4616                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4617                         encoder->get_config = icl_ddi_combo_get_config;
4618                 }
4619         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4620                 /* BXT/GLK have fixed PLL->port mapping */
4621                 encoder->get_config = bxt_ddi_get_config;
4622         } else if (DISPLAY_VER(dev_priv) == 9) {
4623                 encoder->enable_clock = skl_ddi_enable_clock;
4624                 encoder->disable_clock = skl_ddi_disable_clock;
4625                 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4626                 encoder->get_config = skl_ddi_get_config;
4627         } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4628                 encoder->enable_clock = hsw_ddi_enable_clock;
4629                 encoder->disable_clock = hsw_ddi_disable_clock;
4630                 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4631                 encoder->get_config = hsw_ddi_get_config;
4632         }
4633
4634         intel_ddi_buf_trans_init(encoder);
4635
4636         if (DISPLAY_VER(dev_priv) >= 13)
4637                 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4638         else if (IS_DG1(dev_priv))
4639                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4640         else if (IS_ROCKETLAKE(dev_priv))
4641                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4642         else if (DISPLAY_VER(dev_priv) >= 12)
4643                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4644         else if (IS_JSL_EHL(dev_priv))
4645                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4646         else if (DISPLAY_VER(dev_priv) == 11)
4647                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4648         else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4649                 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4650         else
4651                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4652
4653         if (DISPLAY_VER(dev_priv) >= 11)
4654                 dig_port->saved_port_bits =
4655                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4656                         & DDI_BUF_PORT_REVERSAL;
4657         else
4658                 dig_port->saved_port_bits =
4659                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4660                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4661
4662         if (intel_bios_is_lane_reversal_needed(dev_priv, port))
4663                 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4664
4665         dig_port->dp.output_reg = INVALID_MMIO_REG;
4666         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4667         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4668
4669         if (intel_phy_is_tc(dev_priv, phy)) {
4670                 bool is_legacy =
4671                         !intel_bios_encoder_supports_typec_usb(devdata) &&
4672                         !intel_bios_encoder_supports_tbt(devdata);
4673
4674                 intel_tc_port_init(dig_port, is_legacy);
4675
4676                 encoder->update_prepare = intel_ddi_update_prepare;
4677                 encoder->update_complete = intel_ddi_update_complete;
4678         }
4679
4680         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4681         dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4682                                               port - PORT_A;
4683
4684         if (init_dp) {
4685                 if (!intel_ddi_init_dp_connector(dig_port))
4686                         goto err;
4687
4688                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4689
4690                 if (dig_port->dp.mso_link_count)
4691                         encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4692         }
4693
4694         /* In theory we don't need the encoder->type check, but leave it just in
4695          * case we have some really bad VBTs... */
4696         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4697                 if (!intel_ddi_init_hdmi_connector(dig_port))
4698                         goto err;
4699         }
4700
4701         if (DISPLAY_VER(dev_priv) >= 11) {
4702                 if (intel_phy_is_tc(dev_priv, phy))
4703                         dig_port->connected = intel_tc_port_connected;
4704                 else
4705                         dig_port->connected = lpt_digital_port_connected;
4706         } else if (DISPLAY_VER(dev_priv) >= 8) {
4707                 if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||
4708                     IS_BROXTON(dev_priv))
4709                         dig_port->connected = bdw_digital_port_connected;
4710                 else
4711                         dig_port->connected = lpt_digital_port_connected;
4712         } else {
4713                 if (port == PORT_A)
4714                         dig_port->connected = hsw_digital_port_connected;
4715                 else
4716                         dig_port->connected = lpt_digital_port_connected;
4717         }
4718
4719         intel_infoframe_init(dig_port);
4720
4721         return;
4722
4723 err:
4724         drm_encoder_cleanup(&encoder->base);
4725         kfree(dig_port);
4726 }