2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
26 #include "intel_color.h"
28 #include "intel_display_types.h"
29 #include "intel_dsb.h"
31 struct intel_color_funcs {
32 int (*color_check)(struct intel_crtc_state *crtc_state);
34 * Program non-arming double buffered color management registers
35 * before vblank evasion. The registers should then latch after
36 * the arming register is written (by color_commit_arm()) during
37 * the next vblank start, alongside any other double buffered
38 * registers involved with the same commit. This hook is optional.
40 void (*color_commit_noarm)(const struct intel_crtc_state *crtc_state);
42 * Program arming double buffered color management registers
43 * during vblank evasion. The registers (and whatever other registers
44 * they arm that were written by color_commit_noarm) should then latch
45 * during the next vblank start, alongside any other double buffered
46 * registers involved with the same commit.
48 void (*color_commit_arm)(const struct intel_crtc_state *crtc_state);
50 * Perform any extra tasks needed after all the
51 * double buffered registers have been latched.
53 void (*color_post_update)(const struct intel_crtc_state *crtc_state);
55 * Load LUTs (and other single buffered color management
56 * registers). Will (hopefully) be called during the vblank
57 * following the latching of any double buffered registers
58 * involved with the same commit.
60 void (*load_luts)(const struct intel_crtc_state *crtc_state);
62 * Read out the LUTs from the hardware into the software state.
63 * Used by eg. the hardware state checker.
65 void (*read_luts)(struct intel_crtc_state *crtc_state);
69 bool (*lut_equal)(const struct intel_crtc_state *crtc_state,
70 const struct drm_property_blob *blob1,
71 const struct drm_property_blob *blob2,
74 * Read out the CSCs (if any) from the hardware into the
75 * software state. Used by eg. the hardware state checker.
77 void (*read_csc)(struct intel_crtc_state *crtc_state);
80 #define CTM_COEFF_SIGN (1ULL << 63)
82 #define CTM_COEFF_1_0 (1ULL << 32)
83 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
84 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
85 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
86 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
87 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
88 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
90 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
92 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
93 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
95 #define LEGACY_LUT_LENGTH 256
100 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0|
101 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
102 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2|
104 * ILK/SNB don't have explicit post offsets, and instead
105 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
106 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
107 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
108 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
109 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
113 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
114 * format). This macro takes the coefficient we want transformed and the
115 * number of fractional bits.
117 * We only have a 9 bits precision window which slides depending on the value
118 * of the CTM coefficient and we write the value from bit 3. We also round the
121 #define ILK_CSC_COEFF_FP(coeff, fbits) \
122 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
124 #define ILK_CSC_COEFF_1_0 0x7800
125 #define ILK_CSC_COEFF_LIMITED_RANGE ((235 - 16) << (12 - 8)) /* exponent 0 */
126 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 << (12 - 8))
128 static const struct intel_csc_matrix ilk_csc_matrix_identity = {
131 ILK_CSC_COEFF_1_0, 0, 0,
132 0, ILK_CSC_COEFF_1_0, 0,
133 0, 0, ILK_CSC_COEFF_1_0,
138 /* Full range RGB -> limited range RGB matrix */
139 static const struct intel_csc_matrix ilk_csc_matrix_limited_range = {
142 ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
143 0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
144 0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
147 ILK_CSC_POSTOFF_LIMITED_RANGE,
148 ILK_CSC_POSTOFF_LIMITED_RANGE,
149 ILK_CSC_POSTOFF_LIMITED_RANGE,
153 /* BT.709 full range RGB -> limited range YCbCr matrix */
154 static const struct intel_csc_matrix ilk_csc_matrix_rgb_to_ycbcr = {
157 0x1e08, 0x9cc0, 0xb528,
158 0x2ba8, 0x09d8, 0x37e8,
159 0xbce8, 0x9ad8, 0x1e08,
162 0x0800, 0x0100, 0x0800,
166 static void intel_csc_clear(struct intel_csc_matrix *csc)
168 memset(csc, 0, sizeof(*csc));
171 static bool lut_is_legacy(const struct drm_property_blob *lut)
173 return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
177 * When using limited range, multiply the matrix given by userspace by
178 * the matrix that we would use for the limited range.
180 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
184 for (i = 0; i < 9; i++) {
185 u64 user_coeff = input[i];
186 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
187 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
188 CTM_COEFF_4_0 - 1) >> 2;
191 * By scaling every co-efficient with limited range (16-235)
192 * vs full range (0-255) the final o/p will be scaled down to
193 * fit in the limited range supported by the panel.
195 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
196 result[i] |= user_coeff & CTM_COEFF_SIGN;
202 static void ilk_update_pipe_csc(struct intel_crtc *crtc,
203 const struct intel_csc_matrix *csc)
205 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
206 enum pipe pipe = crtc->pipe;
208 intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), csc->preoff[0]);
209 intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), csc->preoff[1]);
210 intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), csc->preoff[2]);
212 intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe),
213 csc->coeff[0] << 16 | csc->coeff[1]);
214 intel_de_write_fw(i915, PIPE_CSC_COEFF_BY(pipe),
215 csc->coeff[2] << 16);
217 intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe),
218 csc->coeff[3] << 16 | csc->coeff[4]);
219 intel_de_write_fw(i915, PIPE_CSC_COEFF_BU(pipe),
220 csc->coeff[5] << 16);
222 intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe),
223 csc->coeff[6] << 16 | csc->coeff[7]);
224 intel_de_write_fw(i915, PIPE_CSC_COEFF_BV(pipe),
225 csc->coeff[8] << 16);
227 if (DISPLAY_VER(i915) < 7)
230 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_HI(pipe), csc->postoff[0]);
231 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_ME(pipe), csc->postoff[1]);
232 intel_de_write_fw(i915, PIPE_CSC_POSTOFF_LO(pipe), csc->postoff[2]);
235 static void ilk_read_pipe_csc(struct intel_crtc *crtc,
236 struct intel_csc_matrix *csc)
238 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
239 enum pipe pipe = crtc->pipe;
242 csc->preoff[0] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_HI(pipe));
243 csc->preoff[1] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_ME(pipe));
244 csc->preoff[2] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_LO(pipe));
246 tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe));
247 csc->coeff[0] = tmp >> 16;
248 csc->coeff[1] = tmp & 0xffff;
249 tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BY(pipe));
250 csc->coeff[2] = tmp >> 16;
252 tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe));
253 csc->coeff[3] = tmp >> 16;
254 csc->coeff[4] = tmp & 0xffff;
255 tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BU(pipe));
256 csc->coeff[5] = tmp >> 16;
258 tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe));
259 csc->coeff[6] = tmp >> 16;
260 csc->coeff[7] = tmp & 0xffff;
261 tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BV(pipe));
262 csc->coeff[8] = tmp >> 16;
264 if (DISPLAY_VER(i915) < 7)
267 csc->postoff[0] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_HI(pipe));
268 csc->postoff[1] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_ME(pipe));
269 csc->postoff[2] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_LO(pipe));
272 static void ilk_read_csc(struct intel_crtc_state *crtc_state)
274 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
276 if (crtc_state->csc_enable)
277 ilk_read_pipe_csc(crtc, &crtc_state->csc);
280 static void skl_read_csc(struct intel_crtc_state *crtc_state)
282 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
285 * Display WA #1184: skl,glk
288 * Danger! On SKL-ICL *reads* from the CSC coeff/offset registers
289 * will disarm an already armed CSC double buffer update.
290 * So this must not be called while armed. Fortunately the state checker
291 * readout happens only after the update has been already been latched.
293 * On earlier and later platforms only writes to said registers will
294 * disarm the update. This is considered normal behavior and also
295 * happens with various other hardware units.
297 if (crtc_state->csc_enable)
298 ilk_read_pipe_csc(crtc, &crtc_state->csc);
301 static void icl_update_output_csc(struct intel_crtc *crtc,
302 const struct intel_csc_matrix *csc)
304 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
305 enum pipe pipe = crtc->pipe;
307 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), csc->preoff[0]);
308 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), csc->preoff[1]);
309 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), csc->preoff[2]);
311 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
312 csc->coeff[0] << 16 | csc->coeff[1]);
313 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
314 csc->coeff[2] << 16);
316 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
317 csc->coeff[3] << 16 | csc->coeff[4]);
318 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
319 csc->coeff[5] << 16);
321 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
322 csc->coeff[6] << 16 | csc->coeff[7]);
323 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
324 csc->coeff[8] << 16);
326 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), csc->postoff[0]);
327 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), csc->postoff[1]);
328 intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), csc->postoff[2]);
331 static void icl_read_output_csc(struct intel_crtc *crtc,
332 struct intel_csc_matrix *csc)
334 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
335 enum pipe pipe = crtc->pipe;
338 csc->preoff[0] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_PREOFF_HI(pipe));
339 csc->preoff[1] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_PREOFF_ME(pipe));
340 csc->preoff[2] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_PREOFF_LO(pipe));
342 tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));
343 csc->coeff[0] = tmp >> 16;
344 csc->coeff[1] = tmp & 0xffff;
345 tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_BY(pipe));
346 csc->coeff[2] = tmp >> 16;
348 tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));
349 csc->coeff[3] = tmp >> 16;
350 csc->coeff[4] = tmp & 0xffff;
351 tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_BU(pipe));
352 csc->coeff[5] = tmp >> 16;
354 tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));
355 csc->coeff[6] = tmp >> 16;
356 csc->coeff[7] = tmp & 0xffff;
357 tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_BV(pipe));
358 csc->coeff[8] = tmp >> 16;
360 csc->postoff[0] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe));
361 csc->postoff[1] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe));
362 csc->postoff[2] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe));
365 static void icl_read_csc(struct intel_crtc_state *crtc_state)
367 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
374 if (crtc_state->csc_mode & ICL_CSC_ENABLE)
375 ilk_read_pipe_csc(crtc, &crtc_state->csc);
377 if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE)
378 icl_read_output_csc(crtc, &crtc_state->output_csc);
381 static bool ilk_limited_range(const struct intel_crtc_state *crtc_state)
383 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
385 /* icl+ have dedicated output CSC */
386 if (DISPLAY_VER(i915) >= 11)
389 /* pre-hsw have TRANSCONF_COLOR_RANGE_SELECT */
390 if (DISPLAY_VER(i915) < 7 || IS_IVYBRIDGE(i915))
393 return crtc_state->limited_color_range;
396 static bool ilk_lut_limited_range(const struct intel_crtc_state *crtc_state)
398 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
400 if (!ilk_limited_range(crtc_state))
403 if (crtc_state->c8_planes)
406 if (DISPLAY_VER(i915) == 10)
407 return crtc_state->hw.gamma_lut;
409 return crtc_state->hw.gamma_lut &&
410 (crtc_state->hw.degamma_lut || crtc_state->hw.ctm);
413 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
415 if (!ilk_limited_range(crtc_state))
418 return !ilk_lut_limited_range(crtc_state);
421 static void ilk_csc_copy(struct drm_i915_private *i915,
422 struct intel_csc_matrix *dst,
423 const struct intel_csc_matrix *src)
427 if (DISPLAY_VER(i915) < 7)
428 memset(dst->postoff, 0, sizeof(dst->postoff));
431 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
432 struct intel_csc_matrix *csc,
433 bool limited_color_range)
435 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
436 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
441 /* for preoff/postoff */
442 if (limited_color_range)
443 ilk_csc_copy(i915, csc, &ilk_csc_matrix_limited_range);
445 ilk_csc_copy(i915, csc, &ilk_csc_matrix_identity);
447 if (limited_color_range)
448 input = ctm_mult_by_limited(temp, ctm->matrix);
453 * Convert fixed point S31.32 input to format supported by the
456 for (i = 0; i < 9; i++) {
457 u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
460 * Clamp input value to min/max supported by
463 abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
468 if (CTM_COEFF_NEGATIVE(input[i]))
469 csc->coeff[i] |= 1 << 15;
471 if (abs_coeff < CTM_COEFF_0_125)
472 csc->coeff[i] |= (3 << 12) |
473 ILK_CSC_COEFF_FP(abs_coeff, 12);
474 else if (abs_coeff < CTM_COEFF_0_25)
475 csc->coeff[i] |= (2 << 12) |
476 ILK_CSC_COEFF_FP(abs_coeff, 11);
477 else if (abs_coeff < CTM_COEFF_0_5)
478 csc->coeff[i] |= (1 << 12) |
479 ILK_CSC_COEFF_FP(abs_coeff, 10);
480 else if (abs_coeff < CTM_COEFF_1_0)
481 csc->coeff[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
482 else if (abs_coeff < CTM_COEFF_2_0)
483 csc->coeff[i] |= (7 << 12) |
484 ILK_CSC_COEFF_FP(abs_coeff, 8);
486 csc->coeff[i] |= (6 << 12) |
487 ILK_CSC_COEFF_FP(abs_coeff, 7);
491 static void ilk_assign_csc(struct intel_crtc_state *crtc_state)
493 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
494 bool limited_color_range = ilk_csc_limited_range(crtc_state);
496 if (crtc_state->hw.ctm) {
497 drm_WARN_ON(&i915->drm, !crtc_state->csc_enable);
499 ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, limited_color_range);
500 } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
501 drm_WARN_ON(&i915->drm, !crtc_state->csc_enable);
503 ilk_csc_copy(i915, &crtc_state->csc, &ilk_csc_matrix_rgb_to_ycbcr);
504 } else if (limited_color_range) {
505 drm_WARN_ON(&i915->drm, !crtc_state->csc_enable);
507 ilk_csc_copy(i915, &crtc_state->csc, &ilk_csc_matrix_limited_range);
508 } else if (crtc_state->csc_enable) {
510 * On GLK both pipe CSC and degamma LUT are controlled
511 * by csc_enable. Hence for the cases where the degama
512 * LUT is needed but CSC is not we need to load an
515 drm_WARN_ON(&i915->drm, !IS_GEMINILAKE(i915));
517 ilk_csc_copy(i915, &crtc_state->csc, &ilk_csc_matrix_identity);
519 intel_csc_clear(&crtc_state->csc);
523 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
525 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
527 if (crtc_state->csc_enable)
528 ilk_update_pipe_csc(crtc, &crtc_state->csc);
531 static void icl_assign_csc(struct intel_crtc_state *crtc_state)
533 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
535 if (crtc_state->hw.ctm) {
536 drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) == 0);
538 ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, false);
540 drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) != 0);
542 intel_csc_clear(&crtc_state->csc);
545 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
546 drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
548 ilk_csc_copy(i915, &crtc_state->output_csc, &ilk_csc_matrix_rgb_to_ycbcr);
549 } else if (crtc_state->limited_color_range) {
550 drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
552 ilk_csc_copy(i915, &crtc_state->output_csc, &ilk_csc_matrix_limited_range);
554 drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) != 0);
556 intel_csc_clear(&crtc_state->output_csc);
560 static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
562 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
564 if (crtc_state->csc_mode & ICL_CSC_ENABLE)
565 ilk_update_pipe_csc(crtc, &crtc_state->csc);
567 if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE)
568 icl_update_output_csc(crtc, &crtc_state->output_csc);
571 static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
573 s64 c = CTM_COEFF_ABS(coeff);
575 /* leave an extra bit for rounding */
576 c >>= 32 - frac_bits - 1;
578 /* round and drop the extra bit */
581 if (CTM_COEFF_NEGATIVE(coeff))
584 c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
585 (s64)(BIT(int_bits + frac_bits - 1) - 1));
587 return c & (BIT(int_bits + frac_bits) - 1);
591 * CHV Color Gamut Mapping (CGM) CSC
592 * |r| | c0 c1 c2 | |r|
593 * |g| = | c3 c4 c5 | x |g|
594 * |b| | c6 c7 c8 | |b|
596 * Coefficients are two's complement s4.12.
598 static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
599 struct intel_csc_matrix *csc)
601 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
604 for (i = 0; i < 9; i++)
605 csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
608 static void chv_load_cgm_csc(struct intel_crtc *crtc,
609 const struct intel_csc_matrix *csc)
611 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
612 enum pipe pipe = crtc->pipe;
614 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF01(pipe),
615 csc->coeff[1] << 16 | csc->coeff[0]);
616 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF23(pipe),
617 csc->coeff[3] << 16 | csc->coeff[2]);
618 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF45(pipe),
619 csc->coeff[5] << 16 | csc->coeff[4]);
620 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF67(pipe),
621 csc->coeff[7] << 16 | csc->coeff[6]);
622 intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF8(pipe),
626 static void chv_read_cgm_csc(struct intel_crtc *crtc,
627 struct intel_csc_matrix *csc)
629 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
630 enum pipe pipe = crtc->pipe;
633 tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF01(pipe));
634 csc->coeff[0] = tmp & 0xffff;
635 csc->coeff[1] = tmp >> 16;
637 tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF23(pipe));
638 csc->coeff[2] = tmp & 0xffff;
639 csc->coeff[3] = tmp >> 16;
641 tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF45(pipe));
642 csc->coeff[4] = tmp & 0xffff;
643 csc->coeff[5] = tmp >> 16;
645 tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF67(pipe));
646 csc->coeff[6] = tmp & 0xffff;
647 csc->coeff[7] = tmp >> 16;
649 tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF8(pipe));
650 csc->coeff[8] = tmp & 0xffff;
653 static void chv_read_csc(struct intel_crtc_state *crtc_state)
655 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
657 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
658 chv_read_cgm_csc(crtc, &crtc_state->csc);
661 static void chv_assign_csc(struct intel_crtc_state *crtc_state)
663 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
665 if (crtc_state->hw.ctm) {
666 drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
668 chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc);
670 drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) != 0);
672 intel_csc_clear(&crtc_state->csc);
676 /* convert hw value with given bit_precision to lut property val */
677 static u32 intel_color_lut_pack(u32 val, int bit_precision)
679 u32 max = 0xffff >> (16 - bit_precision);
681 val = clamp_val(val, 0, max);
683 if (bit_precision < 16)
684 val <<= 16 - bit_precision;
689 static u32 i9xx_lut_8(const struct drm_color_lut *color)
691 return REG_FIELD_PREP(PALETTE_RED_MASK, drm_color_lut_extract(color->red, 8)) |
692 REG_FIELD_PREP(PALETTE_GREEN_MASK, drm_color_lut_extract(color->green, 8)) |
693 REG_FIELD_PREP(PALETTE_BLUE_MASK, drm_color_lut_extract(color->blue, 8));
696 static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
698 entry->red = intel_color_lut_pack(REG_FIELD_GET(PALETTE_RED_MASK, val), 8);
699 entry->green = intel_color_lut_pack(REG_FIELD_GET(PALETTE_GREEN_MASK, val), 8);
700 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PALETTE_BLUE_MASK, val), 8);
703 /* i8xx/i9xx+ 10bit slope format "even DW" (low 8 bits) */
704 static u32 _i9xx_lut_10_ldw(u16 a)
706 return drm_color_lut_extract(a, 10) & 0xff;
709 static u32 i9xx_lut_10_ldw(const struct drm_color_lut *color)
711 return REG_FIELD_PREP(PALETTE_RED_MASK, _i9xx_lut_10_ldw(color[0].red)) |
712 REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_ldw(color[0].green)) |
713 REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_ldw(color[0].blue));
716 /* i8xx/i9xx+ 10bit slope format "odd DW" (high 2 bits + slope) */
717 static u32 _i9xx_lut_10_udw(u16 a, u16 b)
719 unsigned int mantissa, exponent;
721 a = drm_color_lut_extract(a, 10);
722 b = drm_color_lut_extract(b, 10);
724 /* b = a + 8 * m * 2 ^ -e */
725 mantissa = clamp(b - a, 0, 0x7f);
727 while (mantissa > 0xf) {
732 return (exponent << 6) |
737 static u32 i9xx_lut_10_udw(const struct drm_color_lut *color)
739 return REG_FIELD_PREP(PALETTE_RED_MASK, _i9xx_lut_10_udw(color[0].red, color[1].red)) |
740 REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_udw(color[0].green, color[1].green)) |
741 REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_udw(color[0].blue, color[1].blue));
744 static void i9xx_lut_10_pack(struct drm_color_lut *color,
747 u16 red = REG_FIELD_GET(PALETTE_10BIT_RED_LDW_MASK, ldw) |
748 REG_FIELD_GET(PALETTE_10BIT_RED_UDW_MASK, udw) << 8;
749 u16 green = REG_FIELD_GET(PALETTE_10BIT_GREEN_LDW_MASK, ldw) |
750 REG_FIELD_GET(PALETTE_10BIT_GREEN_UDW_MASK, udw) << 8;
751 u16 blue = REG_FIELD_GET(PALETTE_10BIT_BLUE_LDW_MASK, ldw) |
752 REG_FIELD_GET(PALETTE_10BIT_BLUE_UDW_MASK, udw) << 8;
754 color->red = intel_color_lut_pack(red, 10);
755 color->green = intel_color_lut_pack(green, 10);
756 color->blue = intel_color_lut_pack(blue, 10);
759 static void i9xx_lut_10_pack_slope(struct drm_color_lut *color,
762 int r_exp = REG_FIELD_GET(PALETTE_10BIT_RED_EXP_MASK, udw);
763 int r_mant = REG_FIELD_GET(PALETTE_10BIT_RED_MANT_MASK, udw);
764 int g_exp = REG_FIELD_GET(PALETTE_10BIT_GREEN_EXP_MASK, udw);
765 int g_mant = REG_FIELD_GET(PALETTE_10BIT_GREEN_MANT_MASK, udw);
766 int b_exp = REG_FIELD_GET(PALETTE_10BIT_BLUE_EXP_MASK, udw);
767 int b_mant = REG_FIELD_GET(PALETTE_10BIT_BLUE_MANT_MASK, udw);
769 i9xx_lut_10_pack(color, ldw, udw);
771 color->red += r_mant << (3 - r_exp);
772 color->green += g_mant << (3 - g_exp);
773 color->blue += b_mant << (3 - b_exp);
776 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
777 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
779 return REG_FIELD_PREP(PALETTE_RED_MASK, color->red & 0xff) |
780 REG_FIELD_PREP(PALETTE_GREEN_MASK, color->green & 0xff) |
781 REG_FIELD_PREP(PALETTE_BLUE_MASK, color->blue & 0xff);
784 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
785 static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
787 return REG_FIELD_PREP(PALETTE_RED_MASK, color->red >> 8) |
788 REG_FIELD_PREP(PALETTE_GREEN_MASK, color->green >> 8) |
789 REG_FIELD_PREP(PALETTE_BLUE_MASK, color->blue >> 8);
792 static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
794 entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
795 REG_FIELD_GET(PALETTE_RED_MASK, ldw);
796 entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
797 REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
798 entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
799 REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
802 static u16 i965_lut_11p6_max_pack(u32 val)
804 /* PIPEGCMAX is 11.6, clamp to 10.6 */
805 return clamp_val(val, 0, 0xffff);
808 static u32 ilk_lut_10(const struct drm_color_lut *color)
810 return REG_FIELD_PREP(PREC_PALETTE_10_RED_MASK, drm_color_lut_extract(color->red, 10)) |
811 REG_FIELD_PREP(PREC_PALETTE_10_GREEN_MASK, drm_color_lut_extract(color->green, 10)) |
812 REG_FIELD_PREP(PREC_PALETTE_10_BLUE_MASK, drm_color_lut_extract(color->blue, 10));
815 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
817 entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_RED_MASK, val), 10);
818 entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_GREEN_MASK, val), 10);
819 entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_BLUE_MASK, val), 10);
822 /* ilk+ "12.4" interpolated format (low 6 bits) */
823 static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
825 return REG_FIELD_PREP(PREC_PALETTE_12P4_RED_LDW_MASK, color->red & 0x3f) |
826 REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_LDW_MASK, color->green & 0x3f) |
827 REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_LDW_MASK, color->blue & 0x3f);
830 /* ilk+ "12.4" interpolated format (high 10 bits) */
831 static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
833 return REG_FIELD_PREP(PREC_PALETTE_12P4_RED_UDW_MASK, color->red >> 6) |
834 REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_UDW_MASK, color->green >> 6) |
835 REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_UDW_MASK, color->blue >> 6);
838 static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
840 entry->red = REG_FIELD_GET(PREC_PALETTE_12P4_RED_UDW_MASK, udw) << 6 |
841 REG_FIELD_GET(PREC_PALETTE_12P4_RED_LDW_MASK, ldw);
842 entry->green = REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_UDW_MASK, udw) << 6 |
843 REG_FIELD_GET(PREC_PALETTE_12P4_GREEN_LDW_MASK, ldw);
844 entry->blue = REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_UDW_MASK, udw) << 6 |
845 REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_LDW_MASK, ldw);
848 static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
851 * Despite Wa_1406463849, ICL no longer suffers from the SKL
852 * DC5/PSR CSC black screen issue (see skl_color_commit_noarm()).
853 * Possibly due to the extra sticky CSC arming
854 * (see icl_color_post_update()).
856 * On TGL+ all CSC arming issues have been properly fixed.
858 icl_load_csc_matrix(crtc_state);
861 static void skl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
864 * Possibly related to display WA #1184, SKL CSC loses the latched
865 * CSC coeff/offset register values if the CSC registers are disarmed
866 * between DC5 exit and PSR exit. This will cause the plane(s) to
867 * output all black (until CSC_MODE is rearmed and properly latched).
868 * Once PSR exit (and proper register latching) has occurred the
869 * danger is over. Thus when PSR is enabled the CSC coeff/offset
870 * register programming will be peformed from skl_color_commit_arm()
871 * which is called after PSR exit.
873 if (!crtc_state->has_psr)
874 ilk_load_csc_matrix(crtc_state);
877 static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state)
879 ilk_load_csc_matrix(crtc_state);
882 static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
884 /* update TRANSCONF GAMMA_MODE */
885 i9xx_set_pipeconf(crtc_state);
888 static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
891 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
893 /* update TRANSCONF GAMMA_MODE */
894 ilk_set_pipeconf(crtc_state);
896 intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
897 crtc_state->csc_mode);
900 static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
902 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
903 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
905 intel_de_write(i915, GAMMA_MODE(crtc->pipe),
906 crtc_state->gamma_mode);
908 intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
909 crtc_state->csc_mode);
912 static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
914 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
915 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
916 enum pipe pipe = crtc->pipe;
919 if (crtc_state->has_psr)
920 ilk_load_csc_matrix(crtc_state);
923 * We don't (yet) allow userspace to control the pipe background color,
924 * so force it to black, but apply pipe gamma and CSC appropriately
925 * so that its handling will match how we program our planes.
927 if (crtc_state->gamma_enable)
928 val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
929 if (crtc_state->csc_enable)
930 val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
931 intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), val);
933 intel_de_write(i915, GAMMA_MODE(crtc->pipe),
934 crtc_state->gamma_mode);
936 intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
937 crtc_state->csc_mode);
940 static void icl_color_commit_arm(const struct intel_crtc_state *crtc_state)
942 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
943 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
944 enum pipe pipe = crtc->pipe;
947 * We don't (yet) allow userspace to control the pipe background color,
948 * so force it to black.
950 intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), 0);
952 intel_de_write(i915, GAMMA_MODE(crtc->pipe),
953 crtc_state->gamma_mode);
955 intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
956 crtc_state->csc_mode);
959 static void icl_color_post_update(const struct intel_crtc_state *crtc_state)
961 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
962 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
965 * Despite Wa_1406463849, ICL CSC is no longer disarmed by
966 * coeff/offset register *writes*. Instead, once CSC_MODE
967 * is armed it stays armed, even after it has been latched.
968 * Afterwards the coeff/offset registers become effectively
969 * self-arming. That self-arming must be disabled before the
970 * next icl_color_commit_noarm() tries to write the next set
971 * of coeff/offset registers. Fortunately register *reads*
972 * do still disarm the CSC. Naturally this must not be done
973 * until the previously written CSC registers have actually
976 * TGL+ no longer need this workaround.
978 intel_de_read_fw(i915, PIPE_CSC_PREOFF_HI(crtc->pipe));
981 static struct drm_property_blob *
982 create_linear_lut(struct drm_i915_private *i915, int lut_size)
984 struct drm_property_blob *blob;
985 struct drm_color_lut *lut;
988 blob = drm_property_create_blob(&i915->drm,
989 sizeof(lut[0]) * lut_size,
996 for (i = 0; i < lut_size; i++) {
997 u16 val = 0xffff * i / (lut_size - 1);
1007 static u16 lut_limited_range(unsigned int value)
1009 unsigned int min = 16 << 8;
1010 unsigned int max = 235 << 8;
1012 return value * (max - min) / 0xffff + min;
1015 static struct drm_property_blob *
1016 create_resized_lut(struct drm_i915_private *i915,
1017 const struct drm_property_blob *blob_in, int lut_out_size,
1018 bool limited_color_range)
1020 int i, lut_in_size = drm_color_lut_size(blob_in);
1021 struct drm_property_blob *blob_out;
1022 const struct drm_color_lut *lut_in;
1023 struct drm_color_lut *lut_out;
1025 blob_out = drm_property_create_blob(&i915->drm,
1026 sizeof(lut_out[0]) * lut_out_size,
1028 if (IS_ERR(blob_out))
1031 lut_in = blob_in->data;
1032 lut_out = blob_out->data;
1034 for (i = 0; i < lut_out_size; i++) {
1035 const struct drm_color_lut *entry =
1036 &lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)];
1038 if (limited_color_range) {
1039 lut_out[i].red = lut_limited_range(entry->red);
1040 lut_out[i].green = lut_limited_range(entry->green);
1041 lut_out[i].blue = lut_limited_range(entry->blue);
1043 lut_out[i] = *entry;
1050 static void i9xx_load_lut_8(struct intel_crtc *crtc,
1051 const struct drm_property_blob *blob)
1053 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1054 const struct drm_color_lut *lut;
1055 enum pipe pipe = crtc->pipe;
1063 for (i = 0; i < 256; i++)
1064 intel_de_write_fw(dev_priv, PALETTE(pipe, i),
1065 i9xx_lut_8(&lut[i]));
1068 static void i9xx_load_lut_10(struct intel_crtc *crtc,
1069 const struct drm_property_blob *blob)
1071 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1072 const struct drm_color_lut *lut = blob->data;
1073 int i, lut_size = drm_color_lut_size(blob);
1074 enum pipe pipe = crtc->pipe;
1076 for (i = 0; i < lut_size - 1; i++) {
1077 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),
1078 i9xx_lut_10_ldw(&lut[i]));
1079 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),
1080 i9xx_lut_10_udw(&lut[i]));
1084 static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
1086 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1087 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1089 switch (crtc_state->gamma_mode) {
1090 case GAMMA_MODE_MODE_8BIT:
1091 i9xx_load_lut_8(crtc, post_csc_lut);
1093 case GAMMA_MODE_MODE_10BIT:
1094 i9xx_load_lut_10(crtc, post_csc_lut);
1097 MISSING_CASE(crtc_state->gamma_mode);
1102 static void i965_load_lut_10p6(struct intel_crtc *crtc,
1103 const struct drm_property_blob *blob)
1105 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1106 const struct drm_color_lut *lut = blob->data;
1107 int i, lut_size = drm_color_lut_size(blob);
1108 enum pipe pipe = crtc->pipe;
1110 for (i = 0; i < lut_size - 1; i++) {
1111 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0),
1112 i965_lut_10p6_ldw(&lut[i]));
1113 intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1),
1114 i965_lut_10p6_udw(&lut[i]));
1117 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red);
1118 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green);
1119 intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue);
1122 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
1124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1125 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1127 switch (crtc_state->gamma_mode) {
1128 case GAMMA_MODE_MODE_8BIT:
1129 i9xx_load_lut_8(crtc, post_csc_lut);
1131 case GAMMA_MODE_MODE_10BIT:
1132 i965_load_lut_10p6(crtc, post_csc_lut);
1135 MISSING_CASE(crtc_state->gamma_mode);
1140 static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
1141 i915_reg_t reg, u32 val)
1143 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1145 if (crtc_state->dsb)
1146 intel_dsb_reg_write(crtc_state->dsb, reg, val);
1148 intel_de_write_fw(i915, reg, val);
1151 static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
1152 const struct drm_property_blob *blob)
1154 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1155 const struct drm_color_lut *lut;
1156 enum pipe pipe = crtc->pipe;
1164 for (i = 0; i < 256; i++)
1165 ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
1166 i9xx_lut_8(&lut[i]));
1169 static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
1170 const struct drm_property_blob *blob)
1172 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1173 const struct drm_color_lut *lut = blob->data;
1174 int i, lut_size = drm_color_lut_size(blob);
1175 enum pipe pipe = crtc->pipe;
1177 for (i = 0; i < lut_size; i++)
1178 ilk_lut_write(crtc_state, PREC_PALETTE(pipe, i),
1179 ilk_lut_10(&lut[i]));
1182 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
1184 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1185 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
1186 const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut;
1188 switch (crtc_state->gamma_mode) {
1189 case GAMMA_MODE_MODE_8BIT:
1190 ilk_load_lut_8(crtc_state, blob);
1192 case GAMMA_MODE_MODE_10BIT:
1193 ilk_load_lut_10(crtc_state, blob);
1196 MISSING_CASE(crtc_state->gamma_mode);
1201 static int ivb_lut_10_size(u32 prec_index)
1203 if (prec_index & PAL_PREC_SPLIT_MODE)
1210 * IVB/HSW Bspec / PAL_PREC_INDEX:
1211 * "Restriction : Index auto increment mode is not
1212 * supported and must not be enabled."
1214 static void ivb_load_lut_10(const struct intel_crtc_state *crtc_state,
1215 const struct drm_property_blob *blob,
1218 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1219 const struct drm_color_lut *lut = blob->data;
1220 int i, lut_size = drm_color_lut_size(blob);
1221 enum pipe pipe = crtc->pipe;
1223 for (i = 0; i < lut_size; i++) {
1224 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
1226 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),
1227 ilk_lut_10(&lut[i]));
1231 * Reset the index, otherwise it prevents the legacy palette to be
1234 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
1235 PAL_PREC_INDEX_VALUE(0));
1238 /* On BDW+ the index auto increment mode actually works */
1239 static void bdw_load_lut_10(const struct intel_crtc_state *crtc_state,
1240 const struct drm_property_blob *blob,
1243 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1244 const struct drm_color_lut *lut = blob->data;
1245 int i, lut_size = drm_color_lut_size(blob);
1246 enum pipe pipe = crtc->pipe;
1248 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
1250 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
1251 PAL_PREC_AUTO_INCREMENT |
1254 for (i = 0; i < lut_size; i++)
1255 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),
1256 ilk_lut_10(&lut[i]));
1259 * Reset the index, otherwise it prevents the legacy palette to be
1262 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
1263 PAL_PREC_INDEX_VALUE(0));
1266 static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state)
1268 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1269 enum pipe pipe = crtc->pipe;
1271 /* Program the max register to clamp values > 1.0. */
1272 ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
1273 ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
1274 ilk_lut_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
1277 static void glk_load_lut_ext2_max(const struct intel_crtc_state *crtc_state)
1279 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1280 enum pipe pipe = crtc->pipe;
1282 /* Program the max register to clamp values > 1.0. */
1283 ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
1284 ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
1285 ilk_lut_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
1288 static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
1290 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1291 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
1292 const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut;
1294 switch (crtc_state->gamma_mode) {
1295 case GAMMA_MODE_MODE_8BIT:
1296 ilk_load_lut_8(crtc_state, blob);
1298 case GAMMA_MODE_MODE_SPLIT:
1299 ivb_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE |
1300 PAL_PREC_INDEX_VALUE(0));
1301 ivb_load_lut_ext_max(crtc_state);
1302 ivb_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE |
1303 PAL_PREC_INDEX_VALUE(512));
1305 case GAMMA_MODE_MODE_10BIT:
1306 ivb_load_lut_10(crtc_state, blob,
1307 PAL_PREC_INDEX_VALUE(0));
1308 ivb_load_lut_ext_max(crtc_state);
1311 MISSING_CASE(crtc_state->gamma_mode);
1316 static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
1318 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1319 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
1320 const struct drm_property_blob *blob = post_csc_lut ?: pre_csc_lut;
1322 switch (crtc_state->gamma_mode) {
1323 case GAMMA_MODE_MODE_8BIT:
1324 ilk_load_lut_8(crtc_state, blob);
1326 case GAMMA_MODE_MODE_SPLIT:
1327 bdw_load_lut_10(crtc_state, pre_csc_lut, PAL_PREC_SPLIT_MODE |
1328 PAL_PREC_INDEX_VALUE(0));
1329 ivb_load_lut_ext_max(crtc_state);
1330 bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_SPLIT_MODE |
1331 PAL_PREC_INDEX_VALUE(512));
1333 case GAMMA_MODE_MODE_10BIT:
1334 bdw_load_lut_10(crtc_state, blob,
1335 PAL_PREC_INDEX_VALUE(0));
1336 ivb_load_lut_ext_max(crtc_state);
1339 MISSING_CASE(crtc_state->gamma_mode);
1344 static int glk_degamma_lut_size(struct drm_i915_private *i915)
1346 if (DISPLAY_VER(i915) >= 13)
1352 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
1353 const struct drm_property_blob *blob)
1355 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1356 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1357 const struct drm_color_lut *lut = blob->data;
1358 int i, lut_size = drm_color_lut_size(blob);
1359 enum pipe pipe = crtc->pipe;
1362 * When setting the auto-increment bit, the hardware seems to
1363 * ignore the index bits, so we need to reset it to index 0
1366 ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe),
1367 PRE_CSC_GAMC_INDEX_VALUE(0));
1368 ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe),
1369 PRE_CSC_GAMC_AUTO_INCREMENT |
1370 PRE_CSC_GAMC_INDEX_VALUE(0));
1372 for (i = 0; i < lut_size; i++) {
1374 * First lut_size entries represent range from 0 to 1.0
1375 * 3 additional lut entries will represent extended range
1376 * inputs 3.0 and 7.0 respectively, currently clamped
1377 * at 1.0. Since the precision is 16bit, the user
1378 * value can be directly filled to register.
1379 * The pipe degamma table in GLK+ onwards doesn't
1380 * support different values per channel, so this just
1381 * programs green value which will be equal to Red and
1382 * Blue into the lut registers.
1383 * ToDo: Extend to max 7.0. Enable 32 bit input value
1384 * as compared to just 16 to achieve this.
1386 ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe),
1390 /* Clamp values > 1.0. */
1391 while (i++ < glk_degamma_lut_size(i915))
1392 ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
1394 ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 0);
1397 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
1399 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
1400 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1403 glk_load_degamma_lut(crtc_state, pre_csc_lut);
1405 switch (crtc_state->gamma_mode) {
1406 case GAMMA_MODE_MODE_8BIT:
1407 ilk_load_lut_8(crtc_state, post_csc_lut);
1409 case GAMMA_MODE_MODE_10BIT:
1410 bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0));
1411 ivb_load_lut_ext_max(crtc_state);
1412 glk_load_lut_ext2_max(crtc_state);
1415 MISSING_CASE(crtc_state->gamma_mode);
1421 ivb_load_lut_max(const struct intel_crtc_state *crtc_state,
1422 const struct drm_color_lut *color)
1424 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1425 enum pipe pipe = crtc->pipe;
1427 /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
1428 ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
1429 ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
1430 ilk_lut_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
1434 icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
1436 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1437 const struct drm_property_blob *blob = crtc_state->post_csc_lut;
1438 const struct drm_color_lut *lut = blob->data;
1439 enum pipe pipe = crtc->pipe;
1443 * Program Super Fine segment (let's call it seg1)...
1445 * Super Fine segment's step is 1/(8 * 128 * 256) and it has
1446 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
1447 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
1449 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
1450 PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
1451 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
1452 PAL_PREC_AUTO_INCREMENT |
1453 PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
1455 for (i = 0; i < 9; i++) {
1456 const struct drm_color_lut *entry = &lut[i];
1458 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
1459 ilk_lut_12p4_ldw(entry));
1460 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe),
1461 ilk_lut_12p4_udw(entry));
1464 ilk_lut_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe),
1465 PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
1469 icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
1471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1472 const struct drm_property_blob *blob = crtc_state->post_csc_lut;
1473 const struct drm_color_lut *lut = blob->data;
1474 const struct drm_color_lut *entry;
1475 enum pipe pipe = crtc->pipe;
1479 * Program Fine segment (let's call it seg2)...
1481 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
1482 * ... 256/(128 * 256). So in order to program fine segment of LUT we
1483 * need to pick every 8th entry in the LUT, and program 256 indexes.
1485 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
1486 * seg2[0] being unused by the hardware.
1488 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
1489 PAL_PREC_INDEX_VALUE(0));
1490 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
1491 PAL_PREC_AUTO_INCREMENT |
1492 PAL_PREC_INDEX_VALUE(0));
1494 for (i = 1; i < 257; i++) {
1495 entry = &lut[i * 8];
1497 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),
1498 ilk_lut_12p4_ldw(entry));
1499 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),
1500 ilk_lut_12p4_udw(entry));
1504 * Program Coarse segment (let's call it seg3)...
1506 * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
1507 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
1508 * above, we need to pick every (8 * 128)th entry in LUT, and
1509 * program 256 of those.
1511 * Spec is not very clear about if entries seg3[0] and seg3[1] are
1512 * being used or not, but we still need to program these to advance
1515 for (i = 0; i < 256; i++) {
1516 entry = &lut[i * 8 * 128];
1518 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),
1519 ilk_lut_12p4_ldw(entry));
1520 ilk_lut_write(crtc_state, PREC_PAL_DATA(pipe),
1521 ilk_lut_12p4_udw(entry));
1524 ilk_lut_write(crtc_state, PREC_PAL_INDEX(pipe),
1525 PAL_PREC_INDEX_VALUE(0));
1527 /* The last entry in the LUT is to be programmed in GCMAX */
1528 entry = &lut[256 * 8 * 128];
1529 ivb_load_lut_max(crtc_state, entry);
1532 static void icl_load_luts(const struct intel_crtc_state *crtc_state)
1534 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
1535 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1538 glk_load_degamma_lut(crtc_state, pre_csc_lut);
1540 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
1541 case GAMMA_MODE_MODE_8BIT:
1542 ilk_load_lut_8(crtc_state, post_csc_lut);
1544 case GAMMA_MODE_MODE_12BIT_MULTI_SEG:
1545 icl_program_gamma_superfine_segment(crtc_state);
1546 icl_program_gamma_multi_segment(crtc_state);
1547 ivb_load_lut_ext_max(crtc_state);
1548 glk_load_lut_ext2_max(crtc_state);
1550 case GAMMA_MODE_MODE_10BIT:
1551 bdw_load_lut_10(crtc_state, post_csc_lut, PAL_PREC_INDEX_VALUE(0));
1552 ivb_load_lut_ext_max(crtc_state);
1553 glk_load_lut_ext2_max(crtc_state);
1556 MISSING_CASE(crtc_state->gamma_mode);
1560 if (crtc_state->dsb) {
1561 intel_dsb_finish(crtc_state->dsb);
1562 intel_dsb_commit(crtc_state->dsb, false);
1563 intel_dsb_wait(crtc_state->dsb);
1567 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
1569 return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 14)) |
1570 REG_FIELD_PREP(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, drm_color_lut_extract(color->blue, 14));
1573 static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
1575 return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 14));
1578 static void chv_cgm_degamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
1580 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, ldw), 14);
1581 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_BLUE_LDW_MASK, ldw), 14);
1582 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_DEGAMMA_RED_UDW_MASK, udw), 14);
1585 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
1586 const struct drm_property_blob *blob)
1588 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1589 const struct drm_color_lut *lut = blob->data;
1590 int i, lut_size = drm_color_lut_size(blob);
1591 enum pipe pipe = crtc->pipe;
1593 for (i = 0; i < lut_size; i++) {
1594 intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 0),
1595 chv_cgm_degamma_ldw(&lut[i]));
1596 intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 1),
1597 chv_cgm_degamma_udw(&lut[i]));
1601 static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color)
1603 return REG_FIELD_PREP(CGM_PIPE_GAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 10)) |
1604 REG_FIELD_PREP(CGM_PIPE_GAMMA_BLUE_LDW_MASK, drm_color_lut_extract(color->blue, 10));
1607 static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
1609 return REG_FIELD_PREP(CGM_PIPE_GAMMA_RED_UDW_MASK, drm_color_lut_extract(color->red, 10));
1612 static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
1614 entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_LDW_MASK, ldw), 10);
1615 entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_LDW_MASK, ldw), 10);
1616 entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_UDW_MASK, udw), 10);
1619 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
1620 const struct drm_property_blob *blob)
1622 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1623 const struct drm_color_lut *lut = blob->data;
1624 int i, lut_size = drm_color_lut_size(blob);
1625 enum pipe pipe = crtc->pipe;
1627 for (i = 0; i < lut_size; i++) {
1628 intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0),
1629 chv_cgm_gamma_ldw(&lut[i]));
1630 intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1),
1631 chv_cgm_gamma_udw(&lut[i]));
1635 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
1637 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1638 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1639 const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
1640 const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1642 if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
1643 chv_load_cgm_csc(crtc, &crtc_state->csc);
1645 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
1646 chv_load_cgm_degamma(crtc, pre_csc_lut);
1648 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
1649 chv_load_cgm_gamma(crtc, post_csc_lut);
1651 i965_load_luts(crtc_state);
1653 intel_de_write_fw(i915, CGM_PIPE_MODE(crtc->pipe),
1654 crtc_state->cgm_mode);
1657 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1659 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1661 i915->display.funcs.color->load_luts(crtc_state);
1664 void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
1666 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1668 if (i915->display.funcs.color->color_commit_noarm)
1669 i915->display.funcs.color->color_commit_noarm(crtc_state);
1672 void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
1674 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1676 i915->display.funcs.color->color_commit_arm(crtc_state);
1679 void intel_color_post_update(const struct intel_crtc_state *crtc_state)
1681 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1683 if (i915->display.funcs.color->color_post_update)
1684 i915->display.funcs.color->color_post_update(crtc_state);
1687 void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
1689 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1691 /* FIXME DSB has issues loading LUTs, disable it for now */
1694 if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
1697 crtc_state->dsb = intel_dsb_prepare(crtc, 1024);
1700 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
1702 if (!crtc_state->dsb)
1705 intel_dsb_cleanup(crtc_state->dsb);
1706 crtc_state->dsb = NULL;
1709 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1711 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1712 struct intel_atomic_state *state =
1713 to_intel_atomic_state(new_crtc_state->uapi.state);
1714 const struct intel_crtc_state *old_crtc_state =
1715 intel_atomic_get_old_crtc_state(state, crtc);
1717 return !old_crtc_state->post_csc_lut &&
1718 !old_crtc_state->pre_csc_lut;
1721 static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1723 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1724 struct intel_atomic_state *state =
1725 to_intel_atomic_state(new_crtc_state->uapi.state);
1726 const struct intel_crtc_state *old_crtc_state =
1727 intel_atomic_get_old_crtc_state(state, crtc);
1730 * CGM_PIPE_MODE is itself single buffered. We'd have to
1731 * somehow split it out from chv_load_luts() if we wanted
1732 * the ability to preload the CGM LUTs/CSC without tearing.
1734 if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
1737 return !old_crtc_state->post_csc_lut;
1740 int intel_color_check(struct intel_crtc_state *crtc_state)
1742 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1744 return i915->display.funcs.color->color_check(crtc_state);
1747 void intel_color_get_config(struct intel_crtc_state *crtc_state)
1749 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1751 i915->display.funcs.color->read_luts(crtc_state);
1753 if (i915->display.funcs.color->read_csc)
1754 i915->display.funcs.color->read_csc(crtc_state);
1757 bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
1758 const struct drm_property_blob *blob1,
1759 const struct drm_property_blob *blob2,
1760 bool is_pre_csc_lut)
1762 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1765 * FIXME c8_planes readout missing thus
1766 * .read_luts() doesn't read out post_csc_lut.
1768 if (!is_pre_csc_lut && crtc_state->c8_planes)
1771 return i915->display.funcs.color->lut_equal(crtc_state, blob1, blob2,
1775 static bool need_plane_update(struct intel_plane *plane,
1776 const struct intel_crtc_state *crtc_state)
1778 struct drm_i915_private *i915 = to_i915(plane->base.dev);
1781 * On pre-SKL the pipe gamma enable and pipe csc enable for
1782 * the pipe bottom color are configured via the primary plane.
1783 * We have to reconfigure that even if the plane is inactive.
1785 return crtc_state->active_planes & BIT(plane->id) ||
1786 (DISPLAY_VER(i915) < 9 &&
1787 plane->id == PLANE_PRIMARY);
1791 intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
1793 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1794 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1795 struct intel_atomic_state *state =
1796 to_intel_atomic_state(new_crtc_state->uapi.state);
1797 const struct intel_crtc_state *old_crtc_state =
1798 intel_atomic_get_old_crtc_state(state, crtc);
1799 struct intel_plane *plane;
1801 if (!new_crtc_state->hw.active ||
1802 intel_crtc_needs_modeset(new_crtc_state))
1805 if (new_crtc_state->gamma_enable == old_crtc_state->gamma_enable &&
1806 new_crtc_state->csc_enable == old_crtc_state->csc_enable)
1809 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
1810 struct intel_plane_state *plane_state;
1812 if (!need_plane_update(plane, new_crtc_state))
1815 plane_state = intel_atomic_get_plane_state(state, plane);
1816 if (IS_ERR(plane_state))
1817 return PTR_ERR(plane_state);
1819 new_crtc_state->update_planes |= BIT(plane->id);
1820 new_crtc_state->async_flip_planes = 0;
1821 new_crtc_state->do_async_flip = false;
1823 /* plane control register changes blocked by CxSR */
1825 new_crtc_state->disable_cxsr = true;
1831 static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)
1833 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1834 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1836 if (lut_is_legacy(gamma_lut))
1839 return DISPLAY_INFO(i915)->color.gamma_lut_tests;
1842 static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
1844 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1846 return DISPLAY_INFO(i915)->color.degamma_lut_tests;
1849 static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
1851 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1852 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1854 if (lut_is_legacy(gamma_lut))
1855 return LEGACY_LUT_LENGTH;
1857 return DISPLAY_INFO(i915)->color.gamma_lut_size;
1860 static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
1862 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1864 return DISPLAY_INFO(i915)->color.degamma_lut_size;
1867 static int check_lut_size(const struct drm_property_blob *lut, int expected)
1874 len = drm_color_lut_size(lut);
1875 if (len != expected) {
1876 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1884 static int _check_luts(const struct intel_crtc_state *crtc_state,
1885 u32 degamma_tests, u32 gamma_tests)
1887 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1888 const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
1889 const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
1890 int gamma_length, degamma_length;
1892 /* C8 relies on its palette being stored in the legacy LUT */
1893 if (crtc_state->c8_planes && !lut_is_legacy(crtc_state->hw.gamma_lut)) {
1894 drm_dbg_kms(&i915->drm,
1895 "C8 pixelformat requires the legacy LUT\n");
1899 degamma_length = intel_degamma_lut_size(crtc_state);
1900 gamma_length = intel_gamma_lut_size(crtc_state);
1902 if (check_lut_size(degamma_lut, degamma_length) ||
1903 check_lut_size(gamma_lut, gamma_length))
1906 if (drm_color_lut_check(degamma_lut, degamma_tests) ||
1907 drm_color_lut_check(gamma_lut, gamma_tests))
1913 static int check_luts(const struct intel_crtc_state *crtc_state)
1915 return _check_luts(crtc_state,
1916 intel_degamma_lut_tests(crtc_state),
1917 intel_gamma_lut_tests(crtc_state));
1920 static u32 i9xx_gamma_mode(struct intel_crtc_state *crtc_state)
1922 if (!crtc_state->gamma_enable ||
1923 lut_is_legacy(crtc_state->hw.gamma_lut))
1924 return GAMMA_MODE_MODE_8BIT;
1926 return GAMMA_MODE_MODE_10BIT;
1929 static int i9xx_lut_10_diff(u16 a, u16 b)
1931 return drm_color_lut_extract(a, 10) -
1932 drm_color_lut_extract(b, 10);
1935 static int i9xx_check_lut_10(struct drm_i915_private *dev_priv,
1936 const struct drm_property_blob *blob)
1938 const struct drm_color_lut *lut = blob->data;
1939 int lut_size = drm_color_lut_size(blob);
1940 const struct drm_color_lut *a = &lut[lut_size - 2];
1941 const struct drm_color_lut *b = &lut[lut_size - 1];
1943 if (i9xx_lut_10_diff(b->red, a->red) > 0x7f ||
1944 i9xx_lut_10_diff(b->green, a->green) > 0x7f ||
1945 i9xx_lut_10_diff(b->blue, a->blue) > 0x7f) {
1946 drm_dbg_kms(&dev_priv->drm, "Last gamma LUT entry exceeds max slope\n");
1953 void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
1955 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1957 /* make sure {pre,post}_csc_lut were correctly assigned */
1958 if (DISPLAY_VER(i915) >= 11 || HAS_GMCH(i915)) {
1959 drm_WARN_ON(&i915->drm,
1960 crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut);
1961 drm_WARN_ON(&i915->drm,
1962 crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
1963 } else if (DISPLAY_VER(i915) == 10) {
1964 drm_WARN_ON(&i915->drm,
1965 crtc_state->post_csc_lut == crtc_state->hw.gamma_lut &&
1966 crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
1967 crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut);
1968 drm_WARN_ON(&i915->drm,
1969 !ilk_lut_limited_range(crtc_state) &&
1970 crtc_state->post_csc_lut != NULL &&
1971 crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
1972 } else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
1973 drm_WARN_ON(&i915->drm,
1974 crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
1975 crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
1976 drm_WARN_ON(&i915->drm,
1977 !ilk_lut_limited_range(crtc_state) &&
1978 crtc_state->post_csc_lut != crtc_state->hw.degamma_lut &&
1979 crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
1983 static void intel_assign_luts(struct intel_crtc_state *crtc_state)
1985 drm_property_replace_blob(&crtc_state->pre_csc_lut,
1986 crtc_state->hw.degamma_lut);
1987 drm_property_replace_blob(&crtc_state->post_csc_lut,
1988 crtc_state->hw.gamma_lut);
1991 static int i9xx_color_check(struct intel_crtc_state *crtc_state)
1993 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1996 ret = check_luts(crtc_state);
2000 crtc_state->gamma_enable =
2001 crtc_state->hw.gamma_lut &&
2002 !crtc_state->c8_planes;
2004 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
2006 if (DISPLAY_VER(i915) < 4 &&
2007 crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT) {
2008 ret = i9xx_check_lut_10(i915, crtc_state->hw.gamma_lut);
2013 ret = intel_color_add_affected_planes(crtc_state);
2017 intel_assign_luts(crtc_state);
2019 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
2024 static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
2028 if (crtc_state->hw.degamma_lut)
2029 cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
2030 if (crtc_state->hw.ctm)
2031 cgm_mode |= CGM_PIPE_MODE_CSC;
2032 if (crtc_state->hw.gamma_lut &&
2033 !lut_is_legacy(crtc_state->hw.gamma_lut))
2034 cgm_mode |= CGM_PIPE_MODE_GAMMA;
2040 * CHV color pipeline:
2041 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
2042 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
2044 * We always bypass the WGC csc and use the CGM csc
2045 * instead since it has degamma and better precision.
2047 static int chv_color_check(struct intel_crtc_state *crtc_state)
2051 ret = check_luts(crtc_state);
2056 * Pipe gamma will be used only for the legacy LUT.
2057 * Otherwise we bypass it and use the CGM gamma instead.
2059 crtc_state->gamma_enable =
2060 lut_is_legacy(crtc_state->hw.gamma_lut) &&
2061 !crtc_state->c8_planes;
2063 crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
2065 crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
2067 ret = intel_color_add_affected_planes(crtc_state);
2071 intel_assign_luts(crtc_state);
2073 chv_assign_csc(crtc_state);
2075 crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
2080 static bool ilk_gamma_enable(const struct intel_crtc_state *crtc_state)
2082 return (crtc_state->hw.gamma_lut ||
2083 crtc_state->hw.degamma_lut) &&
2084 !crtc_state->c8_planes;
2087 static bool ilk_csc_enable(const struct intel_crtc_state *crtc_state)
2089 return crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
2090 ilk_csc_limited_range(crtc_state) ||
2094 static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
2096 if (!crtc_state->gamma_enable ||
2097 lut_is_legacy(crtc_state->hw.gamma_lut))
2098 return GAMMA_MODE_MODE_8BIT;
2100 return GAMMA_MODE_MODE_10BIT;
2103 static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
2106 * CSC comes after the LUT in RGB->YCbCr mode.
2107 * RGB->YCbCr needs the limited range offsets added to
2108 * the output. RGB limited range output is handled by
2109 * the hw automagically elsewhere.
2111 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2112 return CSC_BLACK_SCREEN_OFFSET;
2114 if (crtc_state->hw.degamma_lut)
2115 return CSC_MODE_YUV_TO_RGB;
2117 return CSC_MODE_YUV_TO_RGB |
2118 CSC_POSITION_BEFORE_GAMMA;
2121 static int ilk_assign_luts(struct intel_crtc_state *crtc_state)
2123 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2125 if (ilk_lut_limited_range(crtc_state)) {
2126 struct drm_property_blob *gamma_lut;
2128 gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
2129 drm_color_lut_size(crtc_state->hw.gamma_lut),
2131 if (IS_ERR(gamma_lut))
2132 return PTR_ERR(gamma_lut);
2134 drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);
2136 drm_property_blob_put(gamma_lut);
2138 drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut);
2143 if (crtc_state->hw.degamma_lut ||
2144 crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) {
2145 drm_property_replace_blob(&crtc_state->pre_csc_lut,
2146 crtc_state->hw.degamma_lut);
2147 drm_property_replace_blob(&crtc_state->post_csc_lut,
2148 crtc_state->hw.gamma_lut);
2150 drm_property_replace_blob(&crtc_state->pre_csc_lut,
2151 crtc_state->hw.gamma_lut);
2152 drm_property_replace_blob(&crtc_state->post_csc_lut,
2159 static int ilk_color_check(struct intel_crtc_state *crtc_state)
2161 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2164 ret = check_luts(crtc_state);
2168 if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
2169 drm_dbg_kms(&i915->drm,
2170 "Degamma and gamma together are not possible\n");
2174 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2175 crtc_state->hw.ctm) {
2176 drm_dbg_kms(&i915->drm,
2177 "YCbCr and CTM together are not possible\n");
2181 crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);
2183 crtc_state->csc_enable = ilk_csc_enable(crtc_state);
2185 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
2187 crtc_state->csc_mode = ilk_csc_mode(crtc_state);
2189 ret = intel_color_add_affected_planes(crtc_state);
2193 ret = ilk_assign_luts(crtc_state);
2197 ilk_assign_csc(crtc_state);
2199 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
2204 static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state)
2206 if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut)
2207 return GAMMA_MODE_MODE_SPLIT;
2209 return ilk_gamma_mode(crtc_state);
2212 static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
2214 bool limited_color_range = ilk_csc_limited_range(crtc_state);
2217 * CSC comes after the LUT in degamma, RGB->YCbCr,
2218 * and RGB full->limited range mode.
2220 if (crtc_state->hw.degamma_lut ||
2221 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
2222 limited_color_range)
2225 return CSC_POSITION_BEFORE_GAMMA;
2228 static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
2230 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2231 struct drm_property_blob *degamma_lut, *gamma_lut;
2233 if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT)
2234 return ilk_assign_luts(crtc_state);
2236 drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
2237 drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
2239 degamma_lut = create_resized_lut(i915, crtc_state->hw.degamma_lut, 512,
2241 if (IS_ERR(degamma_lut))
2242 return PTR_ERR(degamma_lut);
2244 gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 512,
2245 ilk_lut_limited_range(crtc_state));
2246 if (IS_ERR(gamma_lut)) {
2247 drm_property_blob_put(degamma_lut);
2248 return PTR_ERR(gamma_lut);
2251 drm_property_replace_blob(&crtc_state->pre_csc_lut, degamma_lut);
2252 drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);
2254 drm_property_blob_put(degamma_lut);
2255 drm_property_blob_put(gamma_lut);
2260 static int ivb_color_check(struct intel_crtc_state *crtc_state)
2262 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2265 ret = check_luts(crtc_state);
2269 if (crtc_state->c8_planes && crtc_state->hw.degamma_lut) {
2270 drm_dbg_kms(&i915->drm,
2271 "C8 pixelformat and degamma together are not possible\n");
2275 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2276 crtc_state->hw.ctm) {
2277 drm_dbg_kms(&i915->drm,
2278 "YCbCr and CTM together are not possible\n");
2282 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2283 crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
2284 drm_dbg_kms(&i915->drm,
2285 "YCbCr and degamma+gamma together are not possible\n");
2289 crtc_state->gamma_enable = ilk_gamma_enable(crtc_state);
2291 crtc_state->csc_enable = ilk_csc_enable(crtc_state);
2293 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
2295 crtc_state->csc_mode = ivb_csc_mode(crtc_state);
2297 ret = intel_color_add_affected_planes(crtc_state);
2301 ret = ivb_assign_luts(crtc_state);
2305 ilk_assign_csc(crtc_state);
2307 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
2312 static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state)
2314 if (!crtc_state->gamma_enable ||
2315 lut_is_legacy(crtc_state->hw.gamma_lut))
2316 return GAMMA_MODE_MODE_8BIT;
2318 return GAMMA_MODE_MODE_10BIT;
2321 static bool glk_use_pre_csc_lut_for_gamma(const struct intel_crtc_state *crtc_state)
2323 return crtc_state->hw.gamma_lut &&
2324 !crtc_state->c8_planes &&
2325 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
2328 static int glk_assign_luts(struct intel_crtc_state *crtc_state)
2330 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2332 if (glk_use_pre_csc_lut_for_gamma(crtc_state)) {
2333 struct drm_property_blob *gamma_lut;
2335 gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
2336 DISPLAY_INFO(i915)->color.degamma_lut_size,
2338 if (IS_ERR(gamma_lut))
2339 return PTR_ERR(gamma_lut);
2341 drm_property_replace_blob(&crtc_state->pre_csc_lut, gamma_lut);
2342 drm_property_replace_blob(&crtc_state->post_csc_lut, NULL);
2344 drm_property_blob_put(gamma_lut);
2349 if (ilk_lut_limited_range(crtc_state)) {
2350 struct drm_property_blob *gamma_lut;
2352 gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
2353 drm_color_lut_size(crtc_state->hw.gamma_lut),
2355 if (IS_ERR(gamma_lut))
2356 return PTR_ERR(gamma_lut);
2358 drm_property_replace_blob(&crtc_state->post_csc_lut, gamma_lut);
2360 drm_property_blob_put(gamma_lut);
2362 drm_property_replace_blob(&crtc_state->post_csc_lut, crtc_state->hw.gamma_lut);
2365 drm_property_replace_blob(&crtc_state->pre_csc_lut, crtc_state->hw.degamma_lut);
2368 * On GLK+ both pipe CSC and degamma LUT are controlled
2369 * by csc_enable. Hence for the cases where the CSC is
2370 * needed but degamma LUT is not we need to load a
2371 * linear degamma LUT.
2373 if (crtc_state->csc_enable && !crtc_state->pre_csc_lut)
2374 drm_property_replace_blob(&crtc_state->pre_csc_lut,
2375 i915->display.color.glk_linear_degamma_lut);
2380 static int glk_check_luts(const struct intel_crtc_state *crtc_state)
2382 u32 degamma_tests = intel_degamma_lut_tests(crtc_state);
2383 u32 gamma_tests = intel_gamma_lut_tests(crtc_state);
2385 if (glk_use_pre_csc_lut_for_gamma(crtc_state))
2386 gamma_tests |= degamma_tests;
2388 return _check_luts(crtc_state, degamma_tests, gamma_tests);
2391 static int glk_color_check(struct intel_crtc_state *crtc_state)
2393 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2396 ret = glk_check_luts(crtc_state);
2400 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2401 crtc_state->hw.ctm) {
2402 drm_dbg_kms(&i915->drm,
2403 "YCbCr and CTM together are not possible\n");
2407 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2408 crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
2409 drm_dbg_kms(&i915->drm,
2410 "YCbCr and degamma+gamma together are not possible\n");
2414 crtc_state->gamma_enable =
2415 !glk_use_pre_csc_lut_for_gamma(crtc_state) &&
2416 crtc_state->hw.gamma_lut &&
2417 !crtc_state->c8_planes;
2419 /* On GLK+ degamma LUT is controlled by csc_enable */
2420 crtc_state->csc_enable =
2421 glk_use_pre_csc_lut_for_gamma(crtc_state) ||
2422 crtc_state->hw.degamma_lut ||
2423 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
2424 crtc_state->hw.ctm || ilk_csc_limited_range(crtc_state);
2426 crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
2428 crtc_state->csc_mode = 0;
2430 ret = intel_color_add_affected_planes(crtc_state);
2434 ret = glk_assign_luts(crtc_state);
2438 ilk_assign_csc(crtc_state);
2440 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
2445 static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
2447 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2448 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2451 if (crtc_state->hw.degamma_lut)
2452 gamma_mode |= PRE_CSC_GAMMA_ENABLE;
2454 if (crtc_state->hw.gamma_lut &&
2455 !crtc_state->c8_planes)
2456 gamma_mode |= POST_CSC_GAMMA_ENABLE;
2458 if (!crtc_state->hw.gamma_lut ||
2459 lut_is_legacy(crtc_state->hw.gamma_lut))
2460 gamma_mode |= GAMMA_MODE_MODE_8BIT;
2462 * Enable 10bit gamma for D13
2463 * ToDo: Extend to Logarithmic Gamma once the new UAPI
2464 * is accepted and implemented by a userspace consumer
2466 else if (DISPLAY_VER(i915) >= 13)
2467 gamma_mode |= GAMMA_MODE_MODE_10BIT;
2469 gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEG;
2474 static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
2478 if (crtc_state->hw.ctm)
2479 csc_mode |= ICL_CSC_ENABLE;
2481 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
2482 crtc_state->limited_color_range)
2483 csc_mode |= ICL_OUTPUT_CSC_ENABLE;
2488 static int icl_color_check(struct intel_crtc_state *crtc_state)
2492 ret = check_luts(crtc_state);
2496 crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
2498 crtc_state->csc_mode = icl_csc_mode(crtc_state);
2500 intel_assign_luts(crtc_state);
2502 icl_assign_csc(crtc_state);
2504 crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
2509 static int i9xx_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2511 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
2514 switch (crtc_state->gamma_mode) {
2515 case GAMMA_MODE_MODE_8BIT:
2517 case GAMMA_MODE_MODE_10BIT:
2520 MISSING_CASE(crtc_state->gamma_mode);
2525 static int i9xx_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2530 static int i965_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2532 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
2535 switch (crtc_state->gamma_mode) {
2536 case GAMMA_MODE_MODE_8BIT:
2538 case GAMMA_MODE_MODE_10BIT:
2541 MISSING_CASE(crtc_state->gamma_mode);
2546 static int ilk_gamma_mode_precision(u32 gamma_mode)
2548 switch (gamma_mode) {
2549 case GAMMA_MODE_MODE_8BIT:
2551 case GAMMA_MODE_MODE_10BIT:
2554 MISSING_CASE(gamma_mode);
2559 static bool ilk_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
2561 if (crtc_state->c8_planes)
2564 return crtc_state->gamma_enable &&
2565 (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) != 0;
2568 static bool ilk_has_pre_csc_lut(const struct intel_crtc_state *crtc_state)
2570 return crtc_state->gamma_enable &&
2571 (crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0;
2574 static int ilk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2576 if (!ilk_has_post_csc_lut(crtc_state))
2579 return ilk_gamma_mode_precision(crtc_state->gamma_mode);
2582 static int ilk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2584 if (!ilk_has_pre_csc_lut(crtc_state))
2587 return ilk_gamma_mode_precision(crtc_state->gamma_mode);
2590 static int ivb_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2592 if (crtc_state->gamma_enable &&
2593 crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2596 return ilk_post_csc_lut_precision(crtc_state);
2599 static int ivb_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2601 if (crtc_state->gamma_enable &&
2602 crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
2605 return ilk_pre_csc_lut_precision(crtc_state);
2608 static int chv_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2610 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
2613 return i965_post_csc_lut_precision(crtc_state);
2616 static int chv_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2618 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
2624 static int glk_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2626 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
2629 return ilk_gamma_mode_precision(crtc_state->gamma_mode);
2632 static int glk_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2634 if (!crtc_state->csc_enable)
2640 static bool icl_has_post_csc_lut(const struct intel_crtc_state *crtc_state)
2642 if (crtc_state->c8_planes)
2645 return crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE;
2648 static bool icl_has_pre_csc_lut(const struct intel_crtc_state *crtc_state)
2650 return crtc_state->gamma_mode & PRE_CSC_GAMMA_ENABLE;
2653 static int icl_post_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2655 if (!icl_has_post_csc_lut(crtc_state))
2658 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
2659 case GAMMA_MODE_MODE_8BIT:
2661 case GAMMA_MODE_MODE_10BIT:
2663 case GAMMA_MODE_MODE_12BIT_MULTI_SEG:
2666 MISSING_CASE(crtc_state->gamma_mode);
2671 static int icl_pre_csc_lut_precision(const struct intel_crtc_state *crtc_state)
2673 if (!icl_has_pre_csc_lut(crtc_state))
2679 static bool err_check(struct drm_color_lut *lut1,
2680 struct drm_color_lut *lut2, u32 err)
2682 return ((abs((long)lut2->red - lut1->red)) <= err) &&
2683 ((abs((long)lut2->blue - lut1->blue)) <= err) &&
2684 ((abs((long)lut2->green - lut1->green)) <= err);
2687 static bool intel_lut_entries_equal(struct drm_color_lut *lut1,
2688 struct drm_color_lut *lut2,
2689 int lut_size, u32 err)
2693 for (i = 0; i < lut_size; i++) {
2694 if (!err_check(&lut1[i], &lut2[i], err))
2701 static bool intel_lut_equal(const struct drm_property_blob *blob1,
2702 const struct drm_property_blob *blob2,
2703 int check_size, int precision)
2705 struct drm_color_lut *lut1, *lut2;
2706 int lut_size1, lut_size2;
2709 if (!blob1 != !blob2)
2712 if (!blob1 != !precision)
2718 lut_size1 = drm_color_lut_size(blob1);
2719 lut_size2 = drm_color_lut_size(blob2);
2721 if (lut_size1 != lut_size2)
2724 if (check_size > lut_size1)
2730 err = 0xffff >> precision;
2733 check_size = lut_size1;
2735 return intel_lut_entries_equal(lut1, lut2, check_size, err);
2738 static bool i9xx_lut_equal(const struct intel_crtc_state *crtc_state,
2739 const struct drm_property_blob *blob1,
2740 const struct drm_property_blob *blob2,
2741 bool is_pre_csc_lut)
2746 return intel_lut_equal(blob1, blob2, 0,
2747 i9xx_pre_csc_lut_precision(crtc_state));
2749 /* 10bit mode last entry is implicit, just skip it */
2750 if (crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT)
2753 return intel_lut_equal(blob1, blob2, check_size,
2754 i9xx_post_csc_lut_precision(crtc_state));
2757 static bool i965_lut_equal(const struct intel_crtc_state *crtc_state,
2758 const struct drm_property_blob *blob1,
2759 const struct drm_property_blob *blob2,
2760 bool is_pre_csc_lut)
2763 return intel_lut_equal(blob1, blob2, 0,
2764 i9xx_pre_csc_lut_precision(crtc_state));
2766 return intel_lut_equal(blob1, blob2, 0,
2767 i965_post_csc_lut_precision(crtc_state));
2770 static bool chv_lut_equal(const struct intel_crtc_state *crtc_state,
2771 const struct drm_property_blob *blob1,
2772 const struct drm_property_blob *blob2,
2773 bool is_pre_csc_lut)
2776 return intel_lut_equal(blob1, blob2, 0,
2777 chv_pre_csc_lut_precision(crtc_state));
2779 return intel_lut_equal(blob1, blob2, 0,
2780 chv_post_csc_lut_precision(crtc_state));
2783 static bool ilk_lut_equal(const struct intel_crtc_state *crtc_state,
2784 const struct drm_property_blob *blob1,
2785 const struct drm_property_blob *blob2,
2786 bool is_pre_csc_lut)
2789 return intel_lut_equal(blob1, blob2, 0,
2790 ilk_pre_csc_lut_precision(crtc_state));
2792 return intel_lut_equal(blob1, blob2, 0,
2793 ilk_post_csc_lut_precision(crtc_state));
2796 static bool ivb_lut_equal(const struct intel_crtc_state *crtc_state,
2797 const struct drm_property_blob *blob1,
2798 const struct drm_property_blob *blob2,
2799 bool is_pre_csc_lut)
2802 return intel_lut_equal(blob1, blob2, 0,
2803 ivb_pre_csc_lut_precision(crtc_state));
2805 return intel_lut_equal(blob1, blob2, 0,
2806 ivb_post_csc_lut_precision(crtc_state));
2809 static bool glk_lut_equal(const struct intel_crtc_state *crtc_state,
2810 const struct drm_property_blob *blob1,
2811 const struct drm_property_blob *blob2,
2812 bool is_pre_csc_lut)
2815 return intel_lut_equal(blob1, blob2, 0,
2816 glk_pre_csc_lut_precision(crtc_state));
2818 return intel_lut_equal(blob1, blob2, 0,
2819 glk_post_csc_lut_precision(crtc_state));
2822 static bool icl_lut_equal(const struct intel_crtc_state *crtc_state,
2823 const struct drm_property_blob *blob1,
2824 const struct drm_property_blob *blob2,
2825 bool is_pre_csc_lut)
2830 return intel_lut_equal(blob1, blob2, 0,
2831 icl_pre_csc_lut_precision(crtc_state));
2833 /* hw readout broken except for the super fine segment :( */
2834 if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
2835 GAMMA_MODE_MODE_12BIT_MULTI_SEG)
2838 return intel_lut_equal(blob1, blob2, check_size,
2839 icl_post_csc_lut_precision(crtc_state));
2842 static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
2844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2845 enum pipe pipe = crtc->pipe;
2846 struct drm_property_blob *blob;
2847 struct drm_color_lut *lut;
2850 blob = drm_property_create_blob(&dev_priv->drm,
2851 sizeof(lut[0]) * LEGACY_LUT_LENGTH,
2858 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
2859 u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i));
2861 i9xx_lut_8_pack(&lut[i], val);
2867 static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
2869 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2870 u32 lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;
2871 enum pipe pipe = crtc->pipe;
2872 struct drm_property_blob *blob;
2873 struct drm_color_lut *lut;
2877 blob = drm_property_create_blob(&dev_priv->drm,
2878 lut_size * sizeof(lut[0]), NULL);
2884 for (i = 0; i < lut_size - 1; i++) {
2885 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));
2886 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));
2888 i9xx_lut_10_pack(&lut[i], ldw, udw);
2891 i9xx_lut_10_pack_slope(&lut[i], ldw, udw);
2896 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
2898 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2900 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
2903 switch (crtc_state->gamma_mode) {
2904 case GAMMA_MODE_MODE_8BIT:
2905 crtc_state->post_csc_lut = i9xx_read_lut_8(crtc);
2907 case GAMMA_MODE_MODE_10BIT:
2908 crtc_state->post_csc_lut = i9xx_read_lut_10(crtc);
2911 MISSING_CASE(crtc_state->gamma_mode);
2916 static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
2918 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2919 int i, lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;
2920 enum pipe pipe = crtc->pipe;
2921 struct drm_property_blob *blob;
2922 struct drm_color_lut *lut;
2924 blob = drm_property_create_blob(&dev_priv->drm,
2925 sizeof(lut[0]) * lut_size,
2932 for (i = 0; i < lut_size - 1; i++) {
2933 u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0));
2934 u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1));
2936 i965_lut_10p6_pack(&lut[i], ldw, udw);
2939 lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 0)));
2940 lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 1)));
2941 lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 2)));
2946 static void i965_read_luts(struct intel_crtc_state *crtc_state)
2948 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2950 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
2953 switch (crtc_state->gamma_mode) {
2954 case GAMMA_MODE_MODE_8BIT:
2955 crtc_state->post_csc_lut = i9xx_read_lut_8(crtc);
2957 case GAMMA_MODE_MODE_10BIT:
2958 crtc_state->post_csc_lut = i965_read_lut_10p6(crtc);
2961 MISSING_CASE(crtc_state->gamma_mode);
2966 static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
2968 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2969 int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;
2970 enum pipe pipe = crtc->pipe;
2971 struct drm_property_blob *blob;
2972 struct drm_color_lut *lut;
2974 blob = drm_property_create_blob(&dev_priv->drm,
2975 sizeof(lut[0]) * lut_size,
2982 for (i = 0; i < lut_size; i++) {
2983 u32 ldw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0));
2984 u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1));
2986 chv_cgm_degamma_pack(&lut[i], ldw, udw);
2992 static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
2994 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2995 int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
2996 enum pipe pipe = crtc->pipe;
2997 struct drm_property_blob *blob;
2998 struct drm_color_lut *lut;
3000 blob = drm_property_create_blob(&i915->drm,
3001 sizeof(lut[0]) * lut_size,
3008 for (i = 0; i < lut_size; i++) {
3009 u32 ldw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0));
3010 u32 udw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1));
3012 chv_cgm_gamma_pack(&lut[i], ldw, udw);
3018 static void chv_read_luts(struct intel_crtc_state *crtc_state)
3020 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3022 if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
3023 crtc_state->pre_csc_lut = chv_read_cgm_degamma(crtc);
3025 if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
3026 crtc_state->post_csc_lut = chv_read_cgm_gamma(crtc);
3028 i965_read_luts(crtc_state);
3031 static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
3033 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3034 enum pipe pipe = crtc->pipe;
3035 struct drm_property_blob *blob;
3036 struct drm_color_lut *lut;
3039 blob = drm_property_create_blob(&i915->drm,
3040 sizeof(lut[0]) * LEGACY_LUT_LENGTH,
3047 for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
3048 u32 val = intel_de_read_fw(i915, LGC_PALETTE(pipe, i));
3050 i9xx_lut_8_pack(&lut[i], val);
3056 static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
3058 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3059 int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
3060 enum pipe pipe = crtc->pipe;
3061 struct drm_property_blob *blob;
3062 struct drm_color_lut *lut;
3064 blob = drm_property_create_blob(&i915->drm,
3065 sizeof(lut[0]) * lut_size,
3072 for (i = 0; i < lut_size; i++) {
3073 u32 val = intel_de_read_fw(i915, PREC_PALETTE(pipe, i));
3075 ilk_lut_10_pack(&lut[i], val);
3081 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
3083 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3084 struct drm_property_blob **blob =
3085 ilk_has_post_csc_lut(crtc_state) ?
3086 &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;
3088 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
3091 switch (crtc_state->gamma_mode) {
3092 case GAMMA_MODE_MODE_8BIT:
3093 *blob = ilk_read_lut_8(crtc);
3095 case GAMMA_MODE_MODE_10BIT:
3096 *blob = ilk_read_lut_10(crtc);
3099 MISSING_CASE(crtc_state->gamma_mode);
3105 * IVB/HSW Bspec / PAL_PREC_INDEX:
3106 * "Restriction : Index auto increment mode is not
3107 * supported and must not be enabled."
3109 static struct drm_property_blob *ivb_read_lut_10(struct intel_crtc *crtc,
3112 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3113 int i, lut_size = ivb_lut_10_size(prec_index);
3114 enum pipe pipe = crtc->pipe;
3115 struct drm_property_blob *blob;
3116 struct drm_color_lut *lut;
3118 blob = drm_property_create_blob(&dev_priv->drm,
3119 sizeof(lut[0]) * lut_size,
3126 for (i = 0; i < lut_size; i++) {
3129 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe),
3131 val = intel_de_read_fw(dev_priv, PREC_PAL_DATA(pipe));
3133 ilk_lut_10_pack(&lut[i], val);
3136 intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe),
3137 PAL_PREC_INDEX_VALUE(0));
3142 static void ivb_read_luts(struct intel_crtc_state *crtc_state)
3144 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3145 struct drm_property_blob **blob =
3146 ilk_has_post_csc_lut(crtc_state) ?
3147 &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;
3149 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
3152 switch (crtc_state->gamma_mode) {
3153 case GAMMA_MODE_MODE_8BIT:
3154 *blob = ilk_read_lut_8(crtc);
3156 case GAMMA_MODE_MODE_SPLIT:
3157 crtc_state->pre_csc_lut =
3158 ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE |
3159 PAL_PREC_INDEX_VALUE(0));
3160 crtc_state->post_csc_lut =
3161 ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE |
3162 PAL_PREC_INDEX_VALUE(512));
3164 case GAMMA_MODE_MODE_10BIT:
3165 *blob = ivb_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
3168 MISSING_CASE(crtc_state->gamma_mode);
3173 /* On BDW+ the index auto increment mode actually works */
3174 static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
3177 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3178 int i, lut_size = ivb_lut_10_size(prec_index);
3179 enum pipe pipe = crtc->pipe;
3180 struct drm_property_blob *blob;
3181 struct drm_color_lut *lut;
3183 blob = drm_property_create_blob(&i915->drm,
3184 sizeof(lut[0]) * lut_size,
3191 intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
3193 intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
3194 PAL_PREC_AUTO_INCREMENT |
3197 for (i = 0; i < lut_size; i++) {
3198 u32 val = intel_de_read_fw(i915, PREC_PAL_DATA(pipe));
3200 ilk_lut_10_pack(&lut[i], val);
3203 intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
3204 PAL_PREC_INDEX_VALUE(0));
3209 static void bdw_read_luts(struct intel_crtc_state *crtc_state)
3211 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3212 struct drm_property_blob **blob =
3213 ilk_has_post_csc_lut(crtc_state) ?
3214 &crtc_state->post_csc_lut : &crtc_state->pre_csc_lut;
3216 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
3219 switch (crtc_state->gamma_mode) {
3220 case GAMMA_MODE_MODE_8BIT:
3221 *blob = ilk_read_lut_8(crtc);
3223 case GAMMA_MODE_MODE_SPLIT:
3224 crtc_state->pre_csc_lut =
3225 bdw_read_lut_10(crtc, PAL_PREC_SPLIT_MODE |
3226 PAL_PREC_INDEX_VALUE(0));
3227 crtc_state->post_csc_lut =
3228 bdw_read_lut_10(crtc, PAL_PREC_SPLIT_MODE |
3229 PAL_PREC_INDEX_VALUE(512));
3231 case GAMMA_MODE_MODE_10BIT:
3232 *blob = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
3235 MISSING_CASE(crtc_state->gamma_mode);
3240 static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)
3242 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3243 int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;
3244 enum pipe pipe = crtc->pipe;
3245 struct drm_property_blob *blob;
3246 struct drm_color_lut *lut;
3248 blob = drm_property_create_blob(&dev_priv->drm,
3249 sizeof(lut[0]) * lut_size,
3257 * When setting the auto-increment bit, the hardware seems to
3258 * ignore the index bits, so we need to reset it to index 0
3261 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
3262 PRE_CSC_GAMC_INDEX_VALUE(0));
3263 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
3264 PRE_CSC_GAMC_AUTO_INCREMENT |
3265 PRE_CSC_GAMC_INDEX_VALUE(0));
3267 for (i = 0; i < lut_size; i++) {
3268 u32 val = intel_de_read_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe));
3275 intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
3276 PRE_CSC_GAMC_INDEX_VALUE(0));
3281 static void glk_read_luts(struct intel_crtc_state *crtc_state)
3283 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3285 if (crtc_state->csc_enable)
3286 crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc);
3288 if (!crtc_state->gamma_enable && !crtc_state->c8_planes)
3291 switch (crtc_state->gamma_mode) {
3292 case GAMMA_MODE_MODE_8BIT:
3293 crtc_state->post_csc_lut = ilk_read_lut_8(crtc);
3295 case GAMMA_MODE_MODE_10BIT:
3296 crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
3299 MISSING_CASE(crtc_state->gamma_mode);
3304 static struct drm_property_blob *
3305 icl_read_lut_multi_segment(struct intel_crtc *crtc)
3307 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3308 int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
3309 enum pipe pipe = crtc->pipe;
3310 struct drm_property_blob *blob;
3311 struct drm_color_lut *lut;
3313 blob = drm_property_create_blob(&i915->drm,
3314 sizeof(lut[0]) * lut_size,
3321 intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe),
3322 PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
3323 intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe),
3324 PAL_PREC_MULTI_SEG_AUTO_INCREMENT |
3325 PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
3327 for (i = 0; i < 9; i++) {
3328 u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
3329 u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
3331 ilk_lut_12p4_pack(&lut[i], ldw, udw);
3334 intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe),
3335 PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
3338 * FIXME readouts from PAL_PREC_DATA register aren't giving
3339 * correct values in the case of fine and coarse segments.
3340 * Restricting readouts only for super fine segment as of now.
3346 static void icl_read_luts(struct intel_crtc_state *crtc_state)
3348 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3350 if (icl_has_pre_csc_lut(crtc_state))
3351 crtc_state->pre_csc_lut = glk_read_degamma_lut(crtc);
3353 if (!icl_has_post_csc_lut(crtc_state))
3356 switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
3357 case GAMMA_MODE_MODE_8BIT:
3358 crtc_state->post_csc_lut = ilk_read_lut_8(crtc);
3360 case GAMMA_MODE_MODE_10BIT:
3361 crtc_state->post_csc_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
3363 case GAMMA_MODE_MODE_12BIT_MULTI_SEG:
3364 crtc_state->post_csc_lut = icl_read_lut_multi_segment(crtc);
3367 MISSING_CASE(crtc_state->gamma_mode);
3372 static const struct intel_color_funcs chv_color_funcs = {
3373 .color_check = chv_color_check,
3374 .color_commit_arm = i9xx_color_commit_arm,
3375 .load_luts = chv_load_luts,
3376 .read_luts = chv_read_luts,
3377 .lut_equal = chv_lut_equal,
3378 .read_csc = chv_read_csc,
3381 static const struct intel_color_funcs i965_color_funcs = {
3382 .color_check = i9xx_color_check,
3383 .color_commit_arm = i9xx_color_commit_arm,
3384 .load_luts = i965_load_luts,
3385 .read_luts = i965_read_luts,
3386 .lut_equal = i965_lut_equal,
3389 static const struct intel_color_funcs i9xx_color_funcs = {
3390 .color_check = i9xx_color_check,
3391 .color_commit_arm = i9xx_color_commit_arm,
3392 .load_luts = i9xx_load_luts,
3393 .read_luts = i9xx_read_luts,
3394 .lut_equal = i9xx_lut_equal,
3397 static const struct intel_color_funcs tgl_color_funcs = {
3398 .color_check = icl_color_check,
3399 .color_commit_noarm = icl_color_commit_noarm,
3400 .color_commit_arm = icl_color_commit_arm,
3401 .load_luts = icl_load_luts,
3402 .read_luts = icl_read_luts,
3403 .lut_equal = icl_lut_equal,
3404 .read_csc = icl_read_csc,
3407 static const struct intel_color_funcs icl_color_funcs = {
3408 .color_check = icl_color_check,
3409 .color_commit_noarm = icl_color_commit_noarm,
3410 .color_commit_arm = icl_color_commit_arm,
3411 .color_post_update = icl_color_post_update,
3412 .load_luts = icl_load_luts,
3413 .read_luts = icl_read_luts,
3414 .lut_equal = icl_lut_equal,
3415 .read_csc = icl_read_csc,
3418 static const struct intel_color_funcs glk_color_funcs = {
3419 .color_check = glk_color_check,
3420 .color_commit_noarm = skl_color_commit_noarm,
3421 .color_commit_arm = skl_color_commit_arm,
3422 .load_luts = glk_load_luts,
3423 .read_luts = glk_read_luts,
3424 .lut_equal = glk_lut_equal,
3425 .read_csc = skl_read_csc,
3428 static const struct intel_color_funcs skl_color_funcs = {
3429 .color_check = ivb_color_check,
3430 .color_commit_noarm = skl_color_commit_noarm,
3431 .color_commit_arm = skl_color_commit_arm,
3432 .load_luts = bdw_load_luts,
3433 .read_luts = bdw_read_luts,
3434 .lut_equal = ivb_lut_equal,
3435 .read_csc = skl_read_csc,
3438 static const struct intel_color_funcs bdw_color_funcs = {
3439 .color_check = ivb_color_check,
3440 .color_commit_noarm = ilk_color_commit_noarm,
3441 .color_commit_arm = hsw_color_commit_arm,
3442 .load_luts = bdw_load_luts,
3443 .read_luts = bdw_read_luts,
3444 .lut_equal = ivb_lut_equal,
3445 .read_csc = ilk_read_csc,
3448 static const struct intel_color_funcs hsw_color_funcs = {
3449 .color_check = ivb_color_check,
3450 .color_commit_noarm = ilk_color_commit_noarm,
3451 .color_commit_arm = hsw_color_commit_arm,
3452 .load_luts = ivb_load_luts,
3453 .read_luts = ivb_read_luts,
3454 .lut_equal = ivb_lut_equal,
3455 .read_csc = ilk_read_csc,
3458 static const struct intel_color_funcs ivb_color_funcs = {
3459 .color_check = ivb_color_check,
3460 .color_commit_noarm = ilk_color_commit_noarm,
3461 .color_commit_arm = ilk_color_commit_arm,
3462 .load_luts = ivb_load_luts,
3463 .read_luts = ivb_read_luts,
3464 .lut_equal = ivb_lut_equal,
3465 .read_csc = ilk_read_csc,
3468 static const struct intel_color_funcs ilk_color_funcs = {
3469 .color_check = ilk_color_check,
3470 .color_commit_noarm = ilk_color_commit_noarm,
3471 .color_commit_arm = ilk_color_commit_arm,
3472 .load_luts = ilk_load_luts,
3473 .read_luts = ilk_read_luts,
3474 .lut_equal = ilk_lut_equal,
3475 .read_csc = ilk_read_csc,
3478 void intel_color_crtc_init(struct intel_crtc *crtc)
3480 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3481 int degamma_lut_size, gamma_lut_size;
3484 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
3486 gamma_lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
3487 degamma_lut_size = DISPLAY_INFO(i915)->color.degamma_lut_size;
3488 has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
3491 * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
3492 * only mode supported by Alviso and Grantsdale."
3494 * Actually looks like this affects all of gen3.
3495 * Confirmed on alv,cst,pnv. Mobile gen2 parts (alm,mgm)
3496 * are confirmed not to suffer from this restriction.
3498 if (DISPLAY_VER(i915) == 3 && crtc->pipe == PIPE_A)
3499 gamma_lut_size = 256;
3501 drm_crtc_enable_color_mgmt(&crtc->base, degamma_lut_size,
3502 has_ctm, gamma_lut_size);
3505 int intel_color_init(struct drm_i915_private *i915)
3507 struct drm_property_blob *blob;
3509 if (DISPLAY_VER(i915) != 10)
3512 blob = create_linear_lut(i915,
3513 DISPLAY_INFO(i915)->color.degamma_lut_size);
3515 return PTR_ERR(blob);
3517 i915->display.color.glk_linear_degamma_lut = blob;
3522 void intel_color_init_hooks(struct drm_i915_private *i915)
3524 if (HAS_GMCH(i915)) {
3525 if (IS_CHERRYVIEW(i915))
3526 i915->display.funcs.color = &chv_color_funcs;
3527 else if (DISPLAY_VER(i915) >= 4)
3528 i915->display.funcs.color = &i965_color_funcs;
3530 i915->display.funcs.color = &i9xx_color_funcs;
3532 if (DISPLAY_VER(i915) >= 12)
3533 i915->display.funcs.color = &tgl_color_funcs;
3534 else if (DISPLAY_VER(i915) == 11)
3535 i915->display.funcs.color = &icl_color_funcs;
3536 else if (DISPLAY_VER(i915) == 10)
3537 i915->display.funcs.color = &glk_color_funcs;
3538 else if (DISPLAY_VER(i915) == 9)
3539 i915->display.funcs.color = &skl_color_funcs;
3540 else if (DISPLAY_VER(i915) == 8)
3541 i915->display.funcs.color = &bdw_color_funcs;
3542 else if (IS_HASWELL(i915))
3543 i915->display.funcs.color = &hsw_color_funcs;
3544 else if (DISPLAY_VER(i915) == 7)
3545 i915->display.funcs.color = &ivb_color_funcs;
3547 i915->display.funcs.color = &ilk_color_funcs;