2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Madhav Chauhan <madhav.chauhan@intel.com>
25 * Jani Nikula <jani.nikula@intel.com>
28 #include <drm/display/drm_dsc_helper.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_mipi_dsi.h>
34 #include "icl_dsi_regs.h"
35 #include "intel_atomic.h"
36 #include "intel_backlight.h"
37 #include "intel_backlight_regs.h"
38 #include "intel_combo_phy.h"
39 #include "intel_combo_phy_regs.h"
40 #include "intel_connector.h"
41 #include "intel_crtc.h"
42 #include "intel_ddi.h"
44 #include "intel_dsi.h"
45 #include "intel_dsi_vbt.h"
46 #include "intel_panel.h"
47 #include "intel_vdsc.h"
48 #include "intel_vdsc_regs.h"
49 #include "skl_scaler.h"
50 #include "skl_universal_plane.h"
52 static int header_credits_available(struct drm_i915_private *dev_priv,
53 enum transcoder dsi_trans)
55 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
56 >> FREE_HEADER_CREDIT_SHIFT;
59 static int payload_credits_available(struct drm_i915_private *dev_priv,
60 enum transcoder dsi_trans)
62 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
63 >> FREE_PLOAD_CREDIT_SHIFT;
66 static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
67 enum transcoder dsi_trans, int hdr_credit)
69 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
71 drm_err(&dev_priv->drm, "DSI header credits not released\n");
78 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
79 enum transcoder dsi_trans, int payld_credit)
81 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
83 drm_err(&dev_priv->drm, "DSI payload credits not released\n");
90 static enum transcoder dsi_port_to_transcoder(enum port port)
93 return TRANSCODER_DSI_0;
95 return TRANSCODER_DSI_1;
98 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
101 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
102 struct mipi_dsi_device *dsi;
104 enum transcoder dsi_trans;
107 /* wait for header/payload credits to be released */
108 for_each_dsi_port(port, intel_dsi->ports) {
109 dsi_trans = dsi_port_to_transcoder(port);
110 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
111 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
114 /* send nop DCS command */
115 for_each_dsi_port(port, intel_dsi->ports) {
116 dsi = intel_dsi->dsi_hosts[port]->device;
117 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
119 ret = mipi_dsi_dcs_nop(dsi);
121 drm_err(&dev_priv->drm,
122 "error sending DCS NOP command\n");
125 /* wait for header credits to be released */
126 for_each_dsi_port(port, intel_dsi->ports) {
127 dsi_trans = dsi_port_to_transcoder(port);
128 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
131 /* wait for LP TX in progress bit to be cleared */
132 for_each_dsi_port(port, intel_dsi->ports) {
133 dsi_trans = dsi_port_to_transcoder(port);
134 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
135 LPTX_IN_PROGRESS), 20))
136 drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
140 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
141 const struct mipi_dsi_packet *packet)
143 struct intel_dsi *intel_dsi = host->intel_dsi;
144 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
145 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
146 const u8 *data = packet->payload;
147 u32 len = packet->payload_length;
150 /* payload queue can accept *256 bytes*, check limit */
151 if (len > MAX_PLOAD_CREDIT * 4) {
152 drm_err(&i915->drm, "payload size exceeds max queue limit\n");
156 for (i = 0; i < len; i += 4) {
159 if (!wait_for_payload_credits(i915, dsi_trans, 1))
162 for (j = 0; j < min_t(u32, len - i, 4); j++)
163 tmp |= *data++ << 8 * j;
165 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp);
171 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
172 const struct mipi_dsi_packet *packet,
175 struct intel_dsi *intel_dsi = host->intel_dsi;
176 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
177 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
180 if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
183 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
186 tmp |= PAYLOAD_PRESENT;
188 tmp &= ~PAYLOAD_PRESENT;
190 tmp &= ~VBLANK_FENCE;
193 tmp |= LP_DATA_TRANSFER;
195 tmp &= ~LP_DATA_TRANSFER;
197 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
198 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
199 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
200 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
201 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
202 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
207 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
214 mode_flags = crtc_state->mode_flags;
217 * case 1 also covers dual link
218 * In case of dual link, frame update should be set on
221 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
223 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
228 intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST);
231 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
234 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
239 for_each_dsi_phy(phy, intel_dsi->phys) {
241 * Program voltage swing and pre-emphasis level values as per
242 * table in BSPEC under DDI buffer programing
244 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
245 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
247 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
250 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
251 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val);
253 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
255 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
257 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
260 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
261 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val);
263 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
265 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
267 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val);
269 /* Bspec: must not use GRP register for write */
270 for (lane = 0; lane <= 3; lane++)
271 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
276 static void configure_dual_link_mode(struct intel_encoder *encoder,
277 const struct intel_crtc_state *pipe_config)
279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
280 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
281 i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
284 /* FIXME: Move all DSS handling to intel_vdsc.c */
285 if (DISPLAY_VER(dev_priv) >= 12) {
286 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
288 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
289 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
291 dss_ctl1_reg = DSS_CTL1;
292 dss_ctl2_reg = DSS_CTL2;
295 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
296 dss_ctl1 |= SPLITTER_ENABLE;
297 dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
298 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
300 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
301 const struct drm_display_mode *adjusted_mode =
302 &pipe_config->hw.adjusted_mode;
303 u16 hactive = adjusted_mode->crtc_hdisplay;
306 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
307 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
309 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
310 drm_err(&dev_priv->drm,
311 "DL buffer depth exceed max value\n");
313 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
314 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
315 intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
316 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
319 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
322 intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
325 /* aka DSI 8X clock */
326 static int afe_clk(struct intel_encoder *encoder,
327 const struct intel_crtc_state *crtc_state)
329 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
332 if (crtc_state->dsc.compression_enable)
333 bpp = crtc_state->dsc.compressed_bpp;
335 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
337 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
340 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
341 const struct intel_crtc_state *crtc_state)
343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
344 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
347 int theo_word_clk, act_word_clk;
348 u32 esc_clk_div_m, esc_clk_div_m_phy;
350 afe_clk_khz = afe_clk(encoder, crtc_state);
352 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
353 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
354 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
355 esc_clk_div_m = act_word_clk * 8;
356 esc_clk_div_m_phy = (act_word_clk - 1) / 2;
358 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
361 for_each_dsi_port(port, intel_dsi->ports) {
362 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
363 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
364 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
367 for_each_dsi_port(port, intel_dsi->ports) {
368 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
369 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
370 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
373 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
374 for_each_dsi_port(port, intel_dsi->ports) {
375 intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
376 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
377 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
382 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
383 struct intel_dsi *intel_dsi)
387 for_each_dsi_port(port, intel_dsi->ports) {
388 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
389 intel_dsi->io_wakeref[port] =
390 intel_display_power_get(dev_priv,
392 POWER_DOMAIN_PORT_DDI_IO_A :
393 POWER_DOMAIN_PORT_DDI_IO_B);
397 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
400 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
403 for_each_dsi_port(port, intel_dsi->ports)
404 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
405 0, COMBO_PHY_MODE_DSI);
407 get_dsi_io_power_domains(dev_priv, intel_dsi);
410 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
413 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
416 for_each_dsi_phy(phy, intel_dsi->phys)
417 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
418 intel_dsi->lane_count, false);
421 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
424 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
429 /* Step 4b(i) set loadgen select for transmit and aux lanes */
430 for_each_dsi_phy(phy, intel_dsi->phys) {
431 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0);
432 for (lane = 0; lane <= 3; lane++)
433 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
434 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
437 /* Step 4b(ii) set latency optimization for transmit and aux lanes */
438 for_each_dsi_phy(phy, intel_dsi->phys) {
439 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy),
440 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
441 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
442 tmp &= ~FRC_LATENCY_OPTIM_MASK;
443 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
444 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
446 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
447 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
448 intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
449 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
451 tmp = intel_de_read(dev_priv,
452 ICL_PORT_PCS_DW1_LN(0, phy));
453 tmp &= ~LATENCY_OPTIM_MASK;
454 tmp |= LATENCY_OPTIM_VAL(0x1);
455 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
462 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
464 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
465 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
469 /* clear common keeper enable bit */
470 for_each_dsi_phy(phy, intel_dsi->phys) {
471 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
472 tmp &= ~COMMON_KEEPER_EN;
473 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
474 intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
478 * Set SUS Clock Config bitfield to 11b
479 * Note: loadgen select program is done
480 * as part of lane phy sequence configuration
482 for_each_dsi_phy(phy, intel_dsi->phys)
483 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG);
485 /* Clear training enable to change swing values */
486 for_each_dsi_phy(phy, intel_dsi->phys) {
487 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
488 tmp &= ~TX_TRAINING_EN;
489 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
490 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
493 /* Program swing and de-emphasis */
494 dsi_program_swing_and_deemphasis(encoder);
496 /* Set training enable to trigger update */
497 for_each_dsi_phy(phy, intel_dsi->phys) {
498 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
499 tmp |= TX_TRAINING_EN;
500 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
501 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
505 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
507 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
508 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
511 for_each_dsi_port(port, intel_dsi->ports) {
512 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
514 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
517 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
523 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
524 const struct intel_crtc_state *crtc_state)
526 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
527 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
531 /* Program DPHY clock lanes timings */
532 for_each_dsi_port(port, intel_dsi->ports)
533 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
534 intel_dsi->dphy_reg);
536 /* Program DPHY data lanes timings */
537 for_each_dsi_port(port, intel_dsi->ports)
538 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
539 intel_dsi->dphy_data_lane_reg);
542 * If DSI link operating at or below an 800 MHz,
543 * TA_SURE should be override and programmed to
544 * a value '0' inside TA_PARAM_REGISTERS otherwise
545 * leave all fields at HW default values.
547 if (DISPLAY_VER(dev_priv) == 11) {
548 if (afe_clk(encoder, crtc_state) <= 800000) {
549 for_each_dsi_port(port, intel_dsi->ports)
550 intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port),
552 TA_SURE_OVERRIDE | TA_SURE(0));
556 if (IS_JSL_EHL(dev_priv)) {
557 for_each_dsi_phy(phy, intel_dsi->phys)
558 intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
559 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
564 gen11_dsi_setup_timings(struct intel_encoder *encoder,
565 const struct intel_crtc_state *crtc_state)
567 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
568 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
571 /* Program T-INIT master registers */
572 for_each_dsi_port(port, intel_dsi->ports)
573 intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port),
574 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
576 /* shadow register inside display core */
577 for_each_dsi_port(port, intel_dsi->ports)
578 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
579 intel_dsi->dphy_reg);
581 /* shadow register inside display core */
582 for_each_dsi_port(port, intel_dsi->ports)
583 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
584 intel_dsi->dphy_data_lane_reg);
586 /* shadow register inside display core */
587 if (DISPLAY_VER(dev_priv) == 11) {
588 if (afe_clk(encoder, crtc_state) <= 800000) {
589 for_each_dsi_port(port, intel_dsi->ports) {
590 intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port),
592 TA_SURE_OVERRIDE | TA_SURE(0));
598 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
600 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
601 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
605 mutex_lock(&dev_priv->display.dpll.lock);
606 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
607 for_each_dsi_phy(phy, intel_dsi->phys)
608 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
610 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
611 mutex_unlock(&dev_priv->display.dpll.lock);
614 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
616 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
617 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
621 mutex_lock(&dev_priv->display.dpll.lock);
622 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
623 for_each_dsi_phy(phy, intel_dsi->phys)
624 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
626 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
627 mutex_unlock(&dev_priv->display.dpll.lock);
630 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
632 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
633 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
634 bool clock_enabled = false;
638 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
640 for_each_dsi_phy(phy, intel_dsi->phys) {
641 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
642 clock_enabled = true;
645 return clock_enabled;
648 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
649 const struct intel_crtc_state *crtc_state)
651 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
652 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
653 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
657 mutex_lock(&dev_priv->display.dpll.lock);
659 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
660 for_each_dsi_phy(phy, intel_dsi->phys) {
661 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
662 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
664 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
666 for_each_dsi_phy(phy, intel_dsi->phys) {
667 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
669 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
671 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
673 mutex_unlock(&dev_priv->display.dpll.lock);
677 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
678 const struct intel_crtc_state *pipe_config)
680 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
681 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
682 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
683 enum pipe pipe = crtc->pipe;
686 enum transcoder dsi_trans;
688 for_each_dsi_port(port, intel_dsi->ports) {
689 dsi_trans = dsi_port_to_transcoder(port);
690 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
692 if (intel_dsi->eotp_pkt)
693 tmp &= ~EOTP_DISABLED;
695 tmp |= EOTP_DISABLED;
697 /* enable link calibration if freq > 1.5Gbps */
698 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
699 tmp &= ~LINK_CALIBRATION_MASK;
700 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
703 /* configure continuous clock */
704 tmp &= ~CONTINUOUS_CLK_MASK;
705 if (intel_dsi->clock_stop)
706 tmp |= CLK_ENTER_LP_AFTER_DATA;
708 tmp |= CLK_HS_CONTINUOUS;
710 /* configure buffer threshold limit to minimum */
711 tmp &= ~PIX_BUF_THRESHOLD_MASK;
712 tmp |= PIX_BUF_THRESHOLD_1_4;
714 /* set virtual channel to '0' */
715 tmp &= ~PIX_VIRT_CHAN_MASK;
716 tmp |= PIX_VIRT_CHAN(0);
718 /* program BGR transmission */
719 if (intel_dsi->bgr_enabled)
720 tmp |= BGR_TRANSMISSION;
722 /* select pixel format */
723 tmp &= ~PIX_FMT_MASK;
724 if (pipe_config->dsc.compression_enable) {
725 tmp |= PIX_FMT_COMPRESSED;
727 switch (intel_dsi->pixel_format) {
729 MISSING_CASE(intel_dsi->pixel_format);
731 case MIPI_DSI_FMT_RGB565:
732 tmp |= PIX_FMT_RGB565;
734 case MIPI_DSI_FMT_RGB666_PACKED:
735 tmp |= PIX_FMT_RGB666_PACKED;
737 case MIPI_DSI_FMT_RGB666:
738 tmp |= PIX_FMT_RGB666_LOOSE;
740 case MIPI_DSI_FMT_RGB888:
741 tmp |= PIX_FMT_RGB888;
746 if (DISPLAY_VER(dev_priv) >= 12) {
747 if (is_vid_mode(intel_dsi))
748 tmp |= BLANKING_PACKET_ENABLE;
751 /* program DSI operation mode */
752 if (is_vid_mode(intel_dsi)) {
753 tmp &= ~OP_MODE_MASK;
754 switch (intel_dsi->video_mode) {
756 MISSING_CASE(intel_dsi->video_mode);
758 case NON_BURST_SYNC_EVENTS:
759 tmp |= VIDEO_MODE_SYNC_EVENT;
761 case NON_BURST_SYNC_PULSE:
762 tmp |= VIDEO_MODE_SYNC_PULSE;
767 * FIXME: Retrieve this info from VBT.
768 * As per the spec when dsi transcoder is operating
769 * in TE GATE mode, TE comes from GPIO
770 * which is UTIL PIN for DSI 0.
771 * Also this GPIO would not be used for other
772 * purposes is an assumption.
774 tmp &= ~OP_MODE_MASK;
775 tmp |= CMD_MODE_TE_GATE;
776 tmp |= TE_SOURCE_GPIO;
779 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
782 /* enable port sync mode if dual link */
783 if (intel_dsi->dual_link) {
784 for_each_dsi_port(port, intel_dsi->ports) {
785 dsi_trans = dsi_port_to_transcoder(port);
786 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans),
787 0, PORT_SYNC_MODE_ENABLE);
790 /* configure stream splitting */
791 configure_dual_link_mode(encoder, pipe_config);
794 for_each_dsi_port(port, intel_dsi->ports) {
795 dsi_trans = dsi_port_to_transcoder(port);
797 /* select data lane width */
798 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
799 tmp &= ~DDI_PORT_WIDTH_MASK;
800 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
802 /* select input pipe */
803 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
809 tmp |= TRANS_DDI_EDP_INPUT_A_ON;
812 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
815 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
818 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
822 /* enable DDI buffer */
823 tmp |= TRANS_DDI_FUNC_ENABLE;
824 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
827 /* wait for link ready */
828 for_each_dsi_port(port, intel_dsi->ports) {
829 dsi_trans = dsi_port_to_transcoder(port);
830 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
832 drm_err(&dev_priv->drm, "DSI link not ready\n");
837 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
838 const struct intel_crtc_state *crtc_state)
840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
841 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
842 const struct drm_display_mode *adjusted_mode =
843 &crtc_state->hw.adjusted_mode;
845 enum transcoder dsi_trans;
846 /* horizontal timings */
847 u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
849 /* vertical timings */
850 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
851 int mul = 1, div = 1;
854 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
855 * for slower link speed if DSC is enabled.
857 * The compression frequency ratio is the ratio between compressed and
858 * non-compressed link speeds, and simplifies down to the ratio between
859 * compressed and non-compressed bpp.
861 if (crtc_state->dsc.compression_enable) {
862 mul = crtc_state->dsc.compressed_bpp;
863 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
866 hactive = adjusted_mode->crtc_hdisplay;
868 if (is_vid_mode(intel_dsi))
869 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
871 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
873 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
874 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
875 hsync_size = hsync_end - hsync_start;
876 hback_porch = (adjusted_mode->crtc_htotal -
877 adjusted_mode->crtc_hsync_end);
878 vactive = adjusted_mode->crtc_vdisplay;
880 if (is_vid_mode(intel_dsi)) {
881 vtotal = adjusted_mode->crtc_vtotal;
883 int bpp, line_time_us, byte_clk_period_ns;
885 if (crtc_state->dsc.compression_enable)
886 bpp = crtc_state->dsc.compressed_bpp;
888 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
890 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
891 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
892 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
894 vsync_start = adjusted_mode->crtc_vsync_start;
895 vsync_end = adjusted_mode->crtc_vsync_end;
896 vsync_shift = hsync_start - htotal / 2;
898 if (intel_dsi->dual_link) {
900 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
901 hactive += intel_dsi->pixel_overlap;
905 /* minimum hactive as per bspec: 256 pixels */
906 if (adjusted_mode->crtc_hdisplay < 256)
907 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
909 /* if RGB666 format, then hactive must be multiple of 4 pixels */
910 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
911 drm_err(&dev_priv->drm,
912 "hactive pixels are not multiple of 4\n");
914 /* program TRANS_HTOTAL register */
915 for_each_dsi_port(port, intel_dsi->ports) {
916 dsi_trans = dsi_port_to_transcoder(port);
917 intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
918 HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
921 /* TRANS_HSYNC register to be programmed only for video mode */
922 if (is_vid_mode(intel_dsi)) {
923 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
924 /* BSPEC: hsync size should be atleast 16 pixels */
926 drm_err(&dev_priv->drm,
927 "hsync size < 16 pixels\n");
930 if (hback_porch < 16)
931 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
933 if (intel_dsi->dual_link) {
938 for_each_dsi_port(port, intel_dsi->ports) {
939 dsi_trans = dsi_port_to_transcoder(port);
940 intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
941 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
945 /* program TRANS_VTOTAL register */
946 for_each_dsi_port(port, intel_dsi->ports) {
947 dsi_trans = dsi_port_to_transcoder(port);
949 * FIXME: Programing this by assuming progressive mode, since
950 * non-interlaced info from VBT is not saved inside
951 * struct drm_display_mode.
952 * For interlace mode: program required pixel minus 2
954 intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
955 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
958 if (vsync_end < vsync_start || vsync_end > vtotal)
959 drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
961 if (vsync_start < vactive)
962 drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
964 /* program TRANS_VSYNC register for video mode only */
965 if (is_vid_mode(intel_dsi)) {
966 for_each_dsi_port(port, intel_dsi->ports) {
967 dsi_trans = dsi_port_to_transcoder(port);
968 intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),
969 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
974 * FIXME: It has to be programmed only for video modes and interlaced
975 * modes. Put the check condition here once interlaced
976 * info available as described above.
977 * program TRANS_VSYNCSHIFT register
979 if (is_vid_mode(intel_dsi)) {
980 for_each_dsi_port(port, intel_dsi->ports) {
981 dsi_trans = dsi_port_to_transcoder(port);
982 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans),
988 * program TRANS_VBLANK register, should be same as vtotal programmed
990 * FIXME get rid of these local hacks and do it right,
991 * this will not handle eg. delayed vblank correctly.
993 if (DISPLAY_VER(dev_priv) >= 12) {
994 for_each_dsi_port(port, intel_dsi->ports) {
995 dsi_trans = dsi_port_to_transcoder(port);
996 intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
997 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
1002 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1004 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1005 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1007 enum transcoder dsi_trans;
1009 for_each_dsi_port(port, intel_dsi->ports) {
1010 dsi_trans = dsi_port_to_transcoder(port);
1011 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE);
1013 /* wait for transcoder to be enabled */
1014 if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans),
1015 TRANSCONF_STATE_ENABLE, 10))
1016 drm_err(&dev_priv->drm,
1017 "DSI transcoder not enabled\n");
1021 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1022 const struct intel_crtc_state *crtc_state)
1024 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1025 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1027 enum transcoder dsi_trans;
1028 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1031 * escape clock count calculation:
1032 * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1033 * UI (nsec) = (10^6)/Bitrate
1034 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1035 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
1037 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1039 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1041 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1042 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1044 for_each_dsi_port(port, intel_dsi->ports) {
1045 dsi_trans = dsi_port_to_transcoder(port);
1047 /* program hst_tx_timeout */
1048 intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans),
1049 HSTX_TIMEOUT_VALUE_MASK,
1050 HSTX_TIMEOUT_VALUE(hs_tx_timeout));
1052 /* FIXME: DSI_CALIB_TO */
1054 /* program lp_rx_host timeout */
1055 intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans),
1056 LPRX_TIMEOUT_VALUE_MASK,
1057 LPRX_TIMEOUT_VALUE(lp_rx_timeout));
1059 /* FIXME: DSI_PWAIT_TO */
1061 /* program turn around timeout */
1062 intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans),
1063 TA_TIMEOUT_VALUE_MASK,
1064 TA_TIMEOUT_VALUE(ta_timeout));
1068 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1071 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1072 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1076 * used as TE i/p for DSI0,
1077 * for dual link/DSI1 TE is from slave DSI1
1080 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1083 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1086 tmp |= UTIL_PIN_DIRECTION_INPUT;
1087 tmp |= UTIL_PIN_ENABLE;
1089 tmp &= ~UTIL_PIN_ENABLE;
1091 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1095 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1096 const struct intel_crtc_state *crtc_state)
1098 /* step 4a: power up all lanes of the DDI used by DSI */
1099 gen11_dsi_power_up_lanes(encoder);
1101 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1102 gen11_dsi_config_phy_lanes_sequence(encoder);
1104 /* step 4c: configure voltage swing and skew */
1105 gen11_dsi_voltage_swing_program_seq(encoder);
1107 /* setup D-PHY timings */
1108 gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1110 /* enable DDI buffer */
1111 gen11_dsi_enable_ddi_buffer(encoder);
1113 gen11_dsi_gate_clocks(encoder);
1115 gen11_dsi_setup_timings(encoder, crtc_state);
1117 /* Since transcoder is configured to take events from GPIO */
1118 gen11_dsi_config_util_pin(encoder, true);
1120 /* step 4h: setup DSI protocol timeouts */
1121 gen11_dsi_setup_timeouts(encoder, crtc_state);
1123 /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1124 gen11_dsi_configure_transcoder(encoder, crtc_state);
1127 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1129 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1130 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1131 struct mipi_dsi_device *dsi;
1133 enum transcoder dsi_trans;
1137 /* set maximum return packet size */
1138 for_each_dsi_port(port, intel_dsi->ports) {
1139 dsi_trans = dsi_port_to_transcoder(port);
1142 * FIXME: This uses the number of DW's currently in the payload
1143 * receive queue. This is probably not what we want here.
1145 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1146 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1147 /* multiply "Number Rx Payload DW" by 4 to get max value */
1149 dsi = intel_dsi->dsi_hosts[port]->device;
1150 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1152 drm_err(&dev_priv->drm,
1153 "error setting max return pkt size%d\n", tmp);
1156 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1158 /* ensure all panel commands dispatched before enabling transcoder */
1159 wait_for_cmds_dispatched_to_panel(encoder);
1162 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1163 struct intel_encoder *encoder,
1164 const struct intel_crtc_state *crtc_state,
1165 const struct drm_connector_state *conn_state)
1167 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1169 intel_dsi_wait_panel_power_cycle(intel_dsi);
1171 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1172 msleep(intel_dsi->panel_on_delay);
1173 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1175 /* step2: enable IO power */
1176 gen11_dsi_enable_io_power(encoder);
1178 /* step3: enable DSI PLL */
1179 gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1182 static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1183 struct intel_encoder *encoder,
1184 const struct intel_crtc_state *pipe_config,
1185 const struct drm_connector_state *conn_state)
1188 gen11_dsi_map_pll(encoder, pipe_config);
1190 /* step4: enable DSI port and DPHY */
1191 gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1193 /* step5: program and powerup panel */
1194 gen11_dsi_powerup_panel(encoder);
1196 intel_dsc_dsi_pps_write(encoder, pipe_config);
1198 /* step6c: configure transcoder timings */
1199 gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1203 * Wa_1409054076:icl,jsl,ehl
1204 * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1205 * the AMT KVMR feature will incorrectly see pipe A as enabled.
1206 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1207 * it set while DSI is enabled on pipe B
1209 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1210 enum pipe pipe, bool enable)
1212 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1214 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
1215 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1217 enable ? IGNORE_KVMR_PIPE_A : 0);
1221 * Wa_16012360555:adl-p
1222 * SW will have to program the "LP to HS Wakeup Guardband"
1223 * to account for the repeaters on the HS Request/Ready
1224 * PPI signaling between the Display engine and the DPHY.
1226 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
1228 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1229 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1232 if (DISPLAY_VER(i915) == 13) {
1233 for_each_dsi_port(port, intel_dsi->ports)
1234 intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
1235 TGL_DSI_CHKN_LSHS_GB_MASK,
1236 TGL_DSI_CHKN_LSHS_GB(4));
1240 static void gen11_dsi_enable(struct intel_atomic_state *state,
1241 struct intel_encoder *encoder,
1242 const struct intel_crtc_state *crtc_state,
1243 const struct drm_connector_state *conn_state)
1245 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1246 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1248 /* Wa_1409054076:icl,jsl,ehl */
1249 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
1251 /* Wa_16012360555:adl-p */
1252 adlp_set_lp_hs_wakeup_gb(encoder);
1254 /* step6d: enable dsi transcoder */
1255 gen11_dsi_enable_transcoder(encoder);
1257 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1259 /* step7: enable backlight */
1260 intel_backlight_enable(crtc_state, conn_state);
1261 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1263 intel_crtc_vblank_on(crtc_state);
1266 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1269 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1271 enum transcoder dsi_trans;
1273 for_each_dsi_port(port, intel_dsi->ports) {
1274 dsi_trans = dsi_port_to_transcoder(port);
1276 /* disable transcoder */
1277 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0);
1279 /* wait for transcoder to be disabled */
1280 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans),
1281 TRANSCONF_STATE_ENABLE, 50))
1282 drm_err(&dev_priv->drm,
1283 "DSI trancoder not disabled\n");
1287 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1289 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1291 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1293 /* ensure cmds dispatched to panel */
1294 wait_for_cmds_dispatched_to_panel(encoder);
1297 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1299 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1300 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1302 enum transcoder dsi_trans;
1305 /* disable periodic update mode */
1306 if (is_cmd_mode(intel_dsi)) {
1307 for_each_dsi_port(port, intel_dsi->ports)
1308 intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port),
1309 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
1312 /* put dsi link in ULPS */
1313 for_each_dsi_port(port, intel_dsi->ports) {
1314 dsi_trans = dsi_port_to_transcoder(port);
1315 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1316 tmp |= LINK_ENTER_ULPS;
1317 tmp &= ~LINK_ULPS_TYPE_LP11;
1318 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1320 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1323 drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1326 /* disable ddi function */
1327 for_each_dsi_port(port, intel_dsi->ports) {
1328 dsi_trans = dsi_port_to_transcoder(port);
1329 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans),
1330 TRANS_DDI_FUNC_ENABLE, 0);
1333 /* disable port sync mode if dual link */
1334 if (intel_dsi->dual_link) {
1335 for_each_dsi_port(port, intel_dsi->ports) {
1336 dsi_trans = dsi_port_to_transcoder(port);
1337 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans),
1338 PORT_SYNC_MODE_ENABLE, 0);
1343 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1346 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1349 gen11_dsi_ungate_clocks(encoder);
1350 for_each_dsi_port(port, intel_dsi->ports) {
1351 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1353 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1356 drm_err(&dev_priv->drm,
1357 "DDI port:%c buffer not idle\n",
1360 gen11_dsi_gate_clocks(encoder);
1363 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1365 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1366 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1369 for_each_dsi_port(port, intel_dsi->ports) {
1370 intel_wakeref_t wakeref;
1372 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1373 intel_display_power_put(dev_priv,
1375 POWER_DOMAIN_PORT_DDI_IO_A :
1376 POWER_DOMAIN_PORT_DDI_IO_B,
1380 /* set mode to DDI */
1381 for_each_dsi_port(port, intel_dsi->ports)
1382 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
1383 COMBO_PHY_MODE_DSI, 0);
1386 static void gen11_dsi_disable(struct intel_atomic_state *state,
1387 struct intel_encoder *encoder,
1388 const struct intel_crtc_state *old_crtc_state,
1389 const struct drm_connector_state *old_conn_state)
1391 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1393 /* step1: turn off backlight */
1394 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1395 intel_backlight_disable(old_conn_state);
1398 static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1399 struct intel_encoder *encoder,
1400 const struct intel_crtc_state *old_crtc_state,
1401 const struct drm_connector_state *old_conn_state)
1403 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1404 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1406 intel_crtc_vblank_off(old_crtc_state);
1408 /* step2d,e: disable transcoder and wait */
1409 gen11_dsi_disable_transcoder(encoder);
1411 /* Wa_1409054076:icl,jsl,ehl */
1412 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
1414 /* step2f,g: powerdown panel */
1415 gen11_dsi_powerdown_panel(encoder);
1417 /* step2h,i,j: deconfig trancoder */
1418 gen11_dsi_deconfigure_trancoder(encoder);
1420 intel_dsc_disable(old_crtc_state);
1421 skl_scaler_disable(old_crtc_state);
1423 /* step3: disable port */
1424 gen11_dsi_disable_port(encoder);
1426 gen11_dsi_config_util_pin(encoder, false);
1428 /* step4: disable IO power */
1429 gen11_dsi_disable_io_power(encoder);
1431 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1433 msleep(intel_dsi->panel_off_delay);
1434 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1436 intel_dsi->panel_power_off_time = ktime_get_boottime();
1439 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1440 struct drm_display_mode *mode)
1443 return intel_dsi_mode_valid(connector, mode);
1446 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1447 struct intel_crtc_state *pipe_config)
1449 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1450 struct drm_display_mode *adjusted_mode =
1451 &pipe_config->hw.adjusted_mode;
1453 if (pipe_config->dsc.compressed_bpp) {
1454 int div = pipe_config->dsc.compressed_bpp;
1455 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1457 adjusted_mode->crtc_htotal =
1458 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1459 adjusted_mode->crtc_hsync_start =
1460 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1461 adjusted_mode->crtc_hsync_end =
1462 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1465 if (intel_dsi->dual_link) {
1466 adjusted_mode->crtc_hdisplay *= 2;
1467 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1468 adjusted_mode->crtc_hdisplay -=
1469 intel_dsi->pixel_overlap;
1470 adjusted_mode->crtc_htotal *= 2;
1472 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1473 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1475 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1476 if (intel_dsi->dual_link) {
1477 adjusted_mode->crtc_hsync_start *= 2;
1478 adjusted_mode->crtc_hsync_end *= 2;
1481 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1482 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1485 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1487 struct drm_device *dev = intel_dsi->base.base.dev;
1488 struct drm_i915_private *dev_priv = to_i915(dev);
1489 enum transcoder dsi_trans;
1492 if (intel_dsi->ports == BIT(PORT_B))
1493 dsi_trans = TRANSCODER_DSI_1;
1495 dsi_trans = TRANSCODER_DSI_0;
1497 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1498 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1501 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1502 struct intel_crtc_state *pipe_config)
1504 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1505 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1506 I915_MODE_FLAG_DSI_USE_TE0;
1507 else if (intel_dsi->ports == BIT(PORT_B))
1508 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1510 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1513 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1514 struct intel_crtc_state *pipe_config)
1516 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1517 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1519 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));
1521 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1522 if (intel_dsi->dual_link)
1523 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1525 gen11_dsi_get_timings(encoder, pipe_config);
1526 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1527 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1529 /* Get the details on which TE should be enabled */
1530 if (is_cmd_mode(intel_dsi))
1531 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1533 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1534 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1537 static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1538 const struct intel_crtc_state *crtc_state)
1540 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1541 struct intel_crtc *intel_crtc;
1547 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1548 pipe = intel_crtc->pipe;
1550 /* wa verify 1409054076:icl,jsl,ehl */
1551 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
1552 !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1553 drm_dbg_kms(&dev_priv->drm,
1554 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1555 encoder->base.base.id,
1556 encoder->base.name);
1559 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1560 struct intel_crtc_state *crtc_state)
1562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1563 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1564 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
1568 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1572 if (crtc_state->pipe_bpp < 8 * 3)
1575 /* FIXME: split only when necessary */
1576 if (crtc_state->dsc.slice_count > 1)
1577 crtc_state->dsc.dsc_split = true;
1579 /* FIXME: initialize from VBT */
1580 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1582 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1584 ret = intel_dsc_compute_params(crtc_state);
1588 /* DSI specific sanity checks on the common code */
1589 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1590 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1591 drm_WARN_ON(&dev_priv->drm,
1592 vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1593 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1594 drm_WARN_ON(&dev_priv->drm,
1595 vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1597 ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1601 crtc_state->dsc.compression_enable = true;
1606 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1607 struct intel_crtc_state *pipe_config,
1608 struct drm_connector_state *conn_state)
1610 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1611 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1613 struct intel_connector *intel_connector = intel_dsi->attached_connector;
1614 struct drm_display_mode *adjusted_mode =
1615 &pipe_config->hw.adjusted_mode;
1618 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1619 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1621 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
1625 ret = intel_panel_fitting(pipe_config, conn_state);
1629 adjusted_mode->flags = 0;
1631 /* Dual link goes to trancoder DSI'0' */
1632 if (intel_dsi->ports == BIT(PORT_B))
1633 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1635 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1637 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1638 pipe_config->pipe_bpp = 24;
1640 pipe_config->pipe_bpp = 18;
1642 pipe_config->clock_set = true;
1644 if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1645 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1647 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1650 * In case of TE GATE cmd mode, we
1651 * receive TE from the slave if
1652 * dual link is enabled
1654 if (is_cmd_mode(intel_dsi))
1655 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1660 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1661 struct intel_crtc_state *crtc_state)
1663 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1665 get_dsi_io_power_domains(i915,
1666 enc_to_intel_dsi(encoder));
1669 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1672 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1673 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1674 enum transcoder dsi_trans;
1675 intel_wakeref_t wakeref;
1680 wakeref = intel_display_power_get_if_enabled(dev_priv,
1681 encoder->power_domain);
1685 for_each_dsi_port(port, intel_dsi->ports) {
1686 dsi_trans = dsi_port_to_transcoder(port);
1687 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1688 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1689 case TRANS_DDI_EDP_INPUT_A_ON:
1692 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1695 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1698 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1702 drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1706 tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans));
1707 ret = tmp & TRANSCONF_ENABLE;
1710 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1714 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1715 struct intel_crtc_state *crtc_state)
1717 if (crtc_state->dsc.compression_enable) {
1718 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1719 crtc_state->uapi.mode_changed = true;
1727 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1729 intel_encoder_destroy(encoder);
1732 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1733 .destroy = gen11_dsi_encoder_destroy,
1736 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1737 .detect = intel_panel_detect,
1738 .late_register = intel_connector_register,
1739 .early_unregister = intel_connector_unregister,
1740 .destroy = intel_connector_destroy,
1741 .fill_modes = drm_helper_probe_single_connector_modes,
1742 .atomic_get_property = intel_digital_connector_atomic_get_property,
1743 .atomic_set_property = intel_digital_connector_atomic_set_property,
1744 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1745 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1748 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1749 .get_modes = intel_dsi_get_modes,
1750 .mode_valid = gen11_dsi_mode_valid,
1751 .atomic_check = intel_digital_connector_atomic_check,
1754 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1755 struct mipi_dsi_device *dsi)
1760 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1761 struct mipi_dsi_device *dsi)
1766 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1767 const struct mipi_dsi_msg *msg)
1769 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1770 struct mipi_dsi_packet dsi_pkt;
1772 bool enable_lpdt = false;
1774 ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1778 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1781 /* only long packet contains payload */
1782 if (mipi_dsi_packet_format_is_long(msg->type)) {
1783 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt);
1788 /* send packet header */
1789 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt);
1793 //TODO: add payload receive code if needed
1795 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1800 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1801 .attach = gen11_dsi_host_attach,
1802 .detach = gen11_dsi_host_detach,
1803 .transfer = gen11_dsi_host_transfer,
1806 #define ICL_PREPARE_CNT_MAX 0x7
1807 #define ICL_CLK_ZERO_CNT_MAX 0xf
1808 #define ICL_TRAIL_CNT_MAX 0x7
1809 #define ICL_TCLK_PRE_CNT_MAX 0x3
1810 #define ICL_TCLK_POST_CNT_MAX 0x7
1811 #define ICL_HS_ZERO_CNT_MAX 0xf
1812 #define ICL_EXIT_ZERO_CNT_MAX 0x7
1814 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1816 struct drm_device *dev = intel_dsi->base.base.dev;
1817 struct drm_i915_private *dev_priv = to_i915(dev);
1818 struct intel_connector *connector = intel_dsi->attached_connector;
1819 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1821 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1822 u32 ths_prepare_ns, tclk_trail_ns;
1824 u32 tclk_pre_cnt, tclk_post_cnt;
1826 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1828 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1829 ths_prepare_ns = max(mipi_config->ths_prepare,
1830 mipi_config->tclk_prepare);
1833 * prepare cnt in escape clocks
1834 * this field represents a hexadecimal value with a precision
1835 * of 1.2 – i.e. the most significant bit is the integer
1836 * and the least significant 2 bits are fraction bits.
1837 * so, the field can represent a range of 0.25 to 1.75
1839 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1840 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1841 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1843 prepare_cnt = ICL_PREPARE_CNT_MAX;
1846 /* clk zero count in escape clocks */
1847 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1848 ths_prepare_ns, tlpx_ns);
1849 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1850 drm_dbg_kms(&dev_priv->drm,
1851 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1852 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1855 /* trail cnt in escape clocks*/
1856 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1857 if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1858 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1860 trail_cnt = ICL_TRAIL_CNT_MAX;
1863 /* tclk pre count in escape clocks */
1864 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1865 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1866 drm_dbg_kms(&dev_priv->drm,
1867 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1868 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1871 /* tclk post count in escape clocks */
1872 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1873 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1874 drm_dbg_kms(&dev_priv->drm,
1875 "tclk_post_cnt out of range (%d)\n",
1877 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1880 /* hs zero cnt in escape clocks */
1881 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1882 ths_prepare_ns, tlpx_ns);
1883 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1884 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1886 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1889 /* hs exit zero cnt in escape clocks */
1890 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1891 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1892 drm_dbg_kms(&dev_priv->drm,
1893 "exit_zero_cnt out of range (%d)\n",
1895 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1898 /* clock lane dphy timings */
1899 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1900 CLK_PREPARE(prepare_cnt) |
1902 CLK_ZERO(clk_zero_cnt) |
1904 CLK_PRE(tclk_pre_cnt) |
1906 CLK_POST(tclk_post_cnt) |
1907 CLK_TRAIL_OVERRIDE |
1908 CLK_TRAIL(trail_cnt));
1910 /* data lanes dphy timings */
1911 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1912 HS_PREPARE(prepare_cnt) |
1914 HS_ZERO(hs_zero_cnt) |
1916 HS_TRAIL(trail_cnt) |
1918 HS_EXIT(exit_zero_cnt));
1920 intel_dsi_log_params(intel_dsi);
1923 static void icl_dsi_add_properties(struct intel_connector *connector)
1925 const struct drm_display_mode *fixed_mode =
1926 intel_panel_preferred_fixed_mode(connector);
1928 intel_attach_scaling_mode_property(&connector->base);
1930 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1931 intel_dsi_get_panel_orientation(connector),
1932 fixed_mode->hdisplay,
1933 fixed_mode->vdisplay);
1936 void icl_dsi_init(struct drm_i915_private *dev_priv)
1938 struct intel_dsi *intel_dsi;
1939 struct intel_encoder *encoder;
1940 struct intel_connector *intel_connector;
1941 struct drm_connector *connector;
1944 if (!intel_bios_is_dsi_present(dev_priv, &port))
1947 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1951 intel_connector = intel_connector_alloc();
1952 if (!intel_connector) {
1957 encoder = &intel_dsi->base;
1958 intel_dsi->attached_connector = intel_connector;
1959 connector = &intel_connector->base;
1961 /* register DSI encoder with DRM subsystem */
1962 drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs,
1963 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1965 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1966 encoder->pre_enable = gen11_dsi_pre_enable;
1967 encoder->enable = gen11_dsi_enable;
1968 encoder->disable = gen11_dsi_disable;
1969 encoder->post_disable = gen11_dsi_post_disable;
1970 encoder->port = port;
1971 encoder->get_config = gen11_dsi_get_config;
1972 encoder->sync_state = gen11_dsi_sync_state;
1973 encoder->update_pipe = intel_backlight_update;
1974 encoder->compute_config = gen11_dsi_compute_config;
1975 encoder->get_hw_state = gen11_dsi_get_hw_state;
1976 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1977 encoder->type = INTEL_OUTPUT_DSI;
1978 encoder->cloneable = 0;
1979 encoder->pipe_mask = ~0;
1980 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1981 encoder->get_power_domains = gen11_dsi_get_power_domains;
1982 encoder->disable_clock = gen11_dsi_gate_clocks;
1983 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
1984 encoder->shutdown = intel_dsi_shutdown;
1986 /* register DSI connector with DRM subsystem */
1987 drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs,
1988 DRM_MODE_CONNECTOR_DSI);
1989 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1990 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1991 intel_connector->get_hw_state = intel_connector_get_hw_state;
1993 /* attach connector to encoder */
1994 intel_connector_attach_encoder(intel_connector, encoder);
1996 intel_dsi->panel_power_off_time = ktime_get_boottime();
1998 encoder->devdata = intel_bios_encoder_data_lookup(dev_priv, port);
1999 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL);
2001 mutex_lock(&dev_priv->drm.mode_config.mutex);
2002 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
2003 mutex_unlock(&dev_priv->drm.mode_config.mutex);
2005 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2006 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
2010 intel_panel_init(intel_connector, NULL);
2012 intel_backlight_setup(intel_connector, INVALID_PIPE);
2014 if (intel_connector->panel.vbt.dsi.config->dual_link)
2015 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
2017 intel_dsi->ports = BIT(port);
2019 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
2020 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
2022 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
2023 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
2025 for_each_dsi_port(port, intel_dsi->ports) {
2026 struct intel_dsi_host *host;
2028 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
2032 intel_dsi->dsi_hosts[port] = host;
2035 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2036 drm_dbg_kms(&dev_priv->drm, "no device found\n");
2040 icl_dphy_param_init(intel_dsi);
2042 icl_dsi_add_properties(intel_connector);
2046 drm_connector_cleanup(connector);
2047 drm_encoder_cleanup(&encoder->base);
2049 kfree(intel_connector);