2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
8 * Based on drivers/media/video/s5p-tv/mixer_reg.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
19 #include "regs-mixer.h"
22 #include <linux/kernel.h>
23 #include <linux/spinlock.h>
24 #include <linux/wait.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/clk.h>
32 #include <linux/regulator/consumer.h>
34 #include <drm/exynos_drm.h>
36 #include "exynos_drm_drv.h"
37 #include "exynos_drm_crtc.h"
38 #include "exynos_drm_hdmi.h"
39 #include "exynos_drm_iommu.h"
41 #define get_mixer_context(dev) platform_get_drvdata(to_platform_device(dev))
43 struct hdmi_win_data {
45 dma_addr_t chroma_dma_addr;
46 uint32_t pixel_format;
50 unsigned int crtc_width;
51 unsigned int crtc_height;
54 unsigned int fb_width;
55 unsigned int fb_height;
56 unsigned int src_width;
57 unsigned int src_height;
58 unsigned int mode_width;
59 unsigned int mode_height;
60 unsigned int scan_flags;
65 struct mixer_resources {
67 void __iomem *mixer_regs;
68 void __iomem *vp_regs;
72 struct clk *sclk_mixer;
73 struct clk *sclk_hdmi;
77 enum mixer_version_id {
83 struct mixer_context {
85 struct drm_device *drm_dev;
92 struct mutex mixer_mutex;
93 struct mixer_resources mixer_res;
94 struct hdmi_win_data win_data[MIXER_WIN_NR];
95 enum mixer_version_id mxr_ver;
97 wait_queue_head_t wait_vsync_queue;
98 atomic_t wait_vsync_event;
101 struct mixer_drv_data {
102 enum mixer_version_id version;
106 static const u8 filter_y_horiz_tap8[] = {
107 0, -1, -1, -1, -1, -1, -1, -1,
108 -1, -1, -1, -1, -1, 0, 0, 0,
109 0, 2, 4, 5, 6, 6, 6, 6,
110 6, 5, 5, 4, 3, 2, 1, 1,
111 0, -6, -12, -16, -18, -20, -21, -20,
112 -20, -18, -16, -13, -10, -8, -5, -2,
113 127, 126, 125, 121, 114, 107, 99, 89,
114 79, 68, 57, 46, 35, 25, 16, 8,
117 static const u8 filter_y_vert_tap4[] = {
118 0, -3, -6, -8, -8, -8, -8, -7,
119 -6, -5, -4, -3, -2, -1, -1, 0,
120 127, 126, 124, 118, 111, 102, 92, 81,
121 70, 59, 48, 37, 27, 19, 11, 5,
122 0, 5, 11, 19, 27, 37, 48, 59,
123 70, 81, 92, 102, 111, 118, 124, 126,
124 0, 0, -1, -1, -2, -3, -4, -5,
125 -6, -7, -8, -8, -8, -8, -6, -3,
128 static const u8 filter_cr_horiz_tap4[] = {
129 0, -3, -6, -8, -8, -8, -8, -7,
130 -6, -5, -4, -3, -2, -1, -1, 0,
131 127, 126, 124, 118, 111, 102, 92, 81,
132 70, 59, 48, 37, 27, 19, 11, 5,
135 static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
137 return readl(res->vp_regs + reg_id);
140 static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
143 writel(val, res->vp_regs + reg_id);
146 static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
149 u32 old = vp_reg_read(res, reg_id);
151 val = (val & mask) | (old & ~mask);
152 writel(val, res->vp_regs + reg_id);
155 static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
157 return readl(res->mixer_regs + reg_id);
160 static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
163 writel(val, res->mixer_regs + reg_id);
166 static inline void mixer_reg_writemask(struct mixer_resources *res,
167 u32 reg_id, u32 val, u32 mask)
169 u32 old = mixer_reg_read(res, reg_id);
171 val = (val & mask) | (old & ~mask);
172 writel(val, res->mixer_regs + reg_id);
175 static void mixer_regs_dump(struct mixer_context *ctx)
177 #define DUMPREG(reg_id) \
179 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
180 (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
186 DUMPREG(MXR_INT_STATUS);
188 DUMPREG(MXR_LAYER_CFG);
189 DUMPREG(MXR_VIDEO_CFG);
191 DUMPREG(MXR_GRAPHIC0_CFG);
192 DUMPREG(MXR_GRAPHIC0_BASE);
193 DUMPREG(MXR_GRAPHIC0_SPAN);
194 DUMPREG(MXR_GRAPHIC0_WH);
195 DUMPREG(MXR_GRAPHIC0_SXY);
196 DUMPREG(MXR_GRAPHIC0_DXY);
198 DUMPREG(MXR_GRAPHIC1_CFG);
199 DUMPREG(MXR_GRAPHIC1_BASE);
200 DUMPREG(MXR_GRAPHIC1_SPAN);
201 DUMPREG(MXR_GRAPHIC1_WH);
202 DUMPREG(MXR_GRAPHIC1_SXY);
203 DUMPREG(MXR_GRAPHIC1_DXY);
207 static void vp_regs_dump(struct mixer_context *ctx)
209 #define DUMPREG(reg_id) \
211 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
212 (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
217 DUMPREG(VP_SHADOW_UPDATE);
218 DUMPREG(VP_FIELD_ID);
220 DUMPREG(VP_IMG_SIZE_Y);
221 DUMPREG(VP_IMG_SIZE_C);
222 DUMPREG(VP_PER_RATE_CTRL);
223 DUMPREG(VP_TOP_Y_PTR);
224 DUMPREG(VP_BOT_Y_PTR);
225 DUMPREG(VP_TOP_C_PTR);
226 DUMPREG(VP_BOT_C_PTR);
227 DUMPREG(VP_ENDIAN_MODE);
228 DUMPREG(VP_SRC_H_POSITION);
229 DUMPREG(VP_SRC_V_POSITION);
230 DUMPREG(VP_SRC_WIDTH);
231 DUMPREG(VP_SRC_HEIGHT);
232 DUMPREG(VP_DST_H_POSITION);
233 DUMPREG(VP_DST_V_POSITION);
234 DUMPREG(VP_DST_WIDTH);
235 DUMPREG(VP_DST_HEIGHT);
242 static inline void vp_filter_set(struct mixer_resources *res,
243 int reg_id, const u8 *data, unsigned int size)
245 /* assure 4-byte align */
247 for (; size; size -= 4, reg_id += 4, data += 4) {
248 u32 val = (data[0] << 24) | (data[1] << 16) |
249 (data[2] << 8) | data[3];
250 vp_reg_write(res, reg_id, val);
254 static void vp_default_filter(struct mixer_resources *res)
256 vp_filter_set(res, VP_POLY8_Y0_LL,
257 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
258 vp_filter_set(res, VP_POLY4_Y0_LL,
259 filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
260 vp_filter_set(res, VP_POLY4_C0_LL,
261 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
264 static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
266 struct mixer_resources *res = &ctx->mixer_res;
268 /* block update on vsync */
269 mixer_reg_writemask(res, MXR_STATUS, enable ?
270 MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
273 vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
274 VP_SHADOW_UPDATE_ENABLE : 0);
277 static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
279 struct mixer_resources *res = &ctx->mixer_res;
282 /* choosing between interlace and progressive mode */
283 val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
284 MXR_CFG_SCAN_PROGRASSIVE);
286 if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
287 /* choosing between proper HD and SD mode */
289 val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
290 else if (height <= 576)
291 val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
292 else if (height <= 720)
293 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
294 else if (height <= 1080)
295 val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
297 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
300 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
303 static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
305 struct mixer_resources *res = &ctx->mixer_res;
309 val = MXR_CFG_RGB601_0_255;
310 } else if (height == 576) {
311 val = MXR_CFG_RGB601_0_255;
312 } else if (height == 720) {
313 val = MXR_CFG_RGB709_16_235;
314 mixer_reg_write(res, MXR_CM_COEFF_Y,
315 (1 << 30) | (94 << 20) | (314 << 10) |
317 mixer_reg_write(res, MXR_CM_COEFF_CB,
318 (972 << 20) | (851 << 10) | (225 << 0));
319 mixer_reg_write(res, MXR_CM_COEFF_CR,
320 (225 << 20) | (820 << 10) | (1004 << 0));
321 } else if (height == 1080) {
322 val = MXR_CFG_RGB709_16_235;
323 mixer_reg_write(res, MXR_CM_COEFF_Y,
324 (1 << 30) | (94 << 20) | (314 << 10) |
326 mixer_reg_write(res, MXR_CM_COEFF_CB,
327 (972 << 20) | (851 << 10) | (225 << 0));
328 mixer_reg_write(res, MXR_CM_COEFF_CR,
329 (225 << 20) | (820 << 10) | (1004 << 0));
331 val = MXR_CFG_RGB709_16_235;
332 mixer_reg_write(res, MXR_CM_COEFF_Y,
333 (1 << 30) | (94 << 20) | (314 << 10) |
335 mixer_reg_write(res, MXR_CM_COEFF_CB,
336 (972 << 20) | (851 << 10) | (225 << 0));
337 mixer_reg_write(res, MXR_CM_COEFF_CR,
338 (225 << 20) | (820 << 10) | (1004 << 0));
341 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
344 static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable)
346 struct mixer_resources *res = &ctx->mixer_res;
347 u32 val = enable ? ~0 : 0;
351 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
354 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
357 if (ctx->vp_enabled) {
358 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
359 mixer_reg_writemask(res, MXR_CFG, val,
366 static void mixer_run(struct mixer_context *ctx)
368 struct mixer_resources *res = &ctx->mixer_res;
370 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
372 mixer_regs_dump(ctx);
375 static void vp_video_buffer(struct mixer_context *ctx, int win)
377 struct mixer_resources *res = &ctx->mixer_res;
379 struct hdmi_win_data *win_data;
380 unsigned int x_ratio, y_ratio;
381 unsigned int buf_num = 1;
382 dma_addr_t luma_addr[2], chroma_addr[2];
383 bool tiled_mode = false;
384 bool crcb_mode = false;
387 win_data = &ctx->win_data[win];
389 switch (win_data->pixel_format) {
390 case DRM_FORMAT_NV12MT:
392 case DRM_FORMAT_NV12:
396 /* TODO: single buffer format NV12, NV21 */
398 /* ignore pixel format at disable time */
399 if (!win_data->dma_addr)
402 DRM_ERROR("pixel format for vp is wrong [%d].\n",
403 win_data->pixel_format);
407 /* scaling feature: (src << 16) / dst */
408 x_ratio = (win_data->src_width << 16) / win_data->crtc_width;
409 y_ratio = (win_data->src_height << 16) / win_data->crtc_height;
412 luma_addr[0] = win_data->dma_addr;
413 chroma_addr[0] = win_data->chroma_dma_addr;
415 luma_addr[0] = win_data->dma_addr;
416 chroma_addr[0] = win_data->dma_addr
417 + (win_data->fb_width * win_data->fb_height);
420 if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE) {
421 ctx->interlace = true;
423 luma_addr[1] = luma_addr[0] + 0x40;
424 chroma_addr[1] = chroma_addr[0] + 0x40;
426 luma_addr[1] = luma_addr[0] + win_data->fb_width;
427 chroma_addr[1] = chroma_addr[0] + win_data->fb_width;
430 ctx->interlace = false;
435 spin_lock_irqsave(&res->reg_slock, flags);
436 mixer_vsync_set_update(ctx, false);
438 /* interlace or progressive scan mode */
439 val = (ctx->interlace ? ~0 : 0);
440 vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
443 val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
444 val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
445 vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
447 /* setting size of input image */
448 vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(win_data->fb_width) |
449 VP_IMG_VSIZE(win_data->fb_height));
450 /* chroma height has to reduced by 2 to avoid chroma distorions */
451 vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(win_data->fb_width) |
452 VP_IMG_VSIZE(win_data->fb_height / 2));
454 vp_reg_write(res, VP_SRC_WIDTH, win_data->src_width);
455 vp_reg_write(res, VP_SRC_HEIGHT, win_data->src_height);
456 vp_reg_write(res, VP_SRC_H_POSITION,
457 VP_SRC_H_POSITION_VAL(win_data->fb_x));
458 vp_reg_write(res, VP_SRC_V_POSITION, win_data->fb_y);
460 vp_reg_write(res, VP_DST_WIDTH, win_data->crtc_width);
461 vp_reg_write(res, VP_DST_H_POSITION, win_data->crtc_x);
462 if (ctx->interlace) {
463 vp_reg_write(res, VP_DST_HEIGHT, win_data->crtc_height / 2);
464 vp_reg_write(res, VP_DST_V_POSITION, win_data->crtc_y / 2);
466 vp_reg_write(res, VP_DST_HEIGHT, win_data->crtc_height);
467 vp_reg_write(res, VP_DST_V_POSITION, win_data->crtc_y);
470 vp_reg_write(res, VP_H_RATIO, x_ratio);
471 vp_reg_write(res, VP_V_RATIO, y_ratio);
473 vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
475 /* set buffer address to vp */
476 vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
477 vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
478 vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
479 vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);
481 mixer_cfg_scan(ctx, win_data->mode_height);
482 mixer_cfg_rgb_fmt(ctx, win_data->mode_height);
483 mixer_cfg_layer(ctx, win, true);
486 mixer_vsync_set_update(ctx, true);
487 spin_unlock_irqrestore(&res->reg_slock, flags);
492 static void mixer_layer_update(struct mixer_context *ctx)
494 struct mixer_resources *res = &ctx->mixer_res;
497 val = mixer_reg_read(res, MXR_CFG);
499 /* allow one update per vsync only */
500 if (!(val & MXR_CFG_LAYER_UPDATE_COUNT_MASK))
501 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
504 static void mixer_graph_buffer(struct mixer_context *ctx, int win)
506 struct mixer_resources *res = &ctx->mixer_res;
508 struct hdmi_win_data *win_data;
509 unsigned int x_ratio, y_ratio;
510 unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
515 win_data = &ctx->win_data[win];
522 switch (win_data->bpp) {
533 /* 2x scaling feature */
537 dst_x_offset = win_data->crtc_x;
538 dst_y_offset = win_data->crtc_y;
540 /* converting dma address base and source offset */
541 dma_addr = win_data->dma_addr
542 + (win_data->fb_x * win_data->bpp >> 3)
543 + (win_data->fb_y * win_data->fb_width * win_data->bpp >> 3);
547 if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE)
548 ctx->interlace = true;
550 ctx->interlace = false;
552 spin_lock_irqsave(&res->reg_slock, flags);
553 mixer_vsync_set_update(ctx, false);
556 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
557 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
560 mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width);
562 /* setup display size */
563 if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
564 win == MIXER_DEFAULT_WIN) {
565 val = MXR_MXR_RES_HEIGHT(win_data->fb_height);
566 val |= MXR_MXR_RES_WIDTH(win_data->fb_width);
567 mixer_reg_write(res, MXR_RESOLUTION, val);
570 val = MXR_GRP_WH_WIDTH(win_data->crtc_width);
571 val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height);
572 val |= MXR_GRP_WH_H_SCALE(x_ratio);
573 val |= MXR_GRP_WH_V_SCALE(y_ratio);
574 mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);
576 /* setup offsets in source image */
577 val = MXR_GRP_SXY_SX(src_x_offset);
578 val |= MXR_GRP_SXY_SY(src_y_offset);
579 mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);
581 /* setup offsets in display image */
582 val = MXR_GRP_DXY_DX(dst_x_offset);
583 val |= MXR_GRP_DXY_DY(dst_y_offset);
584 mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);
586 /* set buffer address to mixer */
587 mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);
589 mixer_cfg_scan(ctx, win_data->mode_height);
590 mixer_cfg_rgb_fmt(ctx, win_data->mode_height);
591 mixer_cfg_layer(ctx, win, true);
593 /* layer update mandatory for mixer 16.0.33.0 */
594 if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
595 ctx->mxr_ver == MXR_VER_128_0_0_184)
596 mixer_layer_update(ctx);
600 mixer_vsync_set_update(ctx, true);
601 spin_unlock_irqrestore(&res->reg_slock, flags);
604 static void vp_win_reset(struct mixer_context *ctx)
606 struct mixer_resources *res = &ctx->mixer_res;
609 vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
610 for (tries = 100; tries; --tries) {
611 /* waiting until VP_SRESET_PROCESSING is 0 */
612 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
614 usleep_range(10000, 12000);
616 WARN(tries == 0, "failed to reset Video Processor\n");
619 static void mixer_win_reset(struct mixer_context *ctx)
621 struct mixer_resources *res = &ctx->mixer_res;
623 u32 val; /* value stored to register */
625 spin_lock_irqsave(&res->reg_slock, flags);
626 mixer_vsync_set_update(ctx, false);
628 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
630 /* set output in RGB888 mode */
631 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
633 /* 16 beat burst in DMA */
634 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
635 MXR_STATUS_BURST_MASK);
637 /* setting default layer priority: layer1 > layer0 > video
638 * because typical usage scenario would be
640 * layer0 - framebuffer
641 * video - video overlay
643 val = MXR_LAYER_CFG_GRP1_VAL(3);
644 val |= MXR_LAYER_CFG_GRP0_VAL(2);
646 val |= MXR_LAYER_CFG_VP_VAL(1);
647 mixer_reg_write(res, MXR_LAYER_CFG, val);
649 /* setting background color */
650 mixer_reg_write(res, MXR_BG_COLOR0, 0x008080);
651 mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);
652 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
654 /* setting graphical layers */
655 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
656 val |= MXR_GRP_CFG_WIN_BLEND_EN;
657 val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
659 /* Don't blend layer 0 onto the mixer background */
660 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
662 /* Blend layer 1 into layer 0 */
663 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
664 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
665 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
667 /* setting video layers */
668 val = MXR_GRP_CFG_ALPHA_VAL(0);
669 mixer_reg_write(res, MXR_VIDEO_CFG, val);
671 if (ctx->vp_enabled) {
672 /* configuration of Video Processor Registers */
674 vp_default_filter(res);
677 /* disable all layers */
678 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
679 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
681 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
683 mixer_vsync_set_update(ctx, true);
684 spin_unlock_irqrestore(&res->reg_slock, flags);
687 static int mixer_iommu_on(void *ctx, bool enable)
689 struct exynos_drm_hdmi_context *drm_hdmi_ctx;
690 struct mixer_context *mdata = ctx;
691 struct drm_device *drm_dev;
693 drm_hdmi_ctx = mdata->parent_ctx;
694 drm_dev = drm_hdmi_ctx->drm_dev;
696 if (is_drm_iommu_supported(drm_dev)) {
698 return drm_iommu_attach_device(drm_dev, mdata->dev);
700 drm_iommu_detach_device(drm_dev, mdata->dev);
705 static int mixer_enable_vblank(void *ctx, int pipe)
707 struct mixer_context *mixer_ctx = ctx;
708 struct mixer_resources *res = &mixer_ctx->mixer_res;
710 mixer_ctx->pipe = pipe;
712 /* enable vsync interrupt */
713 mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
719 static void mixer_disable_vblank(void *ctx)
721 struct mixer_context *mixer_ctx = ctx;
722 struct mixer_resources *res = &mixer_ctx->mixer_res;
724 /* disable vsync interrupt */
725 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
728 static void mixer_win_mode_set(void *ctx,
729 struct exynos_drm_overlay *overlay)
731 struct mixer_context *mixer_ctx = ctx;
732 struct hdmi_win_data *win_data;
736 DRM_ERROR("overlay is NULL\n");
740 DRM_DEBUG_KMS("set [%d]x[%d] at (%d,%d) to [%d]x[%d] at (%d,%d)\n",
741 overlay->fb_width, overlay->fb_height,
742 overlay->fb_x, overlay->fb_y,
743 overlay->crtc_width, overlay->crtc_height,
744 overlay->crtc_x, overlay->crtc_y);
747 if (win == DEFAULT_ZPOS)
748 win = MIXER_DEFAULT_WIN;
750 if (win < 0 || win >= MIXER_WIN_NR) {
751 DRM_ERROR("mixer window[%d] is wrong\n", win);
755 win_data = &mixer_ctx->win_data[win];
757 win_data->dma_addr = overlay->dma_addr[0];
758 win_data->chroma_dma_addr = overlay->dma_addr[1];
759 win_data->pixel_format = overlay->pixel_format;
760 win_data->bpp = overlay->bpp;
762 win_data->crtc_x = overlay->crtc_x;
763 win_data->crtc_y = overlay->crtc_y;
764 win_data->crtc_width = overlay->crtc_width;
765 win_data->crtc_height = overlay->crtc_height;
767 win_data->fb_x = overlay->fb_x;
768 win_data->fb_y = overlay->fb_y;
769 win_data->fb_width = overlay->fb_width;
770 win_data->fb_height = overlay->fb_height;
771 win_data->src_width = overlay->src_width;
772 win_data->src_height = overlay->src_height;
774 win_data->mode_width = overlay->mode_width;
775 win_data->mode_height = overlay->mode_height;
777 win_data->scan_flags = overlay->scan_flag;
780 static void mixer_win_commit(void *ctx, int win)
782 struct mixer_context *mixer_ctx = ctx;
784 DRM_DEBUG_KMS("win: %d\n", win);
786 mutex_lock(&mixer_ctx->mixer_mutex);
787 if (!mixer_ctx->powered) {
788 mutex_unlock(&mixer_ctx->mixer_mutex);
791 mutex_unlock(&mixer_ctx->mixer_mutex);
793 if (win > 1 && mixer_ctx->vp_enabled)
794 vp_video_buffer(mixer_ctx, win);
796 mixer_graph_buffer(mixer_ctx, win);
798 mixer_ctx->win_data[win].enabled = true;
801 static void mixer_win_disable(void *ctx, int win)
803 struct mixer_context *mixer_ctx = ctx;
804 struct mixer_resources *res = &mixer_ctx->mixer_res;
807 DRM_DEBUG_KMS("win: %d\n", win);
809 mutex_lock(&mixer_ctx->mixer_mutex);
810 if (!mixer_ctx->powered) {
811 mutex_unlock(&mixer_ctx->mixer_mutex);
812 mixer_ctx->win_data[win].resume = false;
815 mutex_unlock(&mixer_ctx->mixer_mutex);
817 spin_lock_irqsave(&res->reg_slock, flags);
818 mixer_vsync_set_update(mixer_ctx, false);
820 mixer_cfg_layer(mixer_ctx, win, false);
822 mixer_vsync_set_update(mixer_ctx, true);
823 spin_unlock_irqrestore(&res->reg_slock, flags);
825 mixer_ctx->win_data[win].enabled = false;
828 static int mixer_check_mode(void *ctx, struct drm_display_mode *mode)
830 struct mixer_context *mixer_ctx = ctx;
836 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n",
837 mode->hdisplay, mode->vdisplay, mode->vrefresh,
838 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
840 if (mixer_ctx->mxr_ver == MXR_VER_0_0_0_16 ||
841 mixer_ctx->mxr_ver == MXR_VER_128_0_0_184)
844 if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
845 (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
846 (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
851 static void mixer_wait_for_vblank(void *ctx)
853 struct mixer_context *mixer_ctx = ctx;
855 mutex_lock(&mixer_ctx->mixer_mutex);
856 if (!mixer_ctx->powered) {
857 mutex_unlock(&mixer_ctx->mixer_mutex);
860 mutex_unlock(&mixer_ctx->mixer_mutex);
862 atomic_set(&mixer_ctx->wait_vsync_event, 1);
865 * wait for MIXER to signal VSYNC interrupt or return after
866 * timeout which is set to 50ms (refresh rate of 20).
868 if (!wait_event_timeout(mixer_ctx->wait_vsync_queue,
869 !atomic_read(&mixer_ctx->wait_vsync_event),
871 DRM_DEBUG_KMS("vblank wait timed out.\n");
874 static void mixer_window_suspend(struct mixer_context *ctx)
876 struct hdmi_win_data *win_data;
879 for (i = 0; i < MIXER_WIN_NR; i++) {
880 win_data = &ctx->win_data[i];
881 win_data->resume = win_data->enabled;
882 mixer_win_disable(ctx, i);
884 mixer_wait_for_vblank(ctx);
887 static void mixer_window_resume(struct mixer_context *ctx)
889 struct hdmi_win_data *win_data;
892 for (i = 0; i < MIXER_WIN_NR; i++) {
893 win_data = &ctx->win_data[i];
894 win_data->enabled = win_data->resume;
895 win_data->resume = false;
899 static void mixer_poweron(struct mixer_context *ctx)
901 struct mixer_resources *res = &ctx->mixer_res;
903 mutex_lock(&ctx->mixer_mutex);
905 mutex_unlock(&ctx->mixer_mutex);
909 mutex_unlock(&ctx->mixer_mutex);
911 clk_prepare_enable(res->mixer);
912 if (ctx->vp_enabled) {
913 clk_prepare_enable(res->vp);
914 clk_prepare_enable(res->sclk_mixer);
917 mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
918 mixer_win_reset(ctx);
920 mixer_window_resume(ctx);
923 static void mixer_poweroff(struct mixer_context *ctx)
925 struct mixer_resources *res = &ctx->mixer_res;
927 mutex_lock(&ctx->mixer_mutex);
930 mutex_unlock(&ctx->mixer_mutex);
932 mixer_window_suspend(ctx);
934 ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
936 clk_disable_unprepare(res->mixer);
937 if (ctx->vp_enabled) {
938 clk_disable_unprepare(res->vp);
939 clk_disable_unprepare(res->sclk_mixer);
942 mutex_lock(&ctx->mixer_mutex);
943 ctx->powered = false;
946 mutex_unlock(&ctx->mixer_mutex);
949 static void mixer_dpms(void *ctx, int mode)
951 struct mixer_context *mixer_ctx = ctx;
954 case DRM_MODE_DPMS_ON:
955 if (pm_runtime_suspended(mixer_ctx->dev))
956 pm_runtime_get_sync(mixer_ctx->dev);
958 case DRM_MODE_DPMS_STANDBY:
959 case DRM_MODE_DPMS_SUSPEND:
960 case DRM_MODE_DPMS_OFF:
961 if (!pm_runtime_suspended(mixer_ctx->dev))
962 pm_runtime_put_sync(mixer_ctx->dev);
965 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
970 static struct exynos_mixer_ops mixer_ops = {
972 .iommu_on = mixer_iommu_on,
973 .enable_vblank = mixer_enable_vblank,
974 .disable_vblank = mixer_disable_vblank,
975 .wait_for_vblank = mixer_wait_for_vblank,
979 .win_mode_set = mixer_win_mode_set,
980 .win_commit = mixer_win_commit,
981 .win_disable = mixer_win_disable,
984 .check_mode = mixer_check_mode,
987 static irqreturn_t mixer_irq_handler(int irq, void *arg)
989 struct exynos_drm_hdmi_context *drm_hdmi_ctx = arg;
990 struct mixer_context *ctx = drm_hdmi_ctx->ctx;
991 struct mixer_resources *res = &ctx->mixer_res;
992 u32 val, base, shadow;
994 spin_lock(&res->reg_slock);
996 /* read interrupt status for handling and clearing flags for VSYNC */
997 val = mixer_reg_read(res, MXR_INT_STATUS);
1000 if (val & MXR_INT_STATUS_VSYNC) {
1001 /* interlace scan need to check shadow register */
1002 if (ctx->interlace) {
1003 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
1004 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
1008 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
1009 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
1014 drm_handle_vblank(drm_hdmi_ctx->drm_dev, ctx->pipe);
1015 exynos_drm_crtc_finish_pageflip(drm_hdmi_ctx->drm_dev,
1018 /* set wait vsync event to zero and wake up queue. */
1019 if (atomic_read(&ctx->wait_vsync_event)) {
1020 atomic_set(&ctx->wait_vsync_event, 0);
1021 DRM_WAKEUP(&ctx->wait_vsync_queue);
1026 /* clear interrupts */
1027 if (~val & MXR_INT_EN_VSYNC) {
1028 /* vsync interrupt use different bit for read and clear */
1029 val &= ~MXR_INT_EN_VSYNC;
1030 val |= MXR_INT_CLEAR_VSYNC;
1032 mixer_reg_write(res, MXR_INT_STATUS, val);
1034 spin_unlock(&res->reg_slock);
1039 static int mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
1040 struct platform_device *pdev)
1042 struct mixer_context *mixer_ctx = ctx->ctx;
1043 struct device *dev = &pdev->dev;
1044 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
1045 struct resource *res;
1048 spin_lock_init(&mixer_res->reg_slock);
1050 mixer_res->mixer = devm_clk_get(dev, "mixer");
1051 if (IS_ERR(mixer_res->mixer)) {
1052 dev_err(dev, "failed to get clock 'mixer'\n");
1056 mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
1057 if (IS_ERR(mixer_res->sclk_hdmi)) {
1058 dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
1061 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1063 dev_err(dev, "get memory resource failed.\n");
1067 mixer_res->mixer_regs = devm_ioremap(dev, res->start,
1068 resource_size(res));
1069 if (mixer_res->mixer_regs == NULL) {
1070 dev_err(dev, "register mapping failed.\n");
1074 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1076 dev_err(dev, "get interrupt resource failed.\n");
1080 ret = devm_request_irq(dev, res->start, mixer_irq_handler,
1081 0, "drm_mixer", ctx);
1083 dev_err(dev, "request interrupt failed.\n");
1086 mixer_res->irq = res->start;
1091 static int vp_resources_init(struct exynos_drm_hdmi_context *ctx,
1092 struct platform_device *pdev)
1094 struct mixer_context *mixer_ctx = ctx->ctx;
1095 struct device *dev = &pdev->dev;
1096 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
1097 struct resource *res;
1099 mixer_res->vp = devm_clk_get(dev, "vp");
1100 if (IS_ERR(mixer_res->vp)) {
1101 dev_err(dev, "failed to get clock 'vp'\n");
1104 mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
1105 if (IS_ERR(mixer_res->sclk_mixer)) {
1106 dev_err(dev, "failed to get clock 'sclk_mixer'\n");
1109 mixer_res->sclk_dac = devm_clk_get(dev, "sclk_dac");
1110 if (IS_ERR(mixer_res->sclk_dac)) {
1111 dev_err(dev, "failed to get clock 'sclk_dac'\n");
1115 if (mixer_res->sclk_hdmi)
1116 clk_set_parent(mixer_res->sclk_mixer, mixer_res->sclk_hdmi);
1118 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1120 dev_err(dev, "get memory resource failed.\n");
1124 mixer_res->vp_regs = devm_ioremap(dev, res->start,
1125 resource_size(res));
1126 if (mixer_res->vp_regs == NULL) {
1127 dev_err(dev, "register mapping failed.\n");
1134 static struct mixer_drv_data exynos5420_mxr_drv_data = {
1135 .version = MXR_VER_128_0_0_184,
1139 static struct mixer_drv_data exynos5250_mxr_drv_data = {
1140 .version = MXR_VER_16_0_33_0,
1144 static struct mixer_drv_data exynos4210_mxr_drv_data = {
1145 .version = MXR_VER_0_0_0_16,
1149 static struct platform_device_id mixer_driver_types[] = {
1151 .name = "s5p-mixer",
1152 .driver_data = (unsigned long)&exynos4210_mxr_drv_data,
1154 .name = "exynos5-mixer",
1155 .driver_data = (unsigned long)&exynos5250_mxr_drv_data,
1161 static struct of_device_id mixer_match_types[] = {
1163 .compatible = "samsung,exynos5-mixer",
1164 .data = &exynos5250_mxr_drv_data,
1166 .compatible = "samsung,exynos5250-mixer",
1167 .data = &exynos5250_mxr_drv_data,
1169 .compatible = "samsung,exynos5420-mixer",
1170 .data = &exynos5420_mxr_drv_data,
1176 static int mixer_probe(struct platform_device *pdev)
1178 struct device *dev = &pdev->dev;
1179 struct exynos_drm_hdmi_context *drm_hdmi_ctx;
1180 struct mixer_context *ctx;
1181 struct mixer_drv_data *drv;
1184 dev_info(dev, "probe start\n");
1186 drm_hdmi_ctx = devm_kzalloc(dev, sizeof(*drm_hdmi_ctx),
1188 if (!drm_hdmi_ctx) {
1189 DRM_ERROR("failed to allocate common hdmi context.\n");
1193 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1195 DRM_ERROR("failed to alloc mixer context.\n");
1199 mutex_init(&ctx->mixer_mutex);
1202 const struct of_device_id *match;
1203 match = of_match_node(mixer_match_types, dev->of_node);
1204 drv = (struct mixer_drv_data *)match->data;
1206 drv = (struct mixer_drv_data *)
1207 platform_get_device_id(pdev)->driver_data;
1211 ctx->parent_ctx = (void *)drm_hdmi_ctx;
1212 drm_hdmi_ctx->ctx = (void *)ctx;
1213 ctx->vp_enabled = drv->is_vp_enabled;
1214 ctx->mxr_ver = drv->version;
1215 DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
1216 atomic_set(&ctx->wait_vsync_event, 0);
1218 platform_set_drvdata(pdev, drm_hdmi_ctx);
1220 /* acquire resources: regs, irqs, clocks */
1221 ret = mixer_resources_init(drm_hdmi_ctx, pdev);
1223 DRM_ERROR("mixer_resources_init failed\n");
1227 if (ctx->vp_enabled) {
1228 /* acquire vp resources: regs, irqs, clocks */
1229 ret = vp_resources_init(drm_hdmi_ctx, pdev);
1231 DRM_ERROR("vp_resources_init failed\n");
1236 /* attach mixer driver to common hdmi. */
1237 exynos_mixer_drv_attach(drm_hdmi_ctx);
1239 /* register specific callback point to common hdmi. */
1240 exynos_mixer_ops_register(&mixer_ops);
1242 pm_runtime_enable(dev);
1248 dev_info(dev, "probe failed\n");
1252 static int mixer_remove(struct platform_device *pdev)
1254 dev_info(&pdev->dev, "remove successful\n");
1256 pm_runtime_disable(&pdev->dev);
1261 #ifdef CONFIG_PM_SLEEP
1262 static int mixer_suspend(struct device *dev)
1264 struct exynos_drm_hdmi_context *drm_hdmi_ctx = get_mixer_context(dev);
1265 struct mixer_context *ctx = drm_hdmi_ctx->ctx;
1267 if (pm_runtime_suspended(dev)) {
1268 DRM_DEBUG_KMS("Already suspended\n");
1272 mixer_poweroff(ctx);
1277 static int mixer_resume(struct device *dev)
1279 struct exynos_drm_hdmi_context *drm_hdmi_ctx = get_mixer_context(dev);
1280 struct mixer_context *ctx = drm_hdmi_ctx->ctx;
1282 if (!pm_runtime_suspended(dev)) {
1283 DRM_DEBUG_KMS("Already resumed\n");
1293 #ifdef CONFIG_PM_RUNTIME
1294 static int mixer_runtime_suspend(struct device *dev)
1296 struct exynos_drm_hdmi_context *drm_hdmi_ctx = get_mixer_context(dev);
1297 struct mixer_context *ctx = drm_hdmi_ctx->ctx;
1299 mixer_poweroff(ctx);
1304 static int mixer_runtime_resume(struct device *dev)
1306 struct exynos_drm_hdmi_context *drm_hdmi_ctx = get_mixer_context(dev);
1307 struct mixer_context *ctx = drm_hdmi_ctx->ctx;
1315 static const struct dev_pm_ops mixer_pm_ops = {
1316 SET_SYSTEM_SLEEP_PM_OPS(mixer_suspend, mixer_resume)
1317 SET_RUNTIME_PM_OPS(mixer_runtime_suspend, mixer_runtime_resume, NULL)
1320 struct platform_driver mixer_driver = {
1322 .name = "exynos-mixer",
1323 .owner = THIS_MODULE,
1324 .pm = &mixer_pm_ops,
1325 .of_match_table = mixer_match_types,
1327 .probe = mixer_probe,
1328 .remove = mixer_remove,
1329 .id_table = mixer_driver_types,