drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_edid.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_atomic_helper.h>
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/wait.h>
  26 #include <linux/i2c.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/clk.h>
  33 #include <linux/gpio/consumer.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/io.h>
  36 #include <linux/of_address.h>
  37 #include <linux/of_device.h>
  38 #include <linux/of_graph.h>
  39 #include <linux/hdmi.h>
  40 #include <linux/component.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <linux/regmap.h>
  43 #include <linux/extcon-provider.h>
  44 #include <sound/hdmi-codec.h>
  45 #include <drm/exynos_drm.h>
  46
  47 #include <media/cec-notifier.h>
  48
  49 #include "exynos_drm_crtc.h"
  50
  51 #define HOTPLUG_DEBOUNCE_MS             1100
  52
  53 enum hdmi_type {
  54         HDMI_TYPE13,
  55         HDMI_TYPE14,
  56         HDMI_TYPE_COUNT
  57 };
  58
  59 #define HDMI_MAPPED_BASE 0xffff0000
  60
  61 enum hdmi_mapped_regs {
  62         HDMI_PHY_STATUS = HDMI_MAPPED_BASE,
  63         HDMI_PHY_RSTOUT,
  64         HDMI_ACR_CON,
  65         HDMI_ACR_MCTS0,
  66         HDMI_ACR_CTS0,
  67         HDMI_ACR_N0
  68 };
  69
  70 static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = {
  71         { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 },
  72         { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT },
  73         { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON },
  74         { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 },
  75         { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 },
  76         { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 },
  77 };
  78
  79 static const char * const supply[] = {
  80         "vdd",
  81         "vdd_osc",
  82         "vdd_pll",
  83 };
  84
  85 struct hdmiphy_config {
  86         int pixel_clock;
  87         u8 conf[32];
  88 };
  89
  90 struct hdmiphy_configs {
  91         int count;
  92         const struct hdmiphy_config *data;
  93 };
  94
  95 struct string_array_spec {
  96         int count;
  97         const char * const *data;
  98 };
  99
 100 #define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a }
 101
 102 struct hdmi_driver_data {
 103         unsigned int type;
 104         unsigned int is_apb_phy:1;
 105         unsigned int has_sysreg:1;
 106         struct hdmiphy_configs phy_confs;
 107         struct string_array_spec clk_gates;
 108         /*
 109          * Array of triplets (p_off, p_on, clock), where p_off and p_on are
 110          * required parents of clock when HDMI-PHY is respectively off or on.
 111          */
 112         struct string_array_spec clk_muxes;
 113 };
 114
 115 struct hdmi_audio {
 116         struct platform_device          *pdev;
 117         struct hdmi_audio_infoframe     infoframe;
 118         struct hdmi_codec_params        params;
 119         bool                            mute;
 120 };
 121
 122 struct hdmi_context {
 123         struct drm_encoder              encoder;
 124         struct device                   *dev;
 125         struct drm_device               *drm_dev;
 126         struct drm_connector            connector;
 127         bool                            dvi_mode;
 128         struct delayed_work             hotplug_work;
 129         struct cec_notifier             *notifier;
 130         const struct hdmi_driver_data   *drv_data;
 131         struct extcon_dev               *edev;
 132
 133         void __iomem                    *regs;
 134         void __iomem                    *regs_hdmiphy;
 135         struct i2c_client               *hdmiphy_port;
 136         struct i2c_adapter              *ddc_adpt;
 137         struct gpio_desc                *hpd_gpio;
 138         int                             irq;
 139         struct regmap                   *pmureg;
 140         struct regmap                   *sysreg;
 141         struct clk                      **clk_gates;
 142         struct clk                      **clk_muxes;
 143         struct regulator_bulk_data      regul_bulk[ARRAY_SIZE(supply)];
 144         struct regulator                *reg_hdmi_en;
 145         struct exynos_drm_clk           phy_clk;
 146         struct drm_bridge               *bridge;
 147
 148         /* mutex protecting subsequent fields below */
 149         struct mutex                    mutex;
 150         struct hdmi_audio               audio;
 151         bool                            powered;
 152 };
 153
 154 static const unsigned int extcon_cable_list[] = {
 155         EXTCON_DISP_HDMI,
 156         EXTCON_NONE,
 157 };
 158
 159 static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
 160 {
 161         return container_of(e, struct hdmi_context, encoder);
 162 }
 163
 164 static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c)
 165 {
 166         return container_of(c, struct hdmi_context, connector);
 167 }
 168
 169 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
 170         {
 171                 .pixel_clock = 27000000,
 172                 .conf = {
 173                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 174                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 175                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 176                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
 177                 },
 178         },
 179         {
 180                 .pixel_clock = 27027000,
 181                 .conf = {
 182                         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 183                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 184                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 185                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
 186                 },
 187         },
 188         {
 189                 .pixel_clock = 74176000,
 190                 .conf = {
 191                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 192                         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 193                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 194                         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80,
 195                 },
 196         },
 197         {
 198                 .pixel_clock = 74250000,
 199                 .conf = {
 200                         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 201                         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 202                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 203                         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80,
 204                 },
 205         },
 206         {
 207                 .pixel_clock = 148500000,
 208                 .conf = {
 209                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 210                         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 211                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 212                         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80,
 213                 },
 214         },
 215 };
 216
 217 static const struct hdmiphy_config hdmiphy_v14_configs[] = {
 218         {
 219                 .pixel_clock = 25200000,
 220                 .conf = {
 221                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 222                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 223                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 224                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 225                 },
 226         },
 227         {
 228                 .pixel_clock = 27000000,
 229                 .conf = {
 230                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 231                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 232                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 233                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 234                 },
 235         },
 236         {
 237                 .pixel_clock = 27027000,
 238                 .conf = {
 239                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 240                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 241                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 242                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 243                 },
 244         },
 245         {
 246                 .pixel_clock = 36000000,
 247                 .conf = {
 248                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 249                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 250                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 251                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 252                 },
 253         },
 254         {
 255                 .pixel_clock = 40000000,
 256                 .conf = {
 257                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 258                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 259                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 260                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 261                 },
 262         },
 263         {
 264                 .pixel_clock = 65000000,
 265                 .conf = {
 266                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 267                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 268                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 269                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 270                 },
 271         },
 272         {
 273                 .pixel_clock = 71000000,
 274                 .conf = {
 275                         0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
 276                         0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 277                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 278                         0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 279                 },
 280         },
 281         {
 282                 .pixel_clock = 73250000,
 283                 .conf = {
 284                         0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
 285                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 286                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 287                         0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 288                 },
 289         },
 290         {
 291                 .pixel_clock = 74176000,
 292                 .conf = {
 293                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 294                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 295                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 296                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 297                 },
 298         },
 299         {
 300                 .pixel_clock = 74250000,
 301                 .conf = {
 302                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 303                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 304                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 305                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 306                 },
 307         },
 308         {
 309                 .pixel_clock = 83500000,
 310                 .conf = {
 311                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 312                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 313                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 314                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 315                 },
 316         },
 317         {
 318                 .pixel_clock = 85500000,
 319                 .conf = {
 320                         0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0x08,
 321                         0x84, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 322                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 323                         0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 324                 },
 325         },
 326         {
 327                 .pixel_clock = 106500000,
 328                 .conf = {
 329                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 330                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 331                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 332                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 333                 },
 334         },
 335         {
 336                 .pixel_clock = 108000000,
 337                 .conf = {
 338                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 339                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 340                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 341                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 342                 },
 343         },
 344         {
 345                 .pixel_clock = 115500000,
 346                 .conf = {
 347                         0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
 348                         0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 349                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 350                         0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 351                 },
 352         },
 353         {
 354                 .pixel_clock = 119000000,
 355                 .conf = {
 356                         0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
 357                         0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 358                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 359                         0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 360                 },
 361         },
 362         {
 363                 .pixel_clock = 146250000,
 364                 .conf = {
 365                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 366                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 367                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 368                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 369                 },
 370         },
 371         {
 372                 .pixel_clock = 148500000,
 373                 .conf = {
 374                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 375                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 376                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 377                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 378                 },
 379         },
 380 };
 381
 382 static const struct hdmiphy_config hdmiphy_5420_configs[] = {
 383         {
 384                 .pixel_clock = 25200000,
 385                 .conf = {
 386                         0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
 387                         0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 388                         0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
 389                         0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 390                 },
 391         },
 392         {
 393                 .pixel_clock = 27000000,
 394                 .conf = {
 395                         0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
 396                         0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 397                         0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 398                         0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 399                 },
 400         },
 401         {
 402                 .pixel_clock = 27027000,
 403                 .conf = {
 404                         0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
 405                         0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 406                         0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 407                         0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 408                 },
 409         },
 410         {
 411                 .pixel_clock = 36000000,
 412                 .conf = {
 413                         0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
 414                         0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 415                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 416                         0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 417                 },
 418         },
 419         {
 420                 .pixel_clock = 40000000,
 421                 .conf = {
 422                         0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
 423                         0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 424                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 425                         0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 426                 },
 427         },
 428         {
 429                 .pixel_clock = 65000000,
 430                 .conf = {
 431                         0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
 432                         0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 433                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 434                         0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 435                 },
 436         },
 437         {
 438                 .pixel_clock = 71000000,
 439                 .conf = {
 440                         0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
 441                         0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 442                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 443                         0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 444                 },
 445         },
 446         {
 447                 .pixel_clock = 73250000,
 448                 .conf = {
 449                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
 450                         0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 451                         0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 452                         0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 453                 },
 454         },
 455         {
 456                 .pixel_clock = 74176000,
 457                 .conf = {
 458                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
 459                         0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 460                         0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 461                         0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 462                 },
 463         },
 464         {
 465                 .pixel_clock = 74250000,
 466                 .conf = {
 467                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
 468                         0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 469                         0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
 470                         0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 471                 },
 472         },
 473         {
 474                 .pixel_clock = 83500000,
 475                 .conf = {
 476                         0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
 477                         0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 478                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 479                         0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 480                 },
 481         },
 482         {
 483                 .pixel_clock = 88750000,
 484                 .conf = {
 485                         0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
 486                         0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 487                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 488                         0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 489                 },
 490         },
 491         {
 492                 .pixel_clock = 106500000,
 493                 .conf = {
 494                         0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
 495                         0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 496                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 497                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 498                 },
 499         },
 500         {
 501                 .pixel_clock = 108000000,
 502                 .conf = {
 503                         0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
 504                         0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 505                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 506                         0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 507                 },
 508         },
 509         {
 510                 .pixel_clock = 115500000,
 511                 .conf = {
 512                         0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
 513                         0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 514                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 515                         0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 516                 },
 517         },
 518         {
 519                 .pixel_clock = 146250000,
 520                 .conf = {
 521                         0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
 522                         0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 523                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 524                         0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 525                 },
 526         },
 527         {
 528                 .pixel_clock = 148500000,
 529                 .conf = {
 530                         0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
 531                         0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 532                         0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
 533                         0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
 534                 },
 535         },
 536 };
 537
 538 static const struct hdmiphy_config hdmiphy_5433_configs[] = {
 539         {
 540                 .pixel_clock = 27000000,
 541                 .conf = {
 542                         0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
 543                         0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
 544                         0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 545                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 546                 },
 547         },
 548         {
 549                 .pixel_clock = 27027000,
 550                 .conf = {
 551                         0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
 552                         0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
 553                         0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 554                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 555                 },
 556         },
 557         {
 558                 .pixel_clock = 40000000,
 559                 .conf = {
 560                         0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02,
 561                         0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 562                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 563                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 564                 },
 565         },
 566         {
 567                 .pixel_clock = 50000000,
 568                 .conf = {
 569                         0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3,
 570                         0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 571                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 572                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 573                 },
 574         },
 575         {
 576                 .pixel_clock = 65000000,
 577                 .conf = {
 578                         0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6,
 579                         0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 580                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 581                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 582                 },
 583         },
 584         {
 585                 .pixel_clock = 74176000,
 586                 .conf = {
 587                         0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42,
 588                         0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 589                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 590                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 591                 },
 592         },
 593         {
 594                 .pixel_clock = 74250000,
 595                 .conf = {
 596                         0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2,
 597                         0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 598                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 599                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 600                 },
 601         },
 602         {
 603                 .pixel_clock = 108000000,
 604                 .conf = {
 605                         0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02,
 606                         0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 607                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 608                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 609                 },
 610         },
 611         {
 612                 .pixel_clock = 148500000,
 613                 .conf = {
 614                         0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1,
 615                         0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
 616                         0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
 617                         0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
 618                 },
 619         },
 620         {
 621                 .pixel_clock = 297000000,
 622                 .conf = {
 623                         0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
 624                         0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 625                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 626                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 627                 },
 628         },
 629 };
 630
 631 static const char * const hdmi_clk_gates4[] = {
 632         "hdmi", "sclk_hdmi"
 633 };
 634
 635 static const char * const hdmi_clk_muxes4[] = {
 636         "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"
 637 };
 638
 639 static const char * const hdmi_clk_gates5433[] = {
 640         "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk"
 641 };
 642
 643 static const char * const hdmi_clk_muxes5433[] = {
 644         "oscclk", "tmds_clko", "tmds_clko_user",
 645         "oscclk", "pixel_clko", "pixel_clko_user"
 646 };
 647
 648 static const struct hdmi_driver_data exynos4210_hdmi_driver_data = {
 649         .type           = HDMI_TYPE13,
 650         .phy_confs      = INIT_ARRAY_SPEC(hdmiphy_v13_configs),
 651         .clk_gates      = INIT_ARRAY_SPEC(hdmi_clk_gates4),
 652         .clk_muxes      = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
 653 };
 654
 655 static const struct hdmi_driver_data exynos4212_hdmi_driver_data = {
 656         .type           = HDMI_TYPE14,
 657         .phy_confs      = INIT_ARRAY_SPEC(hdmiphy_v14_configs),
 658         .clk_gates      = INIT_ARRAY_SPEC(hdmi_clk_gates4),
 659         .clk_muxes      = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
 660 };
 661
 662 static const struct hdmi_driver_data exynos5420_hdmi_driver_data = {
 663         .type           = HDMI_TYPE14,
 664         .is_apb_phy     = 1,
 665         .phy_confs      = INIT_ARRAY_SPEC(hdmiphy_5420_configs),
 666         .clk_gates      = INIT_ARRAY_SPEC(hdmi_clk_gates4),
 667         .clk_muxes      = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
 668 };
 669
 670 static const struct hdmi_driver_data exynos5433_hdmi_driver_data = {
 671         .type           = HDMI_TYPE14,
 672         .is_apb_phy     = 1,
 673         .has_sysreg     = 1,
 674         .phy_confs      = INIT_ARRAY_SPEC(hdmiphy_5433_configs),
 675         .clk_gates      = INIT_ARRAY_SPEC(hdmi_clk_gates5433),
 676         .clk_muxes      = INIT_ARRAY_SPEC(hdmi_clk_muxes5433),
 677 };
 678
 679 static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id)
 680 {
 681         if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE)
 682                 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type];
 683         return reg_id;
 684 }
 685
 686 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 687 {
 688         return readl(hdata->regs + hdmi_map_reg(hdata, reg_id));
 689 }
 690
 691 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 692                                  u32 reg_id, u8 value)
 693 {
 694         writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id));
 695 }
 696
 697 static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id,
 698                                    int bytes, u32 val)
 699 {
 700         reg_id = hdmi_map_reg(hdata, reg_id);
 701
 702         while (--bytes >= 0) {
 703                 writel(val & 0xff, hdata->regs + reg_id);
 704                 val >>= 8;
 705                 reg_id += 4;
 706         }
 707 }
 708
 709 static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id,
 710                                       u8 *buf, int size)
 711 {
 712         for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4)
 713                 writel(*buf++, hdata->regs + reg_id);
 714 }
 715
 716 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 717                                  u32 reg_id, u32 value, u32 mask)
 718 {
 719         u32 old;
 720
 721         reg_id = hdmi_map_reg(hdata, reg_id);
 722         old = readl(hdata->regs + reg_id);
 723         value = (value & mask) | (old & ~mask);
 724         writel(value, hdata->regs + reg_id);
 725 }
 726
 727 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
 728                         u32 reg_offset, const u8 *buf, u32 len)
 729 {
 730         if ((reg_offset + len) > 32)
 731                 return -EINVAL;
 732
 733         if (hdata->hdmiphy_port) {
 734                 int ret;
 735
 736                 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
 737                 if (ret == len)
 738                         return 0;
 739                 return ret;
 740         } else {
 741                 int i;
 742                 for (i = 0; i < len; i++)
 743                         writel(buf[i], hdata->regs_hdmiphy +
 744                                 ((reg_offset + i)<<2));
 745                 return 0;
 746         }
 747 }
 748
 749 static int hdmi_clk_enable_gates(struct hdmi_context *hdata)
 750 {
 751         int i, ret;
 752
 753         for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) {
 754                 ret = clk_prepare_enable(hdata->clk_gates[i]);
 755                 if (!ret)
 756                         continue;
 757
 758                 dev_err(hdata->dev, "Cannot enable clock '%s', %d\n",
 759                         hdata->drv_data->clk_gates.data[i], ret);
 760                 while (i--)
 761                         clk_disable_unprepare(hdata->clk_gates[i]);
 762                 return ret;
 763         }
 764
 765         return 0;
 766 }
 767
 768 static void hdmi_clk_disable_gates(struct hdmi_context *hdata)
 769 {
 770         int i = hdata->drv_data->clk_gates.count;
 771
 772         while (i--)
 773                 clk_disable_unprepare(hdata->clk_gates[i]);
 774 }
 775
 776 static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy)
 777 {
 778         struct device *dev = hdata->dev;
 779         int ret = 0;
 780         int i;
 781
 782         for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) {
 783                 struct clk **c = &hdata->clk_muxes[i];
 784
 785                 ret = clk_set_parent(c[2], c[to_phy]);
 786                 if (!ret)
 787                         continue;
 788
 789                 dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n",
 790                         hdata->drv_data->clk_muxes.data[i + 2],
 791                         hdata->drv_data->clk_muxes.data[i + to_phy], ret);
 792         }
 793
 794         return ret;
 795 }
 796
 797 static int hdmi_audio_infoframe_apply(struct hdmi_context *hdata)
 798 {
 799         struct hdmi_audio_infoframe *infoframe = &hdata->audio.infoframe;
 800         u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)];
 801         int len;
 802
 803         len = hdmi_audio_infoframe_pack(infoframe, buf, sizeof(buf));
 804         if (len < 0)
 805                 return len;
 806
 807         hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC);
 808         hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, len);
 809
 810         return 0;
 811 }
 812
 813 static void hdmi_reg_infoframes(struct hdmi_context *hdata)
 814 {
 815         struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
 816         union hdmi_infoframe frm;
 817         u8 buf[25];
 818         int ret;
 819
 820         if (hdata->dvi_mode) {
 821                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 822                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 823                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 824                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 825                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 826                 return;
 827         }
 828
 829         ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, m, false);
 830         if (!ret)
 831                 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf));
 832         if (ret > 0) {
 833                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
 834                 hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret);
 835         } else {
 836                 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret);
 837         }
 838
 839         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, m);
 840         if (!ret)
 841                 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf,
 842                                 sizeof(buf));
 843         if (ret > 0) {
 844                 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC);
 845                 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3);
 846                 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3);
 847         }
 848
 849         hdmi_audio_infoframe_apply(hdata);
 850 }
 851
 852 static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
 853                                 bool force)
 854 {
 855         struct hdmi_context *hdata = connector_to_hdmi(connector);
 856
 857         if (gpiod_get_value(hdata->hpd_gpio))
 858                 return connector_status_connected;
 859
 860         cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
 861         return connector_status_disconnected;
 862 }
 863
 864 static void hdmi_connector_destroy(struct drm_connector *connector)
 865 {
 866         drm_connector_unregister(connector);
 867         drm_connector_cleanup(connector);
 868 }
 869
 870 static const struct drm_connector_funcs hdmi_connector_funcs = {
 871         .fill_modes = drm_helper_probe_single_connector_modes,
 872         .detect = hdmi_detect,
 873         .destroy = hdmi_connector_destroy,
 874         .reset = drm_atomic_helper_connector_reset,
 875         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 876         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 877 };
 878
 879 static int hdmi_get_modes(struct drm_connector *connector)
 880 {
 881         struct hdmi_context *hdata = connector_to_hdmi(connector);
 882         struct edid *edid;
 883         int ret;
 884
 885         if (!hdata->ddc_adpt)
 886                 return -ENODEV;
 887
 888         edid = drm_get_edid(connector, hdata->ddc_adpt);
 889         if (!edid)
 890                 return -ENODEV;
 891
 892         hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
 893         DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
 894                 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
 895                 edid->width_cm, edid->height_cm);
 896
 897         drm_mode_connector_update_edid_property(connector, edid);
 898         cec_notifier_set_phys_addr_from_edid(hdata->notifier, edid);
 899
 900         ret = drm_add_edid_modes(connector, edid);
 901
 902         kfree(edid);
 903
 904         return ret;
 905 }
 906
 907 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
 908 {
 909         const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs;
 910         int i;
 911
 912         for (i = 0; i < confs->count; i++)
 913                 if (confs->data[i].pixel_clock == pixel_clock)
 914                         return i;
 915
 916         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 917         return -EINVAL;
 918 }
 919
 920 static int hdmi_mode_valid(struct drm_connector *connector,
 921                         struct drm_display_mode *mode)
 922 {
 923         struct hdmi_context *hdata = connector_to_hdmi(connector);
 924         int ret;
 925
 926         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
 927                 mode->hdisplay, mode->vdisplay, mode->vrefresh,
 928                 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
 929                 false, mode->clock * 1000);
 930
 931         ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
 932         if (ret < 0)
 933                 return MODE_BAD;
 934
 935         return MODE_OK;
 936 }
 937
 938 static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
 939         .get_modes = hdmi_get_modes,
 940         .mode_valid = hdmi_mode_valid,
 941 };
 942
 943 static int hdmi_create_connector(struct drm_encoder *encoder)
 944 {
 945         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
 946         struct drm_connector *connector = &hdata->connector;
 947         int ret;
 948
 949         connector->interlace_allowed = true;
 950         connector->polled = DRM_CONNECTOR_POLL_HPD;
 951
 952         ret = drm_connector_init(hdata->drm_dev, connector,
 953                         &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
 954         if (ret) {
 955                 DRM_ERROR("Failed to initialize connector with drm\n");
 956                 return ret;
 957         }
 958
 959         drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
 960         drm_mode_connector_attach_encoder(connector, encoder);
 961
 962         if (hdata->bridge) {
 963                 encoder->bridge = hdata->bridge;
 964                 hdata->bridge->encoder = encoder;
 965                 ret = drm_bridge_attach(encoder, hdata->bridge, NULL);
 966                 if (ret)
 967                         DRM_ERROR("Failed to attach bridge\n");
 968         }
 969
 970         return ret;
 971 }
 972
 973 static bool hdmi_mode_fixup(struct drm_encoder *encoder,
 974                             const struct drm_display_mode *mode,
 975                             struct drm_display_mode *adjusted_mode)
 976 {
 977         struct drm_device *dev = encoder->dev;
 978         struct drm_connector *connector;
 979         struct drm_display_mode *m;
 980         struct drm_connector_list_iter conn_iter;
 981         int mode_ok;
 982
 983         drm_mode_set_crtcinfo(adjusted_mode, 0);
 984
 985         drm_connector_list_iter_begin(dev, &conn_iter);
 986         drm_for_each_connector_iter(connector, &conn_iter) {
 987                 if (connector->encoder == encoder)
 988                         break;
 989         }
 990         if (connector)
 991                 drm_connector_get(connector);
 992         drm_connector_list_iter_end(&conn_iter);
 993
 994         if (!connector)
 995                 return true;
 996
 997         mode_ok = hdmi_mode_valid(connector, adjusted_mode);
 998
 999         if (mode_ok == MODE_OK)
1000                 goto cleanup;
1001
1002         /*
1003          * Find the most suitable mode and copy it to adjusted_mode.
1004          */
1005         list_for_each_entry(m, &connector->modes, head) {
1006                 mode_ok = hdmi_mode_valid(connector, m);
1007
1008                 if (mode_ok == MODE_OK) {
1009                         DRM_INFO("desired mode doesn't exist so\n");
1010                         DRM_INFO("use the most suitable mode among modes.\n");
1011
1012                         DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
1013                                 m->hdisplay, m->vdisplay, m->vrefresh);
1014
1015                         drm_mode_copy(adjusted_mode, m);
1016                         break;
1017                 }
1018         }
1019
1020 cleanup:
1021         drm_connector_put(connector);
1022
1023         return true;
1024 }
1025
1026 static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq)
1027 {
1028         u32 n, cts;
1029
1030         cts = (freq % 9) ? 27000 : 30000;
1031         n = 128 * freq / (27000000 / cts);
1032
1033         hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n);
1034         hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts);
1035         hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts);
1036         hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1037 }
1038
1039 static void hdmi_audio_config(struct hdmi_context *hdata)
1040 {
1041         u32 bit_ch = 1;
1042         u32 data_num, val;
1043         int i;
1044
1045         switch (hdata->audio.params.sample_width) {
1046         case 20:
1047                 data_num = 2;
1048                 break;
1049         case 24:
1050                 data_num = 3;
1051                 break;
1052         default:
1053                 data_num = 1;
1054                 bit_ch = 0;
1055                 break;
1056         }
1057
1058         hdmi_reg_acr(hdata, hdata->audio.params.sample_rate);
1059
1060         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1061                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1062                                 | HDMI_I2S_MUX_ENABLE);
1063
1064         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1065                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1066
1067         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1068         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1069         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1070
1071         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1072         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1073
1074         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1075         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1076                         | HDMI_I2S_SEL_LRCK(6));
1077
1078         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(3)
1079                         | HDMI_I2S_SEL_SDATA0(4));
1080
1081         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1082                         | HDMI_I2S_SEL_SDATA2(2));
1083
1084         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1085
1086         /* I2S_CON_1 & 2 */
1087         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1088                         | HDMI_I2S_L_CH_LOW_POL);
1089         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1090                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1091                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1092                         | HDMI_I2S_BASIC_FORMAT);
1093
1094         /* Configuration of the audio channel status registers */
1095         for (i = 0; i < HDMI_I2S_CH_ST_MAXNUM; i++)
1096                 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST(i),
1097                                 hdata->audio.params.iec.status[i]);
1098
1099         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1100 }
1101
1102 static void hdmi_audio_control(struct hdmi_context *hdata)
1103 {
1104         bool enable = !hdata->audio.mute;
1105
1106         if (hdata->dvi_mode)
1107                 return;
1108
1109         hdmi_reg_writeb(hdata, HDMI_AUI_CON, enable ?
1110                         HDMI_AVI_CON_EVERY_VSYNC : HDMI_AUI_CON_NO_TRAN);
1111         hdmi_reg_writemask(hdata, HDMI_CON_0, enable ?
1112                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1113 }
1114
1115 static void hdmi_start(struct hdmi_context *hdata, bool start)
1116 {
1117         struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1118         u32 val = start ? HDMI_TG_EN : 0;
1119
1120         if (m->flags & DRM_MODE_FLAG_INTERLACE)
1121                 val |= HDMI_FIELD_EN;
1122
1123         hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1124         hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
1125 }
1126
1127 static void hdmi_conf_init(struct hdmi_context *hdata)
1128 {
1129         /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1130         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1131                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1132
1133         /* choose HDMI mode */
1134         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1135                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1136         /* apply video pre-amble and guard band in HDMI mode only */
1137         hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
1138         /* disable bluescreen */
1139         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1140
1141         if (hdata->dvi_mode) {
1142                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1143                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1144                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1145                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1146         }
1147
1148         if (hdata->drv_data->type == HDMI_TYPE13) {
1149                 /* choose bluescreen (fecal) color */
1150                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1151                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1152                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1153
1154                 /* enable AVI packet every vsync, fixes purple line problem */
1155                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1156                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1157                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1158                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1159
1160                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1161                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1162                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1163         } else {
1164                 hdmi_reg_infoframes(hdata);
1165
1166                 /* enable AVI packet every vsync, fixes purple line problem */
1167                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1168         }
1169 }
1170
1171 static void hdmiphy_wait_for_pll(struct hdmi_context *hdata)
1172 {
1173         int tries;
1174
1175         for (tries = 0; tries < 10; ++tries) {
1176                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS);
1177
1178                 if (val & HDMI_PHY_STATUS_READY) {
1179                         DRM_DEBUG_KMS("PLL stabilized after %d tries\n", tries);
1180                         return;
1181                 }
1182                 usleep_range(10, 20);
1183         }
1184
1185         DRM_ERROR("PLL could not reach steady state\n");
1186 }
1187
1188 static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1189 {
1190         struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1191         unsigned int val;
1192
1193         hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1194         hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3,
1195                         (m->htotal << 12) | m->vtotal);
1196
1197         val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1198         hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val);
1199
1200         val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1201         hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val);
1202
1203         val = (m->hsync_start - m->hdisplay - 2);
1204         val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1205         val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1206         hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val);
1207
1208         /*
1209          * Quirk requirement for exynos HDMI IP design,
1210          * 2 pixels less than the actual calculation for hsync_start
1211          * and end.
1212          */
1213
1214         /* Following values & calculations differ for different type of modes */
1215         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1216                 val = ((m->vsync_end - m->vdisplay) / 2);
1217                 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1218                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1219
1220                 val = m->vtotal / 2;
1221                 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1222                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1223
1224                 val = (m->vtotal +
1225                         ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1226                 val |= m->vtotal << 11;
1227                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val);
1228
1229                 val = ((m->vtotal / 2) + 7);
1230                 val |= ((m->vtotal / 2) + 2) << 12;
1231                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val);
1232
1233                 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1234                 val |= ((m->htotal / 2) +
1235                         (m->hsync_start - m->hdisplay)) << 12;
1236                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val);
1237
1238                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1239                                 (m->vtotal - m->vdisplay) / 2);
1240                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1241
1242                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249);
1243         } else {
1244                 val = m->vtotal;
1245                 val |= (m->vtotal - m->vdisplay) << 11;
1246                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1247
1248                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0);
1249
1250                 val = (m->vsync_end - m->vdisplay);
1251                 val |= ((m->vsync_start - m->vdisplay) << 12);
1252                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1253
1254                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001);
1255                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001);
1256                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1257                                 m->vtotal - m->vdisplay);
1258                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1259         }
1260
1261         hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1262         hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
1263         hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
1264         hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1265 }
1266
1267 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1268 {
1269         struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1270         struct drm_display_mode *am =
1271                                 &hdata->encoder.crtc->state->adjusted_mode;
1272         int hquirk = 0;
1273
1274         /*
1275          * In case video mode coming from CRTC differs from requested one HDMI
1276          * sometimes is able to almost properly perform conversion - only
1277          * first line is distorted.
1278          */
1279         if ((m->vdisplay != am->vdisplay) &&
1280             (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366))
1281                 hquirk = 258;
1282
1283         hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1284         hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal);
1285         hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal);
1286         hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1,
1287                         (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1288         hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1,
1289                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1290         hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1,
1291                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1292
1293         /*
1294          * Quirk requirement for exynos 5 HDMI IP design,
1295          * 2 pixels less than the actual calculation for hsync_start
1296          * and end.
1297          */
1298
1299         /* Following values & calculations differ for different type of modes */
1300         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1301                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1302                         (m->vsync_end - m->vdisplay) / 2);
1303                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1304                         (m->vsync_start - m->vdisplay) / 2);
1305                 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2);
1306                 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1307                                 (m->vtotal - m->vdisplay) / 2);
1308                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2,
1309                                 m->vtotal - m->vdisplay / 2);
1310                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal);
1311                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2,
1312                                 (m->vtotal / 2) + 7);
1313                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2,
1314                                 (m->vtotal / 2) + 2);
1315                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2,
1316                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1317                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2,
1318                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1319                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1320                                 (m->vtotal - m->vdisplay) / 2);
1321                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1322                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2,
1323                                 m->vtotal - m->vdisplay / 2);
1324                 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2,
1325                                 (m->vtotal / 2) + 1);
1326                 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2,
1327                                 (m->vtotal / 2) + 1);
1328                 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2,
1329                                 (m->vtotal / 2) + 1);
1330                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0);
1331                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0);
1332         } else {
1333                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1334                         m->vsync_end - m->vdisplay);
1335                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1336                         m->vsync_start - m->vdisplay);
1337                 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal);
1338                 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1339                                 m->vtotal - m->vdisplay);
1340                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff);
1341                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff);
1342                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff);
1343                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff);
1344                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff);
1345                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff);
1346                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1347                                 m->vtotal - m->vdisplay);
1348                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1349         }
1350
1351         hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2,
1352                         m->hsync_start - m->hdisplay - 2);
1353         hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2,
1354                         m->hsync_end - m->hdisplay - 2);
1355         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff);
1356         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff);
1357         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff);
1358         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff);
1359         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff);
1360         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff);
1361         hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff);
1362         hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff);
1363         hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff);
1364         hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff);
1365         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff);
1366         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff);
1367         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff);
1368         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff);
1369         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff);
1370         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff);
1371         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff);
1372         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff);
1373
1374         hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1375         hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2,
1376                                         m->htotal - m->hdisplay - hquirk);
1377         hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay + hquirk);
1378         hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1379         if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1380                 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1);
1381 }
1382
1383 static void hdmi_mode_apply(struct hdmi_context *hdata)
1384 {
1385         if (hdata->drv_data->type == HDMI_TYPE13)
1386                 hdmi_v13_mode_apply(hdata);
1387         else
1388                 hdmi_v14_mode_apply(hdata);
1389
1390         hdmi_start(hdata, true);
1391 }
1392
1393 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1394 {
1395         hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1);
1396         usleep_range(10000, 12000);
1397         hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1);
1398         usleep_range(10000, 12000);
1399         hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
1400         usleep_range(10000, 12000);
1401         hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
1402         usleep_range(10000, 12000);
1403 }
1404
1405 static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
1406 {
1407         u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET;
1408
1409         if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1410                 writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE);
1411 }
1412
1413 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1414 {
1415         struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1416         int ret;
1417         const u8 *phy_conf;
1418
1419         ret = hdmi_find_phy_conf(hdata, m->clock * 1000);
1420         if (ret < 0) {
1421                 DRM_ERROR("failed to find hdmiphy conf\n");
1422                 return;
1423         }
1424         phy_conf = hdata->drv_data->phy_confs.data[ret].conf;
1425
1426         hdmi_clk_set_parents(hdata, false);
1427
1428         hdmiphy_conf_reset(hdata);
1429
1430         hdmiphy_enable_mode_set(hdata, true);
1431         ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32);
1432         if (ret) {
1433                 DRM_ERROR("failed to configure hdmiphy\n");
1434                 return;
1435         }
1436         hdmiphy_enable_mode_set(hdata, false);
1437         hdmi_clk_set_parents(hdata, true);
1438         usleep_range(10000, 12000);
1439         hdmiphy_wait_for_pll(hdata);
1440 }
1441
1442 /* Should be called with hdata->mutex mutex held */
1443 static void hdmi_conf_apply(struct hdmi_context *hdata)
1444 {
1445         hdmi_start(hdata, false);
1446         hdmi_conf_init(hdata);
1447         hdmi_audio_config(hdata);
1448         hdmi_mode_apply(hdata);
1449         hdmi_audio_control(hdata);
1450 }
1451
1452 static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
1453 {
1454         if (!hdata->sysreg)
1455                 return;
1456
1457         regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY,
1458                            SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
1459 }
1460
1461 /* Should be called with hdata->mutex mutex held. */
1462 static void hdmiphy_enable(struct hdmi_context *hdata)
1463 {
1464         if (hdata->powered)
1465                 return;
1466
1467         pm_runtime_get_sync(hdata->dev);
1468
1469         if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk))
1470                 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
1471
1472         regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1473                         PMU_HDMI_PHY_ENABLE_BIT, 1);
1474
1475         hdmi_set_refclk(hdata, true);
1476
1477         hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN);
1478
1479         hdmiphy_conf_apply(hdata);
1480
1481         hdata->powered = true;
1482 }
1483
1484 /* Should be called with hdata->mutex mutex held. */
1485 static void hdmiphy_disable(struct hdmi_context *hdata)
1486 {
1487         if (!hdata->powered)
1488                 return;
1489
1490         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
1491
1492         hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
1493
1494         hdmi_set_refclk(hdata, false);
1495
1496         regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1497                         PMU_HDMI_PHY_ENABLE_BIT, 0);
1498
1499         regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
1500
1501         pm_runtime_put_sync(hdata->dev);
1502
1503         hdata->powered = false;
1504 }
1505
1506 static void hdmi_enable(struct drm_encoder *encoder)
1507 {
1508         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1509
1510         mutex_lock(&hdata->mutex);
1511
1512         hdmiphy_enable(hdata);
1513         hdmi_conf_apply(hdata);
1514
1515         mutex_unlock(&hdata->mutex);
1516 }
1517
1518 static void hdmi_disable(struct drm_encoder *encoder)
1519 {
1520         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1521
1522         mutex_lock(&hdata->mutex);
1523
1524         if (hdata->powered) {
1525                 /*
1526                  * The SFRs of VP and Mixer are updated by Vertical Sync of
1527                  * Timing generator which is a part of HDMI so the sequence
1528                  * to disable TV Subsystem should be as following,
1529                  *      VP -> Mixer -> HDMI
1530                  *
1531                  * To achieve such sequence HDMI is disabled together with
1532                  * HDMI PHY, via pipe clock callback.
1533                  */
1534                 mutex_unlock(&hdata->mutex);
1535                 cancel_delayed_work(&hdata->hotplug_work);
1536                 cec_notifier_set_phys_addr(hdata->notifier,
1537                                            CEC_PHYS_ADDR_INVALID);
1538                 return;
1539         }
1540
1541         mutex_unlock(&hdata->mutex);
1542 }
1543
1544 static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
1545         .mode_fixup     = hdmi_mode_fixup,
1546         .enable         = hdmi_enable,
1547         .disable        = hdmi_disable,
1548 };
1549
1550 static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = {
1551         .destroy = drm_encoder_cleanup,
1552 };
1553
1554 static void hdmi_audio_shutdown(struct device *dev, void *data)
1555 {
1556         struct hdmi_context *hdata = dev_get_drvdata(dev);
1557
1558         mutex_lock(&hdata->mutex);
1559
1560         hdata->audio.mute = true;
1561
1562         if (hdata->powered)
1563                 hdmi_audio_control(hdata);
1564
1565         mutex_unlock(&hdata->mutex);
1566 }
1567
1568 static int hdmi_audio_hw_params(struct device *dev, void *data,
1569                                 struct hdmi_codec_daifmt *daifmt,
1570                                 struct hdmi_codec_params *params)
1571 {
1572         struct hdmi_context *hdata = dev_get_drvdata(dev);
1573
1574         if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv ||
1575             daifmt->frame_clk_inv || daifmt->bit_clk_master ||
1576             daifmt->frame_clk_master) {
1577                 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1578                         daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1579                         daifmt->bit_clk_master,
1580                         daifmt->frame_clk_master);
1581                 return -EINVAL;
1582         }
1583
1584         mutex_lock(&hdata->mutex);
1585
1586         hdata->audio.params = *params;
1587
1588         if (hdata->powered) {
1589                 hdmi_audio_config(hdata);
1590                 hdmi_audio_infoframe_apply(hdata);
1591         }
1592
1593         mutex_unlock(&hdata->mutex);
1594
1595         return 0;
1596 }
1597
1598 static int hdmi_audio_digital_mute(struct device *dev, void *data, bool mute)
1599 {
1600         struct hdmi_context *hdata = dev_get_drvdata(dev);
1601
1602         mutex_lock(&hdata->mutex);
1603
1604         hdata->audio.mute = mute;
1605
1606         if (hdata->powered)
1607                 hdmi_audio_control(hdata);
1608
1609         mutex_unlock(&hdata->mutex);
1610
1611         return 0;
1612 }
1613
1614 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
1615                               size_t len)
1616 {
1617         struct hdmi_context *hdata = dev_get_drvdata(dev);
1618         struct drm_connector *connector = &hdata->connector;
1619
1620         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1621
1622         return 0;
1623 }
1624
1625 static const struct hdmi_codec_ops audio_codec_ops = {
1626         .hw_params = hdmi_audio_hw_params,
1627         .audio_shutdown = hdmi_audio_shutdown,
1628         .digital_mute = hdmi_audio_digital_mute,
1629         .get_eld = hdmi_audio_get_eld,
1630 };
1631
1632 static int hdmi_register_audio_device(struct hdmi_context *hdata)
1633 {
1634         struct hdmi_codec_pdata codec_data = {
1635                 .ops = &audio_codec_ops,
1636                 .max_i2s_channels = 6,
1637                 .i2s = 1,
1638         };
1639
1640         hdata->audio.pdev = platform_device_register_data(
1641                 hdata->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1642                 &codec_data, sizeof(codec_data));
1643
1644         return PTR_ERR_OR_ZERO(hdata->audio.pdev);
1645 }
1646
1647 static void hdmi_extcon_notify(struct hdmi_context *hdata)
1648 {
1649         enum drm_connector_status plug;
1650
1651         if (!hdata->edev)
1652                 return;
1653
1654         plug = hdmi_detect(&hdata->connector, false);
1655
1656         if (plug == connector_status_connected)
1657                 extcon_set_state_sync(hdata->edev, EXTCON_DISP_HDMI, true);
1658         else if (plug == connector_status_disconnected)
1659                 extcon_set_state_sync(hdata->edev, EXTCON_DISP_HDMI, false);
1660 }
1661
1662 static void hdmi_hotplug_work_func(struct work_struct *work)
1663 {
1664         struct hdmi_context *hdata;
1665
1666         hdata = container_of(work, struct hdmi_context, hotplug_work.work);
1667
1668         hdmi_extcon_notify(hdata);
1669
1670         if (hdata->drm_dev)
1671                 drm_helper_hpd_irq_event(hdata->drm_dev);
1672 }
1673
1674 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1675 {
1676         struct hdmi_context *hdata = arg;
1677
1678         mod_delayed_work(system_wq, &hdata->hotplug_work,
1679                         msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
1680
1681         return IRQ_HANDLED;
1682 }
1683
1684 static int hdmi_clks_get(struct hdmi_context *hdata,
1685                          const struct string_array_spec *names,
1686                          struct clk **clks)
1687 {
1688         struct device *dev = hdata->dev;
1689         int i;
1690
1691         for (i = 0; i < names->count; ++i) {
1692                 struct clk *clk = devm_clk_get(dev, names->data[i]);
1693
1694                 if (IS_ERR(clk)) {
1695                         int ret = PTR_ERR(clk);
1696
1697                         dev_err(dev, "Cannot get clock %s, %d\n",
1698                                 names->data[i], ret);
1699
1700                         return ret;
1701                 }
1702
1703                 clks[i] = clk;
1704         }
1705
1706         return 0;
1707 }
1708
1709 static int hdmi_clk_init(struct hdmi_context *hdata)
1710 {
1711         const struct hdmi_driver_data *drv_data = hdata->drv_data;
1712         int count = drv_data->clk_gates.count + drv_data->clk_muxes.count;
1713         struct device *dev = hdata->dev;
1714         struct clk **clks;
1715         int ret;
1716
1717         if (!count)
1718                 return 0;
1719
1720         clks = devm_kzalloc(dev, sizeof(*clks) * count, GFP_KERNEL);
1721         if (!clks)
1722                 return -ENOMEM;
1723
1724         hdata->clk_gates = clks;
1725         hdata->clk_muxes = clks + drv_data->clk_gates.count;
1726
1727         ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates);
1728         if (ret)
1729                 return ret;
1730
1731         return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes);
1732 }
1733
1734
1735 static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
1736 {
1737         struct hdmi_context *hdata = container_of(clk, struct hdmi_context,
1738                                                   phy_clk);
1739         mutex_lock(&hdata->mutex);
1740
1741         if (enable)
1742                 hdmiphy_enable(hdata);
1743         else
1744                 hdmiphy_disable(hdata);
1745
1746         mutex_unlock(&hdata->mutex);
1747 }
1748
1749 static int hdmi_bridge_init(struct hdmi_context *hdata)
1750 {
1751         struct device *dev = hdata->dev;
1752         struct device_node *ep, *np;
1753
1754         ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
1755         if (!ep)
1756                 return 0;
1757
1758         np = of_graph_get_remote_port_parent(ep);
1759         of_node_put(ep);
1760         if (!np) {
1761                 DRM_ERROR("failed to get remote port parent");
1762                 return -EINVAL;
1763         }
1764
1765         hdata->bridge = of_drm_find_bridge(np);
1766         of_node_put(np);
1767
1768         if (!hdata->bridge)
1769                 return -EPROBE_DEFER;
1770
1771         return 0;
1772 }
1773
1774 static int hdmi_resources_init(struct hdmi_context *hdata)
1775 {
1776         struct device *dev = hdata->dev;
1777         int i, ret;
1778
1779         DRM_DEBUG_KMS("HDMI resource init\n");
1780
1781         hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN);
1782         if (IS_ERR(hdata->hpd_gpio)) {
1783                 DRM_ERROR("cannot get hpd gpio property\n");
1784                 return PTR_ERR(hdata->hpd_gpio);
1785         }
1786
1787         hdata->irq = gpiod_to_irq(hdata->hpd_gpio);
1788         if (hdata->irq < 0) {
1789                 DRM_ERROR("failed to get GPIO irq\n");
1790                 return  hdata->irq;
1791         }
1792
1793         ret = hdmi_clk_init(hdata);
1794         if (ret)
1795                 return ret;
1796
1797         ret = hdmi_clk_set_parents(hdata, false);
1798         if (ret)
1799                 return ret;
1800
1801         for (i = 0; i < ARRAY_SIZE(supply); ++i)
1802                 hdata->regul_bulk[i].supply = supply[i];
1803
1804         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk);
1805         if (ret) {
1806                 if (ret != -EPROBE_DEFER)
1807                         DRM_ERROR("failed to get regulators\n");
1808                 return ret;
1809         }
1810
1811         hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
1812
1813         if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) {
1814                 if (IS_ERR(hdata->reg_hdmi_en))
1815                         return PTR_ERR(hdata->reg_hdmi_en);
1816
1817                 ret = regulator_enable(hdata->reg_hdmi_en);
1818                 if (ret) {
1819                         DRM_ERROR("failed to enable hdmi-en regulator\n");
1820                         return ret;
1821                 }
1822         }
1823
1824         return hdmi_bridge_init(hdata);
1825 }
1826
1827 static const struct of_device_id hdmi_match_types[] = {
1828         {
1829                 .compatible = "samsung,exynos4210-hdmi",
1830                 .data = &exynos4210_hdmi_driver_data,
1831         }, {
1832                 .compatible = "samsung,exynos4212-hdmi",
1833                 .data = &exynos4212_hdmi_driver_data,
1834         }, {
1835                 .compatible = "samsung,exynos5420-hdmi",
1836                 .data = &exynos5420_hdmi_driver_data,
1837         }, {
1838                 .compatible = "samsung,exynos5433-hdmi",
1839                 .data = &exynos5433_hdmi_driver_data,
1840         }, {
1841                 /* end node */
1842         }
1843 };
1844 MODULE_DEVICE_TABLE (of, hdmi_match_types);
1845
1846 static int hdmi_bind(struct device *dev, struct device *master, void *data)
1847 {
1848         struct drm_device *drm_dev = data;
1849         struct hdmi_context *hdata = dev_get_drvdata(dev);
1850         struct drm_encoder *encoder = &hdata->encoder;
1851         struct exynos_drm_crtc *crtc;
1852         int ret;
1853
1854         hdata->drm_dev = drm_dev;
1855
1856         hdata->phy_clk.enable = hdmiphy_clk_enable;
1857
1858         drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs,
1859                          DRM_MODE_ENCODER_TMDS, NULL);
1860
1861         drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs);
1862
1863         ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_HDMI);
1864         if (ret < 0)
1865                 return ret;
1866
1867         crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI);
1868         crtc->pipe_clk = &hdata->phy_clk;
1869
1870         ret = hdmi_create_connector(encoder);
1871         if (ret) {
1872                 DRM_ERROR("failed to create connector ret = %d\n", ret);
1873                 drm_encoder_cleanup(encoder);
1874                 return ret;
1875         }
1876
1877         return 0;
1878 }
1879
1880 static void hdmi_unbind(struct device *dev, struct device *master, void *data)
1881 {
1882 }
1883
1884 static const struct component_ops hdmi_component_ops = {
1885         .bind   = hdmi_bind,
1886         .unbind = hdmi_unbind,
1887 };
1888
1889 static int hdmi_get_ddc_adapter(struct hdmi_context *hdata)
1890 {
1891         const char *compatible_str = "samsung,exynos4210-hdmiddc";
1892         struct device_node *np;
1893         struct i2c_adapter *adpt;
1894
1895         np = of_find_compatible_node(NULL, NULL, compatible_str);
1896         if (np)
1897                 np = of_get_next_parent(np);
1898         else
1899                 np = of_parse_phandle(hdata->dev->of_node, "ddc", 0);
1900
1901         if (!np) {
1902                 DRM_ERROR("Failed to find ddc node in device tree\n");
1903                 return -ENODEV;
1904         }
1905
1906         adpt = of_find_i2c_adapter_by_node(np);
1907         of_node_put(np);
1908
1909         if (!adpt) {
1910                 DRM_INFO("Failed to get ddc i2c adapter by node\n");
1911                 return -EPROBE_DEFER;
1912         }
1913
1914         hdata->ddc_adpt = adpt;
1915
1916         return 0;
1917 }
1918
1919 static int hdmi_get_phy_io(struct hdmi_context *hdata)
1920 {
1921         const char *compatible_str = "samsung,exynos4212-hdmiphy";
1922         struct device_node *np;
1923         int ret = 0;
1924
1925         np = of_find_compatible_node(NULL, NULL, compatible_str);
1926         if (!np) {
1927                 np = of_parse_phandle(hdata->dev->of_node, "phy", 0);
1928                 if (!np) {
1929                         DRM_ERROR("Failed to find hdmiphy node in device tree\n");
1930                         return -ENODEV;
1931                 }
1932         }
1933
1934         if (hdata->drv_data->is_apb_phy) {
1935                 hdata->regs_hdmiphy = of_iomap(np, 0);
1936                 if (!hdata->regs_hdmiphy) {
1937                         DRM_ERROR("failed to ioremap hdmi phy\n");
1938                         ret = -ENOMEM;
1939                         goto out;
1940                 }
1941         } else {
1942                 hdata->hdmiphy_port = of_find_i2c_device_by_node(np);
1943                 if (!hdata->hdmiphy_port) {
1944                         DRM_INFO("Failed to get hdmi phy i2c client\n");
1945                         ret = -EPROBE_DEFER;
1946                         goto out;
1947                 }
1948         }
1949
1950 out:
1951         of_node_put(np);
1952         return ret;
1953 }
1954
1955 static int hdmi_extcon_init(struct hdmi_context *hdata)
1956 {
1957         struct device *dev = hdata->dev;
1958         struct extcon_dev *edev;
1959         int ret;
1960
1961         edev = devm_extcon_dev_allocate(dev, extcon_cable_list);
1962         if (IS_ERR(edev))
1963                 return PTR_ERR(edev);
1964
1965         ret = devm_extcon_dev_register(dev, edev);
1966         if (ret)
1967                 return ret;
1968
1969         hdata->edev = edev;
1970
1971         return 0;
1972 }
1973
1974 static int hdmi_probe(struct platform_device *pdev)
1975 {
1976         struct hdmi_audio_infoframe *audio_infoframe;
1977         struct device *dev = &pdev->dev;
1978         struct hdmi_context *hdata;
1979         struct resource *res;
1980         int ret;
1981
1982         hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
1983         if (!hdata)
1984                 return -ENOMEM;
1985
1986         hdata->drv_data = of_device_get_match_data(dev);
1987
1988         platform_set_drvdata(pdev, hdata);
1989
1990         hdata->dev = dev;
1991
1992         mutex_init(&hdata->mutex);
1993
1994         ret = hdmi_resources_init(hdata);
1995         if (ret) {
1996                 if (ret != -EPROBE_DEFER)
1997                         DRM_ERROR("hdmi_resources_init failed\n");
1998                 return ret;
1999         }
2000
2001         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2002         hdata->regs = devm_ioremap_resource(dev, res);
2003         if (IS_ERR(hdata->regs)) {
2004                 ret = PTR_ERR(hdata->regs);
2005                 return ret;
2006         }
2007
2008         ret = hdmi_extcon_init(hdata);
2009         if (ret)
2010                 DRM_INFO("extcon notify won't be supported due to init. fail");
2011
2012         ret = hdmi_get_ddc_adapter(hdata);
2013         if (ret)
2014                 return ret;
2015
2016         ret = hdmi_get_phy_io(hdata);
2017         if (ret)
2018                 goto err_ddc;
2019
2020         INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2021
2022         ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2023                         hdmi_irq_thread, IRQF_TRIGGER_RISING |
2024                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2025                         "hdmi", hdata);
2026         if (ret) {
2027                 DRM_ERROR("failed to register hdmi interrupt\n");
2028                 goto err_hdmiphy;
2029         }
2030
2031         hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
2032                         "samsung,syscon-phandle");
2033         if (IS_ERR(hdata->pmureg)) {
2034                 DRM_ERROR("syscon regmap lookup failed.\n");
2035                 ret = -EPROBE_DEFER;
2036                 goto err_hdmiphy;
2037         }
2038
2039         if (hdata->drv_data->has_sysreg) {
2040                 hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
2041                                 "samsung,sysreg-phandle");
2042                 if (IS_ERR(hdata->sysreg)) {
2043                         DRM_ERROR("sysreg regmap lookup failed.\n");
2044                         ret = -EPROBE_DEFER;
2045                         goto err_hdmiphy;
2046                 }
2047         }
2048
2049         hdata->notifier = cec_notifier_get(&pdev->dev);
2050         if (hdata->notifier == NULL) {
2051                 ret = -ENOMEM;
2052                 goto err_hdmiphy;
2053         }
2054
2055         pm_runtime_enable(dev);
2056
2057         audio_infoframe = &hdata->audio.infoframe;
2058         hdmi_audio_infoframe_init(audio_infoframe);
2059         audio_infoframe->coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
2060         audio_infoframe->sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
2061         audio_infoframe->sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
2062         audio_infoframe->channels = 2;
2063
2064         ret = hdmi_register_audio_device(hdata);
2065         if (ret)
2066                 goto err_notifier_put;
2067
2068         ret = component_add(&pdev->dev, &hdmi_component_ops);
2069         if (ret)
2070                 goto err_unregister_audio;
2071
2072         return ret;
2073
2074 err_unregister_audio:
2075         platform_device_unregister(hdata->audio.pdev);
2076
2077 err_notifier_put:
2078         cec_notifier_put(hdata->notifier);
2079         pm_runtime_disable(dev);
2080
2081 err_hdmiphy:
2082         if (hdata->hdmiphy_port)
2083                 put_device(&hdata->hdmiphy_port->dev);
2084         if (hdata->regs_hdmiphy)
2085                 iounmap(hdata->regs_hdmiphy);
2086 err_ddc:
2087         put_device(&hdata->ddc_adpt->dev);
2088
2089         return ret;
2090 }
2091
2092 static int hdmi_remove(struct platform_device *pdev)
2093 {
2094         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2095
2096         cancel_delayed_work_sync(&hdata->hotplug_work);
2097         cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
2098
2099         component_del(&pdev->dev, &hdmi_component_ops);
2100         platform_device_unregister(hdata->audio.pdev);
2101
2102         cec_notifier_put(hdata->notifier);
2103         pm_runtime_disable(&pdev->dev);
2104
2105         if (!IS_ERR(hdata->reg_hdmi_en))
2106                 regulator_disable(hdata->reg_hdmi_en);
2107
2108         if (hdata->hdmiphy_port)
2109                 put_device(&hdata->hdmiphy_port->dev);
2110
2111         if (hdata->regs_hdmiphy)
2112                 iounmap(hdata->regs_hdmiphy);
2113
2114         put_device(&hdata->ddc_adpt->dev);
2115
2116         mutex_destroy(&hdata->mutex);
2117
2118         return 0;
2119 }
2120
2121 static int __maybe_unused exynos_hdmi_suspend(struct device *dev)
2122 {
2123         struct hdmi_context *hdata = dev_get_drvdata(dev);
2124
2125         hdmi_clk_disable_gates(hdata);
2126
2127         return 0;
2128 }
2129
2130 static int __maybe_unused exynos_hdmi_resume(struct device *dev)
2131 {
2132         struct hdmi_context *hdata = dev_get_drvdata(dev);
2133         int ret;
2134
2135         ret = hdmi_clk_enable_gates(hdata);
2136         if (ret < 0)
2137                 return ret;
2138
2139         return 0;
2140 }
2141
2142 static const struct dev_pm_ops exynos_hdmi_pm_ops = {
2143         SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL)
2144         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2145                                 pm_runtime_force_resume)
2146 };
2147
2148 struct platform_driver hdmi_driver = {
2149         .probe          = hdmi_probe,
2150         .remove         = hdmi_remove,
2151         .driver         = {
2152                 .name   = "exynos-hdmi",
2153                 .owner  = THIS_MODULE,
2154                 .pm     = &exynos_hdmi_pm_ops,
2155                 .of_match_table = hdmi_match_types,
2156         },
2157 };