3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
23 #include <video/of_display_timing.h>
24 #include <video/of_videomode.h>
25 #include <video/samsung_fimd.h>
26 #include <drm/exynos_drm.h>
28 #include "exynos_drm_drv.h"
29 #include "exynos_drm_fbdev.h"
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_iommu.h"
34 * FIMD is stand for Fully Interactive Mobile Display and
35 * as a display controller, it transfers contents drawn on memory
36 * to a LCD Panel through Display Interfaces such as RGB or
40 #define FIMD_DEFAULT_FRAMERATE 60
42 /* position control register for hardware window 0, 2 ~ 4.*/
43 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
44 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
46 * size control register for hardware windows 0 and alpha control register
47 * for hardware windows 1 ~ 4
49 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
50 /* size control register for hardware windows 1 ~ 2. */
51 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
53 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
54 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
55 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
57 /* color key control register for hardware window 1 ~ 4. */
58 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
59 /* color key value register for hardware window 1 ~ 4. */
60 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
62 /* FIMD has totally five hardware windows. */
65 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
67 struct fimd_driver_data {
68 unsigned int timing_base;
70 unsigned int has_shadowcon:1;
71 unsigned int has_clksel:1;
72 unsigned int has_limited_fmt:1;
75 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
81 static struct fimd_driver_data exynos4_fimd_driver_data = {
86 static struct fimd_driver_data exynos5_fimd_driver_data = {
87 .timing_base = 0x20000,
91 struct fimd_win_data {
92 unsigned int offset_x;
93 unsigned int offset_y;
94 unsigned int ovl_width;
95 unsigned int ovl_height;
96 unsigned int fb_width;
97 unsigned int fb_height;
99 unsigned int pixel_format;
101 unsigned int buf_offsize;
102 unsigned int line_size; /* bytes */
107 struct fimd_context {
108 struct exynos_drm_subdrv subdrv;
110 struct drm_crtc *crtc;
114 struct fimd_win_data win_data[WINDOWS_NR];
116 unsigned int default_win;
117 unsigned long irq_flags;
122 wait_queue_head_t wait_vsync_queue;
123 atomic_t wait_vsync_event;
125 struct exynos_drm_panel_info *panel;
126 struct fimd_driver_data *driver_data;
130 static const struct of_device_id fimd_driver_dt_match[] = {
131 { .compatible = "samsung,s3c6400-fimd",
132 .data = &s3c64xx_fimd_driver_data },
133 { .compatible = "samsung,exynos4210-fimd",
134 .data = &exynos4_fimd_driver_data },
135 { .compatible = "samsung,exynos5250-fimd",
136 .data = &exynos5_fimd_driver_data },
141 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
142 struct platform_device *pdev)
145 const struct of_device_id *of_id =
146 of_match_device(fimd_driver_dt_match, &pdev->dev);
149 return (struct fimd_driver_data *)of_id->data;
152 return (struct fimd_driver_data *)
153 platform_get_device_id(pdev)->driver_data;
156 static bool fimd_display_is_connected(struct device *dev)
163 static void *fimd_get_panel(struct device *dev)
165 struct fimd_context *ctx = get_fimd_context(dev);
170 static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode)
177 static int fimd_display_power_on(struct device *dev, int mode)
184 static struct exynos_drm_display_ops fimd_display_ops = {
185 .type = EXYNOS_DISPLAY_TYPE_LCD,
186 .is_connected = fimd_display_is_connected,
187 .get_panel = fimd_get_panel,
188 .check_mode = fimd_check_mode,
189 .power_on = fimd_display_power_on,
192 static void fimd_dpms(struct device *subdrv_dev, int mode)
194 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
196 DRM_DEBUG_KMS("%d\n", mode);
198 mutex_lock(&ctx->lock);
201 case DRM_MODE_DPMS_ON:
203 * enable fimd hardware only if suspended status.
205 * P.S. fimd_dpms function would be called at booting time so
206 * clk_enable could be called double time.
209 pm_runtime_get_sync(subdrv_dev);
211 case DRM_MODE_DPMS_STANDBY:
212 case DRM_MODE_DPMS_SUSPEND:
213 case DRM_MODE_DPMS_OFF:
215 pm_runtime_put_sync(subdrv_dev);
218 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
222 mutex_unlock(&ctx->lock);
225 static void fimd_apply(struct device *subdrv_dev)
227 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
228 struct exynos_drm_manager *mgr = ctx->subdrv.manager;
229 struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
230 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
231 struct fimd_win_data *win_data;
234 for (i = 0; i < WINDOWS_NR; i++) {
235 win_data = &ctx->win_data[i];
236 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
237 ovl_ops->commit(subdrv_dev, i);
240 if (mgr_ops && mgr_ops->commit)
241 mgr_ops->commit(subdrv_dev);
244 static void fimd_commit(struct device *dev)
246 struct fimd_context *ctx = get_fimd_context(dev);
247 struct exynos_drm_panel_info *panel = ctx->panel;
248 struct videomode *vm = &panel->vm;
249 struct fimd_driver_data *driver_data;
252 driver_data = ctx->driver_data;
256 /* setup polarity values from machine code. */
257 writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
259 /* setup vertical timing values. */
260 val = VIDTCON0_VBPD(vm->vback_porch - 1) |
261 VIDTCON0_VFPD(vm->vfront_porch - 1) |
262 VIDTCON0_VSPW(vm->vsync_len - 1);
263 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
265 /* setup horizontal timing values. */
266 val = VIDTCON1_HBPD(vm->hback_porch - 1) |
267 VIDTCON1_HFPD(vm->hfront_porch - 1) |
268 VIDTCON1_HSPW(vm->hsync_len - 1);
269 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
271 /* setup horizontal and vertical display size. */
272 val = VIDTCON2_LINEVAL(vm->vactive - 1) |
273 VIDTCON2_HOZVAL(vm->hactive - 1) |
274 VIDTCON2_LINEVAL_E(vm->vactive - 1) |
275 VIDTCON2_HOZVAL_E(vm->hactive - 1);
276 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
278 /* setup clock source, clock divider, enable dma. */
280 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
282 if (ctx->driver_data->has_clksel) {
283 val &= ~VIDCON0_CLKSEL_MASK;
284 val |= VIDCON0_CLKSEL_LCD;
288 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
290 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
293 * fields of register with prefix '_F' would be updated
294 * at vsync(same as dma start)
296 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
297 writel(val, ctx->regs + VIDCON0);
300 static int fimd_enable_vblank(struct device *dev)
302 struct fimd_context *ctx = get_fimd_context(dev);
308 if (!test_and_set_bit(0, &ctx->irq_flags)) {
309 val = readl(ctx->regs + VIDINTCON0);
311 val |= VIDINTCON0_INT_ENABLE;
312 val |= VIDINTCON0_INT_FRAME;
314 val &= ~VIDINTCON0_FRAMESEL0_MASK;
315 val |= VIDINTCON0_FRAMESEL0_VSYNC;
316 val &= ~VIDINTCON0_FRAMESEL1_MASK;
317 val |= VIDINTCON0_FRAMESEL1_NONE;
319 writel(val, ctx->regs + VIDINTCON0);
325 static void fimd_disable_vblank(struct device *dev)
327 struct fimd_context *ctx = get_fimd_context(dev);
333 if (test_and_clear_bit(0, &ctx->irq_flags)) {
334 val = readl(ctx->regs + VIDINTCON0);
336 val &= ~VIDINTCON0_INT_FRAME;
337 val &= ~VIDINTCON0_INT_ENABLE;
339 writel(val, ctx->regs + VIDINTCON0);
343 static void fimd_wait_for_vblank(struct device *dev)
345 struct fimd_context *ctx = get_fimd_context(dev);
350 atomic_set(&ctx->wait_vsync_event, 1);
353 * wait for FIMD to signal VSYNC interrupt or return after
354 * timeout which is set to 50ms (refresh rate of 20).
356 if (!wait_event_timeout(ctx->wait_vsync_queue,
357 !atomic_read(&ctx->wait_vsync_event),
359 DRM_DEBUG_KMS("vblank wait timed out.\n");
362 static struct exynos_drm_manager_ops fimd_manager_ops = {
365 .commit = fimd_commit,
366 .enable_vblank = fimd_enable_vblank,
367 .disable_vblank = fimd_disable_vblank,
368 .wait_for_vblank = fimd_wait_for_vblank,
371 static void fimd_win_mode_set(struct device *dev,
372 struct exynos_drm_overlay *overlay)
374 struct fimd_context *ctx = get_fimd_context(dev);
375 struct fimd_win_data *win_data;
377 unsigned long offset;
380 dev_err(dev, "overlay is NULL\n");
385 if (win == DEFAULT_ZPOS)
386 win = ctx->default_win;
388 if (win < 0 || win >= WINDOWS_NR)
391 offset = overlay->fb_x * (overlay->bpp >> 3);
392 offset += overlay->fb_y * overlay->pitch;
394 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
396 win_data = &ctx->win_data[win];
398 win_data->offset_x = overlay->crtc_x;
399 win_data->offset_y = overlay->crtc_y;
400 win_data->ovl_width = overlay->crtc_width;
401 win_data->ovl_height = overlay->crtc_height;
402 win_data->fb_width = overlay->fb_width;
403 win_data->fb_height = overlay->fb_height;
404 win_data->dma_addr = overlay->dma_addr[0] + offset;
405 win_data->bpp = overlay->bpp;
406 win_data->pixel_format = overlay->pixel_format;
407 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
409 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
411 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
412 win_data->offset_x, win_data->offset_y);
413 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
414 win_data->ovl_width, win_data->ovl_height);
415 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
416 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
417 overlay->fb_width, overlay->crtc_width);
420 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
422 struct fimd_context *ctx = get_fimd_context(dev);
423 struct fimd_win_data *win_data = &ctx->win_data[win];
429 * In case of s3c64xx, window 0 doesn't support alpha channel.
430 * So the request format is ARGB8888 then change it to XRGB8888.
432 if (ctx->driver_data->has_limited_fmt && !win) {
433 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
434 win_data->pixel_format = DRM_FORMAT_XRGB8888;
437 switch (win_data->pixel_format) {
439 val |= WINCON0_BPPMODE_8BPP_PALETTE;
440 val |= WINCONx_BURSTLEN_8WORD;
441 val |= WINCONx_BYTSWP;
443 case DRM_FORMAT_XRGB1555:
444 val |= WINCON0_BPPMODE_16BPP_1555;
445 val |= WINCONx_HAWSWP;
446 val |= WINCONx_BURSTLEN_16WORD;
448 case DRM_FORMAT_RGB565:
449 val |= WINCON0_BPPMODE_16BPP_565;
450 val |= WINCONx_HAWSWP;
451 val |= WINCONx_BURSTLEN_16WORD;
453 case DRM_FORMAT_XRGB8888:
454 val |= WINCON0_BPPMODE_24BPP_888;
456 val |= WINCONx_BURSTLEN_16WORD;
458 case DRM_FORMAT_ARGB8888:
459 val |= WINCON1_BPPMODE_25BPP_A1888
460 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
462 val |= WINCONx_BURSTLEN_16WORD;
465 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
467 val |= WINCON0_BPPMODE_24BPP_888;
469 val |= WINCONx_BURSTLEN_16WORD;
473 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
475 writel(val, ctx->regs + WINCON(win));
478 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
480 struct fimd_context *ctx = get_fimd_context(dev);
481 unsigned int keycon0 = 0, keycon1 = 0;
483 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
484 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
486 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
488 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
489 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
493 * shadow_protect_win() - disable updating values from shadow registers at vsync
495 * @win: window to protect registers for
496 * @protect: 1 to protect (disable updates)
498 static void fimd_shadow_protect_win(struct fimd_context *ctx,
499 int win, bool protect)
503 if (ctx->driver_data->has_shadowcon) {
505 bits = SHADOWCON_WINx_PROTECT(win);
508 bits = PRTCON_PROTECT;
511 val = readl(ctx->regs + reg);
516 writel(val, ctx->regs + reg);
519 static void fimd_win_commit(struct device *dev, int zpos)
521 struct fimd_context *ctx = get_fimd_context(dev);
522 struct fimd_win_data *win_data;
524 unsigned long val, alpha, size;
531 if (win == DEFAULT_ZPOS)
532 win = ctx->default_win;
534 if (win < 0 || win >= WINDOWS_NR)
537 win_data = &ctx->win_data[win];
540 * SHADOWCON/PRTCON register is used for enabling timing.
542 * for example, once only width value of a register is set,
543 * if the dma is started then fimd hardware could malfunction so
544 * with protect window setting, the register fields with prefix '_F'
545 * wouldn't be updated at vsync also but updated once unprotect window
549 /* protect windows */
550 fimd_shadow_protect_win(ctx, win, true);
552 /* buffer start address */
553 val = (unsigned long)win_data->dma_addr;
554 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
556 /* buffer end address */
557 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
558 val = (unsigned long)(win_data->dma_addr + size);
559 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
561 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
562 (unsigned long)win_data->dma_addr, val, size);
563 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
564 win_data->ovl_width, win_data->ovl_height);
567 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
568 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
569 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
570 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
571 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
574 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
575 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
576 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
577 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
578 writel(val, ctx->regs + VIDOSD_A(win));
580 last_x = win_data->offset_x + win_data->ovl_width;
583 last_y = win_data->offset_y + win_data->ovl_height;
587 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
588 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
590 writel(val, ctx->regs + VIDOSD_B(win));
592 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
593 win_data->offset_x, win_data->offset_y, last_x, last_y);
595 /* hardware window 0 doesn't support alpha channel. */
598 alpha = VIDISD14C_ALPHA1_R(0xf) |
599 VIDISD14C_ALPHA1_G(0xf) |
600 VIDISD14C_ALPHA1_B(0xf);
602 writel(alpha, ctx->regs + VIDOSD_C(win));
606 if (win != 3 && win != 4) {
607 u32 offset = VIDOSD_D(win);
609 offset = VIDOSD_C(win);
610 val = win_data->ovl_width * win_data->ovl_height;
611 writel(val, ctx->regs + offset);
613 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
616 fimd_win_set_pixfmt(dev, win);
618 /* hardware window 0 doesn't support color key. */
620 fimd_win_set_colkey(dev, win);
623 val = readl(ctx->regs + WINCON(win));
624 val |= WINCONx_ENWIN;
625 writel(val, ctx->regs + WINCON(win));
627 /* Enable DMA channel and unprotect windows */
628 fimd_shadow_protect_win(ctx, win, false);
630 if (ctx->driver_data->has_shadowcon) {
631 val = readl(ctx->regs + SHADOWCON);
632 val |= SHADOWCON_CHx_ENABLE(win);
633 writel(val, ctx->regs + SHADOWCON);
636 win_data->enabled = true;
639 static void fimd_win_disable(struct device *dev, int zpos)
641 struct fimd_context *ctx = get_fimd_context(dev);
642 struct fimd_win_data *win_data;
646 if (win == DEFAULT_ZPOS)
647 win = ctx->default_win;
649 if (win < 0 || win >= WINDOWS_NR)
652 win_data = &ctx->win_data[win];
654 if (ctx->suspended) {
655 /* do not resume this window*/
656 win_data->resume = false;
660 /* protect windows */
661 fimd_shadow_protect_win(ctx, win, true);
664 val = readl(ctx->regs + WINCON(win));
665 val &= ~WINCONx_ENWIN;
666 writel(val, ctx->regs + WINCON(win));
668 /* unprotect windows */
669 if (ctx->driver_data->has_shadowcon) {
670 val = readl(ctx->regs + SHADOWCON);
671 val &= ~SHADOWCON_CHx_ENABLE(win);
672 writel(val, ctx->regs + SHADOWCON);
675 fimd_shadow_protect_win(ctx, win, false);
677 win_data->enabled = false;
680 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
681 .mode_set = fimd_win_mode_set,
682 .commit = fimd_win_commit,
683 .disable = fimd_win_disable,
686 static struct exynos_drm_manager fimd_manager = {
688 .ops = &fimd_manager_ops,
689 .overlay_ops = &fimd_overlay_ops,
690 .display_ops = &fimd_display_ops,
693 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
695 struct fimd_context *ctx = (struct fimd_context *)dev_id;
696 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
697 struct drm_device *drm_dev = subdrv->drm_dev;
698 struct exynos_drm_manager *manager = subdrv->manager;
701 val = readl(ctx->regs + VIDINTCON1);
703 if (val & VIDINTCON1_INT_FRAME)
704 /* VSYNC interrupt */
705 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
707 /* check the crtc is detached already from encoder */
708 if (manager->pipe < 0)
711 drm_handle_vblank(drm_dev, manager->pipe);
712 exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe);
714 /* set wait vsync event to zero and wake up queue. */
715 if (atomic_read(&ctx->wait_vsync_event)) {
716 atomic_set(&ctx->wait_vsync_event, 0);
717 DRM_WAKEUP(&ctx->wait_vsync_queue);
723 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
726 * enable drm irq mode.
727 * - with irq_enabled = 1, we can use the vblank feature.
729 * P.S. note that we wouldn't use drm irq handler but
730 * just specific driver own one instead because
731 * drm framework supports only one irq handler.
733 drm_dev->irq_enabled = 1;
736 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
737 * by drm timer once a current process gives up ownership of
738 * vblank event.(after drm_vblank_put function is called)
740 drm_dev->vblank_disable_allowed = 1;
742 /* attach this sub driver to iommu mapping if supported. */
743 if (is_drm_iommu_supported(drm_dev))
744 drm_iommu_attach_device(drm_dev, dev);
749 static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
751 /* detach this sub driver from iommu mapping if supported. */
752 if (is_drm_iommu_supported(drm_dev))
753 drm_iommu_detach_device(drm_dev, dev);
756 static int fimd_configure_clocks(struct fimd_context *ctx, struct device *dev)
758 struct videomode *vm = &ctx->panel->vm;
761 ctx->bus_clk = devm_clk_get(dev, "fimd");
762 if (IS_ERR(ctx->bus_clk)) {
763 dev_err(dev, "failed to get bus clock\n");
764 return PTR_ERR(ctx->bus_clk);
767 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
768 if (IS_ERR(ctx->lcd_clk)) {
769 dev_err(dev, "failed to get lcd clock\n");
770 return PTR_ERR(ctx->lcd_clk);
773 clk = clk_get_rate(ctx->lcd_clk);
775 dev_err(dev, "error getting sclk_fimd clock rate\n");
779 if (vm->pixelclock == 0) {
781 c = vm->hactive + vm->hback_porch + vm->hfront_porch +
783 c *= vm->vactive + vm->vback_porch + vm->vfront_porch +
785 vm->pixelclock = c * FIMD_DEFAULT_FRAMERATE;
786 if (vm->pixelclock == 0) {
787 dev_err(dev, "incorrect display timings\n");
790 dev_warn(dev, "pixel clock recalculated to %luHz (%dHz frame rate)\n",
791 vm->pixelclock, FIMD_DEFAULT_FRAMERATE);
793 ctx->clkdiv = DIV_ROUND_UP(clk, vm->pixelclock);
794 if (ctx->clkdiv > 256) {
795 dev_warn(dev, "calculated pixel clock divider too high (%u), lowered to 256\n",
799 vm->pixelclock = clk / ctx->clkdiv;
800 DRM_DEBUG_KMS("pixel clock = %lu, clkdiv = %d\n", vm->pixelclock,
806 static void fimd_clear_win(struct fimd_context *ctx, int win)
808 writel(0, ctx->regs + WINCON(win));
809 writel(0, ctx->regs + VIDOSD_A(win));
810 writel(0, ctx->regs + VIDOSD_B(win));
811 writel(0, ctx->regs + VIDOSD_C(win));
813 if (win == 1 || win == 2)
814 writel(0, ctx->regs + VIDOSD_D(win));
816 fimd_shadow_protect_win(ctx, win, false);
819 static int fimd_clock(struct fimd_context *ctx, bool enable)
824 ret = clk_prepare_enable(ctx->bus_clk);
828 ret = clk_prepare_enable(ctx->lcd_clk);
830 clk_disable_unprepare(ctx->bus_clk);
834 clk_disable_unprepare(ctx->lcd_clk);
835 clk_disable_unprepare(ctx->bus_clk);
841 static void fimd_window_suspend(struct device *dev)
843 struct fimd_context *ctx = get_fimd_context(dev);
844 struct fimd_win_data *win_data;
847 for (i = 0; i < WINDOWS_NR; i++) {
848 win_data = &ctx->win_data[i];
849 win_data->resume = win_data->enabled;
850 fimd_win_disable(dev, i);
852 fimd_wait_for_vblank(dev);
855 static void fimd_window_resume(struct device *dev)
857 struct fimd_context *ctx = get_fimd_context(dev);
858 struct fimd_win_data *win_data;
861 for (i = 0; i < WINDOWS_NR; i++) {
862 win_data = &ctx->win_data[i];
863 win_data->enabled = win_data->resume;
864 win_data->resume = false;
868 static int fimd_activate(struct fimd_context *ctx, bool enable)
870 struct device *dev = ctx->subdrv.dev;
874 ret = fimd_clock(ctx, true);
878 ctx->suspended = false;
880 /* if vblank was enabled status, enable it again. */
881 if (test_and_clear_bit(0, &ctx->irq_flags))
882 fimd_enable_vblank(dev);
884 fimd_window_resume(dev);
886 fimd_window_suspend(dev);
888 fimd_clock(ctx, false);
889 ctx->suspended = true;
895 static int fimd_probe(struct platform_device *pdev)
897 struct device *dev = &pdev->dev;
898 struct fimd_context *ctx;
899 struct exynos_drm_subdrv *subdrv;
900 struct exynos_drm_fimd_pdata *pdata;
901 struct exynos_drm_panel_info *panel;
902 struct resource *res;
907 struct videomode *vm;
908 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
912 vm = &pdata->panel.vm;
913 ret = of_get_videomode(dev->of_node, vm, OF_USE_NATIVE_MODE);
915 DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
919 pdata = dev->platform_data;
921 DRM_ERROR("no platform data specified\n");
926 panel = &pdata->panel;
928 dev_err(dev, "panel is null.\n");
932 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
936 ret = fimd_configure_clocks(ctx, dev);
940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
942 ctx->regs = devm_ioremap_resource(dev, res);
943 if (IS_ERR(ctx->regs))
944 return PTR_ERR(ctx->regs);
946 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
948 dev_err(dev, "irq request failed.\n");
952 ctx->irq = res->start;
954 ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler,
957 dev_err(dev, "irq request failed.\n");
961 ctx->driver_data = drm_fimd_get_driver_data(pdev);
962 ctx->vidcon0 = pdata->vidcon0;
963 ctx->vidcon1 = pdata->vidcon1;
964 ctx->default_win = pdata->default_win;
966 DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
967 atomic_set(&ctx->wait_vsync_event, 0);
969 subdrv = &ctx->subdrv;
972 subdrv->manager = &fimd_manager;
973 subdrv->probe = fimd_subdrv_probe;
974 subdrv->remove = fimd_subdrv_remove;
976 mutex_init(&ctx->lock);
978 platform_set_drvdata(pdev, ctx);
980 pm_runtime_enable(dev);
981 pm_runtime_get_sync(dev);
983 for (win = 0; win < WINDOWS_NR; win++)
984 fimd_clear_win(ctx, win);
986 exynos_drm_subdrv_register(subdrv);
991 static int fimd_remove(struct platform_device *pdev)
993 struct device *dev = &pdev->dev;
994 struct fimd_context *ctx = platform_get_drvdata(pdev);
996 exynos_drm_subdrv_unregister(&ctx->subdrv);
1001 pm_runtime_set_suspended(dev);
1002 pm_runtime_put_sync(dev);
1005 pm_runtime_disable(dev);
1010 #ifdef CONFIG_PM_SLEEP
1011 static int fimd_suspend(struct device *dev)
1013 struct fimd_context *ctx = get_fimd_context(dev);
1016 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
1017 * called here, an error would be returned by that interface
1018 * because the usage_count of pm runtime is more than 1.
1020 if (!pm_runtime_suspended(dev))
1021 return fimd_activate(ctx, false);
1026 static int fimd_resume(struct device *dev)
1028 struct fimd_context *ctx = get_fimd_context(dev);
1031 * if entered to sleep when lcd panel was on, the usage_count
1032 * of pm runtime would still be 1 so in this case, fimd driver
1033 * should be on directly not drawing on pm runtime interface.
1035 if (!pm_runtime_suspended(dev)) {
1038 ret = fimd_activate(ctx, true);
1043 * in case of dpms on(standby), fimd_apply function will
1044 * be called by encoder's dpms callback to update fimd's
1045 * registers but in case of sleep wakeup, it's not.
1046 * so fimd_apply function should be called at here.
1055 #ifdef CONFIG_PM_RUNTIME
1056 static int fimd_runtime_suspend(struct device *dev)
1058 struct fimd_context *ctx = get_fimd_context(dev);
1060 return fimd_activate(ctx, false);
1063 static int fimd_runtime_resume(struct device *dev)
1065 struct fimd_context *ctx = get_fimd_context(dev);
1067 return fimd_activate(ctx, true);
1071 static struct platform_device_id fimd_driver_ids[] = {
1073 .name = "s3c64xx-fb",
1074 .driver_data = (unsigned long)&s3c64xx_fimd_driver_data,
1076 .name = "exynos4-fb",
1077 .driver_data = (unsigned long)&exynos4_fimd_driver_data,
1079 .name = "exynos5-fb",
1080 .driver_data = (unsigned long)&exynos5_fimd_driver_data,
1085 static const struct dev_pm_ops fimd_pm_ops = {
1086 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1087 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1090 struct platform_driver fimd_driver = {
1091 .probe = fimd_probe,
1092 .remove = fimd_remove,
1093 .id_table = fimd_driver_ids,
1095 .name = "exynos4-fb",
1096 .owner = THIS_MODULE,
1098 .of_match_table = of_match_ptr(fimd_driver_dt_match),