drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fb.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_plane.h"
  35 #include "exynos_drm_iommu.h"
  36
  37 /*
  38  * FIMD stands for Fully Interactive Mobile Display and
  39  * as a display controller, it transfers contents drawn on memory
  40  * to a LCD Panel through Display Interfaces such as RGB or
  41  * CPU Interface.
  42  */
  43
  44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  45
  46 /* position control register for hardware window 0, 2 ~ 4.*/
  47 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  48 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  49 /*
  50  * size control register for hardware windows 0 and alpha control register
  51  * for hardware windows 1 ~ 4
  52  */
  53 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  54 /* size control register for hardware windows 1 ~ 2. */
  55 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  56
  57 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  58 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  59
  60 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  61 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  62 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  63 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  64
  65 /* color key control register for hardware window 1 ~ 4. */
  66 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  67 /* color key value register for hardware window 1 ~ 4. */
  68 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  69
  70 /* I80 trigger control register */
  71 #define TRIGCON                         0x1A4
  72 #define TRGMODE_ENABLE                  (1 << 0)
  73 #define SWTRGCMD_ENABLE                 (1 << 1)
  74 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
  75 #define HWTRGEN_ENABLE                  (1 << 3)
  76 #define HWTRGMASK_ENABLE                (1 << 4)
  77 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
  78 #define HWTRIGEN_PER_ENABLE             (1 << 31)
  79
  80 /* display mode change control register except exynos4 */
  81 #define VIDOUT_CON                      0x000
  82 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  83
  84 /* I80 interface control for main LDI register */
  85 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  86 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  87 #define LCD_CS_SETUP(x)                 ((x) << 16)
  88 #define LCD_WR_SETUP(x)                 ((x) << 12)
  89 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  90 #define LCD_WR_HOLD(x)                  ((x) << 4)
  91 #define I80IFEN_ENABLE                  (1 << 0)
  92
  93 /* FIMD has totally five hardware windows. */
  94 #define WINDOWS_NR      5
  95
  96 /* HW trigger flag on i80 panel. */
  97 #define I80_HW_TRG     (1 << 1)
  98
  99 struct fimd_driver_data {
 100         unsigned int timing_base;
 101         unsigned int lcdblk_offset;
 102         unsigned int lcdblk_vt_shift;
 103         unsigned int lcdblk_bypass_shift;
 104         unsigned int lcdblk_mic_bypass_shift;
 105         unsigned int trg_type;
 106
 107         unsigned int has_shadowcon:1;
 108         unsigned int has_clksel:1;
 109         unsigned int has_limited_fmt:1;
 110         unsigned int has_vidoutcon:1;
 111         unsigned int has_vtsel:1;
 112         unsigned int has_mic_bypass:1;
 113         unsigned int has_dp_clk:1;
 114         unsigned int has_hw_trigger:1;
 115         unsigned int has_trigger_per_te:1;
 116 };
 117
 118 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 119         .timing_base = 0x0,
 120         .has_clksel = 1,
 121         .has_limited_fmt = 1,
 122 };
 123
 124 static struct fimd_driver_data exynos3_fimd_driver_data = {
 125         .timing_base = 0x20000,
 126         .lcdblk_offset = 0x210,
 127         .lcdblk_bypass_shift = 1,
 128         .has_shadowcon = 1,
 129         .has_vidoutcon = 1,
 130 };
 131
 132 static struct fimd_driver_data exynos4_fimd_driver_data = {
 133         .timing_base = 0x0,
 134         .lcdblk_offset = 0x210,
 135         .lcdblk_vt_shift = 10,
 136         .lcdblk_bypass_shift = 1,
 137         .has_shadowcon = 1,
 138         .has_vtsel = 1,
 139 };
 140
 141 static struct fimd_driver_data exynos5_fimd_driver_data = {
 142         .timing_base = 0x20000,
 143         .lcdblk_offset = 0x214,
 144         .lcdblk_vt_shift = 24,
 145         .lcdblk_bypass_shift = 15,
 146         .has_shadowcon = 1,
 147         .has_vidoutcon = 1,
 148         .has_vtsel = 1,
 149         .has_dp_clk = 1,
 150 };
 151
 152 static struct fimd_driver_data exynos5420_fimd_driver_data = {
 153         .timing_base = 0x20000,
 154         .lcdblk_offset = 0x214,
 155         .lcdblk_vt_shift = 24,
 156         .lcdblk_bypass_shift = 15,
 157         .lcdblk_mic_bypass_shift = 11,
 158         .has_shadowcon = 1,
 159         .has_vidoutcon = 1,
 160         .has_vtsel = 1,
 161         .has_mic_bypass = 1,
 162         .has_dp_clk = 1,
 163 };
 164
 165 struct fimd_context {
 166         struct device                   *dev;
 167         struct drm_device               *drm_dev;
 168         struct exynos_drm_crtc          *crtc;
 169         struct exynos_drm_plane         planes[WINDOWS_NR];
 170         struct exynos_drm_plane_config  configs[WINDOWS_NR];
 171         struct clk                      *bus_clk;
 172         struct clk                      *lcd_clk;
 173         void __iomem                    *regs;
 174         struct regmap                   *sysreg;
 175         unsigned long                   irq_flags;
 176         u32                             vidcon0;
 177         u32                             vidcon1;
 178         u32                             vidout_con;
 179         u32                             i80ifcon;
 180         bool                            i80_if;
 181         bool                            suspended;
 182         int                             pipe;
 183         wait_queue_head_t               wait_vsync_queue;
 184         atomic_t                        wait_vsync_event;
 185         atomic_t                        win_updated;
 186         atomic_t                        triggering;
 187         u32                             clkdiv;
 188
 189         const struct fimd_driver_data *driver_data;
 190         struct drm_encoder *encoder;
 191         struct exynos_drm_clk           dp_clk;
 192 };
 193
 194 static const struct of_device_id fimd_driver_dt_match[] = {
 195         { .compatible = "samsung,s3c6400-fimd",
 196           .data = &s3c64xx_fimd_driver_data },
 197         { .compatible = "samsung,exynos3250-fimd",
 198           .data = &exynos3_fimd_driver_data },
 199         { .compatible = "samsung,exynos4210-fimd",
 200           .data = &exynos4_fimd_driver_data },
 201         { .compatible = "samsung,exynos5250-fimd",
 202           .data = &exynos5_fimd_driver_data },
 203         { .compatible = "samsung,exynos5420-fimd",
 204           .data = &exynos5420_fimd_driver_data },
 205         {},
 206 };
 207 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 208
 209 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
 210         DRM_PLANE_TYPE_PRIMARY,
 211         DRM_PLANE_TYPE_OVERLAY,
 212         DRM_PLANE_TYPE_OVERLAY,
 213         DRM_PLANE_TYPE_OVERLAY,
 214         DRM_PLANE_TYPE_CURSOR,
 215 };
 216
 217 static const uint32_t fimd_formats[] = {
 218         DRM_FORMAT_C8,
 219         DRM_FORMAT_XRGB1555,
 220         DRM_FORMAT_RGB565,
 221         DRM_FORMAT_XRGB8888,
 222         DRM_FORMAT_ARGB8888,
 223 };
 224
 225 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 226 {
 227         struct fimd_context *ctx = crtc->ctx;
 228         u32 val;
 229
 230         if (ctx->suspended)
 231                 return -EPERM;
 232
 233         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 234                 val = readl(ctx->regs + VIDINTCON0);
 235
 236                 val |= VIDINTCON0_INT_ENABLE;
 237
 238                 if (ctx->i80_if) {
 239                         val |= VIDINTCON0_INT_I80IFDONE;
 240                         val |= VIDINTCON0_INT_SYSMAINCON;
 241                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 242                 } else {
 243                         val |= VIDINTCON0_INT_FRAME;
 244
 245                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 246                         val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
 247                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 248                         val |= VIDINTCON0_FRAMESEL1_NONE;
 249                 }
 250
 251                 writel(val, ctx->regs + VIDINTCON0);
 252         }
 253
 254         return 0;
 255 }
 256
 257 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 258 {
 259         struct fimd_context *ctx = crtc->ctx;
 260         u32 val;
 261
 262         if (ctx->suspended)
 263                 return;
 264
 265         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 266                 val = readl(ctx->regs + VIDINTCON0);
 267
 268                 val &= ~VIDINTCON0_INT_ENABLE;
 269
 270                 if (ctx->i80_if) {
 271                         val &= ~VIDINTCON0_INT_I80IFDONE;
 272                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 273                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 274                 } else
 275                         val &= ~VIDINTCON0_INT_FRAME;
 276
 277                 writel(val, ctx->regs + VIDINTCON0);
 278         }
 279 }
 280
 281 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 282 {
 283         struct fimd_context *ctx = crtc->ctx;
 284
 285         if (ctx->suspended)
 286                 return;
 287
 288         atomic_set(&ctx->wait_vsync_event, 1);
 289
 290         /*
 291          * wait for FIMD to signal VSYNC interrupt or return after
 292          * timeout which is set to 50ms (refresh rate of 20).
 293          */
 294         if (!wait_event_timeout(ctx->wait_vsync_queue,
 295                                 !atomic_read(&ctx->wait_vsync_event),
 296                                 HZ/20))
 297                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 298 }
 299
 300 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 301                                         bool enable)
 302 {
 303         u32 val = readl(ctx->regs + WINCON(win));
 304
 305         if (enable)
 306                 val |= WINCONx_ENWIN;
 307         else
 308                 val &= ~WINCONx_ENWIN;
 309
 310         writel(val, ctx->regs + WINCON(win));
 311 }
 312
 313 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 314                                                 unsigned int win,
 315                                                 bool enable)
 316 {
 317         u32 val = readl(ctx->regs + SHADOWCON);
 318
 319         if (enable)
 320                 val |= SHADOWCON_CHx_ENABLE(win);
 321         else
 322                 val &= ~SHADOWCON_CHx_ENABLE(win);
 323
 324         writel(val, ctx->regs + SHADOWCON);
 325 }
 326
 327 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 328 {
 329         struct fimd_context *ctx = crtc->ctx;
 330         unsigned int win, ch_enabled = 0;
 331
 332         DRM_DEBUG_KMS("%s\n", __FILE__);
 333
 334         /* Hardware is in unknown state, so ensure it gets enabled properly */
 335         pm_runtime_get_sync(ctx->dev);
 336
 337         clk_prepare_enable(ctx->bus_clk);
 338         clk_prepare_enable(ctx->lcd_clk);
 339
 340         /* Check if any channel is enabled. */
 341         for (win = 0; win < WINDOWS_NR; win++) {
 342                 u32 val = readl(ctx->regs + WINCON(win));
 343
 344                 if (val & WINCONx_ENWIN) {
 345                         fimd_enable_video_output(ctx, win, false);
 346
 347                         if (ctx->driver_data->has_shadowcon)
 348                                 fimd_enable_shadow_channel_path(ctx, win,
 349                                                                 false);
 350
 351                         ch_enabled = 1;
 352                 }
 353         }
 354
 355         /* Wait for vsync, as disable channel takes effect at next vsync */
 356         if (ch_enabled) {
 357                 int pipe = ctx->pipe;
 358
 359                 /* ensure that vblank interrupt won't be reported to core */
 360                 ctx->suspended = false;
 361                 ctx->pipe = -1;
 362
 363                 fimd_enable_vblank(ctx->crtc);
 364                 fimd_wait_for_vblank(ctx->crtc);
 365                 fimd_disable_vblank(ctx->crtc);
 366
 367                 ctx->suspended = true;
 368                 ctx->pipe = pipe;
 369         }
 370
 371         clk_disable_unprepare(ctx->lcd_clk);
 372         clk_disable_unprepare(ctx->bus_clk);
 373
 374         pm_runtime_put(ctx->dev);
 375 }
 376
 377
 378 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
 379                 struct drm_crtc_state *state)
 380 {
 381         struct drm_display_mode *mode = &state->adjusted_mode;
 382         struct fimd_context *ctx = crtc->ctx;
 383         unsigned long ideal_clk, lcd_rate;
 384         u32 clkdiv;
 385
 386         if (mode->clock == 0) {
 387                 DRM_INFO("Mode has zero clock value.\n");
 388                 return -EINVAL;
 389         }
 390
 391         ideal_clk = mode->clock * 1000;
 392
 393         if (ctx->i80_if) {
 394                 /*
 395                  * The frame done interrupt should be occurred prior to the
 396                  * next TE signal.
 397                  */
 398                 ideal_clk *= 2;
 399         }
 400
 401         lcd_rate = clk_get_rate(ctx->lcd_clk);
 402         if (2 * lcd_rate < ideal_clk) {
 403                 DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
 404                          lcd_rate, ideal_clk);
 405                 return -EINVAL;
 406         }
 407
 408         /* Find the clock divider value that gets us closest to ideal_clk */
 409         clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
 410         if (clkdiv >= 0x200) {
 411                 DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk);
 412                 return -EINVAL;
 413         }
 414
 415         ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
 416
 417         return 0;
 418 }
 419
 420 static void fimd_setup_trigger(struct fimd_context *ctx)
 421 {
 422         void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
 423         u32 trg_type = ctx->driver_data->trg_type;
 424         u32 val = readl(timing_base + TRIGCON);
 425
 426         val &= ~(TRGMODE_ENABLE);
 427
 428         if (trg_type == I80_HW_TRG) {
 429                 if (ctx->driver_data->has_hw_trigger)
 430                         val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
 431                 if (ctx->driver_data->has_trigger_per_te)
 432                         val |= HWTRIGEN_PER_ENABLE;
 433         } else {
 434                 val |= TRGMODE_ENABLE;
 435         }
 436
 437         writel(val, timing_base + TRIGCON);
 438 }
 439
 440 static void fimd_commit(struct exynos_drm_crtc *crtc)
 441 {
 442         struct fimd_context *ctx = crtc->ctx;
 443         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 444         const struct fimd_driver_data *driver_data = ctx->driver_data;
 445         void *timing_base = ctx->regs + driver_data->timing_base;
 446         u32 val;
 447
 448         if (ctx->suspended)
 449                 return;
 450
 451         /* nothing to do if we haven't set the mode yet */
 452         if (mode->htotal == 0 || mode->vtotal == 0)
 453                 return;
 454
 455         if (ctx->i80_if) {
 456                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 457                 writel(val, timing_base + I80IFCONFAx(0));
 458
 459                 /* disable auto frame rate */
 460                 writel(0, timing_base + I80IFCONFBx(0));
 461
 462                 /* set video type selection to I80 interface */
 463                 if (driver_data->has_vtsel && ctx->sysreg &&
 464                                 regmap_update_bits(ctx->sysreg,
 465                                         driver_data->lcdblk_offset,
 466                                         0x3 << driver_data->lcdblk_vt_shift,
 467                                         0x1 << driver_data->lcdblk_vt_shift)) {
 468                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 469                         return;
 470                 }
 471         } else {
 472                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 473                 u32 vidcon1;
 474
 475                 /* setup polarity values */
 476                 vidcon1 = ctx->vidcon1;
 477                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 478                         vidcon1 |= VIDCON1_INV_VSYNC;
 479                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 480                         vidcon1 |= VIDCON1_INV_HSYNC;
 481                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 482
 483                 /* setup vertical timing values. */
 484                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 485                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 486                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 487
 488                 val = VIDTCON0_VBPD(vbpd - 1) |
 489                         VIDTCON0_VFPD(vfpd - 1) |
 490                         VIDTCON0_VSPW(vsync_len - 1);
 491                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 492
 493                 /* setup horizontal timing values.  */
 494                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 495                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 496                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 497
 498                 val = VIDTCON1_HBPD(hbpd - 1) |
 499                         VIDTCON1_HFPD(hfpd - 1) |
 500                         VIDTCON1_HSPW(hsync_len - 1);
 501                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 502         }
 503
 504         if (driver_data->has_vidoutcon)
 505                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 506
 507         /* set bypass selection */
 508         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 509                                 driver_data->lcdblk_offset,
 510                                 0x1 << driver_data->lcdblk_bypass_shift,
 511                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 512                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 513                 return;
 514         }
 515
 516         /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
 517          * bit should be cleared.
 518          */
 519         if (driver_data->has_mic_bypass && ctx->sysreg &&
 520             regmap_update_bits(ctx->sysreg,
 521                                 driver_data->lcdblk_offset,
 522                                 0x1 << driver_data->lcdblk_mic_bypass_shift,
 523                                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
 524                 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
 525                 return;
 526         }
 527
 528         /* setup horizontal and vertical display size. */
 529         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 530                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 531                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 532                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 533         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 534
 535         fimd_setup_trigger(ctx);
 536
 537         /*
 538          * fields of register with prefix '_F' would be updated
 539          * at vsync(same as dma start)
 540          */
 541         val = ctx->vidcon0;
 542         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 543
 544         if (ctx->driver_data->has_clksel)
 545                 val |= VIDCON0_CLKSEL_LCD;
 546
 547         if (ctx->clkdiv > 1)
 548                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 549
 550         writel(val, ctx->regs + VIDCON0);
 551 }
 552
 553
 554 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 555                                 uint32_t pixel_format, int width)
 556 {
 557         unsigned long val;
 558
 559         val = WINCONx_ENWIN;
 560
 561         /*
 562          * In case of s3c64xx, window 0 doesn't support alpha channel.
 563          * So the request format is ARGB8888 then change it to XRGB8888.
 564          */
 565         if (ctx->driver_data->has_limited_fmt && !win) {
 566                 if (pixel_format == DRM_FORMAT_ARGB8888)
 567                         pixel_format = DRM_FORMAT_XRGB8888;
 568         }
 569
 570         switch (pixel_format) {
 571         case DRM_FORMAT_C8:
 572                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 573                 val |= WINCONx_BURSTLEN_8WORD;
 574                 val |= WINCONx_BYTSWP;
 575                 break;
 576         case DRM_FORMAT_XRGB1555:
 577                 val |= WINCON0_BPPMODE_16BPP_1555;
 578                 val |= WINCONx_HAWSWP;
 579                 val |= WINCONx_BURSTLEN_16WORD;
 580                 break;
 581         case DRM_FORMAT_RGB565:
 582                 val |= WINCON0_BPPMODE_16BPP_565;
 583                 val |= WINCONx_HAWSWP;
 584                 val |= WINCONx_BURSTLEN_16WORD;
 585                 break;
 586         case DRM_FORMAT_XRGB8888:
 587                 val |= WINCON0_BPPMODE_24BPP_888;
 588                 val |= WINCONx_WSWP;
 589                 val |= WINCONx_BURSTLEN_16WORD;
 590                 break;
 591         case DRM_FORMAT_ARGB8888:
 592                 val |= WINCON1_BPPMODE_25BPP_A1888
 593                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 594                 val |= WINCONx_WSWP;
 595                 val |= WINCONx_BURSTLEN_16WORD;
 596                 break;
 597         default:
 598                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 599
 600                 val |= WINCON0_BPPMODE_24BPP_888;
 601                 val |= WINCONx_WSWP;
 602                 val |= WINCONx_BURSTLEN_16WORD;
 603                 break;
 604         }
 605
 606         /*
 607          * Setting dma-burst to 16Word causes permanent tearing for very small
 608          * buffers, e.g. cursor buffer. Burst Mode switching which based on
 609          * plane size is not recommended as plane size varies alot towards the
 610          * end of the screen and rapid movement causes unstable DMA, but it is
 611          * still better to change dma-burst than displaying garbage.
 612          */
 613
 614         if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 615                 val &= ~WINCONx_BURSTLEN_MASK;
 616                 val |= WINCONx_BURSTLEN_4WORD;
 617         }
 618
 619         writel(val, ctx->regs + WINCON(win));
 620
 621         /* hardware window 0 doesn't support alpha channel. */
 622         if (win != 0) {
 623                 /* OSD alpha */
 624                 val = VIDISD14C_ALPHA0_R(0xf) |
 625                         VIDISD14C_ALPHA0_G(0xf) |
 626                         VIDISD14C_ALPHA0_B(0xf) |
 627                         VIDISD14C_ALPHA1_R(0xf) |
 628                         VIDISD14C_ALPHA1_G(0xf) |
 629                         VIDISD14C_ALPHA1_B(0xf);
 630
 631                 writel(val, ctx->regs + VIDOSD_C(win));
 632
 633                 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
 634                         VIDW_ALPHA_G(0xf);
 635                 writel(val, ctx->regs + VIDWnALPHA0(win));
 636                 writel(val, ctx->regs + VIDWnALPHA1(win));
 637         }
 638 }
 639
 640 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 641 {
 642         unsigned int keycon0 = 0, keycon1 = 0;
 643
 644         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 645                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 646
 647         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 648
 649         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 650         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 651 }
 652
 653 /**
 654  * shadow_protect_win() - disable updating values from shadow registers at vsync
 655  *
 656  * @win: window to protect registers for
 657  * @protect: 1 to protect (disable updates)
 658  */
 659 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 660                                     unsigned int win, bool protect)
 661 {
 662         u32 reg, bits, val;
 663
 664         /*
 665          * SHADOWCON/PRTCON register is used for enabling timing.
 666          *
 667          * for example, once only width value of a register is set,
 668          * if the dma is started then fimd hardware could malfunction so
 669          * with protect window setting, the register fields with prefix '_F'
 670          * wouldn't be updated at vsync also but updated once unprotect window
 671          * is set.
 672          */
 673
 674         if (ctx->driver_data->has_shadowcon) {
 675                 reg = SHADOWCON;
 676                 bits = SHADOWCON_WINx_PROTECT(win);
 677         } else {
 678                 reg = PRTCON;
 679                 bits = PRTCON_PROTECT;
 680         }
 681
 682         val = readl(ctx->regs + reg);
 683         if (protect)
 684                 val |= bits;
 685         else
 686                 val &= ~bits;
 687         writel(val, ctx->regs + reg);
 688 }
 689
 690 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
 691 {
 692         struct fimd_context *ctx = crtc->ctx;
 693         int i;
 694
 695         if (ctx->suspended)
 696                 return;
 697
 698         for (i = 0; i < WINDOWS_NR; i++)
 699                 fimd_shadow_protect_win(ctx, i, true);
 700 }
 701
 702 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
 703 {
 704         struct fimd_context *ctx = crtc->ctx;
 705         int i;
 706
 707         if (ctx->suspended)
 708                 return;
 709
 710         for (i = 0; i < WINDOWS_NR; i++)
 711                 fimd_shadow_protect_win(ctx, i, false);
 712
 713         exynos_crtc_handle_event(crtc);
 714 }
 715
 716 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 717                               struct exynos_drm_plane *plane)
 718 {
 719         struct exynos_drm_plane_state *state =
 720                                 to_exynos_plane_state(plane->base.state);
 721         struct fimd_context *ctx = crtc->ctx;
 722         struct drm_framebuffer *fb = state->base.fb;
 723         dma_addr_t dma_addr;
 724         unsigned long val, size, offset;
 725         unsigned int last_x, last_y, buf_offsize, line_size;
 726         unsigned int win = plane->index;
 727         unsigned int bpp = fb->format->cpp[0];
 728         unsigned int pitch = fb->pitches[0];
 729
 730         if (ctx->suspended)
 731                 return;
 732
 733         offset = state->src.x * bpp;
 734         offset += state->src.y * pitch;
 735
 736         /* buffer start address */
 737         dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
 738         val = (unsigned long)dma_addr;
 739         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 740
 741         /* buffer end address */
 742         size = pitch * state->crtc.h;
 743         val = (unsigned long)(dma_addr + size);
 744         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 745
 746         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 747                         (unsigned long)dma_addr, val, size);
 748         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 749                         state->crtc.w, state->crtc.h);
 750
 751         /* buffer size */
 752         buf_offsize = pitch - (state->crtc.w * bpp);
 753         line_size = state->crtc.w * bpp;
 754         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 755                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 756                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 757                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 758         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 759
 760         /* OSD position */
 761         val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
 762                 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
 763                 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
 764                 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
 765         writel(val, ctx->regs + VIDOSD_A(win));
 766
 767         last_x = state->crtc.x + state->crtc.w;
 768         if (last_x)
 769                 last_x--;
 770         last_y = state->crtc.y + state->crtc.h;
 771         if (last_y)
 772                 last_y--;
 773
 774         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 775                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 776
 777         writel(val, ctx->regs + VIDOSD_B(win));
 778
 779         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 780                         state->crtc.x, state->crtc.y, last_x, last_y);
 781
 782         /* OSD size */
 783         if (win != 3 && win != 4) {
 784                 u32 offset = VIDOSD_D(win);
 785                 if (win == 0)
 786                         offset = VIDOSD_C(win);
 787                 val = state->crtc.w * state->crtc.h;
 788                 writel(val, ctx->regs + offset);
 789
 790                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 791         }
 792
 793         fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w);
 794
 795         /* hardware window 0 doesn't support color key. */
 796         if (win != 0)
 797                 fimd_win_set_colkey(ctx, win);
 798
 799         fimd_enable_video_output(ctx, win, true);
 800
 801         if (ctx->driver_data->has_shadowcon)
 802                 fimd_enable_shadow_channel_path(ctx, win, true);
 803
 804         if (ctx->i80_if)
 805                 atomic_set(&ctx->win_updated, 1);
 806 }
 807
 808 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 809                                struct exynos_drm_plane *plane)
 810 {
 811         struct fimd_context *ctx = crtc->ctx;
 812         unsigned int win = plane->index;
 813
 814         if (ctx->suspended)
 815                 return;
 816
 817         fimd_enable_video_output(ctx, win, false);
 818
 819         if (ctx->driver_data->has_shadowcon)
 820                 fimd_enable_shadow_channel_path(ctx, win, false);
 821 }
 822
 823 static void fimd_enable(struct exynos_drm_crtc *crtc)
 824 {
 825         struct fimd_context *ctx = crtc->ctx;
 826
 827         if (!ctx->suspended)
 828                 return;
 829
 830         ctx->suspended = false;
 831
 832         pm_runtime_get_sync(ctx->dev);
 833
 834         /* if vblank was enabled status, enable it again. */
 835         if (test_and_clear_bit(0, &ctx->irq_flags))
 836                 fimd_enable_vblank(ctx->crtc);
 837
 838         fimd_commit(ctx->crtc);
 839 }
 840
 841 static void fimd_disable(struct exynos_drm_crtc *crtc)
 842 {
 843         struct fimd_context *ctx = crtc->ctx;
 844         int i;
 845
 846         if (ctx->suspended)
 847                 return;
 848
 849         /*
 850          * We need to make sure that all windows are disabled before we
 851          * suspend that connector. Otherwise we might try to scan from
 852          * a destroyed buffer later.
 853          */
 854         for (i = 0; i < WINDOWS_NR; i++)
 855                 fimd_disable_plane(crtc, &ctx->planes[i]);
 856
 857         fimd_enable_vblank(crtc);
 858         fimd_wait_for_vblank(crtc);
 859         fimd_disable_vblank(crtc);
 860
 861         writel(0, ctx->regs + VIDCON0);
 862
 863         pm_runtime_put_sync(ctx->dev);
 864         ctx->suspended = true;
 865 }
 866
 867 static void fimd_trigger(struct device *dev)
 868 {
 869         struct fimd_context *ctx = dev_get_drvdata(dev);
 870         const struct fimd_driver_data *driver_data = ctx->driver_data;
 871         void *timing_base = ctx->regs + driver_data->timing_base;
 872         u32 reg;
 873
 874          /*
 875           * Skips triggering if in triggering state, because multiple triggering
 876           * requests can cause panel reset.
 877           */
 878         if (atomic_read(&ctx->triggering))
 879                 return;
 880
 881         /* Enters triggering mode */
 882         atomic_set(&ctx->triggering, 1);
 883
 884         reg = readl(timing_base + TRIGCON);
 885         reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
 886         writel(reg, timing_base + TRIGCON);
 887
 888         /*
 889          * Exits triggering mode if vblank is not enabled yet, because when the
 890          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 891          */
 892         if (!test_bit(0, &ctx->irq_flags))
 893                 atomic_set(&ctx->triggering, 0);
 894 }
 895
 896 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 897 {
 898         struct fimd_context *ctx = crtc->ctx;
 899         u32 trg_type = ctx->driver_data->trg_type;
 900
 901         /* Checks the crtc is detached already from encoder */
 902         if (ctx->pipe < 0 || !ctx->drm_dev)
 903                 return;
 904
 905         if (trg_type == I80_HW_TRG)
 906                 goto out;
 907
 908         /*
 909          * If there is a page flip request, triggers and handles the page flip
 910          * event so that current fb can be updated into panel GRAM.
 911          */
 912         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 913                 fimd_trigger(ctx->dev);
 914
 915 out:
 916         /* Wakes up vsync event queue */
 917         if (atomic_read(&ctx->wait_vsync_event)) {
 918                 atomic_set(&ctx->wait_vsync_event, 0);
 919                 wake_up(&ctx->wait_vsync_queue);
 920         }
 921
 922         if (test_bit(0, &ctx->irq_flags))
 923                 drm_crtc_handle_vblank(&ctx->crtc->base);
 924 }
 925
 926 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
 927 {
 928         struct fimd_context *ctx = container_of(clk, struct fimd_context,
 929                                                 dp_clk);
 930         u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
 931         writel(val, ctx->regs + DP_MIE_CLKCON);
 932 }
 933
 934 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
 935         .enable = fimd_enable,
 936         .disable = fimd_disable,
 937         .commit = fimd_commit,
 938         .enable_vblank = fimd_enable_vblank,
 939         .disable_vblank = fimd_disable_vblank,
 940         .atomic_begin = fimd_atomic_begin,
 941         .update_plane = fimd_update_plane,
 942         .disable_plane = fimd_disable_plane,
 943         .atomic_flush = fimd_atomic_flush,
 944         .atomic_check = fimd_atomic_check,
 945         .te_handler = fimd_te_handler,
 946 };
 947
 948 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 949 {
 950         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 951         u32 val, clear_bit;
 952
 953         val = readl(ctx->regs + VIDINTCON1);
 954
 955         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
 956         if (val & clear_bit)
 957                 writel(clear_bit, ctx->regs + VIDINTCON1);
 958
 959         /* check the crtc is detached already from encoder */
 960         if (ctx->pipe < 0 || !ctx->drm_dev)
 961                 goto out;
 962
 963         if (!ctx->i80_if)
 964                 drm_crtc_handle_vblank(&ctx->crtc->base);
 965
 966         if (ctx->i80_if) {
 967                 /* Exits triggering mode */
 968                 atomic_set(&ctx->triggering, 0);
 969         } else {
 970                 /* set wait vsync event to zero and wake up queue. */
 971                 if (atomic_read(&ctx->wait_vsync_event)) {
 972                         atomic_set(&ctx->wait_vsync_event, 0);
 973                         wake_up(&ctx->wait_vsync_queue);
 974                 }
 975         }
 976
 977 out:
 978         return IRQ_HANDLED;
 979 }
 980
 981 static int fimd_bind(struct device *dev, struct device *master, void *data)
 982 {
 983         struct fimd_context *ctx = dev_get_drvdata(dev);
 984         struct drm_device *drm_dev = data;
 985         struct exynos_drm_private *priv = drm_dev->dev_private;
 986         struct exynos_drm_plane *exynos_plane;
 987         unsigned int i;
 988         int ret;
 989
 990         ctx->drm_dev = drm_dev;
 991         ctx->pipe = priv->pipe++;
 992
 993         for (i = 0; i < WINDOWS_NR; i++) {
 994                 ctx->configs[i].pixel_formats = fimd_formats;
 995                 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
 996                 ctx->configs[i].zpos = i;
 997                 ctx->configs[i].type = fimd_win_types[i];
 998                 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
 999                                         1 << ctx->pipe, &ctx->configs[i]);
1000                 if (ret)
1001                         return ret;
1002         }
1003
1004         exynos_plane = &ctx->planes[DEFAULT_WIN];
1005         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1006                                            ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
1007                                            &fimd_crtc_ops, ctx);
1008         if (IS_ERR(ctx->crtc))
1009                 return PTR_ERR(ctx->crtc);
1010
1011         if (ctx->driver_data->has_dp_clk) {
1012                 ctx->dp_clk.enable = fimd_dp_clock_enable;
1013                 ctx->crtc->pipe_clk = &ctx->dp_clk;
1014         }
1015
1016         if (ctx->encoder)
1017                 exynos_dpi_bind(drm_dev, ctx->encoder);
1018
1019         if (is_drm_iommu_supported(drm_dev))
1020                 fimd_clear_channels(ctx->crtc);
1021
1022         ret = drm_iommu_attach_device(drm_dev, dev);
1023         if (ret)
1024                 priv->pipe--;
1025
1026         return ret;
1027 }
1028
1029 static void fimd_unbind(struct device *dev, struct device *master,
1030                         void *data)
1031 {
1032         struct fimd_context *ctx = dev_get_drvdata(dev);
1033
1034         fimd_disable(ctx->crtc);
1035
1036         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
1037
1038         if (ctx->encoder)
1039                 exynos_dpi_remove(ctx->encoder);
1040 }
1041
1042 static const struct component_ops fimd_component_ops = {
1043         .bind   = fimd_bind,
1044         .unbind = fimd_unbind,
1045 };
1046
1047 static int fimd_probe(struct platform_device *pdev)
1048 {
1049         struct device *dev = &pdev->dev;
1050         struct fimd_context *ctx;
1051         struct device_node *i80_if_timings;
1052         struct resource *res;
1053         int ret;
1054
1055         if (!dev->of_node)
1056                 return -ENODEV;
1057
1058         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1059         if (!ctx)
1060                 return -ENOMEM;
1061
1062         ctx->dev = dev;
1063         ctx->suspended = true;
1064         ctx->driver_data = of_device_get_match_data(dev);
1065
1066         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1067                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1068         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1069                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1070
1071         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1072         if (i80_if_timings) {
1073                 u32 val;
1074
1075                 ctx->i80_if = true;
1076
1077                 if (ctx->driver_data->has_vidoutcon)
1078                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1079                 else
1080                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1081                 /*
1082                  * The user manual describes that this "DSI_EN" bit is required
1083                  * to enable I80 24-bit data interface.
1084                  */
1085                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1086
1087                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1088                         val = 0;
1089                 ctx->i80ifcon = LCD_CS_SETUP(val);
1090                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1091                         val = 0;
1092                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1093                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1094                         val = 1;
1095                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1096                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1097                         val = 0;
1098                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1099         }
1100         of_node_put(i80_if_timings);
1101
1102         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1103                                                         "samsung,sysreg");
1104         if (IS_ERR(ctx->sysreg)) {
1105                 dev_warn(dev, "failed to get system register.\n");
1106                 ctx->sysreg = NULL;
1107         }
1108
1109         ctx->bus_clk = devm_clk_get(dev, "fimd");
1110         if (IS_ERR(ctx->bus_clk)) {
1111                 dev_err(dev, "failed to get bus clock\n");
1112                 return PTR_ERR(ctx->bus_clk);
1113         }
1114
1115         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1116         if (IS_ERR(ctx->lcd_clk)) {
1117                 dev_err(dev, "failed to get lcd clock\n");
1118                 return PTR_ERR(ctx->lcd_clk);
1119         }
1120
1121         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1122
1123         ctx->regs = devm_ioremap_resource(dev, res);
1124         if (IS_ERR(ctx->regs))
1125                 return PTR_ERR(ctx->regs);
1126
1127         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1128                                            ctx->i80_if ? "lcd_sys" : "vsync");
1129         if (!res) {
1130                 dev_err(dev, "irq request failed.\n");
1131                 return -ENXIO;
1132         }
1133
1134         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1135                                                         0, "drm_fimd", ctx);
1136         if (ret) {
1137                 dev_err(dev, "irq request failed.\n");
1138                 return ret;
1139         }
1140
1141         init_waitqueue_head(&ctx->wait_vsync_queue);
1142         atomic_set(&ctx->wait_vsync_event, 0);
1143
1144         platform_set_drvdata(pdev, ctx);
1145
1146         ctx->encoder = exynos_dpi_probe(dev);
1147         if (IS_ERR(ctx->encoder))
1148                 return PTR_ERR(ctx->encoder);
1149
1150         pm_runtime_enable(dev);
1151
1152         ret = component_add(dev, &fimd_component_ops);
1153         if (ret)
1154                 goto err_disable_pm_runtime;
1155
1156         return ret;
1157
1158 err_disable_pm_runtime:
1159         pm_runtime_disable(dev);
1160
1161         return ret;
1162 }
1163
1164 static int fimd_remove(struct platform_device *pdev)
1165 {
1166         pm_runtime_disable(&pdev->dev);
1167
1168         component_del(&pdev->dev, &fimd_component_ops);
1169
1170         return 0;
1171 }
1172
1173 #ifdef CONFIG_PM
1174 static int exynos_fimd_suspend(struct device *dev)
1175 {
1176         struct fimd_context *ctx = dev_get_drvdata(dev);
1177
1178         clk_disable_unprepare(ctx->lcd_clk);
1179         clk_disable_unprepare(ctx->bus_clk);
1180
1181         return 0;
1182 }
1183
1184 static int exynos_fimd_resume(struct device *dev)
1185 {
1186         struct fimd_context *ctx = dev_get_drvdata(dev);
1187         int ret;
1188
1189         ret = clk_prepare_enable(ctx->bus_clk);
1190         if (ret < 0) {
1191                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1192                 return ret;
1193         }
1194
1195         ret = clk_prepare_enable(ctx->lcd_clk);
1196         if  (ret < 0) {
1197                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1198                 return ret;
1199         }
1200
1201         return 0;
1202 }
1203 #endif
1204
1205 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1206         SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1207 };
1208
1209 struct platform_driver fimd_driver = {
1210         .probe          = fimd_probe,
1211         .remove         = fimd_remove,
1212         .driver         = {
1213                 .name   = "exynos4-fb",
1214                 .owner  = THIS_MODULE,
1215                 .pm     = &exynos_fimd_pm_ops,
1216                 .of_match_table = fimd_driver_dt_match,
1217         },
1218 };