drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22
  23 #include <video/of_display_timing.h>
  24 #include <video/samsung_fimd.h>
  25 #include <drm/exynos_drm.h>
  26
  27 #include "exynos_drm_drv.h"
  28 #include "exynos_drm_fbdev.h"
  29 #include "exynos_drm_crtc.h"
  30 #include "exynos_drm_iommu.h"
  31
  32 /*
  33  * FIMD is stand for Fully Interactive Mobile Display and
  34  * as a display controller, it transfers contents drawn on memory
  35  * to a LCD Panel through Display Interfaces such as RGB or
  36  * CPU Interface.
  37  */
  38
  39 /* position control register for hardware window 0, 2 ~ 4.*/
  40 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  41 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  42 /*
  43  * size control register for hardware windows 0 and alpha control register
  44  * for hardware windows 1 ~ 4
  45  */
  46 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  47 /* size control register for hardware windows 1 ~ 2. */
  48 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  49
  50 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  51 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  52 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  53
  54 /* color key control register for hardware window 1 ~ 4. */
  55 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  56 /* color key value register for hardware window 1 ~ 4. */
  57 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  58
  59 /* FIMD has totally five hardware windows. */
  60 #define WINDOWS_NR      5
  61
  62 #define get_fimd_context(dev)   platform_get_drvdata(to_platform_device(dev))
  63
  64 struct fimd_driver_data {
  65         unsigned int timing_base;
  66
  67         unsigned int has_shadowcon:1;
  68         unsigned int has_clksel:1;
  69 };
  70
  71 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
  72         .timing_base = 0x0,
  73         .has_clksel = 1,
  74 };
  75
  76 static struct fimd_driver_data exynos4_fimd_driver_data = {
  77         .timing_base = 0x0,
  78         .has_shadowcon = 1,
  79 };
  80
  81 static struct fimd_driver_data exynos5_fimd_driver_data = {
  82         .timing_base = 0x20000,
  83         .has_shadowcon = 1,
  84 };
  85
  86 struct fimd_win_data {
  87         unsigned int            offset_x;
  88         unsigned int            offset_y;
  89         unsigned int            ovl_width;
  90         unsigned int            ovl_height;
  91         unsigned int            fb_width;
  92         unsigned int            fb_height;
  93         unsigned int            bpp;
  94         dma_addr_t              dma_addr;
  95         unsigned int            buf_offsize;
  96         unsigned int            line_size;      /* bytes */
  97         bool                    enabled;
  98         bool                    resume;
  99 };
 100
 101 struct fimd_context {
 102         struct exynos_drm_subdrv        subdrv;
 103         int                             irq;
 104         struct drm_crtc                 *crtc;
 105         struct clk                      *bus_clk;
 106         struct clk                      *lcd_clk;
 107         void __iomem                    *regs;
 108         struct fimd_win_data            win_data[WINDOWS_NR];
 109         unsigned int                    clkdiv;
 110         unsigned int                    default_win;
 111         unsigned long                   irq_flags;
 112         u32                             vidcon0;
 113         u32                             vidcon1;
 114         bool                            suspended;
 115         struct mutex                    lock;
 116         wait_queue_head_t               wait_vsync_queue;
 117         atomic_t                        wait_vsync_event;
 118
 119         struct exynos_drm_panel_info *panel;
 120         struct fimd_driver_data *driver_data;
 121 };
 122
 123 #ifdef CONFIG_OF
 124 static const struct of_device_id fimd_driver_dt_match[] = {
 125         { .compatible = "samsung,s3c6400-fimd",
 126           .data = &s3c64xx_fimd_driver_data },
 127         { .compatible = "samsung,exynos4210-fimd",
 128           .data = &exynos4_fimd_driver_data },
 129         { .compatible = "samsung,exynos5250-fimd",
 130           .data = &exynos5_fimd_driver_data },
 131         {},
 132 };
 133 #endif
 134
 135 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
 136         struct platform_device *pdev)
 137 {
 138 #ifdef CONFIG_OF
 139         const struct of_device_id *of_id =
 140                         of_match_device(fimd_driver_dt_match, &pdev->dev);
 141
 142         if (of_id)
 143                 return (struct fimd_driver_data *)of_id->data;
 144 #endif
 145
 146         return (struct fimd_driver_data *)
 147                 platform_get_device_id(pdev)->driver_data;
 148 }
 149
 150 static bool fimd_display_is_connected(struct device *dev)
 151 {
 152         /* TODO. */
 153
 154         return true;
 155 }
 156
 157 static void *fimd_get_panel(struct device *dev)
 158 {
 159         struct fimd_context *ctx = get_fimd_context(dev);
 160
 161         return ctx->panel;
 162 }
 163
 164 static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode)
 165 {
 166         /* TODO. */
 167
 168         return 0;
 169 }
 170
 171 static int fimd_display_power_on(struct device *dev, int mode)
 172 {
 173         /* TODO */
 174
 175         return 0;
 176 }
 177
 178 static struct exynos_drm_display_ops fimd_display_ops = {
 179         .type = EXYNOS_DISPLAY_TYPE_LCD,
 180         .is_connected = fimd_display_is_connected,
 181         .get_panel = fimd_get_panel,
 182         .check_mode = fimd_check_mode,
 183         .power_on = fimd_display_power_on,
 184 };
 185
 186 static void fimd_dpms(struct device *subdrv_dev, int mode)
 187 {
 188         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 189
 190         DRM_DEBUG_KMS("%d\n", mode);
 191
 192         mutex_lock(&ctx->lock);
 193
 194         switch (mode) {
 195         case DRM_MODE_DPMS_ON:
 196                 /*
 197                  * enable fimd hardware only if suspended status.
 198                  *
 199                  * P.S. fimd_dpms function would be called at booting time so
 200                  * clk_enable could be called double time.
 201                  */
 202                 if (ctx->suspended)
 203                         pm_runtime_get_sync(subdrv_dev);
 204                 break;
 205         case DRM_MODE_DPMS_STANDBY:
 206         case DRM_MODE_DPMS_SUSPEND:
 207         case DRM_MODE_DPMS_OFF:
 208                 if (!ctx->suspended)
 209                         pm_runtime_put_sync(subdrv_dev);
 210                 break;
 211         default:
 212                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 213                 break;
 214         }
 215
 216         mutex_unlock(&ctx->lock);
 217 }
 218
 219 static void fimd_apply(struct device *subdrv_dev)
 220 {
 221         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 222         struct exynos_drm_manager *mgr = ctx->subdrv.manager;
 223         struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
 224         struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
 225         struct fimd_win_data *win_data;
 226         int i;
 227
 228         for (i = 0; i < WINDOWS_NR; i++) {
 229                 win_data = &ctx->win_data[i];
 230                 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
 231                         ovl_ops->commit(subdrv_dev, i);
 232         }
 233
 234         if (mgr_ops && mgr_ops->commit)
 235                 mgr_ops->commit(subdrv_dev);
 236 }
 237
 238 static void fimd_commit(struct device *dev)
 239 {
 240         struct fimd_context *ctx = get_fimd_context(dev);
 241         struct exynos_drm_panel_info *panel = ctx->panel;
 242         struct fb_videomode *timing = &panel->timing;
 243         struct fimd_driver_data *driver_data;
 244         u32 val;
 245
 246         driver_data = ctx->driver_data;
 247         if (ctx->suspended)
 248                 return;
 249
 250         /* setup polarity values from machine code. */
 251         writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 252
 253         /* setup vertical timing values. */
 254         val = VIDTCON0_VBPD(timing->upper_margin - 1) |
 255                VIDTCON0_VFPD(timing->lower_margin - 1) |
 256                VIDTCON0_VSPW(timing->vsync_len - 1);
 257         writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 258
 259         /* setup horizontal timing values.  */
 260         val = VIDTCON1_HBPD(timing->left_margin - 1) |
 261                VIDTCON1_HFPD(timing->right_margin - 1) |
 262                VIDTCON1_HSPW(timing->hsync_len - 1);
 263         writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 264
 265         /* setup horizontal and vertical display size. */
 266         val = VIDTCON2_LINEVAL(timing->yres - 1) |
 267                VIDTCON2_HOZVAL(timing->xres - 1) |
 268                VIDTCON2_LINEVAL_E(timing->yres - 1) |
 269                VIDTCON2_HOZVAL_E(timing->xres - 1);
 270         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 271
 272         /* setup clock source, clock divider, enable dma. */
 273         val = ctx->vidcon0;
 274         val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
 275
 276         if (ctx->driver_data->has_clksel) {
 277                 val &= ~VIDCON0_CLKSEL_MASK;
 278                 val |= VIDCON0_CLKSEL_LCD;
 279         }
 280
 281         if (ctx->clkdiv > 1)
 282                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 283         else
 284                 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
 285
 286         /*
 287          * fields of register with prefix '_F' would be updated
 288          * at vsync(same as dma start)
 289          */
 290         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 291         writel(val, ctx->regs + VIDCON0);
 292 }
 293
 294 static int fimd_enable_vblank(struct device *dev)
 295 {
 296         struct fimd_context *ctx = get_fimd_context(dev);
 297         u32 val;
 298
 299         if (ctx->suspended)
 300                 return -EPERM;
 301
 302         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 303                 val = readl(ctx->regs + VIDINTCON0);
 304
 305                 val |= VIDINTCON0_INT_ENABLE;
 306                 val |= VIDINTCON0_INT_FRAME;
 307
 308                 val &= ~VIDINTCON0_FRAMESEL0_MASK;
 309                 val |= VIDINTCON0_FRAMESEL0_VSYNC;
 310                 val &= ~VIDINTCON0_FRAMESEL1_MASK;
 311                 val |= VIDINTCON0_FRAMESEL1_NONE;
 312
 313                 writel(val, ctx->regs + VIDINTCON0);
 314         }
 315
 316         return 0;
 317 }
 318
 319 static void fimd_disable_vblank(struct device *dev)
 320 {
 321         struct fimd_context *ctx = get_fimd_context(dev);
 322         u32 val;
 323
 324         if (ctx->suspended)
 325                 return;
 326
 327         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 328                 val = readl(ctx->regs + VIDINTCON0);
 329
 330                 val &= ~VIDINTCON0_INT_FRAME;
 331                 val &= ~VIDINTCON0_INT_ENABLE;
 332
 333                 writel(val, ctx->regs + VIDINTCON0);
 334         }
 335 }
 336
 337 static void fimd_wait_for_vblank(struct device *dev)
 338 {
 339         struct fimd_context *ctx = get_fimd_context(dev);
 340
 341         if (ctx->suspended)
 342                 return;
 343
 344         atomic_set(&ctx->wait_vsync_event, 1);
 345
 346         /*
 347          * wait for FIMD to signal VSYNC interrupt or return after
 348          * timeout which is set to 50ms (refresh rate of 20).
 349          */
 350         if (!wait_event_timeout(ctx->wait_vsync_queue,
 351                                 !atomic_read(&ctx->wait_vsync_event),
 352                                 DRM_HZ/20))
 353                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 354 }
 355
 356 static struct exynos_drm_manager_ops fimd_manager_ops = {
 357         .dpms = fimd_dpms,
 358         .apply = fimd_apply,
 359         .commit = fimd_commit,
 360         .enable_vblank = fimd_enable_vblank,
 361         .disable_vblank = fimd_disable_vblank,
 362         .wait_for_vblank = fimd_wait_for_vblank,
 363 };
 364
 365 static void fimd_win_mode_set(struct device *dev,
 366                               struct exynos_drm_overlay *overlay)
 367 {
 368         struct fimd_context *ctx = get_fimd_context(dev);
 369         struct fimd_win_data *win_data;
 370         int win;
 371         unsigned long offset;
 372
 373         if (!overlay) {
 374                 dev_err(dev, "overlay is NULL\n");
 375                 return;
 376         }
 377
 378         win = overlay->zpos;
 379         if (win == DEFAULT_ZPOS)
 380                 win = ctx->default_win;
 381
 382         if (win < 0 || win >= WINDOWS_NR)
 383                 return;
 384
 385         offset = overlay->fb_x * (overlay->bpp >> 3);
 386         offset += overlay->fb_y * overlay->pitch;
 387
 388         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
 389
 390         win_data = &ctx->win_data[win];
 391
 392         win_data->offset_x = overlay->crtc_x;
 393         win_data->offset_y = overlay->crtc_y;
 394         win_data->ovl_width = overlay->crtc_width;
 395         win_data->ovl_height = overlay->crtc_height;
 396         win_data->fb_width = overlay->fb_width;
 397         win_data->fb_height = overlay->fb_height;
 398         win_data->dma_addr = overlay->dma_addr[0] + offset;
 399         win_data->bpp = overlay->bpp;
 400         win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
 401                                 (overlay->bpp >> 3);
 402         win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
 403
 404         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 405                         win_data->offset_x, win_data->offset_y);
 406         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 407                         win_data->ovl_width, win_data->ovl_height);
 408         DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
 409         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 410                         overlay->fb_width, overlay->crtc_width);
 411 }
 412
 413 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
 414 {
 415         struct fimd_context *ctx = get_fimd_context(dev);
 416         struct fimd_win_data *win_data = &ctx->win_data[win];
 417         unsigned long val;
 418
 419         val = WINCONx_ENWIN;
 420
 421         switch (win_data->bpp) {
 422         case 1:
 423                 val |= WINCON0_BPPMODE_1BPP;
 424                 val |= WINCONx_BITSWP;
 425                 val |= WINCONx_BURSTLEN_4WORD;
 426                 break;
 427         case 2:
 428                 val |= WINCON0_BPPMODE_2BPP;
 429                 val |= WINCONx_BITSWP;
 430                 val |= WINCONx_BURSTLEN_8WORD;
 431                 break;
 432         case 4:
 433                 val |= WINCON0_BPPMODE_4BPP;
 434                 val |= WINCONx_BITSWP;
 435                 val |= WINCONx_BURSTLEN_8WORD;
 436                 break;
 437         case 8:
 438                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 439                 val |= WINCONx_BURSTLEN_8WORD;
 440                 val |= WINCONx_BYTSWP;
 441                 break;
 442         case 16:
 443                 val |= WINCON0_BPPMODE_16BPP_565;
 444                 val |= WINCONx_HAWSWP;
 445                 val |= WINCONx_BURSTLEN_16WORD;
 446                 break;
 447         case 24:
 448                 val |= WINCON0_BPPMODE_24BPP_888;
 449                 val |= WINCONx_WSWP;
 450                 val |= WINCONx_BURSTLEN_16WORD;
 451                 break;
 452         case 32:
 453                 val |= WINCON1_BPPMODE_28BPP_A4888
 454                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 455                 val |= WINCONx_WSWP;
 456                 val |= WINCONx_BURSTLEN_16WORD;
 457                 break;
 458         default:
 459                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 460
 461                 val |= WINCON0_BPPMODE_24BPP_888;
 462                 val |= WINCONx_WSWP;
 463                 val |= WINCONx_BURSTLEN_16WORD;
 464                 break;
 465         }
 466
 467         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 468
 469         writel(val, ctx->regs + WINCON(win));
 470 }
 471
 472 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
 473 {
 474         struct fimd_context *ctx = get_fimd_context(dev);
 475         unsigned int keycon0 = 0, keycon1 = 0;
 476
 477         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 478                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 479
 480         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 481
 482         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 483         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 484 }
 485
 486 /**
 487  * shadow_protect_win() - disable updating values from shadow registers at vsync
 488  *
 489  * @win: window to protect registers for
 490  * @protect: 1 to protect (disable updates)
 491  */
 492 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 493                                                         int win, bool protect)
 494 {
 495         u32 reg, bits, val;
 496
 497         if (ctx->driver_data->has_shadowcon) {
 498                 reg = SHADOWCON;
 499                 bits = SHADOWCON_WINx_PROTECT(win);
 500         } else {
 501                 reg = PRTCON;
 502                 bits = PRTCON_PROTECT;
 503         }
 504
 505         val = readl(ctx->regs + reg);
 506         if (protect)
 507                 val |= bits;
 508         else
 509                 val &= ~bits;
 510         writel(val, ctx->regs + reg);
 511 }
 512
 513 static void fimd_win_commit(struct device *dev, int zpos)
 514 {
 515         struct fimd_context *ctx = get_fimd_context(dev);
 516         struct fimd_win_data *win_data;
 517         int win = zpos;
 518         unsigned long val, alpha, size;
 519         unsigned int last_x;
 520         unsigned int last_y;
 521
 522         if (ctx->suspended)
 523                 return;
 524
 525         if (win == DEFAULT_ZPOS)
 526                 win = ctx->default_win;
 527
 528         if (win < 0 || win >= WINDOWS_NR)
 529                 return;
 530
 531         win_data = &ctx->win_data[win];
 532
 533         /*
 534          * SHADOWCON/PRTCON register is used for enabling timing.
 535          *
 536          * for example, once only width value of a register is set,
 537          * if the dma is started then fimd hardware could malfunction so
 538          * with protect window setting, the register fields with prefix '_F'
 539          * wouldn't be updated at vsync also but updated once unprotect window
 540          * is set.
 541          */
 542
 543         /* protect windows */
 544         fimd_shadow_protect_win(ctx, win, true);
 545
 546         /* buffer start address */
 547         val = (unsigned long)win_data->dma_addr;
 548         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 549
 550         /* buffer end address */
 551         size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
 552         val = (unsigned long)(win_data->dma_addr + size);
 553         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 554
 555         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 556                         (unsigned long)win_data->dma_addr, val, size);
 557         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 558                         win_data->ovl_width, win_data->ovl_height);
 559
 560         /* buffer size */
 561         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 562                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
 563                 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
 564                 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
 565         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 566
 567         /* OSD position */
 568         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 569                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
 570                 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
 571                 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
 572         writel(val, ctx->regs + VIDOSD_A(win));
 573
 574         last_x = win_data->offset_x + win_data->ovl_width;
 575         if (last_x)
 576                 last_x--;
 577         last_y = win_data->offset_y + win_data->ovl_height;
 578         if (last_y)
 579                 last_y--;
 580
 581         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 582                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 583
 584         writel(val, ctx->regs + VIDOSD_B(win));
 585
 586         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 587                         win_data->offset_x, win_data->offset_y, last_x, last_y);
 588
 589         /* hardware window 0 doesn't support alpha channel. */
 590         if (win != 0) {
 591                 /* OSD alpha */
 592                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 593                         VIDISD14C_ALPHA1_G(0xf) |
 594                         VIDISD14C_ALPHA1_B(0xf);
 595
 596                 writel(alpha, ctx->regs + VIDOSD_C(win));
 597         }
 598
 599         /* OSD size */
 600         if (win != 3 && win != 4) {
 601                 u32 offset = VIDOSD_D(win);
 602                 if (win == 0)
 603                         offset = VIDOSD_C(win);
 604                 val = win_data->ovl_width * win_data->ovl_height;
 605                 writel(val, ctx->regs + offset);
 606
 607                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 608         }
 609
 610         fimd_win_set_pixfmt(dev, win);
 611
 612         /* hardware window 0 doesn't support color key. */
 613         if (win != 0)
 614                 fimd_win_set_colkey(dev, win);
 615
 616         /* wincon */
 617         val = readl(ctx->regs + WINCON(win));
 618         val |= WINCONx_ENWIN;
 619         writel(val, ctx->regs + WINCON(win));
 620
 621         /* Enable DMA channel and unprotect windows */
 622         fimd_shadow_protect_win(ctx, win, false);
 623
 624         if (ctx->driver_data->has_shadowcon) {
 625                 val = readl(ctx->regs + SHADOWCON);
 626                 val |= SHADOWCON_CHx_ENABLE(win);
 627                 writel(val, ctx->regs + SHADOWCON);
 628         }
 629
 630         win_data->enabled = true;
 631 }
 632
 633 static void fimd_win_disable(struct device *dev, int zpos)
 634 {
 635         struct fimd_context *ctx = get_fimd_context(dev);
 636         struct fimd_win_data *win_data;
 637         int win = zpos;
 638         u32 val;
 639
 640         if (win == DEFAULT_ZPOS)
 641                 win = ctx->default_win;
 642
 643         if (win < 0 || win >= WINDOWS_NR)
 644                 return;
 645
 646         win_data = &ctx->win_data[win];
 647
 648         if (ctx->suspended) {
 649                 /* do not resume this window*/
 650                 win_data->resume = false;
 651                 return;
 652         }
 653
 654         /* protect windows */
 655         fimd_shadow_protect_win(ctx, win, true);
 656
 657         /* wincon */
 658         val = readl(ctx->regs + WINCON(win));
 659         val &= ~WINCONx_ENWIN;
 660         writel(val, ctx->regs + WINCON(win));
 661
 662         /* unprotect windows */
 663         if (ctx->driver_data->has_shadowcon) {
 664                 val = readl(ctx->regs + SHADOWCON);
 665                 val &= ~SHADOWCON_CHx_ENABLE(win);
 666                 writel(val, ctx->regs + SHADOWCON);
 667         }
 668
 669         fimd_shadow_protect_win(ctx, win, false);
 670
 671         win_data->enabled = false;
 672 }
 673
 674 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
 675         .mode_set = fimd_win_mode_set,
 676         .commit = fimd_win_commit,
 677         .disable = fimd_win_disable,
 678 };
 679
 680 static struct exynos_drm_manager fimd_manager = {
 681         .pipe           = -1,
 682         .ops            = &fimd_manager_ops,
 683         .overlay_ops    = &fimd_overlay_ops,
 684         .display_ops    = &fimd_display_ops,
 685 };
 686
 687 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 688 {
 689         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 690         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 691         struct drm_device *drm_dev = subdrv->drm_dev;
 692         struct exynos_drm_manager *manager = subdrv->manager;
 693         u32 val;
 694
 695         val = readl(ctx->regs + VIDINTCON1);
 696
 697         if (val & VIDINTCON1_INT_FRAME)
 698                 /* VSYNC interrupt */
 699                 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
 700
 701         /* check the crtc is detached already from encoder */
 702         if (manager->pipe < 0)
 703                 goto out;
 704
 705         drm_handle_vblank(drm_dev, manager->pipe);
 706         exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe);
 707
 708         /* set wait vsync event to zero and wake up queue. */
 709         if (atomic_read(&ctx->wait_vsync_event)) {
 710                 atomic_set(&ctx->wait_vsync_event, 0);
 711                 DRM_WAKEUP(&ctx->wait_vsync_queue);
 712         }
 713 out:
 714         return IRQ_HANDLED;
 715 }
 716
 717 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 718 {
 719         /*
 720          * enable drm irq mode.
 721          * - with irq_enabled = 1, we can use the vblank feature.
 722          *
 723          * P.S. note that we wouldn't use drm irq handler but
 724          *      just specific driver own one instead because
 725          *      drm framework supports only one irq handler.
 726          */
 727         drm_dev->irq_enabled = 1;
 728
 729         /*
 730          * with vblank_disable_allowed = 1, vblank interrupt will be disabled
 731          * by drm timer once a current process gives up ownership of
 732          * vblank event.(after drm_vblank_put function is called)
 733          */
 734         drm_dev->vblank_disable_allowed = 1;
 735
 736         /* attach this sub driver to iommu mapping if supported. */
 737         if (is_drm_iommu_supported(drm_dev))
 738                 drm_iommu_attach_device(drm_dev, dev);
 739
 740         return 0;
 741 }
 742
 743 static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
 744 {
 745         /* detach this sub driver from iommu mapping if supported. */
 746         if (is_drm_iommu_supported(drm_dev))
 747                 drm_iommu_detach_device(drm_dev, dev);
 748 }
 749
 750 static int fimd_calc_clkdiv(struct fimd_context *ctx,
 751                             struct fb_videomode *timing)
 752 {
 753         unsigned long clk = clk_get_rate(ctx->lcd_clk);
 754         u32 retrace;
 755         u32 clkdiv;
 756         u32 best_framerate = 0;
 757         u32 framerate;
 758
 759         retrace = timing->left_margin + timing->hsync_len +
 760                                 timing->right_margin + timing->xres;
 761         retrace *= timing->upper_margin + timing->vsync_len +
 762                                 timing->lower_margin + timing->yres;
 763
 764         /* default framerate is 60Hz */
 765         if (!timing->refresh)
 766                 timing->refresh = 60;
 767
 768         clk /= retrace;
 769
 770         for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
 771                 int tmp;
 772
 773                 /* get best framerate */
 774                 framerate = clk / clkdiv;
 775                 tmp = timing->refresh - framerate;
 776                 if (tmp < 0) {
 777                         best_framerate = framerate;
 778                         continue;
 779                 } else {
 780                         if (!best_framerate)
 781                                 best_framerate = framerate;
 782                         else if (tmp < (best_framerate - framerate))
 783                                 best_framerate = framerate;
 784                         break;
 785                 }
 786         }
 787
 788         return clkdiv;
 789 }
 790
 791 static void fimd_clear_win(struct fimd_context *ctx, int win)
 792 {
 793         writel(0, ctx->regs + WINCON(win));
 794         writel(0, ctx->regs + VIDOSD_A(win));
 795         writel(0, ctx->regs + VIDOSD_B(win));
 796         writel(0, ctx->regs + VIDOSD_C(win));
 797
 798         if (win == 1 || win == 2)
 799                 writel(0, ctx->regs + VIDOSD_D(win));
 800
 801         fimd_shadow_protect_win(ctx, win, false);
 802 }
 803
 804 static int fimd_clock(struct fimd_context *ctx, bool enable)
 805 {
 806         if (enable) {
 807                 int ret;
 808
 809                 ret = clk_prepare_enable(ctx->bus_clk);
 810                 if (ret < 0)
 811                         return ret;
 812
 813                 ret = clk_prepare_enable(ctx->lcd_clk);
 814                 if  (ret < 0) {
 815                         clk_disable_unprepare(ctx->bus_clk);
 816                         return ret;
 817                 }
 818         } else {
 819                 clk_disable_unprepare(ctx->lcd_clk);
 820                 clk_disable_unprepare(ctx->bus_clk);
 821         }
 822
 823         return 0;
 824 }
 825
 826 static void fimd_window_suspend(struct device *dev)
 827 {
 828         struct fimd_context *ctx = get_fimd_context(dev);
 829         struct fimd_win_data *win_data;
 830         int i;
 831
 832         for (i = 0; i < WINDOWS_NR; i++) {
 833                 win_data = &ctx->win_data[i];
 834                 win_data->resume = win_data->enabled;
 835                 fimd_win_disable(dev, i);
 836         }
 837         fimd_wait_for_vblank(dev);
 838 }
 839
 840 static void fimd_window_resume(struct device *dev)
 841 {
 842         struct fimd_context *ctx = get_fimd_context(dev);
 843         struct fimd_win_data *win_data;
 844         int i;
 845
 846         for (i = 0; i < WINDOWS_NR; i++) {
 847                 win_data = &ctx->win_data[i];
 848                 win_data->enabled = win_data->resume;
 849                 win_data->resume = false;
 850         }
 851 }
 852
 853 static int fimd_activate(struct fimd_context *ctx, bool enable)
 854 {
 855         struct device *dev = ctx->subdrv.dev;
 856         if (enable) {
 857                 int ret;
 858
 859                 ret = fimd_clock(ctx, true);
 860                 if (ret < 0)
 861                         return ret;
 862
 863                 ctx->suspended = false;
 864
 865                 /* if vblank was enabled status, enable it again. */
 866                 if (test_and_clear_bit(0, &ctx->irq_flags))
 867                         fimd_enable_vblank(dev);
 868
 869                 fimd_window_resume(dev);
 870         } else {
 871                 fimd_window_suspend(dev);
 872
 873                 fimd_clock(ctx, false);
 874                 ctx->suspended = true;
 875         }
 876
 877         return 0;
 878 }
 879
 880 static int fimd_probe(struct platform_device *pdev)
 881 {
 882         struct device *dev = &pdev->dev;
 883         struct fimd_context *ctx;
 884         struct exynos_drm_subdrv *subdrv;
 885         struct exynos_drm_fimd_pdata *pdata;
 886         struct exynos_drm_panel_info *panel;
 887         struct resource *res;
 888         int win;
 889         int ret = -EINVAL;
 890
 891         if (dev->of_node) {
 892                 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 893                 if (!pdata) {
 894                         DRM_ERROR("memory allocation for pdata failed\n");
 895                         return -ENOMEM;
 896                 }
 897
 898                 ret = of_get_fb_videomode(dev->of_node, &pdata->panel.timing,
 899                                         OF_USE_NATIVE_MODE);
 900                 if (ret) {
 901                         DRM_ERROR("failed: of_get_fb_videomode() : %d\n", ret);
 902                         return ret;
 903                 }
 904         } else {
 905                 pdata = dev->platform_data;
 906                 if (!pdata) {
 907                         DRM_ERROR("no platform data specified\n");
 908                         return -EINVAL;
 909                 }
 910         }
 911
 912         panel = &pdata->panel;
 913         if (!panel) {
 914                 dev_err(dev, "panel is null.\n");
 915                 return -EINVAL;
 916         }
 917
 918         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 919         if (!ctx)
 920                 return -ENOMEM;
 921
 922         ctx->bus_clk = devm_clk_get(dev, "fimd");
 923         if (IS_ERR(ctx->bus_clk)) {
 924                 dev_err(dev, "failed to get bus clock\n");
 925                 return PTR_ERR(ctx->bus_clk);
 926         }
 927
 928         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
 929         if (IS_ERR(ctx->lcd_clk)) {
 930                 dev_err(dev, "failed to get lcd clock\n");
 931                 return PTR_ERR(ctx->lcd_clk);
 932         }
 933
 934         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 935
 936         ctx->regs = devm_ioremap_resource(dev, res);
 937         if (IS_ERR(ctx->regs))
 938                 return PTR_ERR(ctx->regs);
 939
 940         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
 941         if (!res) {
 942                 dev_err(dev, "irq request failed.\n");
 943                 return -ENXIO;
 944         }
 945
 946         ctx->irq = res->start;
 947
 948         ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler,
 949                                                         0, "drm_fimd", ctx);
 950         if (ret) {
 951                 dev_err(dev, "irq request failed.\n");
 952                 return ret;
 953         }
 954
 955         ctx->driver_data = drm_fimd_get_driver_data(pdev);
 956         ctx->vidcon0 = pdata->vidcon0;
 957         ctx->vidcon1 = pdata->vidcon1;
 958         ctx->default_win = pdata->default_win;
 959         ctx->panel = panel;
 960         DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
 961         atomic_set(&ctx->wait_vsync_event, 0);
 962
 963         subdrv = &ctx->subdrv;
 964
 965         subdrv->dev = dev;
 966         subdrv->manager = &fimd_manager;
 967         subdrv->probe = fimd_subdrv_probe;
 968         subdrv->remove = fimd_subdrv_remove;
 969
 970         mutex_init(&ctx->lock);
 971
 972         platform_set_drvdata(pdev, ctx);
 973
 974         pm_runtime_enable(dev);
 975         pm_runtime_get_sync(dev);
 976
 977         ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
 978         panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
 979
 980         DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
 981                         panel->timing.pixclock, ctx->clkdiv);
 982
 983         for (win = 0; win < WINDOWS_NR; win++)
 984                 fimd_clear_win(ctx, win);
 985
 986         exynos_drm_subdrv_register(subdrv);
 987
 988         return 0;
 989 }
 990
 991 static int fimd_remove(struct platform_device *pdev)
 992 {
 993         struct device *dev = &pdev->dev;
 994         struct fimd_context *ctx = platform_get_drvdata(pdev);
 995
 996         exynos_drm_subdrv_unregister(&ctx->subdrv);
 997
 998         if (ctx->suspended)
 999                 goto out;
1000
1001         pm_runtime_set_suspended(dev);
1002         pm_runtime_put_sync(dev);
1003
1004 out:
1005         pm_runtime_disable(dev);
1006
1007         return 0;
1008 }
1009
1010 #ifdef CONFIG_PM_SLEEP
1011 static int fimd_suspend(struct device *dev)
1012 {
1013         struct fimd_context *ctx = get_fimd_context(dev);
1014
1015         /*
1016          * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
1017          * called here, an error would be returned by that interface
1018          * because the usage_count of pm runtime is more than 1.
1019          */
1020         if (!pm_runtime_suspended(dev))
1021                 return fimd_activate(ctx, false);
1022
1023         return 0;
1024 }
1025
1026 static int fimd_resume(struct device *dev)
1027 {
1028         struct fimd_context *ctx = get_fimd_context(dev);
1029
1030         /*
1031          * if entered to sleep when lcd panel was on, the usage_count
1032          * of pm runtime would still be 1 so in this case, fimd driver
1033          * should be on directly not drawing on pm runtime interface.
1034          */
1035         if (!pm_runtime_suspended(dev)) {
1036                 int ret;
1037
1038                 ret = fimd_activate(ctx, true);
1039                 if (ret < 0)
1040                         return ret;
1041
1042                 /*
1043                  * in case of dpms on(standby), fimd_apply function will
1044                  * be called by encoder's dpms callback to update fimd's
1045                  * registers but in case of sleep wakeup, it's not.
1046                  * so fimd_apply function should be called at here.
1047                  */
1048                 fimd_apply(dev);
1049         }
1050
1051         return 0;
1052 }
1053 #endif
1054
1055 #ifdef CONFIG_PM_RUNTIME
1056 static int fimd_runtime_suspend(struct device *dev)
1057 {
1058         struct fimd_context *ctx = get_fimd_context(dev);
1059
1060         return fimd_activate(ctx, false);
1061 }
1062
1063 static int fimd_runtime_resume(struct device *dev)
1064 {
1065         struct fimd_context *ctx = get_fimd_context(dev);
1066
1067         return fimd_activate(ctx, true);
1068 }
1069 #endif
1070
1071 static struct platform_device_id fimd_driver_ids[] = {
1072         {
1073                 .name           = "s3c64xx-fb",
1074                 .driver_data    = (unsigned long)&s3c64xx_fimd_driver_data,
1075         }, {
1076                 .name           = "exynos4-fb",
1077                 .driver_data    = (unsigned long)&exynos4_fimd_driver_data,
1078         }, {
1079                 .name           = "exynos5-fb",
1080                 .driver_data    = (unsigned long)&exynos5_fimd_driver_data,
1081         },
1082         {},
1083 };
1084
1085 static const struct dev_pm_ops fimd_pm_ops = {
1086         SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1087         SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1088 };
1089
1090 struct platform_driver fimd_driver = {
1091         .probe          = fimd_probe,
1092         .remove         = fimd_remove,
1093         .id_table       = fimd_driver_ids,
1094         .driver         = {
1095                 .name   = "exynos4-fb",
1096                 .owner  = THIS_MODULE,
1097                 .pm     = &fimd_pm_ops,
1098                 .of_match_table = of_match_ptr(fimd_driver_dt_match),
1099         },
1100 };