drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include "drmP.h"
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <drm/exynos_drm.h>
  23 #include <plat/regs-fb-v4.h>
  24
  25 #include "exynos_drm_drv.h"
  26 #include "exynos_drm_fbdev.h"
  27 #include "exynos_drm_crtc.h"
  28
  29 /*
  30  * FIMD is stand for Fully Interactive Mobile Display and
  31  * as a display controller, it transfers contents drawn on memory
  32  * to a LCD Panel through Display Interfaces such as RGB or
  33  * CPU Interface.
  34  */
  35
  36 /* position control register for hardware window 0, 2 ~ 4.*/
  37 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  38 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  39 /* size control register for hardware window 0. */
  40 #define VIDOSD_C_SIZE_W0        (VIDOSD_BASE + 0x08)
  41 /* alpha control register for hardware window 1 ~ 4. */
  42 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x18 + (win) * 16)
  43 /* size control register for hardware window 1 ~ 4. */
  44 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  45
  46 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  47 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  48 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  49
  50 /* color key control register for hardware window 1 ~ 4. */
  51 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + (x * 8))
  52 /* color key value register for hardware window 1 ~ 4. */
  53 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + (x * 8))
  54
  55 /* FIMD has totally five hardware windows. */
  56 #define WINDOWS_NR      5
  57
  58 #define get_fimd_context(dev)   platform_get_drvdata(to_platform_device(dev))
  59
  60 struct fimd_win_data {
  61         unsigned int            offset_x;
  62         unsigned int            offset_y;
  63         unsigned int            ovl_width;
  64         unsigned int            ovl_height;
  65         unsigned int            fb_width;
  66         unsigned int            fb_height;
  67         unsigned int            bpp;
  68         dma_addr_t              dma_addr;
  69         void __iomem            *vaddr;
  70         unsigned int            buf_offsize;
  71         unsigned int            line_size;      /* bytes */
  72         bool                    enabled;
  73 };
  74
  75 struct fimd_context {
  76         struct exynos_drm_subdrv        subdrv;
  77         int                             irq;
  78         struct drm_crtc                 *crtc;
  79         struct clk                      *bus_clk;
  80         struct clk                      *lcd_clk;
  81         struct resource                 *regs_res;
  82         void __iomem                    *regs;
  83         struct fimd_win_data            win_data[WINDOWS_NR];
  84         unsigned int                    clkdiv;
  85         unsigned int                    default_win;
  86         unsigned long                   irq_flags;
  87         u32                             vidcon0;
  88         u32                             vidcon1;
  89         bool                            suspended;
  90
  91         struct fb_videomode             *timing;
  92 };
  93
  94 static bool fimd_display_is_connected(struct device *dev)
  95 {
  96         DRM_DEBUG_KMS("%s\n", __FILE__);
  97
  98         /* TODO. */
  99
 100         return true;
 101 }
 102
 103 static void *fimd_get_timing(struct device *dev)
 104 {
 105         struct fimd_context *ctx = get_fimd_context(dev);
 106
 107         DRM_DEBUG_KMS("%s\n", __FILE__);
 108
 109         return ctx->timing;
 110 }
 111
 112 static int fimd_check_timing(struct device *dev, void *timing)
 113 {
 114         DRM_DEBUG_KMS("%s\n", __FILE__);
 115
 116         /* TODO. */
 117
 118         return 0;
 119 }
 120
 121 static int fimd_display_power_on(struct device *dev, int mode)
 122 {
 123         DRM_DEBUG_KMS("%s\n", __FILE__);
 124
 125         /* TODO */
 126
 127         return 0;
 128 }
 129
 130 static struct exynos_drm_display_ops fimd_display_ops = {
 131         .type = EXYNOS_DISPLAY_TYPE_LCD,
 132         .is_connected = fimd_display_is_connected,
 133         .get_timing = fimd_get_timing,
 134         .check_timing = fimd_check_timing,
 135         .power_on = fimd_display_power_on,
 136 };
 137
 138 static void fimd_dpms(struct device *subdrv_dev, int mode)
 139 {
 140         DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
 141
 142         switch (mode) {
 143         case DRM_MODE_DPMS_ON:
 144                 pm_runtime_get_sync(subdrv_dev);
 145                 break;
 146         case DRM_MODE_DPMS_STANDBY:
 147         case DRM_MODE_DPMS_SUSPEND:
 148         case DRM_MODE_DPMS_OFF:
 149                 pm_runtime_put_sync(subdrv_dev);
 150                 break;
 151         default:
 152                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 153                 break;
 154         }
 155 }
 156
 157 static void fimd_apply(struct device *subdrv_dev)
 158 {
 159         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 160         struct exynos_drm_manager *mgr = &ctx->subdrv.manager;
 161         struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
 162         struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
 163         struct fimd_win_data *win_data;
 164
 165         DRM_DEBUG_KMS("%s\n", __FILE__);
 166
 167         win_data = &ctx->win_data[ctx->default_win];
 168         if (win_data->enabled && (ovl_ops && ovl_ops->commit))
 169                 ovl_ops->commit(subdrv_dev);
 170
 171         if (mgr_ops && mgr_ops->commit)
 172                 mgr_ops->commit(subdrv_dev);
 173 }
 174
 175 static void fimd_commit(struct device *dev)
 176 {
 177         struct fimd_context *ctx = get_fimd_context(dev);
 178         struct fb_videomode *timing = ctx->timing;
 179         u32 val;
 180
 181         DRM_DEBUG_KMS("%s\n", __FILE__);
 182
 183         /* setup polarity values from machine code. */
 184         writel(ctx->vidcon1, ctx->regs + VIDCON1);
 185
 186         /* setup vertical timing values. */
 187         val = VIDTCON0_VBPD(timing->upper_margin - 1) |
 188                VIDTCON0_VFPD(timing->lower_margin - 1) |
 189                VIDTCON0_VSPW(timing->vsync_len - 1);
 190         writel(val, ctx->regs + VIDTCON0);
 191
 192         /* setup horizontal timing values.  */
 193         val = VIDTCON1_HBPD(timing->left_margin - 1) |
 194                VIDTCON1_HFPD(timing->right_margin - 1) |
 195                VIDTCON1_HSPW(timing->hsync_len - 1);
 196         writel(val, ctx->regs + VIDTCON1);
 197
 198         /* setup horizontal and vertical display size. */
 199         val = VIDTCON2_LINEVAL(timing->yres - 1) |
 200                VIDTCON2_HOZVAL(timing->xres - 1);
 201         writel(val, ctx->regs + VIDTCON2);
 202
 203         /* setup clock source, clock divider, enable dma. */
 204         val = ctx->vidcon0;
 205         val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
 206
 207         if (ctx->clkdiv > 1)
 208                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 209         else
 210                 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
 211
 212         /*
 213          * fields of register with prefix '_F' would be updated
 214          * at vsync(same as dma start)
 215          */
 216         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 217         writel(val, ctx->regs + VIDCON0);
 218 }
 219
 220 static int fimd_enable_vblank(struct device *dev)
 221 {
 222         struct fimd_context *ctx = get_fimd_context(dev);
 223         u32 val;
 224
 225         DRM_DEBUG_KMS("%s\n", __FILE__);
 226
 227         if (ctx->suspended)
 228                 return -EPERM;
 229
 230         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 231                 val = readl(ctx->regs + VIDINTCON0);
 232
 233                 val |= VIDINTCON0_INT_ENABLE;
 234                 val |= VIDINTCON0_INT_FRAME;
 235
 236                 val &= ~VIDINTCON0_FRAMESEL0_MASK;
 237                 val |= VIDINTCON0_FRAMESEL0_VSYNC;
 238                 val &= ~VIDINTCON0_FRAMESEL1_MASK;
 239                 val |= VIDINTCON0_FRAMESEL1_NONE;
 240
 241                 writel(val, ctx->regs + VIDINTCON0);
 242         }
 243
 244         return 0;
 245 }
 246
 247 static void fimd_disable_vblank(struct device *dev)
 248 {
 249         struct fimd_context *ctx = get_fimd_context(dev);
 250         u32 val;
 251
 252         DRM_DEBUG_KMS("%s\n", __FILE__);
 253
 254         if (ctx->suspended)
 255                 return;
 256
 257         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 258                 val = readl(ctx->regs + VIDINTCON0);
 259
 260                 val &= ~VIDINTCON0_INT_FRAME;
 261                 val &= ~VIDINTCON0_INT_ENABLE;
 262
 263                 writel(val, ctx->regs + VIDINTCON0);
 264         }
 265 }
 266
 267 static struct exynos_drm_manager_ops fimd_manager_ops = {
 268         .dpms = fimd_dpms,
 269         .apply = fimd_apply,
 270         .commit = fimd_commit,
 271         .enable_vblank = fimd_enable_vblank,
 272         .disable_vblank = fimd_disable_vblank,
 273 };
 274
 275 static void fimd_win_mode_set(struct device *dev,
 276                               struct exynos_drm_overlay *overlay)
 277 {
 278         struct fimd_context *ctx = get_fimd_context(dev);
 279         struct fimd_win_data *win_data;
 280         unsigned long offset;
 281
 282         DRM_DEBUG_KMS("%s\n", __FILE__);
 283
 284         if (!overlay) {
 285                 dev_err(dev, "overlay is NULL\n");
 286                 return;
 287         }
 288
 289         offset = overlay->fb_x * (overlay->bpp >> 3);
 290         offset += overlay->fb_y * overlay->pitch;
 291
 292         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
 293
 294         win_data = &ctx->win_data[ctx->default_win];
 295
 296         win_data->offset_x = overlay->crtc_x;
 297         win_data->offset_y = overlay->crtc_y;
 298         win_data->ovl_width = overlay->crtc_width;
 299         win_data->ovl_height = overlay->crtc_height;
 300         win_data->fb_width = overlay->fb_width;
 301         win_data->fb_height = overlay->fb_height;
 302         win_data->dma_addr = overlay->dma_addr + offset;
 303         win_data->vaddr = overlay->vaddr + offset;
 304         win_data->bpp = overlay->bpp;
 305         win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
 306                                 (overlay->bpp >> 3);
 307         win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
 308
 309         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 310                         win_data->offset_x, win_data->offset_y);
 311         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 312                         win_data->ovl_width, win_data->ovl_height);
 313         DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
 314                         (unsigned long)win_data->dma_addr,
 315                         (unsigned long)win_data->vaddr);
 316         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 317                         overlay->fb_width, overlay->crtc_width);
 318 }
 319
 320 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
 321 {
 322         struct fimd_context *ctx = get_fimd_context(dev);
 323         struct fimd_win_data *win_data = &ctx->win_data[win];
 324         unsigned long val;
 325
 326         DRM_DEBUG_KMS("%s\n", __FILE__);
 327
 328         val = WINCONx_ENWIN;
 329
 330         switch (win_data->bpp) {
 331         case 1:
 332                 val |= WINCON0_BPPMODE_1BPP;
 333                 val |= WINCONx_BITSWP;
 334                 val |= WINCONx_BURSTLEN_4WORD;
 335                 break;
 336         case 2:
 337                 val |= WINCON0_BPPMODE_2BPP;
 338                 val |= WINCONx_BITSWP;
 339                 val |= WINCONx_BURSTLEN_8WORD;
 340                 break;
 341         case 4:
 342                 val |= WINCON0_BPPMODE_4BPP;
 343                 val |= WINCONx_BITSWP;
 344                 val |= WINCONx_BURSTLEN_8WORD;
 345                 break;
 346         case 8:
 347                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 348                 val |= WINCONx_BURSTLEN_8WORD;
 349                 val |= WINCONx_BYTSWP;
 350                 break;
 351         case 16:
 352                 val |= WINCON0_BPPMODE_16BPP_565;
 353                 val |= WINCONx_HAWSWP;
 354                 val |= WINCONx_BURSTLEN_16WORD;
 355                 break;
 356         case 24:
 357                 val |= WINCON0_BPPMODE_24BPP_888;
 358                 val |= WINCONx_WSWP;
 359                 val |= WINCONx_BURSTLEN_16WORD;
 360                 break;
 361         case 32:
 362                 val |= WINCON1_BPPMODE_28BPP_A4888
 363                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 364                 val |= WINCONx_WSWP;
 365                 val |= WINCONx_BURSTLEN_16WORD;
 366                 break;
 367         default:
 368                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 369
 370                 val |= WINCON0_BPPMODE_24BPP_888;
 371                 val |= WINCONx_WSWP;
 372                 val |= WINCONx_BURSTLEN_16WORD;
 373                 break;
 374         }
 375
 376         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 377
 378         writel(val, ctx->regs + WINCON(win));
 379 }
 380
 381 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
 382 {
 383         struct fimd_context *ctx = get_fimd_context(dev);
 384         unsigned int keycon0 = 0, keycon1 = 0;
 385
 386         DRM_DEBUG_KMS("%s\n", __FILE__);
 387
 388         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 389                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 390
 391         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 392
 393         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 394         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 395 }
 396
 397 static void fimd_win_commit(struct device *dev)
 398 {
 399         struct fimd_context *ctx = get_fimd_context(dev);
 400         struct fimd_win_data *win_data;
 401         int win = ctx->default_win;
 402         unsigned long val, alpha, size;
 403
 404         DRM_DEBUG_KMS("%s\n", __FILE__);
 405
 406         if (win < 0 || win > WINDOWS_NR)
 407                 return;
 408
 409         win_data = &ctx->win_data[win];
 410
 411         /*
 412          * SHADOWCON register is used for enabling timing.
 413          *
 414          * for example, once only width value of a register is set,
 415          * if the dma is started then fimd hardware could malfunction so
 416          * with protect window setting, the register fields with prefix '_F'
 417          * wouldn't be updated at vsync also but updated once unprotect window
 418          * is set.
 419          */
 420
 421         /* protect windows */
 422         val = readl(ctx->regs + SHADOWCON);
 423         val |= SHADOWCON_WINx_PROTECT(win);
 424         writel(val, ctx->regs + SHADOWCON);
 425
 426         /* buffer start address */
 427         val = (unsigned long)win_data->dma_addr;
 428         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 429
 430         /* buffer end address */
 431         size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
 432         val = (unsigned long)(win_data->dma_addr + size);
 433         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 434
 435         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 436                         (unsigned long)win_data->dma_addr, val, size);
 437         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 438                         win_data->ovl_width, win_data->ovl_height);
 439
 440         /* buffer size */
 441         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 442                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
 443         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 444
 445         /* OSD position */
 446         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 447                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
 448         writel(val, ctx->regs + VIDOSD_A(win));
 449
 450         val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
 451                                         win_data->ovl_width - 1) |
 452                 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
 453                                         win_data->ovl_height - 1);
 454         writel(val, ctx->regs + VIDOSD_B(win));
 455
 456         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 457                         win_data->offset_x, win_data->offset_y,
 458                         win_data->offset_x + win_data->ovl_width - 1,
 459                         win_data->offset_y + win_data->ovl_height - 1);
 460
 461         /* hardware window 0 doesn't support alpha channel. */
 462         if (win != 0) {
 463                 /* OSD alpha */
 464                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 465                         VIDISD14C_ALPHA1_G(0xf) |
 466                         VIDISD14C_ALPHA1_B(0xf);
 467
 468                 writel(alpha, ctx->regs + VIDOSD_C(win));
 469         }
 470
 471         /* OSD size */
 472         if (win != 3 && win != 4) {
 473                 u32 offset = VIDOSD_D(win);
 474                 if (win == 0)
 475                         offset = VIDOSD_C_SIZE_W0;
 476                 val = win_data->ovl_width * win_data->ovl_height;
 477                 writel(val, ctx->regs + offset);
 478
 479                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 480         }
 481
 482         fimd_win_set_pixfmt(dev, win);
 483
 484         /* hardware window 0 doesn't support color key. */
 485         if (win != 0)
 486                 fimd_win_set_colkey(dev, win);
 487
 488         /* wincon */
 489         val = readl(ctx->regs + WINCON(win));
 490         val |= WINCONx_ENWIN;
 491         writel(val, ctx->regs + WINCON(win));
 492
 493         /* Enable DMA channel and unprotect windows */
 494         val = readl(ctx->regs + SHADOWCON);
 495         val |= SHADOWCON_CHx_ENABLE(win);
 496         val &= ~SHADOWCON_WINx_PROTECT(win);
 497         writel(val, ctx->regs + SHADOWCON);
 498
 499         win_data->enabled = true;
 500 }
 501
 502 static void fimd_win_disable(struct device *dev)
 503 {
 504         struct fimd_context *ctx = get_fimd_context(dev);
 505         struct fimd_win_data *win_data;
 506         int win = ctx->default_win;
 507         u32 val;
 508
 509         DRM_DEBUG_KMS("%s\n", __FILE__);
 510
 511         if (win < 0 || win > WINDOWS_NR)
 512                 return;
 513
 514         win_data = &ctx->win_data[win];
 515
 516         /* protect windows */
 517         val = readl(ctx->regs + SHADOWCON);
 518         val |= SHADOWCON_WINx_PROTECT(win);
 519         writel(val, ctx->regs + SHADOWCON);
 520
 521         /* wincon */
 522         val = readl(ctx->regs + WINCON(win));
 523         val &= ~WINCONx_ENWIN;
 524         writel(val, ctx->regs + WINCON(win));
 525
 526         /* unprotect windows */
 527         val = readl(ctx->regs + SHADOWCON);
 528         val &= ~SHADOWCON_CHx_ENABLE(win);
 529         val &= ~SHADOWCON_WINx_PROTECT(win);
 530         writel(val, ctx->regs + SHADOWCON);
 531
 532         win_data->enabled = false;
 533 }
 534
 535 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
 536         .mode_set = fimd_win_mode_set,
 537         .commit = fimd_win_commit,
 538         .disable = fimd_win_disable,
 539 };
 540
 541 static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
 542 {
 543         struct exynos_drm_private *dev_priv = drm_dev->dev_private;
 544         struct drm_pending_vblank_event *e, *t;
 545         struct timeval now;
 546         unsigned long flags;
 547         bool is_checked = false;
 548
 549         spin_lock_irqsave(&drm_dev->event_lock, flags);
 550
 551         list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
 552                         base.link) {
 553                 /* if event's pipe isn't same as crtc then ignore it. */
 554                 if (crtc != e->pipe)
 555                         continue;
 556
 557                 is_checked = true;
 558
 559                 do_gettimeofday(&now);
 560                 e->event.sequence = 0;
 561                 e->event.tv_sec = now.tv_sec;
 562                 e->event.tv_usec = now.tv_usec;
 563
 564                 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
 565                 wake_up_interruptible(&e->base.file_priv->event_wait);
 566         }
 567
 568         if (is_checked) {
 569                 drm_vblank_put(drm_dev, crtc);
 570
 571                 /*
 572                  * don't off vblank if vblank_disable_allowed is 1,
 573                  * because vblank would be off by timer handler.
 574                  */
 575                 if (!drm_dev->vblank_disable_allowed)
 576                         drm_vblank_off(drm_dev, crtc);
 577         }
 578
 579         spin_unlock_irqrestore(&drm_dev->event_lock, flags);
 580 }
 581
 582 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 583 {
 584         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 585         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 586         struct drm_device *drm_dev = subdrv->drm_dev;
 587         struct exynos_drm_manager *manager = &subdrv->manager;
 588         u32 val;
 589
 590         val = readl(ctx->regs + VIDINTCON1);
 591
 592         if (val & VIDINTCON1_INT_FRAME)
 593                 /* VSYNC interrupt */
 594                 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
 595
 596         /* check the crtc is detached already from encoder */
 597         if (manager->pipe < 0)
 598                 goto out;
 599
 600         drm_handle_vblank(drm_dev, manager->pipe);
 601         fimd_finish_pageflip(drm_dev, manager->pipe);
 602
 603 out:
 604         return IRQ_HANDLED;
 605 }
 606
 607 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 608 {
 609         DRM_DEBUG_KMS("%s\n", __FILE__);
 610
 611         /*
 612          * enable drm irq mode.
 613          * - with irq_enabled = 1, we can use the vblank feature.
 614          *
 615          * P.S. note that we wouldn't use drm irq handler but
 616          *      just specific driver own one instead because
 617          *      drm framework supports only one irq handler.
 618          */
 619         drm_dev->irq_enabled = 1;
 620
 621         /*
 622          * with vblank_disable_allowed = 1, vblank interrupt will be disabled
 623          * by drm timer once a current process gives up ownership of
 624          * vblank event.(after drm_vblank_put function is called)
 625          */
 626         drm_dev->vblank_disable_allowed = 1;
 627
 628         return 0;
 629 }
 630
 631 static void fimd_subdrv_remove(struct drm_device *drm_dev)
 632 {
 633         DRM_DEBUG_KMS("%s\n", __FILE__);
 634
 635         /* TODO. */
 636 }
 637
 638 static int fimd_calc_clkdiv(struct fimd_context *ctx,
 639                             struct fb_videomode *timing)
 640 {
 641         unsigned long clk = clk_get_rate(ctx->lcd_clk);
 642         u32 retrace;
 643         u32 clkdiv;
 644         u32 best_framerate = 0;
 645         u32 framerate;
 646
 647         DRM_DEBUG_KMS("%s\n", __FILE__);
 648
 649         retrace = timing->left_margin + timing->hsync_len +
 650                                 timing->right_margin + timing->xres;
 651         retrace *= timing->upper_margin + timing->vsync_len +
 652                                 timing->lower_margin + timing->yres;
 653
 654         /* default framerate is 60Hz */
 655         if (!timing->refresh)
 656                 timing->refresh = 60;
 657
 658         clk /= retrace;
 659
 660         for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
 661                 int tmp;
 662
 663                 /* get best framerate */
 664                 framerate = clk / clkdiv;
 665                 tmp = timing->refresh - framerate;
 666                 if (tmp < 0) {
 667                         best_framerate = framerate;
 668                         continue;
 669                 } else {
 670                         if (!best_framerate)
 671                                 best_framerate = framerate;
 672                         else if (tmp < (best_framerate - framerate))
 673                                 best_framerate = framerate;
 674                         break;
 675                 }
 676         }
 677
 678         return clkdiv;
 679 }
 680
 681 static void fimd_clear_win(struct fimd_context *ctx, int win)
 682 {
 683         u32 val;
 684
 685         DRM_DEBUG_KMS("%s\n", __FILE__);
 686
 687         writel(0, ctx->regs + WINCON(win));
 688         writel(0, ctx->regs + VIDOSD_A(win));
 689         writel(0, ctx->regs + VIDOSD_B(win));
 690         writel(0, ctx->regs + VIDOSD_C(win));
 691
 692         if (win == 1 || win == 2)
 693                 writel(0, ctx->regs + VIDOSD_D(win));
 694
 695         val = readl(ctx->regs + SHADOWCON);
 696         val &= ~SHADOWCON_WINx_PROTECT(win);
 697         writel(val, ctx->regs + SHADOWCON);
 698 }
 699
 700 static int __devinit fimd_probe(struct platform_device *pdev)
 701 {
 702         struct device *dev = &pdev->dev;
 703         struct fimd_context *ctx;
 704         struct exynos_drm_subdrv *subdrv;
 705         struct exynos_drm_fimd_pdata *pdata;
 706         struct fb_videomode *timing;
 707         struct resource *res;
 708         int win;
 709         int ret = -EINVAL;
 710
 711         DRM_DEBUG_KMS("%s\n", __FILE__);
 712
 713         pdata = pdev->dev.platform_data;
 714         if (!pdata) {
 715                 dev_err(dev, "no platform data specified\n");
 716                 return -EINVAL;
 717         }
 718
 719         timing = &pdata->timing;
 720         if (!timing) {
 721                 dev_err(dev, "timing is null.\n");
 722                 return -EINVAL;
 723         }
 724
 725         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 726         if (!ctx)
 727                 return -ENOMEM;
 728
 729         ctx->bus_clk = clk_get(dev, "fimd");
 730         if (IS_ERR(ctx->bus_clk)) {
 731                 dev_err(dev, "failed to get bus clock\n");
 732                 ret = PTR_ERR(ctx->bus_clk);
 733                 goto err_clk_get;
 734         }
 735
 736         clk_enable(ctx->bus_clk);
 737
 738         ctx->lcd_clk = clk_get(dev, "sclk_fimd");
 739         if (IS_ERR(ctx->lcd_clk)) {
 740                 dev_err(dev, "failed to get lcd clock\n");
 741                 ret = PTR_ERR(ctx->lcd_clk);
 742                 goto err_bus_clk;
 743         }
 744
 745         clk_enable(ctx->lcd_clk);
 746
 747         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 748         if (!res) {
 749                 dev_err(dev, "failed to find registers\n");
 750                 ret = -ENOENT;
 751                 goto err_clk;
 752         }
 753
 754         ctx->regs_res = request_mem_region(res->start, resource_size(res),
 755                                            dev_name(dev));
 756         if (!ctx->regs_res) {
 757                 dev_err(dev, "failed to claim register region\n");
 758                 ret = -ENOENT;
 759                 goto err_clk;
 760         }
 761
 762         ctx->regs = ioremap(res->start, resource_size(res));
 763         if (!ctx->regs) {
 764                 dev_err(dev, "failed to map registers\n");
 765                 ret = -ENXIO;
 766                 goto err_req_region_io;
 767         }
 768
 769         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 770         if (!res) {
 771                 dev_err(dev, "irq request failed.\n");
 772                 goto err_req_region_irq;
 773         }
 774
 775         ctx->irq = res->start;
 776
 777         ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
 778         if (ret < 0) {
 779                 dev_err(dev, "irq request failed.\n");
 780                 goto err_req_irq;
 781         }
 782
 783         pm_runtime_set_active(dev);
 784         pm_runtime_enable(dev);
 785         pm_runtime_get_sync(dev);
 786
 787         for (win = 0; win < WINDOWS_NR; win++)
 788                 fimd_clear_win(ctx, win);
 789
 790         ctx->clkdiv = fimd_calc_clkdiv(ctx, timing);
 791         ctx->vidcon0 = pdata->vidcon0;
 792         ctx->vidcon1 = pdata->vidcon1;
 793         ctx->default_win = pdata->default_win;
 794         ctx->timing = timing;
 795
 796         timing->pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
 797
 798         DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
 799                         timing->pixclock, ctx->clkdiv);
 800
 801         subdrv = &ctx->subdrv;
 802
 803         subdrv->probe = fimd_subdrv_probe;
 804         subdrv->remove = fimd_subdrv_remove;
 805         subdrv->manager.pipe = -1;
 806         subdrv->manager.ops = &fimd_manager_ops;
 807         subdrv->manager.overlay_ops = &fimd_overlay_ops;
 808         subdrv->manager.display_ops = &fimd_display_ops;
 809         subdrv->manager.dev = dev;
 810
 811         platform_set_drvdata(pdev, ctx);
 812         exynos_drm_subdrv_register(subdrv);
 813
 814         return 0;
 815
 816 err_req_irq:
 817 err_req_region_irq:
 818         iounmap(ctx->regs);
 819
 820 err_req_region_io:
 821         release_resource(ctx->regs_res);
 822         kfree(ctx->regs_res);
 823
 824 err_clk:
 825         clk_disable(ctx->lcd_clk);
 826         clk_put(ctx->lcd_clk);
 827
 828 err_bus_clk:
 829         clk_disable(ctx->bus_clk);
 830         clk_put(ctx->bus_clk);
 831
 832 err_clk_get:
 833         kfree(ctx);
 834         return ret;
 835 }
 836
 837 static int __devexit fimd_remove(struct platform_device *pdev)
 838 {
 839         struct device *dev = &pdev->dev;
 840         struct fimd_context *ctx = platform_get_drvdata(pdev);
 841
 842         DRM_DEBUG_KMS("%s\n", __FILE__);
 843
 844         exynos_drm_subdrv_unregister(&ctx->subdrv);
 845
 846         if (ctx->suspended)
 847                 goto out;
 848
 849         clk_disable(ctx->lcd_clk);
 850         clk_disable(ctx->bus_clk);
 851
 852         pm_runtime_set_suspended(dev);
 853         pm_runtime_put_sync(dev);
 854
 855 out:
 856         pm_runtime_disable(dev);
 857
 858         clk_put(ctx->lcd_clk);
 859         clk_put(ctx->bus_clk);
 860
 861         iounmap(ctx->regs);
 862         release_resource(ctx->regs_res);
 863         kfree(ctx->regs_res);
 864         free_irq(ctx->irq, ctx);
 865
 866         kfree(ctx);
 867
 868         return 0;
 869 }
 870
 871 #ifdef CONFIG_PM_RUNTIME
 872 static int fimd_runtime_suspend(struct device *dev)
 873 {
 874         struct fimd_context *ctx = get_fimd_context(dev);
 875
 876         DRM_DEBUG_KMS("%s\n", __FILE__);
 877
 878         clk_disable(ctx->lcd_clk);
 879         clk_disable(ctx->bus_clk);
 880
 881         ctx->suspended = true;
 882         return 0;
 883 }
 884
 885 static int fimd_runtime_resume(struct device *dev)
 886 {
 887         struct fimd_context *ctx = get_fimd_context(dev);
 888         int ret;
 889
 890         DRM_DEBUG_KMS("%s\n", __FILE__);
 891
 892         ret = clk_enable(ctx->bus_clk);
 893         if (ret < 0)
 894                 return ret;
 895
 896         ret = clk_enable(ctx->lcd_clk);
 897         if  (ret < 0) {
 898                 clk_disable(ctx->bus_clk);
 899                 return ret;
 900         }
 901
 902         ctx->suspended = false;
 903         return 0;
 904 }
 905 #endif
 906
 907 static const struct dev_pm_ops fimd_pm_ops = {
 908         SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
 909 };
 910
 911 static struct platform_driver fimd_driver = {
 912         .probe          = fimd_probe,
 913         .remove         = __devexit_p(fimd_remove),
 914         .driver         = {
 915                 .name   = "exynos4-fb",
 916                 .owner  = THIS_MODULE,
 917                 .pm     = &fimd_pm_ops,
 918         },
 919 };
 920
 921 static int __init fimd_init(void)
 922 {
 923         return platform_driver_register(&fimd_driver);
 924 }
 925
 926 static void __exit fimd_exit(void)
 927 {
 928         platform_driver_unregister(&fimd_driver);
 929 }
 930
 931 module_init(fimd_init);
 932 module_exit(fimd_exit);
 933
 934 MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
 935 MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
 936 MODULE_DESCRIPTION("Samsung DRM FIMD Driver");
 937 MODULE_LICENSE("GPL");