2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
18 #include <linux/pm_runtime.h>
19 #include <plat/map-base.h>
22 #include <drm/exynos_drm.h>
23 #include "regs-fimc.h"
24 #include "exynos_drm_ipp.h"
25 #include "exynos_drm_fimc.h"
28 * FIMC stands for Fully Interactive Mobile Camera and
29 * supports image scaler/rotator and input/output DMA operations.
30 * input DMA reads image data from the memory.
31 * output DMA writes image data to memory.
32 * FIMC supports image rotation and image effect functions.
34 * M2M operation : supports crop/scale/rotation/csc so on.
35 * Memory ----> FIMC H/W ----> Memory.
36 * Writeback operation : supports cloned screen with FIMD.
37 * FIMD ----> FIMC H/W ----> Memory.
38 * Output operation : supports direct display using local path.
39 * Memory ----> FIMC H/W ----> FIMD.
44 * 1. check suspend/resume api if needed.
45 * 2. need to check use case platform_device_id.
46 * 3. check src/dst size with, height.
47 * 4. added check_prepare api for right register.
48 * 5. need to add supported list in prop_list.
49 * 6. check prescaler/scaler optimization.
52 #define FIMC_MAX_DEVS 4
53 #define FIMC_MAX_SRC 2
54 #define FIMC_MAX_DST 32
55 #define FIMC_SHFACTOR 10
56 #define FIMC_BUF_STOP 1
57 #define FIMC_BUF_START 2
58 #define FIMC_REG_SZ 32
59 #define FIMC_WIDTH_ITU_709 1280
60 #define FIMC_REFRESH_MAX 60
61 #define FIMC_REFRESH_MIN 12
62 #define FIMC_CROP_MAX 8192
63 #define FIMC_CROP_MIN 32
64 #define FIMC_SCALE_MAX 4224
65 #define FIMC_SCALE_MIN 32
67 #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev))
68 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
69 struct fimc_context, ippdrv);
70 #define fimc_read(offset) readl(ctx->regs + (offset))
71 #define fimc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
80 * A structure of scaler.
82 * @range: narrow, wide.
83 * @bypass: unused scaler path.
84 * @up_h: horizontal scale up.
85 * @up_v: vertical scale up.
86 * @hratio: horizontal ratio.
87 * @vratio: vertical ratio.
99 * A structure of scaler capability.
101 * find user manual table 43-1.
102 * @in_hori: scaler input horizontal size.
103 * @bypass: scaler bypass mode.
104 * @dst_h_wo_rot: target horizontal size without output rotation.
105 * @dst_h_rot: target horizontal size with output rotation.
106 * @rl_w_wo_rot: real width without input rotation.
107 * @rl_h_rot: real height without output rotation.
109 struct fimc_capability {
122 * A structure of fimc driver data.
124 * @parent_clk: name of parent clock.
126 struct fimc_driverdata {
131 * A structure of fimc context.
133 * @ippdrv: prepare initialization using ippdrv.
134 * @regs_res: register resources.
135 * @regs: memory mapped io registers.
136 * @lock: locking of operations.
137 * @sclk_fimc_clk: fimc source clock.
138 * @fimc_clk: fimc clock.
139 * @wb_clk: writeback a clock.
140 * @wb_b_clk: writeback b clock.
141 * @sc: scaler infomations.
142 * @odr: ordering of YUV.
143 * @ver: fimc version.
144 * @pol: porarity of writeback.
147 * @suspended: qos operations.
149 struct fimc_context {
150 struct exynos_drm_ippdrv ippdrv;
151 struct resource *regs_res;
154 struct clk *sclk_fimc_clk;
155 struct clk *fimc_clk;
157 struct clk *wb_b_clk;
158 struct fimc_scaler sc;
159 struct fimc_driverdata *ddata;
160 struct exynos_drm_ipp_pol pol;
166 static void fimc_sw_reset(struct fimc_context *ctx)
170 DRM_DEBUG_KMS("%s\n", __func__);
172 /* stop dma operation */
173 cfg = fimc_read(EXYNOS_CISTATUS);
174 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) {
175 cfg = fimc_read(EXYNOS_MSCTRL);
176 cfg &= ~EXYNOS_MSCTRL_ENVID;
177 fimc_write(cfg, EXYNOS_MSCTRL);
180 cfg = fimc_read(EXYNOS_CISRCFMT);
181 cfg |= EXYNOS_CISRCFMT_ITU601_8BIT;
182 fimc_write(cfg, EXYNOS_CISRCFMT);
184 /* disable image capture */
185 cfg = fimc_read(EXYNOS_CIIMGCPT);
186 cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
187 fimc_write(cfg, EXYNOS_CIIMGCPT);
190 cfg = fimc_read(EXYNOS_CIGCTRL);
191 cfg |= (EXYNOS_CIGCTRL_SWRST);
192 fimc_write(cfg, EXYNOS_CIGCTRL);
194 /* s/w reset complete */
195 cfg = fimc_read(EXYNOS_CIGCTRL);
196 cfg &= ~EXYNOS_CIGCTRL_SWRST;
197 fimc_write(cfg, EXYNOS_CIGCTRL);
200 fimc_write(0x0, EXYNOS_CIFCNTSEQ);
203 static void fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
207 DRM_DEBUG_KMS("%s\n", __func__);
209 camblk_cfg = readl(SYSREG_CAMERA_BLK);
210 camblk_cfg &= ~(SYSREG_FIMD0WB_DEST_MASK);
211 camblk_cfg |= ctx->id << (SYSREG_FIMD0WB_DEST_SHIFT);
213 writel(camblk_cfg, SYSREG_CAMERA_BLK);
216 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
220 DRM_DEBUG_KMS("%s:wb[%d]\n", __func__, wb);
222 cfg = fimc_read(EXYNOS_CIGCTRL);
223 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
224 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
225 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
226 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
227 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
228 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
232 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
233 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
236 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
237 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
241 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
242 EXYNOS_CIGCTRL_SELWRITEBACK_A |
243 EXYNOS_CIGCTRL_SELCAM_MIPI_A |
244 EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
248 fimc_write(cfg, EXYNOS_CIGCTRL);
251 static void fimc_set_polarity(struct fimc_context *ctx,
252 struct exynos_drm_ipp_pol *pol)
256 DRM_DEBUG_KMS("%s:inv_pclk[%d]inv_vsync[%d]\n",
257 __func__, pol->inv_pclk, pol->inv_vsync);
258 DRM_DEBUG_KMS("%s:inv_href[%d]inv_hsync[%d]\n",
259 __func__, pol->inv_href, pol->inv_hsync);
261 cfg = fimc_read(EXYNOS_CIGCTRL);
262 cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
263 EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
266 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
268 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
270 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
272 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
274 fimc_write(cfg, EXYNOS_CIGCTRL);
277 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
281 DRM_DEBUG_KMS("%s:enable[%d]\n", __func__, enable);
283 cfg = fimc_read(EXYNOS_CIGCTRL);
285 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
287 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
289 fimc_write(cfg, EXYNOS_CIGCTRL);
292 static void fimc_handle_irq(struct fimc_context *ctx, bool enable,
293 bool overflow, bool level)
297 DRM_DEBUG_KMS("%s:enable[%d]overflow[%d]level[%d]\n", __func__,
298 enable, overflow, level);
300 cfg = fimc_read(EXYNOS_CIGCTRL);
302 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_LEVEL);
303 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE;
305 cfg |= EXYNOS_CIGCTRL_IRQ_OVFEN;
307 cfg |= EXYNOS_CIGCTRL_IRQ_LEVEL;
309 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_ENABLE);
311 fimc_write(cfg, EXYNOS_CIGCTRL);
314 static void fimc_clear_irq(struct fimc_context *ctx)
318 DRM_DEBUG_KMS("%s\n", __func__);
320 cfg = fimc_read(EXYNOS_CIGCTRL);
321 cfg |= EXYNOS_CIGCTRL_IRQ_CLR;
322 fimc_write(cfg, EXYNOS_CIGCTRL);
325 static bool fimc_check_ovf(struct fimc_context *ctx)
327 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
328 u32 cfg, status, flag;
330 status = fimc_read(EXYNOS_CISTATUS);
331 flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
332 EXYNOS_CISTATUS_OVFICR;
334 DRM_DEBUG_KMS("%s:flag[0x%x]\n", __func__, flag);
337 cfg = fimc_read(EXYNOS_CIWDOFST);
338 cfg |= (EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
339 EXYNOS_CIWDOFST_CLROVFICR);
341 fimc_write(cfg, EXYNOS_CIWDOFST);
343 cfg = fimc_read(EXYNOS_CIWDOFST);
344 cfg &= ~(EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
345 EXYNOS_CIWDOFST_CLROVFICR);
347 fimc_write(cfg, EXYNOS_CIWDOFST);
349 dev_err(ippdrv->dev, "occured overflow at %d, status 0x%x.\n",
357 static bool fimc_check_frame_end(struct fimc_context *ctx)
361 cfg = fimc_read(EXYNOS_CISTATUS);
363 DRM_DEBUG_KMS("%s:cfg[0x%x]\n", __func__, cfg);
365 if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
368 cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
369 fimc_write(cfg, EXYNOS_CISTATUS);
374 static int fimc_get_buf_id(struct fimc_context *ctx)
377 int frame_cnt, buf_id;
379 DRM_DEBUG_KMS("%s\n", __func__);
381 cfg = fimc_read(EXYNOS_CISTATUS2);
382 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
385 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
387 DRM_DEBUG_KMS("%s:present[%d]before[%d]\n", __func__,
388 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
389 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
391 if (frame_cnt == 0) {
392 DRM_ERROR("failed to get frame count.\n");
396 buf_id = frame_cnt - 1;
397 DRM_DEBUG_KMS("%s:buf_id[%d]\n", __func__, buf_id);
402 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
406 DRM_DEBUG_KMS("%s:enable[%d]\n", __func__, enable);
408 cfg = fimc_read(EXYNOS_CIOCTRL);
410 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
412 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
414 fimc_write(cfg, EXYNOS_CIOCTRL);
418 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
420 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
423 DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt);
426 cfg = fimc_read(EXYNOS_CISCCTRL);
427 cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
430 case DRM_FORMAT_RGB565:
431 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
432 fimc_write(cfg, EXYNOS_CISCCTRL);
434 case DRM_FORMAT_RGB888:
435 case DRM_FORMAT_XRGB8888:
436 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
437 fimc_write(cfg, EXYNOS_CISCCTRL);
445 cfg = fimc_read(EXYNOS_MSCTRL);
446 cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
447 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
448 EXYNOS_MSCTRL_ORDER422_YCBYCR);
451 case DRM_FORMAT_YUYV:
452 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
454 case DRM_FORMAT_YVYU:
455 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
457 case DRM_FORMAT_UYVY:
458 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
460 case DRM_FORMAT_VYUY:
461 case DRM_FORMAT_YUV444:
462 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
464 case DRM_FORMAT_NV21:
465 case DRM_FORMAT_NV61:
466 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
467 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
469 case DRM_FORMAT_YUV422:
470 case DRM_FORMAT_YUV420:
471 case DRM_FORMAT_YVU420:
472 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
474 case DRM_FORMAT_NV12:
475 case DRM_FORMAT_NV12MT:
476 case DRM_FORMAT_NV16:
477 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
478 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
481 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
485 fimc_write(cfg, EXYNOS_MSCTRL);
490 static int fimc_src_set_fmt(struct device *dev, u32 fmt)
492 struct fimc_context *ctx = get_fimc_context(dev);
493 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
496 DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt);
498 cfg = fimc_read(EXYNOS_MSCTRL);
499 cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
502 case DRM_FORMAT_RGB565:
503 case DRM_FORMAT_RGB888:
504 case DRM_FORMAT_XRGB8888:
505 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
507 case DRM_FORMAT_YUV444:
508 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
510 case DRM_FORMAT_YUYV:
511 case DRM_FORMAT_YVYU:
512 case DRM_FORMAT_UYVY:
513 case DRM_FORMAT_VYUY:
514 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
516 case DRM_FORMAT_NV16:
517 case DRM_FORMAT_NV61:
518 case DRM_FORMAT_YUV422:
519 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
521 case DRM_FORMAT_YUV420:
522 case DRM_FORMAT_YVU420:
523 case DRM_FORMAT_NV12:
524 case DRM_FORMAT_NV21:
525 case DRM_FORMAT_NV12MT:
526 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
529 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
533 fimc_write(cfg, EXYNOS_MSCTRL);
535 cfg = fimc_read(EXYNOS_CIDMAPARAM);
536 cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
538 if (fmt == DRM_FORMAT_NV12MT)
539 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32;
541 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
543 fimc_write(cfg, EXYNOS_CIDMAPARAM);
545 return fimc_src_set_fmt_order(ctx, fmt);
548 static int fimc_src_set_transf(struct device *dev,
549 enum drm_exynos_degree degree,
550 enum drm_exynos_flip flip, bool *swap)
552 struct fimc_context *ctx = get_fimc_context(dev);
553 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
556 DRM_DEBUG_KMS("%s:degree[%d]flip[0x%x]\n", __func__,
559 cfg1 = fimc_read(EXYNOS_MSCTRL);
560 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
561 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
563 cfg2 = fimc_read(EXYNOS_CITRGFMT);
564 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
567 case EXYNOS_DRM_DEGREE_0:
568 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
569 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
570 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
571 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
573 case EXYNOS_DRM_DEGREE_90:
574 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
575 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
576 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
577 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
578 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
580 case EXYNOS_DRM_DEGREE_180:
581 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
582 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
583 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
584 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
585 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
586 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
588 case EXYNOS_DRM_DEGREE_270:
589 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
590 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
591 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
592 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
593 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
594 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
595 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
598 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
602 fimc_write(cfg1, EXYNOS_MSCTRL);
603 fimc_write(cfg2, EXYNOS_CITRGFMT);
604 *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
609 static int fimc_set_window(struct fimc_context *ctx,
610 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
612 u32 cfg, h1, h2, v1, v2;
616 h2 = sz->hsize - pos->w - pos->x;
618 v2 = sz->vsize - pos->h - pos->y;
620 DRM_DEBUG_KMS("%s:x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
621 __func__, pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
622 DRM_DEBUG_KMS("%s:h1[%d]h2[%d]v1[%d]v2[%d]\n", __func__,
626 * set window offset 1, 2 size
627 * check figure 43-21 in user manual
629 cfg = fimc_read(EXYNOS_CIWDOFST);
630 cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
631 EXYNOS_CIWDOFST_WINVEROFST_MASK);
632 cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
633 EXYNOS_CIWDOFST_WINVEROFST(v1));
634 cfg |= EXYNOS_CIWDOFST_WINOFSEN;
635 fimc_write(cfg, EXYNOS_CIWDOFST);
637 cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
638 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
639 fimc_write(cfg, EXYNOS_CIWDOFST2);
644 static int fimc_src_set_size(struct device *dev, int swap,
645 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
647 struct fimc_context *ctx = get_fimc_context(dev);
648 struct drm_exynos_pos img_pos = *pos;
649 struct drm_exynos_sz img_sz = *sz;
652 DRM_DEBUG_KMS("%s:swap[%d]hsize[%d]vsize[%d]\n",
653 __func__, swap, sz->hsize, sz->vsize);
656 cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
657 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
659 fimc_write(cfg, EXYNOS_ORGISIZE);
661 DRM_DEBUG_KMS("%s:x[%d]y[%d]w[%d]h[%d]\n", __func__,
662 pos->x, pos->y, pos->w, pos->h);
667 img_sz.hsize = sz->vsize;
668 img_sz.vsize = sz->hsize;
671 /* set input DMA image size */
672 cfg = fimc_read(EXYNOS_CIREAL_ISIZE);
673 cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
674 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
675 cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
676 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
677 fimc_write(cfg, EXYNOS_CIREAL_ISIZE);
680 * set input FIFO image size
681 * for now, we support only ITU601 8 bit mode
683 cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
684 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
685 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
686 fimc_write(cfg, EXYNOS_CISRCFMT);
688 /* offset Y(RGB), Cb, Cr */
689 cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
690 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
691 fimc_write(cfg, EXYNOS_CIIYOFF);
692 cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
693 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
694 fimc_write(cfg, EXYNOS_CIICBOFF);
695 cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
696 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
697 fimc_write(cfg, EXYNOS_CIICROFF);
699 return fimc_set_window(ctx, &img_pos, &img_sz);
702 static int fimc_src_set_addr(struct device *dev,
703 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
704 enum drm_exynos_ipp_buf_type buf_type)
706 struct fimc_context *ctx = get_fimc_context(dev);
707 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
708 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
709 struct drm_exynos_ipp_property *property;
710 struct drm_exynos_ipp_config *config;
713 DRM_ERROR("failed to get c_node.\n");
717 property = &c_node->property;
719 DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
720 property->prop_id, buf_id, buf_type);
722 if (buf_id > FIMC_MAX_SRC) {
723 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
727 /* address register set */
729 case IPP_BUF_ENQUEUE:
730 config = &property->config[EXYNOS_DRM_OPS_SRC];
731 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
732 EXYNOS_CIIYSA(buf_id));
734 if (config->fmt == DRM_FORMAT_YVU420) {
735 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
736 EXYNOS_CIICBSA(buf_id));
737 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
738 EXYNOS_CIICRSA(buf_id));
740 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
741 EXYNOS_CIICBSA(buf_id));
742 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
743 EXYNOS_CIICRSA(buf_id));
746 case IPP_BUF_DEQUEUE:
747 fimc_write(0x0, EXYNOS_CIIYSA(buf_id));
748 fimc_write(0x0, EXYNOS_CIICBSA(buf_id));
749 fimc_write(0x0, EXYNOS_CIICRSA(buf_id));
759 static struct exynos_drm_ipp_ops fimc_src_ops = {
760 .set_fmt = fimc_src_set_fmt,
761 .set_transf = fimc_src_set_transf,
762 .set_size = fimc_src_set_size,
763 .set_addr = fimc_src_set_addr,
766 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
768 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
771 DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt);
774 cfg = fimc_read(EXYNOS_CISCCTRL);
775 cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
778 case DRM_FORMAT_RGB565:
779 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
780 fimc_write(cfg, EXYNOS_CISCCTRL);
782 case DRM_FORMAT_RGB888:
783 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
784 fimc_write(cfg, EXYNOS_CISCCTRL);
786 case DRM_FORMAT_XRGB8888:
787 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
788 EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
789 fimc_write(cfg, EXYNOS_CISCCTRL);
797 cfg = fimc_read(EXYNOS_CIOCTRL);
798 cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
799 EXYNOS_CIOCTRL_ORDER422_MASK |
800 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
803 case DRM_FORMAT_XRGB8888:
804 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
806 case DRM_FORMAT_YUYV:
807 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
809 case DRM_FORMAT_YVYU:
810 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
812 case DRM_FORMAT_UYVY:
813 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
815 case DRM_FORMAT_VYUY:
816 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
818 case DRM_FORMAT_NV21:
819 case DRM_FORMAT_NV61:
820 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
821 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
823 case DRM_FORMAT_YUV422:
824 case DRM_FORMAT_YUV420:
825 case DRM_FORMAT_YVU420:
826 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
828 case DRM_FORMAT_NV12:
829 case DRM_FORMAT_NV12MT:
830 case DRM_FORMAT_NV16:
831 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
832 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
835 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
839 fimc_write(cfg, EXYNOS_CIOCTRL);
844 static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
846 struct fimc_context *ctx = get_fimc_context(dev);
847 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
850 DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt);
852 cfg = fimc_read(EXYNOS_CIEXTEN);
854 if (fmt == DRM_FORMAT_AYUV) {
855 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
856 fimc_write(cfg, EXYNOS_CIEXTEN);
858 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
859 fimc_write(cfg, EXYNOS_CIEXTEN);
861 cfg = fimc_read(EXYNOS_CITRGFMT);
862 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
865 case DRM_FORMAT_RGB565:
866 case DRM_FORMAT_RGB888:
867 case DRM_FORMAT_XRGB8888:
868 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
870 case DRM_FORMAT_YUYV:
871 case DRM_FORMAT_YVYU:
872 case DRM_FORMAT_UYVY:
873 case DRM_FORMAT_VYUY:
874 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
876 case DRM_FORMAT_NV16:
877 case DRM_FORMAT_NV61:
878 case DRM_FORMAT_YUV422:
879 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
881 case DRM_FORMAT_YUV420:
882 case DRM_FORMAT_YVU420:
883 case DRM_FORMAT_NV12:
884 case DRM_FORMAT_NV12MT:
885 case DRM_FORMAT_NV21:
886 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
889 dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
894 fimc_write(cfg, EXYNOS_CITRGFMT);
897 cfg = fimc_read(EXYNOS_CIDMAPARAM);
898 cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
900 if (fmt == DRM_FORMAT_NV12MT)
901 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32;
903 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
905 fimc_write(cfg, EXYNOS_CIDMAPARAM);
907 return fimc_dst_set_fmt_order(ctx, fmt);
910 static int fimc_dst_set_transf(struct device *dev,
911 enum drm_exynos_degree degree,
912 enum drm_exynos_flip flip, bool *swap)
914 struct fimc_context *ctx = get_fimc_context(dev);
915 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
918 DRM_DEBUG_KMS("%s:degree[%d]flip[0x%x]\n", __func__,
921 cfg = fimc_read(EXYNOS_CITRGFMT);
922 cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
923 cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
926 case EXYNOS_DRM_DEGREE_0:
927 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
928 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
929 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
930 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
932 case EXYNOS_DRM_DEGREE_90:
933 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
934 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
935 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
936 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
937 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
939 case EXYNOS_DRM_DEGREE_180:
940 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
941 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
942 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
943 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
944 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
945 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
947 case EXYNOS_DRM_DEGREE_270:
948 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
949 EXYNOS_CITRGFMT_FLIP_X_MIRROR |
950 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
951 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
952 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
953 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
954 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
957 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
961 fimc_write(cfg, EXYNOS_CITRGFMT);
962 *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
967 static int fimc_get_ratio_shift(u32 src, u32 dst, u32 *ratio, u32 *shift)
969 DRM_DEBUG_KMS("%s:src[%d]dst[%d]\n", __func__, src, dst);
971 if (src >= dst * 64) {
972 DRM_ERROR("failed to make ratio and shift.\n");
974 } else if (src >= dst * 32) {
977 } else if (src >= dst * 16) {
980 } else if (src >= dst * 8) {
983 } else if (src >= dst * 4) {
986 } else if (src >= dst * 2) {
997 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
998 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
1000 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1001 u32 cfg, cfg_ext, shfactor;
1002 u32 pre_dst_width, pre_dst_height;
1003 u32 pre_hratio, hfactor, pre_vratio, vfactor;
1005 u32 src_w, src_h, dst_w, dst_h;
1007 cfg_ext = fimc_read(EXYNOS_CITRGFMT);
1008 if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
1016 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
1024 ret = fimc_get_ratio_shift(src_w, dst_w, &pre_hratio, &hfactor);
1026 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
1030 ret = fimc_get_ratio_shift(src_h, dst_h, &pre_vratio, &vfactor);
1032 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
1036 pre_dst_width = src_w / pre_hratio;
1037 pre_dst_height = src_h / pre_vratio;
1038 DRM_DEBUG_KMS("%s:pre_dst_width[%d]pre_dst_height[%d]\n", __func__,
1039 pre_dst_width, pre_dst_height);
1040 DRM_DEBUG_KMS("%s:pre_hratio[%d]hfactor[%d]pre_vratio[%d]vfactor[%d]\n",
1041 __func__, pre_hratio, hfactor, pre_vratio, vfactor);
1043 sc->hratio = (src_w << 14) / (dst_w << hfactor);
1044 sc->vratio = (src_h << 14) / (dst_h << vfactor);
1045 sc->up_h = (dst_w >= src_w) ? true : false;
1046 sc->up_v = (dst_h >= src_h) ? true : false;
1047 DRM_DEBUG_KMS("%s:hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
1048 __func__, sc->hratio, sc->vratio, sc->up_h, sc->up_v);
1050 shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
1051 DRM_DEBUG_KMS("%s:shfactor[%d]\n", __func__, shfactor);
1053 cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
1054 EXYNOS_CISCPRERATIO_PREHORRATIO(pre_hratio) |
1055 EXYNOS_CISCPRERATIO_PREVERRATIO(pre_vratio));
1056 fimc_write(cfg, EXYNOS_CISCPRERATIO);
1058 cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1059 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1060 fimc_write(cfg, EXYNOS_CISCPREDST);
1065 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1069 DRM_DEBUG_KMS("%s:range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1070 __func__, sc->range, sc->bypass, sc->up_h, sc->up_v);
1071 DRM_DEBUG_KMS("%s:hratio[%d]vratio[%d]\n",
1072 __func__, sc->hratio, sc->vratio);
1074 cfg = fimc_read(EXYNOS_CISCCTRL);
1075 cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1076 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1077 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1078 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1079 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1080 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1083 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1084 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1086 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1088 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1090 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1092 cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1093 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1094 fimc_write(cfg, EXYNOS_CISCCTRL);
1096 cfg_ext = fimc_read(EXYNOS_CIEXTEN);
1097 cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1098 cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1099 cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1100 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1101 fimc_write(cfg_ext, EXYNOS_CIEXTEN);
1104 static int fimc_dst_set_size(struct device *dev, int swap,
1105 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1107 struct fimc_context *ctx = get_fimc_context(dev);
1108 struct drm_exynos_pos img_pos = *pos;
1109 struct drm_exynos_sz img_sz = *sz;
1112 DRM_DEBUG_KMS("%s:swap[%d]hsize[%d]vsize[%d]\n",
1113 __func__, swap, sz->hsize, sz->vsize);
1116 cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1117 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1119 fimc_write(cfg, EXYNOS_ORGOSIZE);
1121 DRM_DEBUG_KMS("%s:x[%d]y[%d]w[%d]h[%d]\n",
1122 __func__, pos->x, pos->y, pos->w, pos->h);
1125 cfg = fimc_read(EXYNOS_CIGCTRL);
1126 cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1128 if (sz->hsize >= FIMC_WIDTH_ITU_709)
1129 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1131 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1133 fimc_write(cfg, EXYNOS_CIGCTRL);
1138 img_sz.hsize = sz->vsize;
1139 img_sz.vsize = sz->hsize;
1142 /* target image size */
1143 cfg = fimc_read(EXYNOS_CITRGFMT);
1144 cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1145 EXYNOS_CITRGFMT_TARGETV_MASK);
1146 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1147 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1148 fimc_write(cfg, EXYNOS_CITRGFMT);
1151 cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1152 fimc_write(cfg, EXYNOS_CITAREA);
1154 /* offset Y(RGB), Cb, Cr */
1155 cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1156 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1157 fimc_write(cfg, EXYNOS_CIOYOFF);
1158 cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1159 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1160 fimc_write(cfg, EXYNOS_CIOCBOFF);
1161 cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1162 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1163 fimc_write(cfg, EXYNOS_CIOCROFF);
1168 static int fimc_dst_get_buf_seq(struct fimc_context *ctx)
1170 u32 cfg, i, buf_num = 0;
1171 u32 mask = 0x00000001;
1173 cfg = fimc_read(EXYNOS_CIFCNTSEQ);
1175 for (i = 0; i < FIMC_REG_SZ; i++)
1176 if (cfg & (mask << i))
1179 DRM_DEBUG_KMS("%s:buf_num[%d]\n", __func__, buf_num);
1184 static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1185 enum drm_exynos_ipp_buf_type buf_type)
1187 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1190 u32 mask = 0x00000001 << buf_id;
1193 DRM_DEBUG_KMS("%s:buf_id[%d]buf_type[%d]\n", __func__,
1196 mutex_lock(&ctx->lock);
1198 /* mask register set */
1199 cfg = fimc_read(EXYNOS_CIFCNTSEQ);
1202 case IPP_BUF_ENQUEUE:
1205 case IPP_BUF_DEQUEUE:
1209 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1216 cfg |= (enable << buf_id);
1217 fimc_write(cfg, EXYNOS_CIFCNTSEQ);
1219 /* interrupt enable */
1220 if (buf_type == IPP_BUF_ENQUEUE &&
1221 fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START)
1222 fimc_handle_irq(ctx, true, false, true);
1224 /* interrupt disable */
1225 if (buf_type == IPP_BUF_DEQUEUE &&
1226 fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP)
1227 fimc_handle_irq(ctx, false, false, true);
1230 mutex_unlock(&ctx->lock);
1234 static int fimc_dst_set_addr(struct device *dev,
1235 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1236 enum drm_exynos_ipp_buf_type buf_type)
1238 struct fimc_context *ctx = get_fimc_context(dev);
1239 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1240 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1241 struct drm_exynos_ipp_property *property;
1242 struct drm_exynos_ipp_config *config;
1245 DRM_ERROR("failed to get c_node.\n");
1249 property = &c_node->property;
1251 DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
1252 property->prop_id, buf_id, buf_type);
1254 if (buf_id > FIMC_MAX_DST) {
1255 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1259 /* address register set */
1261 case IPP_BUF_ENQUEUE:
1262 config = &property->config[EXYNOS_DRM_OPS_DST];
1264 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1265 EXYNOS_CIOYSA(buf_id));
1267 if (config->fmt == DRM_FORMAT_YVU420) {
1268 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1269 EXYNOS_CIOCBSA(buf_id));
1270 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1271 EXYNOS_CIOCRSA(buf_id));
1273 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1274 EXYNOS_CIOCBSA(buf_id));
1275 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1276 EXYNOS_CIOCRSA(buf_id));
1279 case IPP_BUF_DEQUEUE:
1280 fimc_write(0x0, EXYNOS_CIOYSA(buf_id));
1281 fimc_write(0x0, EXYNOS_CIOCBSA(buf_id));
1282 fimc_write(0x0, EXYNOS_CIOCRSA(buf_id));
1289 return fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1292 static struct exynos_drm_ipp_ops fimc_dst_ops = {
1293 .set_fmt = fimc_dst_set_fmt,
1294 .set_transf = fimc_dst_set_transf,
1295 .set_size = fimc_dst_set_size,
1296 .set_addr = fimc_dst_set_addr,
1299 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1301 DRM_DEBUG_KMS("%s:enable[%d]\n", __func__, enable);
1304 clk_enable(ctx->sclk_fimc_clk);
1305 clk_enable(ctx->fimc_clk);
1306 clk_enable(ctx->wb_clk);
1307 ctx->suspended = false;
1309 clk_disable(ctx->sclk_fimc_clk);
1310 clk_disable(ctx->fimc_clk);
1311 clk_disable(ctx->wb_clk);
1312 ctx->suspended = true;
1318 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1320 struct fimc_context *ctx = dev_id;
1321 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1322 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1323 struct drm_exynos_ipp_event_work *event_work =
1327 DRM_DEBUG_KMS("%s:fimc id[%d]\n", __func__, ctx->id);
1329 fimc_clear_irq(ctx);
1330 if (fimc_check_ovf(ctx))
1333 if (!fimc_check_frame_end(ctx))
1336 buf_id = fimc_get_buf_id(ctx);
1340 DRM_DEBUG_KMS("%s:buf_id[%d]\n", __func__, buf_id);
1342 if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) {
1343 DRM_ERROR("failed to dequeue.\n");
1347 event_work->ippdrv = ippdrv;
1348 event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1349 queue_work(ippdrv->event_workq, (struct work_struct *)event_work);
1354 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1356 struct drm_exynos_ipp_prop_list *prop_list;
1358 DRM_DEBUG_KMS("%s\n", __func__);
1360 prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL);
1362 DRM_ERROR("failed to alloc property list.\n");
1366 prop_list->version = 1;
1367 prop_list->writeback = 1;
1368 prop_list->refresh_min = FIMC_REFRESH_MIN;
1369 prop_list->refresh_max = FIMC_REFRESH_MAX;
1370 prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1371 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1372 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1373 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1374 (1 << EXYNOS_DRM_DEGREE_90) |
1375 (1 << EXYNOS_DRM_DEGREE_180) |
1376 (1 << EXYNOS_DRM_DEGREE_270);
1378 prop_list->crop = 1;
1379 prop_list->crop_max.hsize = FIMC_CROP_MAX;
1380 prop_list->crop_max.vsize = FIMC_CROP_MAX;
1381 prop_list->crop_min.hsize = FIMC_CROP_MIN;
1382 prop_list->crop_min.vsize = FIMC_CROP_MIN;
1383 prop_list->scale = 1;
1384 prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1385 prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1386 prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1387 prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1389 ippdrv->prop_list = prop_list;
1394 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1397 case EXYNOS_DRM_FLIP_NONE:
1398 case EXYNOS_DRM_FLIP_VERTICAL:
1399 case EXYNOS_DRM_FLIP_HORIZONTAL:
1400 case EXYNOS_DRM_FLIP_BOTH:
1403 DRM_DEBUG_KMS("%s:invalid flip\n", __func__);
1408 static int fimc_ippdrv_check_property(struct device *dev,
1409 struct drm_exynos_ipp_property *property)
1411 struct fimc_context *ctx = get_fimc_context(dev);
1412 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1413 struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list;
1414 struct drm_exynos_ipp_config *config;
1415 struct drm_exynos_pos *pos;
1416 struct drm_exynos_sz *sz;
1420 DRM_DEBUG_KMS("%s\n", __func__);
1422 for_each_ipp_ops(i) {
1423 if ((i == EXYNOS_DRM_OPS_SRC) &&
1424 (property->cmd == IPP_CMD_WB))
1427 config = &property->config[i];
1431 /* check for flip */
1432 if (!fimc_check_drm_flip(config->flip)) {
1433 DRM_ERROR("invalid flip.\n");
1437 /* check for degree */
1438 switch (config->degree) {
1439 case EXYNOS_DRM_DEGREE_90:
1440 case EXYNOS_DRM_DEGREE_270:
1443 case EXYNOS_DRM_DEGREE_0:
1444 case EXYNOS_DRM_DEGREE_180:
1448 DRM_ERROR("invalid degree.\n");
1452 /* check for buffer bound */
1453 if ((pos->x + pos->w > sz->hsize) ||
1454 (pos->y + pos->h > sz->vsize)) {
1455 DRM_ERROR("out of buf bound.\n");
1459 /* check for crop */
1460 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1462 if ((pos->h < pp->crop_min.hsize) ||
1463 (sz->vsize > pp->crop_max.hsize) ||
1464 (pos->w < pp->crop_min.vsize) ||
1465 (sz->hsize > pp->crop_max.vsize)) {
1466 DRM_ERROR("out of crop size.\n");
1470 if ((pos->w < pp->crop_min.hsize) ||
1471 (sz->hsize > pp->crop_max.hsize) ||
1472 (pos->h < pp->crop_min.vsize) ||
1473 (sz->vsize > pp->crop_max.vsize)) {
1474 DRM_ERROR("out of crop size.\n");
1480 /* check for scale */
1481 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1483 if ((pos->h < pp->scale_min.hsize) ||
1484 (sz->vsize > pp->scale_max.hsize) ||
1485 (pos->w < pp->scale_min.vsize) ||
1486 (sz->hsize > pp->scale_max.vsize)) {
1487 DRM_ERROR("out of scale size.\n");
1491 if ((pos->w < pp->scale_min.hsize) ||
1492 (sz->hsize > pp->scale_max.hsize) ||
1493 (pos->h < pp->scale_min.vsize) ||
1494 (sz->vsize > pp->scale_max.vsize)) {
1495 DRM_ERROR("out of scale size.\n");
1505 for_each_ipp_ops(i) {
1506 if ((i == EXYNOS_DRM_OPS_SRC) &&
1507 (property->cmd == IPP_CMD_WB))
1510 config = &property->config[i];
1514 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1515 i ? "dst" : "src", config->flip, config->degree,
1516 pos->x, pos->y, pos->w, pos->h,
1517 sz->hsize, sz->vsize);
1523 static void fimc_clear_addr(struct fimc_context *ctx)
1527 DRM_DEBUG_KMS("%s:\n", __func__);
1529 for (i = 0; i < FIMC_MAX_SRC; i++) {
1530 fimc_write(0, EXYNOS_CIIYSA(i));
1531 fimc_write(0, EXYNOS_CIICBSA(i));
1532 fimc_write(0, EXYNOS_CIICRSA(i));
1535 for (i = 0; i < FIMC_MAX_DST; i++) {
1536 fimc_write(0, EXYNOS_CIOYSA(i));
1537 fimc_write(0, EXYNOS_CIOCBSA(i));
1538 fimc_write(0, EXYNOS_CIOCRSA(i));
1542 static int fimc_ippdrv_reset(struct device *dev)
1544 struct fimc_context *ctx = get_fimc_context(dev);
1546 DRM_DEBUG_KMS("%s\n", __func__);
1548 /* reset h/w block */
1551 /* reset scaler capability */
1552 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1554 fimc_clear_addr(ctx);
1559 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1561 struct fimc_context *ctx = get_fimc_context(dev);
1562 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1563 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1564 struct drm_exynos_ipp_property *property;
1565 struct drm_exynos_ipp_config *config;
1566 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1567 struct drm_exynos_ipp_set_wb set_wb;
1571 DRM_DEBUG_KMS("%s:cmd[%d]\n", __func__, cmd);
1574 DRM_ERROR("failed to get c_node.\n");
1578 property = &c_node->property;
1580 fimc_handle_irq(ctx, true, false, true);
1582 for_each_ipp_ops(i) {
1583 config = &property->config[i];
1584 img_pos[i] = config->pos;
1587 ret = fimc_set_prescaler(ctx, &ctx->sc,
1588 &img_pos[EXYNOS_DRM_OPS_SRC],
1589 &img_pos[EXYNOS_DRM_OPS_DST]);
1591 dev_err(dev, "failed to set precalser.\n");
1595 /* If set ture, we can save jpeg about screen */
1596 fimc_handle_jpeg(ctx, false);
1597 fimc_set_scaler(ctx, &ctx->sc);
1598 fimc_set_polarity(ctx, &ctx->pol);
1602 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1603 fimc_handle_lastend(ctx, false);
1606 cfg0 = fimc_read(EXYNOS_MSCTRL);
1607 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1608 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1609 fimc_write(cfg0, EXYNOS_MSCTRL);
1612 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1613 fimc_handle_lastend(ctx, true);
1616 fimc_set_camblk_fimd0_wb(ctx);
1619 set_wb.refresh = property->refresh_rate;
1620 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1622 case IPP_CMD_OUTPUT:
1625 dev_err(dev, "invalid operations.\n");
1630 fimc_write(0x0, EXYNOS_CISTATUS);
1632 cfg0 = fimc_read(EXYNOS_CIIMGCPT);
1633 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1634 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1637 cfg1 = fimc_read(EXYNOS_CISCCTRL);
1638 cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1639 cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1640 EXYNOS_CISCCTRL_SCALERSTART);
1642 fimc_write(cfg1, EXYNOS_CISCCTRL);
1644 /* Enable image capture*/
1645 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1646 fimc_write(cfg0, EXYNOS_CIIMGCPT);
1648 /* Disable frame end irq */
1649 cfg0 = fimc_read(EXYNOS_CIGCTRL);
1650 cfg0 &= ~EXYNOS_CIGCTRL_IRQ_END_DISABLE;
1651 fimc_write(cfg0, EXYNOS_CIGCTRL);
1653 cfg0 = fimc_read(EXYNOS_CIOCTRL);
1654 cfg0 &= ~EXYNOS_CIOCTRL_WEAVE_MASK;
1655 fimc_write(cfg0, EXYNOS_CIOCTRL);
1657 if (cmd == IPP_CMD_M2M) {
1658 cfg0 = fimc_read(EXYNOS_MSCTRL);
1659 cfg0 |= EXYNOS_MSCTRL_ENVID;
1660 fimc_write(cfg0, EXYNOS_MSCTRL);
1662 cfg0 = fimc_read(EXYNOS_MSCTRL);
1663 cfg0 |= EXYNOS_MSCTRL_ENVID;
1664 fimc_write(cfg0, EXYNOS_MSCTRL);
1670 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1672 struct fimc_context *ctx = get_fimc_context(dev);
1673 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1676 DRM_DEBUG_KMS("%s:cmd[%d]\n", __func__, cmd);
1681 cfg = fimc_read(EXYNOS_MSCTRL);
1682 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1683 cfg &= ~EXYNOS_MSCTRL_ENVID;
1684 fimc_write(cfg, EXYNOS_MSCTRL);
1687 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1689 case IPP_CMD_OUTPUT:
1691 dev_err(dev, "invalid operations.\n");
1695 fimc_handle_irq(ctx, false, false, true);
1697 /* reset sequence */
1698 fimc_write(0x0, EXYNOS_CIFCNTSEQ);
1700 /* Scaler disable */
1701 cfg = fimc_read(EXYNOS_CISCCTRL);
1702 cfg &= ~EXYNOS_CISCCTRL_SCALERSTART;
1703 fimc_write(cfg, EXYNOS_CISCCTRL);
1705 /* Disable image capture */
1706 cfg = fimc_read(EXYNOS_CIIMGCPT);
1707 cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1708 fimc_write(cfg, EXYNOS_CIIMGCPT);
1710 /* Enable frame end irq */
1711 cfg = fimc_read(EXYNOS_CIGCTRL);
1712 cfg |= EXYNOS_CIGCTRL_IRQ_END_DISABLE;
1713 fimc_write(cfg, EXYNOS_CIGCTRL);
1716 static int __devinit fimc_probe(struct platform_device *pdev)
1718 struct device *dev = &pdev->dev;
1719 struct fimc_context *ctx;
1720 struct clk *parent_clk;
1721 struct resource *res;
1722 struct exynos_drm_ippdrv *ippdrv;
1723 struct exynos_drm_fimc_pdata *pdata;
1724 struct fimc_driverdata *ddata;
1727 pdata = pdev->dev.platform_data;
1729 dev_err(dev, "no platform data specified.\n");
1733 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1737 ddata = (struct fimc_driverdata *)
1738 platform_get_device_id(pdev)->driver_data;
1741 ctx->sclk_fimc_clk = clk_get(dev, "sclk_fimc");
1742 if (IS_ERR(ctx->sclk_fimc_clk)) {
1743 dev_err(dev, "failed to get src fimc clock.\n");
1744 ret = PTR_ERR(ctx->sclk_fimc_clk);
1747 clk_enable(ctx->sclk_fimc_clk);
1749 ctx->fimc_clk = clk_get(dev, "fimc");
1750 if (IS_ERR(ctx->fimc_clk)) {
1751 dev_err(dev, "failed to get fimc clock.\n");
1752 ret = PTR_ERR(ctx->fimc_clk);
1753 clk_disable(ctx->sclk_fimc_clk);
1754 clk_put(ctx->sclk_fimc_clk);
1758 ctx->wb_clk = clk_get(dev, "pxl_async0");
1759 if (IS_ERR(ctx->wb_clk)) {
1760 dev_err(dev, "failed to get writeback a clock.\n");
1761 ret = PTR_ERR(ctx->wb_clk);
1762 clk_disable(ctx->sclk_fimc_clk);
1763 clk_put(ctx->sclk_fimc_clk);
1764 clk_put(ctx->fimc_clk);
1768 ctx->wb_b_clk = clk_get(dev, "pxl_async1");
1769 if (IS_ERR(ctx->wb_b_clk)) {
1770 dev_err(dev, "failed to get writeback b clock.\n");
1771 ret = PTR_ERR(ctx->wb_b_clk);
1772 clk_disable(ctx->sclk_fimc_clk);
1773 clk_put(ctx->sclk_fimc_clk);
1774 clk_put(ctx->fimc_clk);
1775 clk_put(ctx->wb_clk);
1779 parent_clk = clk_get(dev, ddata->parent_clk);
1781 if (IS_ERR(parent_clk)) {
1782 dev_err(dev, "failed to get parent clock.\n");
1783 ret = PTR_ERR(parent_clk);
1784 clk_disable(ctx->sclk_fimc_clk);
1785 clk_put(ctx->sclk_fimc_clk);
1786 clk_put(ctx->fimc_clk);
1787 clk_put(ctx->wb_clk);
1788 clk_put(ctx->wb_b_clk);
1792 if (clk_set_parent(ctx->sclk_fimc_clk, parent_clk)) {
1793 dev_err(dev, "failed to set parent.\n");
1795 clk_put(parent_clk);
1796 clk_disable(ctx->sclk_fimc_clk);
1797 clk_put(ctx->sclk_fimc_clk);
1798 clk_put(ctx->fimc_clk);
1799 clk_put(ctx->wb_clk);
1800 clk_put(ctx->wb_b_clk);
1804 clk_put(parent_clk);
1805 clk_set_rate(ctx->sclk_fimc_clk, pdata->clk_rate);
1807 /* resource memory */
1808 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1809 if (!ctx->regs_res) {
1810 dev_err(dev, "failed to find registers.\n");
1815 ctx->regs = devm_request_and_ioremap(dev, ctx->regs_res);
1817 dev_err(dev, "failed to map registers.\n");
1823 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1825 dev_err(dev, "failed to request irq resource.\n");
1830 ctx->irq = res->start;
1831 ret = request_threaded_irq(ctx->irq, NULL, fimc_irq_handler,
1832 IRQF_ONESHOT, "drm_fimc", ctx);
1834 dev_err(dev, "failed to request irq.\n");
1838 /* context initailization */
1840 ctx->pol = pdata->pol;
1843 ippdrv = &ctx->ippdrv;
1845 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1846 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1847 ippdrv->check_property = fimc_ippdrv_check_property;
1848 ippdrv->reset = fimc_ippdrv_reset;
1849 ippdrv->start = fimc_ippdrv_start;
1850 ippdrv->stop = fimc_ippdrv_stop;
1851 ret = fimc_init_prop_list(ippdrv);
1853 dev_err(dev, "failed to init property list.\n");
1857 DRM_DEBUG_KMS("%s:id[%d]ippdrv[0x%x]\n", __func__, ctx->id,
1860 mutex_init(&ctx->lock);
1861 platform_set_drvdata(pdev, ctx);
1863 pm_runtime_set_active(dev);
1864 pm_runtime_enable(dev);
1866 ret = exynos_drm_ippdrv_register(ippdrv);
1868 dev_err(dev, "failed to register drm fimc device.\n");
1869 goto err_ippdrv_register;
1872 dev_info(&pdev->dev, "drm fimc registered successfully.\n");
1876 err_ippdrv_register:
1877 devm_kfree(dev, ippdrv->prop_list);
1878 pm_runtime_disable(dev);
1880 free_irq(ctx->irq, ctx);
1882 devm_iounmap(dev, ctx->regs);
1884 clk_put(ctx->sclk_fimc_clk);
1885 clk_put(ctx->fimc_clk);
1886 clk_put(ctx->wb_clk);
1887 clk_put(ctx->wb_b_clk);
1889 devm_kfree(dev, ctx);
1893 static int __devexit fimc_remove(struct platform_device *pdev)
1895 struct device *dev = &pdev->dev;
1896 struct fimc_context *ctx = get_fimc_context(dev);
1897 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1899 devm_kfree(dev, ippdrv->prop_list);
1900 exynos_drm_ippdrv_unregister(ippdrv);
1901 mutex_destroy(&ctx->lock);
1903 pm_runtime_set_suspended(dev);
1904 pm_runtime_disable(dev);
1906 free_irq(ctx->irq, ctx);
1907 devm_iounmap(dev, ctx->regs);
1909 clk_put(ctx->sclk_fimc_clk);
1910 clk_put(ctx->fimc_clk);
1911 clk_put(ctx->wb_clk);
1912 clk_put(ctx->wb_b_clk);
1914 devm_kfree(dev, ctx);
1919 #ifdef CONFIG_PM_SLEEP
1920 static int fimc_suspend(struct device *dev)
1922 struct fimc_context *ctx = get_fimc_context(dev);
1924 DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
1926 if (pm_runtime_suspended(dev))
1929 return fimc_clk_ctrl(ctx, false);
1932 static int fimc_resume(struct device *dev)
1934 struct fimc_context *ctx = get_fimc_context(dev);
1936 DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
1938 if (!pm_runtime_suspended(dev))
1939 return fimc_clk_ctrl(ctx, true);
1945 #ifdef CONFIG_PM_RUNTIME
1946 static int fimc_runtime_suspend(struct device *dev)
1948 struct fimc_context *ctx = get_fimc_context(dev);
1950 DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
1952 return fimc_clk_ctrl(ctx, false);
1955 static int fimc_runtime_resume(struct device *dev)
1957 struct fimc_context *ctx = get_fimc_context(dev);
1959 DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id);
1961 return fimc_clk_ctrl(ctx, true);
1965 static struct fimc_driverdata exynos4210_fimc_data = {
1966 .parent_clk = "mout_mpll",
1969 static struct fimc_driverdata exynos4410_fimc_data = {
1970 .parent_clk = "mout_mpll_user",
1973 static struct platform_device_id fimc_driver_ids[] = {
1975 .name = "exynos4210-fimc",
1976 .driver_data = (unsigned long)&exynos4210_fimc_data,
1978 .name = "exynos4412-fimc",
1979 .driver_data = (unsigned long)&exynos4410_fimc_data,
1983 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1985 static const struct dev_pm_ops fimc_pm_ops = {
1986 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1987 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1990 struct platform_driver fimc_driver = {
1991 .probe = fimc_probe,
1992 .remove = __devexit_p(fimc_remove),
1993 .id_table = fimc_driver_ids,
1995 .name = "exynos-drm-fimc",
1996 .owner = THIS_MODULE,