1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <drm/exynos_drm.h>
17 #include <linux/clk.h>
18 #include <linux/component.h>
19 #include <linux/kernel.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/exynos7_decon.h>
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_plane.h"
32 #include "exynos_drm_drv.h"
33 #include "exynos_drm_fb.h"
34 #include "exynos_drm_iommu.h"
37 * DECON stands for Display and Enhancement controller.
40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
44 struct decon_context {
46 struct drm_device *drm_dev;
47 struct exynos_drm_crtc *crtc;
48 struct exynos_drm_plane planes[WINDOWS_NR];
49 struct exynos_drm_plane_config configs[WINDOWS_NR];
55 unsigned long irq_flags;
59 wait_queue_head_t wait_vsync_queue;
60 atomic_t wait_vsync_event;
62 struct drm_encoder *encoder;
65 static const struct of_device_id decon_driver_dt_match[] = {
66 {.compatible = "samsung,exynos7-decon"},
69 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
71 static const uint32_t decon_formats[] = {
83 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
84 DRM_PLANE_TYPE_PRIMARY,
85 DRM_PLANE_TYPE_CURSOR,
88 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
90 struct decon_context *ctx = crtc->ctx;
95 atomic_set(&ctx->wait_vsync_event, 1);
98 * wait for DECON to signal VSYNC interrupt or return after
99 * timeout which is set to 50ms (refresh rate of 20).
101 if (!wait_event_timeout(ctx->wait_vsync_queue,
102 !atomic_read(&ctx->wait_vsync_event),
104 DRM_DEBUG_KMS("vblank wait timed out.\n");
107 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
109 struct decon_context *ctx = crtc->ctx;
110 unsigned int win, ch_enabled = 0;
112 DRM_DEBUG_KMS("%s\n", __FILE__);
114 /* Check if any channel is enabled. */
115 for (win = 0; win < WINDOWS_NR; win++) {
116 u32 val = readl(ctx->regs + WINCON(win));
118 if (val & WINCONx_ENWIN) {
119 val &= ~WINCONx_ENWIN;
120 writel(val, ctx->regs + WINCON(win));
125 /* Wait for vsync, as disable channel takes effect at next vsync */
127 decon_wait_for_vblank(ctx->crtc);
130 static int decon_ctx_initialize(struct decon_context *ctx,
131 struct drm_device *drm_dev)
133 ctx->drm_dev = drm_dev;
134 ctx->pipe = drm_dev->mode_config.num_crtc;
136 decon_clear_channels(ctx->crtc);
138 return drm_iommu_attach_device(drm_dev, ctx->dev);
141 static void decon_ctx_remove(struct decon_context *ctx)
143 /* detach this sub driver from iommu mapping if supported. */
144 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
147 static u32 decon_calc_clkdiv(struct decon_context *ctx,
148 const struct drm_display_mode *mode)
150 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
153 /* Find the clock divider value that gets us closest to ideal_clk */
154 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
156 return (clkdiv < 0x100) ? clkdiv : 0xff;
159 static void decon_commit(struct exynos_drm_crtc *crtc)
161 struct decon_context *ctx = crtc->ctx;
162 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
168 /* nothing to do if we haven't set the mode yet */
169 if (mode->htotal == 0 || mode->vtotal == 0)
173 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
174 /* setup vertical timing values. */
175 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
176 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
177 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
179 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
180 writel(val, ctx->regs + VIDTCON0);
182 val = VIDTCON1_VSPW(vsync_len - 1);
183 writel(val, ctx->regs + VIDTCON1);
185 /* setup horizontal timing values. */
186 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
187 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
188 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
190 /* setup horizontal timing values. */
191 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
192 writel(val, ctx->regs + VIDTCON2);
194 val = VIDTCON3_HSPW(hsync_len - 1);
195 writel(val, ctx->regs + VIDTCON3);
198 /* setup horizontal and vertical display size. */
199 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
200 VIDTCON4_HOZVAL(mode->hdisplay - 1);
201 writel(val, ctx->regs + VIDTCON4);
203 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
206 * fields of register with prefix '_F' would be updated
207 * at vsync(same as dma start)
209 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
210 writel(val, ctx->regs + VIDCON0);
212 clkdiv = decon_calc_clkdiv(ctx, mode);
214 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
215 writel(val, ctx->regs + VCLKCON1);
216 writel(val, ctx->regs + VCLKCON2);
219 val = readl(ctx->regs + DECON_UPDATE);
220 val |= DECON_UPDATE_STANDALONE_F;
221 writel(val, ctx->regs + DECON_UPDATE);
224 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
226 struct decon_context *ctx = crtc->ctx;
232 if (!test_and_set_bit(0, &ctx->irq_flags)) {
233 val = readl(ctx->regs + VIDINTCON0);
235 val |= VIDINTCON0_INT_ENABLE;
238 val |= VIDINTCON0_INT_FRAME;
239 val &= ~VIDINTCON0_FRAMESEL0_MASK;
240 val |= VIDINTCON0_FRAMESEL0_VSYNC;
243 writel(val, ctx->regs + VIDINTCON0);
249 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
251 struct decon_context *ctx = crtc->ctx;
257 if (test_and_clear_bit(0, &ctx->irq_flags)) {
258 val = readl(ctx->regs + VIDINTCON0);
260 val &= ~VIDINTCON0_INT_ENABLE;
262 val &= ~VIDINTCON0_INT_FRAME;
264 writel(val, ctx->regs + VIDINTCON0);
268 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
269 struct drm_framebuffer *fb)
274 val = readl(ctx->regs + WINCON(win));
275 val &= ~WINCONx_BPPMODE_MASK;
277 switch (fb->format->format) {
278 case DRM_FORMAT_RGB565:
279 val |= WINCONx_BPPMODE_16BPP_565;
280 val |= WINCONx_BURSTLEN_16WORD;
282 case DRM_FORMAT_XRGB8888:
283 val |= WINCONx_BPPMODE_24BPP_xRGB;
284 val |= WINCONx_BURSTLEN_16WORD;
286 case DRM_FORMAT_XBGR8888:
287 val |= WINCONx_BPPMODE_24BPP_xBGR;
288 val |= WINCONx_BURSTLEN_16WORD;
290 case DRM_FORMAT_RGBX8888:
291 val |= WINCONx_BPPMODE_24BPP_RGBx;
292 val |= WINCONx_BURSTLEN_16WORD;
294 case DRM_FORMAT_BGRX8888:
295 val |= WINCONx_BPPMODE_24BPP_BGRx;
296 val |= WINCONx_BURSTLEN_16WORD;
298 case DRM_FORMAT_ARGB8888:
299 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
301 val |= WINCONx_BURSTLEN_16WORD;
303 case DRM_FORMAT_ABGR8888:
304 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
306 val |= WINCONx_BURSTLEN_16WORD;
308 case DRM_FORMAT_RGBA8888:
309 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
311 val |= WINCONx_BURSTLEN_16WORD;
313 case DRM_FORMAT_BGRA8888:
314 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
316 val |= WINCONx_BURSTLEN_16WORD;
319 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
321 val |= WINCONx_BPPMODE_24BPP_xRGB;
322 val |= WINCONx_BURSTLEN_16WORD;
326 DRM_DEBUG_KMS("bpp = %d\n", fb->format->cpp[0] * 8);
329 * In case of exynos, setting dma-burst to 16Word causes permanent
330 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
331 * switching which is based on plane size is not recommended as
332 * plane size varies a lot towards the end of the screen and rapid
333 * movement causes unstable DMA which results into iommu crash/tear.
336 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;
337 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
338 val &= ~WINCONx_BURSTLEN_MASK;
339 val |= WINCONx_BURSTLEN_8WORD;
342 writel(val, ctx->regs + WINCON(win));
345 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
347 unsigned int keycon0 = 0, keycon1 = 0;
349 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
350 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
352 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
354 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
355 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
359 * shadow_protect_win() - disable updating values from shadow registers at vsync
361 * @win: window to protect registers for
362 * @protect: 1 to protect (disable updates)
364 static void decon_shadow_protect_win(struct decon_context *ctx,
365 unsigned int win, bool protect)
369 bits = SHADOWCON_WINx_PROTECT(win);
371 val = readl(ctx->regs + SHADOWCON);
376 writel(val, ctx->regs + SHADOWCON);
379 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
381 struct decon_context *ctx = crtc->ctx;
387 for (i = 0; i < WINDOWS_NR; i++)
388 decon_shadow_protect_win(ctx, i, true);
391 static void decon_update_plane(struct exynos_drm_crtc *crtc,
392 struct exynos_drm_plane *plane)
394 struct exynos_drm_plane_state *state =
395 to_exynos_plane_state(plane->base.state);
396 struct decon_context *ctx = crtc->ctx;
397 struct drm_framebuffer *fb = state->base.fb;
399 unsigned long val, alpha;
402 unsigned int win = plane->index;
403 unsigned int bpp = fb->format->cpp[0];
404 unsigned int pitch = fb->pitches[0];
410 * SHADOWCON/PRTCON register is used for enabling timing.
412 * for example, once only width value of a register is set,
413 * if the dma is started then decon hardware could malfunction so
414 * with protect window setting, the register fields with prefix '_F'
415 * wouldn't be updated at vsync also but updated once unprotect window
419 /* buffer start address */
420 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
421 writel(val, ctx->regs + VIDW_BUF_START(win));
423 padding = (pitch / bpp) - fb->width;
426 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
427 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
429 /* offset from the start of the buffer to read */
430 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
431 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
433 DRM_DEBUG_KMS("start addr = 0x%lx\n",
435 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
436 state->crtc.w, state->crtc.h);
438 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
439 VIDOSDxA_TOPLEFT_Y(state->crtc.y);
440 writel(val, ctx->regs + VIDOSD_A(win));
442 last_x = state->crtc.x + state->crtc.w;
445 last_y = state->crtc.y + state->crtc.h;
449 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
451 writel(val, ctx->regs + VIDOSD_B(win));
453 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
454 state->crtc.x, state->crtc.y, last_x, last_y);
457 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
458 VIDOSDxC_ALPHA0_G_F(0x0) |
459 VIDOSDxC_ALPHA0_B_F(0x0);
461 writel(alpha, ctx->regs + VIDOSD_C(win));
463 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
464 VIDOSDxD_ALPHA1_G_F(0xff) |
465 VIDOSDxD_ALPHA1_B_F(0xff);
467 writel(alpha, ctx->regs + VIDOSD_D(win));
469 decon_win_set_pixfmt(ctx, win, fb);
471 /* hardware window 0 doesn't support color key. */
473 decon_win_set_colkey(ctx, win);
476 val = readl(ctx->regs + WINCON(win));
477 val |= WINCONx_TRIPLE_BUF_MODE;
478 val |= WINCONx_ENWIN;
479 writel(val, ctx->regs + WINCON(win));
481 /* Enable DMA channel and unprotect windows */
482 decon_shadow_protect_win(ctx, win, false);
484 val = readl(ctx->regs + DECON_UPDATE);
485 val |= DECON_UPDATE_STANDALONE_F;
486 writel(val, ctx->regs + DECON_UPDATE);
489 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
490 struct exynos_drm_plane *plane)
492 struct decon_context *ctx = crtc->ctx;
493 unsigned int win = plane->index;
499 /* protect windows */
500 decon_shadow_protect_win(ctx, win, true);
503 val = readl(ctx->regs + WINCON(win));
504 val &= ~WINCONx_ENWIN;
505 writel(val, ctx->regs + WINCON(win));
507 val = readl(ctx->regs + DECON_UPDATE);
508 val |= DECON_UPDATE_STANDALONE_F;
509 writel(val, ctx->regs + DECON_UPDATE);
512 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
514 struct decon_context *ctx = crtc->ctx;
520 for (i = 0; i < WINDOWS_NR; i++)
521 decon_shadow_protect_win(ctx, i, false);
522 exynos_crtc_handle_event(crtc);
525 static void decon_init(struct decon_context *ctx)
529 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
531 val = VIDOUTCON0_DISP_IF_0_ON;
533 val |= VIDOUTCON0_RGBIF;
534 writel(val, ctx->regs + VIDOUTCON0);
536 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
539 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
542 static void decon_enable(struct exynos_drm_crtc *crtc)
544 struct decon_context *ctx = crtc->ctx;
549 pm_runtime_get_sync(ctx->dev);
553 /* if vblank was enabled status, enable it again. */
554 if (test_and_clear_bit(0, &ctx->irq_flags))
555 decon_enable_vblank(ctx->crtc);
557 decon_commit(ctx->crtc);
559 ctx->suspended = false;
562 static void decon_disable(struct exynos_drm_crtc *crtc)
564 struct decon_context *ctx = crtc->ctx;
571 * We need to make sure that all windows are disabled before we
572 * suspend that connector. Otherwise we might try to scan from
573 * a destroyed buffer later.
575 for (i = 0; i < WINDOWS_NR; i++)
576 decon_disable_plane(crtc, &ctx->planes[i]);
578 pm_runtime_put_sync(ctx->dev);
580 ctx->suspended = true;
583 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
584 .enable = decon_enable,
585 .disable = decon_disable,
586 .commit = decon_commit,
587 .enable_vblank = decon_enable_vblank,
588 .disable_vblank = decon_disable_vblank,
589 .atomic_begin = decon_atomic_begin,
590 .update_plane = decon_update_plane,
591 .disable_plane = decon_disable_plane,
592 .atomic_flush = decon_atomic_flush,
596 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
598 struct decon_context *ctx = (struct decon_context *)dev_id;
601 val = readl(ctx->regs + VIDINTCON1);
603 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
605 writel(clear_bit, ctx->regs + VIDINTCON1);
607 /* check the crtc is detached already from encoder */
608 if (ctx->pipe < 0 || !ctx->drm_dev)
612 drm_crtc_handle_vblank(&ctx->crtc->base);
614 /* set wait vsync event to zero and wake up queue. */
615 if (atomic_read(&ctx->wait_vsync_event)) {
616 atomic_set(&ctx->wait_vsync_event, 0);
617 wake_up(&ctx->wait_vsync_queue);
624 static int decon_bind(struct device *dev, struct device *master, void *data)
626 struct decon_context *ctx = dev_get_drvdata(dev);
627 struct drm_device *drm_dev = data;
628 struct exynos_drm_plane *exynos_plane;
632 ret = decon_ctx_initialize(ctx, drm_dev);
634 DRM_ERROR("decon_ctx_initialize failed.\n");
638 for (i = 0; i < WINDOWS_NR; i++) {
639 ctx->configs[i].pixel_formats = decon_formats;
640 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
641 ctx->configs[i].zpos = i;
642 ctx->configs[i].type = decon_win_types[i];
644 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
650 exynos_plane = &ctx->planes[DEFAULT_WIN];
651 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
652 EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx);
653 if (IS_ERR(ctx->crtc)) {
654 decon_ctx_remove(ctx);
655 return PTR_ERR(ctx->crtc);
659 exynos_dpi_bind(drm_dev, ctx->encoder);
665 static void decon_unbind(struct device *dev, struct device *master,
668 struct decon_context *ctx = dev_get_drvdata(dev);
670 decon_disable(ctx->crtc);
673 exynos_dpi_remove(ctx->encoder);
675 decon_ctx_remove(ctx);
678 static const struct component_ops decon_component_ops = {
680 .unbind = decon_unbind,
683 static int decon_probe(struct platform_device *pdev)
685 struct device *dev = &pdev->dev;
686 struct decon_context *ctx;
687 struct device_node *i80_if_timings;
688 struct resource *res;
694 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
699 ctx->suspended = true;
701 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
704 of_node_put(i80_if_timings);
706 ctx->regs = of_iomap(dev->of_node, 0);
710 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
711 if (IS_ERR(ctx->pclk)) {
712 dev_err(dev, "failed to get bus clock pclk\n");
713 ret = PTR_ERR(ctx->pclk);
717 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
718 if (IS_ERR(ctx->aclk)) {
719 dev_err(dev, "failed to get bus clock aclk\n");
720 ret = PTR_ERR(ctx->aclk);
724 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
725 if (IS_ERR(ctx->eclk)) {
726 dev_err(dev, "failed to get eclock\n");
727 ret = PTR_ERR(ctx->eclk);
731 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
732 if (IS_ERR(ctx->vclk)) {
733 dev_err(dev, "failed to get vclock\n");
734 ret = PTR_ERR(ctx->vclk);
738 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
739 ctx->i80_if ? "lcd_sys" : "vsync");
741 dev_err(dev, "irq request failed.\n");
746 ret = devm_request_irq(dev, res->start, decon_irq_handler,
747 0, "drm_decon", ctx);
749 dev_err(dev, "irq request failed.\n");
753 init_waitqueue_head(&ctx->wait_vsync_queue);
754 atomic_set(&ctx->wait_vsync_event, 0);
756 platform_set_drvdata(pdev, ctx);
758 ctx->encoder = exynos_dpi_probe(dev);
759 if (IS_ERR(ctx->encoder)) {
760 ret = PTR_ERR(ctx->encoder);
764 pm_runtime_enable(dev);
766 ret = component_add(dev, &decon_component_ops);
768 goto err_disable_pm_runtime;
772 err_disable_pm_runtime:
773 pm_runtime_disable(dev);
781 static int decon_remove(struct platform_device *pdev)
783 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
785 pm_runtime_disable(&pdev->dev);
789 component_del(&pdev->dev, &decon_component_ops);
795 static int exynos7_decon_suspend(struct device *dev)
797 struct decon_context *ctx = dev_get_drvdata(dev);
799 clk_disable_unprepare(ctx->vclk);
800 clk_disable_unprepare(ctx->eclk);
801 clk_disable_unprepare(ctx->aclk);
802 clk_disable_unprepare(ctx->pclk);
807 static int exynos7_decon_resume(struct device *dev)
809 struct decon_context *ctx = dev_get_drvdata(dev);
812 ret = clk_prepare_enable(ctx->pclk);
814 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
818 ret = clk_prepare_enable(ctx->aclk);
820 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
824 ret = clk_prepare_enable(ctx->eclk);
826 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
830 ret = clk_prepare_enable(ctx->vclk);
832 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
840 static const struct dev_pm_ops exynos7_decon_pm_ops = {
841 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
845 struct platform_driver decon_driver = {
846 .probe = decon_probe,
847 .remove = decon_remove,
849 .name = "exynos-decon",
850 .pm = &exynos7_decon_pm_ops,
851 .of_match_table = decon_driver_dt_match,