drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21
  22 #include <video/exynos5433_decon.h>
  23
  24 #include "exynos_drm_drv.h"
  25 #include "exynos_drm_crtc.h"
  26 #include "exynos_drm_fb.h"
  27 #include "exynos_drm_plane.h"
  28 #include "exynos_drm_iommu.h"
  29
  30 #define DSD_CFG_MUX 0x1004
  31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  32
  33 #define WINDOWS_NR      3
  34 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  35
  36 #define IFTYPE_I80      (1 << 0)
  37 #define I80_HW_TRG      (1 << 1)
  38 #define IFTYPE_HDMI     (1 << 2)
  39
  40 static const char * const decon_clks_name[] = {
  41         "pclk",
  42         "aclk_decon",
  43         "aclk_smmu_decon0x",
  44         "aclk_xiu_decon0x",
  45         "pclk_smmu_decon0x",
  46         "sclk_decon_vclk",
  47         "sclk_decon_eclk",
  48 };
  49
  50 enum decon_flag_bits {
  51         BIT_CLKS_ENABLED,
  52         BIT_IRQS_ENABLED,
  53         BIT_WIN_UPDATED,
  54         BIT_SUSPENDED,
  55         BIT_REQUEST_UPDATE
  56 };
  57
  58 struct decon_context {
  59         struct device                   *dev;
  60         struct drm_device               *drm_dev;
  61         struct exynos_drm_crtc          *crtc;
  62         struct exynos_drm_plane         planes[WINDOWS_NR];
  63         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  64         void __iomem                    *addr;
  65         struct regmap                   *sysreg;
  66         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  67         int                             pipe;
  68         unsigned long                   flags;
  69         unsigned long                   out_type;
  70         int                             first_win;
  71         spinlock_t                      vblank_lock;
  72         u32                             frame_id;
  73 };
  74
  75 static const uint32_t decon_formats[] = {
  76         DRM_FORMAT_XRGB1555,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  83         DRM_PLANE_TYPE_PRIMARY,
  84         DRM_PLANE_TYPE_OVERLAY,
  85         DRM_PLANE_TYPE_CURSOR,
  86 };
  87
  88 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  89                                   u32 val)
  90 {
  91         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  92         writel(val, ctx->addr + reg);
  93 }
  94
  95 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  96 {
  97         struct decon_context *ctx = crtc->ctx;
  98         u32 val;
  99
 100         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 101                 return -EPERM;
 102
 103         if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
 104                 val = VIDINTCON0_INTEN;
 105                 if (ctx->out_type & IFTYPE_I80)
 106                         val |= VIDINTCON0_FRAMEDONE;
 107                 else
 108                         val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 109
 110                 writel(val, ctx->addr + DECON_VIDINTCON0);
 111         }
 112
 113         return 0;
 114 }
 115
 116 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 117 {
 118         struct decon_context *ctx = crtc->ctx;
 119
 120         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 121                 return;
 122
 123         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 124                 writel(0, ctx->addr + DECON_VIDINTCON0);
 125 }
 126
 127 /* return number of starts/ends of frame transmissions since reset */
 128 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
 129 {
 130         u32 frm, pfrm, status, cnt = 2;
 131
 132         /* To get consistent result repeat read until frame id is stable.
 133          * Usually the loop will be executed once, in rare cases when the loop
 134          * is executed at frame change time 2nd pass will be needed.
 135          */
 136         frm = readl(ctx->addr + DECON_CRFMID);
 137         do {
 138                 status = readl(ctx->addr + DECON_VIDCON1);
 139                 pfrm = frm;
 140                 frm = readl(ctx->addr + DECON_CRFMID);
 141         } while (frm != pfrm && --cnt);
 142
 143         /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
 144          * of RGB, it should be taken into account.
 145          */
 146         if (!frm)
 147                 return 0;
 148
 149         switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
 150         case VIDCON1_VSTATUS_VS:
 151                 if (!(ctx->out_type & IFTYPE_I80))
 152                         --frm;
 153                 break;
 154         case VIDCON1_VSTATUS_BP:
 155                 --frm;
 156                 break;
 157         case VIDCON1_I80_ACTIVE:
 158         case VIDCON1_VSTATUS_AC:
 159                 if (end)
 160                         --frm;
 161                 break;
 162         default:
 163                 break;
 164         }
 165
 166         return frm;
 167 }
 168
 169 static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
 170 {
 171         struct decon_context *ctx = crtc->ctx;
 172
 173         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 174                 return 0;
 175
 176         return decon_get_frame_count(ctx, false);
 177 }
 178
 179 static void decon_setup_trigger(struct decon_context *ctx)
 180 {
 181         if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
 182                 return;
 183
 184         if (!(ctx->out_type & I80_HW_TRG)) {
 185                 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 186                        TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 187                        ctx->addr + DECON_TRIGCON);
 188                 return;
 189         }
 190
 191         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 192                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 193
 194         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 195                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 196                 DRM_ERROR("Cannot update sysreg.\n");
 197 }
 198
 199 static void decon_commit(struct exynos_drm_crtc *crtc)
 200 {
 201         struct decon_context *ctx = crtc->ctx;
 202         struct drm_display_mode *m = &crtc->base.mode;
 203         bool interlaced = false;
 204         u32 val;
 205
 206         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 207                 return;
 208
 209         if (ctx->out_type & IFTYPE_HDMI) {
 210                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 211                 m->crtc_hsync_end = m->crtc_htotal - 92;
 212                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 213                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 214                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 215                         interlaced = true;
 216         }
 217
 218         decon_setup_trigger(ctx);
 219
 220         /* lcd on and use command if */
 221         val = VIDOUT_LCD_ON;
 222         if (interlaced)
 223                 val |= VIDOUT_INTERLACE_EN_F;
 224         if (ctx->out_type & IFTYPE_I80) {
 225                 val |= VIDOUT_COMMAND_IF;
 226         } else {
 227                 val |= VIDOUT_RGB_IF;
 228         }
 229
 230         writel(val, ctx->addr + DECON_VIDOUTCON0);
 231
 232         if (interlaced)
 233                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 234                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 235         else
 236                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 237                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 238         writel(val, ctx->addr + DECON_VIDTCON2);
 239
 240         if (!(ctx->out_type & IFTYPE_I80)) {
 241                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 242                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 243
 244                 if (interlaced)
 245                         vbp = vbp / 2 - 1;
 246                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 247                 writel(val, ctx->addr + DECON_VIDTCON00);
 248
 249                 val = VIDTCON01_VSPW_F(
 250                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 251                 writel(val, ctx->addr + DECON_VIDTCON01);
 252
 253                 val = VIDTCON10_HBPD_F(
 254                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 255                         VIDTCON10_HFPD_F(
 256                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 257                 writel(val, ctx->addr + DECON_VIDTCON10);
 258
 259                 val = VIDTCON11_HSPW_F(
 260                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 261                 writel(val, ctx->addr + DECON_VIDTCON11);
 262         }
 263
 264         /* enable output and display signal */
 265         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 266
 267         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 268 }
 269
 270 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 271                                  struct drm_framebuffer *fb)
 272 {
 273         unsigned long val;
 274
 275         val = readl(ctx->addr + DECON_WINCONx(win));
 276         val &= ~WINCONx_BPPMODE_MASK;
 277
 278         switch (fb->format->format) {
 279         case DRM_FORMAT_XRGB1555:
 280                 val |= WINCONx_BPPMODE_16BPP_I1555;
 281                 val |= WINCONx_HAWSWP_F;
 282                 val |= WINCONx_BURSTLEN_16WORD;
 283                 break;
 284         case DRM_FORMAT_RGB565:
 285                 val |= WINCONx_BPPMODE_16BPP_565;
 286                 val |= WINCONx_HAWSWP_F;
 287                 val |= WINCONx_BURSTLEN_16WORD;
 288                 break;
 289         case DRM_FORMAT_XRGB8888:
 290                 val |= WINCONx_BPPMODE_24BPP_888;
 291                 val |= WINCONx_WSWP_F;
 292                 val |= WINCONx_BURSTLEN_16WORD;
 293                 break;
 294         case DRM_FORMAT_ARGB8888:
 295                 val |= WINCONx_BPPMODE_32BPP_A8888;
 296                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 297                 val |= WINCONx_BURSTLEN_16WORD;
 298                 break;
 299         default:
 300                 DRM_ERROR("Proper pixel format is not set\n");
 301                 return;
 302         }
 303
 304         DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
 305
 306         /*
 307          * In case of exynos, setting dma-burst to 16Word causes permanent
 308          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 309          * switching which is based on plane size is not recommended as
 310          * plane size varies a lot towards the end of the screen and rapid
 311          * movement causes unstable DMA which results into iommu crash/tear.
 312          */
 313
 314         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 315                 val &= ~WINCONx_BURSTLEN_MASK;
 316                 val |= WINCONx_BURSTLEN_8WORD;
 317         }
 318
 319         writel(val, ctx->addr + DECON_WINCONx(win));
 320 }
 321
 322 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 323                                         bool protect)
 324 {
 325         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 326                        protect ? ~0 : 0);
 327 }
 328
 329 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 330 {
 331         struct decon_context *ctx = crtc->ctx;
 332         int i;
 333
 334         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 335                 return;
 336
 337         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 338                 decon_shadow_protect_win(ctx, i, true);
 339 }
 340
 341 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 342 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 343 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 344
 345 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 346                                struct exynos_drm_plane *plane)
 347 {
 348         struct exynos_drm_plane_state *state =
 349                                 to_exynos_plane_state(plane->base.state);
 350         struct decon_context *ctx = crtc->ctx;
 351         struct drm_framebuffer *fb = state->base.fb;
 352         unsigned int win = plane->index;
 353         unsigned int bpp = fb->format->cpp[0];
 354         unsigned int pitch = fb->pitches[0];
 355         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 356         u32 val;
 357
 358         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 359                 return;
 360
 361         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 362                 val = COORDINATE_X(state->crtc.x) |
 363                         COORDINATE_Y(state->crtc.y / 2);
 364                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 365
 366                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 367                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 368                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 369         } else {
 370                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 371                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 372
 373                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 374                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 375                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 376         }
 377
 378         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 379                 VIDOSD_Wx_ALPHA_B_F(0x0);
 380         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 381
 382         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 383                 VIDOSD_Wx_ALPHA_B_F(0x0);
 384         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 385
 386         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 387
 388         val = dma_addr + pitch * state->src.h;
 389         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 390
 391         if (!(ctx->out_type & IFTYPE_HDMI))
 392                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 393                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 394         else
 395                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 396                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 397         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 398
 399         decon_win_set_pixfmt(ctx, win, fb);
 400
 401         /* window enable */
 402         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 403         set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
 404 }
 405
 406 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 407                                 struct exynos_drm_plane *plane)
 408 {
 409         struct decon_context *ctx = crtc->ctx;
 410         unsigned int win = plane->index;
 411
 412         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 413                 return;
 414
 415         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 416         set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
 417 }
 418
 419 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 420 {
 421         struct decon_context *ctx = crtc->ctx;
 422         unsigned long flags;
 423         int i;
 424
 425         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 426                 return;
 427
 428         spin_lock_irqsave(&ctx->vblank_lock, flags);
 429
 430         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 431                 decon_shadow_protect_win(ctx, i, false);
 432
 433         if (test_and_clear_bit(BIT_REQUEST_UPDATE, &ctx->flags))
 434                 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 435
 436         if (ctx->out_type & IFTYPE_I80)
 437                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 438
 439         ctx->frame_id = decon_get_frame_count(ctx, true);
 440
 441         exynos_crtc_handle_event(crtc);
 442
 443         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 444 }
 445
 446 static void decon_swreset(struct decon_context *ctx)
 447 {
 448         unsigned int tries;
 449         unsigned long flags;
 450
 451         writel(0, ctx->addr + DECON_VIDCON0);
 452         for (tries = 2000; tries; --tries) {
 453                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 454                         break;
 455                 udelay(10);
 456         }
 457
 458         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 459         for (tries = 2000; tries; --tries) {
 460                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 461                         break;
 462                 udelay(10);
 463         }
 464
 465         WARN(tries == 0, "failed to software reset DECON\n");
 466
 467         spin_lock_irqsave(&ctx->vblank_lock, flags);
 468         ctx->frame_id = 0;
 469         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 470
 471         if (!(ctx->out_type & IFTYPE_HDMI))
 472                 return;
 473
 474         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 475         decon_set_bits(ctx, DECON_CMU,
 476                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 477         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 478         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 479                ctx->addr + DECON_CRCCTRL);
 480 }
 481
 482 static void decon_enable(struct exynos_drm_crtc *crtc)
 483 {
 484         struct decon_context *ctx = crtc->ctx;
 485
 486         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 487                 return;
 488
 489         pm_runtime_get_sync(ctx->dev);
 490
 491         exynos_drm_pipe_clk_enable(crtc, true);
 492
 493         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 494
 495         decon_swreset(ctx);
 496
 497         /* if vblank was enabled status, enable it again. */
 498         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 499                 decon_enable_vblank(ctx->crtc);
 500
 501         decon_commit(ctx->crtc);
 502 }
 503
 504 static void decon_disable(struct exynos_drm_crtc *crtc)
 505 {
 506         struct decon_context *ctx = crtc->ctx;
 507         int i;
 508
 509         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 510                 return;
 511
 512         /*
 513          * We need to make sure that all windows are disabled before we
 514          * suspend that connector. Otherwise we might try to scan from
 515          * a destroyed buffer later.
 516          */
 517         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 518                 decon_disable_plane(crtc, &ctx->planes[i]);
 519
 520         decon_swreset(ctx);
 521
 522         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 523
 524         exynos_drm_pipe_clk_enable(crtc, false);
 525
 526         pm_runtime_put_sync(ctx->dev);
 527
 528         set_bit(BIT_SUSPENDED, &ctx->flags);
 529 }
 530
 531 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 532 {
 533         struct decon_context *ctx = crtc->ctx;
 534
 535         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 536             (ctx->out_type & I80_HW_TRG))
 537                 return;
 538
 539         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 540                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 541 }
 542
 543 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 544 {
 545         struct decon_context *ctx = crtc->ctx;
 546         int win, i, ret;
 547
 548         DRM_DEBUG_KMS("%s\n", __FILE__);
 549
 550         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 551                 ret = clk_prepare_enable(ctx->clks[i]);
 552                 if (ret < 0)
 553                         goto err;
 554         }
 555
 556         for (win = 0; win < WINDOWS_NR; win++) {
 557                 decon_shadow_protect_win(ctx, win, true);
 558                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 559                 decon_shadow_protect_win(ctx, win, false);
 560         }
 561
 562         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 563
 564         /* TODO: wait for possible vsync */
 565         msleep(50);
 566
 567 err:
 568         while (--i >= 0)
 569                 clk_disable_unprepare(ctx->clks[i]);
 570 }
 571
 572 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 573         .enable                 = decon_enable,
 574         .disable                = decon_disable,
 575         .enable_vblank          = decon_enable_vblank,
 576         .disable_vblank         = decon_disable_vblank,
 577         .get_vblank_counter     = decon_get_vblank_counter,
 578         .atomic_begin           = decon_atomic_begin,
 579         .update_plane           = decon_update_plane,
 580         .disable_plane          = decon_disable_plane,
 581         .atomic_flush           = decon_atomic_flush,
 582         .te_handler             = decon_te_irq_handler,
 583 };
 584
 585 static int decon_bind(struct device *dev, struct device *master, void *data)
 586 {
 587         struct decon_context *ctx = dev_get_drvdata(dev);
 588         struct drm_device *drm_dev = data;
 589         struct exynos_drm_plane *exynos_plane;
 590         enum exynos_drm_output_type out_type;
 591         unsigned int win;
 592         int ret;
 593
 594         ctx->drm_dev = drm_dev;
 595         ctx->pipe = drm_dev->mode_config.num_crtc;
 596         drm_dev->max_vblank_count = 0xffffffff;
 597
 598         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 599                 int tmp = (win == ctx->first_win) ? 0 : win;
 600
 601                 ctx->configs[win].pixel_formats = decon_formats;
 602                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 603                 ctx->configs[win].zpos = win;
 604                 ctx->configs[win].type = decon_win_types[tmp];
 605
 606                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 607                                         &ctx->configs[win]);
 608                 if (ret)
 609                         return ret;
 610         }
 611
 612         exynos_plane = &ctx->planes[ctx->first_win];
 613         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 614                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 615         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 616                         out_type, &decon_crtc_ops, ctx);
 617         if (IS_ERR(ctx->crtc))
 618                 return PTR_ERR(ctx->crtc);
 619
 620         decon_clear_channels(ctx->crtc);
 621
 622         return drm_iommu_attach_device(drm_dev, dev);
 623 }
 624
 625 static void decon_unbind(struct device *dev, struct device *master, void *data)
 626 {
 627         struct decon_context *ctx = dev_get_drvdata(dev);
 628
 629         decon_disable(ctx->crtc);
 630
 631         /* detach this sub driver from iommu mapping if supported. */
 632         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 633 }
 634
 635 static const struct component_ops decon_component_ops = {
 636         .bind   = decon_bind,
 637         .unbind = decon_unbind,
 638 };
 639
 640 static void decon_handle_vblank(struct decon_context *ctx)
 641 {
 642         u32 frm;
 643
 644         spin_lock(&ctx->vblank_lock);
 645
 646         frm = decon_get_frame_count(ctx, true);
 647
 648         if (frm != ctx->frame_id) {
 649                 /* handle only if incremented, take care of wrap-around */
 650                 if ((s32)(frm - ctx->frame_id) > 0)
 651                         drm_crtc_handle_vblank(&ctx->crtc->base);
 652                 ctx->frame_id = frm;
 653         }
 654
 655         spin_unlock(&ctx->vblank_lock);
 656 }
 657
 658 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 659 {
 660         struct decon_context *ctx = dev_id;
 661         u32 val;
 662
 663         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 664                 goto out;
 665
 666         val = readl(ctx->addr + DECON_VIDINTCON1);
 667         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 668
 669         if (val) {
 670                 writel(val, ctx->addr + DECON_VIDINTCON1);
 671                 if (ctx->out_type & IFTYPE_HDMI) {
 672                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 673                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 674                         if (val ==
 675                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 676                                 return IRQ_HANDLED;
 677                 }
 678                 decon_handle_vblank(ctx);
 679         }
 680
 681 out:
 682         return IRQ_HANDLED;
 683 }
 684
 685 #ifdef CONFIG_PM
 686 static int exynos5433_decon_suspend(struct device *dev)
 687 {
 688         struct decon_context *ctx = dev_get_drvdata(dev);
 689         int i = ARRAY_SIZE(decon_clks_name);
 690
 691         while (--i >= 0)
 692                 clk_disable_unprepare(ctx->clks[i]);
 693
 694         return 0;
 695 }
 696
 697 static int exynos5433_decon_resume(struct device *dev)
 698 {
 699         struct decon_context *ctx = dev_get_drvdata(dev);
 700         int i, ret;
 701
 702         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 703                 ret = clk_prepare_enable(ctx->clks[i]);
 704                 if (ret < 0)
 705                         goto err;
 706         }
 707
 708         return 0;
 709
 710 err:
 711         while (--i >= 0)
 712                 clk_disable_unprepare(ctx->clks[i]);
 713
 714         return ret;
 715 }
 716 #endif
 717
 718 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 719         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 720                            NULL)
 721 };
 722
 723 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 724         {
 725                 .compatible = "samsung,exynos5433-decon",
 726                 .data = (void *)I80_HW_TRG
 727         },
 728         {
 729                 .compatible = "samsung,exynos5433-decon-tv",
 730                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 731         },
 732         {},
 733 };
 734 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 735
 736 static int exynos5433_decon_probe(struct platform_device *pdev)
 737 {
 738         struct device *dev = &pdev->dev;
 739         struct decon_context *ctx;
 740         struct resource *res;
 741         int ret;
 742         int i;
 743
 744         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 745         if (!ctx)
 746                 return -ENOMEM;
 747
 748         __set_bit(BIT_SUSPENDED, &ctx->flags);
 749         ctx->dev = dev;
 750         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 751         spin_lock_init(&ctx->vblank_lock);
 752
 753         if (ctx->out_type & IFTYPE_HDMI) {
 754                 ctx->first_win = 1;
 755         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 756                 ctx->out_type |= IFTYPE_I80;
 757         }
 758
 759         if (ctx->out_type & I80_HW_TRG) {
 760                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 761                                                         "samsung,disp-sysreg");
 762                 if (IS_ERR(ctx->sysreg)) {
 763                         dev_err(dev, "failed to get system register\n");
 764                         return PTR_ERR(ctx->sysreg);
 765                 }
 766         }
 767
 768         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 769                 struct clk *clk;
 770
 771                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 772                 if (IS_ERR(clk))
 773                         return PTR_ERR(clk);
 774
 775                 ctx->clks[i] = clk;
 776         }
 777
 778         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 779         if (!res) {
 780                 dev_err(dev, "cannot find IO resource\n");
 781                 return -ENXIO;
 782         }
 783
 784         ctx->addr = devm_ioremap_resource(dev, res);
 785         if (IS_ERR(ctx->addr)) {
 786                 dev_err(dev, "ioremap failed\n");
 787                 return PTR_ERR(ctx->addr);
 788         }
 789
 790         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 791                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 792         if (!res) {
 793                 dev_err(dev, "cannot find IRQ resource\n");
 794                 return -ENXIO;
 795         }
 796
 797         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 798                                "drm_decon", ctx);
 799         if (ret < 0) {
 800                 dev_err(dev, "lcd_sys irq request failed\n");
 801                 return ret;
 802         }
 803
 804         platform_set_drvdata(pdev, ctx);
 805
 806         pm_runtime_enable(dev);
 807
 808         ret = component_add(dev, &decon_component_ops);
 809         if (ret)
 810                 goto err_disable_pm_runtime;
 811
 812         return 0;
 813
 814 err_disable_pm_runtime:
 815         pm_runtime_disable(dev);
 816
 817         return ret;
 818 }
 819
 820 static int exynos5433_decon_remove(struct platform_device *pdev)
 821 {
 822         pm_runtime_disable(&pdev->dev);
 823
 824         component_del(&pdev->dev, &decon_component_ops);
 825
 826         return 0;
 827 }
 828
 829 struct platform_driver exynos5433_decon_driver = {
 830         .probe          = exynos5433_decon_probe,
 831         .remove         = exynos5433_decon_remove,
 832         .driver         = {
 833                 .name   = "exynos5433-decon",
 834                 .pm     = &exynos5433_decon_pm_ops,
 835                 .of_match_table = exynos5433_decon_driver_dt_match,
 836         },
 837 };