drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #include <video/exynos5433_decon.h>
  21
  22 #include "exynos_drm_drv.h"
  23 #include "exynos_drm_crtc.h"
  24 #include "exynos_drm_plane.h"
  25 #include "exynos_drm_iommu.h"
  26
  27 #define WINDOWS_NR      3
  28 #define CURSOR_WIN      2
  29 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  30
  31 static const char * const decon_clks_name[] = {
  32         "pclk",
  33         "aclk_decon",
  34         "aclk_smmu_decon0x",
  35         "aclk_xiu_decon0x",
  36         "pclk_smmu_decon0x",
  37         "sclk_decon_vclk",
  38         "sclk_decon_eclk",
  39 };
  40
  41 enum decon_iftype {
  42         IFTYPE_RGB,
  43         IFTYPE_I80,
  44         IFTYPE_HDMI
  45 };
  46
  47 enum decon_flag_bits {
  48         BIT_CLKS_ENABLED,
  49         BIT_IRQS_ENABLED,
  50         BIT_WIN_UPDATED,
  51         BIT_SUSPENDED
  52 };
  53
  54 struct decon_context {
  55         struct device                   *dev;
  56         struct drm_device               *drm_dev;
  57         struct exynos_drm_crtc          *crtc;
  58         struct exynos_drm_plane         planes[WINDOWS_NR];
  59         void __iomem                    *addr;
  60         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  61         int                             pipe;
  62         unsigned long                   flags;
  63         enum decon_iftype               out_type;
  64         int                             first_win;
  65 };
  66
  67 static const uint32_t decon_formats[] = {
  68         DRM_FORMAT_XRGB1555,
  69         DRM_FORMAT_RGB565,
  70         DRM_FORMAT_XRGB8888,
  71         DRM_FORMAT_ARGB8888,
  72 };
  73
  74 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  75                                   u32 val)
  76 {
  77         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  78         writel(val, ctx->addr + reg);
  79 }
  80
  81 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  82 {
  83         struct decon_context *ctx = crtc->ctx;
  84         u32 val;
  85
  86         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  87                 return -EPERM;
  88
  89         if (test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
  90                 val = VIDINTCON0_INTEN;
  91                 if (ctx->out_type == IFTYPE_I80)
  92                         val |= VIDINTCON0_FRAMEDONE;
  93                 else
  94                         val |= VIDINTCON0_INTFRMEN;
  95
  96                 writel(val, ctx->addr + DECON_VIDINTCON0);
  97         }
  98
  99         return 0;
 100 }
 101
 102 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 103 {
 104         struct decon_context *ctx = crtc->ctx;
 105
 106         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 107                 return;
 108
 109         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 110                 writel(0, ctx->addr + DECON_VIDINTCON0);
 111 }
 112
 113 static void decon_setup_trigger(struct decon_context *ctx)
 114 {
 115         u32 val = (ctx->out_type != IFTYPE_HDMI)
 116                 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 117                   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
 118                 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 119                   TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
 120         writel(val, ctx->addr + DECON_TRIGCON);
 121 }
 122
 123 static void decon_commit(struct exynos_drm_crtc *crtc)
 124 {
 125         struct decon_context *ctx = crtc->ctx;
 126         struct drm_display_mode *m = &crtc->base.mode;
 127         u32 val;
 128
 129         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 130                 return;
 131
 132         if (ctx->out_type == IFTYPE_HDMI) {
 133                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 134                 m->crtc_hsync_end = m->crtc_htotal - 92;
 135                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 136                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 137         }
 138
 139         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
 140
 141         /* enable clock gate */
 142         val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
 143         writel(val, ctx->addr + DECON_CMU);
 144
 145         /* lcd on and use command if */
 146         val = VIDOUT_LCD_ON;
 147         if (ctx->out_type == IFTYPE_I80)
 148                 val |= VIDOUT_COMMAND_IF;
 149         else
 150                 val |= VIDOUT_RGB_IF;
 151         writel(val, ctx->addr + DECON_VIDOUTCON0);
 152
 153         val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 154                 VIDTCON2_HOZVAL(m->hdisplay - 1);
 155         writel(val, ctx->addr + DECON_VIDTCON2);
 156
 157         if (ctx->out_type != IFTYPE_I80) {
 158                 val = VIDTCON00_VBPD_F(
 159                                 m->crtc_vtotal - m->crtc_vsync_end - 1) |
 160                         VIDTCON00_VFPD_F(
 161                                 m->crtc_vsync_start - m->crtc_vdisplay - 1);
 162                 writel(val, ctx->addr + DECON_VIDTCON00);
 163
 164                 val = VIDTCON01_VSPW_F(
 165                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 166                 writel(val, ctx->addr + DECON_VIDTCON01);
 167
 168                 val = VIDTCON10_HBPD_F(
 169                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 170                         VIDTCON10_HFPD_F(
 171                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 172                 writel(val, ctx->addr + DECON_VIDTCON10);
 173
 174                 val = VIDTCON11_HSPW_F(
 175                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 176                 writel(val, ctx->addr + DECON_VIDTCON11);
 177         }
 178
 179         decon_setup_trigger(ctx);
 180
 181         /* enable output and display signal */
 182         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 183 }
 184
 185 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 186                                  struct drm_framebuffer *fb)
 187 {
 188         unsigned long val;
 189
 190         val = readl(ctx->addr + DECON_WINCONx(win));
 191         val &= ~WINCONx_BPPMODE_MASK;
 192
 193         switch (fb->pixel_format) {
 194         case DRM_FORMAT_XRGB1555:
 195                 val |= WINCONx_BPPMODE_16BPP_I1555;
 196                 val |= WINCONx_HAWSWP_F;
 197                 val |= WINCONx_BURSTLEN_16WORD;
 198                 break;
 199         case DRM_FORMAT_RGB565:
 200                 val |= WINCONx_BPPMODE_16BPP_565;
 201                 val |= WINCONx_HAWSWP_F;
 202                 val |= WINCONx_BURSTLEN_16WORD;
 203                 break;
 204         case DRM_FORMAT_XRGB8888:
 205                 val |= WINCONx_BPPMODE_24BPP_888;
 206                 val |= WINCONx_WSWP_F;
 207                 val |= WINCONx_BURSTLEN_16WORD;
 208                 break;
 209         case DRM_FORMAT_ARGB8888:
 210                 val |= WINCONx_BPPMODE_32BPP_A8888;
 211                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 212                 val |= WINCONx_BURSTLEN_16WORD;
 213                 break;
 214         default:
 215                 DRM_ERROR("Proper pixel format is not set\n");
 216                 return;
 217         }
 218
 219         DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
 220
 221         /*
 222          * In case of exynos, setting dma-burst to 16Word causes permanent
 223          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 224          * switching which is based on plane size is not recommended as
 225          * plane size varies a lot towards the end of the screen and rapid
 226          * movement causes unstable DMA which results into iommu crash/tear.
 227          */
 228
 229         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 230                 val &= ~WINCONx_BURSTLEN_MASK;
 231                 val |= WINCONx_BURSTLEN_8WORD;
 232         }
 233
 234         writel(val, ctx->addr + DECON_WINCONx(win));
 235 }
 236
 237 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 238                                         bool protect)
 239 {
 240         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 241                        protect ? ~0 : 0);
 242 }
 243
 244 static void decon_atomic_begin(struct exynos_drm_crtc *crtc,
 245                                         struct exynos_drm_plane *plane)
 246 {
 247         struct decon_context *ctx = crtc->ctx;
 248
 249         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 250                 return;
 251
 252         decon_shadow_protect_win(ctx, plane->zpos, true);
 253 }
 254
 255 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 256 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 257 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 258
 259 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 260                                struct exynos_drm_plane *plane)
 261 {
 262         struct decon_context *ctx = crtc->ctx;
 263         struct drm_plane_state *state = plane->base.state;
 264         unsigned int win = plane->zpos;
 265         unsigned int bpp = state->fb->bits_per_pixel >> 3;
 266         unsigned int pitch = state->fb->pitches[0];
 267         u32 val;
 268
 269         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 270                 return;
 271
 272         val = COORDINATE_X(plane->crtc_x) | COORDINATE_Y(plane->crtc_y);
 273         writel(val, ctx->addr + DECON_VIDOSDxA(win));
 274
 275         val = COORDINATE_X(plane->crtc_x + plane->crtc_w - 1) |
 276                 COORDINATE_Y(plane->crtc_y + plane->crtc_h - 1);
 277         writel(val, ctx->addr + DECON_VIDOSDxB(win));
 278
 279         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 280                 VIDOSD_Wx_ALPHA_B_F(0x0);
 281         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 282
 283         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 284                 VIDOSD_Wx_ALPHA_B_F(0x0);
 285         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 286
 287         writel(plane->dma_addr[0], ctx->addr + DECON_VIDW0xADD0B0(win));
 288
 289         val = plane->dma_addr[0] + pitch * plane->crtc_h;
 290         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 291
 292         if (ctx->out_type != IFTYPE_HDMI)
 293                 val = BIT_VAL(pitch - plane->crtc_w * bpp, 27, 14)
 294                         | BIT_VAL(plane->crtc_w * bpp, 13, 0);
 295         else
 296                 val = BIT_VAL(pitch - plane->crtc_w * bpp, 29, 15)
 297                         | BIT_VAL(plane->crtc_w * bpp, 14, 0);
 298         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 299
 300         decon_win_set_pixfmt(ctx, win, state->fb);
 301
 302         /* window enable */
 303         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 304
 305         /* standalone update */
 306         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 307 }
 308
 309 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 310                                 struct exynos_drm_plane *plane)
 311 {
 312         struct decon_context *ctx = crtc->ctx;
 313         unsigned int win = plane->zpos;
 314
 315         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 316                 return;
 317
 318         decon_shadow_protect_win(ctx, win, true);
 319
 320         /* window disable */
 321         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 322
 323         decon_shadow_protect_win(ctx, win, false);
 324
 325         /* standalone update */
 326         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 327 }
 328
 329 static void decon_atomic_flush(struct exynos_drm_crtc *crtc,
 330                                 struct exynos_drm_plane *plane)
 331 {
 332         struct decon_context *ctx = crtc->ctx;
 333
 334         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 335                 return;
 336
 337         decon_shadow_protect_win(ctx, plane->zpos, false);
 338
 339         if (ctx->out_type == IFTYPE_I80)
 340                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 341 }
 342
 343 static void decon_swreset(struct decon_context *ctx)
 344 {
 345         unsigned int tries;
 346
 347         writel(0, ctx->addr + DECON_VIDCON0);
 348         for (tries = 2000; tries; --tries) {
 349                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 350                         break;
 351                 udelay(10);
 352         }
 353
 354         WARN(tries == 0, "failed to disable DECON\n");
 355
 356         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 357         for (tries = 2000; tries; --tries) {
 358                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 359                         break;
 360                 udelay(10);
 361         }
 362
 363         WARN(tries == 0, "failed to software reset DECON\n");
 364
 365         if (ctx->out_type != IFTYPE_HDMI)
 366                 return;
 367
 368         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 369         decon_set_bits(ctx, DECON_CMU,
 370                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 371         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 372         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 373                ctx->addr + DECON_CRCCTRL);
 374         decon_setup_trigger(ctx);
 375 }
 376
 377 static void decon_enable(struct exynos_drm_crtc *crtc)
 378 {
 379         struct decon_context *ctx = crtc->ctx;
 380
 381         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 382                 return;
 383
 384         pm_runtime_get_sync(ctx->dev);
 385
 386         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 387
 388         /* if vblank was enabled status, enable it again. */
 389         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 390                 decon_enable_vblank(ctx->crtc);
 391
 392         decon_commit(ctx->crtc);
 393
 394         set_bit(BIT_SUSPENDED, &ctx->flags);
 395 }
 396
 397 static void decon_disable(struct exynos_drm_crtc *crtc)
 398 {
 399         struct decon_context *ctx = crtc->ctx;
 400         int i;
 401
 402         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 403                 return;
 404
 405         /*
 406          * We need to make sure that all windows are disabled before we
 407          * suspend that connector. Otherwise we might try to scan from
 408          * a destroyed buffer later.
 409          */
 410         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 411                 decon_disable_plane(crtc, &ctx->planes[i]);
 412
 413         decon_swreset(ctx);
 414
 415         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 416
 417         pm_runtime_put_sync(ctx->dev);
 418
 419         set_bit(BIT_SUSPENDED, &ctx->flags);
 420 }
 421
 422 void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 423 {
 424         struct decon_context *ctx = crtc->ctx;
 425
 426         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 427                 return;
 428
 429         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 430                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 431
 432         drm_crtc_handle_vblank(&ctx->crtc->base);
 433 }
 434
 435 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 436 {
 437         struct decon_context *ctx = crtc->ctx;
 438         int win, i, ret;
 439
 440         DRM_DEBUG_KMS("%s\n", __FILE__);
 441
 442         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 443                 ret = clk_prepare_enable(ctx->clks[i]);
 444                 if (ret < 0)
 445                         goto err;
 446         }
 447
 448         for (win = 0; win < WINDOWS_NR; win++) {
 449                 decon_shadow_protect_win(ctx, win, true);
 450                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 451                 decon_shadow_protect_win(ctx, win, false);
 452                 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 453         }
 454         /* TODO: wait for possible vsync */
 455         msleep(50);
 456
 457 err:
 458         while (--i >= 0)
 459                 clk_disable_unprepare(ctx->clks[i]);
 460 }
 461
 462 static struct exynos_drm_crtc_ops decon_crtc_ops = {
 463         .enable                 = decon_enable,
 464         .disable                = decon_disable,
 465         .enable_vblank          = decon_enable_vblank,
 466         .disable_vblank         = decon_disable_vblank,
 467         .atomic_begin           = decon_atomic_begin,
 468         .update_plane           = decon_update_plane,
 469         .disable_plane          = decon_disable_plane,
 470         .atomic_flush           = decon_atomic_flush,
 471         .te_handler             = decon_te_irq_handler,
 472 };
 473
 474 static int decon_bind(struct device *dev, struct device *master, void *data)
 475 {
 476         struct decon_context *ctx = dev_get_drvdata(dev);
 477         struct drm_device *drm_dev = data;
 478         struct exynos_drm_private *priv = drm_dev->dev_private;
 479         struct exynos_drm_plane *exynos_plane;
 480         enum exynos_drm_output_type out_type;
 481         enum drm_plane_type type;
 482         unsigned int win;
 483         int ret;
 484
 485         ctx->drm_dev = drm_dev;
 486         ctx->pipe = priv->pipe++;
 487
 488         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 489                 int tmp = (win == ctx->first_win) ? 0 : win;
 490
 491                 type = exynos_plane_get_type(tmp, CURSOR_WIN);
 492                 ret = exynos_plane_init(drm_dev, &ctx->planes[win],
 493                                 1 << ctx->pipe, type, decon_formats,
 494                                 ARRAY_SIZE(decon_formats), win);
 495                 if (ret)
 496                         return ret;
 497         }
 498
 499         exynos_plane = &ctx->planes[ctx->first_win];
 500         out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 501                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 502         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 503                                         ctx->pipe, out_type,
 504                                         &decon_crtc_ops, ctx);
 505         if (IS_ERR(ctx->crtc)) {
 506                 ret = PTR_ERR(ctx->crtc);
 507                 goto err;
 508         }
 509
 510         decon_clear_channels(ctx->crtc);
 511
 512         ret = drm_iommu_attach_device(drm_dev, dev);
 513         if (ret)
 514                 goto err;
 515
 516         return ret;
 517 err:
 518         priv->pipe--;
 519         return ret;
 520 }
 521
 522 static void decon_unbind(struct device *dev, struct device *master, void *data)
 523 {
 524         struct decon_context *ctx = dev_get_drvdata(dev);
 525
 526         decon_disable(ctx->crtc);
 527
 528         /* detach this sub driver from iommu mapping if supported. */
 529         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 530 }
 531
 532 static const struct component_ops decon_component_ops = {
 533         .bind   = decon_bind,
 534         .unbind = decon_unbind,
 535 };
 536
 537 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 538 {
 539         struct decon_context *ctx = dev_id;
 540         u32 val;
 541         int win;
 542
 543         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 544                 goto out;
 545
 546         val = readl(ctx->addr + DECON_VIDINTCON1);
 547         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 548
 549         if (val) {
 550                 for (win = ctx->first_win; win < WINDOWS_NR ; win++) {
 551                         struct exynos_drm_plane *plane = &ctx->planes[win];
 552
 553                         if (!plane->pending_fb)
 554                                 continue;
 555
 556                         exynos_drm_crtc_finish_update(ctx->crtc, plane);
 557                 }
 558
 559                 /* clear */
 560                 writel(val, ctx->addr + DECON_VIDINTCON1);
 561         }
 562
 563 out:
 564         return IRQ_HANDLED;
 565 }
 566
 567 #ifdef CONFIG_PM
 568 static int exynos5433_decon_suspend(struct device *dev)
 569 {
 570         struct decon_context *ctx = dev_get_drvdata(dev);
 571         int i;
 572
 573         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++)
 574                 clk_disable_unprepare(ctx->clks[i]);
 575
 576         return 0;
 577 }
 578
 579 static int exynos5433_decon_resume(struct device *dev)
 580 {
 581         struct decon_context *ctx = dev_get_drvdata(dev);
 582         int i, ret;
 583
 584         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 585                 ret = clk_prepare_enable(ctx->clks[i]);
 586                 if (ret < 0)
 587                         goto err;
 588         }
 589
 590         return 0;
 591
 592 err:
 593         while (--i >= 0)
 594                 clk_disable_unprepare(ctx->clks[i]);
 595
 596         return ret;
 597 }
 598 #endif
 599
 600 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 601         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 602                            NULL)
 603 };
 604
 605 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 606         {
 607                 .compatible = "samsung,exynos5433-decon",
 608                 .data = (void *)IFTYPE_RGB
 609         },
 610         {
 611                 .compatible = "samsung,exynos5433-decon-tv",
 612                 .data = (void *)IFTYPE_HDMI
 613         },
 614         {},
 615 };
 616 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 617
 618 static int exynos5433_decon_probe(struct platform_device *pdev)
 619 {
 620         const struct of_device_id *of_id;
 621         struct device *dev = &pdev->dev;
 622         struct decon_context *ctx;
 623         struct resource *res;
 624         int ret;
 625         int i;
 626
 627         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 628         if (!ctx)
 629                 return -ENOMEM;
 630
 631         __set_bit(BIT_SUSPENDED, &ctx->flags);
 632         ctx->dev = dev;
 633
 634         of_id = of_match_device(exynos5433_decon_driver_dt_match, &pdev->dev);
 635         ctx->out_type = (enum decon_iftype)of_id->data;
 636
 637         if (ctx->out_type == IFTYPE_HDMI)
 638                 ctx->first_win = 1;
 639         else if (of_get_child_by_name(dev->of_node, "i80-if-timings"))
 640                 ctx->out_type = IFTYPE_I80;
 641
 642         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 643                 struct clk *clk;
 644
 645                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 646                 if (IS_ERR(clk))
 647                         return PTR_ERR(clk);
 648
 649                 ctx->clks[i] = clk;
 650         }
 651
 652         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 653         if (!res) {
 654                 dev_err(dev, "cannot find IO resource\n");
 655                 return -ENXIO;
 656         }
 657
 658         ctx->addr = devm_ioremap_resource(dev, res);
 659         if (IS_ERR(ctx->addr)) {
 660                 dev_err(dev, "ioremap failed\n");
 661                 return PTR_ERR(ctx->addr);
 662         }
 663
 664         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 665                         (ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync");
 666         if (!res) {
 667                 dev_err(dev, "cannot find IRQ resource\n");
 668                 return -ENXIO;
 669         }
 670
 671         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 672                                "drm_decon", ctx);
 673         if (ret < 0) {
 674                 dev_err(dev, "lcd_sys irq request failed\n");
 675                 return ret;
 676         }
 677
 678         platform_set_drvdata(pdev, ctx);
 679
 680         pm_runtime_enable(dev);
 681
 682         ret = component_add(dev, &decon_component_ops);
 683         if (ret)
 684                 goto err_disable_pm_runtime;
 685
 686         return 0;
 687
 688 err_disable_pm_runtime:
 689         pm_runtime_disable(dev);
 690
 691         return ret;
 692 }
 693
 694 static int exynos5433_decon_remove(struct platform_device *pdev)
 695 {
 696         pm_runtime_disable(&pdev->dev);
 697
 698         component_del(&pdev->dev, &decon_component_ops);
 699
 700         return 0;
 701 }
 702
 703 struct platform_driver exynos5433_decon_driver = {
 704         .probe          = exynos5433_decon_probe,
 705         .remove         = exynos5433_decon_remove,
 706         .driver         = {
 707                 .name   = "exynos5433-decon",
 708                 .pm     = &exynos5433_decon_pm_ops,
 709                 .of_match_table = exynos5433_decon_driver_dt_match,
 710         },
 711 };