drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21
  22 #include <video/exynos5433_decon.h>
  23
  24 #include "exynos_drm_drv.h"
  25 #include "exynos_drm_crtc.h"
  26 #include "exynos_drm_fb.h"
  27 #include "exynos_drm_plane.h"
  28 #include "exynos_drm_iommu.h"
  29
  30 #define DSD_CFG_MUX 0x1004
  31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  32
  33 #define WINDOWS_NR      3
  34 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  35
  36 #define IFTYPE_I80      (1 << 0)
  37 #define I80_HW_TRG      (1 << 1)
  38 #define IFTYPE_HDMI     (1 << 2)
  39
  40 static const char * const decon_clks_name[] = {
  41         "pclk",
  42         "aclk_decon",
  43         "aclk_smmu_decon0x",
  44         "aclk_xiu_decon0x",
  45         "pclk_smmu_decon0x",
  46         "sclk_decon_vclk",
  47         "sclk_decon_eclk",
  48 };
  49
  50 enum decon_flag_bits {
  51         BIT_CLKS_ENABLED,
  52         BIT_IRQS_ENABLED,
  53         BIT_WIN_UPDATED,
  54         BIT_SUSPENDED,
  55         BIT_REQUEST_UPDATE
  56 };
  57
  58 struct decon_context {
  59         struct device                   *dev;
  60         struct drm_device               *drm_dev;
  61         struct exynos_drm_crtc          *crtc;
  62         struct exynos_drm_plane         planes[WINDOWS_NR];
  63         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  64         void __iomem                    *addr;
  65         struct regmap                   *sysreg;
  66         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  67         int                             pipe;
  68         unsigned long                   flags;
  69         unsigned long                   out_type;
  70         int                             first_win;
  71 };
  72
  73 static const uint32_t decon_formats[] = {
  74         DRM_FORMAT_XRGB1555,
  75         DRM_FORMAT_RGB565,
  76         DRM_FORMAT_XRGB8888,
  77         DRM_FORMAT_ARGB8888,
  78 };
  79
  80 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  81         DRM_PLANE_TYPE_PRIMARY,
  82         DRM_PLANE_TYPE_OVERLAY,
  83         DRM_PLANE_TYPE_CURSOR,
  84 };
  85
  86 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  87                                   u32 val)
  88 {
  89         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  90         writel(val, ctx->addr + reg);
  91 }
  92
  93 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  94 {
  95         struct decon_context *ctx = crtc->ctx;
  96         u32 val;
  97
  98         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  99                 return -EPERM;
 100
 101         if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
 102                 val = VIDINTCON0_INTEN;
 103                 if (ctx->out_type & IFTYPE_I80)
 104                         val |= VIDINTCON0_FRAMEDONE;
 105                 else
 106                         val |= VIDINTCON0_INTFRMEN;
 107
 108                 writel(val, ctx->addr + DECON_VIDINTCON0);
 109         }
 110
 111         return 0;
 112 }
 113
 114 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 115 {
 116         struct decon_context *ctx = crtc->ctx;
 117
 118         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 119                 return;
 120
 121         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 122                 writel(0, ctx->addr + DECON_VIDINTCON0);
 123 }
 124
 125 static void decon_setup_trigger(struct decon_context *ctx)
 126 {
 127         if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
 128                 return;
 129
 130         if (!(ctx->out_type & I80_HW_TRG)) {
 131                 writel(TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
 132                        | TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 133                        ctx->addr + DECON_TRIGCON);
 134                 return;
 135         }
 136
 137         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 138                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 139
 140         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 141                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 142                 DRM_ERROR("Cannot update sysreg.\n");
 143 }
 144
 145 static void decon_commit(struct exynos_drm_crtc *crtc)
 146 {
 147         struct decon_context *ctx = crtc->ctx;
 148         struct drm_display_mode *m = &crtc->base.mode;
 149         bool interlaced = false;
 150         u32 val;
 151
 152         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 153                 return;
 154
 155         if (ctx->out_type & IFTYPE_HDMI) {
 156                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 157                 m->crtc_hsync_end = m->crtc_htotal - 92;
 158                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 159                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 160                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 161                         interlaced = true;
 162         }
 163
 164         decon_setup_trigger(ctx);
 165
 166         /* lcd on and use command if */
 167         val = VIDOUT_LCD_ON;
 168         if (interlaced)
 169                 val |= VIDOUT_INTERLACE_EN_F;
 170         if (ctx->out_type & IFTYPE_I80) {
 171                 val |= VIDOUT_COMMAND_IF;
 172         } else {
 173                 val |= VIDOUT_RGB_IF;
 174         }
 175
 176         writel(val, ctx->addr + DECON_VIDOUTCON0);
 177
 178         if (interlaced)
 179                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 180                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 181         else
 182                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 183                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 184         writel(val, ctx->addr + DECON_VIDTCON2);
 185
 186         if (!(ctx->out_type & IFTYPE_I80)) {
 187                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 188                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 189
 190                 if (interlaced)
 191                         vbp = vbp / 2 - 1;
 192                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 193                 writel(val, ctx->addr + DECON_VIDTCON00);
 194
 195                 val = VIDTCON01_VSPW_F(
 196                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 197                 writel(val, ctx->addr + DECON_VIDTCON01);
 198
 199                 val = VIDTCON10_HBPD_F(
 200                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 201                         VIDTCON10_HFPD_F(
 202                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 203                 writel(val, ctx->addr + DECON_VIDTCON10);
 204
 205                 val = VIDTCON11_HSPW_F(
 206                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 207                 writel(val, ctx->addr + DECON_VIDTCON11);
 208         }
 209
 210         /* enable output and display signal */
 211         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 212
 213         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 214 }
 215
 216 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 217                                  struct drm_framebuffer *fb)
 218 {
 219         unsigned long val;
 220
 221         val = readl(ctx->addr + DECON_WINCONx(win));
 222         val &= ~WINCONx_BPPMODE_MASK;
 223
 224         switch (fb->format->format) {
 225         case DRM_FORMAT_XRGB1555:
 226                 val |= WINCONx_BPPMODE_16BPP_I1555;
 227                 val |= WINCONx_HAWSWP_F;
 228                 val |= WINCONx_BURSTLEN_16WORD;
 229                 break;
 230         case DRM_FORMAT_RGB565:
 231                 val |= WINCONx_BPPMODE_16BPP_565;
 232                 val |= WINCONx_HAWSWP_F;
 233                 val |= WINCONx_BURSTLEN_16WORD;
 234                 break;
 235         case DRM_FORMAT_XRGB8888:
 236                 val |= WINCONx_BPPMODE_24BPP_888;
 237                 val |= WINCONx_WSWP_F;
 238                 val |= WINCONx_BURSTLEN_16WORD;
 239                 break;
 240         case DRM_FORMAT_ARGB8888:
 241                 val |= WINCONx_BPPMODE_32BPP_A8888;
 242                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 243                 val |= WINCONx_BURSTLEN_16WORD;
 244                 break;
 245         default:
 246                 DRM_ERROR("Proper pixel format is not set\n");
 247                 return;
 248         }
 249
 250         DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
 251
 252         /*
 253          * In case of exynos, setting dma-burst to 16Word causes permanent
 254          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 255          * switching which is based on plane size is not recommended as
 256          * plane size varies a lot towards the end of the screen and rapid
 257          * movement causes unstable DMA which results into iommu crash/tear.
 258          */
 259
 260         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 261                 val &= ~WINCONx_BURSTLEN_MASK;
 262                 val |= WINCONx_BURSTLEN_8WORD;
 263         }
 264
 265         writel(val, ctx->addr + DECON_WINCONx(win));
 266 }
 267
 268 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 269                                         bool protect)
 270 {
 271         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 272                        protect ? ~0 : 0);
 273 }
 274
 275 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 276 {
 277         struct decon_context *ctx = crtc->ctx;
 278         int i;
 279
 280         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 281                 return;
 282
 283         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 284                 decon_shadow_protect_win(ctx, i, true);
 285 }
 286
 287 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 288 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 289 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 290
 291 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 292                                struct exynos_drm_plane *plane)
 293 {
 294         struct exynos_drm_plane_state *state =
 295                                 to_exynos_plane_state(plane->base.state);
 296         struct decon_context *ctx = crtc->ctx;
 297         struct drm_framebuffer *fb = state->base.fb;
 298         unsigned int win = plane->index;
 299         unsigned int bpp = fb->format->cpp[0];
 300         unsigned int pitch = fb->pitches[0];
 301         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 302         u32 val;
 303
 304         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 305                 return;
 306
 307         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 308                 val = COORDINATE_X(state->crtc.x) |
 309                         COORDINATE_Y(state->crtc.y / 2);
 310                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 311
 312                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 313                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 314                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 315         } else {
 316                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 317                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 318
 319                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 320                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 321                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 322         }
 323
 324         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 325                 VIDOSD_Wx_ALPHA_B_F(0x0);
 326         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 327
 328         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 329                 VIDOSD_Wx_ALPHA_B_F(0x0);
 330         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 331
 332         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 333
 334         val = dma_addr + pitch * state->src.h;
 335         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 336
 337         if (!(ctx->out_type & IFTYPE_HDMI))
 338                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 339                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 340         else
 341                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 342                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 343         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 344
 345         decon_win_set_pixfmt(ctx, win, fb);
 346
 347         /* window enable */
 348         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 349         set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
 350 }
 351
 352 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 353                                 struct exynos_drm_plane *plane)
 354 {
 355         struct decon_context *ctx = crtc->ctx;
 356         unsigned int win = plane->index;
 357
 358         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 359                 return;
 360
 361         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 362         set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
 363 }
 364
 365 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 366 {
 367         struct decon_context *ctx = crtc->ctx;
 368         int i;
 369
 370         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 371                 return;
 372
 373         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 374                 decon_shadow_protect_win(ctx, i, false);
 375
 376         if (test_and_clear_bit(BIT_REQUEST_UPDATE, &ctx->flags))
 377                 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 378
 379         if (ctx->out_type & IFTYPE_I80)
 380                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 381         exynos_crtc_handle_event(crtc);
 382 }
 383
 384 static void decon_swreset(struct decon_context *ctx)
 385 {
 386         unsigned int tries;
 387
 388         writel(0, ctx->addr + DECON_VIDCON0);
 389         for (tries = 2000; tries; --tries) {
 390                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 391                         break;
 392                 udelay(10);
 393         }
 394
 395         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 396         for (tries = 2000; tries; --tries) {
 397                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 398                         break;
 399                 udelay(10);
 400         }
 401
 402         WARN(tries == 0, "failed to software reset DECON\n");
 403
 404         if (!(ctx->out_type & IFTYPE_HDMI))
 405                 return;
 406
 407         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 408         decon_set_bits(ctx, DECON_CMU,
 409                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 410         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 411         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 412                ctx->addr + DECON_CRCCTRL);
 413 }
 414
 415 static void decon_enable(struct exynos_drm_crtc *crtc)
 416 {
 417         struct decon_context *ctx = crtc->ctx;
 418
 419         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 420                 return;
 421
 422         pm_runtime_get_sync(ctx->dev);
 423
 424         exynos_drm_pipe_clk_enable(crtc, true);
 425
 426         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 427
 428         decon_swreset(ctx);
 429
 430         /* if vblank was enabled status, enable it again. */
 431         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 432                 decon_enable_vblank(ctx->crtc);
 433
 434         decon_commit(ctx->crtc);
 435 }
 436
 437 static void decon_disable(struct exynos_drm_crtc *crtc)
 438 {
 439         struct decon_context *ctx = crtc->ctx;
 440         int i;
 441
 442         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 443                 return;
 444
 445         /*
 446          * We need to make sure that all windows are disabled before we
 447          * suspend that connector. Otherwise we might try to scan from
 448          * a destroyed buffer later.
 449          */
 450         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 451                 decon_disable_plane(crtc, &ctx->planes[i]);
 452
 453         decon_swreset(ctx);
 454
 455         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 456
 457         exynos_drm_pipe_clk_enable(crtc, false);
 458
 459         pm_runtime_put_sync(ctx->dev);
 460
 461         set_bit(BIT_SUSPENDED, &ctx->flags);
 462 }
 463
 464 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 465 {
 466         struct decon_context *ctx = crtc->ctx;
 467
 468         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 469             (ctx->out_type & I80_HW_TRG))
 470                 return;
 471
 472         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 473                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 474 }
 475
 476 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 477 {
 478         struct decon_context *ctx = crtc->ctx;
 479         int win, i, ret;
 480
 481         DRM_DEBUG_KMS("%s\n", __FILE__);
 482
 483         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 484                 ret = clk_prepare_enable(ctx->clks[i]);
 485                 if (ret < 0)
 486                         goto err;
 487         }
 488
 489         for (win = 0; win < WINDOWS_NR; win++) {
 490                 decon_shadow_protect_win(ctx, win, true);
 491                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 492                 decon_shadow_protect_win(ctx, win, false);
 493         }
 494
 495         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 496
 497         /* TODO: wait for possible vsync */
 498         msleep(50);
 499
 500 err:
 501         while (--i >= 0)
 502                 clk_disable_unprepare(ctx->clks[i]);
 503 }
 504
 505 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 506         .enable                 = decon_enable,
 507         .disable                = decon_disable,
 508         .enable_vblank          = decon_enable_vblank,
 509         .disable_vblank         = decon_disable_vblank,
 510         .atomic_begin           = decon_atomic_begin,
 511         .update_plane           = decon_update_plane,
 512         .disable_plane          = decon_disable_plane,
 513         .atomic_flush           = decon_atomic_flush,
 514         .te_handler             = decon_te_irq_handler,
 515 };
 516
 517 static int decon_bind(struct device *dev, struct device *master, void *data)
 518 {
 519         struct decon_context *ctx = dev_get_drvdata(dev);
 520         struct drm_device *drm_dev = data;
 521         struct exynos_drm_private *priv = drm_dev->dev_private;
 522         struct exynos_drm_plane *exynos_plane;
 523         enum exynos_drm_output_type out_type;
 524         unsigned int win;
 525         int ret;
 526
 527         ctx->drm_dev = drm_dev;
 528         ctx->pipe = priv->pipe++;
 529
 530         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 531                 int tmp = (win == ctx->first_win) ? 0 : win;
 532
 533                 ctx->configs[win].pixel_formats = decon_formats;
 534                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 535                 ctx->configs[win].zpos = win;
 536                 ctx->configs[win].type = decon_win_types[tmp];
 537
 538                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 539                                         1 << ctx->pipe, &ctx->configs[win]);
 540                 if (ret)
 541                         return ret;
 542         }
 543
 544         exynos_plane = &ctx->planes[ctx->first_win];
 545         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 546                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 547         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 548                                         ctx->pipe, out_type,
 549                                         &decon_crtc_ops, ctx);
 550         if (IS_ERR(ctx->crtc)) {
 551                 ret = PTR_ERR(ctx->crtc);
 552                 goto err;
 553         }
 554
 555         decon_clear_channels(ctx->crtc);
 556
 557         ret = drm_iommu_attach_device(drm_dev, dev);
 558         if (ret)
 559                 goto err;
 560
 561         return ret;
 562 err:
 563         priv->pipe--;
 564         return ret;
 565 }
 566
 567 static void decon_unbind(struct device *dev, struct device *master, void *data)
 568 {
 569         struct decon_context *ctx = dev_get_drvdata(dev);
 570
 571         decon_disable(ctx->crtc);
 572
 573         /* detach this sub driver from iommu mapping if supported. */
 574         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 575 }
 576
 577 static const struct component_ops decon_component_ops = {
 578         .bind   = decon_bind,
 579         .unbind = decon_unbind,
 580 };
 581
 582 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 583 {
 584         struct decon_context *ctx = dev_id;
 585         u32 val;
 586
 587         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 588                 goto out;
 589
 590         val = readl(ctx->addr + DECON_VIDINTCON1);
 591         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 592
 593         if (val) {
 594                 writel(val, ctx->addr + DECON_VIDINTCON1);
 595                 if (ctx->out_type & IFTYPE_HDMI) {
 596                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 597                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 598                         if (val ==
 599                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 600                                 return IRQ_HANDLED;
 601                 }
 602                 drm_crtc_handle_vblank(&ctx->crtc->base);
 603         }
 604
 605 out:
 606         return IRQ_HANDLED;
 607 }
 608
 609 #ifdef CONFIG_PM
 610 static int exynos5433_decon_suspend(struct device *dev)
 611 {
 612         struct decon_context *ctx = dev_get_drvdata(dev);
 613         int i = ARRAY_SIZE(decon_clks_name);
 614
 615         while (--i >= 0)
 616                 clk_disable_unprepare(ctx->clks[i]);
 617
 618         return 0;
 619 }
 620
 621 static int exynos5433_decon_resume(struct device *dev)
 622 {
 623         struct decon_context *ctx = dev_get_drvdata(dev);
 624         int i, ret;
 625
 626         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 627                 ret = clk_prepare_enable(ctx->clks[i]);
 628                 if (ret < 0)
 629                         goto err;
 630         }
 631
 632         return 0;
 633
 634 err:
 635         while (--i >= 0)
 636                 clk_disable_unprepare(ctx->clks[i]);
 637
 638         return ret;
 639 }
 640 #endif
 641
 642 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 643         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 644                            NULL)
 645 };
 646
 647 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 648         {
 649                 .compatible = "samsung,exynos5433-decon",
 650                 .data = (void *)I80_HW_TRG
 651         },
 652         {
 653                 .compatible = "samsung,exynos5433-decon-tv",
 654                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 655         },
 656         {},
 657 };
 658 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 659
 660 static int exynos5433_decon_probe(struct platform_device *pdev)
 661 {
 662         struct device *dev = &pdev->dev;
 663         struct decon_context *ctx;
 664         struct resource *res;
 665         int ret;
 666         int i;
 667
 668         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 669         if (!ctx)
 670                 return -ENOMEM;
 671
 672         __set_bit(BIT_SUSPENDED, &ctx->flags);
 673         ctx->dev = dev;
 674         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 675
 676         if (ctx->out_type & IFTYPE_HDMI) {
 677                 ctx->first_win = 1;
 678         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 679                 ctx->out_type |= IFTYPE_I80;
 680         }
 681
 682         if (ctx->out_type & I80_HW_TRG) {
 683                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 684                                                         "samsung,disp-sysreg");
 685                 if (IS_ERR(ctx->sysreg)) {
 686                         dev_err(dev, "failed to get system register\n");
 687                         return PTR_ERR(ctx->sysreg);
 688                 }
 689         }
 690
 691         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 692                 struct clk *clk;
 693
 694                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 695                 if (IS_ERR(clk))
 696                         return PTR_ERR(clk);
 697
 698                 ctx->clks[i] = clk;
 699         }
 700
 701         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 702         if (!res) {
 703                 dev_err(dev, "cannot find IO resource\n");
 704                 return -ENXIO;
 705         }
 706
 707         ctx->addr = devm_ioremap_resource(dev, res);
 708         if (IS_ERR(ctx->addr)) {
 709                 dev_err(dev, "ioremap failed\n");
 710                 return PTR_ERR(ctx->addr);
 711         }
 712
 713         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 714                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 715         if (!res) {
 716                 dev_err(dev, "cannot find IRQ resource\n");
 717                 return -ENXIO;
 718         }
 719
 720         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 721                                "drm_decon", ctx);
 722         if (ret < 0) {
 723                 dev_err(dev, "lcd_sys irq request failed\n");
 724                 return ret;
 725         }
 726
 727         platform_set_drvdata(pdev, ctx);
 728
 729         pm_runtime_enable(dev);
 730
 731         ret = component_add(dev, &decon_component_ops);
 732         if (ret)
 733                 goto err_disable_pm_runtime;
 734
 735         return 0;
 736
 737 err_disable_pm_runtime:
 738         pm_runtime_disable(dev);
 739
 740         return ret;
 741 }
 742
 743 static int exynos5433_decon_remove(struct platform_device *pdev)
 744 {
 745         pm_runtime_disable(&pdev->dev);
 746
 747         component_del(&pdev->dev, &decon_component_ops);
 748
 749         return 0;
 750 }
 751
 752 struct platform_driver exynos5433_decon_driver = {
 753         .probe          = exynos5433_decon_probe,
 754         .remove         = exynos5433_decon_remove,
 755         .driver         = {
 756                 .name   = "exynos5433-decon",
 757                 .pm     = &exynos5433_decon_pm_ops,
 758                 .of_match_table = exynos5433_decon_driver_dt_match,
 759         },
 760 };