drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21
  22 #include <video/exynos5433_decon.h>
  23
  24 #include "exynos_drm_drv.h"
  25 #include "exynos_drm_crtc.h"
  26 #include "exynos_drm_fb.h"
  27 #include "exynos_drm_plane.h"
  28 #include "exynos_drm_iommu.h"
  29
  30 #define DSD_CFG_MUX 0x1004
  31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  32
  33 #define WINDOWS_NR      3
  34 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  35
  36 #define IFTYPE_I80      (1 << 0)
  37 #define I80_HW_TRG      (1 << 1)
  38 #define IFTYPE_HDMI     (1 << 2)
  39
  40 static const char * const decon_clks_name[] = {
  41         "pclk",
  42         "aclk_decon",
  43         "aclk_smmu_decon0x",
  44         "aclk_xiu_decon0x",
  45         "pclk_smmu_decon0x",
  46         "sclk_decon_vclk",
  47         "sclk_decon_eclk",
  48 };
  49
  50 enum decon_flag_bits {
  51         BIT_CLKS_ENABLED,
  52         BIT_IRQS_ENABLED,
  53         BIT_WIN_UPDATED,
  54         BIT_SUSPENDED
  55 };
  56
  57 struct decon_context {
  58         struct device                   *dev;
  59         struct drm_device               *drm_dev;
  60         struct exynos_drm_crtc          *crtc;
  61         struct exynos_drm_plane         planes[WINDOWS_NR];
  62         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  63         void __iomem                    *addr;
  64         struct regmap                   *sysreg;
  65         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  66         unsigned long                   flags;
  67         unsigned long                   out_type;
  68         int                             first_win;
  69         spinlock_t                      vblank_lock;
  70         u32                             frame_id;
  71 };
  72
  73 static const uint32_t decon_formats[] = {
  74         DRM_FORMAT_XRGB1555,
  75         DRM_FORMAT_RGB565,
  76         DRM_FORMAT_XRGB8888,
  77         DRM_FORMAT_ARGB8888,
  78 };
  79
  80 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  81         DRM_PLANE_TYPE_PRIMARY,
  82         DRM_PLANE_TYPE_OVERLAY,
  83         DRM_PLANE_TYPE_CURSOR,
  84 };
  85
  86 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  87                                   u32 val)
  88 {
  89         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  90         writel(val, ctx->addr + reg);
  91 }
  92
  93 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  94 {
  95         struct decon_context *ctx = crtc->ctx;
  96         u32 val;
  97
  98         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  99                 return -EPERM;
 100
 101         val = VIDINTCON0_INTEN;
 102         if (ctx->out_type & IFTYPE_I80)
 103                 val |= VIDINTCON0_FRAMEDONE;
 104         else
 105                 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 106
 107         writel(val, ctx->addr + DECON_VIDINTCON0);
 108         set_bit(BIT_IRQS_ENABLED, &ctx->flags);
 109
 110         return 0;
 111 }
 112
 113 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 114 {
 115         struct decon_context *ctx = crtc->ctx;
 116
 117         clear_bit(BIT_IRQS_ENABLED, &ctx->flags);
 118         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 119                 return;
 120
 121         writel(0, ctx->addr + DECON_VIDINTCON0);
 122 }
 123
 124 /* return number of starts/ends of frame transmissions since reset */
 125 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
 126 {
 127         u32 frm, pfrm, status, cnt = 2;
 128
 129         /* To get consistent result repeat read until frame id is stable.
 130          * Usually the loop will be executed once, in rare cases when the loop
 131          * is executed at frame change time 2nd pass will be needed.
 132          */
 133         frm = readl(ctx->addr + DECON_CRFMID);
 134         do {
 135                 status = readl(ctx->addr + DECON_VIDCON1);
 136                 pfrm = frm;
 137                 frm = readl(ctx->addr + DECON_CRFMID);
 138         } while (frm != pfrm && --cnt);
 139
 140         /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
 141          * of RGB, it should be taken into account.
 142          */
 143         if (!frm)
 144                 return 0;
 145
 146         switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
 147         case VIDCON1_VSTATUS_VS:
 148                 if (!(ctx->out_type & IFTYPE_I80))
 149                         --frm;
 150                 break;
 151         case VIDCON1_VSTATUS_BP:
 152                 --frm;
 153                 break;
 154         case VIDCON1_I80_ACTIVE:
 155         case VIDCON1_VSTATUS_AC:
 156                 if (end)
 157                         --frm;
 158                 break;
 159         default:
 160                 break;
 161         }
 162
 163         return frm;
 164 }
 165
 166 static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
 167 {
 168         struct decon_context *ctx = crtc->ctx;
 169
 170         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 171                 return 0;
 172
 173         return decon_get_frame_count(ctx, false);
 174 }
 175
 176 static void decon_setup_trigger(struct decon_context *ctx)
 177 {
 178         if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
 179                 return;
 180
 181         if (!(ctx->out_type & I80_HW_TRG)) {
 182                 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 183                        TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 184                        ctx->addr + DECON_TRIGCON);
 185                 return;
 186         }
 187
 188         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 189                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 190
 191         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 192                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 193                 DRM_ERROR("Cannot update sysreg.\n");
 194 }
 195
 196 static void decon_commit(struct exynos_drm_crtc *crtc)
 197 {
 198         struct decon_context *ctx = crtc->ctx;
 199         struct drm_display_mode *m = &crtc->base.mode;
 200         bool interlaced = false;
 201         u32 val;
 202
 203         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 204                 return;
 205
 206         if (ctx->out_type & IFTYPE_HDMI) {
 207                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 208                 m->crtc_hsync_end = m->crtc_htotal - 92;
 209                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 210                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 211                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 212                         interlaced = true;
 213         }
 214
 215         decon_setup_trigger(ctx);
 216
 217         /* lcd on and use command if */
 218         val = VIDOUT_LCD_ON;
 219         if (interlaced)
 220                 val |= VIDOUT_INTERLACE_EN_F;
 221         if (ctx->out_type & IFTYPE_I80) {
 222                 val |= VIDOUT_COMMAND_IF;
 223         } else {
 224                 val |= VIDOUT_RGB_IF;
 225         }
 226
 227         writel(val, ctx->addr + DECON_VIDOUTCON0);
 228
 229         if (interlaced)
 230                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 231                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 232         else
 233                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 234                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 235         writel(val, ctx->addr + DECON_VIDTCON2);
 236
 237         if (!(ctx->out_type & IFTYPE_I80)) {
 238                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 239                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 240
 241                 if (interlaced)
 242                         vbp = vbp / 2 - 1;
 243                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 244                 writel(val, ctx->addr + DECON_VIDTCON00);
 245
 246                 val = VIDTCON01_VSPW_F(
 247                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 248                 writel(val, ctx->addr + DECON_VIDTCON01);
 249
 250                 val = VIDTCON10_HBPD_F(
 251                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 252                         VIDTCON10_HFPD_F(
 253                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 254                 writel(val, ctx->addr + DECON_VIDTCON10);
 255
 256                 val = VIDTCON11_HSPW_F(
 257                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 258                 writel(val, ctx->addr + DECON_VIDTCON11);
 259         }
 260
 261         /* enable output and display signal */
 262         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 263
 264         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 265 }
 266
 267 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 268                                  struct drm_framebuffer *fb)
 269 {
 270         unsigned long val;
 271
 272         val = readl(ctx->addr + DECON_WINCONx(win));
 273         val &= ~WINCONx_BPPMODE_MASK;
 274
 275         switch (fb->format->format) {
 276         case DRM_FORMAT_XRGB1555:
 277                 val |= WINCONx_BPPMODE_16BPP_I1555;
 278                 val |= WINCONx_HAWSWP_F;
 279                 val |= WINCONx_BURSTLEN_16WORD;
 280                 break;
 281         case DRM_FORMAT_RGB565:
 282                 val |= WINCONx_BPPMODE_16BPP_565;
 283                 val |= WINCONx_HAWSWP_F;
 284                 val |= WINCONx_BURSTLEN_16WORD;
 285                 break;
 286         case DRM_FORMAT_XRGB8888:
 287                 val |= WINCONx_BPPMODE_24BPP_888;
 288                 val |= WINCONx_WSWP_F;
 289                 val |= WINCONx_BURSTLEN_16WORD;
 290                 break;
 291         case DRM_FORMAT_ARGB8888:
 292                 val |= WINCONx_BPPMODE_32BPP_A8888;
 293                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 294                 val |= WINCONx_BURSTLEN_16WORD;
 295                 break;
 296         default:
 297                 DRM_ERROR("Proper pixel format is not set\n");
 298                 return;
 299         }
 300
 301         DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
 302
 303         /*
 304          * In case of exynos, setting dma-burst to 16Word causes permanent
 305          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 306          * switching which is based on plane size is not recommended as
 307          * plane size varies a lot towards the end of the screen and rapid
 308          * movement causes unstable DMA which results into iommu crash/tear.
 309          */
 310
 311         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 312                 val &= ~WINCONx_BURSTLEN_MASK;
 313                 val |= WINCONx_BURSTLEN_8WORD;
 314         }
 315
 316         writel(val, ctx->addr + DECON_WINCONx(win));
 317 }
 318
 319 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
 320 {
 321         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
 322                        protect ? ~0 : 0);
 323 }
 324
 325 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 326 {
 327         struct decon_context *ctx = crtc->ctx;
 328
 329         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 330                 return;
 331
 332         decon_shadow_protect(ctx, true);
 333 }
 334
 335 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 336 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 337 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 338
 339 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 340                                struct exynos_drm_plane *plane)
 341 {
 342         struct exynos_drm_plane_state *state =
 343                                 to_exynos_plane_state(plane->base.state);
 344         struct decon_context *ctx = crtc->ctx;
 345         struct drm_framebuffer *fb = state->base.fb;
 346         unsigned int win = plane->index;
 347         unsigned int bpp = fb->format->cpp[0];
 348         unsigned int pitch = fb->pitches[0];
 349         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 350         u32 val;
 351
 352         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 353                 return;
 354
 355         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 356                 val = COORDINATE_X(state->crtc.x) |
 357                         COORDINATE_Y(state->crtc.y / 2);
 358                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 359
 360                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 361                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 362                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 363         } else {
 364                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 365                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 366
 367                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 368                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 369                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 370         }
 371
 372         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 373                 VIDOSD_Wx_ALPHA_B_F(0x0);
 374         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 375
 376         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 377                 VIDOSD_Wx_ALPHA_B_F(0x0);
 378         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 379
 380         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 381
 382         val = dma_addr + pitch * state->src.h;
 383         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 384
 385         if (!(ctx->out_type & IFTYPE_HDMI))
 386                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 387                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 388         else
 389                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 390                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 391         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 392
 393         decon_win_set_pixfmt(ctx, win, fb);
 394
 395         /* window enable */
 396         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 397 }
 398
 399 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 400                                 struct exynos_drm_plane *plane)
 401 {
 402         struct decon_context *ctx = crtc->ctx;
 403         unsigned int win = plane->index;
 404
 405         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 406                 return;
 407
 408         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 409 }
 410
 411 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 412 {
 413         struct decon_context *ctx = crtc->ctx;
 414         unsigned long flags;
 415
 416         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 417                 return;
 418
 419         spin_lock_irqsave(&ctx->vblank_lock, flags);
 420
 421         decon_shadow_protect(ctx, false);
 422
 423         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 424
 425         if (ctx->out_type & IFTYPE_I80)
 426                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 427
 428         ctx->frame_id = decon_get_frame_count(ctx, true);
 429
 430         exynos_crtc_handle_event(crtc);
 431
 432         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 433 }
 434
 435 static void decon_swreset(struct decon_context *ctx)
 436 {
 437         unsigned int tries;
 438         unsigned long flags;
 439
 440         writel(0, ctx->addr + DECON_VIDCON0);
 441         for (tries = 2000; tries; --tries) {
 442                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 443                         break;
 444                 udelay(10);
 445         }
 446
 447         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 448         for (tries = 2000; tries; --tries) {
 449                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 450                         break;
 451                 udelay(10);
 452         }
 453
 454         WARN(tries == 0, "failed to software reset DECON\n");
 455
 456         spin_lock_irqsave(&ctx->vblank_lock, flags);
 457         ctx->frame_id = 0;
 458         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 459
 460         if (!(ctx->out_type & IFTYPE_HDMI))
 461                 return;
 462
 463         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 464         decon_set_bits(ctx, DECON_CMU,
 465                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 466         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 467         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 468                ctx->addr + DECON_CRCCTRL);
 469 }
 470
 471 static void decon_enable(struct exynos_drm_crtc *crtc)
 472 {
 473         struct decon_context *ctx = crtc->ctx;
 474
 475         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 476                 return;
 477
 478         pm_runtime_get_sync(ctx->dev);
 479
 480         exynos_drm_pipe_clk_enable(crtc, true);
 481
 482         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 483
 484         decon_swreset(ctx);
 485
 486         decon_commit(ctx->crtc);
 487 }
 488
 489 static void decon_disable(struct exynos_drm_crtc *crtc)
 490 {
 491         struct decon_context *ctx = crtc->ctx;
 492         int i;
 493
 494         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 495                 return;
 496
 497         /*
 498          * We need to make sure that all windows are disabled before we
 499          * suspend that connector. Otherwise we might try to scan from
 500          * a destroyed buffer later.
 501          */
 502         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 503                 decon_disable_plane(crtc, &ctx->planes[i]);
 504
 505         decon_swreset(ctx);
 506
 507         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 508
 509         exynos_drm_pipe_clk_enable(crtc, false);
 510
 511         pm_runtime_put_sync(ctx->dev);
 512
 513         set_bit(BIT_SUSPENDED, &ctx->flags);
 514 }
 515
 516 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 517 {
 518         struct decon_context *ctx = crtc->ctx;
 519
 520         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 521             (ctx->out_type & I80_HW_TRG))
 522                 return;
 523
 524         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags) ||
 525             test_bit(BIT_IRQS_ENABLED, &ctx->flags))
 526                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 527 }
 528
 529 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 530 {
 531         struct decon_context *ctx = crtc->ctx;
 532         int win, i, ret;
 533
 534         DRM_DEBUG_KMS("%s\n", __FILE__);
 535
 536         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 537                 ret = clk_prepare_enable(ctx->clks[i]);
 538                 if (ret < 0)
 539                         goto err;
 540         }
 541
 542         decon_shadow_protect(ctx, true);
 543         for (win = 0; win < WINDOWS_NR; win++)
 544                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 545         decon_shadow_protect(ctx, false);
 546
 547         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 548
 549         /* TODO: wait for possible vsync */
 550         msleep(50);
 551
 552 err:
 553         while (--i >= 0)
 554                 clk_disable_unprepare(ctx->clks[i]);
 555 }
 556
 557 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 558         .enable                 = decon_enable,
 559         .disable                = decon_disable,
 560         .enable_vblank          = decon_enable_vblank,
 561         .disable_vblank         = decon_disable_vblank,
 562         .get_vblank_counter     = decon_get_vblank_counter,
 563         .atomic_begin           = decon_atomic_begin,
 564         .update_plane           = decon_update_plane,
 565         .disable_plane          = decon_disable_plane,
 566         .atomic_flush           = decon_atomic_flush,
 567         .te_handler             = decon_te_irq_handler,
 568 };
 569
 570 static int decon_bind(struct device *dev, struct device *master, void *data)
 571 {
 572         struct decon_context *ctx = dev_get_drvdata(dev);
 573         struct drm_device *drm_dev = data;
 574         struct exynos_drm_plane *exynos_plane;
 575         enum exynos_drm_output_type out_type;
 576         unsigned int win;
 577         int ret;
 578
 579         ctx->drm_dev = drm_dev;
 580         drm_dev->max_vblank_count = 0xffffffff;
 581
 582         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 583                 int tmp = (win == ctx->first_win) ? 0 : win;
 584
 585                 ctx->configs[win].pixel_formats = decon_formats;
 586                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 587                 ctx->configs[win].zpos = win;
 588                 ctx->configs[win].type = decon_win_types[tmp];
 589
 590                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 591                                         &ctx->configs[win]);
 592                 if (ret)
 593                         return ret;
 594         }
 595
 596         exynos_plane = &ctx->planes[ctx->first_win];
 597         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 598                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 599         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 600                         out_type, &decon_crtc_ops, ctx);
 601         if (IS_ERR(ctx->crtc))
 602                 return PTR_ERR(ctx->crtc);
 603
 604         decon_clear_channels(ctx->crtc);
 605
 606         return drm_iommu_attach_device(drm_dev, dev);
 607 }
 608
 609 static void decon_unbind(struct device *dev, struct device *master, void *data)
 610 {
 611         struct decon_context *ctx = dev_get_drvdata(dev);
 612
 613         decon_disable(ctx->crtc);
 614
 615         /* detach this sub driver from iommu mapping if supported. */
 616         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 617 }
 618
 619 static const struct component_ops decon_component_ops = {
 620         .bind   = decon_bind,
 621         .unbind = decon_unbind,
 622 };
 623
 624 static void decon_handle_vblank(struct decon_context *ctx)
 625 {
 626         u32 frm;
 627
 628         spin_lock(&ctx->vblank_lock);
 629
 630         frm = decon_get_frame_count(ctx, true);
 631
 632         if (frm != ctx->frame_id) {
 633                 /* handle only if incremented, take care of wrap-around */
 634                 if ((s32)(frm - ctx->frame_id) > 0)
 635                         drm_crtc_handle_vblank(&ctx->crtc->base);
 636                 ctx->frame_id = frm;
 637         }
 638
 639         spin_unlock(&ctx->vblank_lock);
 640 }
 641
 642 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 643 {
 644         struct decon_context *ctx = dev_id;
 645         u32 val;
 646
 647         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 648                 goto out;
 649
 650         val = readl(ctx->addr + DECON_VIDINTCON1);
 651         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 652
 653         if (val) {
 654                 writel(val, ctx->addr + DECON_VIDINTCON1);
 655                 if (ctx->out_type & IFTYPE_HDMI) {
 656                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 657                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 658                         if (val ==
 659                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 660                                 return IRQ_HANDLED;
 661                 }
 662                 decon_handle_vblank(ctx);
 663         }
 664
 665 out:
 666         return IRQ_HANDLED;
 667 }
 668
 669 #ifdef CONFIG_PM
 670 static int exynos5433_decon_suspend(struct device *dev)
 671 {
 672         struct decon_context *ctx = dev_get_drvdata(dev);
 673         int i = ARRAY_SIZE(decon_clks_name);
 674
 675         while (--i >= 0)
 676                 clk_disable_unprepare(ctx->clks[i]);
 677
 678         return 0;
 679 }
 680
 681 static int exynos5433_decon_resume(struct device *dev)
 682 {
 683         struct decon_context *ctx = dev_get_drvdata(dev);
 684         int i, ret;
 685
 686         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 687                 ret = clk_prepare_enable(ctx->clks[i]);
 688                 if (ret < 0)
 689                         goto err;
 690         }
 691
 692         return 0;
 693
 694 err:
 695         while (--i >= 0)
 696                 clk_disable_unprepare(ctx->clks[i]);
 697
 698         return ret;
 699 }
 700 #endif
 701
 702 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 703         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 704                            NULL)
 705 };
 706
 707 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 708         {
 709                 .compatible = "samsung,exynos5433-decon",
 710                 .data = (void *)I80_HW_TRG
 711         },
 712         {
 713                 .compatible = "samsung,exynos5433-decon-tv",
 714                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 715         },
 716         {},
 717 };
 718 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 719
 720 static int exynos5433_decon_probe(struct platform_device *pdev)
 721 {
 722         struct device *dev = &pdev->dev;
 723         struct decon_context *ctx;
 724         struct resource *res;
 725         int ret;
 726         int i;
 727
 728         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 729         if (!ctx)
 730                 return -ENOMEM;
 731
 732         __set_bit(BIT_SUSPENDED, &ctx->flags);
 733         ctx->dev = dev;
 734         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 735         spin_lock_init(&ctx->vblank_lock);
 736
 737         if (ctx->out_type & IFTYPE_HDMI) {
 738                 ctx->first_win = 1;
 739         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 740                 ctx->out_type |= IFTYPE_I80;
 741         }
 742
 743         if (ctx->out_type & I80_HW_TRG) {
 744                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 745                                                         "samsung,disp-sysreg");
 746                 if (IS_ERR(ctx->sysreg)) {
 747                         dev_err(dev, "failed to get system register\n");
 748                         return PTR_ERR(ctx->sysreg);
 749                 }
 750         }
 751
 752         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 753                 struct clk *clk;
 754
 755                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 756                 if (IS_ERR(clk))
 757                         return PTR_ERR(clk);
 758
 759                 ctx->clks[i] = clk;
 760         }
 761
 762         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 763         if (!res) {
 764                 dev_err(dev, "cannot find IO resource\n");
 765                 return -ENXIO;
 766         }
 767
 768         ctx->addr = devm_ioremap_resource(dev, res);
 769         if (IS_ERR(ctx->addr)) {
 770                 dev_err(dev, "ioremap failed\n");
 771                 return PTR_ERR(ctx->addr);
 772         }
 773
 774         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 775                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 776         if (!res) {
 777                 dev_err(dev, "cannot find IRQ resource\n");
 778                 return -ENXIO;
 779         }
 780
 781         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 782                                "drm_decon", ctx);
 783         if (ret < 0) {
 784                 dev_err(dev, "lcd_sys irq request failed\n");
 785                 return ret;
 786         }
 787
 788         platform_set_drvdata(pdev, ctx);
 789
 790         pm_runtime_enable(dev);
 791
 792         ret = component_add(dev, &decon_component_ops);
 793         if (ret)
 794                 goto err_disable_pm_runtime;
 795
 796         return 0;
 797
 798 err_disable_pm_runtime:
 799         pm_runtime_disable(dev);
 800
 801         return ret;
 802 }
 803
 804 static int exynos5433_decon_remove(struct platform_device *pdev)
 805 {
 806         pm_runtime_disable(&pdev->dev);
 807
 808         component_del(&pdev->dev, &decon_component_ops);
 809
 810         return 0;
 811 }
 812
 813 struct platform_driver exynos5433_decon_driver = {
 814         .probe          = exynos5433_decon_probe,
 815         .remove         = exynos5433_decon_remove,
 816         .driver         = {
 817                 .name   = "exynos5433-decon",
 818                 .pm     = &exynos5433_decon_pm_ops,
 819                 .of_match_table = exynos5433_decon_driver_dt_match,
 820         },
 821 };