2 * Copyright (C) 2015 Etnaviv Project
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef __ETNAVIV_GPU_H__
18 #define __ETNAVIV_GPU_H__
20 #include <linux/clk.h>
21 #include <linux/regulator/consumer.h>
23 #include "etnaviv_drv.h"
25 struct etnaviv_gem_submit;
26 struct etnaviv_vram_mapping;
28 struct etnaviv_chip_identity {
35 /* Supported feature fields. */
38 /* Supported minor feature fields. */
41 /* Supported minor feature 1 fields. */
44 /* Supported minor feature 2 fields. */
47 /* Supported minor feature 3 fields. */
50 /* Supported minor feature 4 fields. */
53 /* Supported minor feature 5 fields. */
56 /* Number of streams supported. */
59 /* Total number of temporary registers per thread. */
62 /* Maximum number of threads. */
65 /* Number of shader cores. */
66 u32 shader_core_count;
68 /* Size of the vertex cache. */
69 u32 vertex_cache_size;
71 /* Number of entries in the vertex output buffer. */
72 u32 vertex_output_buffer_size;
74 /* Number of pixel pipes. */
77 /* Number of instructions. */
78 u32 instruction_count;
80 /* Number of constants. */
86 /* Number of varyings */
90 struct etnaviv_event {
91 struct dma_fence *fence;
92 struct etnaviv_cmdbuf *cmdbuf;
94 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
97 struct etnaviv_cmdbuf_suballoc;
98 struct etnaviv_cmdbuf;
100 #define ETNA_NR_EVENTS 30
103 struct drm_device *drm;
104 struct thermal_cooling_device *cooling;
107 struct etnaviv_chip_identity identity;
108 struct etnaviv_file_private *lastctx;
109 struct workqueue_struct *wq;
112 struct etnaviv_cmdbuf *buffer;
115 /* bus base address of memory */
118 /* event management: */
119 DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
120 struct etnaviv_event event[ETNA_NR_EVENTS];
121 struct completion event_free;
122 spinlock_t event_spinlock;
124 /* list of currently in-flight command buffers */
125 struct list_head active_cmd_list;
129 /* Fencing support */
134 wait_queue_head_t fence_event;
136 spinlock_t fence_spinlock;
138 /* worker for handling active-list retiring: */
139 struct work_struct retire_work;
141 /* worker for handling 'sync' points: */
142 struct work_struct sync_point_work;
143 int sync_point_event;
148 struct etnaviv_iommu *mmu;
149 struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;
153 struct clk *clk_core;
154 struct clk *clk_shader;
157 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */
158 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD)
159 struct timer_list hangcheck_timer;
161 u32 hangcheck_dma_addr;
162 struct work_struct recover_work;
163 unsigned int freq_scale;
164 unsigned long base_rate_core;
165 unsigned long base_rate_shader;
168 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
170 etnaviv_writel(data, gpu->mmio + reg);
173 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
175 return etnaviv_readl(gpu->mmio + reg);
178 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
180 return fence_after_eq(gpu->completed_fence, fence);
183 static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence)
185 return fence_after_eq(gpu->retired_fence, fence);
188 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
190 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
192 #ifdef CONFIG_DEBUG_FS
193 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
196 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
197 unsigned int context, bool exclusive, bool implicit);
199 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
200 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
201 u32 fence, struct timespec *timeout);
202 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
203 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
204 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
205 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf);
206 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
207 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
208 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
209 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
211 extern struct platform_driver etnaviv_gpu_driver;
213 #endif /* __ETNAVIV_GPU_H__ */