drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/component.h>
  18 #include <linux/dma-fence.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/of_device.h>
  21 #include <linux/thermal.h>
  22
  23 #include "etnaviv_cmdbuf.h"
  24 #include "etnaviv_dump.h"
  25 #include "etnaviv_gpu.h"
  26 #include "etnaviv_gem.h"
  27 #include "etnaviv_mmu.h"
  28 #include "etnaviv_perfmon.h"
  29 #include "common.xml.h"
  30 #include "state.xml.h"
  31 #include "state_hi.xml.h"
  32 #include "cmdstream.xml.h"
  33
  34 #ifndef PHYS_OFFSET
  35 #define PHYS_OFFSET 0
  36 #endif
  37
  38 static const struct platform_device_id gpu_ids[] = {
  39         { .name = "etnaviv-gpu,2d" },
  40         { },
  41 };
  42
  43 static bool etnaviv_dump_core = true;
  44 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
  45
  46 /*
  47  * Driver functions:
  48  */
  49
  50 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  51 {
  52         switch (param) {
  53         case ETNAVIV_PARAM_GPU_MODEL:
  54                 *value = gpu->identity.model;
  55                 break;
  56
  57         case ETNAVIV_PARAM_GPU_REVISION:
  58                 *value = gpu->identity.revision;
  59                 break;
  60
  61         case ETNAVIV_PARAM_GPU_FEATURES_0:
  62                 *value = gpu->identity.features;
  63                 break;
  64
  65         case ETNAVIV_PARAM_GPU_FEATURES_1:
  66                 *value = gpu->identity.minor_features0;
  67                 break;
  68
  69         case ETNAVIV_PARAM_GPU_FEATURES_2:
  70                 *value = gpu->identity.minor_features1;
  71                 break;
  72
  73         case ETNAVIV_PARAM_GPU_FEATURES_3:
  74                 *value = gpu->identity.minor_features2;
  75                 break;
  76
  77         case ETNAVIV_PARAM_GPU_FEATURES_4:
  78                 *value = gpu->identity.minor_features3;
  79                 break;
  80
  81         case ETNAVIV_PARAM_GPU_FEATURES_5:
  82                 *value = gpu->identity.minor_features4;
  83                 break;
  84
  85         case ETNAVIV_PARAM_GPU_FEATURES_6:
  86                 *value = gpu->identity.minor_features5;
  87                 break;
  88
  89         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
  90                 *value = gpu->identity.stream_count;
  91                 break;
  92
  93         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
  94                 *value = gpu->identity.register_max;
  95                 break;
  96
  97         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
  98                 *value = gpu->identity.thread_count;
  99                 break;
 100
 101         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
 102                 *value = gpu->identity.vertex_cache_size;
 103                 break;
 104
 105         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 106                 *value = gpu->identity.shader_core_count;
 107                 break;
 108
 109         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 110                 *value = gpu->identity.pixel_pipes;
 111                 break;
 112
 113         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 114                 *value = gpu->identity.vertex_output_buffer_size;
 115                 break;
 116
 117         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 118                 *value = gpu->identity.buffer_size;
 119                 break;
 120
 121         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 122                 *value = gpu->identity.instruction_count;
 123                 break;
 124
 125         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 126                 *value = gpu->identity.num_constants;
 127                 break;
 128
 129         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 130                 *value = gpu->identity.varyings_count;
 131                 break;
 132
 133         default:
 134                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 135                 return -EINVAL;
 136         }
 137
 138         return 0;
 139 }
 140
 141
 142 #define etnaviv_is_model_rev(gpu, mod, rev) \
 143         ((gpu)->identity.model == chipModel_##mod && \
 144          (gpu)->identity.revision == rev)
 145 #define etnaviv_field(val, field) \
 146         (((val) & field##__MASK) >> field##__SHIFT)
 147
 148 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 149 {
 150         if (gpu->identity.minor_features0 &
 151             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 152                 u32 specs[4];
 153                 unsigned int streams;
 154
 155                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 156                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 157                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 158                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 159
 160                 gpu->identity.stream_count = etnaviv_field(specs[0],
 161                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 162                 gpu->identity.register_max = etnaviv_field(specs[0],
 163                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 164                 gpu->identity.thread_count = etnaviv_field(specs[0],
 165                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 166                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 167                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 168                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 169                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 170                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 171                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 172                 gpu->identity.vertex_output_buffer_size =
 173                         etnaviv_field(specs[0],
 174                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 175
 176                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 177                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 178                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 179                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 180                 gpu->identity.num_constants = etnaviv_field(specs[1],
 181                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 182
 183                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 184                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 185
 186                 /* This overrides the value from older register if non-zero */
 187                 streams = etnaviv_field(specs[3],
 188                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 189                 if (streams)
 190                         gpu->identity.stream_count = streams;
 191         }
 192
 193         /* Fill in the stream count if not specified */
 194         if (gpu->identity.stream_count == 0) {
 195                 if (gpu->identity.model >= 0x1000)
 196                         gpu->identity.stream_count = 4;
 197                 else
 198                         gpu->identity.stream_count = 1;
 199         }
 200
 201         /* Convert the register max value */
 202         if (gpu->identity.register_max)
 203                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 204         else if (gpu->identity.model == chipModel_GC400)
 205                 gpu->identity.register_max = 32;
 206         else
 207                 gpu->identity.register_max = 64;
 208
 209         /* Convert thread count */
 210         if (gpu->identity.thread_count)
 211                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 212         else if (gpu->identity.model == chipModel_GC400)
 213                 gpu->identity.thread_count = 64;
 214         else if (gpu->identity.model == chipModel_GC500 ||
 215                  gpu->identity.model == chipModel_GC530)
 216                 gpu->identity.thread_count = 128;
 217         else
 218                 gpu->identity.thread_count = 256;
 219
 220         if (gpu->identity.vertex_cache_size == 0)
 221                 gpu->identity.vertex_cache_size = 8;
 222
 223         if (gpu->identity.shader_core_count == 0) {
 224                 if (gpu->identity.model >= 0x1000)
 225                         gpu->identity.shader_core_count = 2;
 226                 else
 227                         gpu->identity.shader_core_count = 1;
 228         }
 229
 230         if (gpu->identity.pixel_pipes == 0)
 231                 gpu->identity.pixel_pipes = 1;
 232
 233         /* Convert virtex buffer size */
 234         if (gpu->identity.vertex_output_buffer_size) {
 235                 gpu->identity.vertex_output_buffer_size =
 236                         1 << gpu->identity.vertex_output_buffer_size;
 237         } else if (gpu->identity.model == chipModel_GC400) {
 238                 if (gpu->identity.revision < 0x4000)
 239                         gpu->identity.vertex_output_buffer_size = 512;
 240                 else if (gpu->identity.revision < 0x4200)
 241                         gpu->identity.vertex_output_buffer_size = 256;
 242                 else
 243                         gpu->identity.vertex_output_buffer_size = 128;
 244         } else {
 245                 gpu->identity.vertex_output_buffer_size = 512;
 246         }
 247
 248         switch (gpu->identity.instruction_count) {
 249         case 0:
 250                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 251                     gpu->identity.model == chipModel_GC880)
 252                         gpu->identity.instruction_count = 512;
 253                 else
 254                         gpu->identity.instruction_count = 256;
 255                 break;
 256
 257         case 1:
 258                 gpu->identity.instruction_count = 1024;
 259                 break;
 260
 261         case 2:
 262                 gpu->identity.instruction_count = 2048;
 263                 break;
 264
 265         default:
 266                 gpu->identity.instruction_count = 256;
 267                 break;
 268         }
 269
 270         if (gpu->identity.num_constants == 0)
 271                 gpu->identity.num_constants = 168;
 272
 273         if (gpu->identity.varyings_count == 0) {
 274                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 275                         gpu->identity.varyings_count = 12;
 276                 else
 277                         gpu->identity.varyings_count = 8;
 278         }
 279
 280         /*
 281          * For some cores, two varyings are consumed for position, so the
 282          * maximum varying count needs to be reduced by one.
 283          */
 284         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 285             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 286             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 287             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 288             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 289             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 290             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 291             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 292             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 293             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 294             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 295                 gpu->identity.varyings_count -= 1;
 296 }
 297
 298 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 299 {
 300         u32 chipIdentity;
 301
 302         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 303
 304         /* Special case for older graphic cores. */
 305         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 306                 gpu->identity.model    = chipModel_GC500;
 307                 gpu->identity.revision = etnaviv_field(chipIdentity,
 308                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 309         } else {
 310
 311                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 312                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 313
 314                 /*
 315                  * !!!! HACK ALERT !!!!
 316                  * Because people change device IDs without letting software
 317                  * know about it - here is the hack to make it all look the
 318                  * same.  Only for GC400 family.
 319                  */
 320                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 321                     gpu->identity.model != chipModel_GC420) {
 322                         gpu->identity.model = gpu->identity.model & 0x0400;
 323                 }
 324
 325                 /* Another special case */
 326                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 327                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 328                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 329
 330                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 331                                 /*
 332                                  * This IP has an ECO; put the correct
 333                                  * revision in it.
 334                                  */
 335                                 gpu->identity.revision = 0x1051;
 336                         }
 337                 }
 338
 339                 /*
 340                  * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 341                  * reality it's just a re-branded GC3000. We can identify this
 342                  * core by the upper half of the revision register being all 1.
 343                  * Fix model/rev here, so all other places can refer to this
 344                  * core by its real identity.
 345                  */
 346                 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
 347                         gpu->identity.model = chipModel_GC3000;
 348                         gpu->identity.revision &= 0xffff;
 349                 }
 350         }
 351
 352         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 353                  gpu->identity.model, gpu->identity.revision);
 354
 355         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 356
 357         /* Disable fast clear on GC700. */
 358         if (gpu->identity.model == chipModel_GC700)
 359                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 360
 361         if ((gpu->identity.model == chipModel_GC500 &&
 362              gpu->identity.revision < 2) ||
 363             (gpu->identity.model == chipModel_GC300 &&
 364              gpu->identity.revision < 0x2000)) {
 365
 366                 /*
 367                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 368                  * registers.
 369                  */
 370                 gpu->identity.minor_features0 = 0;
 371                 gpu->identity.minor_features1 = 0;
 372                 gpu->identity.minor_features2 = 0;
 373                 gpu->identity.minor_features3 = 0;
 374                 gpu->identity.minor_features4 = 0;
 375                 gpu->identity.minor_features5 = 0;
 376         } else
 377                 gpu->identity.minor_features0 =
 378                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 379
 380         if (gpu->identity.minor_features0 &
 381             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 382                 gpu->identity.minor_features1 =
 383                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 384                 gpu->identity.minor_features2 =
 385                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 386                 gpu->identity.minor_features3 =
 387                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 388                 gpu->identity.minor_features4 =
 389                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 390                 gpu->identity.minor_features5 =
 391                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 392         }
 393
 394         /* GC600 idle register reports zero bits where modules aren't present */
 395         if (gpu->identity.model == chipModel_GC600) {
 396                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 397                                  VIVS_HI_IDLE_STATE_RA |
 398                                  VIVS_HI_IDLE_STATE_SE |
 399                                  VIVS_HI_IDLE_STATE_PA |
 400                                  VIVS_HI_IDLE_STATE_SH |
 401                                  VIVS_HI_IDLE_STATE_PE |
 402                                  VIVS_HI_IDLE_STATE_DE |
 403                                  VIVS_HI_IDLE_STATE_FE;
 404         } else {
 405                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 406         }
 407
 408         etnaviv_hw_specs(gpu);
 409 }
 410
 411 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 412 {
 413         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 414                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 415         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 416 }
 417
 418 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 419 {
 420         if (gpu->identity.minor_features2 &
 421             chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
 422                 clk_set_rate(gpu->clk_core,
 423                              gpu->base_rate_core >> gpu->freq_scale);
 424                 clk_set_rate(gpu->clk_shader,
 425                              gpu->base_rate_shader >> gpu->freq_scale);
 426         } else {
 427                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 428                 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 429
 430                 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
 431                 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 432                 etnaviv_gpu_load_clock(gpu, clock);
 433         }
 434 }
 435
 436 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 437 {
 438         u32 control, idle;
 439         unsigned long timeout;
 440         bool failed = true;
 441
 442         /* We hope that the GPU resets in under one second */
 443         timeout = jiffies + msecs_to_jiffies(1000);
 444
 445         while (time_is_after_jiffies(timeout)) {
 446                 /* enable clock */
 447                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 448                 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 449                 etnaviv_gpu_load_clock(gpu, control);
 450
 451                 /* isolate the GPU. */
 452                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 453                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 454
 455                 /* set soft reset. */
 456                 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 457                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 458
 459                 /* wait for reset. */
 460                 usleep_range(10, 20);
 461
 462                 /* reset soft reset bit. */
 463                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 464                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 465
 466                 /* reset GPU isolation. */
 467                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 468                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 469
 470                 /* read idle register. */
 471                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 472
 473                 /* try reseting again if FE it not idle */
 474                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 475                         dev_dbg(gpu->dev, "FE is not idle\n");
 476                         continue;
 477                 }
 478
 479                 /* read reset register. */
 480                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 481
 482                 /* is the GPU idle? */
 483                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 484                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 485                         dev_dbg(gpu->dev, "GPU is not idle\n");
 486                         continue;
 487                 }
 488
 489                 /* disable debug registers, as they are not normally needed */
 490                 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
 491                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 492
 493                 failed = false;
 494                 break;
 495         }
 496
 497         if (failed) {
 498                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 499                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 500
 501                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 502                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 503                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 504                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 505
 506                 return -EBUSY;
 507         }
 508
 509         /* We rely on the GPU running, so program the clock */
 510         etnaviv_gpu_update_clock(gpu);
 511
 512         return 0;
 513 }
 514
 515 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 516 {
 517         u32 pmc, ppc;
 518
 519         /* enable clock gating */
 520         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
 521         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 522
 523         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 524         if (gpu->identity.revision == 0x4301 ||
 525             gpu->identity.revision == 0x4302)
 526                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 527
 528         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 529
 530         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 531
 532         /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
 533         if (gpu->identity.model >= chipModel_GC400 &&
 534             gpu->identity.model != chipModel_GC420 &&
 535             !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
 536                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 537
 538         /*
 539          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 540          * present without a bug fix.
 541          */
 542         if (gpu->identity.revision < 0x5000 &&
 543             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 544             !(gpu->identity.minor_features1 &
 545               chipMinorFeatures1_DISABLE_PE_GATING))
 546                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 547
 548         if (gpu->identity.revision < 0x5422)
 549                 pmc |= BIT(15); /* Unknown bit */
 550
 551         /* Disable TX clock gating on affected core revisions. */
 552         if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 553             etnaviv_is_model_rev(gpu, GC2000, 0x5108))
 554                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
 555
 556         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 557         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 558
 559         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 560 }
 561
 562 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 563 {
 564         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 565         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 566                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 567                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 568 }
 569
 570 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
 571 {
 572         /*
 573          * Base value for VIVS_PM_PULSE_EATER register on models where it
 574          * cannot be read, extracted from vivante kernel driver.
 575          */
 576         u32 pulse_eater = 0x01590880;
 577
 578         if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 579             etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
 580                 pulse_eater |= BIT(23);
 581
 582         }
 583
 584         if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
 585             etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
 586                 pulse_eater &= ~BIT(16);
 587                 pulse_eater |= BIT(17);
 588         }
 589
 590         if ((gpu->identity.revision > 0x5420) &&
 591             (gpu->identity.features & chipFeatures_PIPE_3D))
 592         {
 593                 /* Performance fix: disable internal DFS */
 594                 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
 595                 pulse_eater |= BIT(18);
 596         }
 597
 598         gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 599 }
 600
 601 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 602 {
 603         u16 prefetch;
 604
 605         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 606              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 607             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 608                 u32 mc_memory_debug;
 609
 610                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 611
 612                 if (gpu->identity.revision == 0x5007)
 613                         mc_memory_debug |= 0x0c;
 614                 else
 615                         mc_memory_debug |= 0x08;
 616
 617                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 618         }
 619
 620         /* enable module-level clock gating */
 621         etnaviv_gpu_enable_mlcg(gpu);
 622
 623         /*
 624          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 625          * This is necessary to prevent the iMX6 SoC locking up.
 626          */
 627         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 628                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 629                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 630
 631         /* GC2000 rev 5108 needs a special bus config */
 632         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 633                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 634                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 635                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 636                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 637                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 638                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 639         }
 640
 641         /* setup the pulse eater */
 642         etnaviv_gpu_setup_pulse_eater(gpu);
 643
 644         /* setup the MMU */
 645         etnaviv_iommu_restore(gpu);
 646
 647         /* Start command processor */
 648         prefetch = etnaviv_buffer_init(gpu);
 649
 650         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 651         etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer),
 652                              prefetch);
 653 }
 654
 655 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 656 {
 657         int ret, i;
 658
 659         ret = pm_runtime_get_sync(gpu->dev);
 660         if (ret < 0) {
 661                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 662                 return ret;
 663         }
 664
 665         etnaviv_hw_identify(gpu);
 666
 667         if (gpu->identity.model == 0) {
 668                 dev_err(gpu->dev, "Unknown GPU model\n");
 669                 ret = -ENXIO;
 670                 goto fail;
 671         }
 672
 673         /* Exclude VG cores with FE2.0 */
 674         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 675             gpu->identity.features & chipFeatures_FE20) {
 676                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 677                 ret = -ENXIO;
 678                 goto fail;
 679         }
 680
 681         /*
 682          * Set the GPU linear window to be at the end of the DMA window, where
 683          * the CMA area is likely to reside. This ensures that we are able to
 684          * map the command buffers while having the linear window overlap as
 685          * much RAM as possible, so we can optimize mappings for other buffers.
 686          *
 687          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
 688          * to different views of the memory on the individual engines.
 689          */
 690         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 691             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
 692                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
 693                 if (dma_mask < PHYS_OFFSET + SZ_2G)
 694                         gpu->memory_base = PHYS_OFFSET;
 695                 else
 696                         gpu->memory_base = dma_mask - SZ_2G + 1;
 697         } else if (PHYS_OFFSET >= SZ_2G) {
 698                 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
 699                 gpu->memory_base = PHYS_OFFSET;
 700                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 701         }
 702
 703         ret = etnaviv_hw_reset(gpu);
 704         if (ret) {
 705                 dev_err(gpu->dev, "GPU reset failed\n");
 706                 goto fail;
 707         }
 708
 709         gpu->mmu = etnaviv_iommu_new(gpu);
 710         if (IS_ERR(gpu->mmu)) {
 711                 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
 712                 ret = PTR_ERR(gpu->mmu);
 713                 goto fail;
 714         }
 715
 716         gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
 717         if (IS_ERR(gpu->cmdbuf_suballoc)) {
 718                 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
 719                 ret = PTR_ERR(gpu->cmdbuf_suballoc);
 720                 goto fail;
 721         }
 722
 723         /* Create buffer: */
 724         ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer,
 725                                   PAGE_SIZE);
 726         if (ret) {
 727                 dev_err(gpu->dev, "could not create command buffer\n");
 728                 goto destroy_iommu;
 729         }
 730
 731         if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
 732             etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) {
 733                 ret = -EINVAL;
 734                 dev_err(gpu->dev,
 735                         "command buffer outside valid memory window\n");
 736                 goto free_buffer;
 737         }
 738
 739         /* Setup event management */
 740         spin_lock_init(&gpu->event_spinlock);
 741         init_completion(&gpu->event_free);
 742         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 743         for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
 744                 complete(&gpu->event_free);
 745
 746         /* Now program the hardware */
 747         mutex_lock(&gpu->lock);
 748         etnaviv_gpu_hw_init(gpu);
 749         gpu->exec_state = -1;
 750         mutex_unlock(&gpu->lock);
 751
 752         pm_runtime_mark_last_busy(gpu->dev);
 753         pm_runtime_put_autosuspend(gpu->dev);
 754
 755         return 0;
 756
 757 free_buffer:
 758         etnaviv_cmdbuf_free(&gpu->buffer);
 759 destroy_iommu:
 760         etnaviv_iommu_destroy(gpu->mmu);
 761         gpu->mmu = NULL;
 762 fail:
 763         pm_runtime_mark_last_busy(gpu->dev);
 764         pm_runtime_put_autosuspend(gpu->dev);
 765
 766         return ret;
 767 }
 768
 769 #ifdef CONFIG_DEBUG_FS
 770 struct dma_debug {
 771         u32 address[2];
 772         u32 state[2];
 773 };
 774
 775 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 776 {
 777         u32 i;
 778
 779         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 780         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 781
 782         for (i = 0; i < 500; i++) {
 783                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 784                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 785
 786                 if (debug->address[0] != debug->address[1])
 787                         break;
 788
 789                 if (debug->state[0] != debug->state[1])
 790                         break;
 791         }
 792 }
 793
 794 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 795 {
 796         struct dma_debug debug;
 797         u32 dma_lo, dma_hi, axi, idle;
 798         int ret;
 799
 800         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 801
 802         ret = pm_runtime_get_sync(gpu->dev);
 803         if (ret < 0)
 804                 return ret;
 805
 806         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 807         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 808         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 809         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 810
 811         verify_dma(gpu, &debug);
 812
 813         seq_puts(m, "\tfeatures\n");
 814         seq_printf(m, "\t major_features: 0x%08x\n",
 815                    gpu->identity.features);
 816         seq_printf(m, "\t minor_features0: 0x%08x\n",
 817                    gpu->identity.minor_features0);
 818         seq_printf(m, "\t minor_features1: 0x%08x\n",
 819                    gpu->identity.minor_features1);
 820         seq_printf(m, "\t minor_features2: 0x%08x\n",
 821                    gpu->identity.minor_features2);
 822         seq_printf(m, "\t minor_features3: 0x%08x\n",
 823                    gpu->identity.minor_features3);
 824         seq_printf(m, "\t minor_features4: 0x%08x\n",
 825                    gpu->identity.minor_features4);
 826         seq_printf(m, "\t minor_features5: 0x%08x\n",
 827                    gpu->identity.minor_features5);
 828
 829         seq_puts(m, "\tspecs\n");
 830         seq_printf(m, "\t stream_count:  %d\n",
 831                         gpu->identity.stream_count);
 832         seq_printf(m, "\t register_max: %d\n",
 833                         gpu->identity.register_max);
 834         seq_printf(m, "\t thread_count: %d\n",
 835                         gpu->identity.thread_count);
 836         seq_printf(m, "\t vertex_cache_size: %d\n",
 837                         gpu->identity.vertex_cache_size);
 838         seq_printf(m, "\t shader_core_count: %d\n",
 839                         gpu->identity.shader_core_count);
 840         seq_printf(m, "\t pixel_pipes: %d\n",
 841                         gpu->identity.pixel_pipes);
 842         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 843                         gpu->identity.vertex_output_buffer_size);
 844         seq_printf(m, "\t buffer_size: %d\n",
 845                         gpu->identity.buffer_size);
 846         seq_printf(m, "\t instruction_count: %d\n",
 847                         gpu->identity.instruction_count);
 848         seq_printf(m, "\t num_constants: %d\n",
 849                         gpu->identity.num_constants);
 850         seq_printf(m, "\t varyings_count: %d\n",
 851                         gpu->identity.varyings_count);
 852
 853         seq_printf(m, "\taxi: 0x%08x\n", axi);
 854         seq_printf(m, "\tidle: 0x%08x\n", idle);
 855         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 856         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 857                 seq_puts(m, "\t FE is not idle\n");
 858         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 859                 seq_puts(m, "\t DE is not idle\n");
 860         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 861                 seq_puts(m, "\t PE is not idle\n");
 862         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 863                 seq_puts(m, "\t SH is not idle\n");
 864         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 865                 seq_puts(m, "\t PA is not idle\n");
 866         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 867                 seq_puts(m, "\t SE is not idle\n");
 868         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 869                 seq_puts(m, "\t RA is not idle\n");
 870         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 871                 seq_puts(m, "\t TX is not idle\n");
 872         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 873                 seq_puts(m, "\t VG is not idle\n");
 874         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 875                 seq_puts(m, "\t IM is not idle\n");
 876         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 877                 seq_puts(m, "\t FP is not idle\n");
 878         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 879                 seq_puts(m, "\t TS is not idle\n");
 880         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 881                 seq_puts(m, "\t AXI low power mode\n");
 882
 883         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 884                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 885                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 886                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 887
 888                 seq_puts(m, "\tMC\n");
 889                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 890                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 891                 seq_printf(m, "\t write: 0x%08x\n", write);
 892         }
 893
 894         seq_puts(m, "\tDMA ");
 895
 896         if (debug.address[0] == debug.address[1] &&
 897             debug.state[0] == debug.state[1]) {
 898                 seq_puts(m, "seems to be stuck\n");
 899         } else if (debug.address[0] == debug.address[1]) {
 900                 seq_puts(m, "address is constant\n");
 901         } else {
 902                 seq_puts(m, "is running\n");
 903         }
 904
 905         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 906         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 907         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 908         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 909         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 910                    dma_lo, dma_hi);
 911
 912         ret = 0;
 913
 914         pm_runtime_mark_last_busy(gpu->dev);
 915         pm_runtime_put_autosuspend(gpu->dev);
 916
 917         return ret;
 918 }
 919 #endif
 920
 921 /*
 922  * Hangcheck detection for locked gpu:
 923  */
 924 static void recover_worker(struct work_struct *work)
 925 {
 926         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
 927                                                recover_work);
 928         unsigned long flags;
 929         unsigned int i = 0;
 930
 931         dev_err(gpu->dev, "hangcheck recover!\n");
 932
 933         if (pm_runtime_get_sync(gpu->dev) < 0)
 934                 return;
 935
 936         mutex_lock(&gpu->lock);
 937
 938         /* Only catch the first event, or when manually re-armed */
 939         if (etnaviv_dump_core) {
 940                 etnaviv_core_dump(gpu);
 941                 etnaviv_dump_core = false;
 942         }
 943
 944         etnaviv_hw_reset(gpu);
 945
 946         /* complete all events, the GPU won't do it after the reset */
 947         spin_lock_irqsave(&gpu->event_spinlock, flags);
 948         for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) {
 949                 dma_fence_signal(gpu->event[i].fence);
 950                 gpu->event[i].fence = NULL;
 951                 complete(&gpu->event_free);
 952         }
 953         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 954         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 955         gpu->completed_fence = gpu->active_fence;
 956
 957         etnaviv_gpu_hw_init(gpu);
 958         gpu->lastctx = NULL;
 959         gpu->exec_state = -1;
 960
 961         mutex_unlock(&gpu->lock);
 962         pm_runtime_mark_last_busy(gpu->dev);
 963         pm_runtime_put_autosuspend(gpu->dev);
 964
 965         /* Retire the buffer objects in a work */
 966         queue_work(gpu->wq, &gpu->retire_work);
 967 }
 968
 969 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
 970 {
 971         DBG("%s", dev_name(gpu->dev));
 972         mod_timer(&gpu->hangcheck_timer,
 973                   round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
 974 }
 975
 976 static void hangcheck_handler(struct timer_list *t)
 977 {
 978         struct etnaviv_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
 979         u32 fence = gpu->completed_fence;
 980         bool progress = false;
 981
 982         if (fence != gpu->hangcheck_fence) {
 983                 gpu->hangcheck_fence = fence;
 984                 progress = true;
 985         }
 986
 987         if (!progress) {
 988                 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 989                 int change = dma_addr - gpu->hangcheck_dma_addr;
 990
 991                 if (change < 0 || change > 16) {
 992                         gpu->hangcheck_dma_addr = dma_addr;
 993                         progress = true;
 994                 }
 995         }
 996
 997         if (!progress && fence_after(gpu->active_fence, fence)) {
 998                 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
 999                 dev_err(gpu->dev, "     completed fence: %u\n", fence);
1000                 dev_err(gpu->dev, "     active fence: %u\n",
1001                         gpu->active_fence);
1002                 queue_work(gpu->wq, &gpu->recover_work);
1003         }
1004
1005         /* if still more pending work, reset the hangcheck timer: */
1006         if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
1007                 hangcheck_timer_reset(gpu);
1008 }
1009
1010 static void hangcheck_disable(struct etnaviv_gpu *gpu)
1011 {
1012         del_timer_sync(&gpu->hangcheck_timer);
1013         cancel_work_sync(&gpu->recover_work);
1014 }
1015
1016 /* fence object management */
1017 struct etnaviv_fence {
1018         struct etnaviv_gpu *gpu;
1019         struct dma_fence base;
1020 };
1021
1022 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1023 {
1024         return container_of(fence, struct etnaviv_fence, base);
1025 }
1026
1027 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1028 {
1029         return "etnaviv";
1030 }
1031
1032 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1033 {
1034         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1035
1036         return dev_name(f->gpu->dev);
1037 }
1038
1039 static bool etnaviv_fence_enable_signaling(struct dma_fence *fence)
1040 {
1041         return true;
1042 }
1043
1044 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1045 {
1046         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1047
1048         return fence_completed(f->gpu, f->base.seqno);
1049 }
1050
1051 static void etnaviv_fence_release(struct dma_fence *fence)
1052 {
1053         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1054
1055         kfree_rcu(f, base.rcu);
1056 }
1057
1058 static const struct dma_fence_ops etnaviv_fence_ops = {
1059         .get_driver_name = etnaviv_fence_get_driver_name,
1060         .get_timeline_name = etnaviv_fence_get_timeline_name,
1061         .enable_signaling = etnaviv_fence_enable_signaling,
1062         .signaled = etnaviv_fence_signaled,
1063         .wait = dma_fence_default_wait,
1064         .release = etnaviv_fence_release,
1065 };
1066
1067 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1068 {
1069         struct etnaviv_fence *f;
1070
1071         /*
1072          * GPU lock must already be held, otherwise fence completion order might
1073          * not match the seqno order assigned here.
1074          */
1075         lockdep_assert_held(&gpu->lock);
1076
1077         f = kzalloc(sizeof(*f), GFP_KERNEL);
1078         if (!f)
1079                 return NULL;
1080
1081         f->gpu = gpu;
1082
1083         dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1084                        gpu->fence_context, ++gpu->next_fence);
1085
1086         return &f->base;
1087 }
1088
1089 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1090         unsigned int context, bool exclusive, bool explicit)
1091 {
1092         struct reservation_object *robj = etnaviv_obj->resv;
1093         struct reservation_object_list *fobj;
1094         struct dma_fence *fence;
1095         int i, ret;
1096
1097         if (!exclusive) {
1098                 ret = reservation_object_reserve_shared(robj);
1099                 if (ret)
1100                         return ret;
1101         }
1102
1103         if (explicit)
1104                 return 0;
1105
1106         /*
1107          * If we have any shared fences, then the exclusive fence
1108          * should be ignored as it will already have been signalled.
1109          */
1110         fobj = reservation_object_get_list(robj);
1111         if (!fobj || fobj->shared_count == 0) {
1112                 /* Wait on any existing exclusive fence which isn't our own */
1113                 fence = reservation_object_get_excl(robj);
1114                 if (fence && fence->context != context) {
1115                         ret = dma_fence_wait(fence, true);
1116                         if (ret)
1117                                 return ret;
1118                 }
1119         }
1120
1121         if (!exclusive || !fobj)
1122                 return 0;
1123
1124         for (i = 0; i < fobj->shared_count; i++) {
1125                 fence = rcu_dereference_protected(fobj->shared[i],
1126                                                 reservation_object_held(robj));
1127                 if (fence->context != context) {
1128                         ret = dma_fence_wait(fence, true);
1129                         if (ret)
1130                                 return ret;
1131                 }
1132         }
1133
1134         return 0;
1135 }
1136
1137 /*
1138  * event management:
1139  */
1140
1141 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1142         unsigned int *events)
1143 {
1144         unsigned long flags, timeout = msecs_to_jiffies(10 * 10000);
1145         unsigned i, acquired = 0;
1146
1147         for (i = 0; i < nr_events; i++) {
1148                 unsigned long ret;
1149
1150                 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1151
1152                 if (!ret) {
1153                         dev_err(gpu->dev, "wait_for_completion_timeout failed");
1154                         goto out;
1155                 }
1156
1157                 acquired++;
1158                 timeout = ret;
1159         }
1160
1161         spin_lock_irqsave(&gpu->event_spinlock, flags);
1162
1163         for (i = 0; i < nr_events; i++) {
1164                 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1165
1166                 events[i] = event;
1167                 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1168                 set_bit(event, gpu->event_bitmap);
1169         }
1170
1171         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1172
1173         return 0;
1174
1175 out:
1176         for (i = 0; i < acquired; i++)
1177                 complete(&gpu->event_free);
1178
1179         return -EBUSY;
1180 }
1181
1182 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1183 {
1184         unsigned long flags;
1185
1186         spin_lock_irqsave(&gpu->event_spinlock, flags);
1187
1188         if (!test_bit(event, gpu->event_bitmap)) {
1189                 dev_warn(gpu->dev, "event %u is already marked as free",
1190                          event);
1191                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1192         } else {
1193                 clear_bit(event, gpu->event_bitmap);
1194                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1195
1196                 complete(&gpu->event_free);
1197         }
1198 }
1199
1200 /*
1201  * Cmdstream submission/retirement:
1202  */
1203
1204 static void retire_worker(struct work_struct *work)
1205 {
1206         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1207                                                retire_work);
1208         u32 fence = gpu->completed_fence;
1209         struct etnaviv_gem_submit *submit, *tmp;
1210         LIST_HEAD(retire_list);
1211
1212         mutex_lock(&gpu->lock);
1213         list_for_each_entry_safe(submit, tmp, &gpu->active_submit_list, node) {
1214                 if (!dma_fence_is_signaled(submit->out_fence))
1215                         break;
1216
1217                 list_move(&submit->node, &retire_list);
1218         }
1219
1220         gpu->retired_fence = fence;
1221
1222         mutex_unlock(&gpu->lock);
1223
1224         list_for_each_entry_safe(submit, tmp, &retire_list, node)
1225                 etnaviv_submit_put(submit);
1226 }
1227
1228 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1229         u32 fence, struct timespec *timeout)
1230 {
1231         int ret;
1232
1233         if (fence_after(fence, gpu->next_fence)) {
1234                 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1235                                 fence, gpu->next_fence);
1236                 return -EINVAL;
1237         }
1238
1239         if (!timeout) {
1240                 /* No timeout was requested: just test for completion */
1241                 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1242         } else {
1243                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1244
1245                 ret = wait_event_interruptible_timeout(gpu->fence_event,
1246                                                 fence_completed(gpu, fence),
1247                                                 remaining);
1248                 if (ret == 0) {
1249                         DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1250                                 fence, gpu->retired_fence,
1251                                 gpu->completed_fence);
1252                         ret = -ETIMEDOUT;
1253                 } else if (ret != -ERESTARTSYS) {
1254                         ret = 0;
1255                 }
1256         }
1257
1258         return ret;
1259 }
1260
1261 /*
1262  * Wait for an object to become inactive.  This, on it's own, is not race
1263  * free: the object is moved by the retire worker off the active list, and
1264  * then the iova is put.  Moreover, the object could be re-submitted just
1265  * after we notice that it's become inactive.
1266  *
1267  * Although the retirement happens under the gpu lock, we don't want to hold
1268  * that lock in this function while waiting.
1269  */
1270 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1271         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1272 {
1273         unsigned long remaining;
1274         long ret;
1275
1276         if (!timeout)
1277                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1278
1279         remaining = etnaviv_timeout_to_jiffies(timeout);
1280
1281         ret = wait_event_interruptible_timeout(gpu->fence_event,
1282                                                !is_active(etnaviv_obj),
1283                                                remaining);
1284         if (ret > 0)
1285                 return 0;
1286         else if (ret == -ERESTARTSYS)
1287                 return -ERESTARTSYS;
1288         else
1289                 return -ETIMEDOUT;
1290 }
1291
1292 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1293         struct etnaviv_event *event, unsigned int flags)
1294 {
1295         const struct etnaviv_gem_submit *submit = event->submit;
1296         unsigned int i;
1297
1298         for (i = 0; i < submit->nr_pmrs; i++) {
1299                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1300
1301                 if (pmr->flags == flags)
1302                         etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1303         }
1304 }
1305
1306 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1307         struct etnaviv_event *event)
1308 {
1309         u32 val;
1310
1311         /* disable clock gating */
1312         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1313         val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1314         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1315
1316         /* enable debug register */
1317         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1318         val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1319         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1320
1321         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1322 }
1323
1324 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1325         struct etnaviv_event *event)
1326 {
1327         const struct etnaviv_gem_submit *submit = event->submit;
1328         unsigned int i;
1329         u32 val;
1330
1331         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1332
1333         for (i = 0; i < submit->nr_pmrs; i++) {
1334                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1335
1336                 *pmr->bo_vma = pmr->sequence;
1337         }
1338
1339         /* disable debug register */
1340         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1341         val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1342         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1343
1344         /* enable clock gating */
1345         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1346         val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1347         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1348 }
1349
1350
1351 /* add bo's to gpu's ring, and kick gpu: */
1352 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1353         struct etnaviv_gem_submit *submit)
1354 {
1355         unsigned int i, nr_events = 1, event[3];
1356         int ret;
1357
1358         ret = pm_runtime_get_sync(gpu->dev);
1359         if (ret < 0)
1360                 return ret;
1361         submit->runtime_resumed = true;
1362
1363         /*
1364          * if there are performance monitor requests we need to have
1365          * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1366          *   requests.
1367          * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1368          *   and update the sequence number for userspace.
1369          */
1370         if (submit->nr_pmrs)
1371                 nr_events = 3;
1372
1373         ret = event_alloc(gpu, nr_events, event);
1374         if (ret) {
1375                 DRM_ERROR("no free events\n");
1376                 return ret;
1377         }
1378
1379         mutex_lock(&gpu->lock);
1380
1381         submit->out_fence = etnaviv_gpu_fence_alloc(gpu);
1382         if (!submit->out_fence) {
1383                 for (i = 0; i < nr_events; i++)
1384                         event_free(gpu, event[i]);
1385
1386                 ret = -ENOMEM;
1387                 goto out_unlock;
1388         }
1389
1390         gpu->active_fence = submit->out_fence->seqno;
1391
1392         if (submit->nr_pmrs) {
1393                 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1394                 kref_get(&submit->refcount);
1395                 gpu->event[event[1]].submit = submit;
1396                 etnaviv_sync_point_queue(gpu, event[1]);
1397         }
1398
1399         kref_get(&submit->refcount);
1400         gpu->event[event[0]].fence = submit->out_fence;
1401         etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
1402                              &submit->cmdbuf);
1403
1404         if (submit->nr_pmrs) {
1405                 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1406                 kref_get(&submit->refcount);
1407                 gpu->event[event[2]].submit = submit;
1408                 etnaviv_sync_point_queue(gpu, event[2]);
1409         }
1410
1411         list_add_tail(&submit->node, &gpu->active_submit_list);
1412
1413         hangcheck_timer_reset(gpu);
1414         ret = 0;
1415
1416 out_unlock:
1417         mutex_unlock(&gpu->lock);
1418
1419         return ret;
1420 }
1421
1422 static void sync_point_worker(struct work_struct *work)
1423 {
1424         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1425                                                sync_point_work);
1426         struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1427         u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1428
1429         event->sync_point(gpu, event);
1430         etnaviv_submit_put(event->submit);
1431         event_free(gpu, gpu->sync_point_event);
1432
1433         /* restart FE last to avoid GPU and IRQ racing against this worker */
1434         etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1435 }
1436
1437 /*
1438  * Init/Cleanup:
1439  */
1440 static irqreturn_t irq_handler(int irq, void *data)
1441 {
1442         struct etnaviv_gpu *gpu = data;
1443         irqreturn_t ret = IRQ_NONE;
1444
1445         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1446
1447         if (intr != 0) {
1448                 int event;
1449
1450                 pm_runtime_mark_last_busy(gpu->dev);
1451
1452                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1453
1454                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1455                         dev_err(gpu->dev, "AXI bus error\n");
1456                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1457                 }
1458
1459                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1460                         int i;
1461
1462                         dev_err_ratelimited(gpu->dev,
1463                                 "MMU fault status 0x%08x\n",
1464                                 gpu_read(gpu, VIVS_MMUv2_STATUS));
1465                         for (i = 0; i < 4; i++) {
1466                                 dev_err_ratelimited(gpu->dev,
1467                                         "MMU %d fault addr 0x%08x\n",
1468                                         i, gpu_read(gpu,
1469                                         VIVS_MMUv2_EXCEPTION_ADDR(i)));
1470                         }
1471                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1472                 }
1473
1474                 while ((event = ffs(intr)) != 0) {
1475                         struct dma_fence *fence;
1476
1477                         event -= 1;
1478
1479                         intr &= ~(1 << event);
1480
1481                         dev_dbg(gpu->dev, "event %u\n", event);
1482
1483                         if (gpu->event[event].sync_point) {
1484                                 gpu->sync_point_event = event;
1485                                 queue_work(gpu->wq, &gpu->sync_point_work);
1486                         }
1487
1488                         fence = gpu->event[event].fence;
1489                         if (!fence)
1490                                 continue;
1491
1492                         gpu->event[event].fence = NULL;
1493                         dma_fence_signal(fence);
1494
1495                         /*
1496                          * Events can be processed out of order.  Eg,
1497                          * - allocate and queue event 0
1498                          * - allocate event 1
1499                          * - event 0 completes, we process it
1500                          * - allocate and queue event 0
1501                          * - event 1 and event 0 complete
1502                          * we can end up processing event 0 first, then 1.
1503                          */
1504                         if (fence_after(fence->seqno, gpu->completed_fence))
1505                                 gpu->completed_fence = fence->seqno;
1506
1507                         event_free(gpu, event);
1508                 }
1509
1510                 /* Retire the buffer objects in a work */
1511                 queue_work(gpu->wq, &gpu->retire_work);
1512
1513                 ret = IRQ_HANDLED;
1514         }
1515
1516         return ret;
1517 }
1518
1519 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1520 {
1521         int ret;
1522
1523         if (gpu->clk_bus) {
1524                 ret = clk_prepare_enable(gpu->clk_bus);
1525                 if (ret)
1526                         return ret;
1527         }
1528
1529         if (gpu->clk_core) {
1530                 ret = clk_prepare_enable(gpu->clk_core);
1531                 if (ret)
1532                         goto disable_clk_bus;
1533         }
1534
1535         if (gpu->clk_shader) {
1536                 ret = clk_prepare_enable(gpu->clk_shader);
1537                 if (ret)
1538                         goto disable_clk_core;
1539         }
1540
1541         return 0;
1542
1543 disable_clk_core:
1544         if (gpu->clk_core)
1545                 clk_disable_unprepare(gpu->clk_core);
1546 disable_clk_bus:
1547         if (gpu->clk_bus)
1548                 clk_disable_unprepare(gpu->clk_bus);
1549
1550         return ret;
1551 }
1552
1553 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1554 {
1555         if (gpu->clk_shader)
1556                 clk_disable_unprepare(gpu->clk_shader);
1557         if (gpu->clk_core)
1558                 clk_disable_unprepare(gpu->clk_core);
1559         if (gpu->clk_bus)
1560                 clk_disable_unprepare(gpu->clk_bus);
1561
1562         return 0;
1563 }
1564
1565 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1566 {
1567         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1568
1569         do {
1570                 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1571
1572                 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1573                         return 0;
1574
1575                 if (time_is_before_jiffies(timeout)) {
1576                         dev_warn(gpu->dev,
1577                                  "timed out waiting for idle: idle=0x%x\n",
1578                                  idle);
1579                         return -ETIMEDOUT;
1580                 }
1581
1582                 udelay(5);
1583         } while (1);
1584 }
1585
1586 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1587 {
1588         if (gpu->buffer.suballoc) {
1589                 /* Replace the last WAIT with END */
1590                 mutex_lock(&gpu->lock);
1591                 etnaviv_buffer_end(gpu);
1592                 mutex_unlock(&gpu->lock);
1593
1594                 /*
1595                  * We know that only the FE is busy here, this should
1596                  * happen quickly (as the WAIT is only 200 cycles).  If
1597                  * we fail, just warn and continue.
1598                  */
1599                 etnaviv_gpu_wait_idle(gpu, 100);
1600         }
1601
1602         return etnaviv_gpu_clk_disable(gpu);
1603 }
1604
1605 #ifdef CONFIG_PM
1606 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1607 {
1608         int ret;
1609
1610         ret = mutex_lock_killable(&gpu->lock);
1611         if (ret)
1612                 return ret;
1613
1614         etnaviv_gpu_update_clock(gpu);
1615         etnaviv_gpu_hw_init(gpu);
1616
1617         gpu->lastctx = NULL;
1618         gpu->exec_state = -1;
1619
1620         mutex_unlock(&gpu->lock);
1621
1622         return 0;
1623 }
1624 #endif
1625
1626 static int
1627 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1628                                   unsigned long *state)
1629 {
1630         *state = 6;
1631
1632         return 0;
1633 }
1634
1635 static int
1636 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1637                                   unsigned long *state)
1638 {
1639         struct etnaviv_gpu *gpu = cdev->devdata;
1640
1641         *state = gpu->freq_scale;
1642
1643         return 0;
1644 }
1645
1646 static int
1647 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1648                                   unsigned long state)
1649 {
1650         struct etnaviv_gpu *gpu = cdev->devdata;
1651
1652         mutex_lock(&gpu->lock);
1653         gpu->freq_scale = state;
1654         if (!pm_runtime_suspended(gpu->dev))
1655                 etnaviv_gpu_update_clock(gpu);
1656         mutex_unlock(&gpu->lock);
1657
1658         return 0;
1659 }
1660
1661 static struct thermal_cooling_device_ops cooling_ops = {
1662         .get_max_state = etnaviv_gpu_cooling_get_max_state,
1663         .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1664         .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1665 };
1666
1667 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1668         void *data)
1669 {
1670         struct drm_device *drm = data;
1671         struct etnaviv_drm_private *priv = drm->dev_private;
1672         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1673         int ret;
1674
1675         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1676                 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1677                                 (char *)dev_name(dev), gpu, &cooling_ops);
1678                 if (IS_ERR(gpu->cooling))
1679                         return PTR_ERR(gpu->cooling);
1680         }
1681
1682         gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1683         if (!gpu->wq) {
1684                 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1685                         thermal_cooling_device_unregister(gpu->cooling);
1686                 return -ENOMEM;
1687         }
1688
1689 #ifdef CONFIG_PM
1690         ret = pm_runtime_get_sync(gpu->dev);
1691 #else
1692         ret = etnaviv_gpu_clk_enable(gpu);
1693 #endif
1694         if (ret < 0) {
1695                 destroy_workqueue(gpu->wq);
1696                 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1697                         thermal_cooling_device_unregister(gpu->cooling);
1698                 return ret;
1699         }
1700
1701         gpu->drm = drm;
1702         gpu->fence_context = dma_fence_context_alloc(1);
1703         spin_lock_init(&gpu->fence_spinlock);
1704
1705         INIT_LIST_HEAD(&gpu->active_submit_list);
1706         INIT_WORK(&gpu->retire_work, retire_worker);
1707         INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1708         INIT_WORK(&gpu->recover_work, recover_worker);
1709         init_waitqueue_head(&gpu->fence_event);
1710
1711         timer_setup(&gpu->hangcheck_timer, hangcheck_handler, TIMER_DEFERRABLE);
1712
1713         priv->gpu[priv->num_gpus++] = gpu;
1714
1715         pm_runtime_mark_last_busy(gpu->dev);
1716         pm_runtime_put_autosuspend(gpu->dev);
1717
1718         return 0;
1719 }
1720
1721 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1722         void *data)
1723 {
1724         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1725
1726         DBG("%s", dev_name(gpu->dev));
1727
1728         hangcheck_disable(gpu);
1729
1730         flush_workqueue(gpu->wq);
1731         destroy_workqueue(gpu->wq);
1732
1733 #ifdef CONFIG_PM
1734         pm_runtime_get_sync(gpu->dev);
1735         pm_runtime_put_sync_suspend(gpu->dev);
1736 #else
1737         etnaviv_gpu_hw_suspend(gpu);
1738 #endif
1739
1740         if (gpu->buffer.suballoc)
1741                 etnaviv_cmdbuf_free(&gpu->buffer);
1742
1743         if (gpu->cmdbuf_suballoc) {
1744                 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1745                 gpu->cmdbuf_suballoc = NULL;
1746         }
1747
1748         if (gpu->mmu) {
1749                 etnaviv_iommu_destroy(gpu->mmu);
1750                 gpu->mmu = NULL;
1751         }
1752
1753         gpu->drm = NULL;
1754
1755         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1756                 thermal_cooling_device_unregister(gpu->cooling);
1757         gpu->cooling = NULL;
1758 }
1759
1760 static const struct component_ops gpu_ops = {
1761         .bind = etnaviv_gpu_bind,
1762         .unbind = etnaviv_gpu_unbind,
1763 };
1764
1765 static const struct of_device_id etnaviv_gpu_match[] = {
1766         {
1767                 .compatible = "vivante,gc"
1768         },
1769         { /* sentinel */ }
1770 };
1771
1772 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1773 {
1774         struct device *dev = &pdev->dev;
1775         struct etnaviv_gpu *gpu;
1776         int err;
1777
1778         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1779         if (!gpu)
1780                 return -ENOMEM;
1781
1782         gpu->dev = &pdev->dev;
1783         mutex_init(&gpu->lock);
1784
1785         /* Map registers: */
1786         gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1787         if (IS_ERR(gpu->mmio))
1788                 return PTR_ERR(gpu->mmio);
1789
1790         /* Get Interrupt: */
1791         gpu->irq = platform_get_irq(pdev, 0);
1792         if (gpu->irq < 0) {
1793                 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1794                 return gpu->irq;
1795         }
1796
1797         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1798                                dev_name(gpu->dev), gpu);
1799         if (err) {
1800                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1801                 return err;
1802         }
1803
1804         /* Get Clocks: */
1805         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1806         DBG("clk_bus: %p", gpu->clk_bus);
1807         if (IS_ERR(gpu->clk_bus))
1808                 gpu->clk_bus = NULL;
1809
1810         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1811         DBG("clk_core: %p", gpu->clk_core);
1812         if (IS_ERR(gpu->clk_core))
1813                 gpu->clk_core = NULL;
1814         gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1815
1816         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1817         DBG("clk_shader: %p", gpu->clk_shader);
1818         if (IS_ERR(gpu->clk_shader))
1819                 gpu->clk_shader = NULL;
1820         gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1821
1822         /* TODO: figure out max mapped size */
1823         dev_set_drvdata(dev, gpu);
1824
1825         /*
1826          * We treat the device as initially suspended.  The runtime PM
1827          * autosuspend delay is rather arbitary: no measurements have
1828          * yet been performed to determine an appropriate value.
1829          */
1830         pm_runtime_use_autosuspend(gpu->dev);
1831         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1832         pm_runtime_enable(gpu->dev);
1833
1834         err = component_add(&pdev->dev, &gpu_ops);
1835         if (err < 0) {
1836                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1837                 return err;
1838         }
1839
1840         return 0;
1841 }
1842
1843 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1844 {
1845         component_del(&pdev->dev, &gpu_ops);
1846         pm_runtime_disable(&pdev->dev);
1847         return 0;
1848 }
1849
1850 #ifdef CONFIG_PM
1851 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1852 {
1853         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1854         u32 idle, mask;
1855
1856         /* If we have outstanding fences, we're not idle */
1857         if (gpu->completed_fence != gpu->active_fence)
1858                 return -EBUSY;
1859
1860         /* Check whether the hardware (except FE) is idle */
1861         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1862         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1863         if (idle != mask)
1864                 return -EBUSY;
1865
1866         return etnaviv_gpu_hw_suspend(gpu);
1867 }
1868
1869 static int etnaviv_gpu_rpm_resume(struct device *dev)
1870 {
1871         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1872         int ret;
1873
1874         ret = etnaviv_gpu_clk_enable(gpu);
1875         if (ret)
1876                 return ret;
1877
1878         /* Re-initialise the basic hardware state */
1879         if (gpu->drm && gpu->buffer.suballoc) {
1880                 ret = etnaviv_gpu_hw_resume(gpu);
1881                 if (ret) {
1882                         etnaviv_gpu_clk_disable(gpu);
1883                         return ret;
1884                 }
1885         }
1886
1887         return 0;
1888 }
1889 #endif
1890
1891 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1892         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1893                            NULL)
1894 };
1895
1896 struct platform_driver etnaviv_gpu_driver = {
1897         .driver = {
1898                 .name = "etnaviv-gpu",
1899                 .owner = THIS_MODULE,
1900                 .pm = &etnaviv_gpu_pm_ops,
1901                 .of_match_table = etnaviv_gpu_match,
1902         },
1903         .probe = etnaviv_gpu_platform_probe,
1904         .remove = etnaviv_gpu_platform_remove,
1905         .id_table = gpu_ids,
1906 };