2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
46 #include "drm_crtc_internal.h"
48 static int oui(u8 first, u8 second, u8 third)
50 return (first << 16) | (second << 8) | third;
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
91 #define MICROSOFT_IEEE_OUI 0xca125c
93 struct detailed_mode_closure {
94 struct drm_connector *connector;
95 const struct drm_edid *drm_edid;
106 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
113 static const struct edid_quirk {
116 } edid_quirk_list[] = {
118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
137 /* Belinea 10 15 55 */
138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
141 /* Envision Peripherals, Inc. EN-7100e */
142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
143 /* Envision EN2028 */
144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
146 /* Funai Electronics PM36B */
147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
148 EDID_QUIRK_DETAILED_IN_CM),
150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
153 /* LG Philips LCD LP154W01-A5 */
154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
157 /* Samsung SyncMaster 205BW. Note: irony */
158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
159 /* Samsung SyncMaster 22[5-6]BW */
160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
166 /* ViewSonic VA2026w */
167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
169 /* Medion MD 30217 PG */
170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
181 /* Valve Index Headset */
182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
200 /* HTC Vive and Vive Pro VR Headsets */
201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
210 /* Windows Mixed Reality Headsets */
211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
218 /* Sony PlayStation VR Headset */
219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
221 /* Sensics VR Headsets */
222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
224 /* OSVR HDK and HDK2 VR Headsets */
225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
229 * Autogenerated from the DMT spec.
230 * This table is copied from xfree86/modes/xf86EdidModes.c.
232 static const struct drm_display_mode drm_dmt_modes[] = {
233 /* 0x01 - 640x350@85Hz */
234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
235 736, 832, 0, 350, 382, 385, 445, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x02 - 640x400@85Hz */
238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
239 736, 832, 0, 400, 401, 404, 445, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x03 - 720x400@85Hz */
242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
243 828, 936, 0, 400, 401, 404, 446, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x04 - 640x480@60Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
247 752, 800, 0, 480, 490, 492, 525, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x05 - 640x480@72Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
251 704, 832, 0, 480, 489, 492, 520, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x06 - 640x480@75Hz */
254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
255 720, 840, 0, 480, 481, 484, 500, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
257 /* 0x07 - 640x480@85Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
259 752, 832, 0, 480, 481, 484, 509, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x08 - 800x600@56Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
263 896, 1024, 0, 600, 601, 603, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x09 - 800x600@60Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
267 968, 1056, 0, 600, 601, 605, 628, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0a - 800x600@72Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
271 976, 1040, 0, 600, 637, 643, 666, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0b - 800x600@75Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
275 896, 1056, 0, 600, 601, 604, 625, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0c - 800x600@85Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
279 896, 1048, 0, 600, 601, 604, 631, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0d - 800x600@120Hz RB */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
283 880, 960, 0, 600, 603, 607, 636, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
285 /* 0x0e - 848x480@60Hz */
286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
287 976, 1088, 0, 480, 486, 494, 517, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x0f - 1024x768@43Hz, interlace */
290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
291 1208, 1264, 0, 768, 768, 776, 817, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
293 DRM_MODE_FLAG_INTERLACE) },
294 /* 0x10 - 1024x768@60Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
296 1184, 1344, 0, 768, 771, 777, 806, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
298 /* 0x11 - 1024x768@70Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
300 1184, 1328, 0, 768, 771, 777, 806, 0,
301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x12 - 1024x768@75Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
304 1136, 1312, 0, 768, 769, 772, 800, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x13 - 1024x768@85Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
308 1168, 1376, 0, 768, 769, 772, 808, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x14 - 1024x768@120Hz RB */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
312 1104, 1184, 0, 768, 771, 775, 813, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x15 - 1152x864@75Hz */
315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
316 1344, 1600, 0, 864, 865, 868, 900, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x55 - 1280x720@60Hz */
319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
320 1430, 1650, 0, 720, 725, 730, 750, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x16 - 1280x768@60Hz RB */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
324 1360, 1440, 0, 768, 771, 778, 790, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x17 - 1280x768@60Hz */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
328 1472, 1664, 0, 768, 771, 778, 798, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x18 - 1280x768@75Hz */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
332 1488, 1696, 0, 768, 771, 778, 805, 0,
333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x19 - 1280x768@85Hz */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
336 1496, 1712, 0, 768, 771, 778, 809, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x1a - 1280x768@120Hz RB */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
340 1360, 1440, 0, 768, 771, 778, 813, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
342 /* 0x1b - 1280x800@60Hz RB */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
344 1360, 1440, 0, 800, 803, 809, 823, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
346 /* 0x1c - 1280x800@60Hz */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
348 1480, 1680, 0, 800, 803, 809, 831, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1d - 1280x800@75Hz */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
352 1488, 1696, 0, 800, 803, 809, 838, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x1e - 1280x800@85Hz */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
356 1496, 1712, 0, 800, 803, 809, 843, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x1f - 1280x800@120Hz RB */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
360 1360, 1440, 0, 800, 803, 809, 847, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362 /* 0x20 - 1280x960@60Hz */
363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
364 1488, 1800, 0, 960, 961, 964, 1000, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x21 - 1280x960@85Hz */
367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
368 1504, 1728, 0, 960, 961, 964, 1011, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x22 - 1280x960@120Hz RB */
371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
372 1360, 1440, 0, 960, 963, 967, 1017, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x23 - 1280x1024@60Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x24 - 1280x1024@75Hz */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x25 - 1280x1024@85Hz */
383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x26 - 1280x1024@120Hz RB */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x27 - 1360x768@60Hz */
391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
392 1536, 1792, 0, 768, 771, 777, 795, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x28 - 1360x768@120Hz RB */
395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
396 1440, 1520, 0, 768, 771, 776, 813, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x51 - 1366x768@60Hz */
399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
400 1579, 1792, 0, 768, 771, 774, 798, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x56 - 1366x768@60Hz */
403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
404 1436, 1500, 0, 768, 769, 772, 800, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x29 - 1400x1050@60Hz RB */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
410 /* 0x2a - 1400x1050@60Hz */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x2b - 1400x1050@75Hz */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x2c - 1400x1050@85Hz */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x2d - 1400x1050@120Hz RB */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
426 /* 0x2e - 1440x900@60Hz RB */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
428 1520, 1600, 0, 900, 903, 909, 926, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
430 /* 0x2f - 1440x900@60Hz */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
432 1672, 1904, 0, 900, 903, 909, 934, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x30 - 1440x900@75Hz */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
436 1688, 1936, 0, 900, 903, 909, 942, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x31 - 1440x900@85Hz */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
440 1696, 1952, 0, 900, 903, 909, 948, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x32 - 1440x900@120Hz RB */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
444 1520, 1600, 0, 900, 903, 909, 953, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
446 /* 0x53 - 1600x900@60Hz */
447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
448 1704, 1800, 0, 900, 901, 904, 1000, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x33 - 1600x1200@60Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x34 - 1600x1200@65Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x35 - 1600x1200@70Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x36 - 1600x1200@75Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x37 - 1600x1200@85Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x38 - 1600x1200@120Hz RB */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
474 /* 0x39 - 1680x1050@60Hz RB */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
478 /* 0x3a - 1680x1050@60Hz */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x3b - 1680x1050@75Hz */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x3c - 1680x1050@85Hz */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3d - 1680x1050@120Hz RB */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
494 /* 0x3e - 1792x1344@60Hz */
495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x3f - 1792x1344@75Hz */
499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x40 - 1792x1344@120Hz RB */
503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x41 - 1856x1392@60Hz */
507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x42 - 1856x1392@75Hz */
511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x43 - 1856x1392@120Hz RB */
515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x52 - 1920x1080@60Hz */
519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
522 /* 0x44 - 1920x1200@60Hz RB */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
526 /* 0x45 - 1920x1200@60Hz */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x46 - 1920x1200@75Hz */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x47 - 1920x1200@85Hz */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x48 - 1920x1200@120Hz RB */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x49 - 1920x1440@60Hz */
543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x4a - 1920x1440@75Hz */
547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4b - 1920x1440@120Hz RB */
551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x54 - 2048x1152@60Hz */
555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4c - 2560x1600@60Hz RB */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
562 /* 0x4d - 2560x1600@60Hz */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x4e - 2560x1600@75Hz */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
570 /* 0x4f - 2560x1600@85Hz */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
574 /* 0x50 - 2560x1600@120Hz RB */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
578 /* 0x57 - 4096x2160@60Hz RB */
579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
582 /* 0x58 - 4096x2160@59.94Hz RB */
583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
589 * These more or less come from the DMT spec. The 720x400 modes are
590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
595 * The DMT modes have been fact-checked; the rest are mild guesses.
597 static const struct drm_display_mode edid_est_modes[] = {
598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
599 968, 1056, 0, 600, 601, 605, 628, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
602 896, 1024, 0, 600, 601, 603, 625, 0,
603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
605 720, 840, 0, 480, 481, 484, 500, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
608 704, 832, 0, 480, 489, 492, 520, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
611 768, 864, 0, 480, 483, 486, 525, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
614 752, 800, 0, 480, 490, 492, 525, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
617 846, 900, 0, 400, 421, 423, 449, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
620 846, 900, 0, 400, 412, 414, 449, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
626 1136, 1312, 0, 768, 769, 772, 800, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
629 1184, 1328, 0, 768, 771, 777, 806, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
632 1184, 1344, 0, 768, 771, 777, 806, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
635 1208, 1264, 0, 768, 768, 776, 817, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
638 928, 1152, 0, 624, 625, 628, 667, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
641 896, 1056, 0, 600, 601, 604, 625, 0,
642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
644 976, 1040, 0, 600, 637, 643, 666, 0,
645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
647 1344, 1600, 0, 864, 865, 868, 900, 0,
648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
658 static const struct minimode est3_modes[] = {
666 { 1024, 768, 85, 0 },
667 { 1152, 864, 75, 0 },
669 { 1280, 768, 60, 1 },
670 { 1280, 768, 60, 0 },
671 { 1280, 768, 75, 0 },
672 { 1280, 768, 85, 0 },
673 { 1280, 960, 60, 0 },
674 { 1280, 960, 85, 0 },
675 { 1280, 1024, 60, 0 },
676 { 1280, 1024, 85, 0 },
678 { 1360, 768, 60, 0 },
679 { 1440, 900, 60, 1 },
680 { 1440, 900, 60, 0 },
681 { 1440, 900, 75, 0 },
682 { 1440, 900, 85, 0 },
683 { 1400, 1050, 60, 1 },
684 { 1400, 1050, 60, 0 },
685 { 1400, 1050, 75, 0 },
687 { 1400, 1050, 85, 0 },
688 { 1680, 1050, 60, 1 },
689 { 1680, 1050, 60, 0 },
690 { 1680, 1050, 75, 0 },
691 { 1680, 1050, 85, 0 },
692 { 1600, 1200, 60, 0 },
693 { 1600, 1200, 65, 0 },
694 { 1600, 1200, 70, 0 },
696 { 1600, 1200, 75, 0 },
697 { 1600, 1200, 85, 0 },
698 { 1792, 1344, 60, 0 },
699 { 1792, 1344, 75, 0 },
700 { 1856, 1392, 60, 0 },
701 { 1856, 1392, 75, 0 },
702 { 1920, 1200, 60, 1 },
703 { 1920, 1200, 60, 0 },
705 { 1920, 1200, 75, 0 },
706 { 1920, 1200, 85, 0 },
707 { 1920, 1440, 60, 0 },
708 { 1920, 1440, 75, 0 },
711 static const struct minimode extra_modes[] = {
712 { 1024, 576, 60, 0 },
713 { 1366, 768, 60, 0 },
714 { 1600, 900, 60, 0 },
715 { 1680, 945, 60, 0 },
716 { 1920, 1080, 60, 0 },
717 { 2048, 1152, 60, 0 },
718 { 2048, 1536, 60, 0 },
722 * From CEA/CTA-861 spec.
724 * Do not access directly, instead always use cea_mode_for_vic().
726 static const struct drm_display_mode edid_cea_modes_1[] = {
727 /* 1 - 640x480@60Hz 4:3 */
728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
729 752, 800, 0, 480, 490, 492, 525, 0,
730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
732 /* 2 - 720x480@60Hz 4:3 */
733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
734 798, 858, 0, 480, 489, 495, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
737 /* 3 - 720x480@60Hz 16:9 */
738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
742 /* 4 - 1280x720@60Hz 16:9 */
743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
744 1430, 1650, 0, 720, 725, 730, 750, 0,
745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 5 - 1920x1080i@60Hz 16:9 */
748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
751 DRM_MODE_FLAG_INTERLACE),
752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 6 - 720(1440)x480i@60Hz 4:3 */
754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 480, 488, 494, 525, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
759 /* 7 - 720(1440)x480i@60Hz 16:9 */
760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 480, 488, 494, 525, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 8 - 720(1440)x240@60Hz 4:3 */
766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 240, 244, 247, 262, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_DBLCLK),
770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 9 - 720(1440)x240@60Hz 16:9 */
772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
773 801, 858, 0, 240, 244, 247, 262, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_DBLCLK),
776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 10 - 2880x480i@60Hz 4:3 */
778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 480, 488, 494, 525, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_INTERLACE),
782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
783 /* 11 - 2880x480i@60Hz 16:9 */
784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
785 3204, 3432, 0, 480, 488, 494, 525, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
787 DRM_MODE_FLAG_INTERLACE),
788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
789 /* 12 - 2880x240@60Hz 4:3 */
790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
791 3204, 3432, 0, 240, 244, 247, 262, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 13 - 2880x240@60Hz 16:9 */
795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799 /* 14 - 1440x480@60Hz 4:3 */
800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
801 1596, 1716, 0, 480, 489, 495, 525, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
804 /* 15 - 1440x480@60Hz 16:9 */
805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
809 /* 16 - 1920x1080@60Hz 16:9 */
810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 17 - 720x576@50Hz 4:3 */
815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
816 796, 864, 0, 576, 581, 586, 625, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
819 /* 18 - 720x576@50Hz 16:9 */
820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
824 /* 19 - 1280x720@50Hz 16:9 */
825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
826 1760, 1980, 0, 720, 725, 730, 750, 0,
827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 20 - 1920x1080i@50Hz 16:9 */
830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
833 DRM_MODE_FLAG_INTERLACE),
834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 21 - 720(1440)x576i@50Hz 4:3 */
836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
841 /* 22 - 720(1440)x576i@50Hz 16:9 */
842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 576, 580, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 23 - 720(1440)x288@50Hz 4:3 */
848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 288, 290, 293, 312, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_DBLCLK),
852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 24 - 720(1440)x288@50Hz 16:9 */
854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
855 795, 864, 0, 288, 290, 293, 312, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_DBLCLK),
858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 25 - 2880x576i@50Hz 4:3 */
860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 576, 580, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
863 DRM_MODE_FLAG_INTERLACE),
864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
865 /* 26 - 2880x576i@50Hz 16:9 */
866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
867 3180, 3456, 0, 576, 580, 586, 625, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
869 DRM_MODE_FLAG_INTERLACE),
870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 27 - 2880x288@50Hz 4:3 */
872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
873 3180, 3456, 0, 288, 290, 293, 312, 0,
874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 28 - 2880x288@50Hz 16:9 */
877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
881 /* 29 - 1440x576@50Hz 4:3 */
882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
883 1592, 1728, 0, 576, 581, 586, 625, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
886 /* 30 - 1440x576@50Hz 16:9 */
887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
891 /* 31 - 1920x1080@50Hz 16:9 */
892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 32 - 1920x1080@24Hz 16:9 */
897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 33 - 1920x1080@25Hz 16:9 */
902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
906 /* 34 - 1920x1080@30Hz 16:9 */
907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
911 /* 35 - 2880x480@60Hz 4:3 */
912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
913 3192, 3432, 0, 480, 489, 495, 525, 0,
914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
916 /* 36 - 2880x480@60Hz 16:9 */
917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
921 /* 37 - 2880x576@50Hz 4:3 */
922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
923 3184, 3456, 0, 576, 581, 586, 625, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
926 /* 38 - 2880x576@50Hz 16:9 */
927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 39 - 1920x1080i@50Hz 16:9 */
932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
935 DRM_MODE_FLAG_INTERLACE),
936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
937 /* 40 - 1920x1080i@100Hz 16:9 */
938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
941 DRM_MODE_FLAG_INTERLACE),
942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 41 - 1280x720@100Hz 16:9 */
944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
945 1760, 1980, 0, 720, 725, 730, 750, 0,
946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 42 - 720x576@100Hz 4:3 */
949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
950 796, 864, 0, 576, 581, 586, 625, 0,
951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
953 /* 43 - 720x576@100Hz 16:9 */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 44 - 720(1440)x576i@100Hz 4:3 */
959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
964 /* 45 - 720(1440)x576i@100Hz 16:9 */
965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
966 795, 864, 0, 576, 580, 586, 625, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 46 - 1920x1080i@120Hz 16:9 */
971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
974 DRM_MODE_FLAG_INTERLACE),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
976 /* 47 - 1280x720@120Hz 16:9 */
977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
978 1430, 1650, 0, 720, 725, 730, 750, 0,
979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 48 - 720x480@120Hz 4:3 */
982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
983 798, 858, 0, 480, 489, 495, 525, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
986 /* 49 - 720x480@120Hz 16:9 */
987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
991 /* 50 - 720(1440)x480i@120Hz 4:3 */
992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
993 801, 858, 0, 480, 488, 494, 525, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
997 /* 51 - 720(1440)x480i@120Hz 16:9 */
998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
999 801, 858, 0, 480, 488, 494, 525, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 /* 52 - 720x576@200Hz 4:3 */
1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1005 796, 864, 0, 576, 581, 586, 625, 0,
1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1008 /* 53 - 720x576@200Hz 16:9 */
1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1013 /* 54 - 720(1440)x576i@200Hz 4:3 */
1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1015 795, 864, 0, 576, 580, 586, 625, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1019 /* 55 - 720(1440)x576i@200Hz 16:9 */
1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1021 795, 864, 0, 576, 580, 586, 625, 0,
1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025 /* 56 - 720x480@240Hz 4:3 */
1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1027 798, 858, 0, 480, 489, 495, 525, 0,
1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1030 /* 57 - 720x480@240Hz 16:9 */
1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035 /* 58 - 720(1440)x480i@240Hz 4:3 */
1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1037 801, 858, 0, 480, 488, 494, 525, 0,
1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1041 /* 59 - 720(1440)x480i@240Hz 16:9 */
1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1043 801, 858, 0, 480, 488, 494, 525, 0,
1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1047 /* 60 - 1280x720@24Hz 16:9 */
1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1049 3080, 3300, 0, 720, 725, 730, 750, 0,
1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1052 /* 61 - 1280x720@25Hz 16:9 */
1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1054 3740, 3960, 0, 720, 725, 730, 750, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1057 /* 62 - 1280x720@30Hz 16:9 */
1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1059 3080, 3300, 0, 720, 725, 730, 750, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1062 /* 63 - 1920x1080@120Hz 16:9 */
1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1067 /* 64 - 1920x1080@100Hz 16:9 */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1072 /* 65 - 1280x720@24Hz 64:27 */
1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1074 3080, 3300, 0, 720, 725, 730, 750, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077 /* 66 - 1280x720@25Hz 64:27 */
1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1079 3740, 3960, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 67 - 1280x720@30Hz 64:27 */
1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1084 3080, 3300, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 68 - 1280x720@50Hz 64:27 */
1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1089 1760, 1980, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 69 - 1280x720@60Hz 64:27 */
1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1094 1430, 1650, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 70 - 1280x720@100Hz 64:27 */
1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1099 1760, 1980, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 71 - 1280x720@120Hz 64:27 */
1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1104 1430, 1650, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 72 - 1920x1080@24Hz 64:27 */
1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 73 - 1920x1080@25Hz 64:27 */
1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 74 - 1920x1080@30Hz 64:27 */
1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 75 - 1920x1080@50Hz 64:27 */
1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 76 - 1920x1080@60Hz 64:27 */
1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 77 - 1920x1080@100Hz 64:27 */
1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 78 - 1920x1080@120Hz 64:27 */
1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 79 - 1680x720@24Hz 64:27 */
1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1144 3080, 3300, 0, 720, 725, 730, 750, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 80 - 1680x720@25Hz 64:27 */
1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1149 2948, 3168, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 81 - 1680x720@30Hz 64:27 */
1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1154 2420, 2640, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 82 - 1680x720@50Hz 64:27 */
1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1159 1980, 2200, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162 /* 83 - 1680x720@60Hz 64:27 */
1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1167 /* 84 - 1680x720@100Hz 64:27 */
1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1169 1780, 2000, 0, 720, 725, 730, 825, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1172 /* 85 - 1680x720@120Hz 64:27 */
1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1177 /* 86 - 2560x1080@24Hz 64:27 */
1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1182 /* 87 - 2560x1080@25Hz 64:27 */
1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1187 /* 88 - 2560x1080@30Hz 64:27 */
1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1192 /* 89 - 2560x1080@50Hz 64:27 */
1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1197 /* 90 - 2560x1080@60Hz 64:27 */
1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1202 /* 91 - 2560x1080@100Hz 64:27 */
1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1207 /* 92 - 2560x1080@120Hz 64:27 */
1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1212 /* 93 - 3840x2160@24Hz 16:9 */
1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1217 /* 94 - 3840x2160@25Hz 16:9 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1222 /* 95 - 3840x2160@30Hz 16:9 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1227 /* 96 - 3840x2160@50Hz 16:9 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1232 /* 97 - 3840x2160@60Hz 16:9 */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1237 /* 98 - 4096x2160@24Hz 256:135 */
1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1242 /* 99 - 4096x2160@25Hz 256:135 */
1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1247 /* 100 - 4096x2160@30Hz 256:135 */
1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1252 /* 101 - 4096x2160@50Hz 256:135 */
1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1257 /* 102 - 4096x2160@60Hz 256:135 */
1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1262 /* 103 - 3840x2160@24Hz 64:27 */
1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1267 /* 104 - 3840x2160@25Hz 64:27 */
1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1272 /* 105 - 3840x2160@30Hz 64:27 */
1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1277 /* 106 - 3840x2160@50Hz 64:27 */
1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1282 /* 107 - 3840x2160@60Hz 64:27 */
1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1287 /* 108 - 1280x720@48Hz 16:9 */
1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1289 2280, 2500, 0, 720, 725, 730, 750, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1292 /* 109 - 1280x720@48Hz 64:27 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1297 /* 110 - 1680x720@48Hz 64:27 */
1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1299 2530, 2750, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1302 /* 111 - 1920x1080@48Hz 16:9 */
1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1307 /* 112 - 1920x1080@48Hz 64:27 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1312 /* 113 - 2560x1080@48Hz 64:27 */
1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1317 /* 114 - 3840x2160@48Hz 16:9 */
1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1322 /* 115 - 4096x2160@48Hz 256:135 */
1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1327 /* 116 - 3840x2160@48Hz 64:27 */
1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1332 /* 117 - 3840x2160@100Hz 16:9 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1337 /* 118 - 3840x2160@120Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1342 /* 119 - 3840x2160@100Hz 64:27 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1347 /* 120 - 3840x2160@120Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1352 /* 121 - 5120x2160@24Hz 64:27 */
1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1357 /* 122 - 5120x2160@25Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1362 /* 123 - 5120x2160@30Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1367 /* 124 - 5120x2160@48Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1372 /* 125 - 5120x2160@50Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1377 /* 126 - 5120x2160@60Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1382 /* 127 - 5120x2160@100Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 * From CEA/CTA-861 spec.
1392 * Do not access directly, instead always use cea_mode_for_vic().
1394 static const struct drm_display_mode edid_cea_modes_193[] = {
1395 /* 193 - 5120x2160@120Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1400 /* 194 - 7680x4320@24Hz 16:9 */
1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1405 /* 195 - 7680x4320@25Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1410 /* 196 - 7680x4320@30Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1415 /* 197 - 7680x4320@48Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1420 /* 198 - 7680x4320@50Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1425 /* 199 - 7680x4320@60Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1430 /* 200 - 7680x4320@100Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1435 /* 201 - 7680x4320@120Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1440 /* 202 - 7680x4320@24Hz 64:27 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1445 /* 203 - 7680x4320@25Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1450 /* 204 - 7680x4320@30Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1455 /* 205 - 7680x4320@48Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1460 /* 206 - 7680x4320@50Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1465 /* 207 - 7680x4320@60Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1470 /* 208 - 7680x4320@100Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1475 /* 209 - 7680x4320@120Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1480 /* 210 - 10240x4320@24Hz 64:27 */
1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1485 /* 211 - 10240x4320@25Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1490 /* 212 - 10240x4320@30Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1495 /* 213 - 10240x4320@48Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1500 /* 214 - 10240x4320@50Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1505 /* 215 - 10240x4320@60Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1510 /* 216 - 10240x4320@100Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1515 /* 217 - 10240x4320@120Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1520 /* 218 - 4096x2160@100Hz 256:135 */
1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1525 /* 219 - 4096x2160@120Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1533 * HDMI 1.4 4k modes. Index using the VIC.
1535 static const struct drm_display_mode edid_4k_modes[] = {
1536 /* 0 - dummy, VICs start at 1 */
1538 /* 1 - 3840x2160@30Hz */
1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1540 3840, 4016, 4104, 4400, 0,
1541 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1544 /* 2 - 3840x2160@25Hz */
1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1546 3840, 4896, 4984, 5280, 0,
1547 2160, 2168, 2178, 2250, 0,
1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1550 /* 3 - 3840x2160@24Hz */
1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1552 3840, 5116, 5204, 5500, 0,
1553 2160, 2168, 2178, 2250, 0,
1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1556 /* 4 - 4096x2160@24Hz (SMPTE) */
1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1558 4096, 5116, 5204, 5500, 0,
1559 2160, 2168, 2178, 2250, 0,
1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1564 /*** DDC fetch and block validation ***/
1567 * The opaque EDID type, internal to drm_edid.c.
1570 /* Size allocated for edid */
1572 const struct edid *edid;
1575 static bool version_greater(const struct drm_edid *drm_edid,
1576 u8 version, u8 revision)
1578 const struct edid *edid = drm_edid->edid;
1580 return edid->version > version ||
1581 (edid->version == version && edid->revision > revision);
1584 static int edid_extension_block_count(const struct edid *edid)
1586 return edid->extensions;
1589 static int edid_block_count(const struct edid *edid)
1591 return edid_extension_block_count(edid) + 1;
1594 static int edid_size_by_blocks(int num_blocks)
1596 return num_blocks * EDID_LENGTH;
1599 static int edid_size(const struct edid *edid)
1601 return edid_size_by_blocks(edid_block_count(edid));
1604 static const void *edid_block_data(const struct edid *edid, int index)
1606 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1608 return edid + index;
1611 static const void *edid_extension_block_data(const struct edid *edid, int index)
1613 return edid_block_data(edid, index + 1);
1616 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1620 /* Starting point */
1621 num_blocks = edid_block_count(drm_edid->edid);
1623 /* Limit by allocated size */
1624 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH);
1629 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1631 return drm_edid_block_count(drm_edid) - 1;
1634 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1636 return edid_block_data(drm_edid->edid, index);
1639 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1642 return edid_extension_block_data(drm_edid->edid, index);
1646 * Initializer helper for legacy interfaces, where we have no choice but to
1647 * trust edid size. Not for general purpose use.
1649 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1650 const struct edid *edid)
1655 memset(drm_edid, 0, sizeof(*drm_edid));
1657 drm_edid->edid = edid;
1658 drm_edid->size = edid_size(edid);
1664 * EDID base and extension block iterator.
1666 * struct drm_edid_iter iter;
1669 * drm_edid_iter_begin(drm_edid, &iter);
1670 * drm_edid_iter_for_each(block, &iter) {
1671 * // do stuff with block
1673 * drm_edid_iter_end(&iter);
1675 struct drm_edid_iter {
1676 const struct drm_edid *drm_edid;
1678 /* Current block index. */
1682 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1683 struct drm_edid_iter *iter)
1685 memset(iter, 0, sizeof(*iter));
1687 iter->drm_edid = drm_edid;
1690 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1692 const void *block = NULL;
1694 if (!iter->drm_edid)
1697 if (iter->index < drm_edid_block_count(iter->drm_edid))
1698 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1703 #define drm_edid_iter_for_each(__block, __iter) \
1704 while (((__block) = __drm_edid_iter_next(__iter)))
1706 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1708 memset(iter, 0, sizeof(*iter));
1711 static const u8 edid_header[] = {
1712 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1715 static void edid_header_fix(void *edid)
1717 memcpy(edid, edid_header, sizeof(edid_header));
1721 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1722 * @_edid: pointer to raw base EDID block
1724 * Sanity check the header of the base EDID block.
1726 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1728 int drm_edid_header_is_valid(const void *_edid)
1730 const struct edid *edid = _edid;
1733 for (i = 0; i < sizeof(edid_header); i++) {
1734 if (edid->header[i] == edid_header[i])
1740 EXPORT_SYMBOL(drm_edid_header_is_valid);
1742 static int edid_fixup __read_mostly = 6;
1743 module_param_named(edid_fixup, edid_fixup, int, 0400);
1744 MODULE_PARM_DESC(edid_fixup,
1745 "Minimum number of valid EDID header bytes (0-8, default 6)");
1747 static int edid_block_compute_checksum(const void *_block)
1749 const u8 *block = _block;
1751 u8 csum = 0, crc = 0;
1753 for (i = 0; i < EDID_LENGTH - 1; i++)
1761 static int edid_block_get_checksum(const void *_block)
1763 const struct edid *block = _block;
1765 return block->checksum;
1768 static int edid_block_tag(const void *_block)
1770 const u8 *block = _block;
1775 static bool edid_block_is_zero(const void *edid)
1777 return !memchr_inv(edid, 0, EDID_LENGTH);
1781 * drm_edid_are_equal - compare two edid blobs.
1782 * @edid1: pointer to first blob
1783 * @edid2: pointer to second blob
1784 * This helper can be used during probing to determine if
1787 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1789 int edid1_len, edid2_len;
1790 bool edid1_present = edid1 != NULL;
1791 bool edid2_present = edid2 != NULL;
1793 if (edid1_present != edid2_present)
1797 edid1_len = edid_size(edid1);
1798 edid2_len = edid_size(edid2);
1800 if (edid1_len != edid2_len)
1803 if (memcmp(edid1, edid2, edid1_len))
1809 EXPORT_SYMBOL(drm_edid_are_equal);
1811 enum edid_block_status {
1813 EDID_BLOCK_READ_FAIL,
1816 EDID_BLOCK_HEADER_CORRUPT,
1817 EDID_BLOCK_HEADER_REPAIR,
1818 EDID_BLOCK_HEADER_FIXED,
1819 EDID_BLOCK_CHECKSUM,
1823 static enum edid_block_status edid_block_check(const void *_block,
1826 const struct edid *block = _block;
1829 return EDID_BLOCK_NULL;
1831 if (is_base_block) {
1832 int score = drm_edid_header_is_valid(block);
1834 if (score < clamp(edid_fixup, 0, 8)) {
1835 if (edid_block_is_zero(block))
1836 return EDID_BLOCK_ZERO;
1838 return EDID_BLOCK_HEADER_CORRUPT;
1842 return EDID_BLOCK_HEADER_REPAIR;
1845 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1846 if (edid_block_is_zero(block))
1847 return EDID_BLOCK_ZERO;
1849 return EDID_BLOCK_CHECKSUM;
1852 if (is_base_block) {
1853 if (block->version != 1)
1854 return EDID_BLOCK_VERSION;
1857 return EDID_BLOCK_OK;
1860 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1862 return status == EDID_BLOCK_OK ||
1863 status == EDID_BLOCK_HEADER_FIXED ||
1864 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1867 static bool edid_block_valid(const void *block, bool base)
1869 return edid_block_status_valid(edid_block_check(block, base),
1870 edid_block_tag(block));
1873 static void edid_block_status_print(enum edid_block_status status,
1874 const struct edid *block,
1880 case EDID_BLOCK_READ_FAIL:
1881 pr_debug("EDID block %d read failed\n", block_num);
1883 case EDID_BLOCK_NULL:
1884 pr_debug("EDID block %d pointer is NULL\n", block_num);
1886 case EDID_BLOCK_ZERO:
1887 pr_notice("EDID block %d is all zeroes\n", block_num);
1889 case EDID_BLOCK_HEADER_CORRUPT:
1890 pr_notice("EDID has corrupt header\n");
1892 case EDID_BLOCK_HEADER_REPAIR:
1893 pr_debug("EDID corrupt header needs repair\n");
1895 case EDID_BLOCK_HEADER_FIXED:
1896 pr_debug("EDID corrupt header fixed\n");
1898 case EDID_BLOCK_CHECKSUM:
1899 if (edid_block_status_valid(status, edid_block_tag(block))) {
1900 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1901 block_num, edid_block_tag(block),
1902 edid_block_compute_checksum(block));
1904 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1905 block_num, edid_block_tag(block),
1906 edid_block_compute_checksum(block));
1909 case EDID_BLOCK_VERSION:
1910 pr_notice("EDID has major version %d, instead of 1\n",
1914 WARN(1, "EDID block %d unknown edid block status code %d\n",
1920 static void edid_block_dump(const char *level, const void *block, int block_num)
1922 enum edid_block_status status;
1925 status = edid_block_check(block, block_num == 0);
1926 if (status == EDID_BLOCK_ZERO)
1927 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1928 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1929 sprintf(prefix, "\t[%02x] BAD ", block_num);
1931 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1933 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1934 block, EDID_LENGTH, false);
1938 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1939 * @_block: pointer to raw EDID block
1940 * @block_num: type of block to validate (0 for base, extension otherwise)
1941 * @print_bad_edid: if true, dump bad EDID blocks to the console
1942 * @edid_corrupt: if true, the header or checksum is invalid
1944 * Validate a base or extension EDID block and optionally dump bad blocks to
1947 * Return: True if the block is valid, false otherwise.
1949 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1952 struct edid *block = (struct edid *)_block;
1953 enum edid_block_status status;
1954 bool is_base_block = block_num == 0;
1957 if (WARN_ON(!block))
1960 status = edid_block_check(block, is_base_block);
1961 if (status == EDID_BLOCK_HEADER_REPAIR) {
1962 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1963 edid_header_fix(block);
1965 /* Retry with fixed header, update status if that worked. */
1966 status = edid_block_check(block, is_base_block);
1967 if (status == EDID_BLOCK_OK)
1968 status = EDID_BLOCK_HEADER_FIXED;
1973 * Unknown major version isn't corrupt but we can't use it. Only
1974 * the base block can reset edid_corrupt to false.
1976 if (is_base_block &&
1977 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1978 *edid_corrupt = false;
1979 else if (status != EDID_BLOCK_OK)
1980 *edid_corrupt = true;
1983 edid_block_status_print(status, block, block_num);
1985 /* Determine whether we can use this block with this status. */
1986 valid = edid_block_status_valid(status, edid_block_tag(block));
1988 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
1989 pr_notice("Raw EDID:\n");
1990 edid_block_dump(KERN_NOTICE, block, block_num);
1995 EXPORT_SYMBOL(drm_edid_block_valid);
1998 * drm_edid_is_valid - sanity check EDID data
2001 * Sanity-check an entire EDID record (including extensions)
2003 * Return: True if the EDID data is valid, false otherwise.
2005 bool drm_edid_is_valid(struct edid *edid)
2012 for (i = 0; i < edid_block_count(edid); i++) {
2013 void *block = (void *)edid_block_data(edid, i);
2015 if (!drm_edid_block_valid(block, i, true, NULL))
2021 EXPORT_SYMBOL(drm_edid_is_valid);
2023 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2027 int i, valid_blocks = 0;
2029 for (i = 0; i < edid_block_count(edid); i++) {
2030 const void *src_block = edid_block_data(edid, i);
2032 if (edid_block_valid(src_block, i == 0)) {
2033 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2035 memmove(dst_block, src_block, EDID_LENGTH);
2040 /* We already trusted the base block to be valid here... */
2041 if (WARN_ON(!valid_blocks)) {
2046 edid->extensions = valid_blocks - 1;
2047 edid->checksum = edid_block_compute_checksum(edid);
2049 *alloc_size = edid_size_by_blocks(valid_blocks);
2051 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2058 #define DDC_SEGMENT_ADDR 0x30
2060 * drm_do_probe_ddc_edid() - get EDID information via I2C
2061 * @data: I2C device adapter
2062 * @buf: EDID data buffer to be filled
2063 * @block: 128 byte EDID block to start fetching from
2064 * @len: EDID data buffer length to fetch
2066 * Try to fetch EDID information by calling I2C driver functions.
2068 * Return: 0 on success or -1 on failure.
2071 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2073 struct i2c_adapter *adapter = data;
2074 unsigned char start = block * EDID_LENGTH;
2075 unsigned char segment = block >> 1;
2076 unsigned char xfers = segment ? 3 : 2;
2077 int ret, retries = 5;
2080 * The core I2C driver will automatically retry the transfer if the
2081 * adapter reports EAGAIN. However, we find that bit-banging transfers
2082 * are susceptible to errors under a heavily loaded machine and
2083 * generate spurious NAKs and timeouts. Retrying the transfer
2084 * of the individual block a few times seems to overcome this.
2087 struct i2c_msg msgs[] = {
2089 .addr = DDC_SEGMENT_ADDR,
2107 * Avoid sending the segment addr to not upset non-compliant
2110 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2112 if (ret == -ENXIO) {
2113 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2117 } while (ret != xfers && --retries);
2119 return ret == xfers ? 0 : -1;
2122 static void connector_bad_edid(struct drm_connector *connector,
2123 const struct edid *edid, int num_blocks)
2129 * 0x7e in the EDID is the number of extension blocks. The EDID
2130 * is 1 (base block) + num_ext_blocks big. That means we can think
2131 * of 0x7e in the EDID of the _index_ of the last block in the
2132 * combined chunk of memory.
2134 last_block = edid->extensions;
2136 /* Calculate real checksum for the last edid extension block data */
2137 if (last_block < num_blocks)
2138 connector->real_edid_checksum =
2139 edid_block_compute_checksum(edid + last_block);
2141 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2144 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
2145 for (i = 0; i < num_blocks; i++)
2146 edid_block_dump(KERN_DEBUG, edid + i, i);
2149 /* Get override or firmware EDID */
2150 static struct edid *drm_get_override_edid(struct drm_connector *connector,
2153 struct edid *override = NULL;
2155 if (connector->override_edid)
2156 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
2159 override = drm_load_edid_firmware(connector);
2161 /* FIXME: Get alloc size from deeper down the stack */
2162 if (!IS_ERR_OR_NULL(override) && alloc_size)
2163 *alloc_size = edid_size(override);
2165 return IS_ERR(override) ? NULL : override;
2168 /* For debugfs edid_override implementation */
2169 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2174 if (size < EDID_LENGTH || edid_size(edid) > size)
2177 connector->override_edid = false;
2179 ret = drm_connector_update_edid_property(connector, edid);
2181 connector->override_edid = true;
2186 /* For debugfs edid_override implementation */
2187 int drm_edid_override_reset(struct drm_connector *connector)
2189 connector->override_edid = false;
2191 return drm_connector_update_edid_property(connector, NULL);
2195 * drm_add_override_edid_modes - add modes from override/firmware EDID
2196 * @connector: connector we're probing
2198 * Add modes from the override/firmware EDID, if available. Only to be used from
2199 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2200 * failed during drm_get_edid() and caused the override/firmware EDID to be
2203 * Return: The number of modes added or 0 if we couldn't find any.
2205 int drm_add_override_edid_modes(struct drm_connector *connector)
2207 struct edid *override;
2210 override = drm_get_override_edid(connector, NULL);
2212 drm_connector_update_edid_property(connector, override);
2213 num_modes = drm_add_edid_modes(connector, override);
2216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2217 connector->base.id, connector->name, num_modes);
2222 EXPORT_SYMBOL(drm_add_override_edid_modes);
2224 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2226 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2227 read_block_fn read_block,
2230 enum edid_block_status status;
2231 bool is_base_block = block_num == 0;
2234 for (try = 0; try < 4; try++) {
2235 if (read_block(context, block, block_num, EDID_LENGTH))
2236 return EDID_BLOCK_READ_FAIL;
2238 status = edid_block_check(block, is_base_block);
2239 if (status == EDID_BLOCK_HEADER_REPAIR) {
2240 edid_header_fix(block);
2242 /* Retry with fixed header, update status if that worked. */
2243 status = edid_block_check(block, is_base_block);
2244 if (status == EDID_BLOCK_OK)
2245 status = EDID_BLOCK_HEADER_FIXED;
2248 if (edid_block_status_valid(status, edid_block_tag(block)))
2251 /* Fail early for unrepairable base block all zeros. */
2252 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2259 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2260 read_block_fn read_block, void *context,
2263 enum edid_block_status status;
2264 int i, invalid_blocks = 0;
2265 struct edid *edid, *new;
2266 size_t alloc_size = EDID_LENGTH;
2268 edid = drm_get_override_edid(connector, &alloc_size);
2272 edid = kmalloc(alloc_size, GFP_KERNEL);
2276 status = edid_block_read(edid, 0, read_block, context);
2278 edid_block_status_print(status, edid, 0);
2280 if (status == EDID_BLOCK_READ_FAIL)
2283 /* FIXME: Clarify what a corrupt EDID actually means. */
2284 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2285 connector->edid_corrupt = false;
2287 connector->edid_corrupt = true;
2289 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2290 if (status == EDID_BLOCK_ZERO)
2291 connector->null_edid_counter++;
2293 connector_bad_edid(connector, edid, 1);
2297 if (!edid_extension_block_count(edid))
2300 alloc_size = edid_size(edid);
2301 new = krealloc(edid, alloc_size, GFP_KERNEL);
2306 for (i = 1; i < edid_block_count(edid); i++) {
2307 void *block = (void *)edid_block_data(edid, i);
2309 status = edid_block_read(block, i, read_block, context);
2311 edid_block_status_print(status, block, i);
2313 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2314 if (status == EDID_BLOCK_READ_FAIL)
2320 if (invalid_blocks) {
2321 connector_bad_edid(connector, edid, edid_block_count(edid));
2323 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2338 * drm_do_get_edid - get EDID data using a custom EDID block read function
2339 * @connector: connector we're probing
2340 * @read_block: EDID block read function
2341 * @context: private data passed to the block read function
2343 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2344 * exposes a different interface to read EDID blocks this function can be used
2345 * to get EDID data using a custom block read function.
2347 * As in the general case the DDC bus is accessible by the kernel at the I2C
2348 * level, drivers must make all reasonable efforts to expose it as an I2C
2349 * adapter and use drm_get_edid() instead of abusing this function.
2351 * The EDID may be overridden using debugfs override_edid or firmware EDID
2352 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2353 * order. Having either of them bypasses actual EDID reads.
2355 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2357 struct edid *drm_do_get_edid(struct drm_connector *connector,
2358 read_block_fn read_block,
2361 return _drm_do_get_edid(connector, read_block, context, NULL);
2363 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2366 * drm_edid_raw - Get a pointer to the raw EDID data.
2367 * @drm_edid: drm_edid container
2369 * Get a pointer to the raw EDID data.
2371 * This is for transition only. Avoid using this like the plague.
2373 * Return: Pointer to raw EDID data.
2375 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2377 if (!drm_edid || !drm_edid->size)
2381 * Do not return pointers where relying on EDID extension count would
2382 * lead to buffer overflow.
2384 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2387 return drm_edid->edid;
2389 EXPORT_SYMBOL(drm_edid_raw);
2391 /* Allocate struct drm_edid container *without* duplicating the edid data */
2392 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2394 struct drm_edid *drm_edid;
2396 if (!edid || !size || size < EDID_LENGTH)
2399 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2401 drm_edid->edid = edid;
2402 drm_edid->size = size;
2409 * drm_edid_alloc - Allocate a new drm_edid container
2410 * @edid: Pointer to raw EDID data
2411 * @size: Size of memory allocated for EDID
2413 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2414 * the actual size that has been allocated for the data. There is no validation
2415 * of the raw EDID data against the size, but at least the EDID base block must
2416 * fit in the buffer.
2418 * The returned pointer must be freed using drm_edid_free().
2420 * Return: drm_edid container, or NULL on errors
2422 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2424 const struct drm_edid *drm_edid;
2426 if (!edid || !size || size < EDID_LENGTH)
2429 edid = kmemdup(edid, size, GFP_KERNEL);
2433 drm_edid = _drm_edid_alloc(edid, size);
2439 EXPORT_SYMBOL(drm_edid_alloc);
2442 * drm_edid_dup - Duplicate a drm_edid container
2443 * @drm_edid: EDID to duplicate
2445 * The returned pointer must be freed using drm_edid_free().
2447 * Returns: drm_edid container copy, or NULL on errors
2449 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2454 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2456 EXPORT_SYMBOL(drm_edid_dup);
2459 * drm_edid_free - Free the drm_edid container
2460 * @drm_edid: EDID to free
2462 void drm_edid_free(const struct drm_edid *drm_edid)
2467 kfree(drm_edid->edid);
2470 EXPORT_SYMBOL(drm_edid_free);
2473 * drm_probe_ddc() - probe DDC presence
2474 * @adapter: I2C adapter to probe
2476 * Return: True on success, false on failure.
2479 drm_probe_ddc(struct i2c_adapter *adapter)
2483 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2485 EXPORT_SYMBOL(drm_probe_ddc);
2488 * drm_get_edid - get EDID data, if available
2489 * @connector: connector we're probing
2490 * @adapter: I2C adapter to use for DDC
2492 * Poke the given I2C channel to grab EDID data if possible. If found,
2493 * attach it to the connector.
2495 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2497 struct edid *drm_get_edid(struct drm_connector *connector,
2498 struct i2c_adapter *adapter)
2502 if (connector->force == DRM_FORCE_OFF)
2505 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2508 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2509 drm_connector_update_edid_property(connector, edid);
2512 EXPORT_SYMBOL(drm_get_edid);
2515 * drm_edid_read_custom - Read EDID data using given EDID block read function
2516 * @connector: Connector to use
2517 * @read_block: EDID block read function
2518 * @context: Private data passed to the block read function
2520 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2521 * exposes a different interface to read EDID blocks this function can be used
2522 * to get EDID data using a custom block read function.
2524 * As in the general case the DDC bus is accessible by the kernel at the I2C
2525 * level, drivers must make all reasonable efforts to expose it as an I2C
2526 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2529 * The EDID may be overridden using debugfs override_edid or firmware EDID
2530 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2531 * order. Having either of them bypasses actual EDID reads.
2533 * The returned pointer must be freed using drm_edid_free().
2535 * Return: Pointer to EDID, or NULL if probe/read failed.
2537 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2538 read_block_fn read_block,
2541 const struct drm_edid *drm_edid;
2545 edid = _drm_do_get_edid(connector, read_block, context, &size);
2549 /* Sanity check for now */
2550 drm_WARN_ON(connector->dev, !size);
2552 drm_edid = _drm_edid_alloc(edid, size);
2558 EXPORT_SYMBOL(drm_edid_read_custom);
2561 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2562 * @connector: Connector to use
2563 * @adapter: I2C adapter to use for DDC
2565 * Read EDID using the given I2C adapter.
2567 * The EDID may be overridden using debugfs override_edid or firmware EDID
2568 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2569 * order. Having either of them bypasses actual EDID reads.
2571 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2572 * using drm_edid_read() instead of this function.
2574 * The returned pointer must be freed using drm_edid_free().
2576 * Return: Pointer to EDID, or NULL if probe/read failed.
2578 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2579 struct i2c_adapter *adapter)
2581 const struct drm_edid *drm_edid;
2583 if (connector->force == DRM_FORCE_OFF)
2586 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2589 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2591 /* Note: Do *not* call connector updates here. */
2595 EXPORT_SYMBOL(drm_edid_read_ddc);
2598 * drm_edid_read - Read EDID data using connector's I2C adapter
2599 * @connector: Connector to use
2601 * Read EDID using the connector's I2C adapter.
2603 * The EDID may be overridden using debugfs override_edid or firmware EDID
2604 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2605 * order. Having either of them bypasses actual EDID reads.
2607 * The returned pointer must be freed using drm_edid_free().
2609 * Return: Pointer to EDID, or NULL if probe/read failed.
2611 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2613 if (drm_WARN_ON(connector->dev, !connector->ddc))
2616 return drm_edid_read_ddc(connector, connector->ddc);
2618 EXPORT_SYMBOL(drm_edid_read);
2620 static u32 edid_extract_panel_id(const struct edid *edid)
2623 * We represent the ID as a 32-bit number so it can easily be compared
2626 * NOTE that we deal with endianness differently for the top half
2627 * of this ID than for the bottom half. The bottom half (the product
2628 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2629 * that's how everyone seems to interpret it. The top half (the mfg_id)
2630 * gets stored as big endian because that makes
2631 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2632 * to write (it's easier to extract the ASCII). It doesn't really
2633 * matter, though, as long as the number here is unique.
2635 return (u32)edid->mfg_id[0] << 24 |
2636 (u32)edid->mfg_id[1] << 16 |
2637 (u32)EDID_PRODUCT_ID(edid);
2641 * drm_edid_get_panel_id - Get a panel's ID through DDC
2642 * @adapter: I2C adapter to use for DDC
2644 * This function reads the first block of the EDID of a panel and (assuming
2645 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2646 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2647 * supposed to be different for each different modem of panel.
2649 * This function is intended to be used during early probing on devices where
2650 * more than one panel might be present. Because of its intended use it must
2651 * assume that the EDID of the panel is correct, at least as far as the ID
2652 * is concerned (in other words, we don't process any overrides here).
2654 * NOTE: it's expected that this function and drm_do_get_edid() will both
2655 * be read the EDID, but there is no caching between them. Since we're only
2656 * reading the first block, hopefully this extra overhead won't be too big.
2658 * Return: A 32-bit ID that should be different for each make/model of panel.
2659 * See the functions drm_edid_encode_panel_id() and
2660 * drm_edid_decode_panel_id() for some details on the structure of this
2664 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2666 enum edid_block_status status;
2671 * There are no manufacturer IDs of 0, so if there is a problem reading
2672 * the EDID then we'll just return 0.
2675 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2679 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2681 edid_block_status_print(status, base_block, 0);
2683 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2684 panel_id = edid_extract_panel_id(base_block);
2690 EXPORT_SYMBOL(drm_edid_get_panel_id);
2693 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2694 * @connector: connector we're probing
2695 * @adapter: I2C adapter to use for DDC
2697 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2698 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2699 * switch DDC to the GPU which is retrieving EDID.
2701 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2703 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2704 struct i2c_adapter *adapter)
2706 struct drm_device *dev = connector->dev;
2707 struct pci_dev *pdev = to_pci_dev(dev->dev);
2710 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2713 vga_switcheroo_lock_ddc(pdev);
2714 edid = drm_get_edid(connector, adapter);
2715 vga_switcheroo_unlock_ddc(pdev);
2719 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2722 * drm_edid_duplicate - duplicate an EDID and the extensions
2723 * @edid: EDID to duplicate
2725 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2727 struct edid *drm_edid_duplicate(const struct edid *edid)
2729 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2731 EXPORT_SYMBOL(drm_edid_duplicate);
2733 /*** EDID parsing ***/
2736 * edid_get_quirks - return quirk flags for a given EDID
2737 * @drm_edid: EDID to process
2739 * This tells subsequent routines what fixes they need to apply.
2741 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2743 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2744 const struct edid_quirk *quirk;
2747 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2748 quirk = &edid_quirk_list[i];
2749 if (quirk->panel_id == panel_id)
2750 return quirk->quirks;
2756 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2757 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2760 * Walk the mode list for connector, clearing the preferred status on existing
2761 * modes and setting it anew for the right mode ala quirks.
2763 static void edid_fixup_preferred(struct drm_connector *connector,
2766 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2767 int target_refresh = 0;
2768 int cur_vrefresh, preferred_vrefresh;
2770 if (list_empty(&connector->probed_modes))
2773 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2774 target_refresh = 60;
2775 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2776 target_refresh = 75;
2778 preferred_mode = list_first_entry(&connector->probed_modes,
2779 struct drm_display_mode, head);
2781 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2782 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2784 if (cur_mode == preferred_mode)
2787 /* Largest mode is preferred */
2788 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2789 preferred_mode = cur_mode;
2791 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2792 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2793 /* At a given size, try to get closest to target refresh */
2794 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2795 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2796 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2797 preferred_mode = cur_mode;
2801 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2805 mode_is_rb(const struct drm_display_mode *mode)
2807 return (mode->htotal - mode->hdisplay == 160) &&
2808 (mode->hsync_end - mode->hdisplay == 80) &&
2809 (mode->hsync_end - mode->hsync_start == 32) &&
2810 (mode->vsync_start - mode->vdisplay == 3);
2814 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2815 * @dev: Device to duplicate against
2816 * @hsize: Mode width
2817 * @vsize: Mode height
2818 * @fresh: Mode refresh rate
2819 * @rb: Mode reduced-blanking-ness
2821 * Walk the DMT mode list looking for a match for the given parameters.
2823 * Return: A newly allocated copy of the mode, or NULL if not found.
2825 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2826 int hsize, int vsize, int fresh,
2831 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2832 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2834 if (hsize != ptr->hdisplay)
2836 if (vsize != ptr->vdisplay)
2838 if (fresh != drm_mode_vrefresh(ptr))
2840 if (rb != mode_is_rb(ptr))
2843 return drm_mode_duplicate(dev, ptr);
2848 EXPORT_SYMBOL(drm_mode_find_dmt);
2850 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2852 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2853 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2854 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2856 return descriptor->pixel_clock == 0 &&
2857 descriptor->data.other_data.pad1 == 0 &&
2858 descriptor->data.other_data.type == type;
2861 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2863 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2865 return descriptor->pixel_clock != 0;
2868 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2871 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2875 const u8 *det_base = ext + d;
2877 if (d < 4 || d > 127)
2881 for (i = 0; i < n; i++)
2882 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2886 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2888 unsigned int i, n = min((int)ext[0x02], 6);
2889 const u8 *det_base = ext + 5;
2892 return; /* unknown version */
2894 for (i = 0; i < n; i++)
2895 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2898 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
2899 detailed_cb *cb, void *closure)
2901 struct drm_edid_iter edid_iter;
2908 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2909 cb(&drm_edid->edid->detailed_timings[i], closure);
2911 drm_edid_iter_begin(drm_edid, &edid_iter);
2912 drm_edid_iter_for_each(ext, &edid_iter) {
2915 cea_for_each_detailed_block(ext, cb, closure);
2918 vtb_for_each_detailed_block(ext, cb, closure);
2924 drm_edid_iter_end(&edid_iter);
2928 is_rb(const struct detailed_timing *descriptor, void *data)
2932 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2935 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2936 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2938 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2939 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2943 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2945 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
2947 if (drm_edid->edid->revision >= 4) {
2950 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
2954 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2958 find_gtf2(const struct detailed_timing *descriptor, void *data)
2960 const struct detailed_timing **res = data;
2962 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2965 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2967 if (descriptor->data.other_data.data.range.flags == 0x02)
2971 /* Secondary GTF curve kicks in above some break frequency */
2973 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
2975 const struct detailed_timing *descriptor = NULL;
2977 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
2979 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
2981 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
2985 drm_gtf2_2c(const struct drm_edid *drm_edid)
2987 const struct detailed_timing *descriptor = NULL;
2989 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
2991 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
2993 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
2997 drm_gtf2_m(const struct drm_edid *drm_edid)
2999 const struct detailed_timing *descriptor = NULL;
3001 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3003 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3005 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3009 drm_gtf2_k(const struct drm_edid *drm_edid)
3011 const struct detailed_timing *descriptor = NULL;
3013 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3015 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3017 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3021 drm_gtf2_2j(const struct drm_edid *drm_edid)
3023 const struct detailed_timing *descriptor = NULL;
3025 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3027 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3029 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3032 /* Get standard timing level (CVT/GTF/DMT). */
3033 static int standard_timing_level(const struct drm_edid *drm_edid)
3035 const struct edid *edid = drm_edid->edid;
3037 if (edid->revision >= 2) {
3038 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
3040 if (drm_gtf2_hbreak(drm_edid))
3042 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3049 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3050 * monitors fill with ascii space (0x20) instead.
3053 bad_std_timing(u8 a, u8 b)
3055 return (a == 0x00 && b == 0x00) ||
3056 (a == 0x01 && b == 0x01) ||
3057 (a == 0x20 && b == 0x20);
3060 static int drm_mode_hsync(const struct drm_display_mode *mode)
3062 if (mode->htotal <= 0)
3065 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3069 * Take the standard timing params (in this case width, aspect, and refresh)
3070 * and convert them into a real mode using CVT/GTF/DMT.
3072 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3073 const struct drm_edid *drm_edid,
3074 const struct std_timing *t)
3076 struct drm_device *dev = connector->dev;
3077 struct drm_display_mode *m, *mode = NULL;
3080 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3081 >> EDID_TIMING_ASPECT_SHIFT;
3082 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3083 >> EDID_TIMING_VFREQ_SHIFT;
3084 int timing_level = standard_timing_level(drm_edid);
3086 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3089 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3090 hsize = t->hsize * 8 + 248;
3091 /* vrefresh_rate = vfreq + 60 */
3092 vrefresh_rate = vfreq + 60;
3093 /* the vdisplay is calculated based on the aspect ratio */
3094 if (aspect_ratio == 0) {
3095 if (drm_edid->edid->revision < 3)
3098 vsize = (hsize * 10) / 16;
3099 } else if (aspect_ratio == 1)
3100 vsize = (hsize * 3) / 4;
3101 else if (aspect_ratio == 2)
3102 vsize = (hsize * 4) / 5;
3104 vsize = (hsize * 9) / 16;
3106 /* HDTV hack, part 1 */
3107 if (vrefresh_rate == 60 &&
3108 ((hsize == 1360 && vsize == 765) ||
3109 (hsize == 1368 && vsize == 769))) {
3115 * If this connector already has a mode for this size and refresh
3116 * rate (because it came from detailed or CVT info), use that
3117 * instead. This way we don't have to guess at interlace or
3120 list_for_each_entry(m, &connector->probed_modes, head)
3121 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3122 drm_mode_vrefresh(m) == vrefresh_rate)
3125 /* HDTV hack, part 2 */
3126 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3127 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3131 mode->hdisplay = 1366;
3132 mode->hsync_start = mode->hsync_start - 1;
3133 mode->hsync_end = mode->hsync_end - 1;
3137 /* check whether it can be found in default mode table */
3138 if (drm_monitor_supports_rb(drm_edid)) {
3139 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3144 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3148 /* okay, generate it */
3149 switch (timing_level) {
3153 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3157 * This is potentially wrong if there's ever a monitor with
3158 * more than one ranges section, each claiming a different
3159 * secondary GTF curve. Please don't do that.
3161 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3164 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3165 drm_mode_destroy(dev, mode);
3166 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3167 vrefresh_rate, 0, 0,
3168 drm_gtf2_m(drm_edid),
3169 drm_gtf2_2c(drm_edid),
3170 drm_gtf2_k(drm_edid),
3171 drm_gtf2_2j(drm_edid));
3175 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3183 * EDID is delightfully ambiguous about how interlaced modes are to be
3184 * encoded. Our internal representation is of frame height, but some
3185 * HDTV detailed timings are encoded as field height.
3187 * The format list here is from CEA, in frame size. Technically we
3188 * should be checking refresh rate too. Whatever.
3191 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3192 const struct detailed_pixel_timing *pt)
3195 static const struct {
3197 } cea_interlaced[] = {
3207 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3210 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3211 if ((mode->hdisplay == cea_interlaced[i].w) &&
3212 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3213 mode->vdisplay *= 2;
3214 mode->vsync_start *= 2;
3215 mode->vsync_end *= 2;
3221 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3225 * Create a new mode from an EDID detailed timing section. An EDID detailed
3226 * timing block contains enough info for us to create and return a new struct
3229 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
3230 const struct drm_edid *drm_edid,
3231 const struct detailed_timing *timing,
3234 struct drm_display_mode *mode;
3235 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3236 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3237 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3238 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3239 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3240 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3241 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3242 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3243 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3245 /* ignore tiny modes */
3246 if (hactive < 64 || vactive < 64)
3249 if (pt->misc & DRM_EDID_PT_STEREO) {
3250 DRM_DEBUG_KMS("stereo mode not supported\n");
3253 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3254 DRM_DEBUG_KMS("composite sync not supported\n");
3257 /* it is incorrect if hsync/vsync width is zero */
3258 if (!hsync_pulse_width || !vsync_pulse_width) {
3259 DRM_DEBUG_KMS("Incorrect Detailed timing. "
3260 "Wrong Hsync/Vsync pulse width\n");
3264 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3265 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3272 mode = drm_mode_create(dev);
3276 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3277 mode->clock = 1088 * 10;
3279 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3281 mode->hdisplay = hactive;
3282 mode->hsync_start = mode->hdisplay + hsync_offset;
3283 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3284 mode->htotal = mode->hdisplay + hblank;
3286 mode->vdisplay = vactive;
3287 mode->vsync_start = mode->vdisplay + vsync_offset;
3288 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3289 mode->vtotal = mode->vdisplay + vblank;
3291 /* Some EDIDs have bogus h/vtotal values */
3292 if (mode->hsync_end > mode->htotal)
3293 mode->htotal = mode->hsync_end + 1;
3294 if (mode->vsync_end > mode->vtotal)
3295 mode->vtotal = mode->vsync_end + 1;
3297 drm_mode_do_interlace_quirk(mode, pt);
3299 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3300 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3302 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3303 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3304 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3305 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3309 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3310 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3312 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3313 mode->width_mm *= 10;
3314 mode->height_mm *= 10;
3317 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3318 mode->width_mm = drm_edid->edid->width_cm * 10;
3319 mode->height_mm = drm_edid->edid->height_cm * 10;
3322 mode->type = DRM_MODE_TYPE_DRIVER;
3323 drm_mode_set_name(mode);
3329 mode_in_hsync_range(const struct drm_display_mode *mode,
3330 const struct edid *edid, const u8 *t)
3332 int hsync, hmin, hmax;
3335 if (edid->revision >= 4)
3336 hmin += ((t[4] & 0x04) ? 255 : 0);
3338 if (edid->revision >= 4)
3339 hmax += ((t[4] & 0x08) ? 255 : 0);
3340 hsync = drm_mode_hsync(mode);
3342 return (hsync <= hmax && hsync >= hmin);
3346 mode_in_vsync_range(const struct drm_display_mode *mode,
3347 const struct edid *edid, const u8 *t)
3349 int vsync, vmin, vmax;
3352 if (edid->revision >= 4)
3353 vmin += ((t[4] & 0x01) ? 255 : 0);
3355 if (edid->revision >= 4)
3356 vmax += ((t[4] & 0x02) ? 255 : 0);
3357 vsync = drm_mode_vrefresh(mode);
3359 return (vsync <= vmax && vsync >= vmin);
3363 range_pixel_clock(const struct edid *edid, const u8 *t)
3366 if (t[9] == 0 || t[9] == 255)
3369 /* 1.4 with CVT support gives us real precision, yay */
3370 if (edid->revision >= 4 && t[10] == 0x04)
3371 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3373 /* 1.3 is pathetic, so fuzz up a bit */
3374 return t[9] * 10000 + 5001;
3377 static bool mode_in_range(const struct drm_display_mode *mode,
3378 const struct drm_edid *drm_edid,
3379 const struct detailed_timing *timing)
3381 const struct edid *edid = drm_edid->edid;
3383 const u8 *t = (const u8 *)timing;
3385 if (!mode_in_hsync_range(mode, edid, t))
3388 if (!mode_in_vsync_range(mode, edid, t))
3391 if ((max_clock = range_pixel_clock(edid, t)))
3392 if (mode->clock > max_clock)
3395 /* 1.4 max horizontal check */
3396 if (edid->revision >= 4 && t[10] == 0x04)
3397 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3400 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3406 static bool valid_inferred_mode(const struct drm_connector *connector,
3407 const struct drm_display_mode *mode)
3409 const struct drm_display_mode *m;
3412 list_for_each_entry(m, &connector->probed_modes, head) {
3413 if (mode->hdisplay == m->hdisplay &&
3414 mode->vdisplay == m->vdisplay &&
3415 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3416 return false; /* duplicated */
3417 if (mode->hdisplay <= m->hdisplay &&
3418 mode->vdisplay <= m->vdisplay)
3424 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3425 const struct drm_edid *drm_edid,
3426 const struct detailed_timing *timing)
3429 struct drm_display_mode *newmode;
3430 struct drm_device *dev = connector->dev;
3432 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3433 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3434 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3435 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3437 drm_mode_probed_add(connector, newmode);
3446 /* fix up 1366x768 mode from 1368x768;
3447 * GFT/CVT can't express 1366 width which isn't dividable by 8
3449 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3451 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3452 mode->hdisplay = 1366;
3453 mode->hsync_start--;
3455 drm_mode_set_name(mode);
3459 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3460 const struct drm_edid *drm_edid,
3461 const struct detailed_timing *timing)
3464 struct drm_display_mode *newmode;
3465 struct drm_device *dev = connector->dev;
3467 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3468 const struct minimode *m = &extra_modes[i];
3470 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3474 drm_mode_fixup_1366x768(newmode);
3475 if (!mode_in_range(newmode, drm_edid, timing) ||
3476 !valid_inferred_mode(connector, newmode)) {
3477 drm_mode_destroy(dev, newmode);
3481 drm_mode_probed_add(connector, newmode);
3488 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3489 const struct drm_edid *drm_edid,
3490 const struct detailed_timing *timing)
3493 struct drm_display_mode *newmode;
3494 struct drm_device *dev = connector->dev;
3495 bool rb = drm_monitor_supports_rb(drm_edid);
3497 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3498 const struct minimode *m = &extra_modes[i];
3500 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3504 drm_mode_fixup_1366x768(newmode);
3505 if (!mode_in_range(newmode, drm_edid, timing) ||
3506 !valid_inferred_mode(connector, newmode)) {
3507 drm_mode_destroy(dev, newmode);
3511 drm_mode_probed_add(connector, newmode);
3519 do_inferred_modes(const struct detailed_timing *timing, void *c)
3521 struct detailed_mode_closure *closure = c;
3522 const struct detailed_non_pixel *data = &timing->data.other_data;
3523 const struct detailed_data_monitor_range *range = &data->data.range;
3525 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3528 closure->modes += drm_dmt_modes_for_range(closure->connector,
3532 if (!version_greater(closure->drm_edid, 1, 1))
3533 return; /* GTF not defined yet */
3535 switch (range->flags) {
3536 case 0x02: /* secondary gtf, XXX could do more */
3537 case 0x00: /* default gtf */
3538 closure->modes += drm_gtf_modes_for_range(closure->connector,
3542 case 0x04: /* cvt, only in 1.4+ */
3543 if (!version_greater(closure->drm_edid, 1, 3))
3546 closure->modes += drm_cvt_modes_for_range(closure->connector,
3550 case 0x01: /* just the ranges, no formula */
3556 static int add_inferred_modes(struct drm_connector *connector,
3557 const struct drm_edid *drm_edid)
3559 struct detailed_mode_closure closure = {
3560 .connector = connector,
3561 .drm_edid = drm_edid,
3564 if (version_greater(drm_edid, 1, 0))
3565 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3567 return closure.modes;
3571 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3573 int i, j, m, modes = 0;
3574 struct drm_display_mode *mode;
3575 const u8 *est = ((const u8 *)timing) + 6;
3577 for (i = 0; i < 6; i++) {
3578 for (j = 7; j >= 0; j--) {
3579 m = (i * 8) + (7 - j);
3580 if (m >= ARRAY_SIZE(est3_modes))
3582 if (est[i] & (1 << j)) {
3583 mode = drm_mode_find_dmt(connector->dev,
3589 drm_mode_probed_add(connector, mode);
3600 do_established_modes(const struct detailed_timing *timing, void *c)
3602 struct detailed_mode_closure *closure = c;
3604 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3607 closure->modes += drm_est3_modes(closure->connector, timing);
3611 * Get established modes from EDID and add them. Each EDID block contains a
3612 * bitmap of the supported "established modes" list (defined above). Tease them
3613 * out and add them to the global modes list.
3615 static int add_established_modes(struct drm_connector *connector,
3616 const struct drm_edid *drm_edid)
3618 struct drm_device *dev = connector->dev;
3619 const struct edid *edid = drm_edid->edid;
3620 unsigned long est_bits = edid->established_timings.t1 |
3621 (edid->established_timings.t2 << 8) |
3622 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3624 struct detailed_mode_closure closure = {
3625 .connector = connector,
3626 .drm_edid = drm_edid,
3629 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3630 if (est_bits & (1<<i)) {
3631 struct drm_display_mode *newmode;
3633 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3635 drm_mode_probed_add(connector, newmode);
3641 if (version_greater(drm_edid, 1, 0))
3642 drm_for_each_detailed_block(drm_edid, do_established_modes,
3645 return modes + closure.modes;
3649 do_standard_modes(const struct detailed_timing *timing, void *c)
3651 struct detailed_mode_closure *closure = c;
3652 const struct detailed_non_pixel *data = &timing->data.other_data;
3653 struct drm_connector *connector = closure->connector;
3656 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3659 for (i = 0; i < 6; i++) {
3660 const struct std_timing *std = &data->data.timings[i];
3661 struct drm_display_mode *newmode;
3663 newmode = drm_mode_std(connector, closure->drm_edid, std);
3665 drm_mode_probed_add(connector, newmode);
3672 * Get standard modes from EDID and add them. Standard modes can be calculated
3673 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3674 * add them to the list.
3676 static int add_standard_modes(struct drm_connector *connector,
3677 const struct drm_edid *drm_edid)
3680 struct detailed_mode_closure closure = {
3681 .connector = connector,
3682 .drm_edid = drm_edid,
3685 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3686 struct drm_display_mode *newmode;
3688 newmode = drm_mode_std(connector, drm_edid,
3689 &drm_edid->edid->standard_timings[i]);
3691 drm_mode_probed_add(connector, newmode);
3696 if (version_greater(drm_edid, 1, 0))
3697 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3700 /* XXX should also look for standard codes in VTB blocks */
3702 return modes + closure.modes;
3705 static int drm_cvt_modes(struct drm_connector *connector,
3706 const struct detailed_timing *timing)
3708 int i, j, modes = 0;
3709 struct drm_display_mode *newmode;
3710 struct drm_device *dev = connector->dev;
3711 const struct cvt_timing *cvt;
3712 const int rates[] = { 60, 85, 75, 60, 50 };
3713 const u8 empty[3] = { 0, 0, 0 };
3715 for (i = 0; i < 4; i++) {
3718 cvt = &(timing->data.other_data.data.cvt[i]);
3720 if (!memcmp(cvt->code, empty, 3))
3723 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3724 switch (cvt->code[1] & 0x0c) {
3725 /* default - because compiler doesn't see that we've enumerated all cases */
3728 width = height * 4 / 3;
3731 width = height * 16 / 9;
3734 width = height * 16 / 10;
3737 width = height * 15 / 9;
3741 for (j = 1; j < 5; j++) {
3742 if (cvt->code[2] & (1 << j)) {
3743 newmode = drm_cvt_mode(dev, width, height,
3747 drm_mode_probed_add(connector, newmode);
3758 do_cvt_mode(const struct detailed_timing *timing, void *c)
3760 struct detailed_mode_closure *closure = c;
3762 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3765 closure->modes += drm_cvt_modes(closure->connector, timing);
3769 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
3771 struct detailed_mode_closure closure = {
3772 .connector = connector,
3773 .drm_edid = drm_edid,
3776 if (version_greater(drm_edid, 1, 2))
3777 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
3779 /* XXX should also look for CVT codes in VTB blocks */
3781 return closure.modes;
3784 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3787 do_detailed_mode(const struct detailed_timing *timing, void *c)
3789 struct detailed_mode_closure *closure = c;
3790 struct drm_display_mode *newmode;
3792 if (!is_detailed_timing_descriptor(timing))
3795 newmode = drm_mode_detailed(closure->connector->dev,
3796 closure->drm_edid, timing,
3801 if (closure->preferred)
3802 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3805 * Detailed modes are limited to 10kHz pixel clock resolution,
3806 * so fix up anything that looks like CEA/HDMI mode, but the clock
3807 * is just slightly off.
3809 fixup_detailed_cea_mode_clock(newmode);
3811 drm_mode_probed_add(closure->connector, newmode);
3813 closure->preferred = false;
3817 * add_detailed_modes - Add modes from detailed timings
3818 * @connector: attached connector
3819 * @drm_edid: EDID block to scan
3820 * @quirks: quirks to apply
3822 static int add_detailed_modes(struct drm_connector *connector,
3823 const struct drm_edid *drm_edid, u32 quirks)
3825 struct detailed_mode_closure closure = {
3826 .connector = connector,
3827 .drm_edid = drm_edid,
3832 if (closure.preferred && !version_greater(drm_edid, 1, 3))
3834 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3836 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
3838 return closure.modes;
3841 /* CTA-861-H Table 60 - CTA Tag Codes */
3842 #define CTA_DB_AUDIO 1
3843 #define CTA_DB_VIDEO 2
3844 #define CTA_DB_VENDOR 3
3845 #define CTA_DB_SPEAKER 4
3846 #define CTA_DB_EXTENDED_TAG 7
3848 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
3849 #define CTA_EXT_DB_VIDEO_CAP 0
3850 #define CTA_EXT_DB_VENDOR 1
3851 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
3852 #define CTA_EXT_DB_420_VIDEO_DATA 14
3853 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
3854 #define CTA_EXT_DB_HF_SCDB 0x79
3856 #define EDID_BASIC_AUDIO (1 << 6)
3857 #define EDID_CEA_YCRCB444 (1 << 5)
3858 #define EDID_CEA_YCRCB422 (1 << 4)
3859 #define EDID_CEA_VCDB_QS (1 << 6)
3862 * Search EDID for CEA extension block.
3864 * FIXME: Prefer not returning pointers to raw EDID data.
3866 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
3867 int ext_id, int *ext_index)
3869 const u8 *edid_ext = NULL;
3872 /* No EDID or EDID extensions */
3873 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
3876 /* Find CEA extension */
3877 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
3878 edid_ext = drm_edid_extension_block_data(drm_edid, i);
3879 if (edid_block_tag(edid_ext) == ext_id)
3883 if (i >= drm_edid_extension_block_count(drm_edid))
3891 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
3892 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
3894 const struct displayid_block *block;
3895 struct displayid_iter iter;
3899 /* Look for a top level CEA extension block */
3900 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
3903 /* CEA blocks can also be found embedded in a DisplayID block */
3904 displayid_iter_edid_begin(drm_edid, &iter);
3905 displayid_iter_for_each(block, &iter) {
3906 if (block->tag == DATA_BLOCK_CTA) {
3911 displayid_iter_end(&iter);
3916 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3918 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3919 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3921 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3922 return &edid_cea_modes_1[vic - 1];
3923 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3924 return &edid_cea_modes_193[vic - 193];
3928 static u8 cea_num_vics(void)
3930 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3933 static u8 cea_next_vic(u8 vic)
3935 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3941 * Calculate the alternate clock for the CEA mode
3942 * (60Hz vs. 59.94Hz etc.)
3945 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3947 unsigned int clock = cea_mode->clock;
3949 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3953 * edid_cea_modes contains the 59.94Hz
3954 * variant for 240 and 480 line modes,
3955 * and the 60Hz variant otherwise.
3957 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3958 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3960 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3966 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3969 * For certain VICs the spec allows the vertical
3970 * front porch to vary by one or two lines.
3972 * cea_modes[] stores the variant with the shortest
3973 * vertical front porch. We can adjust the mode to
3974 * get the other variants by simply increasing the
3975 * vertical front porch length.
3977 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3978 cea_mode_for_vic(9)->vtotal != 262 ||
3979 cea_mode_for_vic(12)->vtotal != 262 ||
3980 cea_mode_for_vic(13)->vtotal != 262 ||
3981 cea_mode_for_vic(23)->vtotal != 312 ||
3982 cea_mode_for_vic(24)->vtotal != 312 ||
3983 cea_mode_for_vic(27)->vtotal != 312 ||
3984 cea_mode_for_vic(28)->vtotal != 312);
3986 if (((vic == 8 || vic == 9 ||
3987 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3988 ((vic == 23 || vic == 24 ||
3989 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3990 mode->vsync_start++;
4000 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4001 unsigned int clock_tolerance)
4003 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4006 if (!to_match->clock)
4009 if (to_match->picture_aspect_ratio)
4010 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4012 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4013 struct drm_display_mode cea_mode;
4014 unsigned int clock1, clock2;
4016 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4018 /* Check both 60Hz and 59.94Hz */
4019 clock1 = cea_mode.clock;
4020 clock2 = cea_mode_alternate_clock(&cea_mode);
4022 if (abs(to_match->clock - clock1) > clock_tolerance &&
4023 abs(to_match->clock - clock2) > clock_tolerance)
4027 if (drm_mode_match(to_match, &cea_mode, match_flags))
4029 } while (cea_mode_alternate_timings(vic, &cea_mode));
4036 * drm_match_cea_mode - look for a CEA mode matching given mode
4037 * @to_match: display mode
4039 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4042 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4044 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4047 if (!to_match->clock)
4050 if (to_match->picture_aspect_ratio)
4051 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4053 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4054 struct drm_display_mode cea_mode;
4055 unsigned int clock1, clock2;
4057 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4059 /* Check both 60Hz and 59.94Hz */
4060 clock1 = cea_mode.clock;
4061 clock2 = cea_mode_alternate_clock(&cea_mode);
4063 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4064 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4068 if (drm_mode_match(to_match, &cea_mode, match_flags))
4070 } while (cea_mode_alternate_timings(vic, &cea_mode));
4075 EXPORT_SYMBOL(drm_match_cea_mode);
4077 static bool drm_valid_cea_vic(u8 vic)
4079 return cea_mode_for_vic(vic) != NULL;
4082 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4084 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4087 return mode->picture_aspect_ratio;
4089 return HDMI_PICTURE_ASPECT_NONE;
4092 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4094 return edid_4k_modes[video_code].picture_aspect_ratio;
4098 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4102 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4104 return cea_mode_alternate_clock(hdmi_mode);
4107 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4108 unsigned int clock_tolerance)
4110 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4113 if (!to_match->clock)
4116 if (to_match->picture_aspect_ratio)
4117 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4119 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4120 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4121 unsigned int clock1, clock2;
4123 /* Make sure to also match alternate clocks */
4124 clock1 = hdmi_mode->clock;
4125 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4127 if (abs(to_match->clock - clock1) > clock_tolerance &&
4128 abs(to_match->clock - clock2) > clock_tolerance)
4131 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4139 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4140 * @to_match: display mode
4142 * An HDMI mode is one defined in the HDMI vendor specific block.
4144 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4146 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4148 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4151 if (!to_match->clock)
4154 if (to_match->picture_aspect_ratio)
4155 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4157 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4158 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4159 unsigned int clock1, clock2;
4161 /* Make sure to also match alternate clocks */
4162 clock1 = hdmi_mode->clock;
4163 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4165 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4166 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4167 drm_mode_match(to_match, hdmi_mode, match_flags))
4173 static bool drm_valid_hdmi_vic(u8 vic)
4175 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4178 static int add_alternate_cea_modes(struct drm_connector *connector,
4179 const struct drm_edid *drm_edid)
4181 struct drm_device *dev = connector->dev;
4182 struct drm_display_mode *mode, *tmp;
4186 /* Don't add CTA modes if the CTA extension block is missing */
4187 if (!drm_edid_has_cta_extension(drm_edid))
4191 * Go through all probed modes and create a new mode
4192 * with the alternate clock for certain CEA modes.
4194 list_for_each_entry(mode, &connector->probed_modes, head) {
4195 const struct drm_display_mode *cea_mode = NULL;
4196 struct drm_display_mode *newmode;
4197 u8 vic = drm_match_cea_mode(mode);
4198 unsigned int clock1, clock2;
4200 if (drm_valid_cea_vic(vic)) {
4201 cea_mode = cea_mode_for_vic(vic);
4202 clock2 = cea_mode_alternate_clock(cea_mode);
4204 vic = drm_match_hdmi_mode(mode);
4205 if (drm_valid_hdmi_vic(vic)) {
4206 cea_mode = &edid_4k_modes[vic];
4207 clock2 = hdmi_mode_alternate_clock(cea_mode);
4214 clock1 = cea_mode->clock;
4216 if (clock1 == clock2)
4219 if (mode->clock != clock1 && mode->clock != clock2)
4222 newmode = drm_mode_duplicate(dev, cea_mode);
4226 /* Carry over the stereo flags */
4227 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4230 * The current mode could be either variant. Make
4231 * sure to pick the "other" clock for the new mode.
4233 if (mode->clock != clock1)
4234 newmode->clock = clock1;
4236 newmode->clock = clock2;
4238 list_add_tail(&newmode->head, &list);
4241 list_for_each_entry_safe(mode, tmp, &list, head) {
4242 list_del(&mode->head);
4243 drm_mode_probed_add(connector, mode);
4250 static u8 svd_to_vic(u8 svd)
4252 /* 0-6 bit vic, 7th bit native mode indicator */
4253 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4259 static struct drm_display_mode *
4260 drm_display_mode_from_vic_index(struct drm_connector *connector,
4261 const u8 *video_db, u8 video_len,
4264 struct drm_device *dev = connector->dev;
4265 struct drm_display_mode *newmode;
4268 if (video_db == NULL || video_index >= video_len)
4271 /* CEA modes are numbered 1..127 */
4272 vic = svd_to_vic(video_db[video_index]);
4273 if (!drm_valid_cea_vic(vic))
4276 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4284 * do_y420vdb_modes - Parse YCBCR 420 only modes
4285 * @connector: connector corresponding to the HDMI sink
4286 * @svds: start of the data block of CEA YCBCR 420 VDB
4287 * @len: length of the CEA YCBCR 420 VDB
4289 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4290 * which contains modes which can be supported in YCBCR 420
4291 * output format only.
4293 static int do_y420vdb_modes(struct drm_connector *connector,
4294 const u8 *svds, u8 svds_len)
4297 struct drm_device *dev = connector->dev;
4298 struct drm_display_info *info = &connector->display_info;
4299 struct drm_hdmi_info *hdmi = &info->hdmi;
4301 for (i = 0; i < svds_len; i++) {
4302 u8 vic = svd_to_vic(svds[i]);
4303 struct drm_display_mode *newmode;
4305 if (!drm_valid_cea_vic(vic))
4308 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4311 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4312 drm_mode_probed_add(connector, newmode);
4317 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4322 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4323 * @connector: connector corresponding to the HDMI sink
4324 * @vic: CEA vic for the video mode to be added in the map
4326 * Makes an entry for a videomode in the YCBCR 420 bitmap
4329 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4331 u8 vic = svd_to_vic(svd);
4332 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4334 if (!drm_valid_cea_vic(vic))
4337 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4341 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4343 * @video_code: CEA VIC of the mode
4345 * Creates a new mode matching the specified CEA VIC.
4347 * Returns: A new drm_display_mode on success or NULL on failure
4349 struct drm_display_mode *
4350 drm_display_mode_from_cea_vic(struct drm_device *dev,
4353 const struct drm_display_mode *cea_mode;
4354 struct drm_display_mode *newmode;
4356 cea_mode = cea_mode_for_vic(video_code);
4360 newmode = drm_mode_duplicate(dev, cea_mode);
4366 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4369 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4372 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4374 for (i = 0; i < len; i++) {
4375 struct drm_display_mode *mode;
4377 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4380 * YCBCR420 capability block contains a bitmap which
4381 * gives the index of CEA modes from CEA VDB, which
4382 * can support YCBCR 420 sampling output also (apart
4383 * from RGB/YCBCR444 etc).
4384 * For example, if the bit 0 in bitmap is set,
4385 * first mode in VDB can support YCBCR420 output too.
4386 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4388 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4389 drm_add_cmdb_modes(connector, db[i]);
4391 drm_mode_probed_add(connector, mode);
4399 struct stereo_mandatory_mode {
4400 int width, height, vrefresh;
4404 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4405 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4406 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4408 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4410 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4411 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4412 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4413 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4414 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4418 stereo_match_mandatory(const struct drm_display_mode *mode,
4419 const struct stereo_mandatory_mode *stereo_mode)
4421 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4423 return mode->hdisplay == stereo_mode->width &&
4424 mode->vdisplay == stereo_mode->height &&
4425 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4426 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4429 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4431 struct drm_device *dev = connector->dev;
4432 const struct drm_display_mode *mode;
4433 struct list_head stereo_modes;
4436 INIT_LIST_HEAD(&stereo_modes);
4438 list_for_each_entry(mode, &connector->probed_modes, head) {
4439 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4440 const struct stereo_mandatory_mode *mandatory;
4441 struct drm_display_mode *new_mode;
4443 if (!stereo_match_mandatory(mode,
4444 &stereo_mandatory_modes[i]))
4447 mandatory = &stereo_mandatory_modes[i];
4448 new_mode = drm_mode_duplicate(dev, mode);
4452 new_mode->flags |= mandatory->flags;
4453 list_add_tail(&new_mode->head, &stereo_modes);
4458 list_splice_tail(&stereo_modes, &connector->probed_modes);
4463 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4465 struct drm_device *dev = connector->dev;
4466 struct drm_display_mode *newmode;
4468 if (!drm_valid_hdmi_vic(vic)) {
4469 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4473 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4477 drm_mode_probed_add(connector, newmode);
4482 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4483 const u8 *video_db, u8 video_len, u8 video_index)
4485 struct drm_display_mode *newmode;
4488 if (structure & (1 << 0)) {
4489 newmode = drm_display_mode_from_vic_index(connector, video_db,
4493 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4494 drm_mode_probed_add(connector, newmode);
4498 if (structure & (1 << 6)) {
4499 newmode = drm_display_mode_from_vic_index(connector, video_db,
4503 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4504 drm_mode_probed_add(connector, newmode);
4508 if (structure & (1 << 8)) {
4509 newmode = drm_display_mode_from_vic_index(connector, video_db,
4513 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4514 drm_mode_probed_add(connector, newmode);
4523 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4524 * @connector: connector corresponding to the HDMI sink
4525 * @db: start of the CEA vendor specific block
4526 * @len: length of the CEA block payload, ie. one can access up to db[len]
4528 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4529 * also adds the stereo 3d modes when applicable.
4532 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4533 const u8 *video_db, u8 video_len)
4535 struct drm_display_info *info = &connector->display_info;
4536 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4537 u8 vic_len, hdmi_3d_len = 0;
4544 /* no HDMI_Video_Present */
4545 if (!(db[8] & (1 << 5)))
4548 /* Latency_Fields_Present */
4549 if (db[8] & (1 << 7))
4552 /* I_Latency_Fields_Present */
4553 if (db[8] & (1 << 6))
4556 /* the declared length is not long enough for the 2 first bytes
4557 * of additional video format capabilities */
4558 if (len < (8 + offset + 2))
4563 if (db[8 + offset] & (1 << 7)) {
4564 modes += add_hdmi_mandatory_stereo_modes(connector);
4566 /* 3D_Multi_present */
4567 multi_present = (db[8 + offset] & 0x60) >> 5;
4571 vic_len = db[8 + offset] >> 5;
4572 hdmi_3d_len = db[8 + offset] & 0x1f;
4574 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4577 vic = db[9 + offset + i];
4578 modes += add_hdmi_mode(connector, vic);
4580 offset += 1 + vic_len;
4582 if (multi_present == 1)
4584 else if (multi_present == 2)
4589 if (len < (8 + offset + hdmi_3d_len - 1))
4592 if (hdmi_3d_len < multi_len)
4595 if (multi_present == 1 || multi_present == 2) {
4596 /* 3D_Structure_ALL */
4597 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4599 /* check if 3D_MASK is present */
4600 if (multi_present == 2)
4601 mask = (db[10 + offset] << 8) | db[11 + offset];
4605 for (i = 0; i < 16; i++) {
4606 if (mask & (1 << i))
4607 modes += add_3d_struct_modes(connector,
4614 offset += multi_len;
4616 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4618 struct drm_display_mode *newmode = NULL;
4619 unsigned int newflag = 0;
4620 bool detail_present;
4622 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4624 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4627 /* 2D_VIC_order_X */
4628 vic_index = db[8 + offset + i] >> 4;
4630 /* 3D_Structure_X */
4631 switch (db[8 + offset + i] & 0x0f) {
4633 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4636 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4640 if ((db[9 + offset + i] >> 4) == 1)
4641 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4646 newmode = drm_display_mode_from_vic_index(connector,
4652 newmode->flags |= newflag;
4653 drm_mode_probed_add(connector, newmode);
4664 info->has_hdmi_infoframe = true;
4669 cea_revision(const u8 *cea)
4672 * FIXME is this correct for the DispID variant?
4673 * The DispID spec doesn't really specify whether
4674 * this is the revision of the CEA extension or
4675 * the DispID CEA data block. And the only value
4676 * given as an example is 0.
4682 * CTA Data Block iterator.
4684 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4687 * struct cea_db *db:
4688 * struct cea_db_iter iter;
4690 * cea_db_iter_edid_begin(edid, &iter);
4691 * cea_db_iter_for_each(db, &iter) {
4692 * // do stuff with db
4694 * cea_db_iter_end(&iter);
4696 struct cea_db_iter {
4697 struct drm_edid_iter edid_iter;
4698 struct displayid_iter displayid_iter;
4700 /* Current Data Block Collection. */
4701 const u8 *collection;
4703 /* Current Data Block index in current collection. */
4706 /* End index in current collection. */
4710 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4716 static int cea_db_tag(const struct cea_db *db)
4718 return db->tag_length >> 5;
4721 static int cea_db_payload_len(const void *_db)
4723 /* FIXME: Transition to passing struct cea_db * everywhere. */
4724 const struct cea_db *db = _db;
4726 return db->tag_length & 0x1f;
4729 static const void *cea_db_data(const struct cea_db *db)
4734 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4736 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4737 cea_db_payload_len(db) >= 1 &&
4741 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4743 const u8 *data = cea_db_data(db);
4745 return cea_db_tag(db) == CTA_DB_VENDOR &&
4746 cea_db_payload_len(db) >= 3 &&
4747 oui(data[2], data[1], data[0]) == vendor_oui;
4750 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4751 struct cea_db_iter *iter)
4753 memset(iter, 0, sizeof(*iter));
4755 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4756 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4759 static const struct cea_db *
4760 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4762 const struct cea_db *db;
4764 if (!iter->collection)
4767 db = (const struct cea_db *)&iter->collection[iter->index];
4769 if (iter->index + sizeof(*db) <= iter->end &&
4770 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4778 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4780 static int cea_db_collection_size(const u8 *cta)
4784 if (d < 4 || d > 127)
4792 * - VESA E-EDID v1.4
4793 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4795 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4799 drm_edid_iter_for_each(ext, &iter->edid_iter) {
4802 /* Only support CTA Extension revision 3+ */
4803 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4806 size = cea_db_collection_size(ext);
4811 iter->end = iter->index + size;
4821 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4822 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4824 * Note that the above do not specify any connection between DisplayID Data
4825 * Block revision and CTA Extension versions.
4827 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4829 const struct displayid_block *block;
4831 displayid_iter_for_each(block, &iter->displayid_iter) {
4832 if (block->tag != DATA_BLOCK_CTA)
4836 * The displayid iterator has already verified the block bounds
4837 * in displayid_iter_block().
4839 iter->index = sizeof(*block);
4840 iter->end = iter->index + block->num_bytes;
4848 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
4850 const struct cea_db *db;
4852 if (iter->collection) {
4853 /* Current collection should always be valid. */
4854 db = __cea_db_iter_current_block(iter);
4856 iter->collection = NULL;
4860 /* Next block in CTA Data Block Collection */
4861 iter->index += sizeof(*db) + cea_db_payload_len(db);
4863 db = __cea_db_iter_current_block(iter);
4870 * Find the next CTA Data Block Collection. First iterate all
4871 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
4873 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
4874 * Extension, it's recommended that DisplayID extensions are
4875 * exposed after all of the CTA Extensions.
4877 iter->collection = __cea_db_iter_edid_next(iter);
4878 if (!iter->collection)
4879 iter->collection = __cea_db_iter_displayid_next(iter);
4881 if (!iter->collection)
4884 db = __cea_db_iter_current_block(iter);
4890 #define cea_db_iter_for_each(__db, __iter) \
4891 while (((__db) = __cea_db_iter_next(__iter)))
4893 static void cea_db_iter_end(struct cea_db_iter *iter)
4895 displayid_iter_end(&iter->displayid_iter);
4896 drm_edid_iter_end(&iter->edid_iter);
4898 memset(iter, 0, sizeof(*iter));
4901 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
4903 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
4904 cea_db_payload_len(db) >= 5;
4907 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
4909 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
4910 cea_db_payload_len(db) >= 7;
4913 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
4915 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
4916 cea_db_payload_len(db) == 21;
4919 static bool cea_db_is_vcdb(const struct cea_db *db)
4921 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
4922 cea_db_payload_len(db) == 2;
4925 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
4927 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
4928 cea_db_payload_len(db) >= 7;
4931 static bool cea_db_is_y420cmdb(const struct cea_db *db)
4933 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
4936 static bool cea_db_is_y420vdb(const struct cea_db *db)
4938 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
4941 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
4943 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
4944 cea_db_payload_len(db) >= 3;
4947 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4950 struct drm_display_info *info = &connector->display_info;
4951 struct drm_hdmi_info *hdmi = &info->hdmi;
4952 u8 map_len = cea_db_payload_len(db) - 1;
4957 /* All CEA modes support ycbcr420 sampling also.*/
4958 hdmi->y420_cmdb_map = U64_MAX;
4959 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4964 * This map indicates which of the existing CEA block modes
4965 * from VDB can support YCBCR420 output too. So if bit=0 is
4966 * set, first mode from VDB can support YCBCR420 output too.
4967 * We will parse and keep this map, before parsing VDB itself
4968 * to avoid going through the same block again and again.
4970 * Spec is not clear about max possible size of this block.
4971 * Clamping max bitmap block size at 8 bytes. Every byte can
4972 * address 8 CEA modes, in this way this map can address
4973 * 8*8 = first 64 SVDs.
4975 if (WARN_ON_ONCE(map_len > 8))
4978 for (count = 0; count < map_len; count++)
4979 map |= (u64)db[2 + count] << (8 * count);
4982 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4984 hdmi->y420_cmdb_map = map;
4987 static int add_cea_modes(struct drm_connector *connector,
4988 const struct drm_edid *drm_edid)
4990 const struct cea_db *db;
4991 struct cea_db_iter iter;
4994 cea_db_iter_edid_begin(drm_edid, &iter);
4995 cea_db_iter_for_each(db, &iter) {
4996 const u8 *hdmi = NULL, *video = NULL;
4997 u8 hdmi_len = 0, video_len = 0;
4999 if (cea_db_tag(db) == CTA_DB_VIDEO) {
5000 video = cea_db_data(db);
5001 video_len = cea_db_payload_len(db);
5002 modes += do_cea_modes(connector, video, video_len);
5003 } else if (cea_db_is_hdmi_vsdb(db)) {
5004 /* FIXME: Switch to use cea_db_data() */
5005 hdmi = (const u8 *)db;
5006 hdmi_len = cea_db_payload_len(db);
5007 } else if (cea_db_is_y420vdb(db)) {
5008 const u8 *vdb420 = cea_db_data(db) + 1;
5010 /* Add 4:2:0(only) modes present in EDID */
5011 modes += do_y420vdb_modes(connector, vdb420,
5012 cea_db_payload_len(db) - 1);
5016 * We parse the HDMI VSDB after having added the cea modes as we
5017 * will be patching their flags when the sink supports stereo
5021 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
5024 cea_db_iter_end(&iter);
5029 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
5031 const struct drm_display_mode *cea_mode;
5032 int clock1, clock2, clock;
5037 * allow 5kHz clock difference either way to account for
5038 * the 10kHz clock resolution limit of detailed timings.
5040 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5041 if (drm_valid_cea_vic(vic)) {
5043 cea_mode = cea_mode_for_vic(vic);
5044 clock1 = cea_mode->clock;
5045 clock2 = cea_mode_alternate_clock(cea_mode);
5047 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5048 if (drm_valid_hdmi_vic(vic)) {
5050 cea_mode = &edid_4k_modes[vic];
5051 clock1 = cea_mode->clock;
5052 clock2 = hdmi_mode_alternate_clock(cea_mode);
5058 /* pick whichever is closest */
5059 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5064 if (mode->clock == clock)
5067 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5068 type, vic, mode->clock, clock);
5069 mode->clock = clock;
5072 static uint8_t eotf_supported(const u8 *edid_ext)
5074 return edid_ext[2] &
5075 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5076 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5077 BIT(HDMI_EOTF_SMPTE_ST2084) |
5078 BIT(HDMI_EOTF_BT_2100_HLG));
5081 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5083 return edid_ext[3] &
5084 BIT(HDMI_STATIC_METADATA_TYPE1);
5088 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5092 len = cea_db_payload_len(db);
5094 connector->hdr_sink_metadata.hdmi_type1.eotf =
5096 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5097 hdr_metadata_type(db);
5100 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5102 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5104 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5108 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5110 u8 len = cea_db_payload_len(db);
5112 if (len >= 6 && (db[6] & (1 << 7)))
5113 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5115 connector->latency_present[0] = db[8] >> 7;
5116 connector->latency_present[1] = (db[8] >> 6) & 1;
5119 connector->video_latency[0] = db[9];
5121 connector->audio_latency[0] = db[10];
5123 connector->video_latency[1] = db[11];
5125 connector->audio_latency[1] = db[12];
5127 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
5128 "video latency %d %d, "
5129 "audio latency %d %d\n",
5130 connector->latency_present[0],
5131 connector->latency_present[1],
5132 connector->video_latency[0],
5133 connector->video_latency[1],
5134 connector->audio_latency[0],
5135 connector->audio_latency[1]);
5139 monitor_name(const struct detailed_timing *timing, void *data)
5141 const char **res = data;
5143 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5146 *res = timing->data.other_data.data.str.str;
5149 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5151 const char *edid_name = NULL;
5154 if (!drm_edid || !name)
5157 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5158 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5159 if (edid_name[mnl] == 0x0a)
5162 name[mnl] = edid_name[mnl];
5169 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5170 * @edid: monitor EDID information
5171 * @name: pointer to a character array to hold the name of the monitor
5172 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5175 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5177 int name_length = 0;
5184 struct drm_edid drm_edid = {
5186 .size = edid_size(edid),
5189 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5190 memcpy(name, buf, name_length);
5193 name[name_length] = '\0';
5195 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5197 static void clear_eld(struct drm_connector *connector)
5199 memset(connector->eld, 0, sizeof(connector->eld));
5201 connector->latency_present[0] = false;
5202 connector->latency_present[1] = false;
5203 connector->video_latency[0] = 0;
5204 connector->audio_latency[0] = 0;
5205 connector->video_latency[1] = 0;
5206 connector->audio_latency[1] = 0;
5210 * drm_edid_to_eld - build ELD from EDID
5211 * @connector: connector corresponding to the HDMI/DP sink
5212 * @drm_edid: EDID to parse
5214 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5215 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5217 static void drm_edid_to_eld(struct drm_connector *connector,
5218 const struct drm_edid *drm_edid)
5220 const struct drm_display_info *info = &connector->display_info;
5221 const struct cea_db *db;
5222 struct cea_db_iter iter;
5223 uint8_t *eld = connector->eld;
5224 int total_sad_count = 0;
5227 clear_eld(connector);
5232 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5233 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
5235 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5236 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5238 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5240 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5241 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5242 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5243 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5245 cea_db_iter_edid_begin(drm_edid, &iter);
5246 cea_db_iter_for_each(db, &iter) {
5247 const u8 *data = cea_db_data(db);
5248 int len = cea_db_payload_len(db);
5251 switch (cea_db_tag(db)) {
5253 /* Audio Data Block, contains SADs */
5254 sad_count = min(len / 3, 15 - total_sad_count);
5256 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5257 data, sad_count * 3);
5258 total_sad_count += sad_count;
5260 case CTA_DB_SPEAKER:
5261 /* Speaker Allocation Data Block */
5263 eld[DRM_ELD_SPEAKER] = data[0];
5266 /* HDMI Vendor-Specific Data Block */
5267 if (cea_db_is_hdmi_vsdb(db))
5268 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5274 cea_db_iter_end(&iter);
5276 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5278 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5279 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5280 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5282 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5284 eld[DRM_ELD_BASELINE_ELD_LEN] =
5285 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5287 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
5288 drm_eld_size(eld), total_sad_count);
5291 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5292 struct cea_sad **sads)
5294 const struct cea_db *db;
5295 struct cea_db_iter iter;
5298 cea_db_iter_edid_begin(drm_edid, &iter);
5299 cea_db_iter_for_each(db, &iter) {
5300 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5303 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5304 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5307 for (j = 0; j < count; j++) {
5308 const u8 *sad = &db->data[j * 3];
5310 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5311 (*sads)[j].channels = sad[0] & 0x7;
5312 (*sads)[j].freq = sad[1] & 0x7F;
5313 (*sads)[j].byte2 = sad[2];
5318 cea_db_iter_end(&iter);
5320 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5326 * drm_edid_to_sad - extracts SADs from EDID
5327 * @edid: EDID to parse
5328 * @sads: pointer that will be set to the extracted SADs
5330 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5332 * Note: The returned pointer needs to be freed using kfree().
5334 * Return: The number of found SADs or negative number on error.
5336 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5338 struct drm_edid drm_edid;
5340 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5342 EXPORT_SYMBOL(drm_edid_to_sad);
5344 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5347 const struct cea_db *db;
5348 struct cea_db_iter iter;
5351 cea_db_iter_edid_begin(drm_edid, &iter);
5352 cea_db_iter_for_each(db, &iter) {
5353 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5354 cea_db_payload_len(db) == 3) {
5355 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5359 count = cea_db_payload_len(db);
5363 cea_db_iter_end(&iter);
5365 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5371 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5372 * @edid: EDID to parse
5373 * @sadb: pointer to the speaker block
5375 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5377 * Note: The returned pointer needs to be freed using kfree().
5379 * Return: The number of found Speaker Allocation Blocks or negative number on
5382 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5384 struct drm_edid drm_edid;
5386 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5389 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5392 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5393 * @connector: connector associated with the HDMI/DP sink
5394 * @mode: the display mode
5396 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5397 * the sink doesn't support audio or video.
5399 int drm_av_sync_delay(struct drm_connector *connector,
5400 const struct drm_display_mode *mode)
5402 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5405 if (!connector->latency_present[0])
5407 if (!connector->latency_present[1])
5410 a = connector->audio_latency[i];
5411 v = connector->video_latency[i];
5414 * HDMI/DP sink doesn't support audio or video?
5416 if (a == 255 || v == 255)
5420 * Convert raw EDID values to millisecond.
5421 * Treat unknown latency as 0ms.
5424 a = min(2 * (a - 1), 500);
5426 v = min(2 * (v - 1), 500);
5428 return max(v - a, 0);
5430 EXPORT_SYMBOL(drm_av_sync_delay);
5432 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5434 const struct cea_db *db;
5435 struct cea_db_iter iter;
5439 * Because HDMI identifier is in Vendor Specific Block,
5440 * search it from all data blocks of CEA extension.
5442 cea_db_iter_edid_begin(drm_edid, &iter);
5443 cea_db_iter_for_each(db, &iter) {
5444 if (cea_db_is_hdmi_vsdb(db)) {
5449 cea_db_iter_end(&iter);
5455 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5456 * @edid: monitor EDID information
5458 * Parse the CEA extension according to CEA-861-B.
5460 * Drivers that have added the modes parsed from EDID to drm_display_info
5461 * should use &drm_display_info.is_hdmi instead of calling this function.
5463 * Return: True if the monitor is HDMI, false if not or unknown.
5465 bool drm_detect_hdmi_monitor(const struct edid *edid)
5467 struct drm_edid drm_edid;
5469 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5471 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5473 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5475 struct drm_edid_iter edid_iter;
5476 const struct cea_db *db;
5477 struct cea_db_iter iter;
5479 bool has_audio = false;
5481 drm_edid_iter_begin(drm_edid, &edid_iter);
5482 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5483 if (edid_ext[0] == CEA_EXT) {
5484 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5489 drm_edid_iter_end(&edid_iter);
5492 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5496 cea_db_iter_edid_begin(drm_edid, &iter);
5497 cea_db_iter_for_each(db, &iter) {
5498 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5499 const u8 *data = cea_db_data(db);
5502 for (i = 0; i < cea_db_payload_len(db); i += 3)
5503 DRM_DEBUG_KMS("CEA audio format %d\n",
5504 (data[i] >> 3) & 0xf);
5509 cea_db_iter_end(&iter);
5516 * drm_detect_monitor_audio - check monitor audio capability
5517 * @edid: EDID block to scan
5519 * Monitor should have CEA extension block.
5520 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5521 * audio' only. If there is any audio extension block and supported
5522 * audio format, assume at least 'basic audio' support, even if 'basic
5523 * audio' is not defined in EDID.
5525 * Return: True if the monitor supports audio, false otherwise.
5527 bool drm_detect_monitor_audio(const struct edid *edid)
5529 struct drm_edid drm_edid;
5531 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5533 EXPORT_SYMBOL(drm_detect_monitor_audio);
5537 * drm_default_rgb_quant_range - default RGB quantization range
5538 * @mode: display mode
5540 * Determine the default RGB quantization range for the mode,
5541 * as specified in CEA-861.
5543 * Return: The default RGB quantization range for the mode
5545 enum hdmi_quantization_range
5546 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5548 /* All CEA modes other than VIC 1 use limited quantization range. */
5549 return drm_match_cea_mode(mode) > 1 ?
5550 HDMI_QUANTIZATION_RANGE_LIMITED :
5551 HDMI_QUANTIZATION_RANGE_FULL;
5553 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5555 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5557 struct drm_display_info *info = &connector->display_info;
5559 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5561 if (db[2] & EDID_CEA_VCDB_QS)
5562 info->rgb_quant_range_selectable = true;
5566 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5568 switch (max_frl_rate) {
5571 *max_rate_per_lane = 3;
5575 *max_rate_per_lane = 6;
5579 *max_rate_per_lane = 6;
5583 *max_rate_per_lane = 8;
5587 *max_rate_per_lane = 10;
5591 *max_rate_per_lane = 12;
5596 *max_rate_per_lane = 0;
5600 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5604 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5606 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5607 hdmi->y420_dc_modes = dc_mask;
5610 /* Sink Capability Data Structure */
5611 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5614 struct drm_display_info *display = &connector->display_info;
5615 struct drm_hdmi_info *hdmi = &display->hdmi;
5617 display->has_hdmi_infoframe = true;
5619 if (hf_scds[6] & 0x80) {
5620 hdmi->scdc.supported = true;
5621 if (hf_scds[6] & 0x40)
5622 hdmi->scdc.read_request = true;
5626 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5627 * And as per the spec, three factors confirm this:
5628 * * Availability of a HF-VSDB block in EDID (check)
5629 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5630 * * SCDC support available (let's check)
5631 * Lets check it out.
5635 /* max clock is 5000 KHz times block value */
5636 u32 max_tmds_clock = hf_scds[5] * 5000;
5637 struct drm_scdc *scdc = &hdmi->scdc;
5639 if (max_tmds_clock > 340000) {
5640 display->max_tmds_clock = max_tmds_clock;
5641 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5642 display->max_tmds_clock);
5645 if (scdc->supported) {
5646 scdc->scrambling.supported = true;
5648 /* Few sinks support scrambling for clocks < 340M */
5649 if ((hf_scds[6] & 0x8))
5650 scdc->scrambling.low_rates = true;
5656 u8 dsc_max_frl_rate;
5658 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5660 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5661 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5662 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5663 &hdmi->max_frl_rate_per_lane);
5664 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5666 if (hdmi_dsc->v_1p2) {
5667 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5668 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5670 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5671 hdmi_dsc->bpc_supported = 16;
5672 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5673 hdmi_dsc->bpc_supported = 12;
5674 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5675 hdmi_dsc->bpc_supported = 10;
5677 hdmi_dsc->bpc_supported = 0;
5679 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5680 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5681 &hdmi_dsc->max_frl_rate_per_lane);
5682 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5684 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5685 switch (dsc_max_slices) {
5687 hdmi_dsc->max_slices = 1;
5688 hdmi_dsc->clk_per_slice = 340;
5691 hdmi_dsc->max_slices = 2;
5692 hdmi_dsc->clk_per_slice = 340;
5695 hdmi_dsc->max_slices = 4;
5696 hdmi_dsc->clk_per_slice = 340;
5699 hdmi_dsc->max_slices = 8;
5700 hdmi_dsc->clk_per_slice = 340;
5703 hdmi_dsc->max_slices = 8;
5704 hdmi_dsc->clk_per_slice = 400;
5707 hdmi_dsc->max_slices = 12;
5708 hdmi_dsc->clk_per_slice = 400;
5711 hdmi_dsc->max_slices = 16;
5712 hdmi_dsc->clk_per_slice = 400;
5716 hdmi_dsc->max_slices = 0;
5717 hdmi_dsc->clk_per_slice = 0;
5722 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
5725 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5728 struct drm_display_info *info = &connector->display_info;
5729 unsigned int dc_bpc = 0;
5731 /* HDMI supports at least 8 bpc */
5734 if (cea_db_payload_len(hdmi) < 6)
5737 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5739 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
5740 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5744 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5746 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
5747 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5751 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5753 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
5754 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5759 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5764 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5765 connector->name, dc_bpc);
5768 /* YCRCB444 is optional according to spec. */
5769 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5770 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
5771 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5776 * Spec says that if any deep color mode is supported at all,
5777 * then deep color 36 bit must be supported.
5779 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5780 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5786 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5788 struct drm_display_info *info = &connector->display_info;
5789 u8 len = cea_db_payload_len(db);
5791 info->is_hdmi = true;
5794 info->dvi_dual = db[6] & 1;
5796 info->max_tmds_clock = db[7] * 5000;
5798 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5799 "max TMDS clock %d kHz\n",
5801 info->max_tmds_clock);
5803 drm_parse_hdmi_deep_color_info(connector, db);
5807 * See EDID extension for head-mounted and specialized monitors, specified at:
5808 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5810 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5813 struct drm_display_info *info = &connector->display_info;
5815 bool desktop_usage = db[5] & BIT(6);
5817 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5818 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5819 info->non_desktop = true;
5821 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5825 static void drm_parse_cea_ext(struct drm_connector *connector,
5826 const struct drm_edid *drm_edid)
5828 struct drm_display_info *info = &connector->display_info;
5829 struct drm_edid_iter edid_iter;
5830 const struct cea_db *db;
5831 struct cea_db_iter iter;
5834 drm_edid_iter_begin(drm_edid, &edid_iter);
5835 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5836 if (edid_ext[0] != CEA_EXT)
5840 info->cea_rev = edid_ext[1];
5842 if (info->cea_rev != edid_ext[1])
5843 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",
5844 info->cea_rev, edid_ext[1]);
5846 /* The existence of a CTA extension should imply RGB support */
5847 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5848 if (edid_ext[3] & EDID_CEA_YCRCB444)
5849 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5850 if (edid_ext[3] & EDID_CEA_YCRCB422)
5851 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5853 drm_edid_iter_end(&edid_iter);
5855 cea_db_iter_edid_begin(drm_edid, &iter);
5856 cea_db_iter_for_each(db, &iter) {
5857 /* FIXME: convert parsers to use struct cea_db */
5858 const u8 *data = (const u8 *)db;
5860 if (cea_db_is_hdmi_vsdb(db))
5861 drm_parse_hdmi_vsdb_video(connector, data);
5862 else if (cea_db_is_hdmi_forum_vsdb(db) ||
5863 cea_db_is_hdmi_forum_scdb(db))
5864 drm_parse_hdmi_forum_scds(connector, data);
5865 else if (cea_db_is_microsoft_vsdb(db))
5866 drm_parse_microsoft_vsdb(connector, data);
5867 else if (cea_db_is_y420cmdb(db))
5868 drm_parse_y420cmdb_bitmap(connector, data);
5869 else if (cea_db_is_vcdb(db))
5870 drm_parse_vcdb(connector, data);
5871 else if (cea_db_is_hdmi_hdr_metadata_block(db))
5872 drm_parse_hdr_metadata_block(connector, data);
5874 cea_db_iter_end(&iter);
5878 void get_monitor_range(const struct detailed_timing *timing,
5879 void *info_monitor_range)
5881 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5882 const struct detailed_non_pixel *data = &timing->data.other_data;
5883 const struct detailed_data_monitor_range *range = &data->data.range;
5885 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
5889 * Check for flag range limits only. If flag == 1 then
5890 * no additional timing information provided.
5891 * Default GTF, GTF Secondary curve and CVT are not
5894 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5897 monitor_range->min_vfreq = range->min_vfreq;
5898 monitor_range->max_vfreq = range->max_vfreq;
5901 static void drm_get_monitor_range(struct drm_connector *connector,
5902 const struct drm_edid *drm_edid)
5904 struct drm_display_info *info = &connector->display_info;
5906 if (!version_greater(drm_edid, 1, 1))
5909 drm_for_each_detailed_block(drm_edid, get_monitor_range,
5910 &info->monitor_range);
5912 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5913 info->monitor_range.min_vfreq,
5914 info->monitor_range.max_vfreq);
5917 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5918 const struct displayid_block *block)
5920 struct displayid_vesa_vendor_specific_block *vesa =
5921 (struct displayid_vesa_vendor_specific_block *)block;
5922 struct drm_display_info *info = &connector->display_info;
5924 if (block->num_bytes < 3) {
5925 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5930 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5933 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5934 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5938 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5940 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5943 info->mso_stream_count = 0;
5946 info->mso_stream_count = 2; /* 2 or 4 links */
5949 info->mso_stream_count = 4; /* 4 links */
5953 if (!info->mso_stream_count) {
5954 info->mso_pixel_overlap = 0;
5958 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5959 if (info->mso_pixel_overlap > 8) {
5960 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5961 info->mso_pixel_overlap);
5962 info->mso_pixel_overlap = 8;
5965 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5966 info->mso_stream_count, info->mso_pixel_overlap);
5969 static void drm_update_mso(struct drm_connector *connector,
5970 const struct drm_edid *drm_edid)
5972 const struct displayid_block *block;
5973 struct displayid_iter iter;
5975 displayid_iter_edid_begin(drm_edid, &iter);
5976 displayid_iter_for_each(block, &iter) {
5977 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5978 drm_parse_vesa_mso_data(connector, block);
5980 displayid_iter_end(&iter);
5983 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5984 * all of the values which would have been set from EDID
5986 static void drm_reset_display_info(struct drm_connector *connector)
5988 struct drm_display_info *info = &connector->display_info;
5991 info->height_mm = 0;
5994 info->color_formats = 0;
5996 info->max_tmds_clock = 0;
5997 info->dvi_dual = false;
5998 info->is_hdmi = false;
5999 info->has_hdmi_infoframe = false;
6000 info->rgb_quant_range_selectable = false;
6001 memset(&info->hdmi, 0, sizeof(info->hdmi));
6003 info->edid_hdmi_rgb444_dc_modes = 0;
6004 info->edid_hdmi_ycbcr444_dc_modes = 0;
6006 info->non_desktop = 0;
6007 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6009 info->mso_stream_count = 0;
6010 info->mso_pixel_overlap = 0;
6013 static u32 update_display_info(struct drm_connector *connector,
6014 const struct drm_edid *drm_edid)
6016 struct drm_display_info *info = &connector->display_info;
6017 const struct edid *edid = drm_edid->edid;
6019 u32 quirks = edid_get_quirks(drm_edid);
6021 drm_reset_display_info(connector);
6023 info->width_mm = edid->width_cm * 10;
6024 info->height_mm = edid->height_cm * 10;
6026 drm_get_monitor_range(connector, drm_edid);
6028 if (edid->revision < 3)
6031 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6034 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6035 drm_parse_cea_ext(connector, drm_edid);
6038 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6040 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6041 * tells us to assume 8 bpc color depth if the EDID doesn't have
6042 * extensions which tell otherwise.
6044 if (info->bpc == 0 && edid->revision == 3 &&
6045 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6047 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
6048 connector->name, info->bpc);
6051 /* Only defined for 1.4 with digital displays */
6052 if (edid->revision < 4)
6055 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6056 case DRM_EDID_DIGITAL_DEPTH_6:
6059 case DRM_EDID_DIGITAL_DEPTH_8:
6062 case DRM_EDID_DIGITAL_DEPTH_10:
6065 case DRM_EDID_DIGITAL_DEPTH_12:
6068 case DRM_EDID_DIGITAL_DEPTH_14:
6071 case DRM_EDID_DIGITAL_DEPTH_16:
6074 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6080 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6081 connector->name, info->bpc);
6083 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6084 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6085 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6086 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6088 drm_update_mso(connector, drm_edid);
6091 if (quirks & EDID_QUIRK_NON_DESKTOP) {
6092 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
6093 info->non_desktop ? " (redundant quirk)" : "");
6094 info->non_desktop = true;
6100 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6101 struct displayid_detailed_timings_1 *timings,
6104 struct drm_display_mode *mode;
6105 unsigned pixel_clock = (timings->pixel_clock[0] |
6106 (timings->pixel_clock[1] << 8) |
6107 (timings->pixel_clock[2] << 16)) + 1;
6108 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6109 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6110 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6111 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6112 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6113 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6114 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6115 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6116 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6117 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6119 mode = drm_mode_create(dev);
6123 /* resolution is kHz for type VII, and 10 kHz for type I */
6124 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6125 mode->hdisplay = hactive;
6126 mode->hsync_start = mode->hdisplay + hsync;
6127 mode->hsync_end = mode->hsync_start + hsync_width;
6128 mode->htotal = mode->hdisplay + hblank;
6130 mode->vdisplay = vactive;
6131 mode->vsync_start = mode->vdisplay + vsync;
6132 mode->vsync_end = mode->vsync_start + vsync_width;
6133 mode->vtotal = mode->vdisplay + vblank;
6136 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6137 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6138 mode->type = DRM_MODE_TYPE_DRIVER;
6140 if (timings->flags & 0x80)
6141 mode->type |= DRM_MODE_TYPE_PREFERRED;
6142 drm_mode_set_name(mode);
6147 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6148 const struct displayid_block *block)
6150 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6153 struct drm_display_mode *newmode;
6155 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6156 /* blocks must be multiple of 20 bytes length */
6157 if (block->num_bytes % 20)
6160 num_timings = block->num_bytes / 20;
6161 for (i = 0; i < num_timings; i++) {
6162 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6164 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6168 drm_mode_probed_add(connector, newmode);
6174 static int add_displayid_detailed_modes(struct drm_connector *connector,
6175 const struct drm_edid *drm_edid)
6177 const struct displayid_block *block;
6178 struct displayid_iter iter;
6181 displayid_iter_edid_begin(drm_edid, &iter);
6182 displayid_iter_for_each(block, &iter) {
6183 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6184 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6185 num_modes += add_displayid_detailed_1_modes(connector, block);
6187 displayid_iter_end(&iter);
6192 static int _drm_edid_connector_update(struct drm_connector *connector,
6193 const struct drm_edid *drm_edid)
6199 drm_reset_display_info(connector);
6200 clear_eld(connector);
6205 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6206 * To avoid multiple parsing of same block, lets parse that map
6207 * from sink info, before parsing CEA modes.
6209 quirks = update_display_info(connector, drm_edid);
6211 /* Depends on info->cea_rev set by update_display_info() above */
6212 drm_edid_to_eld(connector, drm_edid);
6215 * EDID spec says modes should be preferred in this order:
6216 * - preferred detailed mode
6217 * - other detailed modes from base block
6218 * - detailed modes from extension blocks
6219 * - CVT 3-byte code modes
6220 * - standard timing codes
6221 * - established timing codes
6222 * - modes inferred from GTF or CVT range information
6224 * We get this pretty much right.
6226 * XXX order for additional mode types in extension blocks?
6228 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6229 num_modes += add_cvt_modes(connector, drm_edid);
6230 num_modes += add_standard_modes(connector, drm_edid);
6231 num_modes += add_established_modes(connector, drm_edid);
6232 num_modes += add_cea_modes(connector, drm_edid);
6233 num_modes += add_alternate_cea_modes(connector, drm_edid);
6234 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6235 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
6236 num_modes += add_inferred_modes(connector, drm_edid);
6238 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6239 edid_fixup_preferred(connector, quirks);
6241 if (quirks & EDID_QUIRK_FORCE_6BPC)
6242 connector->display_info.bpc = 6;
6244 if (quirks & EDID_QUIRK_FORCE_8BPC)
6245 connector->display_info.bpc = 8;
6247 if (quirks & EDID_QUIRK_FORCE_10BPC)
6248 connector->display_info.bpc = 10;
6250 if (quirks & EDID_QUIRK_FORCE_12BPC)
6251 connector->display_info.bpc = 12;
6256 static void _drm_update_tile_info(struct drm_connector *connector,
6257 const struct drm_edid *drm_edid);
6259 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6260 const struct drm_edid *drm_edid)
6262 struct drm_device *dev = connector->dev;
6265 if (connector->edid_blob_ptr) {
6266 const struct edid *old_edid = connector->edid_blob_ptr->data;
6269 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6270 connector->epoch_counter++;
6271 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6272 connector->base.id, connector->name,
6273 connector->epoch_counter);
6278 ret = drm_property_replace_global_blob(dev,
6279 &connector->edid_blob_ptr,
6280 drm_edid ? drm_edid->size : 0,
6281 drm_edid ? drm_edid->edid : NULL,
6283 dev->mode_config.edid_property);
6285 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6286 connector->base.id, connector->name, ret);
6290 ret = drm_object_property_set_value(&connector->base,
6291 dev->mode_config.non_desktop_property,
6292 connector->display_info.non_desktop);
6294 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6295 connector->base.id, connector->name, ret);
6299 ret = drm_connector_set_tile_property(connector);
6301 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6302 connector->base.id, connector->name, ret);
6311 * drm_edid_connector_update - Update connector information from EDID
6312 * @connector: Connector
6315 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6316 * properties, etc. from the passed in EDID.
6318 * If EDID is NULL, reset the information.
6320 * Return: The number of modes added or 0 if we couldn't find any.
6322 int drm_edid_connector_update(struct drm_connector *connector,
6323 const struct drm_edid *drm_edid)
6328 * FIXME: Reconcile the differences in override_edid handling between
6329 * this and drm_connector_update_edid_property().
6331 * If override_edid is set, and the EDID passed in here originates from
6332 * drm_edid_read() and friends, it will be the override EDID, and there
6333 * are no issues. drm_connector_update_edid_property() ignoring requests
6334 * to set the EDID dates back to a time when override EDID was not
6335 * handled at the low level EDID read.
6337 * The only way the EDID passed in here can be different from the
6338 * override EDID is when a driver passes in an EDID that does *not*
6339 * originate from drm_edid_read() and friends, or passes in a stale
6340 * cached version. This, in turn, is a question of when an override EDID
6341 * set via debugfs should take effect.
6344 count = _drm_edid_connector_update(connector, drm_edid);
6346 _drm_update_tile_info(connector, drm_edid);
6348 /* Note: Ignore errors for now. */
6349 _drm_edid_connector_property_update(connector, drm_edid);
6353 EXPORT_SYMBOL(drm_edid_connector_update);
6355 static int _drm_connector_update_edid_property(struct drm_connector *connector,
6356 const struct drm_edid *drm_edid)
6358 /* ignore requests to set edid when overridden */
6359 if (connector->override_edid)
6363 * Set the display info, using edid if available, otherwise resetting
6364 * the values to defaults. This duplicates the work done in
6365 * drm_add_edid_modes, but that function is not consistently called
6366 * before this one in all drivers and the computation is cheap enough
6367 * that it seems better to duplicate it rather than attempt to ensure
6368 * some arbitrary ordering of calls.
6371 update_display_info(connector, drm_edid);
6373 drm_reset_display_info(connector);
6375 _drm_update_tile_info(connector, drm_edid);
6377 return _drm_edid_connector_property_update(connector, drm_edid);
6381 * drm_connector_update_edid_property - update the edid property of a connector
6382 * @connector: drm connector
6383 * @edid: new value of the edid property
6385 * This function creates a new blob modeset object and assigns its id to the
6386 * connector's edid property.
6387 * Since we also parse tile information from EDID's displayID block, we also
6388 * set the connector's tile property here. See drm_connector_set_tile_property()
6391 * This function is deprecated. Use drm_edid_connector_update() instead.
6394 * Zero on success, negative errno on failure.
6396 int drm_connector_update_edid_property(struct drm_connector *connector,
6397 const struct edid *edid)
6399 struct drm_edid drm_edid;
6401 return _drm_connector_update_edid_property(connector,
6402 drm_edid_legacy_init(&drm_edid, edid));
6404 EXPORT_SYMBOL(drm_connector_update_edid_property);
6407 * drm_add_edid_modes - add modes from EDID data, if available
6408 * @connector: connector we're probing
6411 * Add the specified modes to the connector's mode list. Also fills out the
6412 * &drm_display_info structure and ELD in @connector with any information which
6413 * can be derived from the edid.
6415 * This function is deprecated. Use drm_edid_connector_update() instead.
6417 * Return: The number of modes added or 0 if we couldn't find any.
6419 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6421 struct drm_edid drm_edid;
6423 if (edid && !drm_edid_is_valid(edid)) {
6424 drm_warn(connector->dev, "%s: EDID invalid.\n",
6429 return _drm_edid_connector_update(connector,
6430 drm_edid_legacy_init(&drm_edid, edid));
6432 EXPORT_SYMBOL(drm_add_edid_modes);
6435 * drm_add_modes_noedid - add modes for the connectors without EDID
6436 * @connector: connector we're probing
6437 * @hdisplay: the horizontal display limit
6438 * @vdisplay: the vertical display limit
6440 * Add the specified modes to the connector's mode list. Only when the
6441 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6443 * Return: The number of modes added or 0 if we couldn't find any.
6445 int drm_add_modes_noedid(struct drm_connector *connector,
6446 int hdisplay, int vdisplay)
6448 int i, count, num_modes = 0;
6449 struct drm_display_mode *mode;
6450 struct drm_device *dev = connector->dev;
6452 count = ARRAY_SIZE(drm_dmt_modes);
6458 for (i = 0; i < count; i++) {
6459 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6461 if (hdisplay && vdisplay) {
6463 * Only when two are valid, they will be used to check
6464 * whether the mode should be added to the mode list of
6467 if (ptr->hdisplay > hdisplay ||
6468 ptr->vdisplay > vdisplay)
6471 if (drm_mode_vrefresh(ptr) > 61)
6473 mode = drm_mode_duplicate(dev, ptr);
6475 drm_mode_probed_add(connector, mode);
6481 EXPORT_SYMBOL(drm_add_modes_noedid);
6484 * drm_set_preferred_mode - Sets the preferred mode of a connector
6485 * @connector: connector whose mode list should be processed
6486 * @hpref: horizontal resolution of preferred mode
6487 * @vpref: vertical resolution of preferred mode
6489 * Marks a mode as preferred if it matches the resolution specified by @hpref
6492 void drm_set_preferred_mode(struct drm_connector *connector,
6493 int hpref, int vpref)
6495 struct drm_display_mode *mode;
6497 list_for_each_entry(mode, &connector->probed_modes, head) {
6498 if (mode->hdisplay == hpref &&
6499 mode->vdisplay == vpref)
6500 mode->type |= DRM_MODE_TYPE_PREFERRED;
6503 EXPORT_SYMBOL(drm_set_preferred_mode);
6505 static bool is_hdmi2_sink(const struct drm_connector *connector)
6508 * FIXME: sil-sii8620 doesn't have a connector around when
6509 * we need one, so we have to be prepared for a NULL connector.
6514 return connector->display_info.hdmi.scdc.supported ||
6515 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6518 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6519 const struct drm_display_mode *mode)
6521 bool has_hdmi_infoframe = connector ?
6522 connector->display_info.has_hdmi_infoframe : false;
6524 if (!has_hdmi_infoframe)
6527 /* No HDMI VIC when signalling 3D video format */
6528 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6531 return drm_match_hdmi_mode(mode);
6534 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
6535 const struct drm_display_mode *mode)
6540 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6541 * we should send its VIC in vendor infoframes, else send the
6542 * VIC in AVI infoframes. Lets check if this mode is present in
6543 * HDMI 1.4b 4K modes
6545 if (drm_mode_hdmi_vic(connector, mode))
6548 vic = drm_match_cea_mode(mode);
6551 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6552 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6553 * have to make sure we dont break HDMI 1.4 sinks.
6555 if (!is_hdmi2_sink(connector) && vic > 64)
6562 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6563 * data from a DRM display mode
6564 * @frame: HDMI AVI infoframe
6565 * @connector: the connector
6566 * @mode: DRM display mode
6568 * Return: 0 on success or a negative error code on failure.
6571 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
6572 const struct drm_connector *connector,
6573 const struct drm_display_mode *mode)
6575 enum hdmi_picture_aspect picture_aspect;
6578 if (!frame || !mode)
6581 hdmi_avi_infoframe_init(frame);
6583 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6584 frame->pixel_repeat = 1;
6586 vic = drm_mode_cea_vic(connector, mode);
6587 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
6589 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6592 * As some drivers don't support atomic, we can't use connector state.
6593 * So just initialize the frame with default values, just the same way
6594 * as it's done with other properties here.
6596 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6600 * Populate picture aspect ratio from either
6601 * user input (if specified) or from the CEA/HDMI mode lists.
6603 picture_aspect = mode->picture_aspect_ratio;
6604 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6606 picture_aspect = drm_get_cea_aspect_ratio(vic);
6608 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6612 * The infoframe can't convey anything but none, 4:3
6613 * and 16:9, so if the user has asked for anything else
6614 * we can only satisfy it by specifying the right VIC.
6616 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
6618 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6620 } else if (hdmi_vic) {
6621 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6627 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6630 frame->video_code = vic;
6631 frame->picture_aspect = picture_aspect;
6632 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
6633 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
6637 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
6640 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6641 * quantization range information
6642 * @frame: HDMI AVI infoframe
6643 * @connector: the connector
6644 * @mode: DRM display mode
6645 * @rgb_quant_range: RGB quantization range (Q)
6648 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6649 const struct drm_connector *connector,
6650 const struct drm_display_mode *mode,
6651 enum hdmi_quantization_range rgb_quant_range)
6653 const struct drm_display_info *info = &connector->display_info;
6657 * "A Source shall not send a non-zero Q value that does not correspond
6658 * to the default RGB Quantization Range for the transmitted Picture
6659 * unless the Sink indicates support for the Q bit in a Video
6660 * Capabilities Data Block."
6662 * HDMI 2.0 recommends sending non-zero Q when it does match the
6663 * default RGB quantization range for the mode, even when QS=0.
6665 if (info->rgb_quant_range_selectable ||
6666 rgb_quant_range == drm_default_rgb_quant_range(mode))
6667 frame->quantization_range = rgb_quant_range;
6669 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
6673 * "When transmitting any RGB colorimetry, the Source should set the
6674 * YQ-field to match the RGB Quantization Range being transmitted
6675 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6676 * set YQ=1) and the Sink shall ignore the YQ-field."
6678 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6679 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6680 * good way to tell which version of CEA-861 the sink supports, so
6681 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6684 if (!is_hdmi2_sink(connector) ||
6685 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
6686 frame->ycc_quantization_range =
6687 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6689 frame->ycc_quantization_range =
6690 HDMI_YCC_QUANTIZATION_RANGE_FULL;
6692 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6694 static enum hdmi_3d_structure
6695 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6697 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6700 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6701 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6702 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6703 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6704 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6705 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6706 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6707 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6708 case DRM_MODE_FLAG_3D_L_DEPTH:
6709 return HDMI_3D_STRUCTURE_L_DEPTH;
6710 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6711 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6712 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6713 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6714 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6715 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6717 return HDMI_3D_STRUCTURE_INVALID;
6722 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6723 * data from a DRM display mode
6724 * @frame: HDMI vendor infoframe
6725 * @connector: the connector
6726 * @mode: DRM display mode
6728 * Note that there's is a need to send HDMI vendor infoframes only when using a
6729 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6730 * function will return -EINVAL, error that can be safely ignored.
6732 * Return: 0 on success or a negative error code on failure.
6735 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6736 const struct drm_connector *connector,
6737 const struct drm_display_mode *mode)
6740 * FIXME: sil-sii8620 doesn't have a connector around when
6741 * we need one, so we have to be prepared for a NULL connector.
6743 bool has_hdmi_infoframe = connector ?
6744 connector->display_info.has_hdmi_infoframe : false;
6747 if (!frame || !mode)
6750 if (!has_hdmi_infoframe)
6753 err = hdmi_vendor_infoframe_init(frame);
6758 * Even if it's not absolutely necessary to send the infoframe
6759 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6760 * know that the sink can handle it. This is based on a
6761 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6762 * have trouble realizing that they should switch from 3D to 2D
6763 * mode if the source simply stops sending the infoframe when
6764 * it wants to switch from 3D to 2D.
6766 frame->vic = drm_mode_hdmi_vic(connector, mode);
6767 frame->s3d_struct = s3d_structure_from_display_mode(mode);
6771 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6773 static void drm_parse_tiled_block(struct drm_connector *connector,
6774 const struct displayid_block *block)
6776 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6778 u8 tile_v_loc, tile_h_loc;
6779 u8 num_v_tile, num_h_tile;
6780 struct drm_tile_group *tg;
6782 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6783 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6785 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6786 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6787 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6788 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6790 connector->has_tile = true;
6791 if (tile->tile_cap & 0x80)
6792 connector->tile_is_single_monitor = true;
6794 connector->num_h_tile = num_h_tile + 1;
6795 connector->num_v_tile = num_v_tile + 1;
6796 connector->tile_h_loc = tile_h_loc;
6797 connector->tile_v_loc = tile_v_loc;
6798 connector->tile_h_size = w + 1;
6799 connector->tile_v_size = h + 1;
6801 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6802 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6803 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6804 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6805 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6807 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6809 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6813 if (connector->tile_group != tg) {
6814 /* if we haven't got a pointer,
6815 take the reference, drop ref to old tile group */
6816 if (connector->tile_group)
6817 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6818 connector->tile_group = tg;
6820 /* if same tile group, then release the ref we just took. */
6821 drm_mode_put_tile_group(connector->dev, tg);
6825 static void _drm_update_tile_info(struct drm_connector *connector,
6826 const struct drm_edid *drm_edid)
6828 const struct displayid_block *block;
6829 struct displayid_iter iter;
6831 connector->has_tile = false;
6833 displayid_iter_edid_begin(drm_edid, &iter);
6834 displayid_iter_for_each(block, &iter) {
6835 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6836 drm_parse_tiled_block(connector, block);
6838 displayid_iter_end(&iter);
6840 if (!connector->has_tile && connector->tile_group) {
6841 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6842 connector->tile_group = NULL;
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