2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
45 #include "drm_crtc_internal.h"
47 #define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
51 #define EDID_EST_TIMINGS 16
52 #define EDID_STD_TIMINGS 8
53 #define EDID_DETAILED_TIMINGS 4
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
62 /* First detailed mode wrong, use largest 60Hz mode */
63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66 /* Prefer the largest mode at 75 Hz */
67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68 /* Detail timing is in cm not mm */
69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70 /* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74 /* use +hsync +vsync for detailed mode */
75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76 /* Force reduced-blanking timings for detailed modes */
77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
79 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
81 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
83 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
85 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 /* Non desktop display (i.e. HMD) */
87 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
89 struct detailed_mode_closure {
90 struct drm_connector *connector;
102 static const struct edid_quirk {
106 } edid_quirk_list[] = {
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
190 /* HTC Vive and Vive Pro VR Headsets */
191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
199 /* Windows Mixed Reality Headsets */
200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
209 /* Sony PlayStation VR Headset */
210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
212 /* Sensics VR Headsets */
213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
215 /* OSVR HDK and HDK2 VR Headsets */
216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
220 * Autogenerated from the DMT spec.
221 * This table is copied from xfree86/modes/xf86EdidModes.c.
223 static const struct drm_display_mode drm_dmt_modes[] = {
224 /* 0x01 - 640x350@85Hz */
225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
226 736, 832, 0, 350, 382, 385, 445, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
228 /* 0x02 - 640x400@85Hz */
229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
230 736, 832, 0, 400, 401, 404, 445, 0,
231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
232 /* 0x03 - 720x400@85Hz */
233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
234 828, 936, 0, 400, 401, 404, 446, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 0x04 - 640x480@60Hz */
237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
238 752, 800, 0, 480, 490, 492, 525, 0,
239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
240 /* 0x05 - 640x480@72Hz */
241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
242 704, 832, 0, 480, 489, 492, 520, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
244 /* 0x06 - 640x480@75Hz */
245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
246 720, 840, 0, 480, 481, 484, 500, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
248 /* 0x07 - 640x480@85Hz */
249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
250 752, 832, 0, 480, 481, 484, 509, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
252 /* 0x08 - 800x600@56Hz */
253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
254 896, 1024, 0, 600, 601, 603, 625, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
256 /* 0x09 - 800x600@60Hz */
257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
258 968, 1056, 0, 600, 601, 605, 628, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 0x0a - 800x600@72Hz */
261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
262 976, 1040, 0, 600, 637, 643, 666, 0,
263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x0b - 800x600@75Hz */
265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
266 896, 1056, 0, 600, 601, 604, 625, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
268 /* 0x0c - 800x600@85Hz */
269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
270 896, 1048, 0, 600, 601, 604, 631, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
272 /* 0x0d - 800x600@120Hz RB */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
274 880, 960, 0, 600, 603, 607, 636, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 0x0e - 848x480@60Hz */
277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
278 976, 1088, 0, 480, 486, 494, 517, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x0f - 1024x768@43Hz, interlace */
281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
282 1208, 1264, 0, 768, 768, 776, 817, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
284 DRM_MODE_FLAG_INTERLACE) },
285 /* 0x10 - 1024x768@60Hz */
286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
287 1184, 1344, 0, 768, 771, 777, 806, 0,
288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
289 /* 0x11 - 1024x768@70Hz */
290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
291 1184, 1328, 0, 768, 771, 777, 806, 0,
292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 0x12 - 1024x768@75Hz */
294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
295 1136, 1312, 0, 768, 769, 772, 800, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x13 - 1024x768@85Hz */
298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
299 1168, 1376, 0, 768, 769, 772, 808, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x14 - 1024x768@120Hz RB */
302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
303 1104, 1184, 0, 768, 771, 775, 813, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
305 /* 0x15 - 1152x864@75Hz */
306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
307 1344, 1600, 0, 864, 865, 868, 900, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
309 /* 0x55 - 1280x720@60Hz */
310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
311 1430, 1650, 0, 720, 725, 730, 750, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
313 /* 0x16 - 1280x768@60Hz RB */
314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
315 1360, 1440, 0, 768, 771, 778, 790, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
317 /* 0x17 - 1280x768@60Hz */
318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
319 1472, 1664, 0, 768, 771, 778, 798, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 0x18 - 1280x768@75Hz */
322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
323 1488, 1696, 0, 768, 771, 778, 805, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x19 - 1280x768@85Hz */
326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
327 1496, 1712, 0, 768, 771, 778, 809, 0,
328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x1a - 1280x768@120Hz RB */
330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
331 1360, 1440, 0, 768, 771, 778, 813, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
333 /* 0x1b - 1280x800@60Hz RB */
334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
335 1360, 1440, 0, 800, 803, 809, 823, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x1c - 1280x800@60Hz */
338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
339 1480, 1680, 0, 800, 803, 809, 831, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x1d - 1280x800@75Hz */
342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
343 1488, 1696, 0, 800, 803, 809, 838, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x1e - 1280x800@85Hz */
346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
347 1496, 1712, 0, 800, 803, 809, 843, 0,
348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
349 /* 0x1f - 1280x800@120Hz RB */
350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
351 1360, 1440, 0, 800, 803, 809, 847, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
353 /* 0x20 - 1280x960@60Hz */
354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
355 1488, 1800, 0, 960, 961, 964, 1000, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x21 - 1280x960@85Hz */
358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
359 1504, 1728, 0, 960, 961, 964, 1011, 0,
360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x22 - 1280x960@120Hz RB */
362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
363 1360, 1440, 0, 960, 963, 967, 1017, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x23 - 1280x1024@60Hz */
366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 0x24 - 1280x1024@75Hz */
370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x25 - 1280x1024@85Hz */
374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x26 - 1280x1024@120Hz RB */
378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
381 /* 0x27 - 1360x768@60Hz */
382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
383 1536, 1792, 0, 768, 771, 777, 795, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 0x28 - 1360x768@120Hz RB */
386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
387 1440, 1520, 0, 768, 771, 776, 813, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
389 /* 0x51 - 1366x768@60Hz */
390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
391 1579, 1792, 0, 768, 771, 774, 798, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x56 - 1366x768@60Hz */
394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
395 1436, 1500, 0, 768, 769, 772, 800, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 0x29 - 1400x1050@60Hz RB */
398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
401 /* 0x2a - 1400x1050@60Hz */
402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x2b - 1400x1050@75Hz */
406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x2c - 1400x1050@85Hz */
410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 0x2d - 1400x1050@120Hz RB */
414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
417 /* 0x2e - 1440x900@60Hz RB */
418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
419 1520, 1600, 0, 900, 903, 909, 926, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x2f - 1440x900@60Hz */
422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
423 1672, 1904, 0, 900, 903, 909, 934, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x30 - 1440x900@75Hz */
426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
427 1688, 1936, 0, 900, 903, 909, 942, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x31 - 1440x900@85Hz */
430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
431 1696, 1952, 0, 900, 903, 909, 948, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x32 - 1440x900@120Hz RB */
434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
435 1520, 1600, 0, 900, 903, 909, 953, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
437 /* 0x53 - 1600x900@60Hz */
438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
439 1704, 1800, 0, 900, 901, 904, 1000, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x33 - 1600x1200@60Hz */
442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x34 - 1600x1200@65Hz */
446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x35 - 1600x1200@70Hz */
450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x36 - 1600x1200@75Hz */
454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x37 - 1600x1200@85Hz */
458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x38 - 1600x1200@120Hz RB */
462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
465 /* 0x39 - 1680x1050@60Hz RB */
466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
469 /* 0x3a - 1680x1050@60Hz */
470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x3b - 1680x1050@75Hz */
474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x3c - 1680x1050@85Hz */
478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x3d - 1680x1050@120Hz RB */
482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 0x3e - 1792x1344@60Hz */
486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x3f - 1792x1344@75Hz */
490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x40 - 1792x1344@120Hz RB */
494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
497 /* 0x41 - 1856x1392@60Hz */
498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
501 /* 0x42 - 1856x1392@75Hz */
502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x43 - 1856x1392@120Hz RB */
506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
509 /* 0x52 - 1920x1080@60Hz */
510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
513 /* 0x44 - 1920x1200@60Hz RB */
514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x45 - 1920x1200@60Hz */
518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x46 - 1920x1200@75Hz */
522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x47 - 1920x1200@85Hz */
526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
529 /* 0x48 - 1920x1200@120Hz RB */
530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
533 /* 0x49 - 1920x1440@60Hz */
534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x4a - 1920x1440@75Hz */
538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
541 /* 0x4b - 1920x1440@120Hz RB */
542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
545 /* 0x54 - 2048x1152@60Hz */
546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
549 /* 0x4c - 2560x1600@60Hz RB */
550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
553 /* 0x4d - 2560x1600@60Hz */
554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x4e - 2560x1600@75Hz */
558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x4f - 2560x1600@85Hz */
562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
565 /* 0x50 - 2560x1600@120Hz RB */
566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
569 /* 0x57 - 4096x2160@60Hz RB */
570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
573 /* 0x58 - 4096x2160@59.94Hz RB */
574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
580 * These more or less come from the DMT spec. The 720x400 modes are
581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
586 * The DMT modes have been fact-checked; the rest are mild guesses.
588 static const struct drm_display_mode edid_est_modes[] = {
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
590 968, 1056, 0, 600, 601, 605, 628, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
593 896, 1024, 0, 600, 601, 603, 625, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
596 720, 840, 0, 480, 481, 484, 500, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
599 704, 832, 0, 480, 489, 492, 520, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
602 768, 864, 0, 480, 483, 486, 525, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
605 752, 800, 0, 480, 490, 492, 525, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
608 846, 900, 0, 400, 421, 423, 449, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
611 846, 900, 0, 400, 412, 414, 449, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
617 1136, 1312, 0, 768, 769, 772, 800, 0,
618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
620 1184, 1328, 0, 768, 771, 777, 806, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
623 1184, 1344, 0, 768, 771, 777, 806, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
626 1208, 1264, 0, 768, 768, 776, 817, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
629 928, 1152, 0, 624, 625, 628, 667, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
632 896, 1056, 0, 600, 601, 604, 625, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
635 976, 1040, 0, 600, 637, 643, 666, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
638 1344, 1600, 0, 864, 865, 868, 900, 0,
639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
649 static const struct minimode est3_modes[] = {
657 { 1024, 768, 85, 0 },
658 { 1152, 864, 75, 0 },
660 { 1280, 768, 60, 1 },
661 { 1280, 768, 60, 0 },
662 { 1280, 768, 75, 0 },
663 { 1280, 768, 85, 0 },
664 { 1280, 960, 60, 0 },
665 { 1280, 960, 85, 0 },
666 { 1280, 1024, 60, 0 },
667 { 1280, 1024, 85, 0 },
669 { 1360, 768, 60, 0 },
670 { 1440, 900, 60, 1 },
671 { 1440, 900, 60, 0 },
672 { 1440, 900, 75, 0 },
673 { 1440, 900, 85, 0 },
674 { 1400, 1050, 60, 1 },
675 { 1400, 1050, 60, 0 },
676 { 1400, 1050, 75, 0 },
678 { 1400, 1050, 85, 0 },
679 { 1680, 1050, 60, 1 },
680 { 1680, 1050, 60, 0 },
681 { 1680, 1050, 75, 0 },
682 { 1680, 1050, 85, 0 },
683 { 1600, 1200, 60, 0 },
684 { 1600, 1200, 65, 0 },
685 { 1600, 1200, 70, 0 },
687 { 1600, 1200, 75, 0 },
688 { 1600, 1200, 85, 0 },
689 { 1792, 1344, 60, 0 },
690 { 1792, 1344, 75, 0 },
691 { 1856, 1392, 60, 0 },
692 { 1856, 1392, 75, 0 },
693 { 1920, 1200, 60, 1 },
694 { 1920, 1200, 60, 0 },
696 { 1920, 1200, 75, 0 },
697 { 1920, 1200, 85, 0 },
698 { 1920, 1440, 60, 0 },
699 { 1920, 1440, 75, 0 },
702 static const struct minimode extra_modes[] = {
703 { 1024, 576, 60, 0 },
704 { 1366, 768, 60, 0 },
705 { 1600, 900, 60, 0 },
706 { 1680, 945, 60, 0 },
707 { 1920, 1080, 60, 0 },
708 { 2048, 1152, 60, 0 },
709 { 2048, 1536, 60, 0 },
713 * From CEA/CTA-861 spec.
715 * Do not access directly, instead always use cea_mode_for_vic().
717 static const struct drm_display_mode edid_cea_modes_0[] = {
718 /* 0 - dummy, VICs start at 1 */
720 /* 1 - 640x480@60Hz 4:3 */
721 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
722 752, 800, 0, 480, 490, 492, 525, 0,
723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
724 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
725 /* 2 - 720x480@60Hz 4:3 */
726 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
727 798, 858, 0, 480, 489, 495, 525, 0,
728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
729 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
730 /* 3 - 720x480@60Hz 16:9 */
731 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
732 798, 858, 0, 480, 489, 495, 525, 0,
733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
735 /* 4 - 1280x720@60Hz 16:9 */
736 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
737 1430, 1650, 0, 720, 725, 730, 750, 0,
738 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
739 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
740 /* 5 - 1920x1080i@60Hz 16:9 */
741 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
742 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
744 DRM_MODE_FLAG_INTERLACE),
745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
746 /* 6 - 720(1440)x480i@60Hz 4:3 */
747 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
748 801, 858, 0, 480, 488, 494, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
750 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
751 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
752 /* 7 - 720(1440)x480i@60Hz 16:9 */
753 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
754 801, 858, 0, 480, 488, 494, 525, 0,
755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
756 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
757 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
758 /* 8 - 720(1440)x240@60Hz 4:3 */
759 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
760 801, 858, 0, 240, 244, 247, 262, 0,
761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
762 DRM_MODE_FLAG_DBLCLK),
763 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
764 /* 9 - 720(1440)x240@60Hz 16:9 */
765 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 240, 244, 247, 262, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
768 DRM_MODE_FLAG_DBLCLK),
769 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
770 /* 10 - 2880x480i@60Hz 4:3 */
771 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
772 3204, 3432, 0, 480, 488, 494, 525, 0,
773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
774 DRM_MODE_FLAG_INTERLACE),
775 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
776 /* 11 - 2880x480i@60Hz 16:9 */
777 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
778 3204, 3432, 0, 480, 488, 494, 525, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_INTERLACE),
781 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
782 /* 12 - 2880x240@60Hz 4:3 */
783 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
784 3204, 3432, 0, 240, 244, 247, 262, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
786 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
787 /* 13 - 2880x240@60Hz 16:9 */
788 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
789 3204, 3432, 0, 240, 244, 247, 262, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
791 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
792 /* 14 - 1440x480@60Hz 4:3 */
793 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
794 1596, 1716, 0, 480, 489, 495, 525, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
796 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
797 /* 15 - 1440x480@60Hz 16:9 */
798 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
799 1596, 1716, 0, 480, 489, 495, 525, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
801 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
802 /* 16 - 1920x1080@60Hz 16:9 */
803 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
804 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
806 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
807 /* 17 - 720x576@50Hz 4:3 */
808 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
809 796, 864, 0, 576, 581, 586, 625, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
811 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
812 /* 18 - 720x576@50Hz 16:9 */
813 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
814 796, 864, 0, 576, 581, 586, 625, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
817 /* 19 - 1280x720@50Hz 16:9 */
818 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
819 1760, 1980, 0, 720, 725, 730, 750, 0,
820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
821 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 20 - 1920x1080i@50Hz 16:9 */
823 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
824 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
826 DRM_MODE_FLAG_INTERLACE),
827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 21 - 720(1440)x576i@50Hz 4:3 */
829 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
830 795, 864, 0, 576, 580, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
832 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
833 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
834 /* 22 - 720(1440)x576i@50Hz 16:9 */
835 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
836 795, 864, 0, 576, 580, 586, 625, 0,
837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
838 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
839 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
840 /* 23 - 720(1440)x288@50Hz 4:3 */
841 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
842 795, 864, 0, 288, 290, 293, 312, 0,
843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
844 DRM_MODE_FLAG_DBLCLK),
845 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
846 /* 24 - 720(1440)x288@50Hz 16:9 */
847 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 288, 290, 293, 312, 0,
849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
850 DRM_MODE_FLAG_DBLCLK),
851 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 25 - 2880x576i@50Hz 4:3 */
853 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
854 3180, 3456, 0, 576, 580, 586, 625, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
856 DRM_MODE_FLAG_INTERLACE),
857 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
858 /* 26 - 2880x576i@50Hz 16:9 */
859 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
860 3180, 3456, 0, 576, 580, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_INTERLACE),
863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
864 /* 27 - 2880x288@50Hz 4:3 */
865 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
866 3180, 3456, 0, 288, 290, 293, 312, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
869 /* 28 - 2880x288@50Hz 16:9 */
870 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
871 3180, 3456, 0, 288, 290, 293, 312, 0,
872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
873 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
874 /* 29 - 1440x576@50Hz 4:3 */
875 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
876 1592, 1728, 0, 576, 581, 586, 625, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
878 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
879 /* 30 - 1440x576@50Hz 16:9 */
880 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
881 1592, 1728, 0, 576, 581, 586, 625, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
883 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
884 /* 31 - 1920x1080@50Hz 16:9 */
885 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
886 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
888 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 32 - 1920x1080@24Hz 16:9 */
890 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
891 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
893 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 33 - 1920x1080@25Hz 16:9 */
895 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
896 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
898 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
899 /* 34 - 1920x1080@30Hz 16:9 */
900 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
901 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
903 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 35 - 2880x480@60Hz 4:3 */
905 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
906 3192, 3432, 0, 480, 489, 495, 525, 0,
907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
908 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
909 /* 36 - 2880x480@60Hz 16:9 */
910 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
911 3192, 3432, 0, 480, 489, 495, 525, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
913 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
914 /* 37 - 2880x576@50Hz 4:3 */
915 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
916 3184, 3456, 0, 576, 581, 586, 625, 0,
917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
918 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
919 /* 38 - 2880x576@50Hz 16:9 */
920 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
921 3184, 3456, 0, 576, 581, 586, 625, 0,
922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
923 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
924 /* 39 - 1920x1080i@50Hz 16:9 */
925 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
926 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
928 DRM_MODE_FLAG_INTERLACE),
929 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
930 /* 40 - 1920x1080i@100Hz 16:9 */
931 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
932 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
934 DRM_MODE_FLAG_INTERLACE),
935 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
936 /* 41 - 1280x720@100Hz 16:9 */
937 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
938 1760, 1980, 0, 720, 725, 730, 750, 0,
939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
940 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
941 /* 42 - 720x576@100Hz 4:3 */
942 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
943 796, 864, 0, 576, 581, 586, 625, 0,
944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
945 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
946 /* 43 - 720x576@100Hz 16:9 */
947 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
948 796, 864, 0, 576, 581, 586, 625, 0,
949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
950 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
951 /* 44 - 720(1440)x576i@100Hz 4:3 */
952 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
953 795, 864, 0, 576, 580, 586, 625, 0,
954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
955 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
956 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
957 /* 45 - 720(1440)x576i@100Hz 16:9 */
958 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
959 795, 864, 0, 576, 580, 586, 625, 0,
960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
961 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
962 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
963 /* 46 - 1920x1080i@120Hz 16:9 */
964 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
965 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
966 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
967 DRM_MODE_FLAG_INTERLACE),
968 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
969 /* 47 - 1280x720@120Hz 16:9 */
970 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
971 1430, 1650, 0, 720, 725, 730, 750, 0,
972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
973 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
974 /* 48 - 720x480@120Hz 4:3 */
975 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
976 798, 858, 0, 480, 489, 495, 525, 0,
977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
978 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
979 /* 49 - 720x480@120Hz 16:9 */
980 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
981 798, 858, 0, 480, 489, 495, 525, 0,
982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
983 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 50 - 720(1440)x480i@120Hz 4:3 */
985 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
986 801, 858, 0, 480, 488, 494, 525, 0,
987 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
988 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
989 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
990 /* 51 - 720(1440)x480i@120Hz 16:9 */
991 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
992 801, 858, 0, 480, 488, 494, 525, 0,
993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
994 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
995 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
996 /* 52 - 720x576@200Hz 4:3 */
997 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
998 796, 864, 0, 576, 581, 586, 625, 0,
999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1000 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1001 /* 53 - 720x576@200Hz 16:9 */
1002 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1003 796, 864, 0, 576, 581, 586, 625, 0,
1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1005 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1006 /* 54 - 720(1440)x576i@200Hz 4:3 */
1007 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1008 795, 864, 0, 576, 580, 586, 625, 0,
1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1010 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1011 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1012 /* 55 - 720(1440)x576i@200Hz 16:9 */
1013 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1014 795, 864, 0, 576, 580, 586, 625, 0,
1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1016 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1017 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1018 /* 56 - 720x480@240Hz 4:3 */
1019 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1020 798, 858, 0, 480, 489, 495, 525, 0,
1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1022 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1023 /* 57 - 720x480@240Hz 16:9 */
1024 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1025 798, 858, 0, 480, 489, 495, 525, 0,
1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1027 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1028 /* 58 - 720(1440)x480i@240Hz 4:3 */
1029 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1030 801, 858, 0, 480, 488, 494, 525, 0,
1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1032 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1033 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1034 /* 59 - 720(1440)x480i@240Hz 16:9 */
1035 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1036 801, 858, 0, 480, 488, 494, 525, 0,
1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1038 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1039 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1040 /* 60 - 1280x720@24Hz 16:9 */
1041 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1042 3080, 3300, 0, 720, 725, 730, 750, 0,
1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1045 /* 61 - 1280x720@25Hz 16:9 */
1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1047 3740, 3960, 0, 720, 725, 730, 750, 0,
1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1050 /* 62 - 1280x720@30Hz 16:9 */
1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1052 3080, 3300, 0, 720, 725, 730, 750, 0,
1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1055 /* 63 - 1920x1080@120Hz 16:9 */
1056 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1057 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1060 /* 64 - 1920x1080@100Hz 16:9 */
1061 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1062 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1065 /* 65 - 1280x720@24Hz 64:27 */
1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1067 3080, 3300, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070 /* 66 - 1280x720@25Hz 64:27 */
1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1072 3740, 3960, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075 /* 67 - 1280x720@30Hz 64:27 */
1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1077 3080, 3300, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080 /* 68 - 1280x720@50Hz 64:27 */
1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1082 1760, 1980, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 69 - 1280x720@60Hz 64:27 */
1086 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1087 1430, 1650, 0, 720, 725, 730, 750, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 70 - 1280x720@100Hz 64:27 */
1091 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1092 1760, 1980, 0, 720, 725, 730, 750, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 71 - 1280x720@120Hz 64:27 */
1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1097 1430, 1650, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 72 - 1920x1080@24Hz 64:27 */
1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1102 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 73 - 1920x1080@25Hz 64:27 */
1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1107 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 74 - 1920x1080@30Hz 64:27 */
1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1112 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 75 - 1920x1080@50Hz 64:27 */
1116 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1117 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 76 - 1920x1080@60Hz 64:27 */
1121 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1122 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 77 - 1920x1080@100Hz 64:27 */
1126 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1127 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 78 - 1920x1080@120Hz 64:27 */
1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1132 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 79 - 1680x720@24Hz 64:27 */
1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1137 3080, 3300, 0, 720, 725, 730, 750, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 80 - 1680x720@25Hz 64:27 */
1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1142 2948, 3168, 0, 720, 725, 730, 750, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 81 - 1680x720@30Hz 64:27 */
1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1147 2420, 2640, 0, 720, 725, 730, 750, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 82 - 1680x720@50Hz 64:27 */
1151 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1152 1980, 2200, 0, 720, 725, 730, 750, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 83 - 1680x720@60Hz 64:27 */
1156 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1157 1980, 2200, 0, 720, 725, 730, 750, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 84 - 1680x720@100Hz 64:27 */
1161 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1162 1780, 2000, 0, 720, 725, 730, 825, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 85 - 1680x720@120Hz 64:27 */
1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1167 1780, 2000, 0, 720, 725, 730, 825, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 86 - 2560x1080@24Hz 64:27 */
1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1172 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 87 - 2560x1080@25Hz 64:27 */
1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1177 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 88 - 2560x1080@30Hz 64:27 */
1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1182 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 89 - 2560x1080@50Hz 64:27 */
1186 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1187 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1190 /* 90 - 2560x1080@60Hz 64:27 */
1191 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1192 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1195 /* 91 - 2560x1080@100Hz 64:27 */
1196 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1197 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1200 /* 92 - 2560x1080@120Hz 64:27 */
1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1202 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1205 /* 93 - 3840x2160@24Hz 16:9 */
1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1207 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1210 /* 94 - 3840x2160@25Hz 16:9 */
1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1212 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1215 /* 95 - 3840x2160@30Hz 16:9 */
1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1217 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1220 /* 96 - 3840x2160@50Hz 16:9 */
1221 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1222 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1225 /* 97 - 3840x2160@60Hz 16:9 */
1226 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1227 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1230 /* 98 - 4096x2160@24Hz 256:135 */
1231 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1232 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1235 /* 99 - 4096x2160@25Hz 256:135 */
1236 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1237 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1240 /* 100 - 4096x2160@30Hz 256:135 */
1241 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1242 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1245 /* 101 - 4096x2160@50Hz 256:135 */
1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1247 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1250 /* 102 - 4096x2160@60Hz 256:135 */
1251 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1252 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1255 /* 103 - 3840x2160@24Hz 64:27 */
1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1257 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1260 /* 104 - 3840x2160@25Hz 64:27 */
1261 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1262 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1265 /* 105 - 3840x2160@30Hz 64:27 */
1266 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1267 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1270 /* 106 - 3840x2160@50Hz 64:27 */
1271 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1272 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1275 /* 107 - 3840x2160@60Hz 64:27 */
1276 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1277 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1279 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1280 /* 108 - 1280x720@48Hz 16:9 */
1281 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1282 2280, 2500, 0, 720, 725, 730, 750, 0,
1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1284 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1285 /* 109 - 1280x720@48Hz 64:27 */
1286 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1287 2280, 2500, 0, 720, 725, 730, 750, 0,
1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1289 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1290 /* 110 - 1680x720@48Hz 64:27 */
1291 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1292 2530, 2750, 0, 720, 725, 730, 750, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1295 /* 111 - 1920x1080@48Hz 16:9 */
1296 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1297 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1299 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1300 /* 112 - 1920x1080@48Hz 64:27 */
1301 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1302 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1304 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1305 /* 113 - 2560x1080@48Hz 64:27 */
1306 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1307 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1309 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1310 /* 114 - 3840x2160@48Hz 16:9 */
1311 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1312 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1314 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1315 /* 115 - 4096x2160@48Hz 256:135 */
1316 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1317 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1319 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1320 /* 116 - 3840x2160@48Hz 64:27 */
1321 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1322 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1324 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1325 /* 117 - 3840x2160@100Hz 16:9 */
1326 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1327 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1329 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1330 /* 118 - 3840x2160@120Hz 16:9 */
1331 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1332 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1334 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1335 /* 119 - 3840x2160@100Hz 64:27 */
1336 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1337 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1339 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1340 /* 120 - 3840x2160@120Hz 64:27 */
1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1342 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1344 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1345 /* 121 - 5120x2160@24Hz 64:27 */
1346 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1347 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1349 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1350 /* 122 - 5120x2160@25Hz 64:27 */
1351 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1352 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1354 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1355 /* 123 - 5120x2160@30Hz 64:27 */
1356 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1357 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1359 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1360 /* 124 - 5120x2160@48Hz 64:27 */
1361 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1362 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1364 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1365 /* 125 - 5120x2160@50Hz 64:27 */
1366 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1367 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1369 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1370 /* 126 - 5120x2160@60Hz 64:27 */
1371 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1372 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1374 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1375 /* 127 - 5120x2160@100Hz 64:27 */
1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1377 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1379 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1383 * HDMI 1.4 4k modes. Index using the VIC.
1385 static const struct drm_display_mode edid_4k_modes[] = {
1386 /* 0 - dummy, VICs start at 1 */
1388 /* 1 - 3840x2160@30Hz */
1389 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1390 3840, 4016, 4104, 4400, 0,
1391 2160, 2168, 2178, 2250, 0,
1392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1393 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1394 /* 2 - 3840x2160@25Hz */
1395 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1396 3840, 4896, 4984, 5280, 0,
1397 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1400 /* 3 - 3840x2160@24Hz */
1401 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1402 3840, 5116, 5204, 5500, 0,
1403 2160, 2168, 2178, 2250, 0,
1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1405 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1406 /* 4 - 4096x2160@24Hz (SMPTE) */
1407 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1408 4096, 5116, 5204, 5500, 0,
1409 2160, 2168, 2178, 2250, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1414 /*** DDC fetch and block validation ***/
1416 static const u8 edid_header[] = {
1417 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1421 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1422 * @raw_edid: pointer to raw base EDID block
1424 * Sanity check the header of the base EDID block.
1426 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1428 int drm_edid_header_is_valid(const u8 *raw_edid)
1432 for (i = 0; i < sizeof(edid_header); i++)
1433 if (raw_edid[i] == edid_header[i])
1438 EXPORT_SYMBOL(drm_edid_header_is_valid);
1440 static int edid_fixup __read_mostly = 6;
1441 module_param_named(edid_fixup, edid_fixup, int, 0400);
1442 MODULE_PARM_DESC(edid_fixup,
1443 "Minimum number of valid EDID header bytes (0-8, default 6)");
1445 static void drm_get_displayid(struct drm_connector *connector,
1447 static int validate_displayid(u8 *displayid, int length, int idx);
1449 static int drm_edid_block_checksum(const u8 *raw_edid)
1453 for (i = 0; i < EDID_LENGTH; i++)
1454 csum += raw_edid[i];
1459 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1461 if (memchr_inv(in_edid, 0, length))
1468 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1469 * @raw_edid: pointer to raw EDID block
1470 * @block: type of block to validate (0 for base, extension otherwise)
1471 * @print_bad_edid: if true, dump bad EDID blocks to the console
1472 * @edid_corrupt: if true, the header or checksum is invalid
1474 * Validate a base or extension EDID block and optionally dump bad blocks to
1477 * Return: True if the block is valid, false otherwise.
1479 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1483 struct edid *edid = (struct edid *)raw_edid;
1485 if (WARN_ON(!raw_edid))
1488 if (edid_fixup > 8 || edid_fixup < 0)
1492 int score = drm_edid_header_is_valid(raw_edid);
1495 *edid_corrupt = false;
1496 } else if (score >= edid_fixup) {
1497 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1498 * The corrupt flag needs to be set here otherwise, the
1499 * fix-up code here will correct the problem, the
1500 * checksum is correct and the test fails
1503 *edid_corrupt = true;
1504 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1505 memcpy(raw_edid, edid_header, sizeof(edid_header));
1508 *edid_corrupt = true;
1513 csum = drm_edid_block_checksum(raw_edid);
1516 *edid_corrupt = true;
1518 /* allow CEA to slide through, switches mangle this */
1519 if (raw_edid[0] == CEA_EXT) {
1520 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1521 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1524 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1530 /* per-block-type checks */
1531 switch (raw_edid[0]) {
1533 if (edid->version != 1) {
1534 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1538 if (edid->revision > 4)
1539 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1549 if (print_bad_edid) {
1550 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1551 pr_notice("EDID block is all zeroes\n");
1553 pr_notice("Raw EDID:\n");
1554 print_hex_dump(KERN_NOTICE,
1555 " \t", DUMP_PREFIX_NONE, 16, 1,
1556 raw_edid, EDID_LENGTH, false);
1561 EXPORT_SYMBOL(drm_edid_block_valid);
1564 * drm_edid_is_valid - sanity check EDID data
1567 * Sanity-check an entire EDID record (including extensions)
1569 * Return: True if the EDID data is valid, false otherwise.
1571 bool drm_edid_is_valid(struct edid *edid)
1574 u8 *raw = (u8 *)edid;
1579 for (i = 0; i <= edid->extensions; i++)
1580 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1585 EXPORT_SYMBOL(drm_edid_is_valid);
1587 #define DDC_SEGMENT_ADDR 0x30
1589 * drm_do_probe_ddc_edid() - get EDID information via I2C
1590 * @data: I2C device adapter
1591 * @buf: EDID data buffer to be filled
1592 * @block: 128 byte EDID block to start fetching from
1593 * @len: EDID data buffer length to fetch
1595 * Try to fetch EDID information by calling I2C driver functions.
1597 * Return: 0 on success or -1 on failure.
1600 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1602 struct i2c_adapter *adapter = data;
1603 unsigned char start = block * EDID_LENGTH;
1604 unsigned char segment = block >> 1;
1605 unsigned char xfers = segment ? 3 : 2;
1606 int ret, retries = 5;
1609 * The core I2C driver will automatically retry the transfer if the
1610 * adapter reports EAGAIN. However, we find that bit-banging transfers
1611 * are susceptible to errors under a heavily loaded machine and
1612 * generate spurious NAKs and timeouts. Retrying the transfer
1613 * of the individual block a few times seems to overcome this.
1616 struct i2c_msg msgs[] = {
1618 .addr = DDC_SEGMENT_ADDR,
1636 * Avoid sending the segment addr to not upset non-compliant
1639 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1641 if (ret == -ENXIO) {
1642 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1646 } while (ret != xfers && --retries);
1648 return ret == xfers ? 0 : -1;
1651 static void connector_bad_edid(struct drm_connector *connector,
1652 u8 *edid, int num_blocks)
1656 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1659 dev_warn(connector->dev->dev,
1660 "%s: EDID is invalid:\n",
1662 for (i = 0; i < num_blocks; i++) {
1663 u8 *block = edid + i * EDID_LENGTH;
1666 if (drm_edid_is_zero(block, EDID_LENGTH))
1667 sprintf(prefix, "\t[%02x] ZERO ", i);
1668 else if (!drm_edid_block_valid(block, i, false, NULL))
1669 sprintf(prefix, "\t[%02x] BAD ", i);
1671 sprintf(prefix, "\t[%02x] GOOD ", i);
1673 print_hex_dump(KERN_WARNING,
1674 prefix, DUMP_PREFIX_NONE, 16, 1,
1675 block, EDID_LENGTH, false);
1679 /* Get override or firmware EDID */
1680 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1682 struct edid *override = NULL;
1684 if (connector->override_edid)
1685 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1688 override = drm_load_edid_firmware(connector);
1690 return IS_ERR(override) ? NULL : override;
1694 * drm_add_override_edid_modes - add modes from override/firmware EDID
1695 * @connector: connector we're probing
1697 * Add modes from the override/firmware EDID, if available. Only to be used from
1698 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1699 * failed during drm_get_edid() and caused the override/firmware EDID to be
1702 * Return: The number of modes added or 0 if we couldn't find any.
1704 int drm_add_override_edid_modes(struct drm_connector *connector)
1706 struct edid *override;
1709 override = drm_get_override_edid(connector);
1711 drm_connector_update_edid_property(connector, override);
1712 num_modes = drm_add_edid_modes(connector, override);
1715 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1716 connector->base.id, connector->name, num_modes);
1721 EXPORT_SYMBOL(drm_add_override_edid_modes);
1724 * drm_do_get_edid - get EDID data using a custom EDID block read function
1725 * @connector: connector we're probing
1726 * @get_edid_block: EDID block read function
1727 * @data: private data passed to the block read function
1729 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1730 * exposes a different interface to read EDID blocks this function can be used
1731 * to get EDID data using a custom block read function.
1733 * As in the general case the DDC bus is accessible by the kernel at the I2C
1734 * level, drivers must make all reasonable efforts to expose it as an I2C
1735 * adapter and use drm_get_edid() instead of abusing this function.
1737 * The EDID may be overridden using debugfs override_edid or firmare EDID
1738 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1739 * order. Having either of them bypasses actual EDID reads.
1741 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1743 struct edid *drm_do_get_edid(struct drm_connector *connector,
1744 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1748 int i, j = 0, valid_extensions = 0;
1750 struct edid *override;
1752 override = drm_get_override_edid(connector);
1756 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1759 /* base block fetch */
1760 for (i = 0; i < 4; i++) {
1761 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1763 if (drm_edid_block_valid(edid, 0, false,
1764 &connector->edid_corrupt))
1766 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1767 connector->null_edid_counter++;
1774 /* if there's no extensions, we're done */
1775 valid_extensions = edid[0x7e];
1776 if (valid_extensions == 0)
1777 return (struct edid *)edid;
1779 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1784 for (j = 1; j <= edid[0x7e]; j++) {
1785 u8 *block = edid + j * EDID_LENGTH;
1787 for (i = 0; i < 4; i++) {
1788 if (get_edid_block(data, block, j, EDID_LENGTH))
1790 if (drm_edid_block_valid(block, j, false, NULL))
1798 if (valid_extensions != edid[0x7e]) {
1801 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1803 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1804 edid[0x7e] = valid_extensions;
1806 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1812 for (i = 0; i <= edid[0x7e]; i++) {
1813 u8 *block = edid + i * EDID_LENGTH;
1815 if (!drm_edid_block_valid(block, i, false, NULL))
1818 memcpy(base, block, EDID_LENGTH);
1819 base += EDID_LENGTH;
1826 return (struct edid *)edid;
1829 connector_bad_edid(connector, edid, 1);
1834 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1837 * drm_probe_ddc() - probe DDC presence
1838 * @adapter: I2C adapter to probe
1840 * Return: True on success, false on failure.
1843 drm_probe_ddc(struct i2c_adapter *adapter)
1847 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1849 EXPORT_SYMBOL(drm_probe_ddc);
1852 * drm_get_edid - get EDID data, if available
1853 * @connector: connector we're probing
1854 * @adapter: I2C adapter to use for DDC
1856 * Poke the given I2C channel to grab EDID data if possible. If found,
1857 * attach it to the connector.
1859 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1861 struct edid *drm_get_edid(struct drm_connector *connector,
1862 struct i2c_adapter *adapter)
1866 if (connector->force == DRM_FORCE_OFF)
1869 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1872 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1874 drm_get_displayid(connector, edid);
1877 EXPORT_SYMBOL(drm_get_edid);
1880 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1881 * @connector: connector we're probing
1882 * @adapter: I2C adapter to use for DDC
1884 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1885 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1886 * switch DDC to the GPU which is retrieving EDID.
1888 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1890 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1891 struct i2c_adapter *adapter)
1893 struct pci_dev *pdev = connector->dev->pdev;
1896 vga_switcheroo_lock_ddc(pdev);
1897 edid = drm_get_edid(connector, adapter);
1898 vga_switcheroo_unlock_ddc(pdev);
1902 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1905 * drm_edid_duplicate - duplicate an EDID and the extensions
1906 * @edid: EDID to duplicate
1908 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1910 struct edid *drm_edid_duplicate(const struct edid *edid)
1912 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1914 EXPORT_SYMBOL(drm_edid_duplicate);
1916 /*** EDID parsing ***/
1919 * edid_vendor - match a string against EDID's obfuscated vendor field
1920 * @edid: EDID to match
1921 * @vendor: vendor string
1923 * Returns true if @vendor is in @edid, false otherwise
1925 static bool edid_vendor(const struct edid *edid, const char *vendor)
1927 char edid_vendor[3];
1929 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1930 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1931 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1932 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1934 return !strncmp(edid_vendor, vendor, 3);
1938 * edid_get_quirks - return quirk flags for a given EDID
1939 * @edid: EDID to process
1941 * This tells subsequent routines what fixes they need to apply.
1943 static u32 edid_get_quirks(const struct edid *edid)
1945 const struct edid_quirk *quirk;
1948 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1949 quirk = &edid_quirk_list[i];
1951 if (edid_vendor(edid, quirk->vendor) &&
1952 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1953 return quirk->quirks;
1959 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1960 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1963 * edid_fixup_preferred - set preferred modes based on quirk list
1964 * @connector: has mode list to fix up
1965 * @quirks: quirks list
1967 * Walk the mode list for @connector, clearing the preferred status
1968 * on existing modes and setting it anew for the right mode ala @quirks.
1970 static void edid_fixup_preferred(struct drm_connector *connector,
1973 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1974 int target_refresh = 0;
1975 int cur_vrefresh, preferred_vrefresh;
1977 if (list_empty(&connector->probed_modes))
1980 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1981 target_refresh = 60;
1982 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1983 target_refresh = 75;
1985 preferred_mode = list_first_entry(&connector->probed_modes,
1986 struct drm_display_mode, head);
1988 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1989 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1991 if (cur_mode == preferred_mode)
1994 /* Largest mode is preferred */
1995 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1996 preferred_mode = cur_mode;
1998 cur_vrefresh = cur_mode->vrefresh ?
1999 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
2000 preferred_vrefresh = preferred_mode->vrefresh ?
2001 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
2002 /* At a given size, try to get closest to target refresh */
2003 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2004 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2005 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2006 preferred_mode = cur_mode;
2010 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2014 mode_is_rb(const struct drm_display_mode *mode)
2016 return (mode->htotal - mode->hdisplay == 160) &&
2017 (mode->hsync_end - mode->hdisplay == 80) &&
2018 (mode->hsync_end - mode->hsync_start == 32) &&
2019 (mode->vsync_start - mode->vdisplay == 3);
2023 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2024 * @dev: Device to duplicate against
2025 * @hsize: Mode width
2026 * @vsize: Mode height
2027 * @fresh: Mode refresh rate
2028 * @rb: Mode reduced-blanking-ness
2030 * Walk the DMT mode list looking for a match for the given parameters.
2032 * Return: A newly allocated copy of the mode, or NULL if not found.
2034 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2035 int hsize, int vsize, int fresh,
2040 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2041 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2042 if (hsize != ptr->hdisplay)
2044 if (vsize != ptr->vdisplay)
2046 if (fresh != drm_mode_vrefresh(ptr))
2048 if (rb != mode_is_rb(ptr))
2051 return drm_mode_duplicate(dev, ptr);
2056 EXPORT_SYMBOL(drm_mode_find_dmt);
2058 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2061 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2065 u8 *det_base = ext + d;
2068 for (i = 0; i < n; i++)
2069 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2073 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2075 unsigned int i, n = min((int)ext[0x02], 6);
2076 u8 *det_base = ext + 5;
2079 return; /* unknown version */
2081 for (i = 0; i < n; i++)
2082 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2086 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2089 struct edid *edid = (struct edid *)raw_edid;
2094 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2095 cb(&(edid->detailed_timings[i]), closure);
2097 for (i = 1; i <= raw_edid[0x7e]; i++) {
2098 u8 *ext = raw_edid + (i * EDID_LENGTH);
2101 cea_for_each_detailed_block(ext, cb, closure);
2104 vtb_for_each_detailed_block(ext, cb, closure);
2113 is_rb(struct detailed_timing *t, void *data)
2116 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
2118 *(bool *)data = true;
2121 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2123 drm_monitor_supports_rb(struct edid *edid)
2125 if (edid->revision >= 4) {
2127 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2131 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2135 find_gtf2(struct detailed_timing *t, void *data)
2138 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
2142 /* Secondary GTF curve kicks in above some break frequency */
2144 drm_gtf2_hbreak(struct edid *edid)
2147 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2148 return r ? (r[12] * 2) : 0;
2152 drm_gtf2_2c(struct edid *edid)
2155 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2156 return r ? r[13] : 0;
2160 drm_gtf2_m(struct edid *edid)
2163 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2164 return r ? (r[15] << 8) + r[14] : 0;
2168 drm_gtf2_k(struct edid *edid)
2171 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2172 return r ? r[16] : 0;
2176 drm_gtf2_2j(struct edid *edid)
2179 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2180 return r ? r[17] : 0;
2184 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2185 * @edid: EDID block to scan
2187 static int standard_timing_level(struct edid *edid)
2189 if (edid->revision >= 2) {
2190 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2192 if (drm_gtf2_hbreak(edid))
2194 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2201 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2202 * monitors fill with ascii space (0x20) instead.
2205 bad_std_timing(u8 a, u8 b)
2207 return (a == 0x00 && b == 0x00) ||
2208 (a == 0x01 && b == 0x01) ||
2209 (a == 0x20 && b == 0x20);
2213 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2214 * @connector: connector of for the EDID block
2215 * @edid: EDID block to scan
2216 * @t: standard timing params
2218 * Take the standard timing params (in this case width, aspect, and refresh)
2219 * and convert them into a real mode using CVT/GTF/DMT.
2221 static struct drm_display_mode *
2222 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2223 struct std_timing *t)
2225 struct drm_device *dev = connector->dev;
2226 struct drm_display_mode *m, *mode = NULL;
2229 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2230 >> EDID_TIMING_ASPECT_SHIFT;
2231 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2232 >> EDID_TIMING_VFREQ_SHIFT;
2233 int timing_level = standard_timing_level(edid);
2235 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2238 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2239 hsize = t->hsize * 8 + 248;
2240 /* vrefresh_rate = vfreq + 60 */
2241 vrefresh_rate = vfreq + 60;
2242 /* the vdisplay is calculated based on the aspect ratio */
2243 if (aspect_ratio == 0) {
2244 if (edid->revision < 3)
2247 vsize = (hsize * 10) / 16;
2248 } else if (aspect_ratio == 1)
2249 vsize = (hsize * 3) / 4;
2250 else if (aspect_ratio == 2)
2251 vsize = (hsize * 4) / 5;
2253 vsize = (hsize * 9) / 16;
2255 /* HDTV hack, part 1 */
2256 if (vrefresh_rate == 60 &&
2257 ((hsize == 1360 && vsize == 765) ||
2258 (hsize == 1368 && vsize == 769))) {
2264 * If this connector already has a mode for this size and refresh
2265 * rate (because it came from detailed or CVT info), use that
2266 * instead. This way we don't have to guess at interlace or
2269 list_for_each_entry(m, &connector->probed_modes, head)
2270 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2271 drm_mode_vrefresh(m) == vrefresh_rate)
2274 /* HDTV hack, part 2 */
2275 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2276 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2280 mode->hdisplay = 1366;
2281 mode->hsync_start = mode->hsync_start - 1;
2282 mode->hsync_end = mode->hsync_end - 1;
2286 /* check whether it can be found in default mode table */
2287 if (drm_monitor_supports_rb(edid)) {
2288 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2293 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2297 /* okay, generate it */
2298 switch (timing_level) {
2302 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2306 * This is potentially wrong if there's ever a monitor with
2307 * more than one ranges section, each claiming a different
2308 * secondary GTF curve. Please don't do that.
2310 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2313 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2314 drm_mode_destroy(dev, mode);
2315 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2316 vrefresh_rate, 0, 0,
2324 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2332 * EDID is delightfully ambiguous about how interlaced modes are to be
2333 * encoded. Our internal representation is of frame height, but some
2334 * HDTV detailed timings are encoded as field height.
2336 * The format list here is from CEA, in frame size. Technically we
2337 * should be checking refresh rate too. Whatever.
2340 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2341 struct detailed_pixel_timing *pt)
2344 static const struct {
2346 } cea_interlaced[] = {
2356 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2359 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2360 if ((mode->hdisplay == cea_interlaced[i].w) &&
2361 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2362 mode->vdisplay *= 2;
2363 mode->vsync_start *= 2;
2364 mode->vsync_end *= 2;
2370 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2374 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2375 * @dev: DRM device (needed to create new mode)
2377 * @timing: EDID detailed timing info
2378 * @quirks: quirks to apply
2380 * An EDID detailed timing block contains enough info for us to create and
2381 * return a new struct drm_display_mode.
2383 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2385 struct detailed_timing *timing,
2388 struct drm_display_mode *mode;
2389 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2390 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2391 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2392 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2393 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2394 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2395 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2396 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2397 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2399 /* ignore tiny modes */
2400 if (hactive < 64 || vactive < 64)
2403 if (pt->misc & DRM_EDID_PT_STEREO) {
2404 DRM_DEBUG_KMS("stereo mode not supported\n");
2407 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2408 DRM_DEBUG_KMS("composite sync not supported\n");
2411 /* it is incorrect if hsync/vsync width is zero */
2412 if (!hsync_pulse_width || !vsync_pulse_width) {
2413 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2414 "Wrong Hsync/Vsync pulse width\n");
2418 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2419 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2426 mode = drm_mode_create(dev);
2430 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2431 timing->pixel_clock = cpu_to_le16(1088);
2433 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2435 mode->hdisplay = hactive;
2436 mode->hsync_start = mode->hdisplay + hsync_offset;
2437 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2438 mode->htotal = mode->hdisplay + hblank;
2440 mode->vdisplay = vactive;
2441 mode->vsync_start = mode->vdisplay + vsync_offset;
2442 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2443 mode->vtotal = mode->vdisplay + vblank;
2445 /* Some EDIDs have bogus h/vtotal values */
2446 if (mode->hsync_end > mode->htotal)
2447 mode->htotal = mode->hsync_end + 1;
2448 if (mode->vsync_end > mode->vtotal)
2449 mode->vtotal = mode->vsync_end + 1;
2451 drm_mode_do_interlace_quirk(mode, pt);
2453 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2454 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2457 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2458 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2459 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2460 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2463 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2464 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2466 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2467 mode->width_mm *= 10;
2468 mode->height_mm *= 10;
2471 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2472 mode->width_mm = edid->width_cm * 10;
2473 mode->height_mm = edid->height_cm * 10;
2476 mode->type = DRM_MODE_TYPE_DRIVER;
2477 mode->vrefresh = drm_mode_vrefresh(mode);
2478 drm_mode_set_name(mode);
2484 mode_in_hsync_range(const struct drm_display_mode *mode,
2485 struct edid *edid, u8 *t)
2487 int hsync, hmin, hmax;
2490 if (edid->revision >= 4)
2491 hmin += ((t[4] & 0x04) ? 255 : 0);
2493 if (edid->revision >= 4)
2494 hmax += ((t[4] & 0x08) ? 255 : 0);
2495 hsync = drm_mode_hsync(mode);
2497 return (hsync <= hmax && hsync >= hmin);
2501 mode_in_vsync_range(const struct drm_display_mode *mode,
2502 struct edid *edid, u8 *t)
2504 int vsync, vmin, vmax;
2507 if (edid->revision >= 4)
2508 vmin += ((t[4] & 0x01) ? 255 : 0);
2510 if (edid->revision >= 4)
2511 vmax += ((t[4] & 0x02) ? 255 : 0);
2512 vsync = drm_mode_vrefresh(mode);
2514 return (vsync <= vmax && vsync >= vmin);
2518 range_pixel_clock(struct edid *edid, u8 *t)
2521 if (t[9] == 0 || t[9] == 255)
2524 /* 1.4 with CVT support gives us real precision, yay */
2525 if (edid->revision >= 4 && t[10] == 0x04)
2526 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2528 /* 1.3 is pathetic, so fuzz up a bit */
2529 return t[9] * 10000 + 5001;
2533 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2534 struct detailed_timing *timing)
2537 u8 *t = (u8 *)timing;
2539 if (!mode_in_hsync_range(mode, edid, t))
2542 if (!mode_in_vsync_range(mode, edid, t))
2545 if ((max_clock = range_pixel_clock(edid, t)))
2546 if (mode->clock > max_clock)
2549 /* 1.4 max horizontal check */
2550 if (edid->revision >= 4 && t[10] == 0x04)
2551 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2554 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2560 static bool valid_inferred_mode(const struct drm_connector *connector,
2561 const struct drm_display_mode *mode)
2563 const struct drm_display_mode *m;
2566 list_for_each_entry(m, &connector->probed_modes, head) {
2567 if (mode->hdisplay == m->hdisplay &&
2568 mode->vdisplay == m->vdisplay &&
2569 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2570 return false; /* duplicated */
2571 if (mode->hdisplay <= m->hdisplay &&
2572 mode->vdisplay <= m->vdisplay)
2579 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2580 struct detailed_timing *timing)
2583 struct drm_display_mode *newmode;
2584 struct drm_device *dev = connector->dev;
2586 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2587 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2588 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2589 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2591 drm_mode_probed_add(connector, newmode);
2600 /* fix up 1366x768 mode from 1368x768;
2601 * GFT/CVT can't express 1366 width which isn't dividable by 8
2603 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2605 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2606 mode->hdisplay = 1366;
2607 mode->hsync_start--;
2609 drm_mode_set_name(mode);
2614 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2615 struct detailed_timing *timing)
2618 struct drm_display_mode *newmode;
2619 struct drm_device *dev = connector->dev;
2621 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2622 const struct minimode *m = &extra_modes[i];
2623 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2627 drm_mode_fixup_1366x768(newmode);
2628 if (!mode_in_range(newmode, edid, timing) ||
2629 !valid_inferred_mode(connector, newmode)) {
2630 drm_mode_destroy(dev, newmode);
2634 drm_mode_probed_add(connector, newmode);
2642 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2643 struct detailed_timing *timing)
2646 struct drm_display_mode *newmode;
2647 struct drm_device *dev = connector->dev;
2648 bool rb = drm_monitor_supports_rb(edid);
2650 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2651 const struct minimode *m = &extra_modes[i];
2652 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2656 drm_mode_fixup_1366x768(newmode);
2657 if (!mode_in_range(newmode, edid, timing) ||
2658 !valid_inferred_mode(connector, newmode)) {
2659 drm_mode_destroy(dev, newmode);
2663 drm_mode_probed_add(connector, newmode);
2671 do_inferred_modes(struct detailed_timing *timing, void *c)
2673 struct detailed_mode_closure *closure = c;
2674 struct detailed_non_pixel *data = &timing->data.other_data;
2675 struct detailed_data_monitor_range *range = &data->data.range;
2677 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2680 closure->modes += drm_dmt_modes_for_range(closure->connector,
2684 if (!version_greater(closure->edid, 1, 1))
2685 return; /* GTF not defined yet */
2687 switch (range->flags) {
2688 case 0x02: /* secondary gtf, XXX could do more */
2689 case 0x00: /* default gtf */
2690 closure->modes += drm_gtf_modes_for_range(closure->connector,
2694 case 0x04: /* cvt, only in 1.4+ */
2695 if (!version_greater(closure->edid, 1, 3))
2698 closure->modes += drm_cvt_modes_for_range(closure->connector,
2702 case 0x01: /* just the ranges, no formula */
2709 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2711 struct detailed_mode_closure closure = {
2712 .connector = connector,
2716 if (version_greater(edid, 1, 0))
2717 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2720 return closure.modes;
2724 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2726 int i, j, m, modes = 0;
2727 struct drm_display_mode *mode;
2728 u8 *est = ((u8 *)timing) + 6;
2730 for (i = 0; i < 6; i++) {
2731 for (j = 7; j >= 0; j--) {
2732 m = (i * 8) + (7 - j);
2733 if (m >= ARRAY_SIZE(est3_modes))
2735 if (est[i] & (1 << j)) {
2736 mode = drm_mode_find_dmt(connector->dev,
2742 drm_mode_probed_add(connector, mode);
2753 do_established_modes(struct detailed_timing *timing, void *c)
2755 struct detailed_mode_closure *closure = c;
2756 struct detailed_non_pixel *data = &timing->data.other_data;
2758 if (data->type == EDID_DETAIL_EST_TIMINGS)
2759 closure->modes += drm_est3_modes(closure->connector, timing);
2763 * add_established_modes - get est. modes from EDID and add them
2764 * @connector: connector to add mode(s) to
2765 * @edid: EDID block to scan
2767 * Each EDID block contains a bitmap of the supported "established modes" list
2768 * (defined above). Tease them out and add them to the global modes list.
2771 add_established_modes(struct drm_connector *connector, struct edid *edid)
2773 struct drm_device *dev = connector->dev;
2774 unsigned long est_bits = edid->established_timings.t1 |
2775 (edid->established_timings.t2 << 8) |
2776 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2778 struct detailed_mode_closure closure = {
2779 .connector = connector,
2783 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2784 if (est_bits & (1<<i)) {
2785 struct drm_display_mode *newmode;
2786 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2788 drm_mode_probed_add(connector, newmode);
2794 if (version_greater(edid, 1, 0))
2795 drm_for_each_detailed_block((u8 *)edid,
2796 do_established_modes, &closure);
2798 return modes + closure.modes;
2802 do_standard_modes(struct detailed_timing *timing, void *c)
2804 struct detailed_mode_closure *closure = c;
2805 struct detailed_non_pixel *data = &timing->data.other_data;
2806 struct drm_connector *connector = closure->connector;
2807 struct edid *edid = closure->edid;
2809 if (data->type == EDID_DETAIL_STD_MODES) {
2811 for (i = 0; i < 6; i++) {
2812 struct std_timing *std;
2813 struct drm_display_mode *newmode;
2815 std = &data->data.timings[i];
2816 newmode = drm_mode_std(connector, edid, std);
2818 drm_mode_probed_add(connector, newmode);
2826 * add_standard_modes - get std. modes from EDID and add them
2827 * @connector: connector to add mode(s) to
2828 * @edid: EDID block to scan
2830 * Standard modes can be calculated using the appropriate standard (DMT,
2831 * GTF or CVT. Grab them from @edid and add them to the list.
2834 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2837 struct detailed_mode_closure closure = {
2838 .connector = connector,
2842 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2843 struct drm_display_mode *newmode;
2845 newmode = drm_mode_std(connector, edid,
2846 &edid->standard_timings[i]);
2848 drm_mode_probed_add(connector, newmode);
2853 if (version_greater(edid, 1, 0))
2854 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2857 /* XXX should also look for standard codes in VTB blocks */
2859 return modes + closure.modes;
2862 static int drm_cvt_modes(struct drm_connector *connector,
2863 struct detailed_timing *timing)
2865 int i, j, modes = 0;
2866 struct drm_display_mode *newmode;
2867 struct drm_device *dev = connector->dev;
2868 struct cvt_timing *cvt;
2869 const int rates[] = { 60, 85, 75, 60, 50 };
2870 const u8 empty[3] = { 0, 0, 0 };
2872 for (i = 0; i < 4; i++) {
2873 int uninitialized_var(width), height;
2874 cvt = &(timing->data.other_data.data.cvt[i]);
2876 if (!memcmp(cvt->code, empty, 3))
2879 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2880 switch (cvt->code[1] & 0x0c) {
2882 width = height * 4 / 3;
2885 width = height * 16 / 9;
2888 width = height * 16 / 10;
2891 width = height * 15 / 9;
2895 for (j = 1; j < 5; j++) {
2896 if (cvt->code[2] & (1 << j)) {
2897 newmode = drm_cvt_mode(dev, width, height,
2901 drm_mode_probed_add(connector, newmode);
2912 do_cvt_mode(struct detailed_timing *timing, void *c)
2914 struct detailed_mode_closure *closure = c;
2915 struct detailed_non_pixel *data = &timing->data.other_data;
2917 if (data->type == EDID_DETAIL_CVT_3BYTE)
2918 closure->modes += drm_cvt_modes(closure->connector, timing);
2922 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2924 struct detailed_mode_closure closure = {
2925 .connector = connector,
2929 if (version_greater(edid, 1, 2))
2930 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2932 /* XXX should also look for CVT codes in VTB blocks */
2934 return closure.modes;
2937 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2940 do_detailed_mode(struct detailed_timing *timing, void *c)
2942 struct detailed_mode_closure *closure = c;
2943 struct drm_display_mode *newmode;
2945 if (timing->pixel_clock) {
2946 newmode = drm_mode_detailed(closure->connector->dev,
2947 closure->edid, timing,
2952 if (closure->preferred)
2953 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2956 * Detailed modes are limited to 10kHz pixel clock resolution,
2957 * so fix up anything that looks like CEA/HDMI mode, but the clock
2958 * is just slightly off.
2960 fixup_detailed_cea_mode_clock(newmode);
2962 drm_mode_probed_add(closure->connector, newmode);
2964 closure->preferred = false;
2969 * add_detailed_modes - Add modes from detailed timings
2970 * @connector: attached connector
2971 * @edid: EDID block to scan
2972 * @quirks: quirks to apply
2975 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2978 struct detailed_mode_closure closure = {
2979 .connector = connector,
2985 if (closure.preferred && !version_greater(edid, 1, 3))
2987 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2989 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2991 return closure.modes;
2994 #define AUDIO_BLOCK 0x01
2995 #define VIDEO_BLOCK 0x02
2996 #define VENDOR_BLOCK 0x03
2997 #define SPEAKER_BLOCK 0x04
2998 #define HDR_STATIC_METADATA_BLOCK 0x6
2999 #define USE_EXTENDED_TAG 0x07
3000 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3001 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3002 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3003 #define EDID_BASIC_AUDIO (1 << 6)
3004 #define EDID_CEA_YCRCB444 (1 << 5)
3005 #define EDID_CEA_YCRCB422 (1 << 4)
3006 #define EDID_CEA_VCDB_QS (1 << 6)
3009 * Search EDID for CEA extension block.
3011 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
3013 u8 *edid_ext = NULL;
3016 /* No EDID or EDID extensions */
3017 if (edid == NULL || edid->extensions == 0)
3020 /* Find CEA extension */
3021 for (i = 0; i < edid->extensions; i++) {
3022 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3023 if (edid_ext[0] == ext_id)
3027 if (i == edid->extensions)
3034 static u8 *drm_find_displayid_extension(const struct edid *edid)
3036 return drm_find_edid_extension(edid, DISPLAYID_EXT);
3039 static u8 *drm_find_cea_extension(const struct edid *edid)
3043 int length = EDID_LENGTH;
3044 struct displayid_block *block;
3048 /* Look for a top level CEA extension block */
3049 cea = drm_find_edid_extension(edid, CEA_EXT);
3053 /* CEA blocks can also be found embedded in a DisplayID block */
3054 displayid = drm_find_displayid_extension(edid);
3058 ret = validate_displayid(displayid, length, idx);
3062 idx += sizeof(struct displayid_hdr);
3063 for_each_displayid_db(displayid, block, idx, length) {
3064 if (block->tag == DATA_BLOCK_CTA) {
3073 static const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3077 if (vic < ARRAY_SIZE(edid_cea_modes_0))
3078 return &edid_cea_modes_0[vic];
3082 static u8 cea_num_vics(void)
3084 return ARRAY_SIZE(edid_cea_modes_0);
3087 static u8 cea_next_vic(u8 vic)
3093 * Calculate the alternate clock for the CEA mode
3094 * (60Hz vs. 59.94Hz etc.)
3097 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3099 unsigned int clock = cea_mode->clock;
3101 if (cea_mode->vrefresh % 6 != 0)
3105 * edid_cea_modes contains the 59.94Hz
3106 * variant for 240 and 480 line modes,
3107 * and the 60Hz variant otherwise.
3109 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3110 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3112 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3118 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3121 * For certain VICs the spec allows the vertical
3122 * front porch to vary by one or two lines.
3124 * cea_modes[] stores the variant with the shortest
3125 * vertical front porch. We can adjust the mode to
3126 * get the other variants by simply increasing the
3127 * vertical front porch length.
3129 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3130 cea_mode_for_vic(9)->vtotal != 262 ||
3131 cea_mode_for_vic(12)->vtotal != 262 ||
3132 cea_mode_for_vic(13)->vtotal != 262 ||
3133 cea_mode_for_vic(23)->vtotal != 312 ||
3134 cea_mode_for_vic(24)->vtotal != 312 ||
3135 cea_mode_for_vic(27)->vtotal != 312 ||
3136 cea_mode_for_vic(28)->vtotal != 312);
3138 if (((vic == 8 || vic == 9 ||
3139 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3140 ((vic == 23 || vic == 24 ||
3141 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3142 mode->vsync_start++;
3152 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3153 unsigned int clock_tolerance)
3155 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3158 if (!to_match->clock)
3161 if (to_match->picture_aspect_ratio)
3162 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3164 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3165 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3166 unsigned int clock1, clock2;
3168 /* Check both 60Hz and 59.94Hz */
3169 clock1 = cea_mode.clock;
3170 clock2 = cea_mode_alternate_clock(&cea_mode);
3172 if (abs(to_match->clock - clock1) > clock_tolerance &&
3173 abs(to_match->clock - clock2) > clock_tolerance)
3177 if (drm_mode_match(to_match, &cea_mode, match_flags))
3179 } while (cea_mode_alternate_timings(vic, &cea_mode));
3186 * drm_match_cea_mode - look for a CEA mode matching given mode
3187 * @to_match: display mode
3189 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3192 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3194 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3197 if (!to_match->clock)
3200 if (to_match->picture_aspect_ratio)
3201 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3203 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3204 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3205 unsigned int clock1, clock2;
3207 /* Check both 60Hz and 59.94Hz */
3208 clock1 = cea_mode.clock;
3209 clock2 = cea_mode_alternate_clock(&cea_mode);
3211 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3212 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3216 if (drm_mode_match(to_match, &cea_mode, match_flags))
3218 } while (cea_mode_alternate_timings(vic, &cea_mode));
3223 EXPORT_SYMBOL(drm_match_cea_mode);
3225 static bool drm_valid_cea_vic(u8 vic)
3227 return cea_mode_for_vic(vic) != NULL;
3230 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3232 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3235 return mode->picture_aspect_ratio;
3237 return HDMI_PICTURE_ASPECT_NONE;
3240 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3242 return edid_4k_modes[video_code].picture_aspect_ratio;
3246 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3250 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3252 return cea_mode_alternate_clock(hdmi_mode);
3255 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3256 unsigned int clock_tolerance)
3258 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3261 if (!to_match->clock)
3264 if (to_match->picture_aspect_ratio)
3265 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3267 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3268 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3269 unsigned int clock1, clock2;
3271 /* Make sure to also match alternate clocks */
3272 clock1 = hdmi_mode->clock;
3273 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3275 if (abs(to_match->clock - clock1) > clock_tolerance &&
3276 abs(to_match->clock - clock2) > clock_tolerance)
3279 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3287 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3288 * @to_match: display mode
3290 * An HDMI mode is one defined in the HDMI vendor specific block.
3292 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3294 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3296 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3299 if (!to_match->clock)
3302 if (to_match->picture_aspect_ratio)
3303 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3305 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3306 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3307 unsigned int clock1, clock2;
3309 /* Make sure to also match alternate clocks */
3310 clock1 = hdmi_mode->clock;
3311 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3313 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3314 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3315 drm_mode_match(to_match, hdmi_mode, match_flags))
3321 static bool drm_valid_hdmi_vic(u8 vic)
3323 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3327 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3329 struct drm_device *dev = connector->dev;
3330 struct drm_display_mode *mode, *tmp;
3334 /* Don't add CEA modes if the CEA extension block is missing */
3335 if (!drm_find_cea_extension(edid))
3339 * Go through all probed modes and create a new mode
3340 * with the alternate clock for certain CEA modes.
3342 list_for_each_entry(mode, &connector->probed_modes, head) {
3343 const struct drm_display_mode *cea_mode = NULL;
3344 struct drm_display_mode *newmode;
3345 u8 vic = drm_match_cea_mode(mode);
3346 unsigned int clock1, clock2;
3348 if (drm_valid_cea_vic(vic)) {
3349 cea_mode = cea_mode_for_vic(vic);
3350 clock2 = cea_mode_alternate_clock(cea_mode);
3352 vic = drm_match_hdmi_mode(mode);
3353 if (drm_valid_hdmi_vic(vic)) {
3354 cea_mode = &edid_4k_modes[vic];
3355 clock2 = hdmi_mode_alternate_clock(cea_mode);
3362 clock1 = cea_mode->clock;
3364 if (clock1 == clock2)
3367 if (mode->clock != clock1 && mode->clock != clock2)
3370 newmode = drm_mode_duplicate(dev, cea_mode);
3374 /* Carry over the stereo flags */
3375 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3378 * The current mode could be either variant. Make
3379 * sure to pick the "other" clock for the new mode.
3381 if (mode->clock != clock1)
3382 newmode->clock = clock1;
3384 newmode->clock = clock2;
3386 list_add_tail(&newmode->head, &list);
3389 list_for_each_entry_safe(mode, tmp, &list, head) {
3390 list_del(&mode->head);
3391 drm_mode_probed_add(connector, mode);
3398 static u8 svd_to_vic(u8 svd)
3400 /* 0-6 bit vic, 7th bit native mode indicator */
3401 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3407 static struct drm_display_mode *
3408 drm_display_mode_from_vic_index(struct drm_connector *connector,
3409 const u8 *video_db, u8 video_len,
3412 struct drm_device *dev = connector->dev;
3413 struct drm_display_mode *newmode;
3416 if (video_db == NULL || video_index >= video_len)
3419 /* CEA modes are numbered 1..127 */
3420 vic = svd_to_vic(video_db[video_index]);
3421 if (!drm_valid_cea_vic(vic))
3424 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3428 newmode->vrefresh = 0;
3434 * do_y420vdb_modes - Parse YCBCR 420 only modes
3435 * @connector: connector corresponding to the HDMI sink
3436 * @svds: start of the data block of CEA YCBCR 420 VDB
3437 * @len: length of the CEA YCBCR 420 VDB
3439 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3440 * which contains modes which can be supported in YCBCR 420
3441 * output format only.
3443 static int do_y420vdb_modes(struct drm_connector *connector,
3444 const u8 *svds, u8 svds_len)
3447 struct drm_device *dev = connector->dev;
3448 struct drm_display_info *info = &connector->display_info;
3449 struct drm_hdmi_info *hdmi = &info->hdmi;
3451 for (i = 0; i < svds_len; i++) {
3452 u8 vic = svd_to_vic(svds[i]);
3453 struct drm_display_mode *newmode;
3455 if (!drm_valid_cea_vic(vic))
3458 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3461 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3462 drm_mode_probed_add(connector, newmode);
3467 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3472 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3473 * @connector: connector corresponding to the HDMI sink
3474 * @vic: CEA vic for the video mode to be added in the map
3476 * Makes an entry for a videomode in the YCBCR 420 bitmap
3479 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3481 u8 vic = svd_to_vic(svd);
3482 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3484 if (!drm_valid_cea_vic(vic))
3487 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3491 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3494 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3496 for (i = 0; i < len; i++) {
3497 struct drm_display_mode *mode;
3498 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3501 * YCBCR420 capability block contains a bitmap which
3502 * gives the index of CEA modes from CEA VDB, which
3503 * can support YCBCR 420 sampling output also (apart
3504 * from RGB/YCBCR444 etc).
3505 * For example, if the bit 0 in bitmap is set,
3506 * first mode in VDB can support YCBCR420 output too.
3507 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3509 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3510 drm_add_cmdb_modes(connector, db[i]);
3512 drm_mode_probed_add(connector, mode);
3520 struct stereo_mandatory_mode {
3521 int width, height, vrefresh;
3525 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3526 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3527 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3529 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3531 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3532 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3533 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3534 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3535 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3539 stereo_match_mandatory(const struct drm_display_mode *mode,
3540 const struct stereo_mandatory_mode *stereo_mode)
3542 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3544 return mode->hdisplay == stereo_mode->width &&
3545 mode->vdisplay == stereo_mode->height &&
3546 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3547 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3550 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3552 struct drm_device *dev = connector->dev;
3553 const struct drm_display_mode *mode;
3554 struct list_head stereo_modes;
3557 INIT_LIST_HEAD(&stereo_modes);
3559 list_for_each_entry(mode, &connector->probed_modes, head) {
3560 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3561 const struct stereo_mandatory_mode *mandatory;
3562 struct drm_display_mode *new_mode;
3564 if (!stereo_match_mandatory(mode,
3565 &stereo_mandatory_modes[i]))
3568 mandatory = &stereo_mandatory_modes[i];
3569 new_mode = drm_mode_duplicate(dev, mode);
3573 new_mode->flags |= mandatory->flags;
3574 list_add_tail(&new_mode->head, &stereo_modes);
3579 list_splice_tail(&stereo_modes, &connector->probed_modes);
3584 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3586 struct drm_device *dev = connector->dev;
3587 struct drm_display_mode *newmode;
3589 if (!drm_valid_hdmi_vic(vic)) {
3590 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3594 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3598 drm_mode_probed_add(connector, newmode);
3603 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3604 const u8 *video_db, u8 video_len, u8 video_index)
3606 struct drm_display_mode *newmode;
3609 if (structure & (1 << 0)) {
3610 newmode = drm_display_mode_from_vic_index(connector, video_db,
3614 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3615 drm_mode_probed_add(connector, newmode);
3619 if (structure & (1 << 6)) {
3620 newmode = drm_display_mode_from_vic_index(connector, video_db,
3624 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3625 drm_mode_probed_add(connector, newmode);
3629 if (structure & (1 << 8)) {
3630 newmode = drm_display_mode_from_vic_index(connector, video_db,
3634 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3635 drm_mode_probed_add(connector, newmode);
3644 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3645 * @connector: connector corresponding to the HDMI sink
3646 * @db: start of the CEA vendor specific block
3647 * @len: length of the CEA block payload, ie. one can access up to db[len]
3649 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3650 * also adds the stereo 3d modes when applicable.
3653 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3654 const u8 *video_db, u8 video_len)
3656 struct drm_display_info *info = &connector->display_info;
3657 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3658 u8 vic_len, hdmi_3d_len = 0;
3665 /* no HDMI_Video_Present */
3666 if (!(db[8] & (1 << 5)))
3669 /* Latency_Fields_Present */
3670 if (db[8] & (1 << 7))
3673 /* I_Latency_Fields_Present */
3674 if (db[8] & (1 << 6))
3677 /* the declared length is not long enough for the 2 first bytes
3678 * of additional video format capabilities */
3679 if (len < (8 + offset + 2))
3684 if (db[8 + offset] & (1 << 7)) {
3685 modes += add_hdmi_mandatory_stereo_modes(connector);
3687 /* 3D_Multi_present */
3688 multi_present = (db[8 + offset] & 0x60) >> 5;
3692 vic_len = db[8 + offset] >> 5;
3693 hdmi_3d_len = db[8 + offset] & 0x1f;
3695 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3698 vic = db[9 + offset + i];
3699 modes += add_hdmi_mode(connector, vic);
3701 offset += 1 + vic_len;
3703 if (multi_present == 1)
3705 else if (multi_present == 2)
3710 if (len < (8 + offset + hdmi_3d_len - 1))
3713 if (hdmi_3d_len < multi_len)
3716 if (multi_present == 1 || multi_present == 2) {
3717 /* 3D_Structure_ALL */
3718 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3720 /* check if 3D_MASK is present */
3721 if (multi_present == 2)
3722 mask = (db[10 + offset] << 8) | db[11 + offset];
3726 for (i = 0; i < 16; i++) {
3727 if (mask & (1 << i))
3728 modes += add_3d_struct_modes(connector,
3735 offset += multi_len;
3737 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3739 struct drm_display_mode *newmode = NULL;
3740 unsigned int newflag = 0;
3741 bool detail_present;
3743 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3745 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3748 /* 2D_VIC_order_X */
3749 vic_index = db[8 + offset + i] >> 4;
3751 /* 3D_Structure_X */
3752 switch (db[8 + offset + i] & 0x0f) {
3754 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3757 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3761 if ((db[9 + offset + i] >> 4) == 1)
3762 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3767 newmode = drm_display_mode_from_vic_index(connector,
3773 newmode->flags |= newflag;
3774 drm_mode_probed_add(connector, newmode);
3785 info->has_hdmi_infoframe = true;
3790 cea_db_payload_len(const u8 *db)
3792 return db[0] & 0x1f;
3796 cea_db_extended_tag(const u8 *db)
3802 cea_db_tag(const u8 *db)
3808 cea_revision(const u8 *cea)
3814 cea_db_offsets(const u8 *cea, int *start, int *end)
3816 /* DisplayID CTA extension blocks and top-level CEA EDID
3817 * block header definitions differ in the following bytes:
3818 * 1) Byte 2 of the header specifies length differently,
3819 * 2) Byte 3 is only present in the CEA top level block.
3821 * The different definitions for byte 2 follow.
3823 * DisplayID CTA extension block defines byte 2 as:
3824 * Number of payload bytes
3826 * CEA EDID block defines byte 2 as:
3827 * Byte number (decimal) within this block where the 18-byte
3828 * DTDs begin. If no non-DTD data is present in this extension
3829 * block, the value should be set to 04h (the byte after next).
3830 * If set to 00h, there are no DTDs present in this block and
3833 if (cea[0] == DATA_BLOCK_CTA) {
3835 *end = *start + cea[2];
3836 } else if (cea[0] == CEA_EXT) {
3837 /* Data block offset in CEA extension block */
3842 if (*end < 4 || *end > 127)
3851 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3855 if (cea_db_tag(db) != VENDOR_BLOCK)
3858 if (cea_db_payload_len(db) < 5)
3861 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3863 return hdmi_id == HDMI_IEEE_OUI;
3866 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3870 if (cea_db_tag(db) != VENDOR_BLOCK)
3873 if (cea_db_payload_len(db) < 7)
3876 oui = db[3] << 16 | db[2] << 8 | db[1];
3878 return oui == HDMI_FORUM_IEEE_OUI;
3881 static bool cea_db_is_vcdb(const u8 *db)
3883 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3886 if (cea_db_payload_len(db) != 2)
3889 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3895 static bool cea_db_is_y420cmdb(const u8 *db)
3897 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3900 if (!cea_db_payload_len(db))
3903 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3909 static bool cea_db_is_y420vdb(const u8 *db)
3911 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3914 if (!cea_db_payload_len(db))
3917 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3923 #define for_each_cea_db(cea, i, start, end) \
3924 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3926 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3929 struct drm_display_info *info = &connector->display_info;
3930 struct drm_hdmi_info *hdmi = &info->hdmi;
3931 u8 map_len = cea_db_payload_len(db) - 1;
3936 /* All CEA modes support ycbcr420 sampling also.*/
3937 hdmi->y420_cmdb_map = U64_MAX;
3938 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3943 * This map indicates which of the existing CEA block modes
3944 * from VDB can support YCBCR420 output too. So if bit=0 is
3945 * set, first mode from VDB can support YCBCR420 output too.
3946 * We will parse and keep this map, before parsing VDB itself
3947 * to avoid going through the same block again and again.
3949 * Spec is not clear about max possible size of this block.
3950 * Clamping max bitmap block size at 8 bytes. Every byte can
3951 * address 8 CEA modes, in this way this map can address
3952 * 8*8 = first 64 SVDs.
3954 if (WARN_ON_ONCE(map_len > 8))
3957 for (count = 0; count < map_len; count++)
3958 map |= (u64)db[2 + count] << (8 * count);
3961 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3963 hdmi->y420_cmdb_map = map;
3967 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3969 const u8 *cea = drm_find_cea_extension(edid);
3970 const u8 *db, *hdmi = NULL, *video = NULL;
3971 u8 dbl, hdmi_len, video_len = 0;
3974 if (cea && cea_revision(cea) >= 3) {
3977 if (cea_db_offsets(cea, &start, &end))
3980 for_each_cea_db(cea, i, start, end) {
3982 dbl = cea_db_payload_len(db);
3984 if (cea_db_tag(db) == VIDEO_BLOCK) {
3987 modes += do_cea_modes(connector, video, dbl);
3988 } else if (cea_db_is_hdmi_vsdb(db)) {
3991 } else if (cea_db_is_y420vdb(db)) {
3992 const u8 *vdb420 = &db[2];
3994 /* Add 4:2:0(only) modes present in EDID */
3995 modes += do_y420vdb_modes(connector,
4003 * We parse the HDMI VSDB after having added the cea modes as we will
4004 * be patching their flags when the sink supports stereo 3D.
4007 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4013 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4015 const struct drm_display_mode *cea_mode;
4016 int clock1, clock2, clock;
4021 * allow 5kHz clock difference either way to account for
4022 * the 10kHz clock resolution limit of detailed timings.
4024 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4025 if (drm_valid_cea_vic(vic)) {
4027 cea_mode = cea_mode_for_vic(vic);
4028 clock1 = cea_mode->clock;
4029 clock2 = cea_mode_alternate_clock(cea_mode);
4031 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4032 if (drm_valid_hdmi_vic(vic)) {
4034 cea_mode = &edid_4k_modes[vic];
4035 clock1 = cea_mode->clock;
4036 clock2 = hdmi_mode_alternate_clock(cea_mode);
4042 /* pick whichever is closest */
4043 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4048 if (mode->clock == clock)
4051 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4052 type, vic, mode->clock, clock);
4053 mode->clock = clock;
4056 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4058 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4061 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4064 if (cea_db_payload_len(db) < 3)
4070 static uint8_t eotf_supported(const u8 *edid_ext)
4072 return edid_ext[2] &
4073 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4074 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4075 BIT(HDMI_EOTF_SMPTE_ST2084) |
4076 BIT(HDMI_EOTF_BT_2100_HLG));
4079 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4081 return edid_ext[3] &
4082 BIT(HDMI_STATIC_METADATA_TYPE1);
4086 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4090 len = cea_db_payload_len(db);
4092 connector->hdr_sink_metadata.hdmi_type1.eotf =
4094 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4095 hdr_metadata_type(db);
4098 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4100 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4102 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4106 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4108 u8 len = cea_db_payload_len(db);
4110 if (len >= 6 && (db[6] & (1 << 7)))
4111 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4113 connector->latency_present[0] = db[8] >> 7;
4114 connector->latency_present[1] = (db[8] >> 6) & 1;
4117 connector->video_latency[0] = db[9];
4119 connector->audio_latency[0] = db[10];
4121 connector->video_latency[1] = db[11];
4123 connector->audio_latency[1] = db[12];
4125 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4126 "video latency %d %d, "
4127 "audio latency %d %d\n",
4128 connector->latency_present[0],
4129 connector->latency_present[1],
4130 connector->video_latency[0],
4131 connector->video_latency[1],
4132 connector->audio_latency[0],
4133 connector->audio_latency[1]);
4137 monitor_name(struct detailed_timing *t, void *data)
4139 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
4140 *(u8 **)data = t->data.other_data.data.str.str;
4143 static int get_monitor_name(struct edid *edid, char name[13])
4145 char *edid_name = NULL;
4151 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4152 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4153 if (edid_name[mnl] == 0x0a)
4156 name[mnl] = edid_name[mnl];
4163 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4164 * @edid: monitor EDID information
4165 * @name: pointer to a character array to hold the name of the monitor
4166 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4169 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4177 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4178 memcpy(name, buf, name_length);
4179 name[name_length] = '\0';
4181 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4183 static void clear_eld(struct drm_connector *connector)
4185 memset(connector->eld, 0, sizeof(connector->eld));
4187 connector->latency_present[0] = false;
4188 connector->latency_present[1] = false;
4189 connector->video_latency[0] = 0;
4190 connector->audio_latency[0] = 0;
4191 connector->video_latency[1] = 0;
4192 connector->audio_latency[1] = 0;
4196 * drm_edid_to_eld - build ELD from EDID
4197 * @connector: connector corresponding to the HDMI/DP sink
4198 * @edid: EDID to parse
4200 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4201 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4203 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4205 uint8_t *eld = connector->eld;
4208 int total_sad_count = 0;
4212 clear_eld(connector);
4217 cea = drm_find_cea_extension(edid);
4219 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4223 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4224 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4226 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4227 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4229 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4231 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4232 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4233 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4234 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4236 if (cea_revision(cea) >= 3) {
4239 if (cea_db_offsets(cea, &start, &end)) {
4244 for_each_cea_db(cea, i, start, end) {
4246 dbl = cea_db_payload_len(db);
4248 switch (cea_db_tag(db)) {
4252 /* Audio Data Block, contains SADs */
4253 sad_count = min(dbl / 3, 15 - total_sad_count);
4255 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4256 &db[1], sad_count * 3);
4257 total_sad_count += sad_count;
4260 /* Speaker Allocation Data Block */
4262 eld[DRM_ELD_SPEAKER] = db[1];
4265 /* HDMI Vendor-Specific Data Block */
4266 if (cea_db_is_hdmi_vsdb(db))
4267 drm_parse_hdmi_vsdb_audio(connector, db);
4274 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4276 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4277 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4278 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4280 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4282 eld[DRM_ELD_BASELINE_ELD_LEN] =
4283 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4285 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4286 drm_eld_size(eld), total_sad_count);
4290 * drm_edid_to_sad - extracts SADs from EDID
4291 * @edid: EDID to parse
4292 * @sads: pointer that will be set to the extracted SADs
4294 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4296 * Note: The returned pointer needs to be freed using kfree().
4298 * Return: The number of found SADs or negative number on error.
4300 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4303 int i, start, end, dbl;
4306 cea = drm_find_cea_extension(edid);
4308 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4312 if (cea_revision(cea) < 3) {
4313 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4317 if (cea_db_offsets(cea, &start, &end)) {
4318 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4322 for_each_cea_db(cea, i, start, end) {
4325 if (cea_db_tag(db) == AUDIO_BLOCK) {
4327 dbl = cea_db_payload_len(db);
4329 count = dbl / 3; /* SAD is 3B */
4330 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4333 for (j = 0; j < count; j++) {
4334 u8 *sad = &db[1 + j * 3];
4336 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4337 (*sads)[j].channels = sad[0] & 0x7;
4338 (*sads)[j].freq = sad[1] & 0x7F;
4339 (*sads)[j].byte2 = sad[2];
4347 EXPORT_SYMBOL(drm_edid_to_sad);
4350 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4351 * @edid: EDID to parse
4352 * @sadb: pointer to the speaker block
4354 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4356 * Note: The returned pointer needs to be freed using kfree().
4358 * Return: The number of found Speaker Allocation Blocks or negative number on
4361 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4364 int i, start, end, dbl;
4367 cea = drm_find_cea_extension(edid);
4369 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4373 if (cea_revision(cea) < 3) {
4374 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4378 if (cea_db_offsets(cea, &start, &end)) {
4379 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4383 for_each_cea_db(cea, i, start, end) {
4384 const u8 *db = &cea[i];
4386 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4387 dbl = cea_db_payload_len(db);
4389 /* Speaker Allocation Data Block */
4391 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4402 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4405 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4406 * @connector: connector associated with the HDMI/DP sink
4407 * @mode: the display mode
4409 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4410 * the sink doesn't support audio or video.
4412 int drm_av_sync_delay(struct drm_connector *connector,
4413 const struct drm_display_mode *mode)
4415 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4418 if (!connector->latency_present[0])
4420 if (!connector->latency_present[1])
4423 a = connector->audio_latency[i];
4424 v = connector->video_latency[i];
4427 * HDMI/DP sink doesn't support audio or video?
4429 if (a == 255 || v == 255)
4433 * Convert raw EDID values to millisecond.
4434 * Treat unknown latency as 0ms.
4437 a = min(2 * (a - 1), 500);
4439 v = min(2 * (v - 1), 500);
4441 return max(v - a, 0);
4443 EXPORT_SYMBOL(drm_av_sync_delay);
4446 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4447 * @edid: monitor EDID information
4449 * Parse the CEA extension according to CEA-861-B.
4451 * Return: True if the monitor is HDMI, false if not or unknown.
4453 bool drm_detect_hdmi_monitor(struct edid *edid)
4457 int start_offset, end_offset;
4459 edid_ext = drm_find_cea_extension(edid);
4463 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4467 * Because HDMI identifier is in Vendor Specific Block,
4468 * search it from all data blocks of CEA extension.
4470 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4471 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4477 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4480 * drm_detect_monitor_audio - check monitor audio capability
4481 * @edid: EDID block to scan
4483 * Monitor should have CEA extension block.
4484 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4485 * audio' only. If there is any audio extension block and supported
4486 * audio format, assume at least 'basic audio' support, even if 'basic
4487 * audio' is not defined in EDID.
4489 * Return: True if the monitor supports audio, false otherwise.
4491 bool drm_detect_monitor_audio(struct edid *edid)
4495 bool has_audio = false;
4496 int start_offset, end_offset;
4498 edid_ext = drm_find_cea_extension(edid);
4502 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4505 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4509 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4512 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4513 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4515 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4516 DRM_DEBUG_KMS("CEA audio format %d\n",
4517 (edid_ext[i + j] >> 3) & 0xf);
4524 EXPORT_SYMBOL(drm_detect_monitor_audio);
4528 * drm_default_rgb_quant_range - default RGB quantization range
4529 * @mode: display mode
4531 * Determine the default RGB quantization range for the mode,
4532 * as specified in CEA-861.
4534 * Return: The default RGB quantization range for the mode
4536 enum hdmi_quantization_range
4537 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4539 /* All CEA modes other than VIC 1 use limited quantization range. */
4540 return drm_match_cea_mode(mode) > 1 ?
4541 HDMI_QUANTIZATION_RANGE_LIMITED :
4542 HDMI_QUANTIZATION_RANGE_FULL;
4544 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4546 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4548 struct drm_display_info *info = &connector->display_info;
4550 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4552 if (db[2] & EDID_CEA_VCDB_QS)
4553 info->rgb_quant_range_selectable = true;
4556 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4560 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4562 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4563 hdmi->y420_dc_modes = dc_mask;
4566 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4569 struct drm_display_info *display = &connector->display_info;
4570 struct drm_hdmi_info *hdmi = &display->hdmi;
4572 display->has_hdmi_infoframe = true;
4574 if (hf_vsdb[6] & 0x80) {
4575 hdmi->scdc.supported = true;
4576 if (hf_vsdb[6] & 0x40)
4577 hdmi->scdc.read_request = true;
4581 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4582 * And as per the spec, three factors confirm this:
4583 * * Availability of a HF-VSDB block in EDID (check)
4584 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4585 * * SCDC support available (let's check)
4586 * Lets check it out.
4590 /* max clock is 5000 KHz times block value */
4591 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4592 struct drm_scdc *scdc = &hdmi->scdc;
4594 if (max_tmds_clock > 340000) {
4595 display->max_tmds_clock = max_tmds_clock;
4596 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4597 display->max_tmds_clock);
4600 if (scdc->supported) {
4601 scdc->scrambling.supported = true;
4603 /* Few sinks support scrambling for cloks < 340M */
4604 if ((hf_vsdb[6] & 0x8))
4605 scdc->scrambling.low_rates = true;
4609 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4612 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4615 struct drm_display_info *info = &connector->display_info;
4616 unsigned int dc_bpc = 0;
4618 /* HDMI supports at least 8 bpc */
4621 if (cea_db_payload_len(hdmi) < 6)
4624 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4626 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4627 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4631 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4633 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4634 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4638 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4640 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4641 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4646 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4651 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4652 connector->name, dc_bpc);
4656 * Deep color support mandates RGB444 support for all video
4657 * modes and forbids YCRCB422 support for all video modes per
4660 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4662 /* YCRCB444 is optional according to spec. */
4663 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4664 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4665 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4670 * Spec says that if any deep color mode is supported at all,
4671 * then deep color 36 bit must be supported.
4673 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4674 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4680 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4682 struct drm_display_info *info = &connector->display_info;
4683 u8 len = cea_db_payload_len(db);
4686 info->dvi_dual = db[6] & 1;
4688 info->max_tmds_clock = db[7] * 5000;
4690 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4691 "max TMDS clock %d kHz\n",
4693 info->max_tmds_clock);
4695 drm_parse_hdmi_deep_color_info(connector, db);
4698 static void drm_parse_cea_ext(struct drm_connector *connector,
4699 const struct edid *edid)
4701 struct drm_display_info *info = &connector->display_info;
4705 edid_ext = drm_find_cea_extension(edid);
4709 info->cea_rev = edid_ext[1];
4711 /* The existence of a CEA block should imply RGB support */
4712 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4713 if (edid_ext[3] & EDID_CEA_YCRCB444)
4714 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4715 if (edid_ext[3] & EDID_CEA_YCRCB422)
4716 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4718 if (cea_db_offsets(edid_ext, &start, &end))
4721 for_each_cea_db(edid_ext, i, start, end) {
4722 const u8 *db = &edid_ext[i];
4724 if (cea_db_is_hdmi_vsdb(db))
4725 drm_parse_hdmi_vsdb_video(connector, db);
4726 if (cea_db_is_hdmi_forum_vsdb(db))
4727 drm_parse_hdmi_forum_vsdb(connector, db);
4728 if (cea_db_is_y420cmdb(db))
4729 drm_parse_y420cmdb_bitmap(connector, db);
4730 if (cea_db_is_vcdb(db))
4731 drm_parse_vcdb(connector, db);
4732 if (cea_db_is_hdmi_hdr_metadata_block(db))
4733 drm_parse_hdr_metadata_block(connector, db);
4737 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4738 * all of the values which would have been set from EDID
4741 drm_reset_display_info(struct drm_connector *connector)
4743 struct drm_display_info *info = &connector->display_info;
4746 info->height_mm = 0;
4749 info->color_formats = 0;
4751 info->max_tmds_clock = 0;
4752 info->dvi_dual = false;
4753 info->has_hdmi_infoframe = false;
4754 info->rgb_quant_range_selectable = false;
4755 memset(&info->hdmi, 0, sizeof(info->hdmi));
4757 info->non_desktop = 0;
4760 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4762 struct drm_display_info *info = &connector->display_info;
4764 u32 quirks = edid_get_quirks(edid);
4766 drm_reset_display_info(connector);
4768 info->width_mm = edid->width_cm * 10;
4769 info->height_mm = edid->height_cm * 10;
4771 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4773 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4775 if (edid->revision < 3)
4778 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4781 drm_parse_cea_ext(connector, edid);
4784 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4786 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4787 * tells us to assume 8 bpc color depth if the EDID doesn't have
4788 * extensions which tell otherwise.
4790 if (info->bpc == 0 && edid->revision == 3 &&
4791 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
4793 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4794 connector->name, info->bpc);
4797 /* Only defined for 1.4 with digital displays */
4798 if (edid->revision < 4)
4801 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4802 case DRM_EDID_DIGITAL_DEPTH_6:
4805 case DRM_EDID_DIGITAL_DEPTH_8:
4808 case DRM_EDID_DIGITAL_DEPTH_10:
4811 case DRM_EDID_DIGITAL_DEPTH_12:
4814 case DRM_EDID_DIGITAL_DEPTH_14:
4817 case DRM_EDID_DIGITAL_DEPTH_16:
4820 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4826 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4827 connector->name, info->bpc);
4829 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4830 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4831 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4832 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4833 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4837 static int validate_displayid(u8 *displayid, int length, int idx)
4841 struct displayid_hdr *base;
4843 base = (struct displayid_hdr *)&displayid[idx];
4845 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4846 base->rev, base->bytes, base->prod_id, base->ext_count);
4848 if (base->bytes + 5 > length - idx)
4850 for (i = idx; i <= base->bytes + 5; i++) {
4851 csum += displayid[i];
4854 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4860 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4861 struct displayid_detailed_timings_1 *timings)
4863 struct drm_display_mode *mode;
4864 unsigned pixel_clock = (timings->pixel_clock[0] |
4865 (timings->pixel_clock[1] << 8) |
4866 (timings->pixel_clock[2] << 16));
4867 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4868 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4869 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4870 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4871 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4872 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4873 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4874 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4875 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4876 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4877 mode = drm_mode_create(dev);
4881 mode->clock = pixel_clock * 10;
4882 mode->hdisplay = hactive;
4883 mode->hsync_start = mode->hdisplay + hsync;
4884 mode->hsync_end = mode->hsync_start + hsync_width;
4885 mode->htotal = mode->hdisplay + hblank;
4887 mode->vdisplay = vactive;
4888 mode->vsync_start = mode->vdisplay + vsync;
4889 mode->vsync_end = mode->vsync_start + vsync_width;
4890 mode->vtotal = mode->vdisplay + vblank;
4893 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4894 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4895 mode->type = DRM_MODE_TYPE_DRIVER;
4897 if (timings->flags & 0x80)
4898 mode->type |= DRM_MODE_TYPE_PREFERRED;
4899 mode->vrefresh = drm_mode_vrefresh(mode);
4900 drm_mode_set_name(mode);
4905 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4906 struct displayid_block *block)
4908 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4911 struct drm_display_mode *newmode;
4913 /* blocks must be multiple of 20 bytes length */
4914 if (block->num_bytes % 20)
4917 num_timings = block->num_bytes / 20;
4918 for (i = 0; i < num_timings; i++) {
4919 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4921 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4925 drm_mode_probed_add(connector, newmode);
4931 static int add_displayid_detailed_modes(struct drm_connector *connector,
4937 int length = EDID_LENGTH;
4938 struct displayid_block *block;
4941 displayid = drm_find_displayid_extension(edid);
4945 ret = validate_displayid(displayid, length, idx);
4949 idx += sizeof(struct displayid_hdr);
4950 for_each_displayid_db(displayid, block, idx, length) {
4951 switch (block->tag) {
4952 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4953 num_modes += add_displayid_detailed_1_modes(connector, block);
4961 * drm_add_edid_modes - add modes from EDID data, if available
4962 * @connector: connector we're probing
4965 * Add the specified modes to the connector's mode list. Also fills out the
4966 * &drm_display_info structure and ELD in @connector with any information which
4967 * can be derived from the edid.
4969 * Return: The number of modes added or 0 if we couldn't find any.
4971 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4977 clear_eld(connector);
4980 if (!drm_edid_is_valid(edid)) {
4981 clear_eld(connector);
4982 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4987 drm_edid_to_eld(connector, edid);
4990 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4991 * To avoid multiple parsing of same block, lets parse that map
4992 * from sink info, before parsing CEA modes.
4994 quirks = drm_add_display_info(connector, edid);
4997 * EDID spec says modes should be preferred in this order:
4998 * - preferred detailed mode
4999 * - other detailed modes from base block
5000 * - detailed modes from extension blocks
5001 * - CVT 3-byte code modes
5002 * - standard timing codes
5003 * - established timing codes
5004 * - modes inferred from GTF or CVT range information
5006 * We get this pretty much right.
5008 * XXX order for additional mode types in extension blocks?
5010 num_modes += add_detailed_modes(connector, edid, quirks);
5011 num_modes += add_cvt_modes(connector, edid);
5012 num_modes += add_standard_modes(connector, edid);
5013 num_modes += add_established_modes(connector, edid);
5014 num_modes += add_cea_modes(connector, edid);
5015 num_modes += add_alternate_cea_modes(connector, edid);
5016 num_modes += add_displayid_detailed_modes(connector, edid);
5017 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5018 num_modes += add_inferred_modes(connector, edid);
5020 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5021 edid_fixup_preferred(connector, quirks);
5023 if (quirks & EDID_QUIRK_FORCE_6BPC)
5024 connector->display_info.bpc = 6;
5026 if (quirks & EDID_QUIRK_FORCE_8BPC)
5027 connector->display_info.bpc = 8;
5029 if (quirks & EDID_QUIRK_FORCE_10BPC)
5030 connector->display_info.bpc = 10;
5032 if (quirks & EDID_QUIRK_FORCE_12BPC)
5033 connector->display_info.bpc = 12;
5037 EXPORT_SYMBOL(drm_add_edid_modes);
5040 * drm_add_modes_noedid - add modes for the connectors without EDID
5041 * @connector: connector we're probing
5042 * @hdisplay: the horizontal display limit
5043 * @vdisplay: the vertical display limit
5045 * Add the specified modes to the connector's mode list. Only when the
5046 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5048 * Return: The number of modes added or 0 if we couldn't find any.
5050 int drm_add_modes_noedid(struct drm_connector *connector,
5051 int hdisplay, int vdisplay)
5053 int i, count, num_modes = 0;
5054 struct drm_display_mode *mode;
5055 struct drm_device *dev = connector->dev;
5057 count = ARRAY_SIZE(drm_dmt_modes);
5063 for (i = 0; i < count; i++) {
5064 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5065 if (hdisplay && vdisplay) {
5067 * Only when two are valid, they will be used to check
5068 * whether the mode should be added to the mode list of
5071 if (ptr->hdisplay > hdisplay ||
5072 ptr->vdisplay > vdisplay)
5075 if (drm_mode_vrefresh(ptr) > 61)
5077 mode = drm_mode_duplicate(dev, ptr);
5079 drm_mode_probed_add(connector, mode);
5085 EXPORT_SYMBOL(drm_add_modes_noedid);
5088 * drm_set_preferred_mode - Sets the preferred mode of a connector
5089 * @connector: connector whose mode list should be processed
5090 * @hpref: horizontal resolution of preferred mode
5091 * @vpref: vertical resolution of preferred mode
5093 * Marks a mode as preferred if it matches the resolution specified by @hpref
5096 void drm_set_preferred_mode(struct drm_connector *connector,
5097 int hpref, int vpref)
5099 struct drm_display_mode *mode;
5101 list_for_each_entry(mode, &connector->probed_modes, head) {
5102 if (mode->hdisplay == hpref &&
5103 mode->vdisplay == vpref)
5104 mode->type |= DRM_MODE_TYPE_PREFERRED;
5107 EXPORT_SYMBOL(drm_set_preferred_mode);
5109 static bool is_hdmi2_sink(struct drm_connector *connector)
5112 * FIXME: sil-sii8620 doesn't have a connector around when
5113 * we need one, so we have to be prepared for a NULL connector.
5118 return connector->display_info.hdmi.scdc.supported ||
5119 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5122 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5124 return sink_eotf & BIT(output_eotf);
5128 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5129 * HDR metadata from userspace
5130 * @frame: HDMI DRM infoframe
5131 * @conn_state: Connector state containing HDR metadata
5133 * Return: 0 on success or a negative error code on failure.
5136 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5137 const struct drm_connector_state *conn_state)
5139 struct drm_connector *connector;
5140 struct hdr_output_metadata *hdr_metadata;
5143 if (!frame || !conn_state)
5146 connector = conn_state->connector;
5148 if (!conn_state->hdr_output_metadata)
5151 hdr_metadata = conn_state->hdr_output_metadata->data;
5153 if (!hdr_metadata || !connector)
5156 /* Sink EOTF is Bit map while infoframe is absolute values */
5157 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5158 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5159 DRM_DEBUG_KMS("EOTF Not Supported\n");
5163 err = hdmi_drm_infoframe_init(frame);
5167 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5168 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5170 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5171 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5172 BUILD_BUG_ON(sizeof(frame->white_point) !=
5173 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5175 memcpy(&frame->display_primaries,
5176 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5177 sizeof(frame->display_primaries));
5179 memcpy(&frame->white_point,
5180 &hdr_metadata->hdmi_metadata_type1.white_point,
5181 sizeof(frame->white_point));
5183 frame->max_display_mastering_luminance =
5184 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5185 frame->min_display_mastering_luminance =
5186 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5187 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5188 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5192 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5194 static u8 drm_mode_hdmi_vic(struct drm_connector *connector,
5195 const struct drm_display_mode *mode)
5197 bool has_hdmi_infoframe = connector ?
5198 connector->display_info.has_hdmi_infoframe : false;
5200 if (!has_hdmi_infoframe)
5203 /* No HDMI VIC when signalling 3D video format */
5204 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5207 return drm_match_hdmi_mode(mode);
5210 static u8 drm_mode_cea_vic(struct drm_connector *connector,
5211 const struct drm_display_mode *mode)
5216 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5217 * we should send its VIC in vendor infoframes, else send the
5218 * VIC in AVI infoframes. Lets check if this mode is present in
5219 * HDMI 1.4b 4K modes
5221 if (drm_mode_hdmi_vic(connector, mode))
5224 vic = drm_match_cea_mode(mode);
5227 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5228 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5229 * have to make sure we dont break HDMI 1.4 sinks.
5231 if (!is_hdmi2_sink(connector) && vic > 64)
5238 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5239 * data from a DRM display mode
5240 * @frame: HDMI AVI infoframe
5241 * @connector: the connector
5242 * @mode: DRM display mode
5244 * Return: 0 on success or a negative error code on failure.
5247 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5248 struct drm_connector *connector,
5249 const struct drm_display_mode *mode)
5251 enum hdmi_picture_aspect picture_aspect;
5255 if (!frame || !mode)
5258 err = hdmi_avi_infoframe_init(frame);
5262 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5263 frame->pixel_repeat = 1;
5265 vic = drm_mode_cea_vic(connector, mode);
5266 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5268 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5271 * As some drivers don't support atomic, we can't use connector state.
5272 * So just initialize the frame with default values, just the same way
5273 * as it's done with other properties here.
5275 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5279 * Populate picture aspect ratio from either
5280 * user input (if specified) or from the CEA/HDMI mode lists.
5282 picture_aspect = mode->picture_aspect_ratio;
5283 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5285 picture_aspect = drm_get_cea_aspect_ratio(vic);
5287 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5291 * The infoframe can't convey anything but none, 4:3
5292 * and 16:9, so if the user has asked for anything else
5293 * we can only satisfy it by specifying the right VIC.
5295 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5297 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5299 } else if (hdmi_vic) {
5300 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5306 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5309 frame->video_code = vic;
5310 frame->picture_aspect = picture_aspect;
5311 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5312 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5316 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5318 /* HDMI Colorspace Spec Definitions */
5319 #define FULL_COLORIMETRY_MASK 0x1FF
5320 #define NORMAL_COLORIMETRY_MASK 0x3
5321 #define EXTENDED_COLORIMETRY_MASK 0x7
5322 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5324 #define C(x) ((x) << 0)
5325 #define EC(x) ((x) << 2)
5326 #define ACE(x) ((x) << 5)
5328 #define HDMI_COLORIMETRY_NO_DATA 0x0
5329 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5330 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5331 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5332 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5333 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5334 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5335 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5336 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5337 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5338 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5339 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5340 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5342 static const u32 hdmi_colorimetry_val[] = {
5343 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5344 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5345 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5346 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5347 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5348 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5349 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5350 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5351 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5352 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5353 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5361 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5362 * colorspace information
5363 * @frame: HDMI AVI infoframe
5364 * @conn_state: connector state
5367 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5368 const struct drm_connector_state *conn_state)
5370 u32 colorimetry_val;
5371 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5373 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5374 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5376 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5378 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5380 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5381 * structure and extend it in drivers/video/hdmi
5383 frame->extended_colorimetry = (colorimetry_val >> 2) &
5384 EXTENDED_COLORIMETRY_MASK;
5386 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5389 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5390 * quantization range information
5391 * @frame: HDMI AVI infoframe
5392 * @connector: the connector
5393 * @mode: DRM display mode
5394 * @rgb_quant_range: RGB quantization range (Q)
5397 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5398 struct drm_connector *connector,
5399 const struct drm_display_mode *mode,
5400 enum hdmi_quantization_range rgb_quant_range)
5402 const struct drm_display_info *info = &connector->display_info;
5406 * "A Source shall not send a non-zero Q value that does not correspond
5407 * to the default RGB Quantization Range for the transmitted Picture
5408 * unless the Sink indicates support for the Q bit in a Video
5409 * Capabilities Data Block."
5411 * HDMI 2.0 recommends sending non-zero Q when it does match the
5412 * default RGB quantization range for the mode, even when QS=0.
5414 if (info->rgb_quant_range_selectable ||
5415 rgb_quant_range == drm_default_rgb_quant_range(mode))
5416 frame->quantization_range = rgb_quant_range;
5418 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5422 * "When transmitting any RGB colorimetry, the Source should set the
5423 * YQ-field to match the RGB Quantization Range being transmitted
5424 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5425 * set YQ=1) and the Sink shall ignore the YQ-field."
5427 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5428 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5429 * good way to tell which version of CEA-861 the sink supports, so
5430 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5433 if (!is_hdmi2_sink(connector) ||
5434 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5435 frame->ycc_quantization_range =
5436 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5438 frame->ycc_quantization_range =
5439 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5441 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5444 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5446 * @frame: HDMI AVI infoframe
5447 * @conn_state: connector state
5450 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5451 const struct drm_connector_state *conn_state)
5453 frame->right_bar = conn_state->tv.margins.right;
5454 frame->left_bar = conn_state->tv.margins.left;
5455 frame->top_bar = conn_state->tv.margins.top;
5456 frame->bottom_bar = conn_state->tv.margins.bottom;
5458 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5460 static enum hdmi_3d_structure
5461 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5463 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5466 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5467 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5468 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5469 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5470 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5471 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5472 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5473 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5474 case DRM_MODE_FLAG_3D_L_DEPTH:
5475 return HDMI_3D_STRUCTURE_L_DEPTH;
5476 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5477 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5478 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5479 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5480 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5481 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5483 return HDMI_3D_STRUCTURE_INVALID;
5488 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5489 * data from a DRM display mode
5490 * @frame: HDMI vendor infoframe
5491 * @connector: the connector
5492 * @mode: DRM display mode
5494 * Note that there's is a need to send HDMI vendor infoframes only when using a
5495 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5496 * function will return -EINVAL, error that can be safely ignored.
5498 * Return: 0 on success or a negative error code on failure.
5501 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5502 struct drm_connector *connector,
5503 const struct drm_display_mode *mode)
5506 * FIXME: sil-sii8620 doesn't have a connector around when
5507 * we need one, so we have to be prepared for a NULL connector.
5509 bool has_hdmi_infoframe = connector ?
5510 connector->display_info.has_hdmi_infoframe : false;
5513 if (!frame || !mode)
5516 if (!has_hdmi_infoframe)
5519 err = hdmi_vendor_infoframe_init(frame);
5524 * Even if it's not absolutely necessary to send the infoframe
5525 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5526 * know that the sink can handle it. This is based on a
5527 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5528 * have trouble realizing that they shuld switch from 3D to 2D
5529 * mode if the source simply stops sending the infoframe when
5530 * it wants to switch from 3D to 2D.
5532 frame->vic = drm_mode_hdmi_vic(connector, mode);
5533 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5537 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5539 static int drm_parse_tiled_block(struct drm_connector *connector,
5540 struct displayid_block *block)
5542 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5544 u8 tile_v_loc, tile_h_loc;
5545 u8 num_v_tile, num_h_tile;
5546 struct drm_tile_group *tg;
5548 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5549 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5551 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5552 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5553 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5554 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5556 connector->has_tile = true;
5557 if (tile->tile_cap & 0x80)
5558 connector->tile_is_single_monitor = true;
5560 connector->num_h_tile = num_h_tile + 1;
5561 connector->num_v_tile = num_v_tile + 1;
5562 connector->tile_h_loc = tile_h_loc;
5563 connector->tile_v_loc = tile_v_loc;
5564 connector->tile_h_size = w + 1;
5565 connector->tile_v_size = h + 1;
5567 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5568 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5569 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5570 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5571 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5573 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5575 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5580 if (connector->tile_group != tg) {
5581 /* if we haven't got a pointer,
5582 take the reference, drop ref to old tile group */
5583 if (connector->tile_group) {
5584 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5586 connector->tile_group = tg;
5588 /* if same tile group, then release the ref we just took. */
5589 drm_mode_put_tile_group(connector->dev, tg);
5593 static int drm_parse_display_id(struct drm_connector *connector,
5594 u8 *displayid, int length,
5595 bool is_edid_extension)
5597 /* if this is an EDID extension the first byte will be 0x70 */
5599 struct displayid_block *block;
5602 if (is_edid_extension)
5605 ret = validate_displayid(displayid, length, idx);
5609 idx += sizeof(struct displayid_hdr);
5610 for_each_displayid_db(displayid, block, idx, length) {
5611 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5612 block->tag, block->rev, block->num_bytes);
5614 switch (block->tag) {
5615 case DATA_BLOCK_TILED_DISPLAY:
5616 ret = drm_parse_tiled_block(connector, block);
5620 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5621 /* handled in mode gathering code. */
5623 case DATA_BLOCK_CTA:
5624 /* handled in the cea parser code. */
5627 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5634 static void drm_get_displayid(struct drm_connector *connector,
5637 void *displayid = NULL;
5639 connector->has_tile = false;
5640 displayid = drm_find_displayid_extension(edid);
5642 /* drop reference to any tile group we had */
5646 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5649 if (!connector->has_tile)
5653 if (connector->tile_group) {
5654 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5655 connector->tile_group = NULL;
projects / platform / kernel / linux-rpi.git / blob