2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
46 #include "drm_crtc_internal.h"
48 static int oui(u8 first, u8 second, u8 third)
50 return (first << 16) | (second << 8) | third;
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
90 /* Cap the DSC target bitrate to 15bpp */
91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
93 #define MICROSOFT_IEEE_OUI 0xca125c
95 struct detailed_mode_closure {
96 struct drm_connector *connector;
97 const struct drm_edid *drm_edid;
107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
114 static const struct edid_quirk {
117 } edid_quirk_list[] = {
119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
127 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
129 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
132 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
135 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
138 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
139 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
141 /* Belinea 10 15 55 */
142 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
143 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
145 /* Envision Peripherals, Inc. EN-7100e */
146 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
147 /* Envision EN2028 */
148 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
150 /* Funai Electronics PM36B */
151 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
152 EDID_QUIRK_DETAILED_IN_CM),
155 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
158 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
160 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
161 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
163 /* LG Philips LCD LP154W01-A5 */
164 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
165 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
167 /* Samsung SyncMaster 205BW. Note: irony */
168 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
169 /* Samsung SyncMaster 22[5-6]BW */
170 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
171 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
173 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
174 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
176 /* ViewSonic VA2026w */
177 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
179 /* Medion MD 30217 PG */
180 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
183 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
185 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
186 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
188 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
189 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
191 /* Valve Index Headset */
192 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
210 /* HTC Vive and Vive Pro VR Headsets */
211 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
214 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
215 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
220 /* Windows Mixed Reality Headsets */
221 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
222 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
223 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
224 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
225 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
226 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
228 /* Sony PlayStation VR Headset */
229 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
231 /* Sensics VR Headsets */
232 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
234 /* OSVR HDK and HDK2 VR Headsets */
235 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
236 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
240 * Autogenerated from the DMT spec.
241 * This table is copied from xfree86/modes/xf86EdidModes.c.
243 static const struct drm_display_mode drm_dmt_modes[] = {
244 /* 0x01 - 640x350@85Hz */
245 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
246 736, 832, 0, 350, 382, 385, 445, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
248 /* 0x02 - 640x400@85Hz */
249 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
250 736, 832, 0, 400, 401, 404, 445, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
252 /* 0x03 - 720x400@85Hz */
253 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
254 828, 936, 0, 400, 401, 404, 446, 0,
255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
256 /* 0x04 - 640x480@60Hz */
257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
258 752, 800, 0, 480, 490, 492, 525, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
260 /* 0x05 - 640x480@72Hz */
261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
262 704, 832, 0, 480, 489, 492, 520, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
264 /* 0x06 - 640x480@75Hz */
265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
266 720, 840, 0, 480, 481, 484, 500, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 0x07 - 640x480@85Hz */
269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
270 752, 832, 0, 480, 481, 484, 509, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 0x08 - 800x600@56Hz */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
274 896, 1024, 0, 600, 601, 603, 625, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
276 /* 0x09 - 800x600@60Hz */
277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
278 968, 1056, 0, 600, 601, 605, 628, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x0a - 800x600@72Hz */
281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
282 976, 1040, 0, 600, 637, 643, 666, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
284 /* 0x0b - 800x600@75Hz */
285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
286 896, 1056, 0, 600, 601, 604, 625, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x0c - 800x600@85Hz */
289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
290 896, 1048, 0, 600, 601, 604, 631, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 0x0d - 800x600@120Hz RB */
293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
294 880, 960, 0, 600, 603, 607, 636, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
296 /* 0x0e - 848x480@60Hz */
297 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
298 976, 1088, 0, 480, 486, 494, 517, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x0f - 1024x768@43Hz, interlace */
301 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
302 1208, 1264, 0, 768, 768, 776, 817, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
304 DRM_MODE_FLAG_INTERLACE) },
305 /* 0x10 - 1024x768@60Hz */
306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
307 1184, 1344, 0, 768, 771, 777, 806, 0,
308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
309 /* 0x11 - 1024x768@70Hz */
310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
311 1184, 1328, 0, 768, 771, 777, 806, 0,
312 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
313 /* 0x12 - 1024x768@75Hz */
314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
315 1136, 1312, 0, 768, 769, 772, 800, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 0x13 - 1024x768@85Hz */
318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
319 1168, 1376, 0, 768, 769, 772, 808, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 0x14 - 1024x768@120Hz RB */
322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
323 1104, 1184, 0, 768, 771, 775, 813, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
325 /* 0x15 - 1152x864@75Hz */
326 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
327 1344, 1600, 0, 864, 865, 868, 900, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x55 - 1280x720@60Hz */
330 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
331 1430, 1650, 0, 720, 725, 730, 750, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x16 - 1280x768@60Hz RB */
334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
335 1360, 1440, 0, 768, 771, 778, 790, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x17 - 1280x768@60Hz */
338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
339 1472, 1664, 0, 768, 771, 778, 798, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x18 - 1280x768@75Hz */
342 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
343 1488, 1696, 0, 768, 771, 778, 805, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x19 - 1280x768@85Hz */
346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
347 1496, 1712, 0, 768, 771, 778, 809, 0,
348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
349 /* 0x1a - 1280x768@120Hz RB */
350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
351 1360, 1440, 0, 768, 771, 778, 813, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
353 /* 0x1b - 1280x800@60Hz RB */
354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
355 1360, 1440, 0, 800, 803, 809, 823, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
357 /* 0x1c - 1280x800@60Hz */
358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
359 1480, 1680, 0, 800, 803, 809, 831, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x1d - 1280x800@75Hz */
362 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
363 1488, 1696, 0, 800, 803, 809, 838, 0,
364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
365 /* 0x1e - 1280x800@85Hz */
366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
367 1496, 1712, 0, 800, 803, 809, 843, 0,
368 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 0x1f - 1280x800@120Hz RB */
370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
371 1360, 1440, 0, 800, 803, 809, 847, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
373 /* 0x20 - 1280x960@60Hz */
374 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
375 1488, 1800, 0, 960, 961, 964, 1000, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x21 - 1280x960@85Hz */
378 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
379 1504, 1728, 0, 960, 961, 964, 1011, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x22 - 1280x960@120Hz RB */
382 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
383 1360, 1440, 0, 960, 963, 967, 1017, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
385 /* 0x23 - 1280x1024@60Hz */
386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
387 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x24 - 1280x1024@75Hz */
390 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
391 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x25 - 1280x1024@85Hz */
394 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
395 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 0x26 - 1280x1024@120Hz RB */
398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
399 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
401 /* 0x27 - 1360x768@60Hz */
402 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
403 1536, 1792, 0, 768, 771, 777, 795, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x28 - 1360x768@120Hz RB */
406 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
407 1440, 1520, 0, 768, 771, 776, 813, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
409 /* 0x51 - 1366x768@60Hz */
410 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
411 1579, 1792, 0, 768, 771, 774, 798, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 0x56 - 1366x768@60Hz */
414 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
415 1436, 1500, 0, 768, 769, 772, 800, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x29 - 1400x1050@60Hz RB */
418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
419 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x2a - 1400x1050@60Hz */
422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
423 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x2b - 1400x1050@75Hz */
426 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
427 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x2c - 1400x1050@85Hz */
430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
431 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x2d - 1400x1050@120Hz RB */
434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
435 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
437 /* 0x2e - 1440x900@60Hz RB */
438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
439 1520, 1600, 0, 900, 903, 909, 926, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
441 /* 0x2f - 1440x900@60Hz */
442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
443 1672, 1904, 0, 900, 903, 909, 934, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x30 - 1440x900@75Hz */
446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
447 1688, 1936, 0, 900, 903, 909, 942, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x31 - 1440x900@85Hz */
450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
451 1696, 1952, 0, 900, 903, 909, 948, 0,
452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x32 - 1440x900@120Hz RB */
454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
455 1520, 1600, 0, 900, 903, 909, 953, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
457 /* 0x53 - 1600x900@60Hz */
458 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
459 1704, 1800, 0, 900, 901, 904, 1000, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x33 - 1600x1200@60Hz */
462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x34 - 1600x1200@65Hz */
466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 0x35 - 1600x1200@70Hz */
470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
471 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x36 - 1600x1200@75Hz */
474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x37 - 1600x1200@85Hz */
478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x38 - 1600x1200@120Hz RB */
482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
483 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 0x39 - 1680x1050@60Hz RB */
486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
487 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
489 /* 0x3a - 1680x1050@60Hz */
490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
491 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x3b - 1680x1050@75Hz */
494 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
495 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
497 /* 0x3c - 1680x1050@85Hz */
498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
499 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
501 /* 0x3d - 1680x1050@120Hz RB */
502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
503 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
505 /* 0x3e - 1792x1344@60Hz */
506 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
507 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
509 /* 0x3f - 1792x1344@75Hz */
510 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
511 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x40 - 1792x1344@120Hz RB */
514 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
515 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x41 - 1856x1392@60Hz */
518 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
519 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x42 - 1856x1392@75Hz */
522 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
523 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x43 - 1856x1392@120Hz RB */
526 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
527 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x52 - 1920x1080@60Hz */
530 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
531 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
533 /* 0x44 - 1920x1200@60Hz RB */
534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
535 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
537 /* 0x45 - 1920x1200@60Hz */
538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
539 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
541 /* 0x46 - 1920x1200@75Hz */
542 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
543 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
545 /* 0x47 - 1920x1200@85Hz */
546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
547 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
549 /* 0x48 - 1920x1200@120Hz RB */
550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
551 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
553 /* 0x49 - 1920x1440@60Hz */
554 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
555 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x4a - 1920x1440@75Hz */
558 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
559 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x4b - 1920x1440@120Hz RB */
562 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
563 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
565 /* 0x54 - 2048x1152@60Hz */
566 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
567 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
569 /* 0x4c - 2560x1600@60Hz RB */
570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
571 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
573 /* 0x4d - 2560x1600@60Hz */
574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
575 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
577 /* 0x4e - 2560x1600@75Hz */
578 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
579 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
581 /* 0x4f - 2560x1600@85Hz */
582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
583 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
584 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
585 /* 0x50 - 2560x1600@120Hz RB */
586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
587 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
589 /* 0x57 - 4096x2160@60Hz RB */
590 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
591 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
593 /* 0x58 - 4096x2160@59.94Hz RB */
594 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
595 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
600 * These more or less come from the DMT spec. The 720x400 modes are
601 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
602 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
603 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
606 * The DMT modes have been fact-checked; the rest are mild guesses.
608 static const struct drm_display_mode edid_est_modes[] = {
609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
610 968, 1056, 0, 600, 601, 605, 628, 0,
611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
613 896, 1024, 0, 600, 601, 603, 625, 0,
614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
616 720, 840, 0, 480, 481, 484, 500, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
619 704, 832, 0, 480, 489, 492, 520, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
622 768, 864, 0, 480, 483, 486, 525, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
625 752, 800, 0, 480, 490, 492, 525, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
628 846, 900, 0, 400, 421, 423, 449, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
631 846, 900, 0, 400, 412, 414, 449, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
633 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
634 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
637 1136, 1312, 0, 768, 769, 772, 800, 0,
638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
640 1184, 1328, 0, 768, 771, 777, 806, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
643 1184, 1344, 0, 768, 771, 777, 806, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
645 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
646 1208, 1264, 0, 768, 768, 776, 817, 0,
647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
648 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
649 928, 1152, 0, 624, 625, 628, 667, 0,
650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
652 896, 1056, 0, 600, 601, 604, 625, 0,
653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
655 976, 1040, 0, 600, 637, 643, 666, 0,
656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
657 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
658 1344, 1600, 0, 864, 865, 868, 900, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
669 static const struct minimode est3_modes[] = {
677 { 1024, 768, 85, 0 },
678 { 1152, 864, 75, 0 },
680 { 1280, 768, 60, 1 },
681 { 1280, 768, 60, 0 },
682 { 1280, 768, 75, 0 },
683 { 1280, 768, 85, 0 },
684 { 1280, 960, 60, 0 },
685 { 1280, 960, 85, 0 },
686 { 1280, 1024, 60, 0 },
687 { 1280, 1024, 85, 0 },
689 { 1360, 768, 60, 0 },
690 { 1440, 900, 60, 1 },
691 { 1440, 900, 60, 0 },
692 { 1440, 900, 75, 0 },
693 { 1440, 900, 85, 0 },
694 { 1400, 1050, 60, 1 },
695 { 1400, 1050, 60, 0 },
696 { 1400, 1050, 75, 0 },
698 { 1400, 1050, 85, 0 },
699 { 1680, 1050, 60, 1 },
700 { 1680, 1050, 60, 0 },
701 { 1680, 1050, 75, 0 },
702 { 1680, 1050, 85, 0 },
703 { 1600, 1200, 60, 0 },
704 { 1600, 1200, 65, 0 },
705 { 1600, 1200, 70, 0 },
707 { 1600, 1200, 75, 0 },
708 { 1600, 1200, 85, 0 },
709 { 1792, 1344, 60, 0 },
710 { 1792, 1344, 75, 0 },
711 { 1856, 1392, 60, 0 },
712 { 1856, 1392, 75, 0 },
713 { 1920, 1200, 60, 1 },
714 { 1920, 1200, 60, 0 },
716 { 1920, 1200, 75, 0 },
717 { 1920, 1200, 85, 0 },
718 { 1920, 1440, 60, 0 },
719 { 1920, 1440, 75, 0 },
722 static const struct minimode extra_modes[] = {
723 { 1024, 576, 60, 0 },
724 { 1366, 768, 60, 0 },
725 { 1600, 900, 60, 0 },
726 { 1680, 945, 60, 0 },
727 { 1920, 1080, 60, 0 },
728 { 2048, 1152, 60, 0 },
729 { 2048, 1536, 60, 0 },
733 * From CEA/CTA-861 spec.
735 * Do not access directly, instead always use cea_mode_for_vic().
737 static const struct drm_display_mode edid_cea_modes_1[] = {
738 /* 1 - 640x480@60Hz 4:3 */
739 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
740 752, 800, 0, 480, 490, 492, 525, 0,
741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
742 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
743 /* 2 - 720x480@60Hz 4:3 */
744 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
745 798, 858, 0, 480, 489, 495, 525, 0,
746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
747 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
748 /* 3 - 720x480@60Hz 16:9 */
749 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
750 798, 858, 0, 480, 489, 495, 525, 0,
751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 4 - 1280x720@60Hz 16:9 */
754 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
755 1430, 1650, 0, 720, 725, 730, 750, 0,
756 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
758 /* 5 - 1920x1080i@60Hz 16:9 */
759 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
760 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
762 DRM_MODE_FLAG_INTERLACE),
763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
764 /* 6 - 720(1440)x480i@60Hz 4:3 */
765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
766 801, 858, 0, 480, 488, 494, 525, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
770 /* 7 - 720(1440)x480i@60Hz 16:9 */
771 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
772 801, 858, 0, 480, 488, 494, 525, 0,
773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
774 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 8 - 720(1440)x240@60Hz 4:3 */
777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
778 801, 858, 0, 240, 244, 247, 262, 0,
779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
780 DRM_MODE_FLAG_DBLCLK),
781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
782 /* 9 - 720(1440)x240@60Hz 16:9 */
783 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
784 801, 858, 0, 240, 244, 247, 262, 0,
785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
786 DRM_MODE_FLAG_DBLCLK),
787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
788 /* 10 - 2880x480i@60Hz 4:3 */
789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 480, 488, 494, 525, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
792 DRM_MODE_FLAG_INTERLACE),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 11 - 2880x480i@60Hz 16:9 */
795 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 480, 488, 494, 525, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
798 DRM_MODE_FLAG_INTERLACE),
799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 12 - 2880x240@60Hz 4:3 */
801 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
802 3204, 3432, 0, 240, 244, 247, 262, 0,
803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
804 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
805 /* 13 - 2880x240@60Hz 16:9 */
806 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
807 3204, 3432, 0, 240, 244, 247, 262, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
809 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
810 /* 14 - 1440x480@60Hz 4:3 */
811 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
812 1596, 1716, 0, 480, 489, 495, 525, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
815 /* 15 - 1440x480@60Hz 16:9 */
816 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
817 1596, 1716, 0, 480, 489, 495, 525, 0,
818 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
819 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 16 - 1920x1080@60Hz 16:9 */
821 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
822 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
824 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
825 /* 17 - 720x576@50Hz 4:3 */
826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
827 796, 864, 0, 576, 581, 586, 625, 0,
828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
829 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
830 /* 18 - 720x576@50Hz 16:9 */
831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
832 796, 864, 0, 576, 581, 586, 625, 0,
833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 19 - 1280x720@50Hz 16:9 */
836 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
837 1760, 1980, 0, 720, 725, 730, 750, 0,
838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
840 /* 20 - 1920x1080i@50Hz 16:9 */
841 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
842 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
844 DRM_MODE_FLAG_INTERLACE),
845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
846 /* 21 - 720(1440)x576i@50Hz 4:3 */
847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
852 /* 22 - 720(1440)x576i@50Hz 16:9 */
853 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
854 795, 864, 0, 576, 580, 586, 625, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
856 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 23 - 720(1440)x288@50Hz 4:3 */
859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
860 795, 864, 0, 288, 290, 293, 312, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
862 DRM_MODE_FLAG_DBLCLK),
863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
864 /* 24 - 720(1440)x288@50Hz 16:9 */
865 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
866 795, 864, 0, 288, 290, 293, 312, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_DBLCLK),
869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 25 - 2880x576i@50Hz 4:3 */
871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 576, 580, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_INTERLACE),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 26 - 2880x576i@50Hz 16:9 */
877 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 576, 580, 586, 625, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
880 DRM_MODE_FLAG_INTERLACE),
881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 27 - 2880x288@50Hz 4:3 */
883 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
884 3180, 3456, 0, 288, 290, 293, 312, 0,
885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
886 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
887 /* 28 - 2880x288@50Hz 16:9 */
888 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
889 3180, 3456, 0, 288, 290, 293, 312, 0,
890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
891 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
892 /* 29 - 1440x576@50Hz 4:3 */
893 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
894 1592, 1728, 0, 576, 581, 586, 625, 0,
895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
896 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
897 /* 30 - 1440x576@50Hz 16:9 */
898 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
899 1592, 1728, 0, 576, 581, 586, 625, 0,
900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
901 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 31 - 1920x1080@50Hz 16:9 */
903 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
904 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
906 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
907 /* 32 - 1920x1080@24Hz 16:9 */
908 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
909 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
911 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 33 - 1920x1080@25Hz 16:9 */
913 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
914 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
916 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
917 /* 34 - 1920x1080@30Hz 16:9 */
918 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
919 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
920 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
921 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 35 - 2880x480@60Hz 4:3 */
923 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
924 3192, 3432, 0, 480, 489, 495, 525, 0,
925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
926 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
927 /* 36 - 2880x480@60Hz 16:9 */
928 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
929 3192, 3432, 0, 480, 489, 495, 525, 0,
930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
931 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
932 /* 37 - 2880x576@50Hz 4:3 */
933 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
934 3184, 3456, 0, 576, 581, 586, 625, 0,
935 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
937 /* 38 - 2880x576@50Hz 16:9 */
938 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
939 3184, 3456, 0, 576, 581, 586, 625, 0,
940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
942 /* 39 - 1920x1080i@50Hz 16:9 */
943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
944 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
946 DRM_MODE_FLAG_INTERLACE),
947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 40 - 1920x1080i@100Hz 16:9 */
949 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
950 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
952 DRM_MODE_FLAG_INTERLACE),
953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
954 /* 41 - 1280x720@100Hz 16:9 */
955 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
956 1760, 1980, 0, 720, 725, 730, 750, 0,
957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
958 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
959 /* 42 - 720x576@100Hz 4:3 */
960 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
961 796, 864, 0, 576, 581, 586, 625, 0,
962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
964 /* 43 - 720x576@100Hz 16:9 */
965 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
966 796, 864, 0, 576, 581, 586, 625, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
969 /* 44 - 720(1440)x576i@100Hz 4:3 */
970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
975 /* 45 - 720(1440)x576i@100Hz 16:9 */
976 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
977 795, 864, 0, 576, 580, 586, 625, 0,
978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
979 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 46 - 1920x1080i@120Hz 16:9 */
982 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
983 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
985 DRM_MODE_FLAG_INTERLACE),
986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
987 /* 47 - 1280x720@120Hz 16:9 */
988 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
989 1430, 1650, 0, 720, 725, 730, 750, 0,
990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
991 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
992 /* 48 - 720x480@120Hz 4:3 */
993 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
994 798, 858, 0, 480, 489, 495, 525, 0,
995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
997 /* 49 - 720x480@120Hz 16:9 */
998 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
999 798, 858, 0, 480, 489, 495, 525, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1002 /* 50 - 720(1440)x480i@120Hz 4:3 */
1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1008 /* 51 - 720(1440)x480i@120Hz 16:9 */
1009 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1010 801, 858, 0, 480, 488, 494, 525, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1012 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 52 - 720x576@200Hz 4:3 */
1015 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1016 796, 864, 0, 576, 581, 586, 625, 0,
1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1019 /* 53 - 720x576@200Hz 16:9 */
1020 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1021 796, 864, 0, 576, 581, 586, 625, 0,
1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1024 /* 54 - 720(1440)x576i@200Hz 4:3 */
1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1026 795, 864, 0, 576, 580, 586, 625, 0,
1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1030 /* 55 - 720(1440)x576i@200Hz 16:9 */
1031 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1032 795, 864, 0, 576, 580, 586, 625, 0,
1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1034 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1036 /* 56 - 720x480@240Hz 4:3 */
1037 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1038 798, 858, 0, 480, 489, 495, 525, 0,
1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1041 /* 57 - 720x480@240Hz 16:9 */
1042 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1043 798, 858, 0, 480, 489, 495, 525, 0,
1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1046 /* 58 - 720(1440)x480i@240Hz 4:3 */
1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1048 801, 858, 0, 480, 488, 494, 525, 0,
1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1052 /* 59 - 720(1440)x480i@240Hz 16:9 */
1053 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1054 801, 858, 0, 480, 488, 494, 525, 0,
1055 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1056 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 60 - 1280x720@24Hz 16:9 */
1059 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1060 3080, 3300, 0, 720, 725, 730, 750, 0,
1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1062 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1063 /* 61 - 1280x720@25Hz 16:9 */
1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1065 3740, 3960, 0, 720, 725, 730, 750, 0,
1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1067 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1068 /* 62 - 1280x720@30Hz 16:9 */
1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1070 3080, 3300, 0, 720, 725, 730, 750, 0,
1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1073 /* 63 - 1920x1080@120Hz 16:9 */
1074 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1075 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1077 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1078 /* 64 - 1920x1080@100Hz 16:9 */
1079 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1080 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1082 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1083 /* 65 - 1280x720@24Hz 64:27 */
1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1085 3080, 3300, 0, 720, 725, 730, 750, 0,
1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1087 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1088 /* 66 - 1280x720@25Hz 64:27 */
1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1090 3740, 3960, 0, 720, 725, 730, 750, 0,
1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1092 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1093 /* 67 - 1280x720@30Hz 64:27 */
1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1095 3080, 3300, 0, 720, 725, 730, 750, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1097 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1098 /* 68 - 1280x720@50Hz 64:27 */
1099 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1100 1760, 1980, 0, 720, 725, 730, 750, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1103 /* 69 - 1280x720@60Hz 64:27 */
1104 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1105 1430, 1650, 0, 720, 725, 730, 750, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1107 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1108 /* 70 - 1280x720@100Hz 64:27 */
1109 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1110 1760, 1980, 0, 720, 725, 730, 750, 0,
1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1112 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1113 /* 71 - 1280x720@120Hz 64:27 */
1114 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1115 1430, 1650, 0, 720, 725, 730, 750, 0,
1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1117 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1118 /* 72 - 1920x1080@24Hz 64:27 */
1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1120 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1122 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1123 /* 73 - 1920x1080@25Hz 64:27 */
1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1127 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1128 /* 74 - 1920x1080@30Hz 64:27 */
1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1133 /* 75 - 1920x1080@50Hz 64:27 */
1134 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1135 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1137 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1138 /* 76 - 1920x1080@60Hz 64:27 */
1139 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1140 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1142 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1143 /* 77 - 1920x1080@100Hz 64:27 */
1144 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1145 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1147 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1148 /* 78 - 1920x1080@120Hz 64:27 */
1149 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1150 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1152 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1153 /* 79 - 1680x720@24Hz 64:27 */
1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1155 3080, 3300, 0, 720, 725, 730, 750, 0,
1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1157 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1158 /* 80 - 1680x720@25Hz 64:27 */
1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1160 2948, 3168, 0, 720, 725, 730, 750, 0,
1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1163 /* 81 - 1680x720@30Hz 64:27 */
1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1165 2420, 2640, 0, 720, 725, 730, 750, 0,
1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1167 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1168 /* 82 - 1680x720@50Hz 64:27 */
1169 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1170 1980, 2200, 0, 720, 725, 730, 750, 0,
1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1172 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1173 /* 83 - 1680x720@60Hz 64:27 */
1174 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1175 1980, 2200, 0, 720, 725, 730, 750, 0,
1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1177 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1178 /* 84 - 1680x720@100Hz 64:27 */
1179 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1180 1780, 2000, 0, 720, 725, 730, 825, 0,
1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1182 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1183 /* 85 - 1680x720@120Hz 64:27 */
1184 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1185 1780, 2000, 0, 720, 725, 730, 825, 0,
1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1187 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1188 /* 86 - 2560x1080@24Hz 64:27 */
1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1190 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1193 /* 87 - 2560x1080@25Hz 64:27 */
1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1195 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1197 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1198 /* 88 - 2560x1080@30Hz 64:27 */
1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1200 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1202 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1203 /* 89 - 2560x1080@50Hz 64:27 */
1204 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1205 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1207 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1208 /* 90 - 2560x1080@60Hz 64:27 */
1209 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1210 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1212 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1213 /* 91 - 2560x1080@100Hz 64:27 */
1214 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1215 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1217 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1218 /* 92 - 2560x1080@120Hz 64:27 */
1219 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1220 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1223 /* 93 - 3840x2160@24Hz 16:9 */
1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1225 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1227 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1228 /* 94 - 3840x2160@25Hz 16:9 */
1229 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1230 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1232 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1233 /* 95 - 3840x2160@30Hz 16:9 */
1234 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1235 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1238 /* 96 - 3840x2160@50Hz 16:9 */
1239 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1240 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1243 /* 97 - 3840x2160@60Hz 16:9 */
1244 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1245 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1247 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1248 /* 98 - 4096x2160@24Hz 256:135 */
1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1250 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1253 /* 99 - 4096x2160@25Hz 256:135 */
1254 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1255 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1258 /* 100 - 4096x2160@30Hz 256:135 */
1259 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1260 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1263 /* 101 - 4096x2160@50Hz 256:135 */
1264 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1265 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1267 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1268 /* 102 - 4096x2160@60Hz 256:135 */
1269 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1270 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1272 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1273 /* 103 - 3840x2160@24Hz 64:27 */
1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1275 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1277 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1278 /* 104 - 3840x2160@25Hz 64:27 */
1279 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1280 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1282 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1283 /* 105 - 3840x2160@30Hz 64:27 */
1284 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1285 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1287 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1288 /* 106 - 3840x2160@50Hz 64:27 */
1289 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1290 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1292 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1293 /* 107 - 3840x2160@60Hz 64:27 */
1294 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1295 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1297 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1298 /* 108 - 1280x720@48Hz 16:9 */
1299 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1300 2280, 2500, 0, 720, 725, 730, 750, 0,
1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1302 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1303 /* 109 - 1280x720@48Hz 64:27 */
1304 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1305 2280, 2500, 0, 720, 725, 730, 750, 0,
1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1307 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1308 /* 110 - 1680x720@48Hz 64:27 */
1309 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1310 2530, 2750, 0, 720, 725, 730, 750, 0,
1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1312 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1313 /* 111 - 1920x1080@48Hz 16:9 */
1314 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1315 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1317 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1318 /* 112 - 1920x1080@48Hz 64:27 */
1319 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1320 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1322 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1323 /* 113 - 2560x1080@48Hz 64:27 */
1324 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1325 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1327 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1328 /* 114 - 3840x2160@48Hz 16:9 */
1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1330 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1332 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1333 /* 115 - 4096x2160@48Hz 256:135 */
1334 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1335 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1337 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1338 /* 116 - 3840x2160@48Hz 64:27 */
1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1340 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1342 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1343 /* 117 - 3840x2160@100Hz 16:9 */
1344 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1345 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1347 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1348 /* 118 - 3840x2160@120Hz 16:9 */
1349 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1350 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1352 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1353 /* 119 - 3840x2160@100Hz 64:27 */
1354 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1355 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1357 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1358 /* 120 - 3840x2160@120Hz 64:27 */
1359 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1360 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1362 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1363 /* 121 - 5120x2160@24Hz 64:27 */
1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1365 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1367 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1368 /* 122 - 5120x2160@25Hz 64:27 */
1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1370 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1372 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1373 /* 123 - 5120x2160@30Hz 64:27 */
1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1375 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1377 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1378 /* 124 - 5120x2160@48Hz 64:27 */
1379 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1380 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1382 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1383 /* 125 - 5120x2160@50Hz 64:27 */
1384 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1385 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1387 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1388 /* 126 - 5120x2160@60Hz 64:27 */
1389 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1390 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1392 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1393 /* 127 - 5120x2160@100Hz 64:27 */
1394 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1395 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1401 * From CEA/CTA-861 spec.
1403 * Do not access directly, instead always use cea_mode_for_vic().
1405 static const struct drm_display_mode edid_cea_modes_193[] = {
1406 /* 193 - 5120x2160@120Hz 64:27 */
1407 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1408 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1411 /* 194 - 7680x4320@24Hz 16:9 */
1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1413 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1415 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1416 /* 195 - 7680x4320@25Hz 16:9 */
1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1418 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1420 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1421 /* 196 - 7680x4320@30Hz 16:9 */
1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1423 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1425 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1426 /* 197 - 7680x4320@48Hz 16:9 */
1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1428 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1430 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1431 /* 198 - 7680x4320@50Hz 16:9 */
1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1433 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1435 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1436 /* 199 - 7680x4320@60Hz 16:9 */
1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1438 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1440 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1441 /* 200 - 7680x4320@100Hz 16:9 */
1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1443 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1445 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1446 /* 201 - 7680x4320@120Hz 16:9 */
1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1448 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1450 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1451 /* 202 - 7680x4320@24Hz 64:27 */
1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1453 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1455 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1456 /* 203 - 7680x4320@25Hz 64:27 */
1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1458 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1460 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1461 /* 204 - 7680x4320@30Hz 64:27 */
1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1463 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1465 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1466 /* 205 - 7680x4320@48Hz 64:27 */
1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1468 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1470 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1471 /* 206 - 7680x4320@50Hz 64:27 */
1472 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1473 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1475 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1476 /* 207 - 7680x4320@60Hz 64:27 */
1477 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1478 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1480 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1481 /* 208 - 7680x4320@100Hz 64:27 */
1482 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1483 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1485 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1486 /* 209 - 7680x4320@120Hz 64:27 */
1487 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1488 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1490 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1491 /* 210 - 10240x4320@24Hz 64:27 */
1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1493 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1495 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1496 /* 211 - 10240x4320@25Hz 64:27 */
1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1498 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1500 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1501 /* 212 - 10240x4320@30Hz 64:27 */
1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1503 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1505 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1506 /* 213 - 10240x4320@48Hz 64:27 */
1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1508 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1510 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1511 /* 214 - 10240x4320@50Hz 64:27 */
1512 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1513 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1515 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1516 /* 215 - 10240x4320@60Hz 64:27 */
1517 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1518 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1520 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1521 /* 216 - 10240x4320@100Hz 64:27 */
1522 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1523 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1525 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1526 /* 217 - 10240x4320@120Hz 64:27 */
1527 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1528 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1530 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1531 /* 218 - 4096x2160@100Hz 256:135 */
1532 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1533 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1536 /* 219 - 4096x2160@120Hz 256:135 */
1537 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1538 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1540 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1544 * HDMI 1.4 4k modes. Index using the VIC.
1546 static const struct drm_display_mode edid_4k_modes[] = {
1547 /* 0 - dummy, VICs start at 1 */
1549 /* 1 - 3840x2160@30Hz */
1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1551 3840, 4016, 4104, 4400, 0,
1552 2160, 2168, 2178, 2250, 0,
1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1555 /* 2 - 3840x2160@25Hz */
1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1557 3840, 4896, 4984, 5280, 0,
1558 2160, 2168, 2178, 2250, 0,
1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1561 /* 3 - 3840x2160@24Hz */
1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1563 3840, 5116, 5204, 5500, 0,
1564 2160, 2168, 2178, 2250, 0,
1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1567 /* 4 - 4096x2160@24Hz (SMPTE) */
1568 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1569 4096, 5116, 5204, 5500, 0,
1570 2160, 2168, 2178, 2250, 0,
1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1575 /*** DDC fetch and block validation ***/
1578 * The opaque EDID type, internal to drm_edid.c.
1581 /* Size allocated for edid */
1583 const struct edid *edid;
1586 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1588 static int edid_hfeeodb_block_count(const struct edid *edid)
1590 int eeodb = edid_hfeeodb_extension_block_count(edid);
1592 return eeodb ? eeodb + 1 : 0;
1595 static int edid_extension_block_count(const struct edid *edid)
1597 return edid->extensions;
1600 static int edid_block_count(const struct edid *edid)
1602 return edid_extension_block_count(edid) + 1;
1605 static int edid_size_by_blocks(int num_blocks)
1607 return num_blocks * EDID_LENGTH;
1610 static int edid_size(const struct edid *edid)
1612 return edid_size_by_blocks(edid_block_count(edid));
1615 static const void *edid_block_data(const struct edid *edid, int index)
1617 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1619 return edid + index;
1622 static const void *edid_extension_block_data(const struct edid *edid, int index)
1624 return edid_block_data(edid, index + 1);
1627 /* EDID block count indicated in EDID, may exceed allocated size */
1628 static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1632 /* Starting point */
1633 num_blocks = edid_block_count(drm_edid->edid);
1635 /* HF-EEODB override */
1636 if (drm_edid->size >= edid_size_by_blocks(2)) {
1640 * Note: HF-EEODB may specify a smaller extension count than the
1641 * regular one. Unlike in buffer allocation, here we can use it.
1643 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1651 /* EDID block count, limited by allocated size */
1652 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1654 /* Limit by allocated size */
1655 return min(__drm_edid_block_count(drm_edid),
1656 (int)drm_edid->size / EDID_LENGTH);
1659 /* EDID extension block count, limited by allocated size */
1660 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1662 return drm_edid_block_count(drm_edid) - 1;
1665 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1667 return edid_block_data(drm_edid->edid, index);
1670 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1673 return edid_extension_block_data(drm_edid->edid, index);
1677 * Initializer helper for legacy interfaces, where we have no choice but to
1678 * trust edid size. Not for general purpose use.
1680 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1681 const struct edid *edid)
1686 memset(drm_edid, 0, sizeof(*drm_edid));
1688 drm_edid->edid = edid;
1689 drm_edid->size = edid_size(edid);
1695 * EDID base and extension block iterator.
1697 * struct drm_edid_iter iter;
1700 * drm_edid_iter_begin(drm_edid, &iter);
1701 * drm_edid_iter_for_each(block, &iter) {
1702 * // do stuff with block
1704 * drm_edid_iter_end(&iter);
1706 struct drm_edid_iter {
1707 const struct drm_edid *drm_edid;
1709 /* Current block index. */
1713 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1714 struct drm_edid_iter *iter)
1716 memset(iter, 0, sizeof(*iter));
1718 iter->drm_edid = drm_edid;
1721 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1723 const void *block = NULL;
1725 if (!iter->drm_edid)
1728 if (iter->index < drm_edid_block_count(iter->drm_edid))
1729 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1734 #define drm_edid_iter_for_each(__block, __iter) \
1735 while (((__block) = __drm_edid_iter_next(__iter)))
1737 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1739 memset(iter, 0, sizeof(*iter));
1742 static const u8 edid_header[] = {
1743 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1746 static void edid_header_fix(void *edid)
1748 memcpy(edid, edid_header, sizeof(edid_header));
1752 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1753 * @_edid: pointer to raw base EDID block
1755 * Sanity check the header of the base EDID block.
1757 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1759 int drm_edid_header_is_valid(const void *_edid)
1761 const struct edid *edid = _edid;
1764 for (i = 0; i < sizeof(edid_header); i++) {
1765 if (edid->header[i] == edid_header[i])
1771 EXPORT_SYMBOL(drm_edid_header_is_valid);
1773 static int edid_fixup __read_mostly = 6;
1774 module_param_named(edid_fixup, edid_fixup, int, 0400);
1775 MODULE_PARM_DESC(edid_fixup,
1776 "Minimum number of valid EDID header bytes (0-8, default 6)");
1778 static int edid_block_compute_checksum(const void *_block)
1780 const u8 *block = _block;
1782 u8 csum = 0, crc = 0;
1784 for (i = 0; i < EDID_LENGTH - 1; i++)
1792 static int edid_block_get_checksum(const void *_block)
1794 const struct edid *block = _block;
1796 return block->checksum;
1799 static int edid_block_tag(const void *_block)
1801 const u8 *block = _block;
1806 static bool edid_block_is_zero(const void *edid)
1808 return !memchr_inv(edid, 0, EDID_LENGTH);
1812 * drm_edid_are_equal - compare two edid blobs.
1813 * @edid1: pointer to first blob
1814 * @edid2: pointer to second blob
1815 * This helper can be used during probing to determine if
1818 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1820 int edid1_len, edid2_len;
1821 bool edid1_present = edid1 != NULL;
1822 bool edid2_present = edid2 != NULL;
1824 if (edid1_present != edid2_present)
1828 edid1_len = edid_size(edid1);
1829 edid2_len = edid_size(edid2);
1831 if (edid1_len != edid2_len)
1834 if (memcmp(edid1, edid2, edid1_len))
1840 EXPORT_SYMBOL(drm_edid_are_equal);
1842 enum edid_block_status {
1844 EDID_BLOCK_READ_FAIL,
1847 EDID_BLOCK_HEADER_CORRUPT,
1848 EDID_BLOCK_HEADER_REPAIR,
1849 EDID_BLOCK_HEADER_FIXED,
1850 EDID_BLOCK_CHECKSUM,
1854 static enum edid_block_status edid_block_check(const void *_block,
1857 const struct edid *block = _block;
1860 return EDID_BLOCK_NULL;
1862 if (is_base_block) {
1863 int score = drm_edid_header_is_valid(block);
1865 if (score < clamp(edid_fixup, 0, 8)) {
1866 if (edid_block_is_zero(block))
1867 return EDID_BLOCK_ZERO;
1869 return EDID_BLOCK_HEADER_CORRUPT;
1873 return EDID_BLOCK_HEADER_REPAIR;
1876 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1877 if (edid_block_is_zero(block))
1878 return EDID_BLOCK_ZERO;
1880 return EDID_BLOCK_CHECKSUM;
1883 if (is_base_block) {
1884 if (block->version != 1)
1885 return EDID_BLOCK_VERSION;
1888 return EDID_BLOCK_OK;
1891 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1893 return status == EDID_BLOCK_OK ||
1894 status == EDID_BLOCK_HEADER_FIXED ||
1895 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1898 static bool edid_block_valid(const void *block, bool base)
1900 return edid_block_status_valid(edid_block_check(block, base),
1901 edid_block_tag(block));
1904 static void edid_block_status_print(enum edid_block_status status,
1905 const struct edid *block,
1911 case EDID_BLOCK_READ_FAIL:
1912 pr_debug("EDID block %d read failed\n", block_num);
1914 case EDID_BLOCK_NULL:
1915 pr_debug("EDID block %d pointer is NULL\n", block_num);
1917 case EDID_BLOCK_ZERO:
1918 pr_notice("EDID block %d is all zeroes\n", block_num);
1920 case EDID_BLOCK_HEADER_CORRUPT:
1921 pr_notice("EDID has corrupt header\n");
1923 case EDID_BLOCK_HEADER_REPAIR:
1924 pr_debug("EDID corrupt header needs repair\n");
1926 case EDID_BLOCK_HEADER_FIXED:
1927 pr_debug("EDID corrupt header fixed\n");
1929 case EDID_BLOCK_CHECKSUM:
1930 if (edid_block_status_valid(status, edid_block_tag(block))) {
1931 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1932 block_num, edid_block_tag(block),
1933 edid_block_compute_checksum(block));
1935 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1936 block_num, edid_block_tag(block),
1937 edid_block_compute_checksum(block));
1940 case EDID_BLOCK_VERSION:
1941 pr_notice("EDID has major version %d, instead of 1\n",
1945 WARN(1, "EDID block %d unknown edid block status code %d\n",
1951 static void edid_block_dump(const char *level, const void *block, int block_num)
1953 enum edid_block_status status;
1956 status = edid_block_check(block, block_num == 0);
1957 if (status == EDID_BLOCK_ZERO)
1958 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1959 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1960 sprintf(prefix, "\t[%02x] BAD ", block_num);
1962 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1964 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1965 block, EDID_LENGTH, false);
1969 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1970 * @_block: pointer to raw EDID block
1971 * @block_num: type of block to validate (0 for base, extension otherwise)
1972 * @print_bad_edid: if true, dump bad EDID blocks to the console
1973 * @edid_corrupt: if true, the header or checksum is invalid
1975 * Validate a base or extension EDID block and optionally dump bad blocks to
1978 * Return: True if the block is valid, false otherwise.
1980 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1983 struct edid *block = (struct edid *)_block;
1984 enum edid_block_status status;
1985 bool is_base_block = block_num == 0;
1988 if (WARN_ON(!block))
1991 status = edid_block_check(block, is_base_block);
1992 if (status == EDID_BLOCK_HEADER_REPAIR) {
1993 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1994 edid_header_fix(block);
1996 /* Retry with fixed header, update status if that worked. */
1997 status = edid_block_check(block, is_base_block);
1998 if (status == EDID_BLOCK_OK)
1999 status = EDID_BLOCK_HEADER_FIXED;
2004 * Unknown major version isn't corrupt but we can't use it. Only
2005 * the base block can reset edid_corrupt to false.
2007 if (is_base_block &&
2008 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2009 *edid_corrupt = false;
2010 else if (status != EDID_BLOCK_OK)
2011 *edid_corrupt = true;
2014 edid_block_status_print(status, block, block_num);
2016 /* Determine whether we can use this block with this status. */
2017 valid = edid_block_status_valid(status, edid_block_tag(block));
2019 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2020 pr_notice("Raw EDID:\n");
2021 edid_block_dump(KERN_NOTICE, block, block_num);
2026 EXPORT_SYMBOL(drm_edid_block_valid);
2029 * drm_edid_is_valid - sanity check EDID data
2032 * Sanity-check an entire EDID record (including extensions)
2034 * Return: True if the EDID data is valid, false otherwise.
2036 bool drm_edid_is_valid(struct edid *edid)
2043 for (i = 0; i < edid_block_count(edid); i++) {
2044 void *block = (void *)edid_block_data(edid, i);
2046 if (!drm_edid_block_valid(block, i, true, NULL))
2052 EXPORT_SYMBOL(drm_edid_is_valid);
2055 * drm_edid_valid - sanity check EDID data
2056 * @drm_edid: EDID data
2058 * Sanity check an EDID. Cross check block count against allocated size and
2059 * checksum the blocks.
2061 * Return: True if the EDID data is valid, false otherwise.
2063 bool drm_edid_valid(const struct drm_edid *drm_edid)
2070 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2073 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2074 const void *block = drm_edid_block_data(drm_edid, i);
2076 if (!edid_block_valid(block, i == 0))
2082 EXPORT_SYMBOL(drm_edid_valid);
2084 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2088 int i, valid_blocks = 0;
2091 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2092 * back to regular extension count here. We don't want to start
2093 * modifying the HF-EEODB extension too.
2095 for (i = 0; i < edid_block_count(edid); i++) {
2096 const void *src_block = edid_block_data(edid, i);
2098 if (edid_block_valid(src_block, i == 0)) {
2099 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2101 memmove(dst_block, src_block, EDID_LENGTH);
2106 /* We already trusted the base block to be valid here... */
2107 if (WARN_ON(!valid_blocks)) {
2112 edid->extensions = valid_blocks - 1;
2113 edid->checksum = edid_block_compute_checksum(edid);
2115 *alloc_size = edid_size_by_blocks(valid_blocks);
2117 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2124 #define DDC_SEGMENT_ADDR 0x30
2126 * drm_do_probe_ddc_edid() - get EDID information via I2C
2127 * @data: I2C device adapter
2128 * @buf: EDID data buffer to be filled
2129 * @block: 128 byte EDID block to start fetching from
2130 * @len: EDID data buffer length to fetch
2132 * Try to fetch EDID information by calling I2C driver functions.
2134 * Return: 0 on success or -1 on failure.
2137 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2139 struct i2c_adapter *adapter = data;
2140 unsigned char start = block * EDID_LENGTH;
2141 unsigned char segment = block >> 1;
2142 unsigned char xfers = segment ? 3 : 2;
2143 int ret, retries = 5;
2146 * The core I2C driver will automatically retry the transfer if the
2147 * adapter reports EAGAIN. However, we find that bit-banging transfers
2148 * are susceptible to errors under a heavily loaded machine and
2149 * generate spurious NAKs and timeouts. Retrying the transfer
2150 * of the individual block a few times seems to overcome this.
2153 struct i2c_msg msgs[] = {
2155 .addr = DDC_SEGMENT_ADDR,
2173 * Avoid sending the segment addr to not upset non-compliant
2176 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2178 if (ret == -ENXIO) {
2179 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2183 } while (ret != xfers && --retries);
2185 return ret == xfers ? 0 : -1;
2188 static void connector_bad_edid(struct drm_connector *connector,
2189 const struct edid *edid, int num_blocks)
2195 * 0x7e in the EDID is the number of extension blocks. The EDID
2196 * is 1 (base block) + num_ext_blocks big. That means we can think
2197 * of 0x7e in the EDID of the _index_ of the last block in the
2198 * combined chunk of memory.
2200 last_block = edid->extensions;
2202 /* Calculate real checksum for the last edid extension block data */
2203 if (last_block < num_blocks)
2204 connector->real_edid_checksum =
2205 edid_block_compute_checksum(edid + last_block);
2207 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2210 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2211 connector->base.id, connector->name);
2212 for (i = 0; i < num_blocks; i++)
2213 edid_block_dump(KERN_DEBUG, edid + i, i);
2216 /* Get override or firmware EDID */
2217 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2219 const struct drm_edid *override = NULL;
2221 mutex_lock(&connector->edid_override_mutex);
2223 if (connector->edid_override)
2224 override = drm_edid_dup(connector->edid_override);
2226 mutex_unlock(&connector->edid_override_mutex);
2229 override = drm_edid_load_firmware(connector);
2231 return IS_ERR(override) ? NULL : override;
2234 /* For debugfs edid_override implementation */
2235 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2237 const struct drm_edid *drm_edid;
2239 mutex_lock(&connector->edid_override_mutex);
2241 drm_edid = connector->edid_override;
2243 seq_write(m, drm_edid->edid, drm_edid->size);
2245 mutex_unlock(&connector->edid_override_mutex);
2250 /* For debugfs edid_override implementation */
2251 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2254 const struct drm_edid *drm_edid;
2256 drm_edid = drm_edid_alloc(edid, size);
2257 if (!drm_edid_valid(drm_edid)) {
2258 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2259 connector->base.id, connector->name);
2260 drm_edid_free(drm_edid);
2264 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2265 connector->base.id, connector->name);
2267 mutex_lock(&connector->edid_override_mutex);
2269 drm_edid_free(connector->edid_override);
2270 connector->edid_override = drm_edid;
2272 mutex_unlock(&connector->edid_override_mutex);
2277 /* For debugfs edid_override implementation */
2278 int drm_edid_override_reset(struct drm_connector *connector)
2280 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2281 connector->base.id, connector->name);
2283 mutex_lock(&connector->edid_override_mutex);
2285 drm_edid_free(connector->edid_override);
2286 connector->edid_override = NULL;
2288 mutex_unlock(&connector->edid_override_mutex);
2294 * drm_edid_override_connector_update - add modes from override/firmware EDID
2295 * @connector: connector we're probing
2297 * Add modes from the override/firmware EDID, if available. Only to be used from
2298 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2299 * failed during drm_get_edid() and caused the override/firmware EDID to be
2302 * Return: The number of modes added or 0 if we couldn't find any.
2304 int drm_edid_override_connector_update(struct drm_connector *connector)
2306 const struct drm_edid *override;
2309 override = drm_edid_override_get(connector);
2311 num_modes = drm_edid_connector_update(connector, override);
2313 drm_edid_free(override);
2315 drm_dbg_kms(connector->dev,
2316 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2317 connector->base.id, connector->name, num_modes);
2322 EXPORT_SYMBOL(drm_edid_override_connector_update);
2324 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2326 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2327 read_block_fn read_block,
2330 enum edid_block_status status;
2331 bool is_base_block = block_num == 0;
2334 for (try = 0; try < 4; try++) {
2335 if (read_block(context, block, block_num, EDID_LENGTH))
2336 return EDID_BLOCK_READ_FAIL;
2338 status = edid_block_check(block, is_base_block);
2339 if (status == EDID_BLOCK_HEADER_REPAIR) {
2340 edid_header_fix(block);
2342 /* Retry with fixed header, update status if that worked. */
2343 status = edid_block_check(block, is_base_block);
2344 if (status == EDID_BLOCK_OK)
2345 status = EDID_BLOCK_HEADER_FIXED;
2348 if (edid_block_status_valid(status, edid_block_tag(block)))
2351 /* Fail early for unrepairable base block all zeros. */
2352 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2359 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2360 read_block_fn read_block, void *context,
2363 enum edid_block_status status;
2364 int i, num_blocks, invalid_blocks = 0;
2365 const struct drm_edid *override;
2366 struct edid *edid, *new;
2367 size_t alloc_size = EDID_LENGTH;
2369 override = drm_edid_override_get(connector);
2371 alloc_size = override->size;
2372 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2373 drm_edid_free(override);
2379 edid = kmalloc(alloc_size, GFP_KERNEL);
2383 status = edid_block_read(edid, 0, read_block, context);
2385 edid_block_status_print(status, edid, 0);
2387 if (status == EDID_BLOCK_READ_FAIL)
2390 /* FIXME: Clarify what a corrupt EDID actually means. */
2391 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2392 connector->edid_corrupt = false;
2394 connector->edid_corrupt = true;
2396 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2397 if (status == EDID_BLOCK_ZERO)
2398 connector->null_edid_counter++;
2400 connector_bad_edid(connector, edid, 1);
2404 if (!edid_extension_block_count(edid))
2407 alloc_size = edid_size(edid);
2408 new = krealloc(edid, alloc_size, GFP_KERNEL);
2413 num_blocks = edid_block_count(edid);
2414 for (i = 1; i < num_blocks; i++) {
2415 void *block = (void *)edid_block_data(edid, i);
2417 status = edid_block_read(block, i, read_block, context);
2419 edid_block_status_print(status, block, i);
2421 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2422 if (status == EDID_BLOCK_READ_FAIL)
2425 } else if (i == 1) {
2427 * If the first EDID extension is a CTA extension, and
2428 * the first Data Block is HF-EEODB, override the
2429 * extension block count.
2431 * Note: HF-EEODB could specify a smaller extension
2432 * count too, but we can't risk allocating a smaller
2435 int eeodb = edid_hfeeodb_block_count(edid);
2437 if (eeodb > num_blocks) {
2439 alloc_size = edid_size_by_blocks(num_blocks);
2440 new = krealloc(edid, alloc_size, GFP_KERNEL);
2448 if (invalid_blocks) {
2449 connector_bad_edid(connector, edid, num_blocks);
2451 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2466 * drm_do_get_edid - get EDID data using a custom EDID block read function
2467 * @connector: connector we're probing
2468 * @read_block: EDID block read function
2469 * @context: private data passed to the block read function
2471 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2472 * exposes a different interface to read EDID blocks this function can be used
2473 * to get EDID data using a custom block read function.
2475 * As in the general case the DDC bus is accessible by the kernel at the I2C
2476 * level, drivers must make all reasonable efforts to expose it as an I2C
2477 * adapter and use drm_get_edid() instead of abusing this function.
2479 * The EDID may be overridden using debugfs override_edid or firmware EDID
2480 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2481 * order. Having either of them bypasses actual EDID reads.
2483 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2485 struct edid *drm_do_get_edid(struct drm_connector *connector,
2486 read_block_fn read_block,
2489 return _drm_do_get_edid(connector, read_block, context, NULL);
2491 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2494 * drm_edid_raw - Get a pointer to the raw EDID data.
2495 * @drm_edid: drm_edid container
2497 * Get a pointer to the raw EDID data.
2499 * This is for transition only. Avoid using this like the plague.
2501 * Return: Pointer to raw EDID data.
2503 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2505 if (!drm_edid || !drm_edid->size)
2509 * Do not return pointers where relying on EDID extension count would
2510 * lead to buffer overflow.
2512 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2515 return drm_edid->edid;
2517 EXPORT_SYMBOL(drm_edid_raw);
2519 /* Allocate struct drm_edid container *without* duplicating the edid data */
2520 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2522 struct drm_edid *drm_edid;
2524 if (!edid || !size || size < EDID_LENGTH)
2527 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2529 drm_edid->edid = edid;
2530 drm_edid->size = size;
2537 * drm_edid_alloc - Allocate a new drm_edid container
2538 * @edid: Pointer to raw EDID data
2539 * @size: Size of memory allocated for EDID
2541 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2542 * the actual size that has been allocated for the data. There is no validation
2543 * of the raw EDID data against the size, but at least the EDID base block must
2544 * fit in the buffer.
2546 * The returned pointer must be freed using drm_edid_free().
2548 * Return: drm_edid container, or NULL on errors
2550 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2552 const struct drm_edid *drm_edid;
2554 if (!edid || !size || size < EDID_LENGTH)
2557 edid = kmemdup(edid, size, GFP_KERNEL);
2561 drm_edid = _drm_edid_alloc(edid, size);
2567 EXPORT_SYMBOL(drm_edid_alloc);
2570 * drm_edid_dup - Duplicate a drm_edid container
2571 * @drm_edid: EDID to duplicate
2573 * The returned pointer must be freed using drm_edid_free().
2575 * Returns: drm_edid container copy, or NULL on errors
2577 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2582 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2584 EXPORT_SYMBOL(drm_edid_dup);
2587 * drm_edid_free - Free the drm_edid container
2588 * @drm_edid: EDID to free
2590 void drm_edid_free(const struct drm_edid *drm_edid)
2595 kfree(drm_edid->edid);
2598 EXPORT_SYMBOL(drm_edid_free);
2601 * drm_probe_ddc() - probe DDC presence
2602 * @adapter: I2C adapter to probe
2604 * Return: True on success, false on failure.
2607 drm_probe_ddc(struct i2c_adapter *adapter)
2611 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2613 EXPORT_SYMBOL(drm_probe_ddc);
2616 * drm_get_edid - get EDID data, if available
2617 * @connector: connector we're probing
2618 * @adapter: I2C adapter to use for DDC
2620 * Poke the given I2C channel to grab EDID data if possible. If found,
2621 * attach it to the connector.
2623 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2625 struct edid *drm_get_edid(struct drm_connector *connector,
2626 struct i2c_adapter *adapter)
2630 if (connector->force == DRM_FORCE_OFF)
2633 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2636 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2637 drm_connector_update_edid_property(connector, edid);
2640 EXPORT_SYMBOL(drm_get_edid);
2643 * drm_edid_read_custom - Read EDID data using given EDID block read function
2644 * @connector: Connector to use
2645 * @read_block: EDID block read function
2646 * @context: Private data passed to the block read function
2648 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2649 * exposes a different interface to read EDID blocks this function can be used
2650 * to get EDID data using a custom block read function.
2652 * As in the general case the DDC bus is accessible by the kernel at the I2C
2653 * level, drivers must make all reasonable efforts to expose it as an I2C
2654 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2657 * The EDID may be overridden using debugfs override_edid or firmware EDID
2658 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2659 * order. Having either of them bypasses actual EDID reads.
2661 * The returned pointer must be freed using drm_edid_free().
2663 * Return: Pointer to EDID, or NULL if probe/read failed.
2665 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2666 read_block_fn read_block,
2669 const struct drm_edid *drm_edid;
2673 edid = _drm_do_get_edid(connector, read_block, context, &size);
2677 /* Sanity check for now */
2678 drm_WARN_ON(connector->dev, !size);
2680 drm_edid = _drm_edid_alloc(edid, size);
2686 EXPORT_SYMBOL(drm_edid_read_custom);
2689 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2690 * @connector: Connector to use
2691 * @adapter: I2C adapter to use for DDC
2693 * Read EDID using the given I2C adapter.
2695 * The EDID may be overridden using debugfs override_edid or firmware EDID
2696 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2697 * order. Having either of them bypasses actual EDID reads.
2699 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2700 * using drm_edid_read() instead of this function.
2702 * The returned pointer must be freed using drm_edid_free().
2704 * Return: Pointer to EDID, or NULL if probe/read failed.
2706 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2707 struct i2c_adapter *adapter)
2709 const struct drm_edid *drm_edid;
2711 if (connector->force == DRM_FORCE_OFF)
2714 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2717 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2719 /* Note: Do *not* call connector updates here. */
2723 EXPORT_SYMBOL(drm_edid_read_ddc);
2726 * drm_edid_read - Read EDID data using connector's I2C adapter
2727 * @connector: Connector to use
2729 * Read EDID using the connector's I2C adapter.
2731 * The EDID may be overridden using debugfs override_edid or firmware EDID
2732 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2733 * order. Having either of them bypasses actual EDID reads.
2735 * The returned pointer must be freed using drm_edid_free().
2737 * Return: Pointer to EDID, or NULL if probe/read failed.
2739 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2741 if (drm_WARN_ON(connector->dev, !connector->ddc))
2744 return drm_edid_read_ddc(connector, connector->ddc);
2746 EXPORT_SYMBOL(drm_edid_read);
2748 static u32 edid_extract_panel_id(const struct edid *edid)
2751 * We represent the ID as a 32-bit number so it can easily be compared
2754 * NOTE that we deal with endianness differently for the top half
2755 * of this ID than for the bottom half. The bottom half (the product
2756 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2757 * that's how everyone seems to interpret it. The top half (the mfg_id)
2758 * gets stored as big endian because that makes
2759 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2760 * to write (it's easier to extract the ASCII). It doesn't really
2761 * matter, though, as long as the number here is unique.
2763 return (u32)edid->mfg_id[0] << 24 |
2764 (u32)edid->mfg_id[1] << 16 |
2765 (u32)EDID_PRODUCT_ID(edid);
2769 * drm_edid_get_panel_id - Get a panel's ID through DDC
2770 * @adapter: I2C adapter to use for DDC
2772 * This function reads the first block of the EDID of a panel and (assuming
2773 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2774 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2775 * supposed to be different for each different modem of panel.
2777 * This function is intended to be used during early probing on devices where
2778 * more than one panel might be present. Because of its intended use it must
2779 * assume that the EDID of the panel is correct, at least as far as the ID
2780 * is concerned (in other words, we don't process any overrides here).
2782 * NOTE: it's expected that this function and drm_do_get_edid() will both
2783 * be read the EDID, but there is no caching between them. Since we're only
2784 * reading the first block, hopefully this extra overhead won't be too big.
2786 * Return: A 32-bit ID that should be different for each make/model of panel.
2787 * See the functions drm_edid_encode_panel_id() and
2788 * drm_edid_decode_panel_id() for some details on the structure of this
2792 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2794 enum edid_block_status status;
2799 * There are no manufacturer IDs of 0, so if there is a problem reading
2800 * the EDID then we'll just return 0.
2803 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2807 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2809 edid_block_status_print(status, base_block, 0);
2811 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2812 panel_id = edid_extract_panel_id(base_block);
2814 edid_block_dump(KERN_NOTICE, base_block, 0);
2820 EXPORT_SYMBOL(drm_edid_get_panel_id);
2823 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2824 * @connector: connector we're probing
2825 * @adapter: I2C adapter to use for DDC
2827 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2828 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2829 * switch DDC to the GPU which is retrieving EDID.
2831 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2833 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2834 struct i2c_adapter *adapter)
2836 struct drm_device *dev = connector->dev;
2837 struct pci_dev *pdev = to_pci_dev(dev->dev);
2840 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2843 vga_switcheroo_lock_ddc(pdev);
2844 edid = drm_get_edid(connector, adapter);
2845 vga_switcheroo_unlock_ddc(pdev);
2849 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2852 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2853 * @connector: connector we're probing
2854 * @adapter: I2C adapter to use for DDC
2856 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2857 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2858 * temporarily switch DDC to the GPU which is retrieving EDID.
2860 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2862 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2863 struct i2c_adapter *adapter)
2865 struct drm_device *dev = connector->dev;
2866 struct pci_dev *pdev = to_pci_dev(dev->dev);
2867 const struct drm_edid *drm_edid;
2869 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2872 vga_switcheroo_lock_ddc(pdev);
2873 drm_edid = drm_edid_read_ddc(connector, adapter);
2874 vga_switcheroo_unlock_ddc(pdev);
2878 EXPORT_SYMBOL(drm_edid_read_switcheroo);
2881 * drm_edid_duplicate - duplicate an EDID and the extensions
2882 * @edid: EDID to duplicate
2884 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2886 struct edid *drm_edid_duplicate(const struct edid *edid)
2891 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2893 EXPORT_SYMBOL(drm_edid_duplicate);
2895 /*** EDID parsing ***/
2898 * edid_get_quirks - return quirk flags for a given EDID
2899 * @drm_edid: EDID to process
2901 * This tells subsequent routines what fixes they need to apply.
2903 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2905 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2906 const struct edid_quirk *quirk;
2909 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2910 quirk = &edid_quirk_list[i];
2911 if (quirk->panel_id == panel_id)
2912 return quirk->quirks;
2918 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2919 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2922 * Walk the mode list for connector, clearing the preferred status on existing
2923 * modes and setting it anew for the right mode ala quirks.
2925 static void edid_fixup_preferred(struct drm_connector *connector)
2927 const struct drm_display_info *info = &connector->display_info;
2928 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2929 int target_refresh = 0;
2930 int cur_vrefresh, preferred_vrefresh;
2932 if (list_empty(&connector->probed_modes))
2935 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2936 target_refresh = 60;
2937 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2938 target_refresh = 75;
2940 preferred_mode = list_first_entry(&connector->probed_modes,
2941 struct drm_display_mode, head);
2943 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2944 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2946 if (cur_mode == preferred_mode)
2949 /* Largest mode is preferred */
2950 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2951 preferred_mode = cur_mode;
2953 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2954 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2955 /* At a given size, try to get closest to target refresh */
2956 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2957 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2958 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2959 preferred_mode = cur_mode;
2963 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2967 mode_is_rb(const struct drm_display_mode *mode)
2969 return (mode->htotal - mode->hdisplay == 160) &&
2970 (mode->hsync_end - mode->hdisplay == 80) &&
2971 (mode->hsync_end - mode->hsync_start == 32) &&
2972 (mode->vsync_start - mode->vdisplay == 3);
2976 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2977 * @dev: Device to duplicate against
2978 * @hsize: Mode width
2979 * @vsize: Mode height
2980 * @fresh: Mode refresh rate
2981 * @rb: Mode reduced-blanking-ness
2983 * Walk the DMT mode list looking for a match for the given parameters.
2985 * Return: A newly allocated copy of the mode, or NULL if not found.
2987 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2988 int hsize, int vsize, int fresh,
2993 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2994 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2996 if (hsize != ptr->hdisplay)
2998 if (vsize != ptr->vdisplay)
3000 if (fresh != drm_mode_vrefresh(ptr))
3002 if (rb != mode_is_rb(ptr))
3005 return drm_mode_duplicate(dev, ptr);
3010 EXPORT_SYMBOL(drm_mode_find_dmt);
3012 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3014 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3015 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3016 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3018 return descriptor->pixel_clock == 0 &&
3019 descriptor->data.other_data.pad1 == 0 &&
3020 descriptor->data.other_data.type == type;
3023 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3025 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3027 return descriptor->pixel_clock != 0;
3030 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3033 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3037 const u8 *det_base = ext + d;
3039 if (d < 4 || d > 127)
3043 for (i = 0; i < n; i++)
3044 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3048 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3050 unsigned int i, n = min((int)ext[0x02], 6);
3051 const u8 *det_base = ext + 5;
3054 return; /* unknown version */
3056 for (i = 0; i < n; i++)
3057 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3060 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3061 detailed_cb *cb, void *closure)
3063 struct drm_edid_iter edid_iter;
3070 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3071 cb(&drm_edid->edid->detailed_timings[i], closure);
3073 drm_edid_iter_begin(drm_edid, &edid_iter);
3074 drm_edid_iter_for_each(ext, &edid_iter) {
3077 cea_for_each_detailed_block(ext, cb, closure);
3080 vtb_for_each_detailed_block(ext, cb, closure);
3086 drm_edid_iter_end(&edid_iter);
3090 is_rb(const struct detailed_timing *descriptor, void *data)
3094 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3097 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3098 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3100 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3101 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3105 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3107 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3109 if (drm_edid->edid->revision >= 4) {
3112 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3116 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
3120 find_gtf2(const struct detailed_timing *descriptor, void *data)
3122 const struct detailed_timing **res = data;
3124 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3127 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3129 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3133 /* Secondary GTF curve kicks in above some break frequency */
3135 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3137 const struct detailed_timing *descriptor = NULL;
3139 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3141 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3143 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3147 drm_gtf2_2c(const struct drm_edid *drm_edid)
3149 const struct detailed_timing *descriptor = NULL;
3151 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3153 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3155 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3159 drm_gtf2_m(const struct drm_edid *drm_edid)
3161 const struct detailed_timing *descriptor = NULL;
3163 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3165 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3167 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3171 drm_gtf2_k(const struct drm_edid *drm_edid)
3173 const struct detailed_timing *descriptor = NULL;
3175 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3177 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3179 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3183 drm_gtf2_2j(const struct drm_edid *drm_edid)
3185 const struct detailed_timing *descriptor = NULL;
3187 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3189 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3191 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3195 get_timing_level(const struct detailed_timing *descriptor, void *data)
3199 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3202 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3204 switch (descriptor->data.other_data.data.range.flags) {
3205 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3208 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3211 case DRM_EDID_CVT_SUPPORT_FLAG:
3219 /* Get standard timing level (CVT/GTF/DMT). */
3220 static int standard_timing_level(const struct drm_edid *drm_edid)
3222 const struct edid *edid = drm_edid->edid;
3224 if (edid->revision >= 4) {
3226 * If the range descriptor doesn't
3227 * indicate otherwise default to CVT
3229 int ret = LEVEL_CVT;
3231 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3234 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3236 } else if (edid->revision >= 2) {
3244 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3245 * monitors fill with ascii space (0x20) instead.
3248 bad_std_timing(u8 a, u8 b)
3250 return (a == 0x00 && b == 0x00) ||
3251 (a == 0x01 && b == 0x01) ||
3252 (a == 0x20 && b == 0x20);
3255 static int drm_mode_hsync(const struct drm_display_mode *mode)
3257 if (mode->htotal <= 0)
3260 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3263 static struct drm_display_mode *
3264 drm_gtf2_mode(struct drm_device *dev,
3265 const struct drm_edid *drm_edid,
3266 int hsize, int vsize, int vrefresh_rate)
3268 struct drm_display_mode *mode;
3271 * This is potentially wrong if there's ever a monitor with
3272 * more than one ranges section, each claiming a different
3273 * secondary GTF curve. Please don't do that.
3275 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3279 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3280 drm_mode_destroy(dev, mode);
3281 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3282 vrefresh_rate, 0, 0,
3283 drm_gtf2_m(drm_edid),
3284 drm_gtf2_2c(drm_edid),
3285 drm_gtf2_k(drm_edid),
3286 drm_gtf2_2j(drm_edid));
3293 * Take the standard timing params (in this case width, aspect, and refresh)
3294 * and convert them into a real mode using CVT/GTF/DMT.
3296 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3297 const struct drm_edid *drm_edid,
3298 const struct std_timing *t)
3300 struct drm_device *dev = connector->dev;
3301 struct drm_display_mode *m, *mode = NULL;
3304 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3305 >> EDID_TIMING_ASPECT_SHIFT;
3306 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3307 >> EDID_TIMING_VFREQ_SHIFT;
3308 int timing_level = standard_timing_level(drm_edid);
3310 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3313 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3314 hsize = t->hsize * 8 + 248;
3315 /* vrefresh_rate = vfreq + 60 */
3316 vrefresh_rate = vfreq + 60;
3317 /* the vdisplay is calculated based on the aspect ratio */
3318 if (aspect_ratio == 0) {
3319 if (drm_edid->edid->revision < 3)
3322 vsize = (hsize * 10) / 16;
3323 } else if (aspect_ratio == 1)
3324 vsize = (hsize * 3) / 4;
3325 else if (aspect_ratio == 2)
3326 vsize = (hsize * 4) / 5;
3328 vsize = (hsize * 9) / 16;
3330 /* HDTV hack, part 1 */
3331 if (vrefresh_rate == 60 &&
3332 ((hsize == 1360 && vsize == 765) ||
3333 (hsize == 1368 && vsize == 769))) {
3339 * If this connector already has a mode for this size and refresh
3340 * rate (because it came from detailed or CVT info), use that
3341 * instead. This way we don't have to guess at interlace or
3344 list_for_each_entry(m, &connector->probed_modes, head)
3345 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3346 drm_mode_vrefresh(m) == vrefresh_rate)
3349 /* HDTV hack, part 2 */
3350 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3351 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3355 mode->hdisplay = 1366;
3356 mode->hsync_start = mode->hsync_start - 1;
3357 mode->hsync_end = mode->hsync_end - 1;
3361 /* check whether it can be found in default mode table */
3362 if (drm_monitor_supports_rb(drm_edid)) {
3363 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3368 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3372 /* okay, generate it */
3373 switch (timing_level) {
3377 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3380 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3383 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3391 * EDID is delightfully ambiguous about how interlaced modes are to be
3392 * encoded. Our internal representation is of frame height, but some
3393 * HDTV detailed timings are encoded as field height.
3395 * The format list here is from CEA, in frame size. Technically we
3396 * should be checking refresh rate too. Whatever.
3399 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3400 const struct detailed_pixel_timing *pt)
3403 static const struct {
3405 } cea_interlaced[] = {
3415 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3418 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3419 if ((mode->hdisplay == cea_interlaced[i].w) &&
3420 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3421 mode->vdisplay *= 2;
3422 mode->vsync_start *= 2;
3423 mode->vsync_end *= 2;
3429 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3433 * Create a new mode from an EDID detailed timing section. An EDID detailed
3434 * timing block contains enough info for us to create and return a new struct
3437 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3438 const struct drm_edid *drm_edid,
3439 const struct detailed_timing *timing)
3441 const struct drm_display_info *info = &connector->display_info;
3442 struct drm_device *dev = connector->dev;
3443 struct drm_display_mode *mode;
3444 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3445 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3446 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3447 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3448 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3449 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3450 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3451 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3452 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3454 /* ignore tiny modes */
3455 if (hactive < 64 || vactive < 64)
3458 if (pt->misc & DRM_EDID_PT_STEREO) {
3459 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3460 connector->base.id, connector->name);
3463 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3464 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3465 connector->base.id, connector->name);
3468 /* it is incorrect if hsync/vsync width is zero */
3469 if (!hsync_pulse_width || !vsync_pulse_width) {
3470 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3471 connector->base.id, connector->name);
3475 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3476 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3483 mode = drm_mode_create(dev);
3487 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3488 mode->clock = 1088 * 10;
3490 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3492 mode->hdisplay = hactive;
3493 mode->hsync_start = mode->hdisplay + hsync_offset;
3494 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3495 mode->htotal = mode->hdisplay + hblank;
3497 mode->vdisplay = vactive;
3498 mode->vsync_start = mode->vdisplay + vsync_offset;
3499 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3500 mode->vtotal = mode->vdisplay + vblank;
3502 /* Some EDIDs have bogus h/vtotal values */
3503 if (mode->hsync_end > mode->htotal)
3504 mode->htotal = mode->hsync_end + 1;
3505 if (mode->vsync_end > mode->vtotal)
3506 mode->vtotal = mode->vsync_end + 1;
3508 drm_mode_do_interlace_quirk(mode, pt);
3510 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3511 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3513 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3514 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3515 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3516 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3520 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3521 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3523 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3524 mode->width_mm *= 10;
3525 mode->height_mm *= 10;
3528 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3529 mode->width_mm = drm_edid->edid->width_cm * 10;
3530 mode->height_mm = drm_edid->edid->height_cm * 10;
3533 mode->type = DRM_MODE_TYPE_DRIVER;
3534 drm_mode_set_name(mode);
3540 mode_in_hsync_range(const struct drm_display_mode *mode,
3541 const struct edid *edid, const u8 *t)
3543 int hsync, hmin, hmax;
3546 if (edid->revision >= 4)
3547 hmin += ((t[4] & 0x04) ? 255 : 0);
3549 if (edid->revision >= 4)
3550 hmax += ((t[4] & 0x08) ? 255 : 0);
3551 hsync = drm_mode_hsync(mode);
3553 return (hsync <= hmax && hsync >= hmin);
3557 mode_in_vsync_range(const struct drm_display_mode *mode,
3558 const struct edid *edid, const u8 *t)
3560 int vsync, vmin, vmax;
3563 if (edid->revision >= 4)
3564 vmin += ((t[4] & 0x01) ? 255 : 0);
3566 if (edid->revision >= 4)
3567 vmax += ((t[4] & 0x02) ? 255 : 0);
3568 vsync = drm_mode_vrefresh(mode);
3570 return (vsync <= vmax && vsync >= vmin);
3574 range_pixel_clock(const struct edid *edid, const u8 *t)
3577 if (t[9] == 0 || t[9] == 255)
3580 /* 1.4 with CVT support gives us real precision, yay */
3581 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3582 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3584 /* 1.3 is pathetic, so fuzz up a bit */
3585 return t[9] * 10000 + 5001;
3588 static bool mode_in_range(const struct drm_display_mode *mode,
3589 const struct drm_edid *drm_edid,
3590 const struct detailed_timing *timing)
3592 const struct edid *edid = drm_edid->edid;
3594 const u8 *t = (const u8 *)timing;
3596 if (!mode_in_hsync_range(mode, edid, t))
3599 if (!mode_in_vsync_range(mode, edid, t))
3602 if ((max_clock = range_pixel_clock(edid, t)))
3603 if (mode->clock > max_clock)
3606 /* 1.4 max horizontal check */
3607 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3608 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3611 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3617 static bool valid_inferred_mode(const struct drm_connector *connector,
3618 const struct drm_display_mode *mode)
3620 const struct drm_display_mode *m;
3623 list_for_each_entry(m, &connector->probed_modes, head) {
3624 if (mode->hdisplay == m->hdisplay &&
3625 mode->vdisplay == m->vdisplay &&
3626 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3627 return false; /* duplicated */
3628 if (mode->hdisplay <= m->hdisplay &&
3629 mode->vdisplay <= m->vdisplay)
3635 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3636 const struct drm_edid *drm_edid,
3637 const struct detailed_timing *timing)
3640 struct drm_display_mode *newmode;
3641 struct drm_device *dev = connector->dev;
3643 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3644 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3645 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3646 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3648 drm_mode_probed_add(connector, newmode);
3657 /* fix up 1366x768 mode from 1368x768;
3658 * GFT/CVT can't express 1366 width which isn't dividable by 8
3660 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3662 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3663 mode->hdisplay = 1366;
3664 mode->hsync_start--;
3666 drm_mode_set_name(mode);
3670 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3671 const struct drm_edid *drm_edid,
3672 const struct detailed_timing *timing)
3675 struct drm_display_mode *newmode;
3676 struct drm_device *dev = connector->dev;
3678 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3679 const struct minimode *m = &extra_modes[i];
3681 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3685 drm_mode_fixup_1366x768(newmode);
3686 if (!mode_in_range(newmode, drm_edid, timing) ||
3687 !valid_inferred_mode(connector, newmode)) {
3688 drm_mode_destroy(dev, newmode);
3692 drm_mode_probed_add(connector, newmode);
3699 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3700 const struct drm_edid *drm_edid,
3701 const struct detailed_timing *timing)
3704 struct drm_display_mode *newmode;
3705 struct drm_device *dev = connector->dev;
3707 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3708 const struct minimode *m = &extra_modes[i];
3710 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3714 drm_mode_fixup_1366x768(newmode);
3715 if (!mode_in_range(newmode, drm_edid, timing) ||
3716 !valid_inferred_mode(connector, newmode)) {
3717 drm_mode_destroy(dev, newmode);
3721 drm_mode_probed_add(connector, newmode);
3728 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3729 const struct drm_edid *drm_edid,
3730 const struct detailed_timing *timing)
3733 struct drm_display_mode *newmode;
3734 struct drm_device *dev = connector->dev;
3735 bool rb = drm_monitor_supports_rb(drm_edid);
3737 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3738 const struct minimode *m = &extra_modes[i];
3740 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3744 drm_mode_fixup_1366x768(newmode);
3745 if (!mode_in_range(newmode, drm_edid, timing) ||
3746 !valid_inferred_mode(connector, newmode)) {
3747 drm_mode_destroy(dev, newmode);
3751 drm_mode_probed_add(connector, newmode);
3759 do_inferred_modes(const struct detailed_timing *timing, void *c)
3761 struct detailed_mode_closure *closure = c;
3762 const struct detailed_non_pixel *data = &timing->data.other_data;
3763 const struct detailed_data_monitor_range *range = &data->data.range;
3765 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3768 closure->modes += drm_dmt_modes_for_range(closure->connector,
3772 if (closure->drm_edid->edid->revision < 2)
3773 return; /* GTF not defined yet */
3775 switch (range->flags) {
3776 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3777 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3781 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3782 closure->modes += drm_gtf_modes_for_range(closure->connector,
3786 case DRM_EDID_CVT_SUPPORT_FLAG:
3787 if (closure->drm_edid->edid->revision < 4)
3790 closure->modes += drm_cvt_modes_for_range(closure->connector,
3794 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3800 static int add_inferred_modes(struct drm_connector *connector,
3801 const struct drm_edid *drm_edid)
3803 struct detailed_mode_closure closure = {
3804 .connector = connector,
3805 .drm_edid = drm_edid,
3808 if (drm_edid->edid->revision >= 1)
3809 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3811 return closure.modes;
3815 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3817 int i, j, m, modes = 0;
3818 struct drm_display_mode *mode;
3819 const u8 *est = ((const u8 *)timing) + 6;
3821 for (i = 0; i < 6; i++) {
3822 for (j = 7; j >= 0; j--) {
3823 m = (i * 8) + (7 - j);
3824 if (m >= ARRAY_SIZE(est3_modes))
3826 if (est[i] & (1 << j)) {
3827 mode = drm_mode_find_dmt(connector->dev,
3833 drm_mode_probed_add(connector, mode);
3844 do_established_modes(const struct detailed_timing *timing, void *c)
3846 struct detailed_mode_closure *closure = c;
3848 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3851 closure->modes += drm_est3_modes(closure->connector, timing);
3855 * Get established modes from EDID and add them. Each EDID block contains a
3856 * bitmap of the supported "established modes" list (defined above). Tease them
3857 * out and add them to the global modes list.
3859 static int add_established_modes(struct drm_connector *connector,
3860 const struct drm_edid *drm_edid)
3862 struct drm_device *dev = connector->dev;
3863 const struct edid *edid = drm_edid->edid;
3864 unsigned long est_bits = edid->established_timings.t1 |
3865 (edid->established_timings.t2 << 8) |
3866 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3868 struct detailed_mode_closure closure = {
3869 .connector = connector,
3870 .drm_edid = drm_edid,
3873 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3874 if (est_bits & (1<<i)) {
3875 struct drm_display_mode *newmode;
3877 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3879 drm_mode_probed_add(connector, newmode);
3885 if (edid->revision >= 1)
3886 drm_for_each_detailed_block(drm_edid, do_established_modes,
3889 return modes + closure.modes;
3893 do_standard_modes(const struct detailed_timing *timing, void *c)
3895 struct detailed_mode_closure *closure = c;
3896 const struct detailed_non_pixel *data = &timing->data.other_data;
3897 struct drm_connector *connector = closure->connector;
3900 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3903 for (i = 0; i < 6; i++) {
3904 const struct std_timing *std = &data->data.timings[i];
3905 struct drm_display_mode *newmode;
3907 newmode = drm_mode_std(connector, closure->drm_edid, std);
3909 drm_mode_probed_add(connector, newmode);
3916 * Get standard modes from EDID and add them. Standard modes can be calculated
3917 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3918 * add them to the list.
3920 static int add_standard_modes(struct drm_connector *connector,
3921 const struct drm_edid *drm_edid)
3924 struct detailed_mode_closure closure = {
3925 .connector = connector,
3926 .drm_edid = drm_edid,
3929 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3930 struct drm_display_mode *newmode;
3932 newmode = drm_mode_std(connector, drm_edid,
3933 &drm_edid->edid->standard_timings[i]);
3935 drm_mode_probed_add(connector, newmode);
3940 if (drm_edid->edid->revision >= 1)
3941 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3944 /* XXX should also look for standard codes in VTB blocks */
3946 return modes + closure.modes;
3949 static int drm_cvt_modes(struct drm_connector *connector,
3950 const struct detailed_timing *timing)
3952 int i, j, modes = 0;
3953 struct drm_display_mode *newmode;
3954 struct drm_device *dev = connector->dev;
3955 const struct cvt_timing *cvt;
3956 static const int rates[] = { 60, 85, 75, 60, 50 };
3957 const u8 empty[3] = { 0, 0, 0 };
3959 for (i = 0; i < 4; i++) {
3962 cvt = &(timing->data.other_data.data.cvt[i]);
3964 if (!memcmp(cvt->code, empty, 3))
3967 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3968 switch (cvt->code[1] & 0x0c) {
3969 /* default - because compiler doesn't see that we've enumerated all cases */
3972 width = height * 4 / 3;
3975 width = height * 16 / 9;
3978 width = height * 16 / 10;
3981 width = height * 15 / 9;
3985 for (j = 1; j < 5; j++) {
3986 if (cvt->code[2] & (1 << j)) {
3987 newmode = drm_cvt_mode(dev, width, height,
3991 drm_mode_probed_add(connector, newmode);
4002 do_cvt_mode(const struct detailed_timing *timing, void *c)
4004 struct detailed_mode_closure *closure = c;
4006 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4009 closure->modes += drm_cvt_modes(closure->connector, timing);
4013 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4015 struct detailed_mode_closure closure = {
4016 .connector = connector,
4017 .drm_edid = drm_edid,
4020 if (drm_edid->edid->revision >= 3)
4021 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4023 /* XXX should also look for CVT codes in VTB blocks */
4025 return closure.modes;
4028 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4029 struct drm_display_mode *mode);
4032 do_detailed_mode(const struct detailed_timing *timing, void *c)
4034 struct detailed_mode_closure *closure = c;
4035 struct drm_display_mode *newmode;
4037 if (!is_detailed_timing_descriptor(timing))
4040 newmode = drm_mode_detailed(closure->connector,
4041 closure->drm_edid, timing);
4045 if (closure->preferred)
4046 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4049 * Detailed modes are limited to 10kHz pixel clock resolution,
4050 * so fix up anything that looks like CEA/HDMI mode, but the clock
4051 * is just slightly off.
4053 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4055 drm_mode_probed_add(closure->connector, newmode);
4057 closure->preferred = false;
4061 * add_detailed_modes - Add modes from detailed timings
4062 * @connector: attached connector
4063 * @drm_edid: EDID block to scan
4065 static int add_detailed_modes(struct drm_connector *connector,
4066 const struct drm_edid *drm_edid)
4068 struct detailed_mode_closure closure = {
4069 .connector = connector,
4070 .drm_edid = drm_edid,
4073 if (drm_edid->edid->revision >= 4)
4074 closure.preferred = true; /* first detailed timing is always preferred */
4077 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4079 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4081 return closure.modes;
4084 /* CTA-861-H Table 60 - CTA Tag Codes */
4085 #define CTA_DB_AUDIO 1
4086 #define CTA_DB_VIDEO 2
4087 #define CTA_DB_VENDOR 3
4088 #define CTA_DB_SPEAKER 4
4089 #define CTA_DB_EXTENDED_TAG 7
4091 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
4092 #define CTA_EXT_DB_VIDEO_CAP 0
4093 #define CTA_EXT_DB_VENDOR 1
4094 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
4095 #define CTA_EXT_DB_420_VIDEO_DATA 14
4096 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4097 #define CTA_EXT_DB_HF_EEODB 0x78
4098 #define CTA_EXT_DB_HF_SCDB 0x79
4100 #define EDID_BASIC_AUDIO (1 << 6)
4101 #define EDID_CEA_YCRCB444 (1 << 5)
4102 #define EDID_CEA_YCRCB422 (1 << 4)
4103 #define EDID_CEA_VCDB_QS (1 << 6)
4106 * Search EDID for CEA extension block.
4108 * FIXME: Prefer not returning pointers to raw EDID data.
4110 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4111 int ext_id, int *ext_index)
4113 const u8 *edid_ext = NULL;
4116 /* No EDID or EDID extensions */
4117 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4120 /* Find CEA extension */
4121 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4122 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4123 if (edid_block_tag(edid_ext) == ext_id)
4127 if (i >= drm_edid_extension_block_count(drm_edid))
4135 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4136 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4138 const struct displayid_block *block;
4139 struct displayid_iter iter;
4143 /* Look for a top level CEA extension block */
4144 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4147 /* CEA blocks can also be found embedded in a DisplayID block */
4148 displayid_iter_edid_begin(drm_edid, &iter);
4149 displayid_iter_for_each(block, &iter) {
4150 if (block->tag == DATA_BLOCK_CTA) {
4155 displayid_iter_end(&iter);
4160 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4162 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4163 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4165 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4166 return &edid_cea_modes_1[vic - 1];
4167 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4168 return &edid_cea_modes_193[vic - 193];
4172 static u8 cea_num_vics(void)
4174 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4177 static u8 cea_next_vic(u8 vic)
4179 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4185 * Calculate the alternate clock for the CEA mode
4186 * (60Hz vs. 59.94Hz etc.)
4189 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4191 unsigned int clock = cea_mode->clock;
4193 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4197 * edid_cea_modes contains the 59.94Hz
4198 * variant for 240 and 480 line modes,
4199 * and the 60Hz variant otherwise.
4201 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4202 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4204 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4210 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4213 * For certain VICs the spec allows the vertical
4214 * front porch to vary by one or two lines.
4216 * cea_modes[] stores the variant with the shortest
4217 * vertical front porch. We can adjust the mode to
4218 * get the other variants by simply increasing the
4219 * vertical front porch length.
4221 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4222 cea_mode_for_vic(9)->vtotal != 262 ||
4223 cea_mode_for_vic(12)->vtotal != 262 ||
4224 cea_mode_for_vic(13)->vtotal != 262 ||
4225 cea_mode_for_vic(23)->vtotal != 312 ||
4226 cea_mode_for_vic(24)->vtotal != 312 ||
4227 cea_mode_for_vic(27)->vtotal != 312 ||
4228 cea_mode_for_vic(28)->vtotal != 312);
4230 if (((vic == 8 || vic == 9 ||
4231 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4232 ((vic == 23 || vic == 24 ||
4233 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4234 mode->vsync_start++;
4244 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4245 unsigned int clock_tolerance)
4247 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4250 if (!to_match->clock)
4253 if (to_match->picture_aspect_ratio)
4254 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4256 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4257 struct drm_display_mode cea_mode;
4258 unsigned int clock1, clock2;
4260 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4262 /* Check both 60Hz and 59.94Hz */
4263 clock1 = cea_mode.clock;
4264 clock2 = cea_mode_alternate_clock(&cea_mode);
4266 if (abs(to_match->clock - clock1) > clock_tolerance &&
4267 abs(to_match->clock - clock2) > clock_tolerance)
4271 if (drm_mode_match(to_match, &cea_mode, match_flags))
4273 } while (cea_mode_alternate_timings(vic, &cea_mode));
4280 * drm_match_cea_mode - look for a CEA mode matching given mode
4281 * @to_match: display mode
4283 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4286 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4288 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4291 if (!to_match->clock)
4294 if (to_match->picture_aspect_ratio)
4295 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4297 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4298 struct drm_display_mode cea_mode;
4299 unsigned int clock1, clock2;
4301 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4303 /* Check both 60Hz and 59.94Hz */
4304 clock1 = cea_mode.clock;
4305 clock2 = cea_mode_alternate_clock(&cea_mode);
4307 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4308 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4312 if (drm_mode_match(to_match, &cea_mode, match_flags))
4314 } while (cea_mode_alternate_timings(vic, &cea_mode));
4319 EXPORT_SYMBOL(drm_match_cea_mode);
4321 static bool drm_valid_cea_vic(u8 vic)
4323 return cea_mode_for_vic(vic) != NULL;
4326 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4328 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4331 return mode->picture_aspect_ratio;
4333 return HDMI_PICTURE_ASPECT_NONE;
4336 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4338 return edid_4k_modes[video_code].picture_aspect_ratio;
4342 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4346 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4348 return cea_mode_alternate_clock(hdmi_mode);
4351 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4352 unsigned int clock_tolerance)
4354 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4357 if (!to_match->clock)
4360 if (to_match->picture_aspect_ratio)
4361 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4363 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4364 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4365 unsigned int clock1, clock2;
4367 /* Make sure to also match alternate clocks */
4368 clock1 = hdmi_mode->clock;
4369 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4371 if (abs(to_match->clock - clock1) > clock_tolerance &&
4372 abs(to_match->clock - clock2) > clock_tolerance)
4375 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4383 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4384 * @to_match: display mode
4386 * An HDMI mode is one defined in the HDMI vendor specific block.
4388 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4390 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4392 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4395 if (!to_match->clock)
4398 if (to_match->picture_aspect_ratio)
4399 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4401 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4402 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4403 unsigned int clock1, clock2;
4405 /* Make sure to also match alternate clocks */
4406 clock1 = hdmi_mode->clock;
4407 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4409 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4410 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4411 drm_mode_match(to_match, hdmi_mode, match_flags))
4417 static bool drm_valid_hdmi_vic(u8 vic)
4419 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4422 static int add_alternate_cea_modes(struct drm_connector *connector,
4423 const struct drm_edid *drm_edid)
4425 struct drm_device *dev = connector->dev;
4426 struct drm_display_mode *mode, *tmp;
4430 /* Don't add CTA modes if the CTA extension block is missing */
4431 if (!drm_edid_has_cta_extension(drm_edid))
4435 * Go through all probed modes and create a new mode
4436 * with the alternate clock for certain CEA modes.
4438 list_for_each_entry(mode, &connector->probed_modes, head) {
4439 const struct drm_display_mode *cea_mode = NULL;
4440 struct drm_display_mode *newmode;
4441 u8 vic = drm_match_cea_mode(mode);
4442 unsigned int clock1, clock2;
4444 if (drm_valid_cea_vic(vic)) {
4445 cea_mode = cea_mode_for_vic(vic);
4446 clock2 = cea_mode_alternate_clock(cea_mode);
4448 vic = drm_match_hdmi_mode(mode);
4449 if (drm_valid_hdmi_vic(vic)) {
4450 cea_mode = &edid_4k_modes[vic];
4451 clock2 = hdmi_mode_alternate_clock(cea_mode);
4458 clock1 = cea_mode->clock;
4460 if (clock1 == clock2)
4463 if (mode->clock != clock1 && mode->clock != clock2)
4466 newmode = drm_mode_duplicate(dev, cea_mode);
4470 /* Carry over the stereo flags */
4471 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4474 * The current mode could be either variant. Make
4475 * sure to pick the "other" clock for the new mode.
4477 if (mode->clock != clock1)
4478 newmode->clock = clock1;
4480 newmode->clock = clock2;
4482 list_add_tail(&newmode->head, &list);
4485 list_for_each_entry_safe(mode, tmp, &list, head) {
4486 list_del(&mode->head);
4487 drm_mode_probed_add(connector, mode);
4494 static u8 svd_to_vic(u8 svd)
4496 /* 0-6 bit vic, 7th bit native mode indicator */
4497 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4504 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4505 * the EDID, or NULL on errors.
4507 static struct drm_display_mode *
4508 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4510 const struct drm_display_info *info = &connector->display_info;
4511 struct drm_device *dev = connector->dev;
4513 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4516 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4520 * do_y420vdb_modes - Parse YCBCR 420 only modes
4521 * @connector: connector corresponding to the HDMI sink
4522 * @svds: start of the data block of CEA YCBCR 420 VDB
4523 * @len: length of the CEA YCBCR 420 VDB
4525 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4526 * which contains modes which can be supported in YCBCR 420
4527 * output format only.
4529 static int do_y420vdb_modes(struct drm_connector *connector,
4530 const u8 *svds, u8 svds_len)
4532 struct drm_device *dev = connector->dev;
4535 for (i = 0; i < svds_len; i++) {
4536 u8 vic = svd_to_vic(svds[i]);
4537 struct drm_display_mode *newmode;
4539 if (!drm_valid_cea_vic(vic))
4542 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4545 drm_mode_probed_add(connector, newmode);
4553 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4555 * @video_code: CEA VIC of the mode
4557 * Creates a new mode matching the specified CEA VIC.
4559 * Returns: A new drm_display_mode on success or NULL on failure
4561 struct drm_display_mode *
4562 drm_display_mode_from_cea_vic(struct drm_device *dev,
4565 const struct drm_display_mode *cea_mode;
4566 struct drm_display_mode *newmode;
4568 cea_mode = cea_mode_for_vic(video_code);
4572 newmode = drm_mode_duplicate(dev, cea_mode);
4578 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4580 /* Add modes based on VICs parsed in parse_cta_vdb() */
4581 static int add_cta_vdb_modes(struct drm_connector *connector)
4583 const struct drm_display_info *info = &connector->display_info;
4589 for (i = 0; i < info->vics_len; i++) {
4590 struct drm_display_mode *mode;
4592 mode = drm_display_mode_from_vic_index(connector, i);
4594 drm_mode_probed_add(connector, mode);
4602 struct stereo_mandatory_mode {
4603 int width, height, vrefresh;
4607 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4608 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4609 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4611 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4613 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4614 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4615 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4616 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4617 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4621 stereo_match_mandatory(const struct drm_display_mode *mode,
4622 const struct stereo_mandatory_mode *stereo_mode)
4624 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4626 return mode->hdisplay == stereo_mode->width &&
4627 mode->vdisplay == stereo_mode->height &&
4628 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4629 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4632 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4634 struct drm_device *dev = connector->dev;
4635 const struct drm_display_mode *mode;
4636 struct list_head stereo_modes;
4639 INIT_LIST_HEAD(&stereo_modes);
4641 list_for_each_entry(mode, &connector->probed_modes, head) {
4642 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4643 const struct stereo_mandatory_mode *mandatory;
4644 struct drm_display_mode *new_mode;
4646 if (!stereo_match_mandatory(mode,
4647 &stereo_mandatory_modes[i]))
4650 mandatory = &stereo_mandatory_modes[i];
4651 new_mode = drm_mode_duplicate(dev, mode);
4655 new_mode->flags |= mandatory->flags;
4656 list_add_tail(&new_mode->head, &stereo_modes);
4661 list_splice_tail(&stereo_modes, &connector->probed_modes);
4666 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4668 struct drm_device *dev = connector->dev;
4669 struct drm_display_mode *newmode;
4671 if (!drm_valid_hdmi_vic(vic)) {
4672 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4673 connector->base.id, connector->name, vic);
4677 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4681 drm_mode_probed_add(connector, newmode);
4686 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4689 struct drm_display_mode *newmode;
4692 if (structure & (1 << 0)) {
4693 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4695 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4696 drm_mode_probed_add(connector, newmode);
4700 if (structure & (1 << 6)) {
4701 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4703 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4704 drm_mode_probed_add(connector, newmode);
4708 if (structure & (1 << 8)) {
4709 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4711 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4712 drm_mode_probed_add(connector, newmode);
4720 static bool hdmi_vsdb_latency_present(const u8 *db)
4722 return db[8] & BIT(7);
4725 static bool hdmi_vsdb_i_latency_present(const u8 *db)
4727 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4730 static int hdmi_vsdb_latency_length(const u8 *db)
4732 if (hdmi_vsdb_i_latency_present(db))
4734 else if (hdmi_vsdb_latency_present(db))
4741 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4742 * @connector: connector corresponding to the HDMI sink
4743 * @db: start of the CEA vendor specific block
4744 * @len: length of the CEA block payload, ie. one can access up to db[len]
4746 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4747 * also adds the stereo 3d modes when applicable.
4750 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4752 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4753 u8 vic_len, hdmi_3d_len = 0;
4760 /* no HDMI_Video_Present */
4761 if (!(db[8] & (1 << 5)))
4764 offset += hdmi_vsdb_latency_length(db);
4766 /* the declared length is not long enough for the 2 first bytes
4767 * of additional video format capabilities */
4768 if (len < (8 + offset + 2))
4773 if (db[8 + offset] & (1 << 7)) {
4774 modes += add_hdmi_mandatory_stereo_modes(connector);
4776 /* 3D_Multi_present */
4777 multi_present = (db[8 + offset] & 0x60) >> 5;
4781 vic_len = db[8 + offset] >> 5;
4782 hdmi_3d_len = db[8 + offset] & 0x1f;
4784 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4787 vic = db[9 + offset + i];
4788 modes += add_hdmi_mode(connector, vic);
4790 offset += 1 + vic_len;
4792 if (multi_present == 1)
4794 else if (multi_present == 2)
4799 if (len < (8 + offset + hdmi_3d_len - 1))
4802 if (hdmi_3d_len < multi_len)
4805 if (multi_present == 1 || multi_present == 2) {
4806 /* 3D_Structure_ALL */
4807 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4809 /* check if 3D_MASK is present */
4810 if (multi_present == 2)
4811 mask = (db[10 + offset] << 8) | db[11 + offset];
4815 for (i = 0; i < 16; i++) {
4816 if (mask & (1 << i))
4817 modes += add_3d_struct_modes(connector,
4822 offset += multi_len;
4824 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4826 struct drm_display_mode *newmode = NULL;
4827 unsigned int newflag = 0;
4828 bool detail_present;
4830 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4832 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4835 /* 2D_VIC_order_X */
4836 vic_index = db[8 + offset + i] >> 4;
4838 /* 3D_Structure_X */
4839 switch (db[8 + offset + i] & 0x0f) {
4841 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4844 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4848 if ((db[9 + offset + i] >> 4) == 1)
4849 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4854 newmode = drm_display_mode_from_vic_index(connector,
4858 newmode->flags |= newflag;
4859 drm_mode_probed_add(connector, newmode);
4873 cea_revision(const u8 *cea)
4876 * FIXME is this correct for the DispID variant?
4877 * The DispID spec doesn't really specify whether
4878 * this is the revision of the CEA extension or
4879 * the DispID CEA data block. And the only value
4880 * given as an example is 0.
4886 * CTA Data Block iterator.
4888 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4891 * struct cea_db *db:
4892 * struct cea_db_iter iter;
4894 * cea_db_iter_edid_begin(edid, &iter);
4895 * cea_db_iter_for_each(db, &iter) {
4896 * // do stuff with db
4898 * cea_db_iter_end(&iter);
4900 struct cea_db_iter {
4901 struct drm_edid_iter edid_iter;
4902 struct displayid_iter displayid_iter;
4904 /* Current Data Block Collection. */
4905 const u8 *collection;
4907 /* Current Data Block index in current collection. */
4910 /* End index in current collection. */
4914 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4920 static int cea_db_tag(const struct cea_db *db)
4922 return db->tag_length >> 5;
4925 static int cea_db_payload_len(const void *_db)
4927 /* FIXME: Transition to passing struct cea_db * everywhere. */
4928 const struct cea_db *db = _db;
4930 return db->tag_length & 0x1f;
4933 static const void *cea_db_data(const struct cea_db *db)
4938 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4940 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4941 cea_db_payload_len(db) >= 1 &&
4945 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4947 const u8 *data = cea_db_data(db);
4949 return cea_db_tag(db) == CTA_DB_VENDOR &&
4950 cea_db_payload_len(db) >= 3 &&
4951 oui(data[2], data[1], data[0]) == vendor_oui;
4954 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4955 struct cea_db_iter *iter)
4957 memset(iter, 0, sizeof(*iter));
4959 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4960 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4963 static const struct cea_db *
4964 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4966 const struct cea_db *db;
4968 if (!iter->collection)
4971 db = (const struct cea_db *)&iter->collection[iter->index];
4973 if (iter->index + sizeof(*db) <= iter->end &&
4974 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4982 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4984 static int cea_db_collection_size(const u8 *cta)
4988 if (d < 4 || d > 127)
4996 * - VESA E-EDID v1.4
4997 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4999 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5003 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5006 /* Only support CTA Extension revision 3+ */
5007 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5010 size = cea_db_collection_size(ext);
5015 iter->end = iter->index + size;
5025 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5026 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5028 * Note that the above do not specify any connection between DisplayID Data
5029 * Block revision and CTA Extension versions.
5031 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5033 const struct displayid_block *block;
5035 displayid_iter_for_each(block, &iter->displayid_iter) {
5036 if (block->tag != DATA_BLOCK_CTA)
5040 * The displayid iterator has already verified the block bounds
5041 * in displayid_iter_block().
5043 iter->index = sizeof(*block);
5044 iter->end = iter->index + block->num_bytes;
5052 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5054 const struct cea_db *db;
5056 if (iter->collection) {
5057 /* Current collection should always be valid. */
5058 db = __cea_db_iter_current_block(iter);
5060 iter->collection = NULL;
5064 /* Next block in CTA Data Block Collection */
5065 iter->index += sizeof(*db) + cea_db_payload_len(db);
5067 db = __cea_db_iter_current_block(iter);
5074 * Find the next CTA Data Block Collection. First iterate all
5075 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5077 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5078 * Extension, it's recommended that DisplayID extensions are
5079 * exposed after all of the CTA Extensions.
5081 iter->collection = __cea_db_iter_edid_next(iter);
5082 if (!iter->collection)
5083 iter->collection = __cea_db_iter_displayid_next(iter);
5085 if (!iter->collection)
5088 db = __cea_db_iter_current_block(iter);
5094 #define cea_db_iter_for_each(__db, __iter) \
5095 while (((__db) = __cea_db_iter_next(__iter)))
5097 static void cea_db_iter_end(struct cea_db_iter *iter)
5099 displayid_iter_end(&iter->displayid_iter);
5100 drm_edid_iter_end(&iter->edid_iter);
5102 memset(iter, 0, sizeof(*iter));
5105 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5107 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5108 cea_db_payload_len(db) >= 5;
5111 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5113 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5114 cea_db_payload_len(db) >= 7;
5117 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5119 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5120 cea_db_payload_len(db) >= 2;
5123 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5125 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5126 cea_db_payload_len(db) == 21;
5129 static bool cea_db_is_vcdb(const struct cea_db *db)
5131 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5132 cea_db_payload_len(db) == 2;
5135 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5137 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5138 cea_db_payload_len(db) >= 7;
5141 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5143 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5146 static bool cea_db_is_y420vdb(const struct cea_db *db)
5148 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5151 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5153 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5154 cea_db_payload_len(db) >= 3;
5158 * Get the HF-EEODB override extension block count from EDID.
5160 * The passed in EDID may be partially read, as long as it has at least two
5161 * blocks (base block and one extension block) if EDID extension count is > 0.
5163 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5164 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5165 * iterators instead.
5168 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5170 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5174 /* No extensions according to base block, no HF-EEODB. */
5175 if (!edid_extension_block_count(edid))
5178 /* HF-EEODB is always in the first EDID extension block only */
5179 cta = edid_extension_block_data(edid, 0);
5180 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5183 /* Need to have the data block collection, and at least 3 bytes. */
5184 if (cea_db_collection_size(cta) < 3)
5188 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5189 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5190 * through 6 of Block 1 of the E-EDID.
5192 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5199 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5201 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5202 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5203 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5204 * support YCBCR420 output too.
5206 static void parse_cta_y420cmdb(struct drm_connector *connector,
5207 const struct cea_db *db, u64 *y420cmdb_map)
5209 struct drm_display_info *info = &connector->display_info;
5210 int i, map_len = cea_db_payload_len(db) - 1;
5211 const u8 *data = cea_db_data(db) + 1;
5215 /* All CEA modes support ycbcr420 sampling also.*/
5221 * This map indicates which of the existing CEA block modes
5222 * from VDB can support YCBCR420 output too. So if bit=0 is
5223 * set, first mode from VDB can support YCBCR420 output too.
5224 * We will parse and keep this map, before parsing VDB itself
5225 * to avoid going through the same block again and again.
5227 * Spec is not clear about max possible size of this block.
5228 * Clamping max bitmap block size at 8 bytes. Every byte can
5229 * address 8 CEA modes, in this way this map can address
5230 * 8*8 = first 64 SVDs.
5232 if (WARN_ON_ONCE(map_len > 8))
5235 for (i = 0; i < map_len; i++)
5236 map |= (u64)data[i] << (8 * i);
5240 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5242 *y420cmdb_map = map;
5245 static int add_cea_modes(struct drm_connector *connector,
5246 const struct drm_edid *drm_edid)
5248 const struct cea_db *db;
5249 struct cea_db_iter iter;
5252 /* CTA VDB block VICs parsed earlier */
5253 modes = add_cta_vdb_modes(connector);
5255 cea_db_iter_edid_begin(drm_edid, &iter);
5256 cea_db_iter_for_each(db, &iter) {
5257 if (cea_db_is_hdmi_vsdb(db)) {
5258 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5259 cea_db_payload_len(db));
5260 } else if (cea_db_is_y420vdb(db)) {
5261 const u8 *vdb420 = cea_db_data(db) + 1;
5263 /* Add 4:2:0(only) modes present in EDID */
5264 modes += do_y420vdb_modes(connector, vdb420,
5265 cea_db_payload_len(db) - 1);
5268 cea_db_iter_end(&iter);
5273 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5274 struct drm_display_mode *mode)
5276 const struct drm_display_mode *cea_mode;
5277 int clock1, clock2, clock;
5282 * allow 5kHz clock difference either way to account for
5283 * the 10kHz clock resolution limit of detailed timings.
5285 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5286 if (drm_valid_cea_vic(vic)) {
5288 cea_mode = cea_mode_for_vic(vic);
5289 clock1 = cea_mode->clock;
5290 clock2 = cea_mode_alternate_clock(cea_mode);
5292 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5293 if (drm_valid_hdmi_vic(vic)) {
5295 cea_mode = &edid_4k_modes[vic];
5296 clock1 = cea_mode->clock;
5297 clock2 = hdmi_mode_alternate_clock(cea_mode);
5303 /* pick whichever is closest */
5304 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5309 if (mode->clock == clock)
5312 drm_dbg_kms(connector->dev,
5313 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5314 connector->base.id, connector->name,
5315 type, vic, mode->clock, clock);
5316 mode->clock = clock;
5319 static void drm_calculate_luminance_range(struct drm_connector *connector)
5321 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5322 struct drm_luminance_range_info *luminance_range =
5323 &connector->display_info.luminance_range;
5324 static const u8 pre_computed_values[] = {
5325 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5326 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5328 u32 max_avg, min_cll, max, min, q, r;
5330 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5333 max_avg = hdr_metadata->max_fall;
5334 min_cll = hdr_metadata->min_cll;
5337 * From the specification (CTA-861-G), for calculating the maximum
5338 * luminance we need to use:
5339 * Luminance = 50*2**(CV/32)
5340 * Where CV is a one-byte value.
5341 * For calculating this expression we may need float point precision;
5342 * to avoid this complexity level, we take advantage that CV is divided
5343 * by a constant. From the Euclids division algorithm, we know that CV
5344 * can be written as: CV = 32*q + r. Next, we replace CV in the
5345 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5346 * need to pre-compute the value of r/32. For pre-computing the values
5347 * We just used the following Ruby line:
5348 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5349 * The results of the above expressions can be verified at
5350 * pre_computed_values.
5354 max = (1 << q) * pre_computed_values[r];
5356 /* min luminance: maxLum * (CV/255)^2 / 100 */
5357 q = DIV_ROUND_CLOSEST(min_cll, 255);
5358 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5360 luminance_range->min_luminance = min;
5361 luminance_range->max_luminance = max;
5364 static uint8_t eotf_supported(const u8 *edid_ext)
5366 return edid_ext[2] &
5367 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5368 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5369 BIT(HDMI_EOTF_SMPTE_ST2084) |
5370 BIT(HDMI_EOTF_BT_2100_HLG));
5373 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5375 return edid_ext[3] &
5376 BIT(HDMI_STATIC_METADATA_TYPE1);
5380 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5384 len = cea_db_payload_len(db);
5386 connector->hdr_sink_metadata.hdmi_type1.eotf =
5388 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5389 hdr_metadata_type(db);
5392 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5394 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5396 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5398 /* Calculate only when all values are available */
5399 drm_calculate_luminance_range(connector);
5403 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5405 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5407 u8 len = cea_db_payload_len(db);
5409 if (len >= 6 && (db[6] & (1 << 7)))
5410 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5412 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5413 connector->latency_present[0] = true;
5414 connector->video_latency[0] = db[9];
5415 connector->audio_latency[0] = db[10];
5418 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5419 connector->latency_present[1] = true;
5420 connector->video_latency[1] = db[11];
5421 connector->audio_latency[1] = db[12];
5424 drm_dbg_kms(connector->dev,
5425 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5426 connector->base.id, connector->name,
5427 connector->latency_present[0], connector->latency_present[1],
5428 connector->video_latency[0], connector->video_latency[1],
5429 connector->audio_latency[0], connector->audio_latency[1]);
5433 monitor_name(const struct detailed_timing *timing, void *data)
5435 const char **res = data;
5437 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5440 *res = timing->data.other_data.data.str.str;
5443 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5445 const char *edid_name = NULL;
5448 if (!drm_edid || !name)
5451 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5452 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5453 if (edid_name[mnl] == 0x0a)
5456 name[mnl] = edid_name[mnl];
5463 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5464 * @edid: monitor EDID information
5465 * @name: pointer to a character array to hold the name of the monitor
5466 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5469 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5471 int name_length = 0;
5478 struct drm_edid drm_edid = {
5480 .size = edid_size(edid),
5483 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5484 memcpy(name, buf, name_length);
5487 name[name_length] = '\0';
5489 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5491 static void clear_eld(struct drm_connector *connector)
5493 memset(connector->eld, 0, sizeof(connector->eld));
5495 connector->latency_present[0] = false;
5496 connector->latency_present[1] = false;
5497 connector->video_latency[0] = 0;
5498 connector->audio_latency[0] = 0;
5499 connector->video_latency[1] = 0;
5500 connector->audio_latency[1] = 0;
5504 * drm_edid_to_eld - build ELD from EDID
5505 * @connector: connector corresponding to the HDMI/DP sink
5506 * @drm_edid: EDID to parse
5508 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5509 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5511 static void drm_edid_to_eld(struct drm_connector *connector,
5512 const struct drm_edid *drm_edid)
5514 const struct drm_display_info *info = &connector->display_info;
5515 const struct cea_db *db;
5516 struct cea_db_iter iter;
5517 uint8_t *eld = connector->eld;
5518 int total_sad_count = 0;
5524 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5525 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5526 connector->base.id, connector->name,
5527 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5529 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5530 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5532 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5534 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5535 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5536 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5537 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5539 cea_db_iter_edid_begin(drm_edid, &iter);
5540 cea_db_iter_for_each(db, &iter) {
5541 const u8 *data = cea_db_data(db);
5542 int len = cea_db_payload_len(db);
5545 switch (cea_db_tag(db)) {
5547 /* Audio Data Block, contains SADs */
5548 sad_count = min(len / 3, 15 - total_sad_count);
5550 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5551 data, sad_count * 3);
5552 total_sad_count += sad_count;
5554 case CTA_DB_SPEAKER:
5555 /* Speaker Allocation Data Block */
5557 eld[DRM_ELD_SPEAKER] = data[0];
5560 /* HDMI Vendor-Specific Data Block */
5561 if (cea_db_is_hdmi_vsdb(db))
5562 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5568 cea_db_iter_end(&iter);
5570 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5572 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5573 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5574 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5576 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5578 eld[DRM_ELD_BASELINE_ELD_LEN] =
5579 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5581 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5582 connector->base.id, connector->name,
5583 drm_eld_size(eld), total_sad_count);
5586 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5587 struct cea_sad **sads)
5589 const struct cea_db *db;
5590 struct cea_db_iter iter;
5593 cea_db_iter_edid_begin(drm_edid, &iter);
5594 cea_db_iter_for_each(db, &iter) {
5595 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5598 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5599 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5602 for (j = 0; j < count; j++) {
5603 const u8 *sad = &db->data[j * 3];
5605 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5606 (*sads)[j].channels = sad[0] & 0x7;
5607 (*sads)[j].freq = sad[1] & 0x7F;
5608 (*sads)[j].byte2 = sad[2];
5613 cea_db_iter_end(&iter);
5615 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5621 * drm_edid_to_sad - extracts SADs from EDID
5622 * @edid: EDID to parse
5623 * @sads: pointer that will be set to the extracted SADs
5625 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5627 * Note: The returned pointer needs to be freed using kfree().
5629 * Return: The number of found SADs or negative number on error.
5631 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5633 struct drm_edid drm_edid;
5635 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5637 EXPORT_SYMBOL(drm_edid_to_sad);
5639 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5642 const struct cea_db *db;
5643 struct cea_db_iter iter;
5646 cea_db_iter_edid_begin(drm_edid, &iter);
5647 cea_db_iter_for_each(db, &iter) {
5648 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5649 cea_db_payload_len(db) == 3) {
5650 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5654 count = cea_db_payload_len(db);
5658 cea_db_iter_end(&iter);
5660 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5666 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5667 * @edid: EDID to parse
5668 * @sadb: pointer to the speaker block
5670 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5672 * Note: The returned pointer needs to be freed using kfree().
5674 * Return: The number of found Speaker Allocation Blocks or negative number on
5677 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5679 struct drm_edid drm_edid;
5681 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5684 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5687 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5688 * @connector: connector associated with the HDMI/DP sink
5689 * @mode: the display mode
5691 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5692 * the sink doesn't support audio or video.
5694 int drm_av_sync_delay(struct drm_connector *connector,
5695 const struct drm_display_mode *mode)
5697 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5700 if (!connector->latency_present[0])
5702 if (!connector->latency_present[1])
5705 a = connector->audio_latency[i];
5706 v = connector->video_latency[i];
5709 * HDMI/DP sink doesn't support audio or video?
5711 if (a == 255 || v == 255)
5715 * Convert raw EDID values to millisecond.
5716 * Treat unknown latency as 0ms.
5719 a = min(2 * (a - 1), 500);
5721 v = min(2 * (v - 1), 500);
5723 return max(v - a, 0);
5725 EXPORT_SYMBOL(drm_av_sync_delay);
5727 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5729 const struct cea_db *db;
5730 struct cea_db_iter iter;
5734 * Because HDMI identifier is in Vendor Specific Block,
5735 * search it from all data blocks of CEA extension.
5737 cea_db_iter_edid_begin(drm_edid, &iter);
5738 cea_db_iter_for_each(db, &iter) {
5739 if (cea_db_is_hdmi_vsdb(db)) {
5744 cea_db_iter_end(&iter);
5750 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5751 * @edid: monitor EDID information
5753 * Parse the CEA extension according to CEA-861-B.
5755 * Drivers that have added the modes parsed from EDID to drm_display_info
5756 * should use &drm_display_info.is_hdmi instead of calling this function.
5758 * Return: True if the monitor is HDMI, false if not or unknown.
5760 bool drm_detect_hdmi_monitor(const struct edid *edid)
5762 struct drm_edid drm_edid;
5764 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5766 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5768 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5770 struct drm_edid_iter edid_iter;
5771 const struct cea_db *db;
5772 struct cea_db_iter iter;
5774 bool has_audio = false;
5776 drm_edid_iter_begin(drm_edid, &edid_iter);
5777 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5778 if (edid_ext[0] == CEA_EXT) {
5779 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5784 drm_edid_iter_end(&edid_iter);
5787 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5791 cea_db_iter_edid_begin(drm_edid, &iter);
5792 cea_db_iter_for_each(db, &iter) {
5793 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5794 const u8 *data = cea_db_data(db);
5797 for (i = 0; i < cea_db_payload_len(db); i += 3)
5798 DRM_DEBUG_KMS("CEA audio format %d\n",
5799 (data[i] >> 3) & 0xf);
5804 cea_db_iter_end(&iter);
5811 * drm_detect_monitor_audio - check monitor audio capability
5812 * @edid: EDID block to scan
5814 * Monitor should have CEA extension block.
5815 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5816 * audio' only. If there is any audio extension block and supported
5817 * audio format, assume at least 'basic audio' support, even if 'basic
5818 * audio' is not defined in EDID.
5820 * Return: True if the monitor supports audio, false otherwise.
5822 bool drm_detect_monitor_audio(const struct edid *edid)
5824 struct drm_edid drm_edid;
5826 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5828 EXPORT_SYMBOL(drm_detect_monitor_audio);
5832 * drm_default_rgb_quant_range - default RGB quantization range
5833 * @mode: display mode
5835 * Determine the default RGB quantization range for the mode,
5836 * as specified in CEA-861.
5838 * Return: The default RGB quantization range for the mode
5840 enum hdmi_quantization_range
5841 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5843 /* All CEA modes other than VIC 1 use limited quantization range. */
5844 return drm_match_cea_mode(mode) > 1 ?
5845 HDMI_QUANTIZATION_RANGE_LIMITED :
5846 HDMI_QUANTIZATION_RANGE_FULL;
5848 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5850 /* CTA-861 Video Data Block (CTA VDB) */
5851 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5853 struct drm_display_info *info = &connector->display_info;
5854 int i, vic_index, len = cea_db_payload_len(db);
5855 const u8 *svds = cea_db_data(db);
5861 /* Gracefully handle multiple VDBs, however unlikely that is */
5862 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5866 vic_index = info->vics_len;
5867 info->vics_len += len;
5870 for (i = 0; i < len; i++) {
5871 u8 vic = svd_to_vic(svds[i]);
5873 if (!drm_valid_cea_vic(vic))
5876 info->vics[vic_index++] = vic;
5881 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5883 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5884 * using the VICs themselves.
5886 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5888 struct drm_display_info *info = &connector->display_info;
5889 struct drm_hdmi_info *hdmi = &info->hdmi;
5890 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5892 for (i = 0; i < len; i++) {
5893 u8 vic = info->vics[i];
5895 if (vic && y420cmdb_map & BIT_ULL(i))
5896 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5900 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5902 const struct drm_display_info *info = &connector->display_info;
5905 if (!vic || !info->vics)
5908 for (i = 0; i < info->vics_len; i++) {
5909 if (info->vics[i] == vic)
5916 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5917 static void parse_cta_y420vdb(struct drm_connector *connector,
5918 const struct cea_db *db)
5920 struct drm_display_info *info = &connector->display_info;
5921 struct drm_hdmi_info *hdmi = &info->hdmi;
5922 const u8 *svds = cea_db_data(db) + 1;
5925 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5926 u8 vic = svd_to_vic(svds[i]);
5928 if (!drm_valid_cea_vic(vic))
5931 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5932 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5936 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5938 struct drm_display_info *info = &connector->display_info;
5940 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5941 connector->base.id, connector->name, db[2]);
5943 if (db[2] & EDID_CEA_VCDB_QS)
5944 info->rgb_quant_range_selectable = true;
5948 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5950 switch (max_frl_rate) {
5953 *max_rate_per_lane = 3;
5957 *max_rate_per_lane = 6;
5961 *max_rate_per_lane = 6;
5965 *max_rate_per_lane = 8;
5969 *max_rate_per_lane = 10;
5973 *max_rate_per_lane = 12;
5978 *max_rate_per_lane = 0;
5982 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5986 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5988 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5989 hdmi->y420_dc_modes = dc_mask;
5992 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
5995 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5997 if (!hdmi_dsc->v_1p2)
6000 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6001 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6003 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6004 hdmi_dsc->bpc_supported = 16;
6005 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6006 hdmi_dsc->bpc_supported = 12;
6007 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6008 hdmi_dsc->bpc_supported = 10;
6010 /* Supports min 8 BPC if DSC 1.2 is supported*/
6011 hdmi_dsc->bpc_supported = 8;
6013 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6015 u8 dsc_max_frl_rate;
6017 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6018 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6019 &hdmi_dsc->max_frl_rate_per_lane);
6021 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6023 switch (dsc_max_slices) {
6025 hdmi_dsc->max_slices = 1;
6026 hdmi_dsc->clk_per_slice = 340;
6029 hdmi_dsc->max_slices = 2;
6030 hdmi_dsc->clk_per_slice = 340;
6033 hdmi_dsc->max_slices = 4;
6034 hdmi_dsc->clk_per_slice = 340;
6037 hdmi_dsc->max_slices = 8;
6038 hdmi_dsc->clk_per_slice = 340;
6041 hdmi_dsc->max_slices = 8;
6042 hdmi_dsc->clk_per_slice = 400;
6045 hdmi_dsc->max_slices = 12;
6046 hdmi_dsc->clk_per_slice = 400;
6049 hdmi_dsc->max_slices = 16;
6050 hdmi_dsc->clk_per_slice = 400;
6054 hdmi_dsc->max_slices = 0;
6055 hdmi_dsc->clk_per_slice = 0;
6059 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6060 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6063 /* Sink Capability Data Structure */
6064 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6067 struct drm_display_info *info = &connector->display_info;
6068 struct drm_hdmi_info *hdmi = &info->hdmi;
6069 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6070 int max_tmds_clock = 0;
6071 u8 max_frl_rate = 0;
6072 bool dsc_support = false;
6074 info->has_hdmi_infoframe = true;
6076 if (hf_scds[6] & 0x80) {
6077 hdmi->scdc.supported = true;
6078 if (hf_scds[6] & 0x40)
6079 hdmi->scdc.read_request = true;
6083 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6084 * And as per the spec, three factors confirm this:
6085 * * Availability of a HF-VSDB block in EDID (check)
6086 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6087 * * SCDC support available (let's check)
6088 * Lets check it out.
6092 struct drm_scdc *scdc = &hdmi->scdc;
6094 /* max clock is 5000 KHz times block value */
6095 max_tmds_clock = hf_scds[5] * 5000;
6097 if (max_tmds_clock > 340000) {
6098 info->max_tmds_clock = max_tmds_clock;
6101 if (scdc->supported) {
6102 scdc->scrambling.supported = true;
6104 /* Few sinks support scrambling for clocks < 340M */
6105 if ((hf_scds[6] & 0x8))
6106 scdc->scrambling.low_rates = true;
6111 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6112 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6113 &hdmi->max_frl_rate_per_lane);
6116 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6118 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6119 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6123 drm_dbg_kms(connector->dev,
6124 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6125 connector->base.id, connector->name,
6126 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6129 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6132 struct drm_display_info *info = &connector->display_info;
6133 unsigned int dc_bpc = 0;
6135 /* HDMI supports at least 8 bpc */
6138 if (cea_db_payload_len(hdmi) < 6)
6141 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6143 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6144 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6145 connector->base.id, connector->name);
6148 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6150 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6151 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6152 connector->base.id, connector->name);
6155 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6157 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6158 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6159 connector->base.id, connector->name);
6163 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6164 connector->base.id, connector->name);
6168 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6169 connector->base.id, connector->name, dc_bpc);
6172 /* YCRCB444 is optional according to spec. */
6173 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6174 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6175 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6176 connector->base.id, connector->name);
6180 * Spec says that if any deep color mode is supported at all,
6181 * then deep color 36 bit must be supported.
6183 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6184 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6185 connector->base.id, connector->name);
6189 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6191 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6193 struct drm_display_info *info = &connector->display_info;
6194 u8 len = cea_db_payload_len(db);
6196 info->is_hdmi = true;
6199 info->dvi_dual = db[6] & 1;
6201 info->max_tmds_clock = db[7] * 5000;
6204 * Try to infer whether the sink supports HDMI infoframes.
6206 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6207 * supports infoframes if HDMI_Video_present is set.
6209 if (len >= 8 && db[8] & BIT(5))
6210 info->has_hdmi_infoframe = true;
6212 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6213 connector->base.id, connector->name,
6214 info->dvi_dual, info->max_tmds_clock);
6216 drm_parse_hdmi_deep_color_info(connector, db);
6220 * See EDID extension for head-mounted and specialized monitors, specified at:
6221 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6223 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6226 struct drm_display_info *info = &connector->display_info;
6228 bool desktop_usage = db[5] & BIT(6);
6230 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6231 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6232 info->non_desktop = true;
6234 drm_dbg_kms(connector->dev,
6235 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6236 connector->base.id, connector->name, version, db[5]);
6239 static void drm_parse_cea_ext(struct drm_connector *connector,
6240 const struct drm_edid *drm_edid)
6242 struct drm_display_info *info = &connector->display_info;
6243 struct drm_edid_iter edid_iter;
6244 const struct cea_db *db;
6245 struct cea_db_iter iter;
6247 u64 y420cmdb_map = 0;
6249 drm_edid_iter_begin(drm_edid, &edid_iter);
6250 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6251 if (edid_ext[0] != CEA_EXT)
6255 info->cea_rev = edid_ext[1];
6257 if (info->cea_rev != edid_ext[1])
6258 drm_dbg_kms(connector->dev,
6259 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6260 connector->base.id, connector->name,
6261 info->cea_rev, edid_ext[1]);
6263 /* The existence of a CTA extension should imply RGB support */
6264 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6265 if (edid_ext[3] & EDID_CEA_YCRCB444)
6266 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6267 if (edid_ext[3] & EDID_CEA_YCRCB422)
6268 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6269 if (edid_ext[3] & EDID_BASIC_AUDIO)
6270 info->has_audio = true;
6273 drm_edid_iter_end(&edid_iter);
6275 cea_db_iter_edid_begin(drm_edid, &iter);
6276 cea_db_iter_for_each(db, &iter) {
6277 /* FIXME: convert parsers to use struct cea_db */
6278 const u8 *data = (const u8 *)db;
6280 if (cea_db_is_hdmi_vsdb(db))
6281 drm_parse_hdmi_vsdb_video(connector, data);
6282 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6283 cea_db_is_hdmi_forum_scdb(db))
6284 drm_parse_hdmi_forum_scds(connector, data);
6285 else if (cea_db_is_microsoft_vsdb(db))
6286 drm_parse_microsoft_vsdb(connector, data);
6287 else if (cea_db_is_y420cmdb(db))
6288 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6289 else if (cea_db_is_y420vdb(db))
6290 parse_cta_y420vdb(connector, db);
6291 else if (cea_db_is_vcdb(db))
6292 drm_parse_vcdb(connector, data);
6293 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6294 drm_parse_hdr_metadata_block(connector, data);
6295 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6296 parse_cta_vdb(connector, db);
6297 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6298 info->has_audio = true;
6300 cea_db_iter_end(&iter);
6303 update_cta_y420cmdb(connector, y420cmdb_map);
6307 void get_monitor_range(const struct detailed_timing *timing, void *c)
6309 struct detailed_mode_closure *closure = c;
6310 struct drm_display_info *info = &closure->connector->display_info;
6311 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6312 const struct detailed_non_pixel *data = &timing->data.other_data;
6313 const struct detailed_data_monitor_range *range = &data->data.range;
6314 const struct edid *edid = closure->drm_edid->edid;
6316 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6320 * These limits are used to determine the VRR refresh
6321 * rate range. Only the "range limits only" variant
6322 * of the range descriptor seems to guarantee that
6323 * any and all timings are accepted by the sink, as
6324 * opposed to just timings conforming to the indicated
6325 * formula (GTF/GTF2/CVT). Thus other variants of the
6326 * range descriptor are not accepted here.
6328 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6331 monitor_range->min_vfreq = range->min_vfreq;
6332 monitor_range->max_vfreq = range->max_vfreq;
6334 if (edid->revision >= 4) {
6335 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6336 monitor_range->min_vfreq += 255;
6337 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6338 monitor_range->max_vfreq += 255;
6342 static void drm_get_monitor_range(struct drm_connector *connector,
6343 const struct drm_edid *drm_edid)
6345 const struct drm_display_info *info = &connector->display_info;
6346 struct detailed_mode_closure closure = {
6347 .connector = connector,
6348 .drm_edid = drm_edid,
6351 if (drm_edid->edid->revision < 4)
6354 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6357 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6359 drm_dbg_kms(connector->dev,
6360 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6361 connector->base.id, connector->name,
6362 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6365 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6366 const struct displayid_block *block)
6368 struct displayid_vesa_vendor_specific_block *vesa =
6369 (struct displayid_vesa_vendor_specific_block *)block;
6370 struct drm_display_info *info = &connector->display_info;
6372 if (block->num_bytes < 3) {
6373 drm_dbg_kms(connector->dev,
6374 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6375 connector->base.id, connector->name, block->num_bytes);
6379 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6382 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6383 drm_dbg_kms(connector->dev,
6384 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6385 connector->base.id, connector->name);
6389 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6391 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6392 connector->base.id, connector->name);
6395 info->mso_stream_count = 0;
6398 info->mso_stream_count = 2; /* 2 or 4 links */
6401 info->mso_stream_count = 4; /* 4 links */
6405 if (!info->mso_stream_count) {
6406 info->mso_pixel_overlap = 0;
6410 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6411 if (info->mso_pixel_overlap > 8) {
6412 drm_dbg_kms(connector->dev,
6413 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6414 connector->base.id, connector->name,
6415 info->mso_pixel_overlap);
6416 info->mso_pixel_overlap = 8;
6419 drm_dbg_kms(connector->dev,
6420 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6421 connector->base.id, connector->name,
6422 info->mso_stream_count, info->mso_pixel_overlap);
6425 static void drm_update_mso(struct drm_connector *connector,
6426 const struct drm_edid *drm_edid)
6428 const struct displayid_block *block;
6429 struct displayid_iter iter;
6431 displayid_iter_edid_begin(drm_edid, &iter);
6432 displayid_iter_for_each(block, &iter) {
6433 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6434 drm_parse_vesa_mso_data(connector, block);
6436 displayid_iter_end(&iter);
6439 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6440 * all of the values which would have been set from EDID
6442 static void drm_reset_display_info(struct drm_connector *connector)
6444 struct drm_display_info *info = &connector->display_info;
6447 info->height_mm = 0;
6450 info->color_formats = 0;
6452 info->max_tmds_clock = 0;
6453 info->dvi_dual = false;
6454 info->is_hdmi = false;
6455 info->has_audio = false;
6456 info->has_hdmi_infoframe = false;
6457 info->rgb_quant_range_selectable = false;
6458 memset(&info->hdmi, 0, sizeof(info->hdmi));
6460 info->edid_hdmi_rgb444_dc_modes = 0;
6461 info->edid_hdmi_ycbcr444_dc_modes = 0;
6463 info->non_desktop = 0;
6464 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6465 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6467 info->mso_stream_count = 0;
6468 info->mso_pixel_overlap = 0;
6469 info->max_dsc_bpp = 0;
6478 static void update_displayid_info(struct drm_connector *connector,
6479 const struct drm_edid *drm_edid)
6481 struct drm_display_info *info = &connector->display_info;
6482 const struct displayid_block *block;
6483 struct displayid_iter iter;
6485 displayid_iter_edid_begin(drm_edid, &iter);
6486 displayid_iter_for_each(block, &iter) {
6487 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6488 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6489 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6490 info->non_desktop = true;
6493 * We're only interested in the base section here, no need to
6498 displayid_iter_end(&iter);
6501 static void update_display_info(struct drm_connector *connector,
6502 const struct drm_edid *drm_edid)
6504 struct drm_display_info *info = &connector->display_info;
6505 const struct edid *edid;
6507 drm_reset_display_info(connector);
6508 clear_eld(connector);
6513 edid = drm_edid->edid;
6515 info->quirks = edid_get_quirks(drm_edid);
6517 info->width_mm = edid->width_cm * 10;
6518 info->height_mm = edid->height_cm * 10;
6520 drm_get_monitor_range(connector, drm_edid);
6522 if (edid->revision < 3)
6525 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6528 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6529 drm_parse_cea_ext(connector, drm_edid);
6531 update_displayid_info(connector, drm_edid);
6534 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6536 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6537 * tells us to assume 8 bpc color depth if the EDID doesn't have
6538 * extensions which tell otherwise.
6540 if (info->bpc == 0 && edid->revision == 3 &&
6541 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6543 drm_dbg_kms(connector->dev,
6544 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6545 connector->base.id, connector->name, info->bpc);
6548 /* Only defined for 1.4 with digital displays */
6549 if (edid->revision < 4)
6552 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6553 case DRM_EDID_DIGITAL_DEPTH_6:
6556 case DRM_EDID_DIGITAL_DEPTH_8:
6559 case DRM_EDID_DIGITAL_DEPTH_10:
6562 case DRM_EDID_DIGITAL_DEPTH_12:
6565 case DRM_EDID_DIGITAL_DEPTH_14:
6568 case DRM_EDID_DIGITAL_DEPTH_16:
6571 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6577 drm_dbg_kms(connector->dev,
6578 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6579 connector->base.id, connector->name, info->bpc);
6581 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6582 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6583 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6584 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6586 drm_update_mso(connector, drm_edid);
6589 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6590 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6591 connector->base.id, connector->name,
6592 info->non_desktop ? " (redundant quirk)" : "");
6593 info->non_desktop = true;
6596 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6597 info->max_dsc_bpp = 15;
6599 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6602 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6605 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6608 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6611 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6612 drm_edid_to_eld(connector, drm_edid);
6615 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6616 struct displayid_detailed_timings_1 *timings,
6619 struct drm_display_mode *mode;
6620 unsigned pixel_clock = (timings->pixel_clock[0] |
6621 (timings->pixel_clock[1] << 8) |
6622 (timings->pixel_clock[2] << 16)) + 1;
6623 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6624 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6625 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6626 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6627 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6628 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6629 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6630 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6631 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6632 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6634 mode = drm_mode_create(dev);
6638 /* resolution is kHz for type VII, and 10 kHz for type I */
6639 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6640 mode->hdisplay = hactive;
6641 mode->hsync_start = mode->hdisplay + hsync;
6642 mode->hsync_end = mode->hsync_start + hsync_width;
6643 mode->htotal = mode->hdisplay + hblank;
6645 mode->vdisplay = vactive;
6646 mode->vsync_start = mode->vdisplay + vsync;
6647 mode->vsync_end = mode->vsync_start + vsync_width;
6648 mode->vtotal = mode->vdisplay + vblank;
6651 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6652 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6653 mode->type = DRM_MODE_TYPE_DRIVER;
6655 if (timings->flags & 0x80)
6656 mode->type |= DRM_MODE_TYPE_PREFERRED;
6657 drm_mode_set_name(mode);
6662 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6663 const struct displayid_block *block)
6665 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6668 struct drm_display_mode *newmode;
6670 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6671 /* blocks must be multiple of 20 bytes length */
6672 if (block->num_bytes % 20)
6675 num_timings = block->num_bytes / 20;
6676 for (i = 0; i < num_timings; i++) {
6677 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6679 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6683 drm_mode_probed_add(connector, newmode);
6689 static int add_displayid_detailed_modes(struct drm_connector *connector,
6690 const struct drm_edid *drm_edid)
6692 const struct displayid_block *block;
6693 struct displayid_iter iter;
6696 displayid_iter_edid_begin(drm_edid, &iter);
6697 displayid_iter_for_each(block, &iter) {
6698 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6699 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6700 num_modes += add_displayid_detailed_1_modes(connector, block);
6702 displayid_iter_end(&iter);
6707 static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6708 const struct drm_edid *drm_edid)
6710 const struct drm_display_info *info = &connector->display_info;
6717 * EDID spec says modes should be preferred in this order:
6718 * - preferred detailed mode
6719 * - other detailed modes from base block
6720 * - detailed modes from extension blocks
6721 * - CVT 3-byte code modes
6722 * - standard timing codes
6723 * - established timing codes
6724 * - modes inferred from GTF or CVT range information
6726 * We get this pretty much right.
6728 * XXX order for additional mode types in extension blocks?
6730 num_modes += add_detailed_modes(connector, drm_edid);
6731 num_modes += add_cvt_modes(connector, drm_edid);
6732 num_modes += add_standard_modes(connector, drm_edid);
6733 num_modes += add_established_modes(connector, drm_edid);
6734 num_modes += add_cea_modes(connector, drm_edid);
6735 num_modes += add_alternate_cea_modes(connector, drm_edid);
6736 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6737 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6738 num_modes += add_inferred_modes(connector, drm_edid);
6740 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6741 edid_fixup_preferred(connector);
6746 static void _drm_update_tile_info(struct drm_connector *connector,
6747 const struct drm_edid *drm_edid);
6749 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6750 const struct drm_edid *drm_edid)
6752 struct drm_device *dev = connector->dev;
6755 if (connector->edid_blob_ptr) {
6756 const struct edid *old_edid = connector->edid_blob_ptr->data;
6759 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6760 connector->epoch_counter++;
6761 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6762 connector->base.id, connector->name,
6763 connector->epoch_counter);
6768 ret = drm_property_replace_global_blob(dev,
6769 &connector->edid_blob_ptr,
6770 drm_edid ? drm_edid->size : 0,
6771 drm_edid ? drm_edid->edid : NULL,
6773 dev->mode_config.edid_property);
6775 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6776 connector->base.id, connector->name, ret);
6780 ret = drm_object_property_set_value(&connector->base,
6781 dev->mode_config.non_desktop_property,
6782 connector->display_info.non_desktop);
6784 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6785 connector->base.id, connector->name, ret);
6789 ret = drm_connector_set_tile_property(connector);
6791 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6792 connector->base.id, connector->name, ret);
6801 * drm_edid_connector_update - Update connector information from EDID
6802 * @connector: Connector
6805 * Update the connector display info, ELD, HDR metadata, relevant properties,
6806 * etc. from the passed in EDID.
6808 * If EDID is NULL, reset the information.
6810 * Must be called before calling drm_edid_connector_add_modes().
6812 * Return: 0 on success, negative error on errors.
6814 int drm_edid_connector_update(struct drm_connector *connector,
6815 const struct drm_edid *drm_edid)
6817 update_display_info(connector, drm_edid);
6819 _drm_update_tile_info(connector, drm_edid);
6821 return _drm_edid_connector_property_update(connector, drm_edid);
6823 EXPORT_SYMBOL(drm_edid_connector_update);
6826 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6827 * @connector: Connector
6829 * Add the modes from the previously updated EDID property to the connector
6830 * probed modes list.
6832 * drm_edid_connector_update() must have been called before this to update the
6835 * Return: The number of modes added, or 0 if we couldn't find any.
6837 int drm_edid_connector_add_modes(struct drm_connector *connector)
6839 const struct drm_edid *drm_edid = NULL;
6842 if (connector->edid_blob_ptr)
6843 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6844 connector->edid_blob_ptr->length);
6846 count = _drm_edid_connector_add_modes(connector, drm_edid);
6848 drm_edid_free(drm_edid);
6852 EXPORT_SYMBOL(drm_edid_connector_add_modes);
6855 * drm_connector_update_edid_property - update the edid property of a connector
6856 * @connector: drm connector
6857 * @edid: new value of the edid property
6859 * This function creates a new blob modeset object and assigns its id to the
6860 * connector's edid property.
6861 * Since we also parse tile information from EDID's displayID block, we also
6862 * set the connector's tile property here. See drm_connector_set_tile_property()
6865 * This function is deprecated. Use drm_edid_connector_update() instead.
6868 * Zero on success, negative errno on failure.
6870 int drm_connector_update_edid_property(struct drm_connector *connector,
6871 const struct edid *edid)
6873 struct drm_edid drm_edid;
6875 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6877 EXPORT_SYMBOL(drm_connector_update_edid_property);
6880 * drm_add_edid_modes - add modes from EDID data, if available
6881 * @connector: connector we're probing
6884 * Add the specified modes to the connector's mode list. Also fills out the
6885 * &drm_display_info structure and ELD in @connector with any information which
6886 * can be derived from the edid.
6888 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6890 * Return: The number of modes added or 0 if we couldn't find any.
6892 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6894 struct drm_edid _drm_edid;
6895 const struct drm_edid *drm_edid;
6897 if (edid && !drm_edid_is_valid(edid)) {
6898 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6899 connector->base.id, connector->name);
6903 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6905 update_display_info(connector, drm_edid);
6907 return _drm_edid_connector_add_modes(connector, drm_edid);
6909 EXPORT_SYMBOL(drm_add_edid_modes);
6912 * drm_add_modes_noedid - add modes for the connectors without EDID
6913 * @connector: connector we're probing
6914 * @hdisplay: the horizontal display limit
6915 * @vdisplay: the vertical display limit
6917 * Add the specified modes to the connector's mode list. Only when the
6918 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6920 * Return: The number of modes added or 0 if we couldn't find any.
6922 int drm_add_modes_noedid(struct drm_connector *connector,
6923 int hdisplay, int vdisplay)
6925 int i, count, num_modes = 0;
6926 struct drm_display_mode *mode;
6927 struct drm_device *dev = connector->dev;
6929 count = ARRAY_SIZE(drm_dmt_modes);
6935 for (i = 0; i < count; i++) {
6936 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6938 if (hdisplay && vdisplay) {
6940 * Only when two are valid, they will be used to check
6941 * whether the mode should be added to the mode list of
6944 if (ptr->hdisplay > hdisplay ||
6945 ptr->vdisplay > vdisplay)
6948 if (drm_mode_vrefresh(ptr) > 61)
6950 mode = drm_mode_duplicate(dev, ptr);
6952 drm_mode_probed_add(connector, mode);
6958 EXPORT_SYMBOL(drm_add_modes_noedid);
6961 * drm_set_preferred_mode - Sets the preferred mode of a connector
6962 * @connector: connector whose mode list should be processed
6963 * @hpref: horizontal resolution of preferred mode
6964 * @vpref: vertical resolution of preferred mode
6966 * Marks a mode as preferred if it matches the resolution specified by @hpref
6969 void drm_set_preferred_mode(struct drm_connector *connector,
6970 int hpref, int vpref)
6972 struct drm_display_mode *mode;
6974 list_for_each_entry(mode, &connector->probed_modes, head) {
6975 if (mode->hdisplay == hpref &&
6976 mode->vdisplay == vpref)
6977 mode->type |= DRM_MODE_TYPE_PREFERRED;
6980 EXPORT_SYMBOL(drm_set_preferred_mode);
6982 static bool is_hdmi2_sink(const struct drm_connector *connector)
6985 * FIXME: sil-sii8620 doesn't have a connector around when
6986 * we need one, so we have to be prepared for a NULL connector.
6991 return connector->display_info.hdmi.scdc.supported ||
6992 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6995 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6996 const struct drm_display_mode *mode)
6998 bool has_hdmi_infoframe = connector ?
6999 connector->display_info.has_hdmi_infoframe : false;
7001 if (!has_hdmi_infoframe)
7004 /* No HDMI VIC when signalling 3D video format */
7005 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7008 return drm_match_hdmi_mode(mode);
7011 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7012 const struct drm_display_mode *mode)
7015 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7016 * we should send its VIC in vendor infoframes, else send the
7017 * VIC in AVI infoframes. Lets check if this mode is present in
7018 * HDMI 1.4b 4K modes
7020 if (drm_mode_hdmi_vic(connector, mode))
7023 return drm_match_cea_mode(mode);
7027 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7028 * conform to HDMI 1.4.
7030 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7031 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7033 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7036 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7038 if (!is_hdmi2_sink(connector) && vic > 64 &&
7039 !cta_vdb_has_vic(connector, vic))
7046 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7047 * data from a DRM display mode
7048 * @frame: HDMI AVI infoframe
7049 * @connector: the connector
7050 * @mode: DRM display mode
7052 * Return: 0 on success or a negative error code on failure.
7055 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7056 const struct drm_connector *connector,
7057 const struct drm_display_mode *mode)
7059 enum hdmi_picture_aspect picture_aspect;
7062 if (!frame || !mode)
7065 hdmi_avi_infoframe_init(frame);
7067 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7068 frame->pixel_repeat = 1;
7070 vic = drm_mode_cea_vic(connector, mode);
7071 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7073 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7076 * As some drivers don't support atomic, we can't use connector state.
7077 * So just initialize the frame with default values, just the same way
7078 * as it's done with other properties here.
7080 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7084 * Populate picture aspect ratio from either
7085 * user input (if specified) or from the CEA/HDMI mode lists.
7087 picture_aspect = mode->picture_aspect_ratio;
7088 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7090 picture_aspect = drm_get_cea_aspect_ratio(vic);
7092 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7096 * The infoframe can't convey anything but none, 4:3
7097 * and 16:9, so if the user has asked for anything else
7098 * we can only satisfy it by specifying the right VIC.
7100 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7102 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7104 } else if (hdmi_vic) {
7105 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7111 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7114 frame->video_code = vic_for_avi_infoframe(connector, vic);
7115 frame->picture_aspect = picture_aspect;
7116 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7117 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7121 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7124 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7125 * quantization range information
7126 * @frame: HDMI AVI infoframe
7127 * @connector: the connector
7128 * @mode: DRM display mode
7129 * @rgb_quant_range: RGB quantization range (Q)
7132 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7133 const struct drm_connector *connector,
7134 const struct drm_display_mode *mode,
7135 enum hdmi_quantization_range rgb_quant_range)
7137 const struct drm_display_info *info = &connector->display_info;
7141 * "A Source shall not send a non-zero Q value that does not correspond
7142 * to the default RGB Quantization Range for the transmitted Picture
7143 * unless the Sink indicates support for the Q bit in a Video
7144 * Capabilities Data Block."
7146 * HDMI 2.0 recommends sending non-zero Q when it does match the
7147 * default RGB quantization range for the mode, even when QS=0.
7149 if (info->rgb_quant_range_selectable ||
7150 rgb_quant_range == drm_default_rgb_quant_range(mode))
7151 frame->quantization_range = rgb_quant_range;
7153 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7157 * "When transmitting any RGB colorimetry, the Source should set the
7158 * YQ-field to match the RGB Quantization Range being transmitted
7159 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7160 * set YQ=1) and the Sink shall ignore the YQ-field."
7162 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7163 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7164 * good way to tell which version of CEA-861 the sink supports, so
7165 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7168 if (!is_hdmi2_sink(connector) ||
7169 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7170 frame->ycc_quantization_range =
7171 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7173 frame->ycc_quantization_range =
7174 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7176 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7178 static enum hdmi_3d_structure
7179 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7181 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7184 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7185 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7186 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7187 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7188 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7189 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7190 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7191 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7192 case DRM_MODE_FLAG_3D_L_DEPTH:
7193 return HDMI_3D_STRUCTURE_L_DEPTH;
7194 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7195 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7196 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7197 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7198 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7199 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7201 return HDMI_3D_STRUCTURE_INVALID;
7206 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7207 * data from a DRM display mode
7208 * @frame: HDMI vendor infoframe
7209 * @connector: the connector
7210 * @mode: DRM display mode
7212 * Note that there's is a need to send HDMI vendor infoframes only when using a
7213 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7214 * function will return -EINVAL, error that can be safely ignored.
7216 * Return: 0 on success or a negative error code on failure.
7219 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7220 const struct drm_connector *connector,
7221 const struct drm_display_mode *mode)
7224 * FIXME: sil-sii8620 doesn't have a connector around when
7225 * we need one, so we have to be prepared for a NULL connector.
7227 bool has_hdmi_infoframe = connector ?
7228 connector->display_info.has_hdmi_infoframe : false;
7231 if (!frame || !mode)
7234 if (!has_hdmi_infoframe)
7237 err = hdmi_vendor_infoframe_init(frame);
7242 * Even if it's not absolutely necessary to send the infoframe
7243 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7244 * know that the sink can handle it. This is based on a
7245 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7246 * have trouble realizing that they should switch from 3D to 2D
7247 * mode if the source simply stops sending the infoframe when
7248 * it wants to switch from 3D to 2D.
7250 frame->vic = drm_mode_hdmi_vic(connector, mode);
7251 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7255 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7257 static void drm_parse_tiled_block(struct drm_connector *connector,
7258 const struct displayid_block *block)
7260 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7262 u8 tile_v_loc, tile_h_loc;
7263 u8 num_v_tile, num_h_tile;
7264 struct drm_tile_group *tg;
7266 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7267 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7269 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7270 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7271 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7272 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7274 connector->has_tile = true;
7275 if (tile->tile_cap & 0x80)
7276 connector->tile_is_single_monitor = true;
7278 connector->num_h_tile = num_h_tile + 1;
7279 connector->num_v_tile = num_v_tile + 1;
7280 connector->tile_h_loc = tile_h_loc;
7281 connector->tile_v_loc = tile_v_loc;
7282 connector->tile_h_size = w + 1;
7283 connector->tile_v_size = h + 1;
7285 drm_dbg_kms(connector->dev,
7286 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7287 connector->base.id, connector->name,
7289 connector->tile_h_size, connector->tile_v_size,
7290 connector->num_h_tile, connector->num_v_tile,
7291 connector->tile_h_loc, connector->tile_v_loc,
7292 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7294 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7296 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7300 if (connector->tile_group != tg) {
7301 /* if we haven't got a pointer,
7302 take the reference, drop ref to old tile group */
7303 if (connector->tile_group)
7304 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7305 connector->tile_group = tg;
7307 /* if same tile group, then release the ref we just took. */
7308 drm_mode_put_tile_group(connector->dev, tg);
7312 static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7313 const struct displayid_block *block)
7315 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 &&
7316 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7317 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7318 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7321 static void _drm_update_tile_info(struct drm_connector *connector,
7322 const struct drm_edid *drm_edid)
7324 const struct displayid_block *block;
7325 struct displayid_iter iter;
7327 connector->has_tile = false;
7329 displayid_iter_edid_begin(drm_edid, &iter);
7330 displayid_iter_for_each(block, &iter) {
7331 if (displayid_is_tiled_block(&iter, block))
7332 drm_parse_tiled_block(connector, block);
7334 displayid_iter_end(&iter);
7336 if (!connector->has_tile && connector->tile_group) {
7337 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7338 connector->tile_group = NULL;
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