2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
46 #include "drm_crtc_internal.h"
48 static int oui(u8 first, u8 second, u8 third)
50 return (first << 16) | (second << 8) | third;
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
91 #define MICROSOFT_IEEE_OUI 0xca125c
93 struct detailed_mode_closure {
94 struct drm_connector *connector;
95 const struct drm_edid *drm_edid;
106 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
113 static const struct edid_quirk {
116 } edid_quirk_list[] = {
118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
137 /* Belinea 10 15 55 */
138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
141 /* Envision Peripherals, Inc. EN-7100e */
142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
143 /* Envision EN2028 */
144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
146 /* Funai Electronics PM36B */
147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
148 EDID_QUIRK_DETAILED_IN_CM),
150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
153 /* LG Philips LCD LP154W01-A5 */
154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
157 /* Samsung SyncMaster 205BW. Note: irony */
158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
159 /* Samsung SyncMaster 22[5-6]BW */
160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
166 /* ViewSonic VA2026w */
167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
169 /* Medion MD 30217 PG */
170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
181 /* Valve Index Headset */
182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
200 /* HTC Vive and Vive Pro VR Headsets */
201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
210 /* Windows Mixed Reality Headsets */
211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
218 /* Sony PlayStation VR Headset */
219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
221 /* Sensics VR Headsets */
222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
224 /* OSVR HDK and HDK2 VR Headsets */
225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
229 * Autogenerated from the DMT spec.
230 * This table is copied from xfree86/modes/xf86EdidModes.c.
232 static const struct drm_display_mode drm_dmt_modes[] = {
233 /* 0x01 - 640x350@85Hz */
234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
235 736, 832, 0, 350, 382, 385, 445, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x02 - 640x400@85Hz */
238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
239 736, 832, 0, 400, 401, 404, 445, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x03 - 720x400@85Hz */
242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
243 828, 936, 0, 400, 401, 404, 446, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x04 - 640x480@60Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
247 752, 800, 0, 480, 490, 492, 525, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x05 - 640x480@72Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
251 704, 832, 0, 480, 489, 492, 520, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x06 - 640x480@75Hz */
254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
255 720, 840, 0, 480, 481, 484, 500, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
257 /* 0x07 - 640x480@85Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
259 752, 832, 0, 480, 481, 484, 509, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x08 - 800x600@56Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
263 896, 1024, 0, 600, 601, 603, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x09 - 800x600@60Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
267 968, 1056, 0, 600, 601, 605, 628, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0a - 800x600@72Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
271 976, 1040, 0, 600, 637, 643, 666, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0b - 800x600@75Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
275 896, 1056, 0, 600, 601, 604, 625, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0c - 800x600@85Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
279 896, 1048, 0, 600, 601, 604, 631, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0d - 800x600@120Hz RB */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
283 880, 960, 0, 600, 603, 607, 636, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
285 /* 0x0e - 848x480@60Hz */
286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
287 976, 1088, 0, 480, 486, 494, 517, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x0f - 1024x768@43Hz, interlace */
290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
291 1208, 1264, 0, 768, 768, 776, 817, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
293 DRM_MODE_FLAG_INTERLACE) },
294 /* 0x10 - 1024x768@60Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
296 1184, 1344, 0, 768, 771, 777, 806, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
298 /* 0x11 - 1024x768@70Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
300 1184, 1328, 0, 768, 771, 777, 806, 0,
301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x12 - 1024x768@75Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
304 1136, 1312, 0, 768, 769, 772, 800, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x13 - 1024x768@85Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
308 1168, 1376, 0, 768, 769, 772, 808, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x14 - 1024x768@120Hz RB */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
312 1104, 1184, 0, 768, 771, 775, 813, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x15 - 1152x864@75Hz */
315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
316 1344, 1600, 0, 864, 865, 868, 900, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x55 - 1280x720@60Hz */
319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
320 1430, 1650, 0, 720, 725, 730, 750, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x16 - 1280x768@60Hz RB */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
324 1360, 1440, 0, 768, 771, 778, 790, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x17 - 1280x768@60Hz */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
328 1472, 1664, 0, 768, 771, 778, 798, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x18 - 1280x768@75Hz */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
332 1488, 1696, 0, 768, 771, 778, 805, 0,
333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x19 - 1280x768@85Hz */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
336 1496, 1712, 0, 768, 771, 778, 809, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x1a - 1280x768@120Hz RB */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
340 1360, 1440, 0, 768, 771, 778, 813, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
342 /* 0x1b - 1280x800@60Hz RB */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
344 1360, 1440, 0, 800, 803, 809, 823, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
346 /* 0x1c - 1280x800@60Hz */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
348 1480, 1680, 0, 800, 803, 809, 831, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1d - 1280x800@75Hz */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
352 1488, 1696, 0, 800, 803, 809, 838, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x1e - 1280x800@85Hz */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
356 1496, 1712, 0, 800, 803, 809, 843, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x1f - 1280x800@120Hz RB */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
360 1360, 1440, 0, 800, 803, 809, 847, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362 /* 0x20 - 1280x960@60Hz */
363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
364 1488, 1800, 0, 960, 961, 964, 1000, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x21 - 1280x960@85Hz */
367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
368 1504, 1728, 0, 960, 961, 964, 1011, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x22 - 1280x960@120Hz RB */
371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
372 1360, 1440, 0, 960, 963, 967, 1017, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x23 - 1280x1024@60Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x24 - 1280x1024@75Hz */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x25 - 1280x1024@85Hz */
383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x26 - 1280x1024@120Hz RB */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x27 - 1360x768@60Hz */
391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
392 1536, 1792, 0, 768, 771, 777, 795, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x28 - 1360x768@120Hz RB */
395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
396 1440, 1520, 0, 768, 771, 776, 813, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x51 - 1366x768@60Hz */
399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
400 1579, 1792, 0, 768, 771, 774, 798, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x56 - 1366x768@60Hz */
403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
404 1436, 1500, 0, 768, 769, 772, 800, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x29 - 1400x1050@60Hz RB */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
410 /* 0x2a - 1400x1050@60Hz */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x2b - 1400x1050@75Hz */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x2c - 1400x1050@85Hz */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x2d - 1400x1050@120Hz RB */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
426 /* 0x2e - 1440x900@60Hz RB */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
428 1520, 1600, 0, 900, 903, 909, 926, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
430 /* 0x2f - 1440x900@60Hz */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
432 1672, 1904, 0, 900, 903, 909, 934, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x30 - 1440x900@75Hz */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
436 1688, 1936, 0, 900, 903, 909, 942, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x31 - 1440x900@85Hz */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
440 1696, 1952, 0, 900, 903, 909, 948, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x32 - 1440x900@120Hz RB */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
444 1520, 1600, 0, 900, 903, 909, 953, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
446 /* 0x53 - 1600x900@60Hz */
447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
448 1704, 1800, 0, 900, 901, 904, 1000, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x33 - 1600x1200@60Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x34 - 1600x1200@65Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x35 - 1600x1200@70Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x36 - 1600x1200@75Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x37 - 1600x1200@85Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x38 - 1600x1200@120Hz RB */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
474 /* 0x39 - 1680x1050@60Hz RB */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
478 /* 0x3a - 1680x1050@60Hz */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x3b - 1680x1050@75Hz */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x3c - 1680x1050@85Hz */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3d - 1680x1050@120Hz RB */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
494 /* 0x3e - 1792x1344@60Hz */
495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x3f - 1792x1344@75Hz */
499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x40 - 1792x1344@120Hz RB */
503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x41 - 1856x1392@60Hz */
507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x42 - 1856x1392@75Hz */
511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x43 - 1856x1392@120Hz RB */
515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x52 - 1920x1080@60Hz */
519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
522 /* 0x44 - 1920x1200@60Hz RB */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
526 /* 0x45 - 1920x1200@60Hz */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x46 - 1920x1200@75Hz */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x47 - 1920x1200@85Hz */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x48 - 1920x1200@120Hz RB */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x49 - 1920x1440@60Hz */
543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x4a - 1920x1440@75Hz */
547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4b - 1920x1440@120Hz RB */
551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x54 - 2048x1152@60Hz */
555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4c - 2560x1600@60Hz RB */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
562 /* 0x4d - 2560x1600@60Hz */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x4e - 2560x1600@75Hz */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
570 /* 0x4f - 2560x1600@85Hz */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
574 /* 0x50 - 2560x1600@120Hz RB */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
578 /* 0x57 - 4096x2160@60Hz RB */
579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
582 /* 0x58 - 4096x2160@59.94Hz RB */
583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
589 * These more or less come from the DMT spec. The 720x400 modes are
590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
595 * The DMT modes have been fact-checked; the rest are mild guesses.
597 static const struct drm_display_mode edid_est_modes[] = {
598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
599 968, 1056, 0, 600, 601, 605, 628, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
602 896, 1024, 0, 600, 601, 603, 625, 0,
603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
605 720, 840, 0, 480, 481, 484, 500, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
608 704, 832, 0, 480, 489, 492, 520, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
611 768, 864, 0, 480, 483, 486, 525, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
614 752, 800, 0, 480, 490, 492, 525, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
617 846, 900, 0, 400, 421, 423, 449, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
620 846, 900, 0, 400, 412, 414, 449, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
626 1136, 1312, 0, 768, 769, 772, 800, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
629 1184, 1328, 0, 768, 771, 777, 806, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
632 1184, 1344, 0, 768, 771, 777, 806, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
635 1208, 1264, 0, 768, 768, 776, 817, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
638 928, 1152, 0, 624, 625, 628, 667, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
641 896, 1056, 0, 600, 601, 604, 625, 0,
642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
644 976, 1040, 0, 600, 637, 643, 666, 0,
645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
647 1344, 1600, 0, 864, 865, 868, 900, 0,
648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
658 static const struct minimode est3_modes[] = {
666 { 1024, 768, 85, 0 },
667 { 1152, 864, 75, 0 },
669 { 1280, 768, 60, 1 },
670 { 1280, 768, 60, 0 },
671 { 1280, 768, 75, 0 },
672 { 1280, 768, 85, 0 },
673 { 1280, 960, 60, 0 },
674 { 1280, 960, 85, 0 },
675 { 1280, 1024, 60, 0 },
676 { 1280, 1024, 85, 0 },
678 { 1360, 768, 60, 0 },
679 { 1440, 900, 60, 1 },
680 { 1440, 900, 60, 0 },
681 { 1440, 900, 75, 0 },
682 { 1440, 900, 85, 0 },
683 { 1400, 1050, 60, 1 },
684 { 1400, 1050, 60, 0 },
685 { 1400, 1050, 75, 0 },
687 { 1400, 1050, 85, 0 },
688 { 1680, 1050, 60, 1 },
689 { 1680, 1050, 60, 0 },
690 { 1680, 1050, 75, 0 },
691 { 1680, 1050, 85, 0 },
692 { 1600, 1200, 60, 0 },
693 { 1600, 1200, 65, 0 },
694 { 1600, 1200, 70, 0 },
696 { 1600, 1200, 75, 0 },
697 { 1600, 1200, 85, 0 },
698 { 1792, 1344, 60, 0 },
699 { 1792, 1344, 75, 0 },
700 { 1856, 1392, 60, 0 },
701 { 1856, 1392, 75, 0 },
702 { 1920, 1200, 60, 1 },
703 { 1920, 1200, 60, 0 },
705 { 1920, 1200, 75, 0 },
706 { 1920, 1200, 85, 0 },
707 { 1920, 1440, 60, 0 },
708 { 1920, 1440, 75, 0 },
711 static const struct minimode extra_modes[] = {
712 { 1024, 576, 60, 0 },
713 { 1366, 768, 60, 0 },
714 { 1600, 900, 60, 0 },
715 { 1680, 945, 60, 0 },
716 { 1920, 1080, 60, 0 },
717 { 2048, 1152, 60, 0 },
718 { 2048, 1536, 60, 0 },
722 * From CEA/CTA-861 spec.
724 * Do not access directly, instead always use cea_mode_for_vic().
726 static const struct drm_display_mode edid_cea_modes_1[] = {
727 /* 1 - 640x480@60Hz 4:3 */
728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
729 752, 800, 0, 480, 490, 492, 525, 0,
730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
732 /* 2 - 720x480@60Hz 4:3 */
733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
734 798, 858, 0, 480, 489, 495, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
737 /* 3 - 720x480@60Hz 16:9 */
738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
742 /* 4 - 1280x720@60Hz 16:9 */
743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
744 1430, 1650, 0, 720, 725, 730, 750, 0,
745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 5 - 1920x1080i@60Hz 16:9 */
748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
751 DRM_MODE_FLAG_INTERLACE),
752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 6 - 720(1440)x480i@60Hz 4:3 */
754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 480, 488, 494, 525, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
759 /* 7 - 720(1440)x480i@60Hz 16:9 */
760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 480, 488, 494, 525, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 8 - 720(1440)x240@60Hz 4:3 */
766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 240, 244, 247, 262, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_DBLCLK),
770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 9 - 720(1440)x240@60Hz 16:9 */
772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
773 801, 858, 0, 240, 244, 247, 262, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_DBLCLK),
776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 10 - 2880x480i@60Hz 4:3 */
778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 480, 488, 494, 525, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_INTERLACE),
782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
783 /* 11 - 2880x480i@60Hz 16:9 */
784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
785 3204, 3432, 0, 480, 488, 494, 525, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
787 DRM_MODE_FLAG_INTERLACE),
788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
789 /* 12 - 2880x240@60Hz 4:3 */
790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
791 3204, 3432, 0, 240, 244, 247, 262, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 13 - 2880x240@60Hz 16:9 */
795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799 /* 14 - 1440x480@60Hz 4:3 */
800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
801 1596, 1716, 0, 480, 489, 495, 525, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
804 /* 15 - 1440x480@60Hz 16:9 */
805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
809 /* 16 - 1920x1080@60Hz 16:9 */
810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 17 - 720x576@50Hz 4:3 */
815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
816 796, 864, 0, 576, 581, 586, 625, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
819 /* 18 - 720x576@50Hz 16:9 */
820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
824 /* 19 - 1280x720@50Hz 16:9 */
825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
826 1760, 1980, 0, 720, 725, 730, 750, 0,
827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 20 - 1920x1080i@50Hz 16:9 */
830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
833 DRM_MODE_FLAG_INTERLACE),
834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 21 - 720(1440)x576i@50Hz 4:3 */
836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
841 /* 22 - 720(1440)x576i@50Hz 16:9 */
842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 576, 580, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 23 - 720(1440)x288@50Hz 4:3 */
848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 288, 290, 293, 312, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_DBLCLK),
852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 24 - 720(1440)x288@50Hz 16:9 */
854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
855 795, 864, 0, 288, 290, 293, 312, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_DBLCLK),
858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 25 - 2880x576i@50Hz 4:3 */
860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 576, 580, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
863 DRM_MODE_FLAG_INTERLACE),
864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
865 /* 26 - 2880x576i@50Hz 16:9 */
866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
867 3180, 3456, 0, 576, 580, 586, 625, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
869 DRM_MODE_FLAG_INTERLACE),
870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 27 - 2880x288@50Hz 4:3 */
872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
873 3180, 3456, 0, 288, 290, 293, 312, 0,
874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 28 - 2880x288@50Hz 16:9 */
877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
881 /* 29 - 1440x576@50Hz 4:3 */
882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
883 1592, 1728, 0, 576, 581, 586, 625, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
886 /* 30 - 1440x576@50Hz 16:9 */
887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
891 /* 31 - 1920x1080@50Hz 16:9 */
892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 32 - 1920x1080@24Hz 16:9 */
897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 33 - 1920x1080@25Hz 16:9 */
902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
906 /* 34 - 1920x1080@30Hz 16:9 */
907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
911 /* 35 - 2880x480@60Hz 4:3 */
912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
913 3192, 3432, 0, 480, 489, 495, 525, 0,
914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
916 /* 36 - 2880x480@60Hz 16:9 */
917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
921 /* 37 - 2880x576@50Hz 4:3 */
922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
923 3184, 3456, 0, 576, 581, 586, 625, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
926 /* 38 - 2880x576@50Hz 16:9 */
927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 39 - 1920x1080i@50Hz 16:9 */
932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
935 DRM_MODE_FLAG_INTERLACE),
936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
937 /* 40 - 1920x1080i@100Hz 16:9 */
938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
941 DRM_MODE_FLAG_INTERLACE),
942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 41 - 1280x720@100Hz 16:9 */
944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
945 1760, 1980, 0, 720, 725, 730, 750, 0,
946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 42 - 720x576@100Hz 4:3 */
949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
950 796, 864, 0, 576, 581, 586, 625, 0,
951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
953 /* 43 - 720x576@100Hz 16:9 */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 44 - 720(1440)x576i@100Hz 4:3 */
959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
964 /* 45 - 720(1440)x576i@100Hz 16:9 */
965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
966 795, 864, 0, 576, 580, 586, 625, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 46 - 1920x1080i@120Hz 16:9 */
971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
974 DRM_MODE_FLAG_INTERLACE),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
976 /* 47 - 1280x720@120Hz 16:9 */
977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
978 1430, 1650, 0, 720, 725, 730, 750, 0,
979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 48 - 720x480@120Hz 4:3 */
982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
983 798, 858, 0, 480, 489, 495, 525, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
986 /* 49 - 720x480@120Hz 16:9 */
987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
991 /* 50 - 720(1440)x480i@120Hz 4:3 */
992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
993 801, 858, 0, 480, 488, 494, 525, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
997 /* 51 - 720(1440)x480i@120Hz 16:9 */
998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
999 801, 858, 0, 480, 488, 494, 525, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 /* 52 - 720x576@200Hz 4:3 */
1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1005 796, 864, 0, 576, 581, 586, 625, 0,
1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1008 /* 53 - 720x576@200Hz 16:9 */
1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1013 /* 54 - 720(1440)x576i@200Hz 4:3 */
1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1015 795, 864, 0, 576, 580, 586, 625, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1019 /* 55 - 720(1440)x576i@200Hz 16:9 */
1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1021 795, 864, 0, 576, 580, 586, 625, 0,
1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025 /* 56 - 720x480@240Hz 4:3 */
1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1027 798, 858, 0, 480, 489, 495, 525, 0,
1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1030 /* 57 - 720x480@240Hz 16:9 */
1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035 /* 58 - 720(1440)x480i@240Hz 4:3 */
1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1037 801, 858, 0, 480, 488, 494, 525, 0,
1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1041 /* 59 - 720(1440)x480i@240Hz 16:9 */
1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1043 801, 858, 0, 480, 488, 494, 525, 0,
1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1047 /* 60 - 1280x720@24Hz 16:9 */
1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1049 3080, 3300, 0, 720, 725, 730, 750, 0,
1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1052 /* 61 - 1280x720@25Hz 16:9 */
1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1054 3740, 3960, 0, 720, 725, 730, 750, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1057 /* 62 - 1280x720@30Hz 16:9 */
1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1059 3080, 3300, 0, 720, 725, 730, 750, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1062 /* 63 - 1920x1080@120Hz 16:9 */
1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1067 /* 64 - 1920x1080@100Hz 16:9 */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1072 /* 65 - 1280x720@24Hz 64:27 */
1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1074 3080, 3300, 0, 720, 725, 730, 750, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077 /* 66 - 1280x720@25Hz 64:27 */
1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1079 3740, 3960, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 67 - 1280x720@30Hz 64:27 */
1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1084 3080, 3300, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 68 - 1280x720@50Hz 64:27 */
1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1089 1760, 1980, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 69 - 1280x720@60Hz 64:27 */
1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1094 1430, 1650, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 70 - 1280x720@100Hz 64:27 */
1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1099 1760, 1980, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 71 - 1280x720@120Hz 64:27 */
1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1104 1430, 1650, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 72 - 1920x1080@24Hz 64:27 */
1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 73 - 1920x1080@25Hz 64:27 */
1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 74 - 1920x1080@30Hz 64:27 */
1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 75 - 1920x1080@50Hz 64:27 */
1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 76 - 1920x1080@60Hz 64:27 */
1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 77 - 1920x1080@100Hz 64:27 */
1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 78 - 1920x1080@120Hz 64:27 */
1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 79 - 1680x720@24Hz 64:27 */
1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1144 3080, 3300, 0, 720, 725, 730, 750, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 80 - 1680x720@25Hz 64:27 */
1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1149 2948, 3168, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 81 - 1680x720@30Hz 64:27 */
1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1154 2420, 2640, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 82 - 1680x720@50Hz 64:27 */
1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1159 1980, 2200, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162 /* 83 - 1680x720@60Hz 64:27 */
1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1167 /* 84 - 1680x720@100Hz 64:27 */
1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1169 1780, 2000, 0, 720, 725, 730, 825, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1172 /* 85 - 1680x720@120Hz 64:27 */
1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1177 /* 86 - 2560x1080@24Hz 64:27 */
1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1182 /* 87 - 2560x1080@25Hz 64:27 */
1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1187 /* 88 - 2560x1080@30Hz 64:27 */
1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1192 /* 89 - 2560x1080@50Hz 64:27 */
1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1197 /* 90 - 2560x1080@60Hz 64:27 */
1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1202 /* 91 - 2560x1080@100Hz 64:27 */
1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1207 /* 92 - 2560x1080@120Hz 64:27 */
1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1212 /* 93 - 3840x2160@24Hz 16:9 */
1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1217 /* 94 - 3840x2160@25Hz 16:9 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1222 /* 95 - 3840x2160@30Hz 16:9 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1227 /* 96 - 3840x2160@50Hz 16:9 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1232 /* 97 - 3840x2160@60Hz 16:9 */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1237 /* 98 - 4096x2160@24Hz 256:135 */
1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1242 /* 99 - 4096x2160@25Hz 256:135 */
1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1247 /* 100 - 4096x2160@30Hz 256:135 */
1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1252 /* 101 - 4096x2160@50Hz 256:135 */
1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1257 /* 102 - 4096x2160@60Hz 256:135 */
1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1262 /* 103 - 3840x2160@24Hz 64:27 */
1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1267 /* 104 - 3840x2160@25Hz 64:27 */
1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1272 /* 105 - 3840x2160@30Hz 64:27 */
1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1277 /* 106 - 3840x2160@50Hz 64:27 */
1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1282 /* 107 - 3840x2160@60Hz 64:27 */
1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1287 /* 108 - 1280x720@48Hz 16:9 */
1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1289 2280, 2500, 0, 720, 725, 730, 750, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1292 /* 109 - 1280x720@48Hz 64:27 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1297 /* 110 - 1680x720@48Hz 64:27 */
1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1299 2530, 2750, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1302 /* 111 - 1920x1080@48Hz 16:9 */
1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1307 /* 112 - 1920x1080@48Hz 64:27 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1312 /* 113 - 2560x1080@48Hz 64:27 */
1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1317 /* 114 - 3840x2160@48Hz 16:9 */
1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1322 /* 115 - 4096x2160@48Hz 256:135 */
1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1327 /* 116 - 3840x2160@48Hz 64:27 */
1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1332 /* 117 - 3840x2160@100Hz 16:9 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1337 /* 118 - 3840x2160@120Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1342 /* 119 - 3840x2160@100Hz 64:27 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1347 /* 120 - 3840x2160@120Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1352 /* 121 - 5120x2160@24Hz 64:27 */
1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1357 /* 122 - 5120x2160@25Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1362 /* 123 - 5120x2160@30Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1367 /* 124 - 5120x2160@48Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1372 /* 125 - 5120x2160@50Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1377 /* 126 - 5120x2160@60Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1382 /* 127 - 5120x2160@100Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 * From CEA/CTA-861 spec.
1392 * Do not access directly, instead always use cea_mode_for_vic().
1394 static const struct drm_display_mode edid_cea_modes_193[] = {
1395 /* 193 - 5120x2160@120Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1400 /* 194 - 7680x4320@24Hz 16:9 */
1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1405 /* 195 - 7680x4320@25Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1410 /* 196 - 7680x4320@30Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1415 /* 197 - 7680x4320@48Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1420 /* 198 - 7680x4320@50Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1425 /* 199 - 7680x4320@60Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1430 /* 200 - 7680x4320@100Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1435 /* 201 - 7680x4320@120Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1440 /* 202 - 7680x4320@24Hz 64:27 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1445 /* 203 - 7680x4320@25Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1450 /* 204 - 7680x4320@30Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1455 /* 205 - 7680x4320@48Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1460 /* 206 - 7680x4320@50Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1465 /* 207 - 7680x4320@60Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1470 /* 208 - 7680x4320@100Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1475 /* 209 - 7680x4320@120Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1480 /* 210 - 10240x4320@24Hz 64:27 */
1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1485 /* 211 - 10240x4320@25Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1490 /* 212 - 10240x4320@30Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1495 /* 213 - 10240x4320@48Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1500 /* 214 - 10240x4320@50Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1505 /* 215 - 10240x4320@60Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1510 /* 216 - 10240x4320@100Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1515 /* 217 - 10240x4320@120Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1520 /* 218 - 4096x2160@100Hz 256:135 */
1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1525 /* 219 - 4096x2160@120Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1533 * HDMI 1.4 4k modes. Index using the VIC.
1535 static const struct drm_display_mode edid_4k_modes[] = {
1536 /* 0 - dummy, VICs start at 1 */
1538 /* 1 - 3840x2160@30Hz */
1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1540 3840, 4016, 4104, 4400, 0,
1541 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1544 /* 2 - 3840x2160@25Hz */
1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1546 3840, 4896, 4984, 5280, 0,
1547 2160, 2168, 2178, 2250, 0,
1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1550 /* 3 - 3840x2160@24Hz */
1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1552 3840, 5116, 5204, 5500, 0,
1553 2160, 2168, 2178, 2250, 0,
1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1556 /* 4 - 4096x2160@24Hz (SMPTE) */
1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1558 4096, 5116, 5204, 5500, 0,
1559 2160, 2168, 2178, 2250, 0,
1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1564 /*** DDC fetch and block validation ***/
1567 * The opaque EDID type, internal to drm_edid.c.
1570 /* Size allocated for edid */
1572 const struct edid *edid;
1575 static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1577 static int edid_hfeeodb_block_count(const struct edid *edid)
1579 int eeodb = edid_hfeeodb_extension_block_count(edid);
1581 return eeodb ? eeodb + 1 : 0;
1584 static int edid_extension_block_count(const struct edid *edid)
1586 return edid->extensions;
1589 static int edid_block_count(const struct edid *edid)
1591 return edid_extension_block_count(edid) + 1;
1594 static int edid_size_by_blocks(int num_blocks)
1596 return num_blocks * EDID_LENGTH;
1599 static int edid_size(const struct edid *edid)
1601 return edid_size_by_blocks(edid_block_count(edid));
1604 static const void *edid_block_data(const struct edid *edid, int index)
1606 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1608 return edid + index;
1611 static const void *edid_extension_block_data(const struct edid *edid, int index)
1613 return edid_block_data(edid, index + 1);
1616 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1620 /* Starting point */
1621 num_blocks = edid_block_count(drm_edid->edid);
1623 /* HF-EEODB override */
1624 if (drm_edid->size >= edid_size_by_blocks(2)) {
1628 * Note: HF-EEODB may specify a smaller extension count than the
1629 * regular one. Unlike in buffer allocation, here we can use it.
1631 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1636 /* Limit by allocated size */
1637 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH);
1642 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1644 return drm_edid_block_count(drm_edid) - 1;
1647 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1649 return edid_block_data(drm_edid->edid, index);
1652 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1655 return edid_extension_block_data(drm_edid->edid, index);
1659 * Initializer helper for legacy interfaces, where we have no choice but to
1660 * trust edid size. Not for general purpose use.
1662 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1663 const struct edid *edid)
1668 memset(drm_edid, 0, sizeof(*drm_edid));
1670 drm_edid->edid = edid;
1671 drm_edid->size = edid_size(edid);
1677 * EDID base and extension block iterator.
1679 * struct drm_edid_iter iter;
1682 * drm_edid_iter_begin(drm_edid, &iter);
1683 * drm_edid_iter_for_each(block, &iter) {
1684 * // do stuff with block
1686 * drm_edid_iter_end(&iter);
1688 struct drm_edid_iter {
1689 const struct drm_edid *drm_edid;
1691 /* Current block index. */
1695 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1696 struct drm_edid_iter *iter)
1698 memset(iter, 0, sizeof(*iter));
1700 iter->drm_edid = drm_edid;
1703 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1705 const void *block = NULL;
1707 if (!iter->drm_edid)
1710 if (iter->index < drm_edid_block_count(iter->drm_edid))
1711 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1716 #define drm_edid_iter_for_each(__block, __iter) \
1717 while (((__block) = __drm_edid_iter_next(__iter)))
1719 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1721 memset(iter, 0, sizeof(*iter));
1724 static const u8 edid_header[] = {
1725 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1728 static void edid_header_fix(void *edid)
1730 memcpy(edid, edid_header, sizeof(edid_header));
1734 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1735 * @_edid: pointer to raw base EDID block
1737 * Sanity check the header of the base EDID block.
1739 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1741 int drm_edid_header_is_valid(const void *_edid)
1743 const struct edid *edid = _edid;
1746 for (i = 0; i < sizeof(edid_header); i++) {
1747 if (edid->header[i] == edid_header[i])
1753 EXPORT_SYMBOL(drm_edid_header_is_valid);
1755 static int edid_fixup __read_mostly = 6;
1756 module_param_named(edid_fixup, edid_fixup, int, 0400);
1757 MODULE_PARM_DESC(edid_fixup,
1758 "Minimum number of valid EDID header bytes (0-8, default 6)");
1760 static int edid_block_compute_checksum(const void *_block)
1762 const u8 *block = _block;
1764 u8 csum = 0, crc = 0;
1766 for (i = 0; i < EDID_LENGTH - 1; i++)
1774 static int edid_block_get_checksum(const void *_block)
1776 const struct edid *block = _block;
1778 return block->checksum;
1781 static int edid_block_tag(const void *_block)
1783 const u8 *block = _block;
1788 static bool edid_block_is_zero(const void *edid)
1790 return !memchr_inv(edid, 0, EDID_LENGTH);
1794 * drm_edid_are_equal - compare two edid blobs.
1795 * @edid1: pointer to first blob
1796 * @edid2: pointer to second blob
1797 * This helper can be used during probing to determine if
1800 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1802 int edid1_len, edid2_len;
1803 bool edid1_present = edid1 != NULL;
1804 bool edid2_present = edid2 != NULL;
1806 if (edid1_present != edid2_present)
1810 edid1_len = edid_size(edid1);
1811 edid2_len = edid_size(edid2);
1813 if (edid1_len != edid2_len)
1816 if (memcmp(edid1, edid2, edid1_len))
1822 EXPORT_SYMBOL(drm_edid_are_equal);
1824 enum edid_block_status {
1826 EDID_BLOCK_READ_FAIL,
1829 EDID_BLOCK_HEADER_CORRUPT,
1830 EDID_BLOCK_HEADER_REPAIR,
1831 EDID_BLOCK_HEADER_FIXED,
1832 EDID_BLOCK_CHECKSUM,
1836 static enum edid_block_status edid_block_check(const void *_block,
1839 const struct edid *block = _block;
1842 return EDID_BLOCK_NULL;
1844 if (is_base_block) {
1845 int score = drm_edid_header_is_valid(block);
1847 if (score < clamp(edid_fixup, 0, 8)) {
1848 if (edid_block_is_zero(block))
1849 return EDID_BLOCK_ZERO;
1851 return EDID_BLOCK_HEADER_CORRUPT;
1855 return EDID_BLOCK_HEADER_REPAIR;
1858 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1859 if (edid_block_is_zero(block))
1860 return EDID_BLOCK_ZERO;
1862 return EDID_BLOCK_CHECKSUM;
1865 if (is_base_block) {
1866 if (block->version != 1)
1867 return EDID_BLOCK_VERSION;
1870 return EDID_BLOCK_OK;
1873 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1875 return status == EDID_BLOCK_OK ||
1876 status == EDID_BLOCK_HEADER_FIXED ||
1877 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1880 static bool edid_block_valid(const void *block, bool base)
1882 return edid_block_status_valid(edid_block_check(block, base),
1883 edid_block_tag(block));
1886 static void edid_block_status_print(enum edid_block_status status,
1887 const struct edid *block,
1893 case EDID_BLOCK_READ_FAIL:
1894 pr_debug("EDID block %d read failed\n", block_num);
1896 case EDID_BLOCK_NULL:
1897 pr_debug("EDID block %d pointer is NULL\n", block_num);
1899 case EDID_BLOCK_ZERO:
1900 pr_notice("EDID block %d is all zeroes\n", block_num);
1902 case EDID_BLOCK_HEADER_CORRUPT:
1903 pr_notice("EDID has corrupt header\n");
1905 case EDID_BLOCK_HEADER_REPAIR:
1906 pr_debug("EDID corrupt header needs repair\n");
1908 case EDID_BLOCK_HEADER_FIXED:
1909 pr_debug("EDID corrupt header fixed\n");
1911 case EDID_BLOCK_CHECKSUM:
1912 if (edid_block_status_valid(status, edid_block_tag(block))) {
1913 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1914 block_num, edid_block_tag(block),
1915 edid_block_compute_checksum(block));
1917 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1918 block_num, edid_block_tag(block),
1919 edid_block_compute_checksum(block));
1922 case EDID_BLOCK_VERSION:
1923 pr_notice("EDID has major version %d, instead of 1\n",
1927 WARN(1, "EDID block %d unknown edid block status code %d\n",
1933 static void edid_block_dump(const char *level, const void *block, int block_num)
1935 enum edid_block_status status;
1938 status = edid_block_check(block, block_num == 0);
1939 if (status == EDID_BLOCK_ZERO)
1940 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1941 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1942 sprintf(prefix, "\t[%02x] BAD ", block_num);
1944 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1946 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1947 block, EDID_LENGTH, false);
1951 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1952 * @_block: pointer to raw EDID block
1953 * @block_num: type of block to validate (0 for base, extension otherwise)
1954 * @print_bad_edid: if true, dump bad EDID blocks to the console
1955 * @edid_corrupt: if true, the header or checksum is invalid
1957 * Validate a base or extension EDID block and optionally dump bad blocks to
1960 * Return: True if the block is valid, false otherwise.
1962 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1965 struct edid *block = (struct edid *)_block;
1966 enum edid_block_status status;
1967 bool is_base_block = block_num == 0;
1970 if (WARN_ON(!block))
1973 status = edid_block_check(block, is_base_block);
1974 if (status == EDID_BLOCK_HEADER_REPAIR) {
1975 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1976 edid_header_fix(block);
1978 /* Retry with fixed header, update status if that worked. */
1979 status = edid_block_check(block, is_base_block);
1980 if (status == EDID_BLOCK_OK)
1981 status = EDID_BLOCK_HEADER_FIXED;
1986 * Unknown major version isn't corrupt but we can't use it. Only
1987 * the base block can reset edid_corrupt to false.
1989 if (is_base_block &&
1990 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1991 *edid_corrupt = false;
1992 else if (status != EDID_BLOCK_OK)
1993 *edid_corrupt = true;
1996 edid_block_status_print(status, block, block_num);
1998 /* Determine whether we can use this block with this status. */
1999 valid = edid_block_status_valid(status, edid_block_tag(block));
2001 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2002 pr_notice("Raw EDID:\n");
2003 edid_block_dump(KERN_NOTICE, block, block_num);
2008 EXPORT_SYMBOL(drm_edid_block_valid);
2011 * drm_edid_is_valid - sanity check EDID data
2014 * Sanity-check an entire EDID record (including extensions)
2016 * Return: True if the EDID data is valid, false otherwise.
2018 bool drm_edid_is_valid(struct edid *edid)
2025 for (i = 0; i < edid_block_count(edid); i++) {
2026 void *block = (void *)edid_block_data(edid, i);
2028 if (!drm_edid_block_valid(block, i, true, NULL))
2034 EXPORT_SYMBOL(drm_edid_is_valid);
2036 static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2040 int i, valid_blocks = 0;
2043 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2044 * back to regular extension count here. We don't want to start
2045 * modifying the HF-EEODB extension too.
2047 for (i = 0; i < edid_block_count(edid); i++) {
2048 const void *src_block = edid_block_data(edid, i);
2050 if (edid_block_valid(src_block, i == 0)) {
2051 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2053 memmove(dst_block, src_block, EDID_LENGTH);
2058 /* We already trusted the base block to be valid here... */
2059 if (WARN_ON(!valid_blocks)) {
2064 edid->extensions = valid_blocks - 1;
2065 edid->checksum = edid_block_compute_checksum(edid);
2067 *alloc_size = edid_size_by_blocks(valid_blocks);
2069 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2076 #define DDC_SEGMENT_ADDR 0x30
2078 * drm_do_probe_ddc_edid() - get EDID information via I2C
2079 * @data: I2C device adapter
2080 * @buf: EDID data buffer to be filled
2081 * @block: 128 byte EDID block to start fetching from
2082 * @len: EDID data buffer length to fetch
2084 * Try to fetch EDID information by calling I2C driver functions.
2086 * Return: 0 on success or -1 on failure.
2089 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2091 struct i2c_adapter *adapter = data;
2092 unsigned char start = block * EDID_LENGTH;
2093 unsigned char segment = block >> 1;
2094 unsigned char xfers = segment ? 3 : 2;
2095 int ret, retries = 5;
2098 * The core I2C driver will automatically retry the transfer if the
2099 * adapter reports EAGAIN. However, we find that bit-banging transfers
2100 * are susceptible to errors under a heavily loaded machine and
2101 * generate spurious NAKs and timeouts. Retrying the transfer
2102 * of the individual block a few times seems to overcome this.
2105 struct i2c_msg msgs[] = {
2107 .addr = DDC_SEGMENT_ADDR,
2125 * Avoid sending the segment addr to not upset non-compliant
2128 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2130 if (ret == -ENXIO) {
2131 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2135 } while (ret != xfers && --retries);
2137 return ret == xfers ? 0 : -1;
2140 static void connector_bad_edid(struct drm_connector *connector,
2141 const struct edid *edid, int num_blocks)
2147 * 0x7e in the EDID is the number of extension blocks. The EDID
2148 * is 1 (base block) + num_ext_blocks big. That means we can think
2149 * of 0x7e in the EDID of the _index_ of the last block in the
2150 * combined chunk of memory.
2152 last_block = edid->extensions;
2154 /* Calculate real checksum for the last edid extension block data */
2155 if (last_block < num_blocks)
2156 connector->real_edid_checksum =
2157 edid_block_compute_checksum(edid + last_block);
2159 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2162 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
2163 for (i = 0; i < num_blocks; i++)
2164 edid_block_dump(KERN_DEBUG, edid + i, i);
2167 /* Get override or firmware EDID */
2168 static struct edid *drm_get_override_edid(struct drm_connector *connector,
2171 struct edid *override = NULL;
2173 if (connector->override_edid)
2174 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
2177 override = drm_load_edid_firmware(connector);
2179 /* FIXME: Get alloc size from deeper down the stack */
2180 if (!IS_ERR_OR_NULL(override) && alloc_size)
2181 *alloc_size = edid_size(override);
2183 return IS_ERR(override) ? NULL : override;
2186 /* For debugfs edid_override implementation */
2187 int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2192 if (size < EDID_LENGTH || edid_size(edid) > size)
2195 connector->override_edid = false;
2197 ret = drm_connector_update_edid_property(connector, edid);
2199 connector->override_edid = true;
2204 /* For debugfs edid_override implementation */
2205 int drm_edid_override_reset(struct drm_connector *connector)
2207 connector->override_edid = false;
2209 return drm_connector_update_edid_property(connector, NULL);
2213 * drm_add_override_edid_modes - add modes from override/firmware EDID
2214 * @connector: connector we're probing
2216 * Add modes from the override/firmware EDID, if available. Only to be used from
2217 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2218 * failed during drm_get_edid() and caused the override/firmware EDID to be
2221 * Return: The number of modes added or 0 if we couldn't find any.
2223 int drm_add_override_edid_modes(struct drm_connector *connector)
2225 struct edid *override;
2228 override = drm_get_override_edid(connector, NULL);
2230 drm_connector_update_edid_property(connector, override);
2231 num_modes = drm_add_edid_modes(connector, override);
2234 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2235 connector->base.id, connector->name, num_modes);
2240 EXPORT_SYMBOL(drm_add_override_edid_modes);
2242 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2244 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2245 read_block_fn read_block,
2248 enum edid_block_status status;
2249 bool is_base_block = block_num == 0;
2252 for (try = 0; try < 4; try++) {
2253 if (read_block(context, block, block_num, EDID_LENGTH))
2254 return EDID_BLOCK_READ_FAIL;
2256 status = edid_block_check(block, is_base_block);
2257 if (status == EDID_BLOCK_HEADER_REPAIR) {
2258 edid_header_fix(block);
2260 /* Retry with fixed header, update status if that worked. */
2261 status = edid_block_check(block, is_base_block);
2262 if (status == EDID_BLOCK_OK)
2263 status = EDID_BLOCK_HEADER_FIXED;
2266 if (edid_block_status_valid(status, edid_block_tag(block)))
2269 /* Fail early for unrepairable base block all zeros. */
2270 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2277 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2278 read_block_fn read_block, void *context,
2281 enum edid_block_status status;
2282 int i, num_blocks, invalid_blocks = 0;
2283 struct edid *edid, *new;
2284 size_t alloc_size = EDID_LENGTH;
2286 edid = drm_get_override_edid(connector, &alloc_size);
2290 edid = kmalloc(alloc_size, GFP_KERNEL);
2294 status = edid_block_read(edid, 0, read_block, context);
2296 edid_block_status_print(status, edid, 0);
2298 if (status == EDID_BLOCK_READ_FAIL)
2301 /* FIXME: Clarify what a corrupt EDID actually means. */
2302 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2303 connector->edid_corrupt = false;
2305 connector->edid_corrupt = true;
2307 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2308 if (status == EDID_BLOCK_ZERO)
2309 connector->null_edid_counter++;
2311 connector_bad_edid(connector, edid, 1);
2315 if (!edid_extension_block_count(edid))
2318 alloc_size = edid_size(edid);
2319 new = krealloc(edid, alloc_size, GFP_KERNEL);
2324 num_blocks = edid_block_count(edid);
2325 for (i = 1; i < num_blocks; i++) {
2326 void *block = (void *)edid_block_data(edid, i);
2328 status = edid_block_read(block, i, read_block, context);
2330 edid_block_status_print(status, block, i);
2332 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2333 if (status == EDID_BLOCK_READ_FAIL)
2336 } else if (i == 1) {
2338 * If the first EDID extension is a CTA extension, and
2339 * the first Data Block is HF-EEODB, override the
2340 * extension block count.
2342 * Note: HF-EEODB could specify a smaller extension
2343 * count too, but we can't risk allocating a smaller
2346 int eeodb = edid_hfeeodb_block_count(edid);
2348 if (eeodb > num_blocks) {
2350 alloc_size = edid_size_by_blocks(num_blocks);
2351 new = krealloc(edid, alloc_size, GFP_KERNEL);
2359 if (invalid_blocks) {
2360 connector_bad_edid(connector, edid, num_blocks);
2362 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2377 * drm_do_get_edid - get EDID data using a custom EDID block read function
2378 * @connector: connector we're probing
2379 * @read_block: EDID block read function
2380 * @context: private data passed to the block read function
2382 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2383 * exposes a different interface to read EDID blocks this function can be used
2384 * to get EDID data using a custom block read function.
2386 * As in the general case the DDC bus is accessible by the kernel at the I2C
2387 * level, drivers must make all reasonable efforts to expose it as an I2C
2388 * adapter and use drm_get_edid() instead of abusing this function.
2390 * The EDID may be overridden using debugfs override_edid or firmware EDID
2391 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2392 * order. Having either of them bypasses actual EDID reads.
2394 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2396 struct edid *drm_do_get_edid(struct drm_connector *connector,
2397 read_block_fn read_block,
2400 return _drm_do_get_edid(connector, read_block, context, NULL);
2402 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2405 * drm_edid_raw - Get a pointer to the raw EDID data.
2406 * @drm_edid: drm_edid container
2408 * Get a pointer to the raw EDID data.
2410 * This is for transition only. Avoid using this like the plague.
2412 * Return: Pointer to raw EDID data.
2414 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2416 if (!drm_edid || !drm_edid->size)
2420 * Do not return pointers where relying on EDID extension count would
2421 * lead to buffer overflow.
2423 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2426 return drm_edid->edid;
2428 EXPORT_SYMBOL(drm_edid_raw);
2430 /* Allocate struct drm_edid container *without* duplicating the edid data */
2431 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2433 struct drm_edid *drm_edid;
2435 if (!edid || !size || size < EDID_LENGTH)
2438 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2440 drm_edid->edid = edid;
2441 drm_edid->size = size;
2448 * drm_edid_alloc - Allocate a new drm_edid container
2449 * @edid: Pointer to raw EDID data
2450 * @size: Size of memory allocated for EDID
2452 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2453 * the actual size that has been allocated for the data. There is no validation
2454 * of the raw EDID data against the size, but at least the EDID base block must
2455 * fit in the buffer.
2457 * The returned pointer must be freed using drm_edid_free().
2459 * Return: drm_edid container, or NULL on errors
2461 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2463 const struct drm_edid *drm_edid;
2465 if (!edid || !size || size < EDID_LENGTH)
2468 edid = kmemdup(edid, size, GFP_KERNEL);
2472 drm_edid = _drm_edid_alloc(edid, size);
2478 EXPORT_SYMBOL(drm_edid_alloc);
2481 * drm_edid_dup - Duplicate a drm_edid container
2482 * @drm_edid: EDID to duplicate
2484 * The returned pointer must be freed using drm_edid_free().
2486 * Returns: drm_edid container copy, or NULL on errors
2488 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2493 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2495 EXPORT_SYMBOL(drm_edid_dup);
2498 * drm_edid_free - Free the drm_edid container
2499 * @drm_edid: EDID to free
2501 void drm_edid_free(const struct drm_edid *drm_edid)
2506 kfree(drm_edid->edid);
2509 EXPORT_SYMBOL(drm_edid_free);
2512 * drm_probe_ddc() - probe DDC presence
2513 * @adapter: I2C adapter to probe
2515 * Return: True on success, false on failure.
2518 drm_probe_ddc(struct i2c_adapter *adapter)
2522 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2524 EXPORT_SYMBOL(drm_probe_ddc);
2527 * drm_get_edid - get EDID data, if available
2528 * @connector: connector we're probing
2529 * @adapter: I2C adapter to use for DDC
2531 * Poke the given I2C channel to grab EDID data if possible. If found,
2532 * attach it to the connector.
2534 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2536 struct edid *drm_get_edid(struct drm_connector *connector,
2537 struct i2c_adapter *adapter)
2541 if (connector->force == DRM_FORCE_OFF)
2544 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2547 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2548 drm_connector_update_edid_property(connector, edid);
2551 EXPORT_SYMBOL(drm_get_edid);
2554 * drm_edid_read_custom - Read EDID data using given EDID block read function
2555 * @connector: Connector to use
2556 * @read_block: EDID block read function
2557 * @context: Private data passed to the block read function
2559 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2560 * exposes a different interface to read EDID blocks this function can be used
2561 * to get EDID data using a custom block read function.
2563 * As in the general case the DDC bus is accessible by the kernel at the I2C
2564 * level, drivers must make all reasonable efforts to expose it as an I2C
2565 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2568 * The EDID may be overridden using debugfs override_edid or firmware EDID
2569 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2570 * order. Having either of them bypasses actual EDID reads.
2572 * The returned pointer must be freed using drm_edid_free().
2574 * Return: Pointer to EDID, or NULL if probe/read failed.
2576 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2577 read_block_fn read_block,
2580 const struct drm_edid *drm_edid;
2584 edid = _drm_do_get_edid(connector, read_block, context, &size);
2588 /* Sanity check for now */
2589 drm_WARN_ON(connector->dev, !size);
2591 drm_edid = _drm_edid_alloc(edid, size);
2597 EXPORT_SYMBOL(drm_edid_read_custom);
2600 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2601 * @connector: Connector to use
2602 * @adapter: I2C adapter to use for DDC
2604 * Read EDID using the given I2C adapter.
2606 * The EDID may be overridden using debugfs override_edid or firmware EDID
2607 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2608 * order. Having either of them bypasses actual EDID reads.
2610 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2611 * using drm_edid_read() instead of this function.
2613 * The returned pointer must be freed using drm_edid_free().
2615 * Return: Pointer to EDID, or NULL if probe/read failed.
2617 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2618 struct i2c_adapter *adapter)
2620 const struct drm_edid *drm_edid;
2622 if (connector->force == DRM_FORCE_OFF)
2625 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2628 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2630 /* Note: Do *not* call connector updates here. */
2634 EXPORT_SYMBOL(drm_edid_read_ddc);
2637 * drm_edid_read - Read EDID data using connector's I2C adapter
2638 * @connector: Connector to use
2640 * Read EDID using the connector's I2C adapter.
2642 * The EDID may be overridden using debugfs override_edid or firmware EDID
2643 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2644 * order. Having either of them bypasses actual EDID reads.
2646 * The returned pointer must be freed using drm_edid_free().
2648 * Return: Pointer to EDID, or NULL if probe/read failed.
2650 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2652 if (drm_WARN_ON(connector->dev, !connector->ddc))
2655 return drm_edid_read_ddc(connector, connector->ddc);
2657 EXPORT_SYMBOL(drm_edid_read);
2659 static u32 edid_extract_panel_id(const struct edid *edid)
2662 * We represent the ID as a 32-bit number so it can easily be compared
2665 * NOTE that we deal with endianness differently for the top half
2666 * of this ID than for the bottom half. The bottom half (the product
2667 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2668 * that's how everyone seems to interpret it. The top half (the mfg_id)
2669 * gets stored as big endian because that makes
2670 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2671 * to write (it's easier to extract the ASCII). It doesn't really
2672 * matter, though, as long as the number here is unique.
2674 return (u32)edid->mfg_id[0] << 24 |
2675 (u32)edid->mfg_id[1] << 16 |
2676 (u32)EDID_PRODUCT_ID(edid);
2680 * drm_edid_get_panel_id - Get a panel's ID through DDC
2681 * @adapter: I2C adapter to use for DDC
2683 * This function reads the first block of the EDID of a panel and (assuming
2684 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2685 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2686 * supposed to be different for each different modem of panel.
2688 * This function is intended to be used during early probing on devices where
2689 * more than one panel might be present. Because of its intended use it must
2690 * assume that the EDID of the panel is correct, at least as far as the ID
2691 * is concerned (in other words, we don't process any overrides here).
2693 * NOTE: it's expected that this function and drm_do_get_edid() will both
2694 * be read the EDID, but there is no caching between them. Since we're only
2695 * reading the first block, hopefully this extra overhead won't be too big.
2697 * Return: A 32-bit ID that should be different for each make/model of panel.
2698 * See the functions drm_edid_encode_panel_id() and
2699 * drm_edid_decode_panel_id() for some details on the structure of this
2703 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2705 enum edid_block_status status;
2710 * There are no manufacturer IDs of 0, so if there is a problem reading
2711 * the EDID then we'll just return 0.
2714 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2718 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2720 edid_block_status_print(status, base_block, 0);
2722 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2723 panel_id = edid_extract_panel_id(base_block);
2729 EXPORT_SYMBOL(drm_edid_get_panel_id);
2732 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2733 * @connector: connector we're probing
2734 * @adapter: I2C adapter to use for DDC
2736 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2737 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2738 * switch DDC to the GPU which is retrieving EDID.
2740 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2742 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2743 struct i2c_adapter *adapter)
2745 struct drm_device *dev = connector->dev;
2746 struct pci_dev *pdev = to_pci_dev(dev->dev);
2749 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2752 vga_switcheroo_lock_ddc(pdev);
2753 edid = drm_get_edid(connector, adapter);
2754 vga_switcheroo_unlock_ddc(pdev);
2758 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2761 * drm_edid_duplicate - duplicate an EDID and the extensions
2762 * @edid: EDID to duplicate
2764 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2766 struct edid *drm_edid_duplicate(const struct edid *edid)
2768 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2770 EXPORT_SYMBOL(drm_edid_duplicate);
2772 /*** EDID parsing ***/
2775 * edid_get_quirks - return quirk flags for a given EDID
2776 * @drm_edid: EDID to process
2778 * This tells subsequent routines what fixes they need to apply.
2780 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2782 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2783 const struct edid_quirk *quirk;
2786 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2787 quirk = &edid_quirk_list[i];
2788 if (quirk->panel_id == panel_id)
2789 return quirk->quirks;
2795 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2796 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2799 * Walk the mode list for connector, clearing the preferred status on existing
2800 * modes and setting it anew for the right mode ala quirks.
2802 static void edid_fixup_preferred(struct drm_connector *connector,
2805 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2806 int target_refresh = 0;
2807 int cur_vrefresh, preferred_vrefresh;
2809 if (list_empty(&connector->probed_modes))
2812 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2813 target_refresh = 60;
2814 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2815 target_refresh = 75;
2817 preferred_mode = list_first_entry(&connector->probed_modes,
2818 struct drm_display_mode, head);
2820 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2821 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2823 if (cur_mode == preferred_mode)
2826 /* Largest mode is preferred */
2827 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2828 preferred_mode = cur_mode;
2830 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2831 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2832 /* At a given size, try to get closest to target refresh */
2833 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2834 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2835 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2836 preferred_mode = cur_mode;
2840 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2844 mode_is_rb(const struct drm_display_mode *mode)
2846 return (mode->htotal - mode->hdisplay == 160) &&
2847 (mode->hsync_end - mode->hdisplay == 80) &&
2848 (mode->hsync_end - mode->hsync_start == 32) &&
2849 (mode->vsync_start - mode->vdisplay == 3);
2853 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2854 * @dev: Device to duplicate against
2855 * @hsize: Mode width
2856 * @vsize: Mode height
2857 * @fresh: Mode refresh rate
2858 * @rb: Mode reduced-blanking-ness
2860 * Walk the DMT mode list looking for a match for the given parameters.
2862 * Return: A newly allocated copy of the mode, or NULL if not found.
2864 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2865 int hsize, int vsize, int fresh,
2870 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2871 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2873 if (hsize != ptr->hdisplay)
2875 if (vsize != ptr->vdisplay)
2877 if (fresh != drm_mode_vrefresh(ptr))
2879 if (rb != mode_is_rb(ptr))
2882 return drm_mode_duplicate(dev, ptr);
2887 EXPORT_SYMBOL(drm_mode_find_dmt);
2889 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2891 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2892 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2893 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2895 return descriptor->pixel_clock == 0 &&
2896 descriptor->data.other_data.pad1 == 0 &&
2897 descriptor->data.other_data.type == type;
2900 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2902 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2904 return descriptor->pixel_clock != 0;
2907 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2910 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2914 const u8 *det_base = ext + d;
2916 if (d < 4 || d > 127)
2920 for (i = 0; i < n; i++)
2921 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2925 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2927 unsigned int i, n = min((int)ext[0x02], 6);
2928 const u8 *det_base = ext + 5;
2931 return; /* unknown version */
2933 for (i = 0; i < n; i++)
2934 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2937 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
2938 detailed_cb *cb, void *closure)
2940 struct drm_edid_iter edid_iter;
2947 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2948 cb(&drm_edid->edid->detailed_timings[i], closure);
2950 drm_edid_iter_begin(drm_edid, &edid_iter);
2951 drm_edid_iter_for_each(ext, &edid_iter) {
2954 cea_for_each_detailed_block(ext, cb, closure);
2957 vtb_for_each_detailed_block(ext, cb, closure);
2963 drm_edid_iter_end(&edid_iter);
2967 is_rb(const struct detailed_timing *descriptor, void *data)
2971 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2974 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2975 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2977 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2978 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
2982 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2984 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
2986 if (drm_edid->edid->revision >= 4) {
2989 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
2993 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2997 find_gtf2(const struct detailed_timing *descriptor, void *data)
2999 const struct detailed_timing **res = data;
3001 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3004 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3006 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3010 /* Secondary GTF curve kicks in above some break frequency */
3012 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3014 const struct detailed_timing *descriptor = NULL;
3016 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3018 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3020 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3024 drm_gtf2_2c(const struct drm_edid *drm_edid)
3026 const struct detailed_timing *descriptor = NULL;
3028 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3030 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3032 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3036 drm_gtf2_m(const struct drm_edid *drm_edid)
3038 const struct detailed_timing *descriptor = NULL;
3040 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3042 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3044 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3048 drm_gtf2_k(const struct drm_edid *drm_edid)
3050 const struct detailed_timing *descriptor = NULL;
3052 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3054 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3056 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3060 drm_gtf2_2j(const struct drm_edid *drm_edid)
3062 const struct detailed_timing *descriptor = NULL;
3064 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3066 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3068 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3072 get_timing_level(const struct detailed_timing *descriptor, void *data)
3076 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3079 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3081 switch (descriptor->data.other_data.data.range.flags) {
3082 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3085 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3088 case DRM_EDID_CVT_SUPPORT_FLAG:
3096 /* Get standard timing level (CVT/GTF/DMT). */
3097 static int standard_timing_level(const struct drm_edid *drm_edid)
3099 const struct edid *edid = drm_edid->edid;
3101 if (edid->revision >= 4) {
3103 * If the range descriptor doesn't
3104 * indicate otherwise default to CVT
3106 int ret = LEVEL_CVT;
3108 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3111 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3113 } else if (edid->revision >= 2) {
3121 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3122 * monitors fill with ascii space (0x20) instead.
3125 bad_std_timing(u8 a, u8 b)
3127 return (a == 0x00 && b == 0x00) ||
3128 (a == 0x01 && b == 0x01) ||
3129 (a == 0x20 && b == 0x20);
3132 static int drm_mode_hsync(const struct drm_display_mode *mode)
3134 if (mode->htotal <= 0)
3137 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3140 static struct drm_display_mode *
3141 drm_gtf2_mode(struct drm_device *dev,
3142 const struct drm_edid *drm_edid,
3143 int hsize, int vsize, int vrefresh_rate)
3145 struct drm_display_mode *mode;
3148 * This is potentially wrong if there's ever a monitor with
3149 * more than one ranges section, each claiming a different
3150 * secondary GTF curve. Please don't do that.
3152 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3156 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3157 drm_mode_destroy(dev, mode);
3158 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3159 vrefresh_rate, 0, 0,
3160 drm_gtf2_m(drm_edid),
3161 drm_gtf2_2c(drm_edid),
3162 drm_gtf2_k(drm_edid),
3163 drm_gtf2_2j(drm_edid));
3170 * Take the standard timing params (in this case width, aspect, and refresh)
3171 * and convert them into a real mode using CVT/GTF/DMT.
3173 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3174 const struct drm_edid *drm_edid,
3175 const struct std_timing *t)
3177 struct drm_device *dev = connector->dev;
3178 struct drm_display_mode *m, *mode = NULL;
3181 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3182 >> EDID_TIMING_ASPECT_SHIFT;
3183 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3184 >> EDID_TIMING_VFREQ_SHIFT;
3185 int timing_level = standard_timing_level(drm_edid);
3187 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3190 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3191 hsize = t->hsize * 8 + 248;
3192 /* vrefresh_rate = vfreq + 60 */
3193 vrefresh_rate = vfreq + 60;
3194 /* the vdisplay is calculated based on the aspect ratio */
3195 if (aspect_ratio == 0) {
3196 if (drm_edid->edid->revision < 3)
3199 vsize = (hsize * 10) / 16;
3200 } else if (aspect_ratio == 1)
3201 vsize = (hsize * 3) / 4;
3202 else if (aspect_ratio == 2)
3203 vsize = (hsize * 4) / 5;
3205 vsize = (hsize * 9) / 16;
3207 /* HDTV hack, part 1 */
3208 if (vrefresh_rate == 60 &&
3209 ((hsize == 1360 && vsize == 765) ||
3210 (hsize == 1368 && vsize == 769))) {
3216 * If this connector already has a mode for this size and refresh
3217 * rate (because it came from detailed or CVT info), use that
3218 * instead. This way we don't have to guess at interlace or
3221 list_for_each_entry(m, &connector->probed_modes, head)
3222 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3223 drm_mode_vrefresh(m) == vrefresh_rate)
3226 /* HDTV hack, part 2 */
3227 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3228 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3232 mode->hdisplay = 1366;
3233 mode->hsync_start = mode->hsync_start - 1;
3234 mode->hsync_end = mode->hsync_end - 1;
3238 /* check whether it can be found in default mode table */
3239 if (drm_monitor_supports_rb(drm_edid)) {
3240 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3245 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3249 /* okay, generate it */
3250 switch (timing_level) {
3254 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3257 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3260 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3268 * EDID is delightfully ambiguous about how interlaced modes are to be
3269 * encoded. Our internal representation is of frame height, but some
3270 * HDTV detailed timings are encoded as field height.
3272 * The format list here is from CEA, in frame size. Technically we
3273 * should be checking refresh rate too. Whatever.
3276 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3277 const struct detailed_pixel_timing *pt)
3280 static const struct {
3282 } cea_interlaced[] = {
3292 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3295 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3296 if ((mode->hdisplay == cea_interlaced[i].w) &&
3297 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3298 mode->vdisplay *= 2;
3299 mode->vsync_start *= 2;
3300 mode->vsync_end *= 2;
3306 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3310 * Create a new mode from an EDID detailed timing section. An EDID detailed
3311 * timing block contains enough info for us to create and return a new struct
3314 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
3315 const struct drm_edid *drm_edid,
3316 const struct detailed_timing *timing,
3319 struct drm_display_mode *mode;
3320 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3321 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3322 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3323 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3324 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3325 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3326 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3327 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3328 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3330 /* ignore tiny modes */
3331 if (hactive < 64 || vactive < 64)
3334 if (pt->misc & DRM_EDID_PT_STEREO) {
3335 DRM_DEBUG_KMS("stereo mode not supported\n");
3338 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3339 DRM_DEBUG_KMS("composite sync not supported\n");
3342 /* it is incorrect if hsync/vsync width is zero */
3343 if (!hsync_pulse_width || !vsync_pulse_width) {
3344 DRM_DEBUG_KMS("Incorrect Detailed timing. "
3345 "Wrong Hsync/Vsync pulse width\n");
3349 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3350 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3357 mode = drm_mode_create(dev);
3361 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3362 mode->clock = 1088 * 10;
3364 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3366 mode->hdisplay = hactive;
3367 mode->hsync_start = mode->hdisplay + hsync_offset;
3368 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3369 mode->htotal = mode->hdisplay + hblank;
3371 mode->vdisplay = vactive;
3372 mode->vsync_start = mode->vdisplay + vsync_offset;
3373 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3374 mode->vtotal = mode->vdisplay + vblank;
3376 /* Some EDIDs have bogus h/vtotal values */
3377 if (mode->hsync_end > mode->htotal)
3378 mode->htotal = mode->hsync_end + 1;
3379 if (mode->vsync_end > mode->vtotal)
3380 mode->vtotal = mode->vsync_end + 1;
3382 drm_mode_do_interlace_quirk(mode, pt);
3384 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3385 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3387 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3388 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3389 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3390 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3394 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3395 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3397 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3398 mode->width_mm *= 10;
3399 mode->height_mm *= 10;
3402 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3403 mode->width_mm = drm_edid->edid->width_cm * 10;
3404 mode->height_mm = drm_edid->edid->height_cm * 10;
3407 mode->type = DRM_MODE_TYPE_DRIVER;
3408 drm_mode_set_name(mode);
3414 mode_in_hsync_range(const struct drm_display_mode *mode,
3415 const struct edid *edid, const u8 *t)
3417 int hsync, hmin, hmax;
3420 if (edid->revision >= 4)
3421 hmin += ((t[4] & 0x04) ? 255 : 0);
3423 if (edid->revision >= 4)
3424 hmax += ((t[4] & 0x08) ? 255 : 0);
3425 hsync = drm_mode_hsync(mode);
3427 return (hsync <= hmax && hsync >= hmin);
3431 mode_in_vsync_range(const struct drm_display_mode *mode,
3432 const struct edid *edid, const u8 *t)
3434 int vsync, vmin, vmax;
3437 if (edid->revision >= 4)
3438 vmin += ((t[4] & 0x01) ? 255 : 0);
3440 if (edid->revision >= 4)
3441 vmax += ((t[4] & 0x02) ? 255 : 0);
3442 vsync = drm_mode_vrefresh(mode);
3444 return (vsync <= vmax && vsync >= vmin);
3448 range_pixel_clock(const struct edid *edid, const u8 *t)
3451 if (t[9] == 0 || t[9] == 255)
3454 /* 1.4 with CVT support gives us real precision, yay */
3455 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3456 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3458 /* 1.3 is pathetic, so fuzz up a bit */
3459 return t[9] * 10000 + 5001;
3462 static bool mode_in_range(const struct drm_display_mode *mode,
3463 const struct drm_edid *drm_edid,
3464 const struct detailed_timing *timing)
3466 const struct edid *edid = drm_edid->edid;
3468 const u8 *t = (const u8 *)timing;
3470 if (!mode_in_hsync_range(mode, edid, t))
3473 if (!mode_in_vsync_range(mode, edid, t))
3476 if ((max_clock = range_pixel_clock(edid, t)))
3477 if (mode->clock > max_clock)
3480 /* 1.4 max horizontal check */
3481 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3482 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3485 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3491 static bool valid_inferred_mode(const struct drm_connector *connector,
3492 const struct drm_display_mode *mode)
3494 const struct drm_display_mode *m;
3497 list_for_each_entry(m, &connector->probed_modes, head) {
3498 if (mode->hdisplay == m->hdisplay &&
3499 mode->vdisplay == m->vdisplay &&
3500 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3501 return false; /* duplicated */
3502 if (mode->hdisplay <= m->hdisplay &&
3503 mode->vdisplay <= m->vdisplay)
3509 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3510 const struct drm_edid *drm_edid,
3511 const struct detailed_timing *timing)
3514 struct drm_display_mode *newmode;
3515 struct drm_device *dev = connector->dev;
3517 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3518 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3519 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3520 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3522 drm_mode_probed_add(connector, newmode);
3531 /* fix up 1366x768 mode from 1368x768;
3532 * GFT/CVT can't express 1366 width which isn't dividable by 8
3534 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3536 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3537 mode->hdisplay = 1366;
3538 mode->hsync_start--;
3540 drm_mode_set_name(mode);
3544 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3545 const struct drm_edid *drm_edid,
3546 const struct detailed_timing *timing)
3549 struct drm_display_mode *newmode;
3550 struct drm_device *dev = connector->dev;
3552 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3553 const struct minimode *m = &extra_modes[i];
3555 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3559 drm_mode_fixup_1366x768(newmode);
3560 if (!mode_in_range(newmode, drm_edid, timing) ||
3561 !valid_inferred_mode(connector, newmode)) {
3562 drm_mode_destroy(dev, newmode);
3566 drm_mode_probed_add(connector, newmode);
3573 static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3574 const struct drm_edid *drm_edid,
3575 const struct detailed_timing *timing)
3578 struct drm_display_mode *newmode;
3579 struct drm_device *dev = connector->dev;
3581 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3582 const struct minimode *m = &extra_modes[i];
3584 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3588 drm_mode_fixup_1366x768(newmode);
3589 if (!mode_in_range(newmode, drm_edid, timing) ||
3590 !valid_inferred_mode(connector, newmode)) {
3591 drm_mode_destroy(dev, newmode);
3595 drm_mode_probed_add(connector, newmode);
3602 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3603 const struct drm_edid *drm_edid,
3604 const struct detailed_timing *timing)
3607 struct drm_display_mode *newmode;
3608 struct drm_device *dev = connector->dev;
3609 bool rb = drm_monitor_supports_rb(drm_edid);
3611 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3612 const struct minimode *m = &extra_modes[i];
3614 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3618 drm_mode_fixup_1366x768(newmode);
3619 if (!mode_in_range(newmode, drm_edid, timing) ||
3620 !valid_inferred_mode(connector, newmode)) {
3621 drm_mode_destroy(dev, newmode);
3625 drm_mode_probed_add(connector, newmode);
3633 do_inferred_modes(const struct detailed_timing *timing, void *c)
3635 struct detailed_mode_closure *closure = c;
3636 const struct detailed_non_pixel *data = &timing->data.other_data;
3637 const struct detailed_data_monitor_range *range = &data->data.range;
3639 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3642 closure->modes += drm_dmt_modes_for_range(closure->connector,
3646 if (closure->drm_edid->edid->revision < 2)
3647 return; /* GTF not defined yet */
3649 switch (range->flags) {
3650 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3651 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3655 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3656 closure->modes += drm_gtf_modes_for_range(closure->connector,
3660 case DRM_EDID_CVT_SUPPORT_FLAG:
3661 if (closure->drm_edid->edid->revision < 4)
3664 closure->modes += drm_cvt_modes_for_range(closure->connector,
3668 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3674 static int add_inferred_modes(struct drm_connector *connector,
3675 const struct drm_edid *drm_edid)
3677 struct detailed_mode_closure closure = {
3678 .connector = connector,
3679 .drm_edid = drm_edid,
3682 if (drm_edid->edid->revision >= 1)
3683 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3685 return closure.modes;
3689 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3691 int i, j, m, modes = 0;
3692 struct drm_display_mode *mode;
3693 const u8 *est = ((const u8 *)timing) + 6;
3695 for (i = 0; i < 6; i++) {
3696 for (j = 7; j >= 0; j--) {
3697 m = (i * 8) + (7 - j);
3698 if (m >= ARRAY_SIZE(est3_modes))
3700 if (est[i] & (1 << j)) {
3701 mode = drm_mode_find_dmt(connector->dev,
3707 drm_mode_probed_add(connector, mode);
3718 do_established_modes(const struct detailed_timing *timing, void *c)
3720 struct detailed_mode_closure *closure = c;
3722 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3725 closure->modes += drm_est3_modes(closure->connector, timing);
3729 * Get established modes from EDID and add them. Each EDID block contains a
3730 * bitmap of the supported "established modes" list (defined above). Tease them
3731 * out and add them to the global modes list.
3733 static int add_established_modes(struct drm_connector *connector,
3734 const struct drm_edid *drm_edid)
3736 struct drm_device *dev = connector->dev;
3737 const struct edid *edid = drm_edid->edid;
3738 unsigned long est_bits = edid->established_timings.t1 |
3739 (edid->established_timings.t2 << 8) |
3740 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3742 struct detailed_mode_closure closure = {
3743 .connector = connector,
3744 .drm_edid = drm_edid,
3747 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3748 if (est_bits & (1<<i)) {
3749 struct drm_display_mode *newmode;
3751 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3753 drm_mode_probed_add(connector, newmode);
3759 if (edid->revision >= 1)
3760 drm_for_each_detailed_block(drm_edid, do_established_modes,
3763 return modes + closure.modes;
3767 do_standard_modes(const struct detailed_timing *timing, void *c)
3769 struct detailed_mode_closure *closure = c;
3770 const struct detailed_non_pixel *data = &timing->data.other_data;
3771 struct drm_connector *connector = closure->connector;
3774 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3777 for (i = 0; i < 6; i++) {
3778 const struct std_timing *std = &data->data.timings[i];
3779 struct drm_display_mode *newmode;
3781 newmode = drm_mode_std(connector, closure->drm_edid, std);
3783 drm_mode_probed_add(connector, newmode);
3790 * Get standard modes from EDID and add them. Standard modes can be calculated
3791 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3792 * add them to the list.
3794 static int add_standard_modes(struct drm_connector *connector,
3795 const struct drm_edid *drm_edid)
3798 struct detailed_mode_closure closure = {
3799 .connector = connector,
3800 .drm_edid = drm_edid,
3803 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3804 struct drm_display_mode *newmode;
3806 newmode = drm_mode_std(connector, drm_edid,
3807 &drm_edid->edid->standard_timings[i]);
3809 drm_mode_probed_add(connector, newmode);
3814 if (drm_edid->edid->revision >= 1)
3815 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3818 /* XXX should also look for standard codes in VTB blocks */
3820 return modes + closure.modes;
3823 static int drm_cvt_modes(struct drm_connector *connector,
3824 const struct detailed_timing *timing)
3826 int i, j, modes = 0;
3827 struct drm_display_mode *newmode;
3828 struct drm_device *dev = connector->dev;
3829 const struct cvt_timing *cvt;
3830 const int rates[] = { 60, 85, 75, 60, 50 };
3831 const u8 empty[3] = { 0, 0, 0 };
3833 for (i = 0; i < 4; i++) {
3836 cvt = &(timing->data.other_data.data.cvt[i]);
3838 if (!memcmp(cvt->code, empty, 3))
3841 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3842 switch (cvt->code[1] & 0x0c) {
3843 /* default - because compiler doesn't see that we've enumerated all cases */
3846 width = height * 4 / 3;
3849 width = height * 16 / 9;
3852 width = height * 16 / 10;
3855 width = height * 15 / 9;
3859 for (j = 1; j < 5; j++) {
3860 if (cvt->code[2] & (1 << j)) {
3861 newmode = drm_cvt_mode(dev, width, height,
3865 drm_mode_probed_add(connector, newmode);
3876 do_cvt_mode(const struct detailed_timing *timing, void *c)
3878 struct detailed_mode_closure *closure = c;
3880 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3883 closure->modes += drm_cvt_modes(closure->connector, timing);
3887 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
3889 struct detailed_mode_closure closure = {
3890 .connector = connector,
3891 .drm_edid = drm_edid,
3894 if (drm_edid->edid->revision >= 3)
3895 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
3897 /* XXX should also look for CVT codes in VTB blocks */
3899 return closure.modes;
3902 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3905 do_detailed_mode(const struct detailed_timing *timing, void *c)
3907 struct detailed_mode_closure *closure = c;
3908 struct drm_display_mode *newmode;
3910 if (!is_detailed_timing_descriptor(timing))
3913 newmode = drm_mode_detailed(closure->connector->dev,
3914 closure->drm_edid, timing,
3919 if (closure->preferred)
3920 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3923 * Detailed modes are limited to 10kHz pixel clock resolution,
3924 * so fix up anything that looks like CEA/HDMI mode, but the clock
3925 * is just slightly off.
3927 fixup_detailed_cea_mode_clock(newmode);
3929 drm_mode_probed_add(closure->connector, newmode);
3931 closure->preferred = false;
3935 * add_detailed_modes - Add modes from detailed timings
3936 * @connector: attached connector
3937 * @drm_edid: EDID block to scan
3938 * @quirks: quirks to apply
3940 static int add_detailed_modes(struct drm_connector *connector,
3941 const struct drm_edid *drm_edid, u32 quirks)
3943 struct detailed_mode_closure closure = {
3944 .connector = connector,
3945 .drm_edid = drm_edid,
3949 if (drm_edid->edid->revision >= 4)
3950 closure.preferred = true; /* first detailed timing is always preferred */
3953 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
3955 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
3957 return closure.modes;
3960 /* CTA-861-H Table 60 - CTA Tag Codes */
3961 #define CTA_DB_AUDIO 1
3962 #define CTA_DB_VIDEO 2
3963 #define CTA_DB_VENDOR 3
3964 #define CTA_DB_SPEAKER 4
3965 #define CTA_DB_EXTENDED_TAG 7
3967 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
3968 #define CTA_EXT_DB_VIDEO_CAP 0
3969 #define CTA_EXT_DB_VENDOR 1
3970 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
3971 #define CTA_EXT_DB_420_VIDEO_DATA 14
3972 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
3973 #define CTA_EXT_DB_HF_EEODB 0x78
3974 #define CTA_EXT_DB_HF_SCDB 0x79
3976 #define EDID_BASIC_AUDIO (1 << 6)
3977 #define EDID_CEA_YCRCB444 (1 << 5)
3978 #define EDID_CEA_YCRCB422 (1 << 4)
3979 #define EDID_CEA_VCDB_QS (1 << 6)
3982 * Search EDID for CEA extension block.
3984 * FIXME: Prefer not returning pointers to raw EDID data.
3986 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
3987 int ext_id, int *ext_index)
3989 const u8 *edid_ext = NULL;
3992 /* No EDID or EDID extensions */
3993 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
3996 /* Find CEA extension */
3997 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
3998 edid_ext = drm_edid_extension_block_data(drm_edid, i);
3999 if (edid_block_tag(edid_ext) == ext_id)
4003 if (i >= drm_edid_extension_block_count(drm_edid))
4011 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4012 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4014 const struct displayid_block *block;
4015 struct displayid_iter iter;
4019 /* Look for a top level CEA extension block */
4020 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4023 /* CEA blocks can also be found embedded in a DisplayID block */
4024 displayid_iter_edid_begin(drm_edid, &iter);
4025 displayid_iter_for_each(block, &iter) {
4026 if (block->tag == DATA_BLOCK_CTA) {
4031 displayid_iter_end(&iter);
4036 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4038 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4039 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4041 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4042 return &edid_cea_modes_1[vic - 1];
4043 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4044 return &edid_cea_modes_193[vic - 193];
4048 static u8 cea_num_vics(void)
4050 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4053 static u8 cea_next_vic(u8 vic)
4055 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4061 * Calculate the alternate clock for the CEA mode
4062 * (60Hz vs. 59.94Hz etc.)
4065 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4067 unsigned int clock = cea_mode->clock;
4069 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4073 * edid_cea_modes contains the 59.94Hz
4074 * variant for 240 and 480 line modes,
4075 * and the 60Hz variant otherwise.
4077 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4078 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4080 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4086 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4089 * For certain VICs the spec allows the vertical
4090 * front porch to vary by one or two lines.
4092 * cea_modes[] stores the variant with the shortest
4093 * vertical front porch. We can adjust the mode to
4094 * get the other variants by simply increasing the
4095 * vertical front porch length.
4097 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4098 cea_mode_for_vic(9)->vtotal != 262 ||
4099 cea_mode_for_vic(12)->vtotal != 262 ||
4100 cea_mode_for_vic(13)->vtotal != 262 ||
4101 cea_mode_for_vic(23)->vtotal != 312 ||
4102 cea_mode_for_vic(24)->vtotal != 312 ||
4103 cea_mode_for_vic(27)->vtotal != 312 ||
4104 cea_mode_for_vic(28)->vtotal != 312);
4106 if (((vic == 8 || vic == 9 ||
4107 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4108 ((vic == 23 || vic == 24 ||
4109 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4110 mode->vsync_start++;
4120 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4121 unsigned int clock_tolerance)
4123 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4126 if (!to_match->clock)
4129 if (to_match->picture_aspect_ratio)
4130 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4132 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4133 struct drm_display_mode cea_mode;
4134 unsigned int clock1, clock2;
4136 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4138 /* Check both 60Hz and 59.94Hz */
4139 clock1 = cea_mode.clock;
4140 clock2 = cea_mode_alternate_clock(&cea_mode);
4142 if (abs(to_match->clock - clock1) > clock_tolerance &&
4143 abs(to_match->clock - clock2) > clock_tolerance)
4147 if (drm_mode_match(to_match, &cea_mode, match_flags))
4149 } while (cea_mode_alternate_timings(vic, &cea_mode));
4156 * drm_match_cea_mode - look for a CEA mode matching given mode
4157 * @to_match: display mode
4159 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4162 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4164 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4167 if (!to_match->clock)
4170 if (to_match->picture_aspect_ratio)
4171 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4173 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4174 struct drm_display_mode cea_mode;
4175 unsigned int clock1, clock2;
4177 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4179 /* Check both 60Hz and 59.94Hz */
4180 clock1 = cea_mode.clock;
4181 clock2 = cea_mode_alternate_clock(&cea_mode);
4183 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4184 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4188 if (drm_mode_match(to_match, &cea_mode, match_flags))
4190 } while (cea_mode_alternate_timings(vic, &cea_mode));
4195 EXPORT_SYMBOL(drm_match_cea_mode);
4197 static bool drm_valid_cea_vic(u8 vic)
4199 return cea_mode_for_vic(vic) != NULL;
4202 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4204 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4207 return mode->picture_aspect_ratio;
4209 return HDMI_PICTURE_ASPECT_NONE;
4212 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4214 return edid_4k_modes[video_code].picture_aspect_ratio;
4218 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4222 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4224 return cea_mode_alternate_clock(hdmi_mode);
4227 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4228 unsigned int clock_tolerance)
4230 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4233 if (!to_match->clock)
4236 if (to_match->picture_aspect_ratio)
4237 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4239 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4240 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4241 unsigned int clock1, clock2;
4243 /* Make sure to also match alternate clocks */
4244 clock1 = hdmi_mode->clock;
4245 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4247 if (abs(to_match->clock - clock1) > clock_tolerance &&
4248 abs(to_match->clock - clock2) > clock_tolerance)
4251 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4259 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4260 * @to_match: display mode
4262 * An HDMI mode is one defined in the HDMI vendor specific block.
4264 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4266 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4268 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4271 if (!to_match->clock)
4274 if (to_match->picture_aspect_ratio)
4275 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4277 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4278 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4279 unsigned int clock1, clock2;
4281 /* Make sure to also match alternate clocks */
4282 clock1 = hdmi_mode->clock;
4283 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4285 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4286 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4287 drm_mode_match(to_match, hdmi_mode, match_flags))
4293 static bool drm_valid_hdmi_vic(u8 vic)
4295 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4298 static int add_alternate_cea_modes(struct drm_connector *connector,
4299 const struct drm_edid *drm_edid)
4301 struct drm_device *dev = connector->dev;
4302 struct drm_display_mode *mode, *tmp;
4306 /* Don't add CTA modes if the CTA extension block is missing */
4307 if (!drm_edid_has_cta_extension(drm_edid))
4311 * Go through all probed modes and create a new mode
4312 * with the alternate clock for certain CEA modes.
4314 list_for_each_entry(mode, &connector->probed_modes, head) {
4315 const struct drm_display_mode *cea_mode = NULL;
4316 struct drm_display_mode *newmode;
4317 u8 vic = drm_match_cea_mode(mode);
4318 unsigned int clock1, clock2;
4320 if (drm_valid_cea_vic(vic)) {
4321 cea_mode = cea_mode_for_vic(vic);
4322 clock2 = cea_mode_alternate_clock(cea_mode);
4324 vic = drm_match_hdmi_mode(mode);
4325 if (drm_valid_hdmi_vic(vic)) {
4326 cea_mode = &edid_4k_modes[vic];
4327 clock2 = hdmi_mode_alternate_clock(cea_mode);
4334 clock1 = cea_mode->clock;
4336 if (clock1 == clock2)
4339 if (mode->clock != clock1 && mode->clock != clock2)
4342 newmode = drm_mode_duplicate(dev, cea_mode);
4346 /* Carry over the stereo flags */
4347 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4350 * The current mode could be either variant. Make
4351 * sure to pick the "other" clock for the new mode.
4353 if (mode->clock != clock1)
4354 newmode->clock = clock1;
4356 newmode->clock = clock2;
4358 list_add_tail(&newmode->head, &list);
4361 list_for_each_entry_safe(mode, tmp, &list, head) {
4362 list_del(&mode->head);
4363 drm_mode_probed_add(connector, mode);
4370 static u8 svd_to_vic(u8 svd)
4372 /* 0-6 bit vic, 7th bit native mode indicator */
4373 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4379 static struct drm_display_mode *
4380 drm_display_mode_from_vic_index(struct drm_connector *connector,
4381 const u8 *video_db, u8 video_len,
4384 struct drm_device *dev = connector->dev;
4385 struct drm_display_mode *newmode;
4388 if (video_db == NULL || video_index >= video_len)
4391 /* CEA modes are numbered 1..127 */
4392 vic = svd_to_vic(video_db[video_index]);
4393 if (!drm_valid_cea_vic(vic))
4396 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4404 * do_y420vdb_modes - Parse YCBCR 420 only modes
4405 * @connector: connector corresponding to the HDMI sink
4406 * @svds: start of the data block of CEA YCBCR 420 VDB
4407 * @len: length of the CEA YCBCR 420 VDB
4409 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4410 * which contains modes which can be supported in YCBCR 420
4411 * output format only.
4413 static int do_y420vdb_modes(struct drm_connector *connector,
4414 const u8 *svds, u8 svds_len)
4417 struct drm_device *dev = connector->dev;
4418 struct drm_display_info *info = &connector->display_info;
4419 struct drm_hdmi_info *hdmi = &info->hdmi;
4421 for (i = 0; i < svds_len; i++) {
4422 u8 vic = svd_to_vic(svds[i]);
4423 struct drm_display_mode *newmode;
4425 if (!drm_valid_cea_vic(vic))
4428 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4431 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4432 drm_mode_probed_add(connector, newmode);
4437 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4442 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4443 * @connector: connector corresponding to the HDMI sink
4444 * @vic: CEA vic for the video mode to be added in the map
4446 * Makes an entry for a videomode in the YCBCR 420 bitmap
4449 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4451 u8 vic = svd_to_vic(svd);
4452 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4454 if (!drm_valid_cea_vic(vic))
4457 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4461 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4463 * @video_code: CEA VIC of the mode
4465 * Creates a new mode matching the specified CEA VIC.
4467 * Returns: A new drm_display_mode on success or NULL on failure
4469 struct drm_display_mode *
4470 drm_display_mode_from_cea_vic(struct drm_device *dev,
4473 const struct drm_display_mode *cea_mode;
4474 struct drm_display_mode *newmode;
4476 cea_mode = cea_mode_for_vic(video_code);
4480 newmode = drm_mode_duplicate(dev, cea_mode);
4486 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4489 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4492 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4494 for (i = 0; i < len; i++) {
4495 struct drm_display_mode *mode;
4497 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4500 * YCBCR420 capability block contains a bitmap which
4501 * gives the index of CEA modes from CEA VDB, which
4502 * can support YCBCR 420 sampling output also (apart
4503 * from RGB/YCBCR444 etc).
4504 * For example, if the bit 0 in bitmap is set,
4505 * first mode in VDB can support YCBCR420 output too.
4506 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4508 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4509 drm_add_cmdb_modes(connector, db[i]);
4511 drm_mode_probed_add(connector, mode);
4519 struct stereo_mandatory_mode {
4520 int width, height, vrefresh;
4524 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4525 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4526 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4528 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4530 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4531 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4532 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4533 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4534 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4538 stereo_match_mandatory(const struct drm_display_mode *mode,
4539 const struct stereo_mandatory_mode *stereo_mode)
4541 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4543 return mode->hdisplay == stereo_mode->width &&
4544 mode->vdisplay == stereo_mode->height &&
4545 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4546 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4549 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4551 struct drm_device *dev = connector->dev;
4552 const struct drm_display_mode *mode;
4553 struct list_head stereo_modes;
4556 INIT_LIST_HEAD(&stereo_modes);
4558 list_for_each_entry(mode, &connector->probed_modes, head) {
4559 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4560 const struct stereo_mandatory_mode *mandatory;
4561 struct drm_display_mode *new_mode;
4563 if (!stereo_match_mandatory(mode,
4564 &stereo_mandatory_modes[i]))
4567 mandatory = &stereo_mandatory_modes[i];
4568 new_mode = drm_mode_duplicate(dev, mode);
4572 new_mode->flags |= mandatory->flags;
4573 list_add_tail(&new_mode->head, &stereo_modes);
4578 list_splice_tail(&stereo_modes, &connector->probed_modes);
4583 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4585 struct drm_device *dev = connector->dev;
4586 struct drm_display_mode *newmode;
4588 if (!drm_valid_hdmi_vic(vic)) {
4589 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4593 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4597 drm_mode_probed_add(connector, newmode);
4602 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4603 const u8 *video_db, u8 video_len, u8 video_index)
4605 struct drm_display_mode *newmode;
4608 if (structure & (1 << 0)) {
4609 newmode = drm_display_mode_from_vic_index(connector, video_db,
4613 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4614 drm_mode_probed_add(connector, newmode);
4618 if (structure & (1 << 6)) {
4619 newmode = drm_display_mode_from_vic_index(connector, video_db,
4623 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4624 drm_mode_probed_add(connector, newmode);
4628 if (structure & (1 << 8)) {
4629 newmode = drm_display_mode_from_vic_index(connector, video_db,
4633 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4634 drm_mode_probed_add(connector, newmode);
4643 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4644 * @connector: connector corresponding to the HDMI sink
4645 * @db: start of the CEA vendor specific block
4646 * @len: length of the CEA block payload, ie. one can access up to db[len]
4648 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4649 * also adds the stereo 3d modes when applicable.
4652 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4653 const u8 *video_db, u8 video_len)
4655 struct drm_display_info *info = &connector->display_info;
4656 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4657 u8 vic_len, hdmi_3d_len = 0;
4664 /* no HDMI_Video_Present */
4665 if (!(db[8] & (1 << 5)))
4668 /* Latency_Fields_Present */
4669 if (db[8] & (1 << 7))
4672 /* I_Latency_Fields_Present */
4673 if (db[8] & (1 << 6))
4676 /* the declared length is not long enough for the 2 first bytes
4677 * of additional video format capabilities */
4678 if (len < (8 + offset + 2))
4683 if (db[8 + offset] & (1 << 7)) {
4684 modes += add_hdmi_mandatory_stereo_modes(connector);
4686 /* 3D_Multi_present */
4687 multi_present = (db[8 + offset] & 0x60) >> 5;
4691 vic_len = db[8 + offset] >> 5;
4692 hdmi_3d_len = db[8 + offset] & 0x1f;
4694 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4697 vic = db[9 + offset + i];
4698 modes += add_hdmi_mode(connector, vic);
4700 offset += 1 + vic_len;
4702 if (multi_present == 1)
4704 else if (multi_present == 2)
4709 if (len < (8 + offset + hdmi_3d_len - 1))
4712 if (hdmi_3d_len < multi_len)
4715 if (multi_present == 1 || multi_present == 2) {
4716 /* 3D_Structure_ALL */
4717 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4719 /* check if 3D_MASK is present */
4720 if (multi_present == 2)
4721 mask = (db[10 + offset] << 8) | db[11 + offset];
4725 for (i = 0; i < 16; i++) {
4726 if (mask & (1 << i))
4727 modes += add_3d_struct_modes(connector,
4734 offset += multi_len;
4736 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4738 struct drm_display_mode *newmode = NULL;
4739 unsigned int newflag = 0;
4740 bool detail_present;
4742 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4744 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4747 /* 2D_VIC_order_X */
4748 vic_index = db[8 + offset + i] >> 4;
4750 /* 3D_Structure_X */
4751 switch (db[8 + offset + i] & 0x0f) {
4753 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4756 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4760 if ((db[9 + offset + i] >> 4) == 1)
4761 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4766 newmode = drm_display_mode_from_vic_index(connector,
4772 newmode->flags |= newflag;
4773 drm_mode_probed_add(connector, newmode);
4784 info->has_hdmi_infoframe = true;
4789 cea_revision(const u8 *cea)
4792 * FIXME is this correct for the DispID variant?
4793 * The DispID spec doesn't really specify whether
4794 * this is the revision of the CEA extension or
4795 * the DispID CEA data block. And the only value
4796 * given as an example is 0.
4802 * CTA Data Block iterator.
4804 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4807 * struct cea_db *db:
4808 * struct cea_db_iter iter;
4810 * cea_db_iter_edid_begin(edid, &iter);
4811 * cea_db_iter_for_each(db, &iter) {
4812 * // do stuff with db
4814 * cea_db_iter_end(&iter);
4816 struct cea_db_iter {
4817 struct drm_edid_iter edid_iter;
4818 struct displayid_iter displayid_iter;
4820 /* Current Data Block Collection. */
4821 const u8 *collection;
4823 /* Current Data Block index in current collection. */
4826 /* End index in current collection. */
4830 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4836 static int cea_db_tag(const struct cea_db *db)
4838 return db->tag_length >> 5;
4841 static int cea_db_payload_len(const void *_db)
4843 /* FIXME: Transition to passing struct cea_db * everywhere. */
4844 const struct cea_db *db = _db;
4846 return db->tag_length & 0x1f;
4849 static const void *cea_db_data(const struct cea_db *db)
4854 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4856 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4857 cea_db_payload_len(db) >= 1 &&
4861 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4863 const u8 *data = cea_db_data(db);
4865 return cea_db_tag(db) == CTA_DB_VENDOR &&
4866 cea_db_payload_len(db) >= 3 &&
4867 oui(data[2], data[1], data[0]) == vendor_oui;
4870 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4871 struct cea_db_iter *iter)
4873 memset(iter, 0, sizeof(*iter));
4875 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4876 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4879 static const struct cea_db *
4880 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4882 const struct cea_db *db;
4884 if (!iter->collection)
4887 db = (const struct cea_db *)&iter->collection[iter->index];
4889 if (iter->index + sizeof(*db) <= iter->end &&
4890 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4898 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4900 static int cea_db_collection_size(const u8 *cta)
4904 if (d < 4 || d > 127)
4912 * - VESA E-EDID v1.4
4913 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4915 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4919 drm_edid_iter_for_each(ext, &iter->edid_iter) {
4922 /* Only support CTA Extension revision 3+ */
4923 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4926 size = cea_db_collection_size(ext);
4931 iter->end = iter->index + size;
4941 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4942 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4944 * Note that the above do not specify any connection between DisplayID Data
4945 * Block revision and CTA Extension versions.
4947 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4949 const struct displayid_block *block;
4951 displayid_iter_for_each(block, &iter->displayid_iter) {
4952 if (block->tag != DATA_BLOCK_CTA)
4956 * The displayid iterator has already verified the block bounds
4957 * in displayid_iter_block().
4959 iter->index = sizeof(*block);
4960 iter->end = iter->index + block->num_bytes;
4968 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
4970 const struct cea_db *db;
4972 if (iter->collection) {
4973 /* Current collection should always be valid. */
4974 db = __cea_db_iter_current_block(iter);
4976 iter->collection = NULL;
4980 /* Next block in CTA Data Block Collection */
4981 iter->index += sizeof(*db) + cea_db_payload_len(db);
4983 db = __cea_db_iter_current_block(iter);
4990 * Find the next CTA Data Block Collection. First iterate all
4991 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
4993 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
4994 * Extension, it's recommended that DisplayID extensions are
4995 * exposed after all of the CTA Extensions.
4997 iter->collection = __cea_db_iter_edid_next(iter);
4998 if (!iter->collection)
4999 iter->collection = __cea_db_iter_displayid_next(iter);
5001 if (!iter->collection)
5004 db = __cea_db_iter_current_block(iter);
5010 #define cea_db_iter_for_each(__db, __iter) \
5011 while (((__db) = __cea_db_iter_next(__iter)))
5013 static void cea_db_iter_end(struct cea_db_iter *iter)
5015 displayid_iter_end(&iter->displayid_iter);
5016 drm_edid_iter_end(&iter->edid_iter);
5018 memset(iter, 0, sizeof(*iter));
5021 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5023 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5024 cea_db_payload_len(db) >= 5;
5027 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5029 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5030 cea_db_payload_len(db) >= 7;
5033 static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5035 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5036 cea_db_payload_len(db) >= 2;
5039 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5041 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5042 cea_db_payload_len(db) == 21;
5045 static bool cea_db_is_vcdb(const struct cea_db *db)
5047 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5048 cea_db_payload_len(db) == 2;
5051 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5053 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5054 cea_db_payload_len(db) >= 7;
5057 static bool cea_db_is_y420cmdb(const struct cea_db *db)
5059 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5062 static bool cea_db_is_y420vdb(const struct cea_db *db)
5064 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5067 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5069 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5070 cea_db_payload_len(db) >= 3;
5074 * Get the HF-EEODB override extension block count from EDID.
5076 * The passed in EDID may be partially read, as long as it has at least two
5077 * blocks (base block and one extension block) if EDID extension count is > 0.
5079 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5080 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5081 * iterators instead.
5084 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5086 static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5090 /* No extensions according to base block, no HF-EEODB. */
5091 if (!edid_extension_block_count(edid))
5094 /* HF-EEODB is always in the first EDID extension block only */
5095 cta = edid_extension_block_data(edid, 0);
5096 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5099 /* Need to have the data block collection, and at least 3 bytes. */
5100 if (cea_db_collection_size(cta) < 3)
5104 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5105 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5106 * through 6 of Block 1 of the E-EDID.
5108 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5114 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
5117 struct drm_display_info *info = &connector->display_info;
5118 struct drm_hdmi_info *hdmi = &info->hdmi;
5119 u8 map_len = cea_db_payload_len(db) - 1;
5124 /* All CEA modes support ycbcr420 sampling also.*/
5125 hdmi->y420_cmdb_map = U64_MAX;
5126 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5131 * This map indicates which of the existing CEA block modes
5132 * from VDB can support YCBCR420 output too. So if bit=0 is
5133 * set, first mode from VDB can support YCBCR420 output too.
5134 * We will parse and keep this map, before parsing VDB itself
5135 * to avoid going through the same block again and again.
5137 * Spec is not clear about max possible size of this block.
5138 * Clamping max bitmap block size at 8 bytes. Every byte can
5139 * address 8 CEA modes, in this way this map can address
5140 * 8*8 = first 64 SVDs.
5142 if (WARN_ON_ONCE(map_len > 8))
5145 for (count = 0; count < map_len; count++)
5146 map |= (u64)db[2 + count] << (8 * count);
5149 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5151 hdmi->y420_cmdb_map = map;
5154 static int add_cea_modes(struct drm_connector *connector,
5155 const struct drm_edid *drm_edid)
5157 const struct cea_db *db;
5158 struct cea_db_iter iter;
5161 cea_db_iter_edid_begin(drm_edid, &iter);
5162 cea_db_iter_for_each(db, &iter) {
5163 const u8 *hdmi = NULL, *video = NULL;
5164 u8 hdmi_len = 0, video_len = 0;
5166 if (cea_db_tag(db) == CTA_DB_VIDEO) {
5167 video = cea_db_data(db);
5168 video_len = cea_db_payload_len(db);
5169 modes += do_cea_modes(connector, video, video_len);
5170 } else if (cea_db_is_hdmi_vsdb(db)) {
5171 /* FIXME: Switch to use cea_db_data() */
5172 hdmi = (const u8 *)db;
5173 hdmi_len = cea_db_payload_len(db);
5174 } else if (cea_db_is_y420vdb(db)) {
5175 const u8 *vdb420 = cea_db_data(db) + 1;
5177 /* Add 4:2:0(only) modes present in EDID */
5178 modes += do_y420vdb_modes(connector, vdb420,
5179 cea_db_payload_len(db) - 1);
5183 * We parse the HDMI VSDB after having added the cea modes as we
5184 * will be patching their flags when the sink supports stereo
5188 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
5191 cea_db_iter_end(&iter);
5196 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
5198 const struct drm_display_mode *cea_mode;
5199 int clock1, clock2, clock;
5204 * allow 5kHz clock difference either way to account for
5205 * the 10kHz clock resolution limit of detailed timings.
5207 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5208 if (drm_valid_cea_vic(vic)) {
5210 cea_mode = cea_mode_for_vic(vic);
5211 clock1 = cea_mode->clock;
5212 clock2 = cea_mode_alternate_clock(cea_mode);
5214 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5215 if (drm_valid_hdmi_vic(vic)) {
5217 cea_mode = &edid_4k_modes[vic];
5218 clock1 = cea_mode->clock;
5219 clock2 = hdmi_mode_alternate_clock(cea_mode);
5225 /* pick whichever is closest */
5226 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5231 if (mode->clock == clock)
5234 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5235 type, vic, mode->clock, clock);
5236 mode->clock = clock;
5239 static void drm_calculate_luminance_range(struct drm_connector *connector)
5241 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5242 struct drm_luminance_range_info *luminance_range =
5243 &connector->display_info.luminance_range;
5244 static const u8 pre_computed_values[] = {
5245 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5246 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5248 u32 max_avg, min_cll, max, min, q, r;
5250 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5253 max_avg = hdr_metadata->max_fall;
5254 min_cll = hdr_metadata->min_cll;
5257 * From the specification (CTA-861-G), for calculating the maximum
5258 * luminance we need to use:
5259 * Luminance = 50*2**(CV/32)
5260 * Where CV is a one-byte value.
5261 * For calculating this expression we may need float point precision;
5262 * to avoid this complexity level, we take advantage that CV is divided
5263 * by a constant. From the Euclids division algorithm, we know that CV
5264 * can be written as: CV = 32*q + r. Next, we replace CV in the
5265 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5266 * need to pre-compute the value of r/32. For pre-computing the values
5267 * We just used the following Ruby line:
5268 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5269 * The results of the above expressions can be verified at
5270 * pre_computed_values.
5274 max = (1 << q) * pre_computed_values[r];
5276 /* min luminance: maxLum * (CV/255)^2 / 100 */
5277 q = DIV_ROUND_CLOSEST(min_cll, 255);
5278 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5280 luminance_range->min_luminance = min;
5281 luminance_range->max_luminance = max;
5284 static uint8_t eotf_supported(const u8 *edid_ext)
5286 return edid_ext[2] &
5287 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5288 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5289 BIT(HDMI_EOTF_SMPTE_ST2084) |
5290 BIT(HDMI_EOTF_BT_2100_HLG));
5293 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5295 return edid_ext[3] &
5296 BIT(HDMI_STATIC_METADATA_TYPE1);
5300 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5304 len = cea_db_payload_len(db);
5306 connector->hdr_sink_metadata.hdmi_type1.eotf =
5308 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5309 hdr_metadata_type(db);
5312 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5314 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5316 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5318 /* Calculate only when all values are available */
5319 drm_calculate_luminance_range(connector);
5324 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5326 u8 len = cea_db_payload_len(db);
5328 if (len >= 6 && (db[6] & (1 << 7)))
5329 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5331 connector->latency_present[0] = db[8] >> 7;
5332 connector->latency_present[1] = (db[8] >> 6) & 1;
5335 connector->video_latency[0] = db[9];
5337 connector->audio_latency[0] = db[10];
5339 connector->video_latency[1] = db[11];
5341 connector->audio_latency[1] = db[12];
5343 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
5344 "video latency %d %d, "
5345 "audio latency %d %d\n",
5346 connector->latency_present[0],
5347 connector->latency_present[1],
5348 connector->video_latency[0],
5349 connector->video_latency[1],
5350 connector->audio_latency[0],
5351 connector->audio_latency[1]);
5355 monitor_name(const struct detailed_timing *timing, void *data)
5357 const char **res = data;
5359 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5362 *res = timing->data.other_data.data.str.str;
5365 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5367 const char *edid_name = NULL;
5370 if (!drm_edid || !name)
5373 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5374 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5375 if (edid_name[mnl] == 0x0a)
5378 name[mnl] = edid_name[mnl];
5385 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5386 * @edid: monitor EDID information
5387 * @name: pointer to a character array to hold the name of the monitor
5388 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5391 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5393 int name_length = 0;
5400 struct drm_edid drm_edid = {
5402 .size = edid_size(edid),
5405 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5406 memcpy(name, buf, name_length);
5409 name[name_length] = '\0';
5411 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5413 static void clear_eld(struct drm_connector *connector)
5415 memset(connector->eld, 0, sizeof(connector->eld));
5417 connector->latency_present[0] = false;
5418 connector->latency_present[1] = false;
5419 connector->video_latency[0] = 0;
5420 connector->audio_latency[0] = 0;
5421 connector->video_latency[1] = 0;
5422 connector->audio_latency[1] = 0;
5426 * drm_edid_to_eld - build ELD from EDID
5427 * @connector: connector corresponding to the HDMI/DP sink
5428 * @drm_edid: EDID to parse
5430 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5431 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5433 static void drm_edid_to_eld(struct drm_connector *connector,
5434 const struct drm_edid *drm_edid)
5436 const struct drm_display_info *info = &connector->display_info;
5437 const struct cea_db *db;
5438 struct cea_db_iter iter;
5439 uint8_t *eld = connector->eld;
5440 int total_sad_count = 0;
5443 clear_eld(connector);
5448 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5449 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
5451 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5452 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5454 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5456 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5457 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5458 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5459 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5461 cea_db_iter_edid_begin(drm_edid, &iter);
5462 cea_db_iter_for_each(db, &iter) {
5463 const u8 *data = cea_db_data(db);
5464 int len = cea_db_payload_len(db);
5467 switch (cea_db_tag(db)) {
5469 /* Audio Data Block, contains SADs */
5470 sad_count = min(len / 3, 15 - total_sad_count);
5472 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5473 data, sad_count * 3);
5474 total_sad_count += sad_count;
5476 case CTA_DB_SPEAKER:
5477 /* Speaker Allocation Data Block */
5479 eld[DRM_ELD_SPEAKER] = data[0];
5482 /* HDMI Vendor-Specific Data Block */
5483 if (cea_db_is_hdmi_vsdb(db))
5484 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5490 cea_db_iter_end(&iter);
5492 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5494 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5495 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5496 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5498 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5500 eld[DRM_ELD_BASELINE_ELD_LEN] =
5501 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5503 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
5504 drm_eld_size(eld), total_sad_count);
5507 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5508 struct cea_sad **sads)
5510 const struct cea_db *db;
5511 struct cea_db_iter iter;
5514 cea_db_iter_edid_begin(drm_edid, &iter);
5515 cea_db_iter_for_each(db, &iter) {
5516 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5519 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5520 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5523 for (j = 0; j < count; j++) {
5524 const u8 *sad = &db->data[j * 3];
5526 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5527 (*sads)[j].channels = sad[0] & 0x7;
5528 (*sads)[j].freq = sad[1] & 0x7F;
5529 (*sads)[j].byte2 = sad[2];
5534 cea_db_iter_end(&iter);
5536 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5542 * drm_edid_to_sad - extracts SADs from EDID
5543 * @edid: EDID to parse
5544 * @sads: pointer that will be set to the extracted SADs
5546 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5548 * Note: The returned pointer needs to be freed using kfree().
5550 * Return: The number of found SADs or negative number on error.
5552 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5554 struct drm_edid drm_edid;
5556 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5558 EXPORT_SYMBOL(drm_edid_to_sad);
5560 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5563 const struct cea_db *db;
5564 struct cea_db_iter iter;
5567 cea_db_iter_edid_begin(drm_edid, &iter);
5568 cea_db_iter_for_each(db, &iter) {
5569 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5570 cea_db_payload_len(db) == 3) {
5571 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5575 count = cea_db_payload_len(db);
5579 cea_db_iter_end(&iter);
5581 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5587 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5588 * @edid: EDID to parse
5589 * @sadb: pointer to the speaker block
5591 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5593 * Note: The returned pointer needs to be freed using kfree().
5595 * Return: The number of found Speaker Allocation Blocks or negative number on
5598 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5600 struct drm_edid drm_edid;
5602 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5605 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5608 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5609 * @connector: connector associated with the HDMI/DP sink
5610 * @mode: the display mode
5612 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5613 * the sink doesn't support audio or video.
5615 int drm_av_sync_delay(struct drm_connector *connector,
5616 const struct drm_display_mode *mode)
5618 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5621 if (!connector->latency_present[0])
5623 if (!connector->latency_present[1])
5626 a = connector->audio_latency[i];
5627 v = connector->video_latency[i];
5630 * HDMI/DP sink doesn't support audio or video?
5632 if (a == 255 || v == 255)
5636 * Convert raw EDID values to millisecond.
5637 * Treat unknown latency as 0ms.
5640 a = min(2 * (a - 1), 500);
5642 v = min(2 * (v - 1), 500);
5644 return max(v - a, 0);
5646 EXPORT_SYMBOL(drm_av_sync_delay);
5648 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5650 const struct cea_db *db;
5651 struct cea_db_iter iter;
5655 * Because HDMI identifier is in Vendor Specific Block,
5656 * search it from all data blocks of CEA extension.
5658 cea_db_iter_edid_begin(drm_edid, &iter);
5659 cea_db_iter_for_each(db, &iter) {
5660 if (cea_db_is_hdmi_vsdb(db)) {
5665 cea_db_iter_end(&iter);
5671 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5672 * @edid: monitor EDID information
5674 * Parse the CEA extension according to CEA-861-B.
5676 * Drivers that have added the modes parsed from EDID to drm_display_info
5677 * should use &drm_display_info.is_hdmi instead of calling this function.
5679 * Return: True if the monitor is HDMI, false if not or unknown.
5681 bool drm_detect_hdmi_monitor(const struct edid *edid)
5683 struct drm_edid drm_edid;
5685 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5687 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5689 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5691 struct drm_edid_iter edid_iter;
5692 const struct cea_db *db;
5693 struct cea_db_iter iter;
5695 bool has_audio = false;
5697 drm_edid_iter_begin(drm_edid, &edid_iter);
5698 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5699 if (edid_ext[0] == CEA_EXT) {
5700 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5705 drm_edid_iter_end(&edid_iter);
5708 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5712 cea_db_iter_edid_begin(drm_edid, &iter);
5713 cea_db_iter_for_each(db, &iter) {
5714 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5715 const u8 *data = cea_db_data(db);
5718 for (i = 0; i < cea_db_payload_len(db); i += 3)
5719 DRM_DEBUG_KMS("CEA audio format %d\n",
5720 (data[i] >> 3) & 0xf);
5725 cea_db_iter_end(&iter);
5732 * drm_detect_monitor_audio - check monitor audio capability
5733 * @edid: EDID block to scan
5735 * Monitor should have CEA extension block.
5736 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5737 * audio' only. If there is any audio extension block and supported
5738 * audio format, assume at least 'basic audio' support, even if 'basic
5739 * audio' is not defined in EDID.
5741 * Return: True if the monitor supports audio, false otherwise.
5743 bool drm_detect_monitor_audio(const struct edid *edid)
5745 struct drm_edid drm_edid;
5747 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5749 EXPORT_SYMBOL(drm_detect_monitor_audio);
5753 * drm_default_rgb_quant_range - default RGB quantization range
5754 * @mode: display mode
5756 * Determine the default RGB quantization range for the mode,
5757 * as specified in CEA-861.
5759 * Return: The default RGB quantization range for the mode
5761 enum hdmi_quantization_range
5762 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5764 /* All CEA modes other than VIC 1 use limited quantization range. */
5765 return drm_match_cea_mode(mode) > 1 ?
5766 HDMI_QUANTIZATION_RANGE_LIMITED :
5767 HDMI_QUANTIZATION_RANGE_FULL;
5769 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5771 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5773 struct drm_display_info *info = &connector->display_info;
5775 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5777 if (db[2] & EDID_CEA_VCDB_QS)
5778 info->rgb_quant_range_selectable = true;
5782 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5784 switch (max_frl_rate) {
5787 *max_rate_per_lane = 3;
5791 *max_rate_per_lane = 6;
5795 *max_rate_per_lane = 6;
5799 *max_rate_per_lane = 8;
5803 *max_rate_per_lane = 10;
5807 *max_rate_per_lane = 12;
5812 *max_rate_per_lane = 0;
5816 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5820 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5822 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5823 hdmi->y420_dc_modes = dc_mask;
5826 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
5829 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5831 if (!hdmi_dsc->v_1p2)
5834 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5835 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5837 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5838 hdmi_dsc->bpc_supported = 16;
5839 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5840 hdmi_dsc->bpc_supported = 12;
5841 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5842 hdmi_dsc->bpc_supported = 10;
5844 /* Supports min 8 BPC if DSC 1.2 is supported*/
5845 hdmi_dsc->bpc_supported = 8;
5847 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
5849 u8 dsc_max_frl_rate;
5851 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5852 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5853 &hdmi_dsc->max_frl_rate_per_lane);
5855 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5857 switch (dsc_max_slices) {
5859 hdmi_dsc->max_slices = 1;
5860 hdmi_dsc->clk_per_slice = 340;
5863 hdmi_dsc->max_slices = 2;
5864 hdmi_dsc->clk_per_slice = 340;
5867 hdmi_dsc->max_slices = 4;
5868 hdmi_dsc->clk_per_slice = 340;
5871 hdmi_dsc->max_slices = 8;
5872 hdmi_dsc->clk_per_slice = 340;
5875 hdmi_dsc->max_slices = 8;
5876 hdmi_dsc->clk_per_slice = 400;
5879 hdmi_dsc->max_slices = 12;
5880 hdmi_dsc->clk_per_slice = 400;
5883 hdmi_dsc->max_slices = 16;
5884 hdmi_dsc->clk_per_slice = 400;
5888 hdmi_dsc->max_slices = 0;
5889 hdmi_dsc->clk_per_slice = 0;
5893 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
5894 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5897 /* Sink Capability Data Structure */
5898 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5901 struct drm_display_info *display = &connector->display_info;
5902 struct drm_hdmi_info *hdmi = &display->hdmi;
5903 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5904 int max_tmds_clock = 0;
5905 u8 max_frl_rate = 0;
5906 bool dsc_support = false;
5908 display->has_hdmi_infoframe = true;
5910 if (hf_scds[6] & 0x80) {
5911 hdmi->scdc.supported = true;
5912 if (hf_scds[6] & 0x40)
5913 hdmi->scdc.read_request = true;
5917 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5918 * And as per the spec, three factors confirm this:
5919 * * Availability of a HF-VSDB block in EDID (check)
5920 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5921 * * SCDC support available (let's check)
5922 * Lets check it out.
5926 struct drm_scdc *scdc = &hdmi->scdc;
5928 /* max clock is 5000 KHz times block value */
5929 max_tmds_clock = hf_scds[5] * 5000;
5931 if (max_tmds_clock > 340000) {
5932 display->max_tmds_clock = max_tmds_clock;
5935 if (scdc->supported) {
5936 scdc->scrambling.supported = true;
5938 /* Few sinks support scrambling for clocks < 340M */
5939 if ((hf_scds[6] & 0x8))
5940 scdc->scrambling.low_rates = true;
5945 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5946 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5947 &hdmi->max_frl_rate_per_lane);
5950 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
5952 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
5953 drm_parse_dsc_info(hdmi_dsc, hf_scds);
5957 drm_dbg_kms(connector->dev,
5958 "HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
5959 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
5962 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5965 struct drm_display_info *info = &connector->display_info;
5966 unsigned int dc_bpc = 0;
5968 /* HDMI supports at least 8 bpc */
5971 if (cea_db_payload_len(hdmi) < 6)
5974 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5976 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
5977 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5981 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5983 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
5984 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5988 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5990 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
5991 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5996 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
6001 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
6002 connector->name, dc_bpc);
6005 /* YCRCB444 is optional according to spec. */
6006 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6007 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6008 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
6013 * Spec says that if any deep color mode is supported at all,
6014 * then deep color 36 bit must be supported.
6016 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6017 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
6023 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6025 struct drm_display_info *info = &connector->display_info;
6026 u8 len = cea_db_payload_len(db);
6028 info->is_hdmi = true;
6031 info->dvi_dual = db[6] & 1;
6033 info->max_tmds_clock = db[7] * 5000;
6035 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
6036 "max TMDS clock %d kHz\n",
6038 info->max_tmds_clock);
6040 drm_parse_hdmi_deep_color_info(connector, db);
6044 * See EDID extension for head-mounted and specialized monitors, specified at:
6045 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6047 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6050 struct drm_display_info *info = &connector->display_info;
6052 bool desktop_usage = db[5] & BIT(6);
6054 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6055 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6056 info->non_desktop = true;
6058 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
6062 static void drm_parse_cea_ext(struct drm_connector *connector,
6063 const struct drm_edid *drm_edid)
6065 struct drm_display_info *info = &connector->display_info;
6066 struct drm_edid_iter edid_iter;
6067 const struct cea_db *db;
6068 struct cea_db_iter iter;
6071 drm_edid_iter_begin(drm_edid, &edid_iter);
6072 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6073 if (edid_ext[0] != CEA_EXT)
6077 info->cea_rev = edid_ext[1];
6079 if (info->cea_rev != edid_ext[1])
6080 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",
6081 info->cea_rev, edid_ext[1]);
6083 /* The existence of a CTA extension should imply RGB support */
6084 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6085 if (edid_ext[3] & EDID_CEA_YCRCB444)
6086 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6087 if (edid_ext[3] & EDID_CEA_YCRCB422)
6088 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6090 drm_edid_iter_end(&edid_iter);
6092 cea_db_iter_edid_begin(drm_edid, &iter);
6093 cea_db_iter_for_each(db, &iter) {
6094 /* FIXME: convert parsers to use struct cea_db */
6095 const u8 *data = (const u8 *)db;
6097 if (cea_db_is_hdmi_vsdb(db))
6098 drm_parse_hdmi_vsdb_video(connector, data);
6099 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6100 cea_db_is_hdmi_forum_scdb(db))
6101 drm_parse_hdmi_forum_scds(connector, data);
6102 else if (cea_db_is_microsoft_vsdb(db))
6103 drm_parse_microsoft_vsdb(connector, data);
6104 else if (cea_db_is_y420cmdb(db))
6105 drm_parse_y420cmdb_bitmap(connector, data);
6106 else if (cea_db_is_vcdb(db))
6107 drm_parse_vcdb(connector, data);
6108 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6109 drm_parse_hdr_metadata_block(connector, data);
6111 cea_db_iter_end(&iter);
6115 void get_monitor_range(const struct detailed_timing *timing, void *c)
6117 struct detailed_mode_closure *closure = c;
6118 struct drm_display_info *info = &closure->connector->display_info;
6119 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6120 const struct detailed_non_pixel *data = &timing->data.other_data;
6121 const struct detailed_data_monitor_range *range = &data->data.range;
6122 const struct edid *edid = closure->drm_edid->edid;
6124 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6128 * These limits are used to determine the VRR refresh
6129 * rate range. Only the "range limits only" variant
6130 * of the range descriptor seems to guarantee that
6131 * any and all timings are accepted by the sink, as
6132 * opposed to just timings conforming to the indicated
6133 * formula (GTF/GTF2/CVT). Thus other variants of the
6134 * range descriptor are not accepted here.
6136 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6139 monitor_range->min_vfreq = range->min_vfreq;
6140 monitor_range->max_vfreq = range->max_vfreq;
6142 if (edid->revision >= 4) {
6143 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6144 monitor_range->min_vfreq += 255;
6145 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6146 monitor_range->max_vfreq += 255;
6150 static void drm_get_monitor_range(struct drm_connector *connector,
6151 const struct drm_edid *drm_edid)
6153 const struct drm_display_info *info = &connector->display_info;
6154 struct detailed_mode_closure closure = {
6155 .connector = connector,
6156 .drm_edid = drm_edid,
6159 if (drm_edid->edid->revision < 4)
6162 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6165 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6167 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6168 info->monitor_range.min_vfreq,
6169 info->monitor_range.max_vfreq);
6172 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6173 const struct displayid_block *block)
6175 struct displayid_vesa_vendor_specific_block *vesa =
6176 (struct displayid_vesa_vendor_specific_block *)block;
6177 struct drm_display_info *info = &connector->display_info;
6179 if (block->num_bytes < 3) {
6180 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
6185 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6188 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6189 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
6193 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6195 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
6198 info->mso_stream_count = 0;
6201 info->mso_stream_count = 2; /* 2 or 4 links */
6204 info->mso_stream_count = 4; /* 4 links */
6208 if (!info->mso_stream_count) {
6209 info->mso_pixel_overlap = 0;
6213 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6214 if (info->mso_pixel_overlap > 8) {
6215 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
6216 info->mso_pixel_overlap);
6217 info->mso_pixel_overlap = 8;
6220 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
6221 info->mso_stream_count, info->mso_pixel_overlap);
6224 static void drm_update_mso(struct drm_connector *connector,
6225 const struct drm_edid *drm_edid)
6227 const struct displayid_block *block;
6228 struct displayid_iter iter;
6230 displayid_iter_edid_begin(drm_edid, &iter);
6231 displayid_iter_for_each(block, &iter) {
6232 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6233 drm_parse_vesa_mso_data(connector, block);
6235 displayid_iter_end(&iter);
6238 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6239 * all of the values which would have been set from EDID
6241 static void drm_reset_display_info(struct drm_connector *connector)
6243 struct drm_display_info *info = &connector->display_info;
6246 info->height_mm = 0;
6249 info->color_formats = 0;
6251 info->max_tmds_clock = 0;
6252 info->dvi_dual = false;
6253 info->is_hdmi = false;
6254 info->has_hdmi_infoframe = false;
6255 info->rgb_quant_range_selectable = false;
6256 memset(&info->hdmi, 0, sizeof(info->hdmi));
6258 info->edid_hdmi_rgb444_dc_modes = 0;
6259 info->edid_hdmi_ycbcr444_dc_modes = 0;
6261 info->non_desktop = 0;
6262 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6263 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6265 info->mso_stream_count = 0;
6266 info->mso_pixel_overlap = 0;
6269 static u32 update_display_info(struct drm_connector *connector,
6270 const struct drm_edid *drm_edid)
6272 struct drm_display_info *info = &connector->display_info;
6273 const struct edid *edid = drm_edid->edid;
6275 u32 quirks = edid_get_quirks(drm_edid);
6277 drm_reset_display_info(connector);
6279 info->width_mm = edid->width_cm * 10;
6280 info->height_mm = edid->height_cm * 10;
6282 drm_get_monitor_range(connector, drm_edid);
6284 if (edid->revision < 3)
6287 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
6290 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6291 drm_parse_cea_ext(connector, drm_edid);
6294 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6296 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6297 * tells us to assume 8 bpc color depth if the EDID doesn't have
6298 * extensions which tell otherwise.
6300 if (info->bpc == 0 && edid->revision == 3 &&
6301 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6303 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
6304 connector->name, info->bpc);
6307 /* Only defined for 1.4 with digital displays */
6308 if (edid->revision < 4)
6311 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6312 case DRM_EDID_DIGITAL_DEPTH_6:
6315 case DRM_EDID_DIGITAL_DEPTH_8:
6318 case DRM_EDID_DIGITAL_DEPTH_10:
6321 case DRM_EDID_DIGITAL_DEPTH_12:
6324 case DRM_EDID_DIGITAL_DEPTH_14:
6327 case DRM_EDID_DIGITAL_DEPTH_16:
6330 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6336 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6337 connector->name, info->bpc);
6339 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6340 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6341 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6342 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6344 drm_update_mso(connector, drm_edid);
6347 if (quirks & EDID_QUIRK_NON_DESKTOP) {
6348 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
6349 info->non_desktop ? " (redundant quirk)" : "");
6350 info->non_desktop = true;
6356 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6357 struct displayid_detailed_timings_1 *timings,
6360 struct drm_display_mode *mode;
6361 unsigned pixel_clock = (timings->pixel_clock[0] |
6362 (timings->pixel_clock[1] << 8) |
6363 (timings->pixel_clock[2] << 16)) + 1;
6364 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6365 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6366 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6367 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6368 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6369 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6370 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6371 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6372 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6373 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6375 mode = drm_mode_create(dev);
6379 /* resolution is kHz for type VII, and 10 kHz for type I */
6380 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6381 mode->hdisplay = hactive;
6382 mode->hsync_start = mode->hdisplay + hsync;
6383 mode->hsync_end = mode->hsync_start + hsync_width;
6384 mode->htotal = mode->hdisplay + hblank;
6386 mode->vdisplay = vactive;
6387 mode->vsync_start = mode->vdisplay + vsync;
6388 mode->vsync_end = mode->vsync_start + vsync_width;
6389 mode->vtotal = mode->vdisplay + vblank;
6392 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6393 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6394 mode->type = DRM_MODE_TYPE_DRIVER;
6396 if (timings->flags & 0x80)
6397 mode->type |= DRM_MODE_TYPE_PREFERRED;
6398 drm_mode_set_name(mode);
6403 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6404 const struct displayid_block *block)
6406 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6409 struct drm_display_mode *newmode;
6411 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6412 /* blocks must be multiple of 20 bytes length */
6413 if (block->num_bytes % 20)
6416 num_timings = block->num_bytes / 20;
6417 for (i = 0; i < num_timings; i++) {
6418 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6420 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6424 drm_mode_probed_add(connector, newmode);
6430 static int add_displayid_detailed_modes(struct drm_connector *connector,
6431 const struct drm_edid *drm_edid)
6433 const struct displayid_block *block;
6434 struct displayid_iter iter;
6437 displayid_iter_edid_begin(drm_edid, &iter);
6438 displayid_iter_for_each(block, &iter) {
6439 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6440 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6441 num_modes += add_displayid_detailed_1_modes(connector, block);
6443 displayid_iter_end(&iter);
6448 static int _drm_edid_connector_update(struct drm_connector *connector,
6449 const struct drm_edid *drm_edid)
6455 drm_reset_display_info(connector);
6456 clear_eld(connector);
6461 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6462 * To avoid multiple parsing of same block, lets parse that map
6463 * from sink info, before parsing CEA modes.
6465 quirks = update_display_info(connector, drm_edid);
6467 /* Depends on info->cea_rev set by update_display_info() above */
6468 drm_edid_to_eld(connector, drm_edid);
6471 * EDID spec says modes should be preferred in this order:
6472 * - preferred detailed mode
6473 * - other detailed modes from base block
6474 * - detailed modes from extension blocks
6475 * - CVT 3-byte code modes
6476 * - standard timing codes
6477 * - established timing codes
6478 * - modes inferred from GTF or CVT range information
6480 * We get this pretty much right.
6482 * XXX order for additional mode types in extension blocks?
6484 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6485 num_modes += add_cvt_modes(connector, drm_edid);
6486 num_modes += add_standard_modes(connector, drm_edid);
6487 num_modes += add_established_modes(connector, drm_edid);
6488 num_modes += add_cea_modes(connector, drm_edid);
6489 num_modes += add_alternate_cea_modes(connector, drm_edid);
6490 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6491 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6492 num_modes += add_inferred_modes(connector, drm_edid);
6494 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6495 edid_fixup_preferred(connector, quirks);
6497 if (quirks & EDID_QUIRK_FORCE_6BPC)
6498 connector->display_info.bpc = 6;
6500 if (quirks & EDID_QUIRK_FORCE_8BPC)
6501 connector->display_info.bpc = 8;
6503 if (quirks & EDID_QUIRK_FORCE_10BPC)
6504 connector->display_info.bpc = 10;
6506 if (quirks & EDID_QUIRK_FORCE_12BPC)
6507 connector->display_info.bpc = 12;
6512 static void _drm_update_tile_info(struct drm_connector *connector,
6513 const struct drm_edid *drm_edid);
6515 static int _drm_edid_connector_property_update(struct drm_connector *connector,
6516 const struct drm_edid *drm_edid)
6518 struct drm_device *dev = connector->dev;
6521 if (connector->edid_blob_ptr) {
6522 const struct edid *old_edid = connector->edid_blob_ptr->data;
6525 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6526 connector->epoch_counter++;
6527 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6528 connector->base.id, connector->name,
6529 connector->epoch_counter);
6534 ret = drm_property_replace_global_blob(dev,
6535 &connector->edid_blob_ptr,
6536 drm_edid ? drm_edid->size : 0,
6537 drm_edid ? drm_edid->edid : NULL,
6539 dev->mode_config.edid_property);
6541 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6542 connector->base.id, connector->name, ret);
6546 ret = drm_object_property_set_value(&connector->base,
6547 dev->mode_config.non_desktop_property,
6548 connector->display_info.non_desktop);
6550 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6551 connector->base.id, connector->name, ret);
6555 ret = drm_connector_set_tile_property(connector);
6557 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6558 connector->base.id, connector->name, ret);
6567 * drm_edid_connector_update - Update connector information from EDID
6568 * @connector: Connector
6571 * Update the connector mode list, display info, ELD, HDR metadata, relevant
6572 * properties, etc. from the passed in EDID.
6574 * If EDID is NULL, reset the information.
6576 * Return: The number of modes added or 0 if we couldn't find any.
6578 int drm_edid_connector_update(struct drm_connector *connector,
6579 const struct drm_edid *drm_edid)
6584 * FIXME: Reconcile the differences in override_edid handling between
6585 * this and drm_connector_update_edid_property().
6587 * If override_edid is set, and the EDID passed in here originates from
6588 * drm_edid_read() and friends, it will be the override EDID, and there
6589 * are no issues. drm_connector_update_edid_property() ignoring requests
6590 * to set the EDID dates back to a time when override EDID was not
6591 * handled at the low level EDID read.
6593 * The only way the EDID passed in here can be different from the
6594 * override EDID is when a driver passes in an EDID that does *not*
6595 * originate from drm_edid_read() and friends, or passes in a stale
6596 * cached version. This, in turn, is a question of when an override EDID
6597 * set via debugfs should take effect.
6600 count = _drm_edid_connector_update(connector, drm_edid);
6602 _drm_update_tile_info(connector, drm_edid);
6604 /* Note: Ignore errors for now. */
6605 _drm_edid_connector_property_update(connector, drm_edid);
6609 EXPORT_SYMBOL(drm_edid_connector_update);
6611 static int _drm_connector_update_edid_property(struct drm_connector *connector,
6612 const struct drm_edid *drm_edid)
6614 /* ignore requests to set edid when overridden */
6615 if (connector->override_edid)
6619 * Set the display info, using edid if available, otherwise resetting
6620 * the values to defaults. This duplicates the work done in
6621 * drm_add_edid_modes, but that function is not consistently called
6622 * before this one in all drivers and the computation is cheap enough
6623 * that it seems better to duplicate it rather than attempt to ensure
6624 * some arbitrary ordering of calls.
6627 update_display_info(connector, drm_edid);
6629 drm_reset_display_info(connector);
6631 _drm_update_tile_info(connector, drm_edid);
6633 return _drm_edid_connector_property_update(connector, drm_edid);
6637 * drm_connector_update_edid_property - update the edid property of a connector
6638 * @connector: drm connector
6639 * @edid: new value of the edid property
6641 * This function creates a new blob modeset object and assigns its id to the
6642 * connector's edid property.
6643 * Since we also parse tile information from EDID's displayID block, we also
6644 * set the connector's tile property here. See drm_connector_set_tile_property()
6647 * This function is deprecated. Use drm_edid_connector_update() instead.
6650 * Zero on success, negative errno on failure.
6652 int drm_connector_update_edid_property(struct drm_connector *connector,
6653 const struct edid *edid)
6655 struct drm_edid drm_edid;
6657 return _drm_connector_update_edid_property(connector,
6658 drm_edid_legacy_init(&drm_edid, edid));
6660 EXPORT_SYMBOL(drm_connector_update_edid_property);
6663 * drm_add_edid_modes - add modes from EDID data, if available
6664 * @connector: connector we're probing
6667 * Add the specified modes to the connector's mode list. Also fills out the
6668 * &drm_display_info structure and ELD in @connector with any information which
6669 * can be derived from the edid.
6671 * This function is deprecated. Use drm_edid_connector_update() instead.
6673 * Return: The number of modes added or 0 if we couldn't find any.
6675 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6677 struct drm_edid drm_edid;
6679 if (edid && !drm_edid_is_valid(edid)) {
6680 drm_warn(connector->dev, "%s: EDID invalid.\n",
6685 return _drm_edid_connector_update(connector,
6686 drm_edid_legacy_init(&drm_edid, edid));
6688 EXPORT_SYMBOL(drm_add_edid_modes);
6691 * drm_add_modes_noedid - add modes for the connectors without EDID
6692 * @connector: connector we're probing
6693 * @hdisplay: the horizontal display limit
6694 * @vdisplay: the vertical display limit
6696 * Add the specified modes to the connector's mode list. Only when the
6697 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6699 * Return: The number of modes added or 0 if we couldn't find any.
6701 int drm_add_modes_noedid(struct drm_connector *connector,
6702 int hdisplay, int vdisplay)
6704 int i, count, num_modes = 0;
6705 struct drm_display_mode *mode;
6706 struct drm_device *dev = connector->dev;
6708 count = ARRAY_SIZE(drm_dmt_modes);
6714 for (i = 0; i < count; i++) {
6715 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6717 if (hdisplay && vdisplay) {
6719 * Only when two are valid, they will be used to check
6720 * whether the mode should be added to the mode list of
6723 if (ptr->hdisplay > hdisplay ||
6724 ptr->vdisplay > vdisplay)
6727 if (drm_mode_vrefresh(ptr) > 61)
6729 mode = drm_mode_duplicate(dev, ptr);
6731 drm_mode_probed_add(connector, mode);
6737 EXPORT_SYMBOL(drm_add_modes_noedid);
6740 * drm_set_preferred_mode - Sets the preferred mode of a connector
6741 * @connector: connector whose mode list should be processed
6742 * @hpref: horizontal resolution of preferred mode
6743 * @vpref: vertical resolution of preferred mode
6745 * Marks a mode as preferred if it matches the resolution specified by @hpref
6748 void drm_set_preferred_mode(struct drm_connector *connector,
6749 int hpref, int vpref)
6751 struct drm_display_mode *mode;
6753 list_for_each_entry(mode, &connector->probed_modes, head) {
6754 if (mode->hdisplay == hpref &&
6755 mode->vdisplay == vpref)
6756 mode->type |= DRM_MODE_TYPE_PREFERRED;
6759 EXPORT_SYMBOL(drm_set_preferred_mode);
6761 static bool is_hdmi2_sink(const struct drm_connector *connector)
6764 * FIXME: sil-sii8620 doesn't have a connector around when
6765 * we need one, so we have to be prepared for a NULL connector.
6770 return connector->display_info.hdmi.scdc.supported ||
6771 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6774 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6775 const struct drm_display_mode *mode)
6777 bool has_hdmi_infoframe = connector ?
6778 connector->display_info.has_hdmi_infoframe : false;
6780 if (!has_hdmi_infoframe)
6783 /* No HDMI VIC when signalling 3D video format */
6784 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6787 return drm_match_hdmi_mode(mode);
6790 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
6791 const struct drm_display_mode *mode)
6796 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6797 * we should send its VIC in vendor infoframes, else send the
6798 * VIC in AVI infoframes. Lets check if this mode is present in
6799 * HDMI 1.4b 4K modes
6801 if (drm_mode_hdmi_vic(connector, mode))
6804 vic = drm_match_cea_mode(mode);
6807 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6808 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6809 * have to make sure we dont break HDMI 1.4 sinks.
6811 if (!is_hdmi2_sink(connector) && vic > 64)
6818 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6819 * data from a DRM display mode
6820 * @frame: HDMI AVI infoframe
6821 * @connector: the connector
6822 * @mode: DRM display mode
6824 * Return: 0 on success or a negative error code on failure.
6827 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
6828 const struct drm_connector *connector,
6829 const struct drm_display_mode *mode)
6831 enum hdmi_picture_aspect picture_aspect;
6834 if (!frame || !mode)
6837 hdmi_avi_infoframe_init(frame);
6839 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6840 frame->pixel_repeat = 1;
6842 vic = drm_mode_cea_vic(connector, mode);
6843 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
6845 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6848 * As some drivers don't support atomic, we can't use connector state.
6849 * So just initialize the frame with default values, just the same way
6850 * as it's done with other properties here.
6852 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6856 * Populate picture aspect ratio from either
6857 * user input (if specified) or from the CEA/HDMI mode lists.
6859 picture_aspect = mode->picture_aspect_ratio;
6860 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6862 picture_aspect = drm_get_cea_aspect_ratio(vic);
6864 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6868 * The infoframe can't convey anything but none, 4:3
6869 * and 16:9, so if the user has asked for anything else
6870 * we can only satisfy it by specifying the right VIC.
6872 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
6874 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6876 } else if (hdmi_vic) {
6877 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6883 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6886 frame->video_code = vic;
6887 frame->picture_aspect = picture_aspect;
6888 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
6889 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
6893 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
6896 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6897 * quantization range information
6898 * @frame: HDMI AVI infoframe
6899 * @connector: the connector
6900 * @mode: DRM display mode
6901 * @rgb_quant_range: RGB quantization range (Q)
6904 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6905 const struct drm_connector *connector,
6906 const struct drm_display_mode *mode,
6907 enum hdmi_quantization_range rgb_quant_range)
6909 const struct drm_display_info *info = &connector->display_info;
6913 * "A Source shall not send a non-zero Q value that does not correspond
6914 * to the default RGB Quantization Range for the transmitted Picture
6915 * unless the Sink indicates support for the Q bit in a Video
6916 * Capabilities Data Block."
6918 * HDMI 2.0 recommends sending non-zero Q when it does match the
6919 * default RGB quantization range for the mode, even when QS=0.
6921 if (info->rgb_quant_range_selectable ||
6922 rgb_quant_range == drm_default_rgb_quant_range(mode))
6923 frame->quantization_range = rgb_quant_range;
6925 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
6929 * "When transmitting any RGB colorimetry, the Source should set the
6930 * YQ-field to match the RGB Quantization Range being transmitted
6931 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6932 * set YQ=1) and the Sink shall ignore the YQ-field."
6934 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6935 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6936 * good way to tell which version of CEA-861 the sink supports, so
6937 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6940 if (!is_hdmi2_sink(connector) ||
6941 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
6942 frame->ycc_quantization_range =
6943 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6945 frame->ycc_quantization_range =
6946 HDMI_YCC_QUANTIZATION_RANGE_FULL;
6948 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6950 static enum hdmi_3d_structure
6951 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6953 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6956 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6957 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6958 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6959 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6960 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6961 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6962 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6963 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6964 case DRM_MODE_FLAG_3D_L_DEPTH:
6965 return HDMI_3D_STRUCTURE_L_DEPTH;
6966 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6967 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6968 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6969 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6970 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6971 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6973 return HDMI_3D_STRUCTURE_INVALID;
6978 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6979 * data from a DRM display mode
6980 * @frame: HDMI vendor infoframe
6981 * @connector: the connector
6982 * @mode: DRM display mode
6984 * Note that there's is a need to send HDMI vendor infoframes only when using a
6985 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6986 * function will return -EINVAL, error that can be safely ignored.
6988 * Return: 0 on success or a negative error code on failure.
6991 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6992 const struct drm_connector *connector,
6993 const struct drm_display_mode *mode)
6996 * FIXME: sil-sii8620 doesn't have a connector around when
6997 * we need one, so we have to be prepared for a NULL connector.
6999 bool has_hdmi_infoframe = connector ?
7000 connector->display_info.has_hdmi_infoframe : false;
7003 if (!frame || !mode)
7006 if (!has_hdmi_infoframe)
7009 err = hdmi_vendor_infoframe_init(frame);
7014 * Even if it's not absolutely necessary to send the infoframe
7015 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7016 * know that the sink can handle it. This is based on a
7017 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7018 * have trouble realizing that they should switch from 3D to 2D
7019 * mode if the source simply stops sending the infoframe when
7020 * it wants to switch from 3D to 2D.
7022 frame->vic = drm_mode_hdmi_vic(connector, mode);
7023 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7027 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7029 static void drm_parse_tiled_block(struct drm_connector *connector,
7030 const struct displayid_block *block)
7032 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7034 u8 tile_v_loc, tile_h_loc;
7035 u8 num_v_tile, num_h_tile;
7036 struct drm_tile_group *tg;
7038 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7039 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7041 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7042 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7043 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7044 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7046 connector->has_tile = true;
7047 if (tile->tile_cap & 0x80)
7048 connector->tile_is_single_monitor = true;
7050 connector->num_h_tile = num_h_tile + 1;
7051 connector->num_v_tile = num_v_tile + 1;
7052 connector->tile_h_loc = tile_h_loc;
7053 connector->tile_v_loc = tile_v_loc;
7054 connector->tile_h_size = w + 1;
7055 connector->tile_v_size = h + 1;
7057 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
7058 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
7059 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
7060 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
7061 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7063 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7065 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7069 if (connector->tile_group != tg) {
7070 /* if we haven't got a pointer,
7071 take the reference, drop ref to old tile group */
7072 if (connector->tile_group)
7073 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7074 connector->tile_group = tg;
7076 /* if same tile group, then release the ref we just took. */
7077 drm_mode_put_tile_group(connector->dev, tg);
7081 static void _drm_update_tile_info(struct drm_connector *connector,
7082 const struct drm_edid *drm_edid)
7084 const struct displayid_block *block;
7085 struct displayid_iter iter;
7087 connector->has_tile = false;
7089 displayid_iter_edid_begin(drm_edid, &iter);
7090 displayid_iter_for_each(block, &iter) {
7091 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
7092 drm_parse_tiled_block(connector, block);
7094 displayid_iter_end(&iter);
7096 if (!connector->has_tile && connector->tile_group) {
7097 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7098 connector->tile_group = NULL;
projects / platform / kernel / linux-rpi.git / blob