2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
46 #include "drm_crtc_internal.h"
48 static int oui(u8 first, u8 second, u8 third)
50 return (first << 16) | (second << 8) | third;
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* use +hsync +vsync for detailed mode */
77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
78 /* Force reduced-blanking timings for detailed modes */
79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
81 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
83 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
85 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
87 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
88 /* Non desktop display (i.e. HMD) */
89 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
91 #define MICROSOFT_IEEE_OUI 0xca125c
93 struct detailed_mode_closure {
94 struct drm_connector *connector;
95 const struct drm_edid *drm_edid;
106 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
108 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
113 static const struct edid_quirk {
116 } edid_quirk_list[] = {
118 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
120 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
122 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
123 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
125 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
126 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
128 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
129 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
131 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
132 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
134 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
135 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
137 /* Belinea 10 15 55 */
138 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
139 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
141 /* Envision Peripherals, Inc. EN-7100e */
142 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
143 /* Envision EN2028 */
144 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
146 /* Funai Electronics PM36B */
147 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
148 EDID_QUIRK_DETAILED_IN_CM),
150 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
151 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
153 /* LG Philips LCD LP154W01-A5 */
154 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
155 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
157 /* Samsung SyncMaster 205BW. Note: irony */
158 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
159 /* Samsung SyncMaster 22[5-6]BW */
160 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
161 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
163 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
164 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
166 /* ViewSonic VA2026w */
167 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
169 /* Medion MD 30217 PG */
170 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
173 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
175 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
176 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
178 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
179 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
181 /* Valve Index Headset */
182 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
183 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
184 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
185 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
186 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
187 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
200 /* HTC Vive and Vive Pro VR Headsets */
201 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
204 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
205 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
210 /* Windows Mixed Reality Headsets */
211 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
213 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
214 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
218 /* Sony PlayStation VR Headset */
219 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
221 /* Sensics VR Headsets */
222 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
224 /* OSVR HDK and HDK2 VR Headsets */
225 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
229 * Autogenerated from the DMT spec.
230 * This table is copied from xfree86/modes/xf86EdidModes.c.
232 static const struct drm_display_mode drm_dmt_modes[] = {
233 /* 0x01 - 640x350@85Hz */
234 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
235 736, 832, 0, 350, 382, 385, 445, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x02 - 640x400@85Hz */
238 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
239 736, 832, 0, 400, 401, 404, 445, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x03 - 720x400@85Hz */
242 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
243 828, 936, 0, 400, 401, 404, 446, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x04 - 640x480@60Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
247 752, 800, 0, 480, 490, 492, 525, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x05 - 640x480@72Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
251 704, 832, 0, 480, 489, 492, 520, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x06 - 640x480@75Hz */
254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
255 720, 840, 0, 480, 481, 484, 500, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
257 /* 0x07 - 640x480@85Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
259 752, 832, 0, 480, 481, 484, 509, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x08 - 800x600@56Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
263 896, 1024, 0, 600, 601, 603, 625, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x09 - 800x600@60Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
267 968, 1056, 0, 600, 601, 605, 628, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0a - 800x600@72Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
271 976, 1040, 0, 600, 637, 643, 666, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0b - 800x600@75Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
275 896, 1056, 0, 600, 601, 604, 625, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0c - 800x600@85Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
279 896, 1048, 0, 600, 601, 604, 631, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0d - 800x600@120Hz RB */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
283 880, 960, 0, 600, 603, 607, 636, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
285 /* 0x0e - 848x480@60Hz */
286 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
287 976, 1088, 0, 480, 486, 494, 517, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x0f - 1024x768@43Hz, interlace */
290 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
291 1208, 1264, 0, 768, 768, 776, 817, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
293 DRM_MODE_FLAG_INTERLACE) },
294 /* 0x10 - 1024x768@60Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
296 1184, 1344, 0, 768, 771, 777, 806, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
298 /* 0x11 - 1024x768@70Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
300 1184, 1328, 0, 768, 771, 777, 806, 0,
301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x12 - 1024x768@75Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
304 1136, 1312, 0, 768, 769, 772, 800, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x13 - 1024x768@85Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
308 1168, 1376, 0, 768, 769, 772, 808, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x14 - 1024x768@120Hz RB */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
312 1104, 1184, 0, 768, 771, 775, 813, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 0x15 - 1152x864@75Hz */
315 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
316 1344, 1600, 0, 864, 865, 868, 900, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x55 - 1280x720@60Hz */
319 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
320 1430, 1650, 0, 720, 725, 730, 750, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x16 - 1280x768@60Hz RB */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
324 1360, 1440, 0, 768, 771, 778, 790, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x17 - 1280x768@60Hz */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
328 1472, 1664, 0, 768, 771, 778, 798, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x18 - 1280x768@75Hz */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
332 1488, 1696, 0, 768, 771, 778, 805, 0,
333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x19 - 1280x768@85Hz */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
336 1496, 1712, 0, 768, 771, 778, 809, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x1a - 1280x768@120Hz RB */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
340 1360, 1440, 0, 768, 771, 778, 813, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
342 /* 0x1b - 1280x800@60Hz RB */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
344 1360, 1440, 0, 800, 803, 809, 823, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
346 /* 0x1c - 1280x800@60Hz */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
348 1480, 1680, 0, 800, 803, 809, 831, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1d - 1280x800@75Hz */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
352 1488, 1696, 0, 800, 803, 809, 838, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x1e - 1280x800@85Hz */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
356 1496, 1712, 0, 800, 803, 809, 843, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x1f - 1280x800@120Hz RB */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
360 1360, 1440, 0, 800, 803, 809, 847, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362 /* 0x20 - 1280x960@60Hz */
363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
364 1488, 1800, 0, 960, 961, 964, 1000, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x21 - 1280x960@85Hz */
367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
368 1504, 1728, 0, 960, 961, 964, 1011, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x22 - 1280x960@120Hz RB */
371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
372 1360, 1440, 0, 960, 963, 967, 1017, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x23 - 1280x1024@60Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
376 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x24 - 1280x1024@75Hz */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x25 - 1280x1024@85Hz */
383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
384 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x26 - 1280x1024@120Hz RB */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
388 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x27 - 1360x768@60Hz */
391 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
392 1536, 1792, 0, 768, 771, 777, 795, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x28 - 1360x768@120Hz RB */
395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
396 1440, 1520, 0, 768, 771, 776, 813, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
398 /* 0x51 - 1366x768@60Hz */
399 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
400 1579, 1792, 0, 768, 771, 774, 798, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x56 - 1366x768@60Hz */
403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
404 1436, 1500, 0, 768, 769, 772, 800, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x29 - 1400x1050@60Hz RB */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
408 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
410 /* 0x2a - 1400x1050@60Hz */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
412 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x2b - 1400x1050@75Hz */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
416 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x2c - 1400x1050@85Hz */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
420 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x2d - 1400x1050@120Hz RB */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
424 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
426 /* 0x2e - 1440x900@60Hz RB */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
428 1520, 1600, 0, 900, 903, 909, 926, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
430 /* 0x2f - 1440x900@60Hz */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
432 1672, 1904, 0, 900, 903, 909, 934, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x30 - 1440x900@75Hz */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
436 1688, 1936, 0, 900, 903, 909, 942, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x31 - 1440x900@85Hz */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
440 1696, 1952, 0, 900, 903, 909, 948, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x32 - 1440x900@120Hz RB */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
444 1520, 1600, 0, 900, 903, 909, 953, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
446 /* 0x53 - 1600x900@60Hz */
447 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
448 1704, 1800, 0, 900, 901, 904, 1000, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x33 - 1600x1200@60Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x34 - 1600x1200@65Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x35 - 1600x1200@70Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x36 - 1600x1200@75Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x37 - 1600x1200@85Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x38 - 1600x1200@120Hz RB */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
472 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
474 /* 0x39 - 1680x1050@60Hz RB */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
476 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
478 /* 0x3a - 1680x1050@60Hz */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
480 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x3b - 1680x1050@75Hz */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
484 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x3c - 1680x1050@85Hz */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
488 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3d - 1680x1050@120Hz RB */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
492 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
494 /* 0x3e - 1792x1344@60Hz */
495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
496 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x3f - 1792x1344@75Hz */
499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
500 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x40 - 1792x1344@120Hz RB */
503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
504 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x41 - 1856x1392@60Hz */
507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
508 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x42 - 1856x1392@75Hz */
511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
512 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x43 - 1856x1392@120Hz RB */
515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
516 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x52 - 1920x1080@60Hz */
519 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
520 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
522 /* 0x44 - 1920x1200@60Hz RB */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
524 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
526 /* 0x45 - 1920x1200@60Hz */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
528 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x46 - 1920x1200@75Hz */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
532 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x47 - 1920x1200@85Hz */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
536 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x48 - 1920x1200@120Hz RB */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
540 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x49 - 1920x1440@60Hz */
543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
544 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 0x4a - 1920x1440@75Hz */
547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
548 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4b - 1920x1440@120Hz RB */
551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
552 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x54 - 2048x1152@60Hz */
555 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
556 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4c - 2560x1600@60Hz RB */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
560 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
562 /* 0x4d - 2560x1600@60Hz */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
564 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x4e - 2560x1600@75Hz */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
568 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
570 /* 0x4f - 2560x1600@85Hz */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
572 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
574 /* 0x50 - 2560x1600@120Hz RB */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
576 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
578 /* 0x57 - 4096x2160@60Hz RB */
579 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
580 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
582 /* 0x58 - 4096x2160@59.94Hz RB */
583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
589 * These more or less come from the DMT spec. The 720x400 modes are
590 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
591 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
592 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
595 * The DMT modes have been fact-checked; the rest are mild guesses.
597 static const struct drm_display_mode edid_est_modes[] = {
598 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
599 968, 1056, 0, 600, 601, 605, 628, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
601 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
602 896, 1024, 0, 600, 601, 603, 625, 0,
603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
605 720, 840, 0, 480, 481, 484, 500, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
607 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
608 704, 832, 0, 480, 489, 492, 520, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
611 768, 864, 0, 480, 483, 486, 525, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
613 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
614 752, 800, 0, 480, 490, 492, 525, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
616 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
617 846, 900, 0, 400, 421, 423, 449, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
619 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
620 846, 900, 0, 400, 412, 414, 449, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
622 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
623 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
625 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
626 1136, 1312, 0, 768, 769, 772, 800, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
629 1184, 1328, 0, 768, 771, 777, 806, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
631 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
632 1184, 1344, 0, 768, 771, 777, 806, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
634 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
635 1208, 1264, 0, 768, 768, 776, 817, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
637 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
638 928, 1152, 0, 624, 625, 628, 667, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
640 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
641 896, 1056, 0, 600, 601, 604, 625, 0,
642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
643 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
644 976, 1040, 0, 600, 637, 643, 666, 0,
645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
646 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
647 1344, 1600, 0, 864, 865, 868, 900, 0,
648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
658 static const struct minimode est3_modes[] = {
666 { 1024, 768, 85, 0 },
667 { 1152, 864, 75, 0 },
669 { 1280, 768, 60, 1 },
670 { 1280, 768, 60, 0 },
671 { 1280, 768, 75, 0 },
672 { 1280, 768, 85, 0 },
673 { 1280, 960, 60, 0 },
674 { 1280, 960, 85, 0 },
675 { 1280, 1024, 60, 0 },
676 { 1280, 1024, 85, 0 },
678 { 1360, 768, 60, 0 },
679 { 1440, 900, 60, 1 },
680 { 1440, 900, 60, 0 },
681 { 1440, 900, 75, 0 },
682 { 1440, 900, 85, 0 },
683 { 1400, 1050, 60, 1 },
684 { 1400, 1050, 60, 0 },
685 { 1400, 1050, 75, 0 },
687 { 1400, 1050, 85, 0 },
688 { 1680, 1050, 60, 1 },
689 { 1680, 1050, 60, 0 },
690 { 1680, 1050, 75, 0 },
691 { 1680, 1050, 85, 0 },
692 { 1600, 1200, 60, 0 },
693 { 1600, 1200, 65, 0 },
694 { 1600, 1200, 70, 0 },
696 { 1600, 1200, 75, 0 },
697 { 1600, 1200, 85, 0 },
698 { 1792, 1344, 60, 0 },
699 { 1792, 1344, 75, 0 },
700 { 1856, 1392, 60, 0 },
701 { 1856, 1392, 75, 0 },
702 { 1920, 1200, 60, 1 },
703 { 1920, 1200, 60, 0 },
705 { 1920, 1200, 75, 0 },
706 { 1920, 1200, 85, 0 },
707 { 1920, 1440, 60, 0 },
708 { 1920, 1440, 75, 0 },
711 static const struct minimode extra_modes[] = {
712 { 1024, 576, 60, 0 },
713 { 1366, 768, 60, 0 },
714 { 1600, 900, 60, 0 },
715 { 1680, 945, 60, 0 },
716 { 1920, 1080, 60, 0 },
717 { 2048, 1152, 60, 0 },
718 { 2048, 1536, 60, 0 },
722 * From CEA/CTA-861 spec.
724 * Do not access directly, instead always use cea_mode_for_vic().
726 static const struct drm_display_mode edid_cea_modes_1[] = {
727 /* 1 - 640x480@60Hz 4:3 */
728 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
729 752, 800, 0, 480, 490, 492, 525, 0,
730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
731 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
732 /* 2 - 720x480@60Hz 4:3 */
733 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
734 798, 858, 0, 480, 489, 495, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
736 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
737 /* 3 - 720x480@60Hz 16:9 */
738 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
739 798, 858, 0, 480, 489, 495, 525, 0,
740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
741 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
742 /* 4 - 1280x720@60Hz 16:9 */
743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
744 1430, 1650, 0, 720, 725, 730, 750, 0,
745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
746 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 5 - 1920x1080i@60Hz 16:9 */
748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
749 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
751 DRM_MODE_FLAG_INTERLACE),
752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 6 - 720(1440)x480i@60Hz 4:3 */
754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 480, 488, 494, 525, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
758 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
759 /* 7 - 720(1440)x480i@60Hz 16:9 */
760 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 480, 488, 494, 525, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
765 /* 8 - 720(1440)x240@60Hz 4:3 */
766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 240, 244, 247, 262, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_DBLCLK),
770 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 9 - 720(1440)x240@60Hz 16:9 */
772 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
773 801, 858, 0, 240, 244, 247, 262, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_DBLCLK),
776 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 10 - 2880x480i@60Hz 4:3 */
778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 480, 488, 494, 525, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_INTERLACE),
782 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
783 /* 11 - 2880x480i@60Hz 16:9 */
784 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
785 3204, 3432, 0, 480, 488, 494, 525, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
787 DRM_MODE_FLAG_INTERLACE),
788 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
789 /* 12 - 2880x240@60Hz 4:3 */
790 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
791 3204, 3432, 0, 240, 244, 247, 262, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
794 /* 13 - 2880x240@60Hz 16:9 */
795 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
796 3204, 3432, 0, 240, 244, 247, 262, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
798 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799 /* 14 - 1440x480@60Hz 4:3 */
800 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
801 1596, 1716, 0, 480, 489, 495, 525, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
803 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
804 /* 15 - 1440x480@60Hz 16:9 */
805 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
806 1596, 1716, 0, 480, 489, 495, 525, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
809 /* 16 - 1920x1080@60Hz 16:9 */
810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
811 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 17 - 720x576@50Hz 4:3 */
815 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
816 796, 864, 0, 576, 581, 586, 625, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
818 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
819 /* 18 - 720x576@50Hz 16:9 */
820 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
821 796, 864, 0, 576, 581, 586, 625, 0,
822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
823 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
824 /* 19 - 1280x720@50Hz 16:9 */
825 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
826 1760, 1980, 0, 720, 725, 730, 750, 0,
827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 20 - 1920x1080i@50Hz 16:9 */
830 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
831 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
833 DRM_MODE_FLAG_INTERLACE),
834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 21 - 720(1440)x576i@50Hz 4:3 */
836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
841 /* 22 - 720(1440)x576i@50Hz 16:9 */
842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 576, 580, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
847 /* 23 - 720(1440)x288@50Hz 4:3 */
848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 288, 290, 293, 312, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_DBLCLK),
852 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 24 - 720(1440)x288@50Hz 16:9 */
854 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
855 795, 864, 0, 288, 290, 293, 312, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_DBLCLK),
858 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 25 - 2880x576i@50Hz 4:3 */
860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 576, 580, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
863 DRM_MODE_FLAG_INTERLACE),
864 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
865 /* 26 - 2880x576i@50Hz 16:9 */
866 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
867 3180, 3456, 0, 576, 580, 586, 625, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
869 DRM_MODE_FLAG_INTERLACE),
870 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 27 - 2880x288@50Hz 4:3 */
872 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
873 3180, 3456, 0, 288, 290, 293, 312, 0,
874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 28 - 2880x288@50Hz 16:9 */
877 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
878 3180, 3456, 0, 288, 290, 293, 312, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
880 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
881 /* 29 - 1440x576@50Hz 4:3 */
882 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
883 1592, 1728, 0, 576, 581, 586, 625, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
886 /* 30 - 1440x576@50Hz 16:9 */
887 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
888 1592, 1728, 0, 576, 581, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
891 /* 31 - 1920x1080@50Hz 16:9 */
892 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
893 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 32 - 1920x1080@24Hz 16:9 */
897 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
898 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
900 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 33 - 1920x1080@25Hz 16:9 */
902 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
903 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
905 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
906 /* 34 - 1920x1080@30Hz 16:9 */
907 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
908 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
910 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
911 /* 35 - 2880x480@60Hz 4:3 */
912 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
913 3192, 3432, 0, 480, 489, 495, 525, 0,
914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
915 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
916 /* 36 - 2880x480@60Hz 16:9 */
917 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
918 3192, 3432, 0, 480, 489, 495, 525, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
920 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
921 /* 37 - 2880x576@50Hz 4:3 */
922 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
923 3184, 3456, 0, 576, 581, 586, 625, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
925 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
926 /* 38 - 2880x576@50Hz 16:9 */
927 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
928 3184, 3456, 0, 576, 581, 586, 625, 0,
929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
930 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 39 - 1920x1080i@50Hz 16:9 */
932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
933 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
935 DRM_MODE_FLAG_INTERLACE),
936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
937 /* 40 - 1920x1080i@100Hz 16:9 */
938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
939 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
941 DRM_MODE_FLAG_INTERLACE),
942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 41 - 1280x720@100Hz 16:9 */
944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
945 1760, 1980, 0, 720, 725, 730, 750, 0,
946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 42 - 720x576@100Hz 4:3 */
949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
950 796, 864, 0, 576, 581, 586, 625, 0,
951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
953 /* 43 - 720x576@100Hz 16:9 */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 44 - 720(1440)x576i@100Hz 4:3 */
959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
964 /* 45 - 720(1440)x576i@100Hz 16:9 */
965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
966 795, 864, 0, 576, 580, 586, 625, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
969 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 46 - 1920x1080i@120Hz 16:9 */
971 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
972 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
974 DRM_MODE_FLAG_INTERLACE),
975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
976 /* 47 - 1280x720@120Hz 16:9 */
977 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
978 1430, 1650, 0, 720, 725, 730, 750, 0,
979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
981 /* 48 - 720x480@120Hz 4:3 */
982 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
983 798, 858, 0, 480, 489, 495, 525, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
986 /* 49 - 720x480@120Hz 16:9 */
987 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
988 798, 858, 0, 480, 489, 495, 525, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
990 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
991 /* 50 - 720(1440)x480i@120Hz 4:3 */
992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
993 801, 858, 0, 480, 488, 494, 525, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
997 /* 51 - 720(1440)x480i@120Hz 16:9 */
998 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
999 801, 858, 0, 480, 488, 494, 525, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1001 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1002 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 /* 52 - 720x576@200Hz 4:3 */
1004 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1005 796, 864, 0, 576, 581, 586, 625, 0,
1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1008 /* 53 - 720x576@200Hz 16:9 */
1009 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1010 796, 864, 0, 576, 581, 586, 625, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1013 /* 54 - 720(1440)x576i@200Hz 4:3 */
1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1015 795, 864, 0, 576, 580, 586, 625, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1019 /* 55 - 720(1440)x576i@200Hz 16:9 */
1020 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1021 795, 864, 0, 576, 580, 586, 625, 0,
1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1023 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1024 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025 /* 56 - 720x480@240Hz 4:3 */
1026 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1027 798, 858, 0, 480, 489, 495, 525, 0,
1028 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1030 /* 57 - 720x480@240Hz 16:9 */
1031 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1032 798, 858, 0, 480, 489, 495, 525, 0,
1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1034 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035 /* 58 - 720(1440)x480i@240Hz 4:3 */
1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1037 801, 858, 0, 480, 488, 494, 525, 0,
1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1041 /* 59 - 720(1440)x480i@240Hz 16:9 */
1042 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1043 801, 858, 0, 480, 488, 494, 525, 0,
1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1045 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1046 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1047 /* 60 - 1280x720@24Hz 16:9 */
1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1049 3080, 3300, 0, 720, 725, 730, 750, 0,
1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1052 /* 61 - 1280x720@25Hz 16:9 */
1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1054 3740, 3960, 0, 720, 725, 730, 750, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1057 /* 62 - 1280x720@30Hz 16:9 */
1058 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1059 3080, 3300, 0, 720, 725, 730, 750, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1062 /* 63 - 1920x1080@120Hz 16:9 */
1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1067 /* 64 - 1920x1080@100Hz 16:9 */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1072 /* 65 - 1280x720@24Hz 64:27 */
1073 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1074 3080, 3300, 0, 720, 725, 730, 750, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077 /* 66 - 1280x720@25Hz 64:27 */
1078 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1079 3740, 3960, 0, 720, 725, 730, 750, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 67 - 1280x720@30Hz 64:27 */
1083 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1084 3080, 3300, 0, 720, 725, 730, 750, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 68 - 1280x720@50Hz 64:27 */
1088 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1089 1760, 1980, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 69 - 1280x720@60Hz 64:27 */
1093 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1094 1430, 1650, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 70 - 1280x720@100Hz 64:27 */
1098 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1099 1760, 1980, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 71 - 1280x720@120Hz 64:27 */
1103 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1104 1430, 1650, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 72 - 1920x1080@24Hz 64:27 */
1108 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1109 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 73 - 1920x1080@25Hz 64:27 */
1113 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1114 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 74 - 1920x1080@30Hz 64:27 */
1118 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1119 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 75 - 1920x1080@50Hz 64:27 */
1123 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1124 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 76 - 1920x1080@60Hz 64:27 */
1128 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1129 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 77 - 1920x1080@100Hz 64:27 */
1133 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1134 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 78 - 1920x1080@120Hz 64:27 */
1138 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1139 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 79 - 1680x720@24Hz 64:27 */
1143 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1144 3080, 3300, 0, 720, 725, 730, 750, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 80 - 1680x720@25Hz 64:27 */
1148 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1149 2948, 3168, 0, 720, 725, 730, 750, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 81 - 1680x720@30Hz 64:27 */
1153 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1154 2420, 2640, 0, 720, 725, 730, 750, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 82 - 1680x720@50Hz 64:27 */
1158 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1159 1980, 2200, 0, 720, 725, 730, 750, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162 /* 83 - 1680x720@60Hz 64:27 */
1163 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1164 1980, 2200, 0, 720, 725, 730, 750, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1167 /* 84 - 1680x720@100Hz 64:27 */
1168 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1169 1780, 2000, 0, 720, 725, 730, 825, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1172 /* 85 - 1680x720@120Hz 64:27 */
1173 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1174 1780, 2000, 0, 720, 725, 730, 825, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1177 /* 86 - 2560x1080@24Hz 64:27 */
1178 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1179 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1182 /* 87 - 2560x1080@25Hz 64:27 */
1183 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1184 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1187 /* 88 - 2560x1080@30Hz 64:27 */
1188 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1189 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1192 /* 89 - 2560x1080@50Hz 64:27 */
1193 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1194 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1197 /* 90 - 2560x1080@60Hz 64:27 */
1198 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1199 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1202 /* 91 - 2560x1080@100Hz 64:27 */
1203 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1204 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1207 /* 92 - 2560x1080@120Hz 64:27 */
1208 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1209 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1212 /* 93 - 3840x2160@24Hz 16:9 */
1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1217 /* 94 - 3840x2160@25Hz 16:9 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1222 /* 95 - 3840x2160@30Hz 16:9 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1227 /* 96 - 3840x2160@50Hz 16:9 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1232 /* 97 - 3840x2160@60Hz 16:9 */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1237 /* 98 - 4096x2160@24Hz 256:135 */
1238 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1239 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1241 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1242 /* 99 - 4096x2160@25Hz 256:135 */
1243 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1244 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1247 /* 100 - 4096x2160@30Hz 256:135 */
1248 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1249 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1252 /* 101 - 4096x2160@50Hz 256:135 */
1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1254 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1257 /* 102 - 4096x2160@60Hz 256:135 */
1258 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1259 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1261 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1262 /* 103 - 3840x2160@24Hz 64:27 */
1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1264 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1266 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1267 /* 104 - 3840x2160@25Hz 64:27 */
1268 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1269 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1271 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1272 /* 105 - 3840x2160@30Hz 64:27 */
1273 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1274 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1276 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1277 /* 106 - 3840x2160@50Hz 64:27 */
1278 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1279 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1282 /* 107 - 3840x2160@60Hz 64:27 */
1283 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1284 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1286 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1287 /* 108 - 1280x720@48Hz 16:9 */
1288 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1289 2280, 2500, 0, 720, 725, 730, 750, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1291 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1292 /* 109 - 1280x720@48Hz 64:27 */
1293 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1294 2280, 2500, 0, 720, 725, 730, 750, 0,
1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1296 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1297 /* 110 - 1680x720@48Hz 64:27 */
1298 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1299 2530, 2750, 0, 720, 725, 730, 750, 0,
1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1301 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1302 /* 111 - 1920x1080@48Hz 16:9 */
1303 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1304 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1306 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1307 /* 112 - 1920x1080@48Hz 64:27 */
1308 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1309 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1311 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1312 /* 113 - 2560x1080@48Hz 64:27 */
1313 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1314 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1316 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1317 /* 114 - 3840x2160@48Hz 16:9 */
1318 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1319 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1321 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1322 /* 115 - 4096x2160@48Hz 256:135 */
1323 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1324 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1326 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1327 /* 116 - 3840x2160@48Hz 64:27 */
1328 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1329 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1331 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1332 /* 117 - 3840x2160@100Hz 16:9 */
1333 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1334 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1336 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1337 /* 118 - 3840x2160@120Hz 16:9 */
1338 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1339 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1341 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1342 /* 119 - 3840x2160@100Hz 64:27 */
1343 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1344 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1346 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1347 /* 120 - 3840x2160@120Hz 64:27 */
1348 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1349 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1351 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1352 /* 121 - 5120x2160@24Hz 64:27 */
1353 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1354 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1356 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1357 /* 122 - 5120x2160@25Hz 64:27 */
1358 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1359 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1361 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1362 /* 123 - 5120x2160@30Hz 64:27 */
1363 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1364 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1366 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1367 /* 124 - 5120x2160@48Hz 64:27 */
1368 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1369 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1371 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1372 /* 125 - 5120x2160@50Hz 64:27 */
1373 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1374 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1376 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1377 /* 126 - 5120x2160@60Hz 64:27 */
1378 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1379 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1381 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1382 /* 127 - 5120x2160@100Hz 64:27 */
1383 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1384 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1386 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1390 * From CEA/CTA-861 spec.
1392 * Do not access directly, instead always use cea_mode_for_vic().
1394 static const struct drm_display_mode edid_cea_modes_193[] = {
1395 /* 193 - 5120x2160@120Hz 64:27 */
1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1397 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1400 /* 194 - 7680x4320@24Hz 16:9 */
1401 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1402 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1405 /* 195 - 7680x4320@25Hz 16:9 */
1406 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1407 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1410 /* 196 - 7680x4320@30Hz 16:9 */
1411 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1412 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1414 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1415 /* 197 - 7680x4320@48Hz 16:9 */
1416 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1417 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1419 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1420 /* 198 - 7680x4320@50Hz 16:9 */
1421 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1422 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1424 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1425 /* 199 - 7680x4320@60Hz 16:9 */
1426 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1427 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1429 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1430 /* 200 - 7680x4320@100Hz 16:9 */
1431 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1432 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1434 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1435 /* 201 - 7680x4320@120Hz 16:9 */
1436 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1437 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1439 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1440 /* 202 - 7680x4320@24Hz 64:27 */
1441 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1442 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1444 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1445 /* 203 - 7680x4320@25Hz 64:27 */
1446 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1447 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1449 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1450 /* 204 - 7680x4320@30Hz 64:27 */
1451 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1452 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1454 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1455 /* 205 - 7680x4320@48Hz 64:27 */
1456 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1457 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1459 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1460 /* 206 - 7680x4320@50Hz 64:27 */
1461 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1462 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1464 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1465 /* 207 - 7680x4320@60Hz 64:27 */
1466 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1467 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1469 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1470 /* 208 - 7680x4320@100Hz 64:27 */
1471 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1472 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1474 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1475 /* 209 - 7680x4320@120Hz 64:27 */
1476 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1477 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1479 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1480 /* 210 - 10240x4320@24Hz 64:27 */
1481 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1482 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1484 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1485 /* 211 - 10240x4320@25Hz 64:27 */
1486 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1487 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1489 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1490 /* 212 - 10240x4320@30Hz 64:27 */
1491 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1492 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1494 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1495 /* 213 - 10240x4320@48Hz 64:27 */
1496 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1497 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1499 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1500 /* 214 - 10240x4320@50Hz 64:27 */
1501 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1502 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1504 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1505 /* 215 - 10240x4320@60Hz 64:27 */
1506 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1507 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1509 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1510 /* 216 - 10240x4320@100Hz 64:27 */
1511 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1512 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1514 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1515 /* 217 - 10240x4320@120Hz 64:27 */
1516 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1517 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1519 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1520 /* 218 - 4096x2160@100Hz 256:135 */
1521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1522 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1524 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1525 /* 219 - 4096x2160@120Hz 256:135 */
1526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1527 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1529 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1533 * HDMI 1.4 4k modes. Index using the VIC.
1535 static const struct drm_display_mode edid_4k_modes[] = {
1536 /* 0 - dummy, VICs start at 1 */
1538 /* 1 - 3840x2160@30Hz */
1539 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1540 3840, 4016, 4104, 4400, 0,
1541 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1544 /* 2 - 3840x2160@25Hz */
1545 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1546 3840, 4896, 4984, 5280, 0,
1547 2160, 2168, 2178, 2250, 0,
1548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1549 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1550 /* 3 - 3840x2160@24Hz */
1551 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1552 3840, 5116, 5204, 5500, 0,
1553 2160, 2168, 2178, 2250, 0,
1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1555 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1556 /* 4 - 4096x2160@24Hz (SMPTE) */
1557 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1558 4096, 5116, 5204, 5500, 0,
1559 2160, 2168, 2178, 2250, 0,
1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1564 /*** DDC fetch and block validation ***/
1567 * The opaque EDID type, internal to drm_edid.c.
1570 /* Size allocated for edid */
1572 const struct edid *edid;
1575 static bool version_greater(const struct drm_edid *drm_edid,
1576 u8 version, u8 revision)
1578 const struct edid *edid = drm_edid->edid;
1580 return edid->version > version ||
1581 (edid->version == version && edid->revision > revision);
1584 static int edid_extension_block_count(const struct edid *edid)
1586 return edid->extensions;
1589 static int edid_block_count(const struct edid *edid)
1591 return edid_extension_block_count(edid) + 1;
1594 static int edid_size_by_blocks(int num_blocks)
1596 return num_blocks * EDID_LENGTH;
1599 static int edid_size(const struct edid *edid)
1601 return edid_size_by_blocks(edid_block_count(edid));
1604 static const void *edid_block_data(const struct edid *edid, int index)
1606 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1608 return edid + index;
1611 static const void *edid_extension_block_data(const struct edid *edid, int index)
1613 return edid_block_data(edid, index + 1);
1616 static int drm_edid_block_count(const struct drm_edid *drm_edid)
1620 /* Starting point */
1621 num_blocks = edid_block_count(drm_edid->edid);
1623 /* Limit by allocated size */
1624 num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH);
1629 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1631 return drm_edid_block_count(drm_edid) - 1;
1634 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1636 return edid_block_data(drm_edid->edid, index);
1639 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1642 return edid_extension_block_data(drm_edid->edid, index);
1646 * Initializer helper for legacy interfaces, where we have no choice but to
1647 * trust edid size. Not for general purpose use.
1649 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1650 const struct edid *edid)
1655 memset(drm_edid, 0, sizeof(*drm_edid));
1657 drm_edid->edid = edid;
1658 drm_edid->size = edid_size(edid);
1664 * EDID base and extension block iterator.
1666 * struct drm_edid_iter iter;
1669 * drm_edid_iter_begin(drm_edid, &iter);
1670 * drm_edid_iter_for_each(block, &iter) {
1671 * // do stuff with block
1673 * drm_edid_iter_end(&iter);
1675 struct drm_edid_iter {
1676 const struct drm_edid *drm_edid;
1678 /* Current block index. */
1682 static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1683 struct drm_edid_iter *iter)
1685 memset(iter, 0, sizeof(*iter));
1687 iter->drm_edid = drm_edid;
1690 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1692 const void *block = NULL;
1694 if (!iter->drm_edid)
1697 if (iter->index < drm_edid_block_count(iter->drm_edid))
1698 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1703 #define drm_edid_iter_for_each(__block, __iter) \
1704 while (((__block) = __drm_edid_iter_next(__iter)))
1706 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1708 memset(iter, 0, sizeof(*iter));
1711 static const u8 edid_header[] = {
1712 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1715 static void edid_header_fix(void *edid)
1717 memcpy(edid, edid_header, sizeof(edid_header));
1721 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1722 * @_edid: pointer to raw base EDID block
1724 * Sanity check the header of the base EDID block.
1726 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1728 int drm_edid_header_is_valid(const void *_edid)
1730 const struct edid *edid = _edid;
1733 for (i = 0; i < sizeof(edid_header); i++) {
1734 if (edid->header[i] == edid_header[i])
1740 EXPORT_SYMBOL(drm_edid_header_is_valid);
1742 static int edid_fixup __read_mostly = 6;
1743 module_param_named(edid_fixup, edid_fixup, int, 0400);
1744 MODULE_PARM_DESC(edid_fixup,
1745 "Minimum number of valid EDID header bytes (0-8, default 6)");
1747 static int edid_block_compute_checksum(const void *_block)
1749 const u8 *block = _block;
1751 u8 csum = 0, crc = 0;
1753 for (i = 0; i < EDID_LENGTH - 1; i++)
1761 static int edid_block_get_checksum(const void *_block)
1763 const struct edid *block = _block;
1765 return block->checksum;
1768 static int edid_block_tag(const void *_block)
1770 const u8 *block = _block;
1775 static bool edid_block_is_zero(const void *edid)
1777 return !memchr_inv(edid, 0, EDID_LENGTH);
1781 * drm_edid_are_equal - compare two edid blobs.
1782 * @edid1: pointer to first blob
1783 * @edid2: pointer to second blob
1784 * This helper can be used during probing to determine if
1787 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1789 int edid1_len, edid2_len;
1790 bool edid1_present = edid1 != NULL;
1791 bool edid2_present = edid2 != NULL;
1793 if (edid1_present != edid2_present)
1797 edid1_len = edid_size(edid1);
1798 edid2_len = edid_size(edid2);
1800 if (edid1_len != edid2_len)
1803 if (memcmp(edid1, edid2, edid1_len))
1809 EXPORT_SYMBOL(drm_edid_are_equal);
1811 enum edid_block_status {
1813 EDID_BLOCK_READ_FAIL,
1816 EDID_BLOCK_HEADER_CORRUPT,
1817 EDID_BLOCK_HEADER_REPAIR,
1818 EDID_BLOCK_HEADER_FIXED,
1819 EDID_BLOCK_CHECKSUM,
1823 static enum edid_block_status edid_block_check(const void *_block,
1826 const struct edid *block = _block;
1829 return EDID_BLOCK_NULL;
1831 if (is_base_block) {
1832 int score = drm_edid_header_is_valid(block);
1834 if (score < clamp(edid_fixup, 0, 8)) {
1835 if (edid_block_is_zero(block))
1836 return EDID_BLOCK_ZERO;
1838 return EDID_BLOCK_HEADER_CORRUPT;
1842 return EDID_BLOCK_HEADER_REPAIR;
1845 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1846 if (edid_block_is_zero(block))
1847 return EDID_BLOCK_ZERO;
1849 return EDID_BLOCK_CHECKSUM;
1852 if (is_base_block) {
1853 if (block->version != 1)
1854 return EDID_BLOCK_VERSION;
1857 return EDID_BLOCK_OK;
1860 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1862 return status == EDID_BLOCK_OK ||
1863 status == EDID_BLOCK_HEADER_FIXED ||
1864 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1867 static bool edid_block_valid(const void *block, bool base)
1869 return edid_block_status_valid(edid_block_check(block, base),
1870 edid_block_tag(block));
1873 static void edid_block_status_print(enum edid_block_status status,
1874 const struct edid *block,
1880 case EDID_BLOCK_READ_FAIL:
1881 pr_debug("EDID block %d read failed\n", block_num);
1883 case EDID_BLOCK_NULL:
1884 pr_debug("EDID block %d pointer is NULL\n", block_num);
1886 case EDID_BLOCK_ZERO:
1887 pr_notice("EDID block %d is all zeroes\n", block_num);
1889 case EDID_BLOCK_HEADER_CORRUPT:
1890 pr_notice("EDID has corrupt header\n");
1892 case EDID_BLOCK_HEADER_REPAIR:
1893 pr_debug("EDID corrupt header needs repair\n");
1895 case EDID_BLOCK_HEADER_FIXED:
1896 pr_debug("EDID corrupt header fixed\n");
1898 case EDID_BLOCK_CHECKSUM:
1899 if (edid_block_status_valid(status, edid_block_tag(block))) {
1900 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1901 block_num, edid_block_tag(block),
1902 edid_block_compute_checksum(block));
1904 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1905 block_num, edid_block_tag(block),
1906 edid_block_compute_checksum(block));
1909 case EDID_BLOCK_VERSION:
1910 pr_notice("EDID has major version %d, instead of 1\n",
1914 WARN(1, "EDID block %d unknown edid block status code %d\n",
1920 static void edid_block_dump(const char *level, const void *block, int block_num)
1922 enum edid_block_status status;
1925 status = edid_block_check(block, block_num == 0);
1926 if (status == EDID_BLOCK_ZERO)
1927 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1928 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1929 sprintf(prefix, "\t[%02x] BAD ", block_num);
1931 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1933 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1934 block, EDID_LENGTH, false);
1938 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1939 * @_block: pointer to raw EDID block
1940 * @block_num: type of block to validate (0 for base, extension otherwise)
1941 * @print_bad_edid: if true, dump bad EDID blocks to the console
1942 * @edid_corrupt: if true, the header or checksum is invalid
1944 * Validate a base or extension EDID block and optionally dump bad blocks to
1947 * Return: True if the block is valid, false otherwise.
1949 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1952 struct edid *block = (struct edid *)_block;
1953 enum edid_block_status status;
1954 bool is_base_block = block_num == 0;
1957 if (WARN_ON(!block))
1960 status = edid_block_check(block, is_base_block);
1961 if (status == EDID_BLOCK_HEADER_REPAIR) {
1962 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1963 edid_header_fix(block);
1965 /* Retry with fixed header, update status if that worked. */
1966 status = edid_block_check(block, is_base_block);
1967 if (status == EDID_BLOCK_OK)
1968 status = EDID_BLOCK_HEADER_FIXED;
1973 * Unknown major version isn't corrupt but we can't use it. Only
1974 * the base block can reset edid_corrupt to false.
1976 if (is_base_block &&
1977 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1978 *edid_corrupt = false;
1979 else if (status != EDID_BLOCK_OK)
1980 *edid_corrupt = true;
1983 edid_block_status_print(status, block, block_num);
1985 /* Determine whether we can use this block with this status. */
1986 valid = edid_block_status_valid(status, edid_block_tag(block));
1988 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
1989 pr_notice("Raw EDID:\n");
1990 edid_block_dump(KERN_NOTICE, block, block_num);
1995 EXPORT_SYMBOL(drm_edid_block_valid);
1998 * drm_edid_is_valid - sanity check EDID data
2001 * Sanity-check an entire EDID record (including extensions)
2003 * Return: True if the EDID data is valid, false otherwise.
2005 bool drm_edid_is_valid(struct edid *edid)
2012 for (i = 0; i < edid_block_count(edid); i++) {
2013 void *block = (void *)edid_block_data(edid, i);
2015 if (!drm_edid_block_valid(block, i, true, NULL))
2021 EXPORT_SYMBOL(drm_edid_is_valid);
2023 static struct edid *edid_filter_invalid_blocks(const struct edid *edid,
2027 struct edid *new, *dest_block;
2028 int valid_extensions = edid->extensions - invalid_blocks;
2031 *alloc_size = edid_size_by_blocks(valid_extensions + 1);
2033 new = kmalloc(*alloc_size, GFP_KERNEL);
2038 for (i = 0; i < edid_block_count(edid); i++) {
2039 const void *block = edid_block_data(edid, i);
2041 if (edid_block_valid(block, i == 0))
2042 memcpy(dest_block++, block, EDID_LENGTH);
2045 new->extensions = valid_extensions;
2046 new->checksum = edid_block_compute_checksum(new);
2054 #define DDC_SEGMENT_ADDR 0x30
2056 * drm_do_probe_ddc_edid() - get EDID information via I2C
2057 * @data: I2C device adapter
2058 * @buf: EDID data buffer to be filled
2059 * @block: 128 byte EDID block to start fetching from
2060 * @len: EDID data buffer length to fetch
2062 * Try to fetch EDID information by calling I2C driver functions.
2064 * Return: 0 on success or -1 on failure.
2067 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2069 struct i2c_adapter *adapter = data;
2070 unsigned char start = block * EDID_LENGTH;
2071 unsigned char segment = block >> 1;
2072 unsigned char xfers = segment ? 3 : 2;
2073 int ret, retries = 5;
2076 * The core I2C driver will automatically retry the transfer if the
2077 * adapter reports EAGAIN. However, we find that bit-banging transfers
2078 * are susceptible to errors under a heavily loaded machine and
2079 * generate spurious NAKs and timeouts. Retrying the transfer
2080 * of the individual block a few times seems to overcome this.
2083 struct i2c_msg msgs[] = {
2085 .addr = DDC_SEGMENT_ADDR,
2103 * Avoid sending the segment addr to not upset non-compliant
2106 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2108 if (ret == -ENXIO) {
2109 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2113 } while (ret != xfers && --retries);
2115 return ret == xfers ? 0 : -1;
2118 static void connector_bad_edid(struct drm_connector *connector,
2119 const struct edid *edid, int num_blocks)
2125 * 0x7e in the EDID is the number of extension blocks. The EDID
2126 * is 1 (base block) + num_ext_blocks big. That means we can think
2127 * of 0x7e in the EDID of the _index_ of the last block in the
2128 * combined chunk of memory.
2130 last_block = edid->extensions;
2132 /* Calculate real checksum for the last edid extension block data */
2133 if (last_block < num_blocks)
2134 connector->real_edid_checksum =
2135 edid_block_compute_checksum(edid + last_block);
2137 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2140 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
2141 for (i = 0; i < num_blocks; i++)
2142 edid_block_dump(KERN_DEBUG, edid + i, i);
2145 /* Get override or firmware EDID */
2146 static struct edid *drm_get_override_edid(struct drm_connector *connector,
2149 struct edid *override = NULL;
2151 if (connector->override_edid)
2152 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
2155 override = drm_load_edid_firmware(connector);
2157 /* FIXME: Get alloc size from deeper down the stack */
2158 if (!IS_ERR_OR_NULL(override) && alloc_size)
2159 *alloc_size = edid_size(override);
2161 return IS_ERR(override) ? NULL : override;
2165 * drm_add_override_edid_modes - add modes from override/firmware EDID
2166 * @connector: connector we're probing
2168 * Add modes from the override/firmware EDID, if available. Only to be used from
2169 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2170 * failed during drm_get_edid() and caused the override/firmware EDID to be
2173 * Return: The number of modes added or 0 if we couldn't find any.
2175 int drm_add_override_edid_modes(struct drm_connector *connector)
2177 struct edid *override;
2180 override = drm_get_override_edid(connector, NULL);
2182 drm_connector_update_edid_property(connector, override);
2183 num_modes = drm_add_edid_modes(connector, override);
2186 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2187 connector->base.id, connector->name, num_modes);
2192 EXPORT_SYMBOL(drm_add_override_edid_modes);
2194 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2196 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2197 read_block_fn read_block,
2200 enum edid_block_status status;
2201 bool is_base_block = block_num == 0;
2204 for (try = 0; try < 4; try++) {
2205 if (read_block(context, block, block_num, EDID_LENGTH))
2206 return EDID_BLOCK_READ_FAIL;
2208 status = edid_block_check(block, is_base_block);
2209 if (status == EDID_BLOCK_HEADER_REPAIR) {
2210 edid_header_fix(block);
2212 /* Retry with fixed header, update status if that worked. */
2213 status = edid_block_check(block, is_base_block);
2214 if (status == EDID_BLOCK_OK)
2215 status = EDID_BLOCK_HEADER_FIXED;
2218 if (edid_block_status_valid(status, edid_block_tag(block)))
2221 /* Fail early for unrepairable base block all zeros. */
2222 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2229 static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2230 read_block_fn read_block, void *context,
2233 enum edid_block_status status;
2234 int i, invalid_blocks = 0;
2235 struct edid *edid, *new;
2236 size_t alloc_size = EDID_LENGTH;
2238 edid = drm_get_override_edid(connector, &alloc_size);
2242 edid = kmalloc(alloc_size, GFP_KERNEL);
2246 status = edid_block_read(edid, 0, read_block, context);
2248 edid_block_status_print(status, edid, 0);
2250 if (status == EDID_BLOCK_READ_FAIL)
2253 /* FIXME: Clarify what a corrupt EDID actually means. */
2254 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2255 connector->edid_corrupt = false;
2257 connector->edid_corrupt = true;
2259 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2260 if (status == EDID_BLOCK_ZERO)
2261 connector->null_edid_counter++;
2263 connector_bad_edid(connector, edid, 1);
2267 if (!edid_extension_block_count(edid))
2270 alloc_size = edid_size(edid);
2271 new = krealloc(edid, alloc_size, GFP_KERNEL);
2276 for (i = 1; i < edid_block_count(edid); i++) {
2277 void *block = (void *)edid_block_data(edid, i);
2279 status = edid_block_read(block, i, read_block, context);
2281 edid_block_status_print(status, block, i);
2283 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2284 if (status == EDID_BLOCK_READ_FAIL)
2290 if (invalid_blocks) {
2291 connector_bad_edid(connector, edid, edid_block_count(edid));
2293 edid = edid_filter_invalid_blocks(edid, invalid_blocks,
2309 * drm_do_get_edid - get EDID data using a custom EDID block read function
2310 * @connector: connector we're probing
2311 * @read_block: EDID block read function
2312 * @context: private data passed to the block read function
2314 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2315 * exposes a different interface to read EDID blocks this function can be used
2316 * to get EDID data using a custom block read function.
2318 * As in the general case the DDC bus is accessible by the kernel at the I2C
2319 * level, drivers must make all reasonable efforts to expose it as an I2C
2320 * adapter and use drm_get_edid() instead of abusing this function.
2322 * The EDID may be overridden using debugfs override_edid or firmware EDID
2323 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2324 * order. Having either of them bypasses actual EDID reads.
2326 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2328 struct edid *drm_do_get_edid(struct drm_connector *connector,
2329 read_block_fn read_block,
2332 return _drm_do_get_edid(connector, read_block, context, NULL);
2334 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2336 /* Allocate struct drm_edid container *without* duplicating the edid data */
2337 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2339 struct drm_edid *drm_edid;
2341 if (!edid || !size || size < EDID_LENGTH)
2344 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2346 drm_edid->edid = edid;
2347 drm_edid->size = size;
2354 * drm_edid_alloc - Allocate a new drm_edid container
2355 * @edid: Pointer to raw EDID data
2356 * @size: Size of memory allocated for EDID
2358 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2359 * the actual size that has been allocated for the data. There is no validation
2360 * of the raw EDID data against the size, but at least the EDID base block must
2361 * fit in the buffer.
2363 * The returned pointer must be freed using drm_edid_free().
2365 * Return: drm_edid container, or NULL on errors
2367 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2369 const struct drm_edid *drm_edid;
2371 if (!edid || !size || size < EDID_LENGTH)
2374 edid = kmemdup(edid, size, GFP_KERNEL);
2378 drm_edid = _drm_edid_alloc(edid, size);
2384 EXPORT_SYMBOL(drm_edid_alloc);
2387 * drm_edid_dup - Duplicate a drm_edid container
2388 * @drm_edid: EDID to duplicate
2390 * The returned pointer must be freed using drm_edid_free().
2392 * Returns: drm_edid container copy, or NULL on errors
2394 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2399 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2401 EXPORT_SYMBOL(drm_edid_dup);
2404 * drm_edid_free - Free the drm_edid container
2405 * @drm_edid: EDID to free
2407 void drm_edid_free(const struct drm_edid *drm_edid)
2412 kfree(drm_edid->edid);
2415 EXPORT_SYMBOL(drm_edid_free);
2418 * drm_probe_ddc() - probe DDC presence
2419 * @adapter: I2C adapter to probe
2421 * Return: True on success, false on failure.
2424 drm_probe_ddc(struct i2c_adapter *adapter)
2428 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2430 EXPORT_SYMBOL(drm_probe_ddc);
2433 * drm_get_edid - get EDID data, if available
2434 * @connector: connector we're probing
2435 * @adapter: I2C adapter to use for DDC
2437 * Poke the given I2C channel to grab EDID data if possible. If found,
2438 * attach it to the connector.
2440 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2442 struct edid *drm_get_edid(struct drm_connector *connector,
2443 struct i2c_adapter *adapter)
2447 if (connector->force == DRM_FORCE_OFF)
2450 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2453 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2454 drm_connector_update_edid_property(connector, edid);
2457 EXPORT_SYMBOL(drm_get_edid);
2460 * drm_edid_read_custom - Read EDID data using given EDID block read function
2461 * @connector: Connector to use
2462 * @read_block: EDID block read function
2463 * @context: Private data passed to the block read function
2465 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2466 * exposes a different interface to read EDID blocks this function can be used
2467 * to get EDID data using a custom block read function.
2469 * As in the general case the DDC bus is accessible by the kernel at the I2C
2470 * level, drivers must make all reasonable efforts to expose it as an I2C
2471 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2474 * The EDID may be overridden using debugfs override_edid or firmware EDID
2475 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2476 * order. Having either of them bypasses actual EDID reads.
2478 * The returned pointer must be freed using drm_edid_free().
2480 * Return: Pointer to EDID, or NULL if probe/read failed.
2482 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2483 read_block_fn read_block,
2486 const struct drm_edid *drm_edid;
2490 edid = _drm_do_get_edid(connector, read_block, context, &size);
2494 /* Sanity check for now */
2495 drm_WARN_ON(connector->dev, !size);
2497 drm_edid = _drm_edid_alloc(edid, size);
2503 EXPORT_SYMBOL(drm_edid_read_custom);
2506 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2507 * @connector: Connector to use
2508 * @adapter: I2C adapter to use for DDC
2510 * Read EDID using the given I2C adapter.
2512 * The EDID may be overridden using debugfs override_edid or firmware EDID
2513 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2514 * order. Having either of them bypasses actual EDID reads.
2516 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2517 * using drm_edid_read() instead of this function.
2519 * The returned pointer must be freed using drm_edid_free().
2521 * Return: Pointer to EDID, or NULL if probe/read failed.
2523 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2524 struct i2c_adapter *adapter)
2526 const struct drm_edid *drm_edid;
2528 if (connector->force == DRM_FORCE_OFF)
2531 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2534 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2536 /* Note: Do *not* call connector updates here. */
2540 EXPORT_SYMBOL(drm_edid_read_ddc);
2543 * drm_edid_read - Read EDID data using connector's I2C adapter
2544 * @connector: Connector to use
2546 * Read EDID using the connector's I2C adapter.
2548 * The EDID may be overridden using debugfs override_edid or firmware EDID
2549 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2550 * order. Having either of them bypasses actual EDID reads.
2552 * The returned pointer must be freed using drm_edid_free().
2554 * Return: Pointer to EDID, or NULL if probe/read failed.
2556 const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2558 if (drm_WARN_ON(connector->dev, !connector->ddc))
2561 return drm_edid_read_ddc(connector, connector->ddc);
2563 EXPORT_SYMBOL(drm_edid_read);
2565 static u32 edid_extract_panel_id(const struct edid *edid)
2568 * We represent the ID as a 32-bit number so it can easily be compared
2571 * NOTE that we deal with endianness differently for the top half
2572 * of this ID than for the bottom half. The bottom half (the product
2573 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2574 * that's how everyone seems to interpret it. The top half (the mfg_id)
2575 * gets stored as big endian because that makes
2576 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2577 * to write (it's easier to extract the ASCII). It doesn't really
2578 * matter, though, as long as the number here is unique.
2580 return (u32)edid->mfg_id[0] << 24 |
2581 (u32)edid->mfg_id[1] << 16 |
2582 (u32)EDID_PRODUCT_ID(edid);
2586 * drm_edid_get_panel_id - Get a panel's ID through DDC
2587 * @adapter: I2C adapter to use for DDC
2589 * This function reads the first block of the EDID of a panel and (assuming
2590 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2591 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2592 * supposed to be different for each different modem of panel.
2594 * This function is intended to be used during early probing on devices where
2595 * more than one panel might be present. Because of its intended use it must
2596 * assume that the EDID of the panel is correct, at least as far as the ID
2597 * is concerned (in other words, we don't process any overrides here).
2599 * NOTE: it's expected that this function and drm_do_get_edid() will both
2600 * be read the EDID, but there is no caching between them. Since we're only
2601 * reading the first block, hopefully this extra overhead won't be too big.
2603 * Return: A 32-bit ID that should be different for each make/model of panel.
2604 * See the functions drm_edid_encode_panel_id() and
2605 * drm_edid_decode_panel_id() for some details on the structure of this
2609 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2611 enum edid_block_status status;
2616 * There are no manufacturer IDs of 0, so if there is a problem reading
2617 * the EDID then we'll just return 0.
2620 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2624 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2626 edid_block_status_print(status, base_block, 0);
2628 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2629 panel_id = edid_extract_panel_id(base_block);
2635 EXPORT_SYMBOL(drm_edid_get_panel_id);
2638 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2639 * @connector: connector we're probing
2640 * @adapter: I2C adapter to use for DDC
2642 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2643 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2644 * switch DDC to the GPU which is retrieving EDID.
2646 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2648 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2649 struct i2c_adapter *adapter)
2651 struct drm_device *dev = connector->dev;
2652 struct pci_dev *pdev = to_pci_dev(dev->dev);
2655 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2658 vga_switcheroo_lock_ddc(pdev);
2659 edid = drm_get_edid(connector, adapter);
2660 vga_switcheroo_unlock_ddc(pdev);
2664 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2667 * drm_edid_duplicate - duplicate an EDID and the extensions
2668 * @edid: EDID to duplicate
2670 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2672 struct edid *drm_edid_duplicate(const struct edid *edid)
2674 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2676 EXPORT_SYMBOL(drm_edid_duplicate);
2678 /*** EDID parsing ***/
2681 * edid_get_quirks - return quirk flags for a given EDID
2682 * @drm_edid: EDID to process
2684 * This tells subsequent routines what fixes they need to apply.
2686 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2688 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2689 const struct edid_quirk *quirk;
2692 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2693 quirk = &edid_quirk_list[i];
2694 if (quirk->panel_id == panel_id)
2695 return quirk->quirks;
2701 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2702 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2705 * Walk the mode list for connector, clearing the preferred status on existing
2706 * modes and setting it anew for the right mode ala quirks.
2708 static void edid_fixup_preferred(struct drm_connector *connector,
2711 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2712 int target_refresh = 0;
2713 int cur_vrefresh, preferred_vrefresh;
2715 if (list_empty(&connector->probed_modes))
2718 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2719 target_refresh = 60;
2720 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2721 target_refresh = 75;
2723 preferred_mode = list_first_entry(&connector->probed_modes,
2724 struct drm_display_mode, head);
2726 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2727 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2729 if (cur_mode == preferred_mode)
2732 /* Largest mode is preferred */
2733 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2734 preferred_mode = cur_mode;
2736 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2737 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2738 /* At a given size, try to get closest to target refresh */
2739 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2740 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2741 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2742 preferred_mode = cur_mode;
2746 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2750 mode_is_rb(const struct drm_display_mode *mode)
2752 return (mode->htotal - mode->hdisplay == 160) &&
2753 (mode->hsync_end - mode->hdisplay == 80) &&
2754 (mode->hsync_end - mode->hsync_start == 32) &&
2755 (mode->vsync_start - mode->vdisplay == 3);
2759 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2760 * @dev: Device to duplicate against
2761 * @hsize: Mode width
2762 * @vsize: Mode height
2763 * @fresh: Mode refresh rate
2764 * @rb: Mode reduced-blanking-ness
2766 * Walk the DMT mode list looking for a match for the given parameters.
2768 * Return: A newly allocated copy of the mode, or NULL if not found.
2770 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2771 int hsize, int vsize, int fresh,
2776 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2777 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2779 if (hsize != ptr->hdisplay)
2781 if (vsize != ptr->vdisplay)
2783 if (fresh != drm_mode_vrefresh(ptr))
2785 if (rb != mode_is_rb(ptr))
2788 return drm_mode_duplicate(dev, ptr);
2793 EXPORT_SYMBOL(drm_mode_find_dmt);
2795 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2797 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2798 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2799 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2801 return descriptor->pixel_clock == 0 &&
2802 descriptor->data.other_data.pad1 == 0 &&
2803 descriptor->data.other_data.type == type;
2806 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2808 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2810 return descriptor->pixel_clock != 0;
2813 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2816 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2820 const u8 *det_base = ext + d;
2822 if (d < 4 || d > 127)
2826 for (i = 0; i < n; i++)
2827 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2831 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2833 unsigned int i, n = min((int)ext[0x02], 6);
2834 const u8 *det_base = ext + 5;
2837 return; /* unknown version */
2839 for (i = 0; i < n; i++)
2840 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2843 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
2844 detailed_cb *cb, void *closure)
2846 struct drm_edid_iter edid_iter;
2853 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2854 cb(&drm_edid->edid->detailed_timings[i], closure);
2856 drm_edid_iter_begin(drm_edid, &edid_iter);
2857 drm_edid_iter_for_each(ext, &edid_iter) {
2860 cea_for_each_detailed_block(ext, cb, closure);
2863 vtb_for_each_detailed_block(ext, cb, closure);
2869 drm_edid_iter_end(&edid_iter);
2873 is_rb(const struct detailed_timing *descriptor, void *data)
2877 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2880 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2881 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2883 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2884 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2888 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2890 drm_monitor_supports_rb(const struct drm_edid *drm_edid)
2892 if (drm_edid->edid->revision >= 4) {
2895 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
2899 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2903 find_gtf2(const struct detailed_timing *descriptor, void *data)
2905 const struct detailed_timing **res = data;
2907 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2910 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2912 if (descriptor->data.other_data.data.range.flags == 0x02)
2916 /* Secondary GTF curve kicks in above some break frequency */
2918 drm_gtf2_hbreak(const struct drm_edid *drm_edid)
2920 const struct detailed_timing *descriptor = NULL;
2922 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
2924 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
2926 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
2930 drm_gtf2_2c(const struct drm_edid *drm_edid)
2932 const struct detailed_timing *descriptor = NULL;
2934 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
2936 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
2938 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
2942 drm_gtf2_m(const struct drm_edid *drm_edid)
2944 const struct detailed_timing *descriptor = NULL;
2946 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
2948 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
2950 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
2954 drm_gtf2_k(const struct drm_edid *drm_edid)
2956 const struct detailed_timing *descriptor = NULL;
2958 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
2960 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
2962 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
2966 drm_gtf2_2j(const struct drm_edid *drm_edid)
2968 const struct detailed_timing *descriptor = NULL;
2970 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
2972 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
2974 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
2977 /* Get standard timing level (CVT/GTF/DMT). */
2978 static int standard_timing_level(const struct drm_edid *drm_edid)
2980 const struct edid *edid = drm_edid->edid;
2982 if (edid->revision >= 2) {
2983 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2985 if (drm_gtf2_hbreak(drm_edid))
2987 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2994 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2995 * monitors fill with ascii space (0x20) instead.
2998 bad_std_timing(u8 a, u8 b)
3000 return (a == 0x00 && b == 0x00) ||
3001 (a == 0x01 && b == 0x01) ||
3002 (a == 0x20 && b == 0x20);
3005 static int drm_mode_hsync(const struct drm_display_mode *mode)
3007 if (mode->htotal <= 0)
3010 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3014 * Take the standard timing params (in this case width, aspect, and refresh)
3015 * and convert them into a real mode using CVT/GTF/DMT.
3017 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3018 const struct drm_edid *drm_edid,
3019 const struct std_timing *t)
3021 struct drm_device *dev = connector->dev;
3022 struct drm_display_mode *m, *mode = NULL;
3025 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3026 >> EDID_TIMING_ASPECT_SHIFT;
3027 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3028 >> EDID_TIMING_VFREQ_SHIFT;
3029 int timing_level = standard_timing_level(drm_edid);
3031 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3034 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3035 hsize = t->hsize * 8 + 248;
3036 /* vrefresh_rate = vfreq + 60 */
3037 vrefresh_rate = vfreq + 60;
3038 /* the vdisplay is calculated based on the aspect ratio */
3039 if (aspect_ratio == 0) {
3040 if (drm_edid->edid->revision < 3)
3043 vsize = (hsize * 10) / 16;
3044 } else if (aspect_ratio == 1)
3045 vsize = (hsize * 3) / 4;
3046 else if (aspect_ratio == 2)
3047 vsize = (hsize * 4) / 5;
3049 vsize = (hsize * 9) / 16;
3051 /* HDTV hack, part 1 */
3052 if (vrefresh_rate == 60 &&
3053 ((hsize == 1360 && vsize == 765) ||
3054 (hsize == 1368 && vsize == 769))) {
3060 * If this connector already has a mode for this size and refresh
3061 * rate (because it came from detailed or CVT info), use that
3062 * instead. This way we don't have to guess at interlace or
3065 list_for_each_entry(m, &connector->probed_modes, head)
3066 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3067 drm_mode_vrefresh(m) == vrefresh_rate)
3070 /* HDTV hack, part 2 */
3071 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3072 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3076 mode->hdisplay = 1366;
3077 mode->hsync_start = mode->hsync_start - 1;
3078 mode->hsync_end = mode->hsync_end - 1;
3082 /* check whether it can be found in default mode table */
3083 if (drm_monitor_supports_rb(drm_edid)) {
3084 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3089 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3093 /* okay, generate it */
3094 switch (timing_level) {
3098 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3102 * This is potentially wrong if there's ever a monitor with
3103 * more than one ranges section, each claiming a different
3104 * secondary GTF curve. Please don't do that.
3106 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3109 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3110 drm_mode_destroy(dev, mode);
3111 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3112 vrefresh_rate, 0, 0,
3113 drm_gtf2_m(drm_edid),
3114 drm_gtf2_2c(drm_edid),
3115 drm_gtf2_k(drm_edid),
3116 drm_gtf2_2j(drm_edid));
3120 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3128 * EDID is delightfully ambiguous about how interlaced modes are to be
3129 * encoded. Our internal representation is of frame height, but some
3130 * HDTV detailed timings are encoded as field height.
3132 * The format list here is from CEA, in frame size. Technically we
3133 * should be checking refresh rate too. Whatever.
3136 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3137 const struct detailed_pixel_timing *pt)
3140 static const struct {
3142 } cea_interlaced[] = {
3152 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3155 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3156 if ((mode->hdisplay == cea_interlaced[i].w) &&
3157 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3158 mode->vdisplay *= 2;
3159 mode->vsync_start *= 2;
3160 mode->vsync_end *= 2;
3166 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3170 * Create a new mode from an EDID detailed timing section. An EDID detailed
3171 * timing block contains enough info for us to create and return a new struct
3174 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
3175 const struct drm_edid *drm_edid,
3176 const struct detailed_timing *timing,
3179 struct drm_display_mode *mode;
3180 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3181 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3182 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3183 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3184 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3185 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3186 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3187 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3188 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3190 /* ignore tiny modes */
3191 if (hactive < 64 || vactive < 64)
3194 if (pt->misc & DRM_EDID_PT_STEREO) {
3195 DRM_DEBUG_KMS("stereo mode not supported\n");
3198 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3199 DRM_DEBUG_KMS("composite sync not supported\n");
3202 /* it is incorrect if hsync/vsync width is zero */
3203 if (!hsync_pulse_width || !vsync_pulse_width) {
3204 DRM_DEBUG_KMS("Incorrect Detailed timing. "
3205 "Wrong Hsync/Vsync pulse width\n");
3209 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3210 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3217 mode = drm_mode_create(dev);
3221 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3222 mode->clock = 1088 * 10;
3224 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3226 mode->hdisplay = hactive;
3227 mode->hsync_start = mode->hdisplay + hsync_offset;
3228 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3229 mode->htotal = mode->hdisplay + hblank;
3231 mode->vdisplay = vactive;
3232 mode->vsync_start = mode->vdisplay + vsync_offset;
3233 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3234 mode->vtotal = mode->vdisplay + vblank;
3236 /* Some EDIDs have bogus h/vtotal values */
3237 if (mode->hsync_end > mode->htotal)
3238 mode->htotal = mode->hsync_end + 1;
3239 if (mode->vsync_end > mode->vtotal)
3240 mode->vtotal = mode->vsync_end + 1;
3242 drm_mode_do_interlace_quirk(mode, pt);
3244 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3245 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3247 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3248 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3249 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3250 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3254 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3255 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3257 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3258 mode->width_mm *= 10;
3259 mode->height_mm *= 10;
3262 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3263 mode->width_mm = drm_edid->edid->width_cm * 10;
3264 mode->height_mm = drm_edid->edid->height_cm * 10;
3267 mode->type = DRM_MODE_TYPE_DRIVER;
3268 drm_mode_set_name(mode);
3274 mode_in_hsync_range(const struct drm_display_mode *mode,
3275 const struct edid *edid, const u8 *t)
3277 int hsync, hmin, hmax;
3280 if (edid->revision >= 4)
3281 hmin += ((t[4] & 0x04) ? 255 : 0);
3283 if (edid->revision >= 4)
3284 hmax += ((t[4] & 0x08) ? 255 : 0);
3285 hsync = drm_mode_hsync(mode);
3287 return (hsync <= hmax && hsync >= hmin);
3291 mode_in_vsync_range(const struct drm_display_mode *mode,
3292 const struct edid *edid, const u8 *t)
3294 int vsync, vmin, vmax;
3297 if (edid->revision >= 4)
3298 vmin += ((t[4] & 0x01) ? 255 : 0);
3300 if (edid->revision >= 4)
3301 vmax += ((t[4] & 0x02) ? 255 : 0);
3302 vsync = drm_mode_vrefresh(mode);
3304 return (vsync <= vmax && vsync >= vmin);
3308 range_pixel_clock(const struct edid *edid, const u8 *t)
3311 if (t[9] == 0 || t[9] == 255)
3314 /* 1.4 with CVT support gives us real precision, yay */
3315 if (edid->revision >= 4 && t[10] == 0x04)
3316 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3318 /* 1.3 is pathetic, so fuzz up a bit */
3319 return t[9] * 10000 + 5001;
3322 static bool mode_in_range(const struct drm_display_mode *mode,
3323 const struct drm_edid *drm_edid,
3324 const struct detailed_timing *timing)
3326 const struct edid *edid = drm_edid->edid;
3328 const u8 *t = (const u8 *)timing;
3330 if (!mode_in_hsync_range(mode, edid, t))
3333 if (!mode_in_vsync_range(mode, edid, t))
3336 if ((max_clock = range_pixel_clock(edid, t)))
3337 if (mode->clock > max_clock)
3340 /* 1.4 max horizontal check */
3341 if (edid->revision >= 4 && t[10] == 0x04)
3342 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3345 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3351 static bool valid_inferred_mode(const struct drm_connector *connector,
3352 const struct drm_display_mode *mode)
3354 const struct drm_display_mode *m;
3357 list_for_each_entry(m, &connector->probed_modes, head) {
3358 if (mode->hdisplay == m->hdisplay &&
3359 mode->vdisplay == m->vdisplay &&
3360 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3361 return false; /* duplicated */
3362 if (mode->hdisplay <= m->hdisplay &&
3363 mode->vdisplay <= m->vdisplay)
3369 static int drm_dmt_modes_for_range(struct drm_connector *connector,
3370 const struct drm_edid *drm_edid,
3371 const struct detailed_timing *timing)
3374 struct drm_display_mode *newmode;
3375 struct drm_device *dev = connector->dev;
3377 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3378 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3379 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3380 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3382 drm_mode_probed_add(connector, newmode);
3391 /* fix up 1366x768 mode from 1368x768;
3392 * GFT/CVT can't express 1366 width which isn't dividable by 8
3394 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3396 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3397 mode->hdisplay = 1366;
3398 mode->hsync_start--;
3400 drm_mode_set_name(mode);
3404 static int drm_gtf_modes_for_range(struct drm_connector *connector,
3405 const struct drm_edid *drm_edid,
3406 const struct detailed_timing *timing)
3409 struct drm_display_mode *newmode;
3410 struct drm_device *dev = connector->dev;
3412 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3413 const struct minimode *m = &extra_modes[i];
3415 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3419 drm_mode_fixup_1366x768(newmode);
3420 if (!mode_in_range(newmode, drm_edid, timing) ||
3421 !valid_inferred_mode(connector, newmode)) {
3422 drm_mode_destroy(dev, newmode);
3426 drm_mode_probed_add(connector, newmode);
3433 static int drm_cvt_modes_for_range(struct drm_connector *connector,
3434 const struct drm_edid *drm_edid,
3435 const struct detailed_timing *timing)
3438 struct drm_display_mode *newmode;
3439 struct drm_device *dev = connector->dev;
3440 bool rb = drm_monitor_supports_rb(drm_edid);
3442 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3443 const struct minimode *m = &extra_modes[i];
3445 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3449 drm_mode_fixup_1366x768(newmode);
3450 if (!mode_in_range(newmode, drm_edid, timing) ||
3451 !valid_inferred_mode(connector, newmode)) {
3452 drm_mode_destroy(dev, newmode);
3456 drm_mode_probed_add(connector, newmode);
3464 do_inferred_modes(const struct detailed_timing *timing, void *c)
3466 struct detailed_mode_closure *closure = c;
3467 const struct detailed_non_pixel *data = &timing->data.other_data;
3468 const struct detailed_data_monitor_range *range = &data->data.range;
3470 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3473 closure->modes += drm_dmt_modes_for_range(closure->connector,
3477 if (!version_greater(closure->drm_edid, 1, 1))
3478 return; /* GTF not defined yet */
3480 switch (range->flags) {
3481 case 0x02: /* secondary gtf, XXX could do more */
3482 case 0x00: /* default gtf */
3483 closure->modes += drm_gtf_modes_for_range(closure->connector,
3487 case 0x04: /* cvt, only in 1.4+ */
3488 if (!version_greater(closure->drm_edid, 1, 3))
3491 closure->modes += drm_cvt_modes_for_range(closure->connector,
3495 case 0x01: /* just the ranges, no formula */
3501 static int add_inferred_modes(struct drm_connector *connector,
3502 const struct drm_edid *drm_edid)
3504 struct detailed_mode_closure closure = {
3505 .connector = connector,
3506 .drm_edid = drm_edid,
3509 if (version_greater(drm_edid, 1, 0))
3510 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3512 return closure.modes;
3516 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3518 int i, j, m, modes = 0;
3519 struct drm_display_mode *mode;
3520 const u8 *est = ((const u8 *)timing) + 6;
3522 for (i = 0; i < 6; i++) {
3523 for (j = 7; j >= 0; j--) {
3524 m = (i * 8) + (7 - j);
3525 if (m >= ARRAY_SIZE(est3_modes))
3527 if (est[i] & (1 << j)) {
3528 mode = drm_mode_find_dmt(connector->dev,
3534 drm_mode_probed_add(connector, mode);
3545 do_established_modes(const struct detailed_timing *timing, void *c)
3547 struct detailed_mode_closure *closure = c;
3549 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3552 closure->modes += drm_est3_modes(closure->connector, timing);
3556 * Get established modes from EDID and add them. Each EDID block contains a
3557 * bitmap of the supported "established modes" list (defined above). Tease them
3558 * out and add them to the global modes list.
3560 static int add_established_modes(struct drm_connector *connector,
3561 const struct drm_edid *drm_edid)
3563 struct drm_device *dev = connector->dev;
3564 const struct edid *edid = drm_edid->edid;
3565 unsigned long est_bits = edid->established_timings.t1 |
3566 (edid->established_timings.t2 << 8) |
3567 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3569 struct detailed_mode_closure closure = {
3570 .connector = connector,
3571 .drm_edid = drm_edid,
3574 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3575 if (est_bits & (1<<i)) {
3576 struct drm_display_mode *newmode;
3578 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3580 drm_mode_probed_add(connector, newmode);
3586 if (version_greater(drm_edid, 1, 0))
3587 drm_for_each_detailed_block(drm_edid, do_established_modes,
3590 return modes + closure.modes;
3594 do_standard_modes(const struct detailed_timing *timing, void *c)
3596 struct detailed_mode_closure *closure = c;
3597 const struct detailed_non_pixel *data = &timing->data.other_data;
3598 struct drm_connector *connector = closure->connector;
3601 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3604 for (i = 0; i < 6; i++) {
3605 const struct std_timing *std = &data->data.timings[i];
3606 struct drm_display_mode *newmode;
3608 newmode = drm_mode_std(connector, closure->drm_edid, std);
3610 drm_mode_probed_add(connector, newmode);
3617 * Get standard modes from EDID and add them. Standard modes can be calculated
3618 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3619 * add them to the list.
3621 static int add_standard_modes(struct drm_connector *connector,
3622 const struct drm_edid *drm_edid)
3625 struct detailed_mode_closure closure = {
3626 .connector = connector,
3627 .drm_edid = drm_edid,
3630 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3631 struct drm_display_mode *newmode;
3633 newmode = drm_mode_std(connector, drm_edid,
3634 &drm_edid->edid->standard_timings[i]);
3636 drm_mode_probed_add(connector, newmode);
3641 if (version_greater(drm_edid, 1, 0))
3642 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3645 /* XXX should also look for standard codes in VTB blocks */
3647 return modes + closure.modes;
3650 static int drm_cvt_modes(struct drm_connector *connector,
3651 const struct detailed_timing *timing)
3653 int i, j, modes = 0;
3654 struct drm_display_mode *newmode;
3655 struct drm_device *dev = connector->dev;
3656 const struct cvt_timing *cvt;
3657 const int rates[] = { 60, 85, 75, 60, 50 };
3658 const u8 empty[3] = { 0, 0, 0 };
3660 for (i = 0; i < 4; i++) {
3663 cvt = &(timing->data.other_data.data.cvt[i]);
3665 if (!memcmp(cvt->code, empty, 3))
3668 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3669 switch (cvt->code[1] & 0x0c) {
3670 /* default - because compiler doesn't see that we've enumerated all cases */
3673 width = height * 4 / 3;
3676 width = height * 16 / 9;
3679 width = height * 16 / 10;
3682 width = height * 15 / 9;
3686 for (j = 1; j < 5; j++) {
3687 if (cvt->code[2] & (1 << j)) {
3688 newmode = drm_cvt_mode(dev, width, height,
3692 drm_mode_probed_add(connector, newmode);
3703 do_cvt_mode(const struct detailed_timing *timing, void *c)
3705 struct detailed_mode_closure *closure = c;
3707 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3710 closure->modes += drm_cvt_modes(closure->connector, timing);
3714 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
3716 struct detailed_mode_closure closure = {
3717 .connector = connector,
3718 .drm_edid = drm_edid,
3721 if (version_greater(drm_edid, 1, 2))
3722 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
3724 /* XXX should also look for CVT codes in VTB blocks */
3726 return closure.modes;
3729 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3732 do_detailed_mode(const struct detailed_timing *timing, void *c)
3734 struct detailed_mode_closure *closure = c;
3735 struct drm_display_mode *newmode;
3737 if (!is_detailed_timing_descriptor(timing))
3740 newmode = drm_mode_detailed(closure->connector->dev,
3741 closure->drm_edid, timing,
3746 if (closure->preferred)
3747 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3750 * Detailed modes are limited to 10kHz pixel clock resolution,
3751 * so fix up anything that looks like CEA/HDMI mode, but the clock
3752 * is just slightly off.
3754 fixup_detailed_cea_mode_clock(newmode);
3756 drm_mode_probed_add(closure->connector, newmode);
3758 closure->preferred = false;
3762 * add_detailed_modes - Add modes from detailed timings
3763 * @connector: attached connector
3764 * @drm_edid: EDID block to scan
3765 * @quirks: quirks to apply
3767 static int add_detailed_modes(struct drm_connector *connector,
3768 const struct drm_edid *drm_edid, u32 quirks)
3770 struct detailed_mode_closure closure = {
3771 .connector = connector,
3772 .drm_edid = drm_edid,
3777 if (closure.preferred && !version_greater(drm_edid, 1, 3))
3779 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3781 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
3783 return closure.modes;
3786 /* CTA-861-H Table 60 - CTA Tag Codes */
3787 #define CTA_DB_AUDIO 1
3788 #define CTA_DB_VIDEO 2
3789 #define CTA_DB_VENDOR 3
3790 #define CTA_DB_SPEAKER 4
3791 #define CTA_DB_EXTENDED_TAG 7
3793 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
3794 #define CTA_EXT_DB_VIDEO_CAP 0
3795 #define CTA_EXT_DB_VENDOR 1
3796 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
3797 #define CTA_EXT_DB_420_VIDEO_DATA 14
3798 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
3799 #define CTA_EXT_DB_HF_SCDB 0x79
3801 #define EDID_BASIC_AUDIO (1 << 6)
3802 #define EDID_CEA_YCRCB444 (1 << 5)
3803 #define EDID_CEA_YCRCB422 (1 << 4)
3804 #define EDID_CEA_VCDB_QS (1 << 6)
3807 * Search EDID for CEA extension block.
3809 * FIXME: Prefer not returning pointers to raw EDID data.
3811 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
3812 int ext_id, int *ext_index)
3814 const u8 *edid_ext = NULL;
3817 /* No EDID or EDID extensions */
3818 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
3821 /* Find CEA extension */
3822 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
3823 edid_ext = drm_edid_extension_block_data(drm_edid, i);
3824 if (edid_block_tag(edid_ext) == ext_id)
3828 if (i >= drm_edid_extension_block_count(drm_edid))
3836 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
3837 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
3839 const struct displayid_block *block;
3840 struct displayid_iter iter;
3844 /* Look for a top level CEA extension block */
3845 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
3848 /* CEA blocks can also be found embedded in a DisplayID block */
3849 displayid_iter_edid_begin(drm_edid, &iter);
3850 displayid_iter_for_each(block, &iter) {
3851 if (block->tag == DATA_BLOCK_CTA) {
3856 displayid_iter_end(&iter);
3861 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3863 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3864 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3866 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3867 return &edid_cea_modes_1[vic - 1];
3868 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3869 return &edid_cea_modes_193[vic - 193];
3873 static u8 cea_num_vics(void)
3875 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3878 static u8 cea_next_vic(u8 vic)
3880 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3886 * Calculate the alternate clock for the CEA mode
3887 * (60Hz vs. 59.94Hz etc.)
3890 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3892 unsigned int clock = cea_mode->clock;
3894 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3898 * edid_cea_modes contains the 59.94Hz
3899 * variant for 240 and 480 line modes,
3900 * and the 60Hz variant otherwise.
3902 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3903 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3905 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3911 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3914 * For certain VICs the spec allows the vertical
3915 * front porch to vary by one or two lines.
3917 * cea_modes[] stores the variant with the shortest
3918 * vertical front porch. We can adjust the mode to
3919 * get the other variants by simply increasing the
3920 * vertical front porch length.
3922 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3923 cea_mode_for_vic(9)->vtotal != 262 ||
3924 cea_mode_for_vic(12)->vtotal != 262 ||
3925 cea_mode_for_vic(13)->vtotal != 262 ||
3926 cea_mode_for_vic(23)->vtotal != 312 ||
3927 cea_mode_for_vic(24)->vtotal != 312 ||
3928 cea_mode_for_vic(27)->vtotal != 312 ||
3929 cea_mode_for_vic(28)->vtotal != 312);
3931 if (((vic == 8 || vic == 9 ||
3932 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3933 ((vic == 23 || vic == 24 ||
3934 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3935 mode->vsync_start++;
3945 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3946 unsigned int clock_tolerance)
3948 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3951 if (!to_match->clock)
3954 if (to_match->picture_aspect_ratio)
3955 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3957 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3958 struct drm_display_mode cea_mode;
3959 unsigned int clock1, clock2;
3961 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
3963 /* Check both 60Hz and 59.94Hz */
3964 clock1 = cea_mode.clock;
3965 clock2 = cea_mode_alternate_clock(&cea_mode);
3967 if (abs(to_match->clock - clock1) > clock_tolerance &&
3968 abs(to_match->clock - clock2) > clock_tolerance)
3972 if (drm_mode_match(to_match, &cea_mode, match_flags))
3974 } while (cea_mode_alternate_timings(vic, &cea_mode));
3981 * drm_match_cea_mode - look for a CEA mode matching given mode
3982 * @to_match: display mode
3984 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3987 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3989 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3992 if (!to_match->clock)
3995 if (to_match->picture_aspect_ratio)
3996 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3998 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3999 struct drm_display_mode cea_mode;
4000 unsigned int clock1, clock2;
4002 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4004 /* Check both 60Hz and 59.94Hz */
4005 clock1 = cea_mode.clock;
4006 clock2 = cea_mode_alternate_clock(&cea_mode);
4008 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4009 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4013 if (drm_mode_match(to_match, &cea_mode, match_flags))
4015 } while (cea_mode_alternate_timings(vic, &cea_mode));
4020 EXPORT_SYMBOL(drm_match_cea_mode);
4022 static bool drm_valid_cea_vic(u8 vic)
4024 return cea_mode_for_vic(vic) != NULL;
4027 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4029 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4032 return mode->picture_aspect_ratio;
4034 return HDMI_PICTURE_ASPECT_NONE;
4037 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4039 return edid_4k_modes[video_code].picture_aspect_ratio;
4043 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4047 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4049 return cea_mode_alternate_clock(hdmi_mode);
4052 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4053 unsigned int clock_tolerance)
4055 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4058 if (!to_match->clock)
4061 if (to_match->picture_aspect_ratio)
4062 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4064 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4065 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4066 unsigned int clock1, clock2;
4068 /* Make sure to also match alternate clocks */
4069 clock1 = hdmi_mode->clock;
4070 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4072 if (abs(to_match->clock - clock1) > clock_tolerance &&
4073 abs(to_match->clock - clock2) > clock_tolerance)
4076 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4084 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4085 * @to_match: display mode
4087 * An HDMI mode is one defined in the HDMI vendor specific block.
4089 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4091 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4093 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4096 if (!to_match->clock)
4099 if (to_match->picture_aspect_ratio)
4100 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4102 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4103 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4104 unsigned int clock1, clock2;
4106 /* Make sure to also match alternate clocks */
4107 clock1 = hdmi_mode->clock;
4108 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4110 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4111 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4112 drm_mode_match(to_match, hdmi_mode, match_flags))
4118 static bool drm_valid_hdmi_vic(u8 vic)
4120 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4123 static int add_alternate_cea_modes(struct drm_connector *connector,
4124 const struct drm_edid *drm_edid)
4126 struct drm_device *dev = connector->dev;
4127 struct drm_display_mode *mode, *tmp;
4131 /* Don't add CTA modes if the CTA extension block is missing */
4132 if (!drm_edid_has_cta_extension(drm_edid))
4136 * Go through all probed modes and create a new mode
4137 * with the alternate clock for certain CEA modes.
4139 list_for_each_entry(mode, &connector->probed_modes, head) {
4140 const struct drm_display_mode *cea_mode = NULL;
4141 struct drm_display_mode *newmode;
4142 u8 vic = drm_match_cea_mode(mode);
4143 unsigned int clock1, clock2;
4145 if (drm_valid_cea_vic(vic)) {
4146 cea_mode = cea_mode_for_vic(vic);
4147 clock2 = cea_mode_alternate_clock(cea_mode);
4149 vic = drm_match_hdmi_mode(mode);
4150 if (drm_valid_hdmi_vic(vic)) {
4151 cea_mode = &edid_4k_modes[vic];
4152 clock2 = hdmi_mode_alternate_clock(cea_mode);
4159 clock1 = cea_mode->clock;
4161 if (clock1 == clock2)
4164 if (mode->clock != clock1 && mode->clock != clock2)
4167 newmode = drm_mode_duplicate(dev, cea_mode);
4171 /* Carry over the stereo flags */
4172 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4175 * The current mode could be either variant. Make
4176 * sure to pick the "other" clock for the new mode.
4178 if (mode->clock != clock1)
4179 newmode->clock = clock1;
4181 newmode->clock = clock2;
4183 list_add_tail(&newmode->head, &list);
4186 list_for_each_entry_safe(mode, tmp, &list, head) {
4187 list_del(&mode->head);
4188 drm_mode_probed_add(connector, mode);
4195 static u8 svd_to_vic(u8 svd)
4197 /* 0-6 bit vic, 7th bit native mode indicator */
4198 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4204 static struct drm_display_mode *
4205 drm_display_mode_from_vic_index(struct drm_connector *connector,
4206 const u8 *video_db, u8 video_len,
4209 struct drm_device *dev = connector->dev;
4210 struct drm_display_mode *newmode;
4213 if (video_db == NULL || video_index >= video_len)
4216 /* CEA modes are numbered 1..127 */
4217 vic = svd_to_vic(video_db[video_index]);
4218 if (!drm_valid_cea_vic(vic))
4221 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4229 * do_y420vdb_modes - Parse YCBCR 420 only modes
4230 * @connector: connector corresponding to the HDMI sink
4231 * @svds: start of the data block of CEA YCBCR 420 VDB
4232 * @len: length of the CEA YCBCR 420 VDB
4234 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4235 * which contains modes which can be supported in YCBCR 420
4236 * output format only.
4238 static int do_y420vdb_modes(struct drm_connector *connector,
4239 const u8 *svds, u8 svds_len)
4242 struct drm_device *dev = connector->dev;
4243 struct drm_display_info *info = &connector->display_info;
4244 struct drm_hdmi_info *hdmi = &info->hdmi;
4246 for (i = 0; i < svds_len; i++) {
4247 u8 vic = svd_to_vic(svds[i]);
4248 struct drm_display_mode *newmode;
4250 if (!drm_valid_cea_vic(vic))
4253 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4256 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4257 drm_mode_probed_add(connector, newmode);
4262 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4267 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4268 * @connector: connector corresponding to the HDMI sink
4269 * @vic: CEA vic for the video mode to be added in the map
4271 * Makes an entry for a videomode in the YCBCR 420 bitmap
4274 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4276 u8 vic = svd_to_vic(svd);
4277 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4279 if (!drm_valid_cea_vic(vic))
4282 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4286 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4288 * @video_code: CEA VIC of the mode
4290 * Creates a new mode matching the specified CEA VIC.
4292 * Returns: A new drm_display_mode on success or NULL on failure
4294 struct drm_display_mode *
4295 drm_display_mode_from_cea_vic(struct drm_device *dev,
4298 const struct drm_display_mode *cea_mode;
4299 struct drm_display_mode *newmode;
4301 cea_mode = cea_mode_for_vic(video_code);
4305 newmode = drm_mode_duplicate(dev, cea_mode);
4311 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4314 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4317 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4319 for (i = 0; i < len; i++) {
4320 struct drm_display_mode *mode;
4322 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4325 * YCBCR420 capability block contains a bitmap which
4326 * gives the index of CEA modes from CEA VDB, which
4327 * can support YCBCR 420 sampling output also (apart
4328 * from RGB/YCBCR444 etc).
4329 * For example, if the bit 0 in bitmap is set,
4330 * first mode in VDB can support YCBCR420 output too.
4331 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4333 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4334 drm_add_cmdb_modes(connector, db[i]);
4336 drm_mode_probed_add(connector, mode);
4344 struct stereo_mandatory_mode {
4345 int width, height, vrefresh;
4349 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4350 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4351 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4353 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4355 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4356 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4357 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4358 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4359 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4363 stereo_match_mandatory(const struct drm_display_mode *mode,
4364 const struct stereo_mandatory_mode *stereo_mode)
4366 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4368 return mode->hdisplay == stereo_mode->width &&
4369 mode->vdisplay == stereo_mode->height &&
4370 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4371 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4374 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4376 struct drm_device *dev = connector->dev;
4377 const struct drm_display_mode *mode;
4378 struct list_head stereo_modes;
4381 INIT_LIST_HEAD(&stereo_modes);
4383 list_for_each_entry(mode, &connector->probed_modes, head) {
4384 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4385 const struct stereo_mandatory_mode *mandatory;
4386 struct drm_display_mode *new_mode;
4388 if (!stereo_match_mandatory(mode,
4389 &stereo_mandatory_modes[i]))
4392 mandatory = &stereo_mandatory_modes[i];
4393 new_mode = drm_mode_duplicate(dev, mode);
4397 new_mode->flags |= mandatory->flags;
4398 list_add_tail(&new_mode->head, &stereo_modes);
4403 list_splice_tail(&stereo_modes, &connector->probed_modes);
4408 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4410 struct drm_device *dev = connector->dev;
4411 struct drm_display_mode *newmode;
4413 if (!drm_valid_hdmi_vic(vic)) {
4414 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4418 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4422 drm_mode_probed_add(connector, newmode);
4427 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4428 const u8 *video_db, u8 video_len, u8 video_index)
4430 struct drm_display_mode *newmode;
4433 if (structure & (1 << 0)) {
4434 newmode = drm_display_mode_from_vic_index(connector, video_db,
4438 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4439 drm_mode_probed_add(connector, newmode);
4443 if (structure & (1 << 6)) {
4444 newmode = drm_display_mode_from_vic_index(connector, video_db,
4448 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4449 drm_mode_probed_add(connector, newmode);
4453 if (structure & (1 << 8)) {
4454 newmode = drm_display_mode_from_vic_index(connector, video_db,
4458 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4459 drm_mode_probed_add(connector, newmode);
4468 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4469 * @connector: connector corresponding to the HDMI sink
4470 * @db: start of the CEA vendor specific block
4471 * @len: length of the CEA block payload, ie. one can access up to db[len]
4473 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4474 * also adds the stereo 3d modes when applicable.
4477 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4478 const u8 *video_db, u8 video_len)
4480 struct drm_display_info *info = &connector->display_info;
4481 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4482 u8 vic_len, hdmi_3d_len = 0;
4489 /* no HDMI_Video_Present */
4490 if (!(db[8] & (1 << 5)))
4493 /* Latency_Fields_Present */
4494 if (db[8] & (1 << 7))
4497 /* I_Latency_Fields_Present */
4498 if (db[8] & (1 << 6))
4501 /* the declared length is not long enough for the 2 first bytes
4502 * of additional video format capabilities */
4503 if (len < (8 + offset + 2))
4508 if (db[8 + offset] & (1 << 7)) {
4509 modes += add_hdmi_mandatory_stereo_modes(connector);
4511 /* 3D_Multi_present */
4512 multi_present = (db[8 + offset] & 0x60) >> 5;
4516 vic_len = db[8 + offset] >> 5;
4517 hdmi_3d_len = db[8 + offset] & 0x1f;
4519 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4522 vic = db[9 + offset + i];
4523 modes += add_hdmi_mode(connector, vic);
4525 offset += 1 + vic_len;
4527 if (multi_present == 1)
4529 else if (multi_present == 2)
4534 if (len < (8 + offset + hdmi_3d_len - 1))
4537 if (hdmi_3d_len < multi_len)
4540 if (multi_present == 1 || multi_present == 2) {
4541 /* 3D_Structure_ALL */
4542 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4544 /* check if 3D_MASK is present */
4545 if (multi_present == 2)
4546 mask = (db[10 + offset] << 8) | db[11 + offset];
4550 for (i = 0; i < 16; i++) {
4551 if (mask & (1 << i))
4552 modes += add_3d_struct_modes(connector,
4559 offset += multi_len;
4561 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4563 struct drm_display_mode *newmode = NULL;
4564 unsigned int newflag = 0;
4565 bool detail_present;
4567 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4569 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4572 /* 2D_VIC_order_X */
4573 vic_index = db[8 + offset + i] >> 4;
4575 /* 3D_Structure_X */
4576 switch (db[8 + offset + i] & 0x0f) {
4578 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4581 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4585 if ((db[9 + offset + i] >> 4) == 1)
4586 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4591 newmode = drm_display_mode_from_vic_index(connector,
4597 newmode->flags |= newflag;
4598 drm_mode_probed_add(connector, newmode);
4609 info->has_hdmi_infoframe = true;
4614 cea_revision(const u8 *cea)
4617 * FIXME is this correct for the DispID variant?
4618 * The DispID spec doesn't really specify whether
4619 * this is the revision of the CEA extension or
4620 * the DispID CEA data block. And the only value
4621 * given as an example is 0.
4627 * CTA Data Block iterator.
4629 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4632 * struct cea_db *db:
4633 * struct cea_db_iter iter;
4635 * cea_db_iter_edid_begin(edid, &iter);
4636 * cea_db_iter_for_each(db, &iter) {
4637 * // do stuff with db
4639 * cea_db_iter_end(&iter);
4641 struct cea_db_iter {
4642 struct drm_edid_iter edid_iter;
4643 struct displayid_iter displayid_iter;
4645 /* Current Data Block Collection. */
4646 const u8 *collection;
4648 /* Current Data Block index in current collection. */
4651 /* End index in current collection. */
4655 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4661 static int cea_db_tag(const struct cea_db *db)
4663 return db->tag_length >> 5;
4666 static int cea_db_payload_len(const void *_db)
4668 /* FIXME: Transition to passing struct cea_db * everywhere. */
4669 const struct cea_db *db = _db;
4671 return db->tag_length & 0x1f;
4674 static const void *cea_db_data(const struct cea_db *db)
4679 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4681 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4682 cea_db_payload_len(db) >= 1 &&
4686 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4688 const u8 *data = cea_db_data(db);
4690 return cea_db_tag(db) == CTA_DB_VENDOR &&
4691 cea_db_payload_len(db) >= 3 &&
4692 oui(data[2], data[1], data[0]) == vendor_oui;
4695 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4696 struct cea_db_iter *iter)
4698 memset(iter, 0, sizeof(*iter));
4700 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4701 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4704 static const struct cea_db *
4705 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4707 const struct cea_db *db;
4709 if (!iter->collection)
4712 db = (const struct cea_db *)&iter->collection[iter->index];
4714 if (iter->index + sizeof(*db) <= iter->end &&
4715 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4723 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4725 static int cea_db_collection_size(const u8 *cta)
4729 if (d < 4 || d > 127)
4737 * - VESA E-EDID v1.4
4738 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4740 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4744 drm_edid_iter_for_each(ext, &iter->edid_iter) {
4747 /* Only support CTA Extension revision 3+ */
4748 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4751 size = cea_db_collection_size(ext);
4756 iter->end = iter->index + size;
4766 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4767 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4769 * Note that the above do not specify any connection between DisplayID Data
4770 * Block revision and CTA Extension versions.
4772 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4774 const struct displayid_block *block;
4776 displayid_iter_for_each(block, &iter->displayid_iter) {
4777 if (block->tag != DATA_BLOCK_CTA)
4781 * The displayid iterator has already verified the block bounds
4782 * in displayid_iter_block().
4784 iter->index = sizeof(*block);
4785 iter->end = iter->index + block->num_bytes;
4793 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
4795 const struct cea_db *db;
4797 if (iter->collection) {
4798 /* Current collection should always be valid. */
4799 db = __cea_db_iter_current_block(iter);
4801 iter->collection = NULL;
4805 /* Next block in CTA Data Block Collection */
4806 iter->index += sizeof(*db) + cea_db_payload_len(db);
4808 db = __cea_db_iter_current_block(iter);
4815 * Find the next CTA Data Block Collection. First iterate all
4816 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
4818 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
4819 * Extension, it's recommended that DisplayID extensions are
4820 * exposed after all of the CTA Extensions.
4822 iter->collection = __cea_db_iter_edid_next(iter);
4823 if (!iter->collection)
4824 iter->collection = __cea_db_iter_displayid_next(iter);
4826 if (!iter->collection)
4829 db = __cea_db_iter_current_block(iter);
4835 #define cea_db_iter_for_each(__db, __iter) \
4836 while (((__db) = __cea_db_iter_next(__iter)))
4838 static void cea_db_iter_end(struct cea_db_iter *iter)
4840 displayid_iter_end(&iter->displayid_iter);
4841 drm_edid_iter_end(&iter->edid_iter);
4843 memset(iter, 0, sizeof(*iter));
4846 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
4848 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
4849 cea_db_payload_len(db) >= 5;
4852 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
4854 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
4855 cea_db_payload_len(db) >= 7;
4858 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
4860 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
4861 cea_db_payload_len(db) == 21;
4864 static bool cea_db_is_vcdb(const struct cea_db *db)
4866 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
4867 cea_db_payload_len(db) == 2;
4870 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
4872 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
4873 cea_db_payload_len(db) >= 7;
4876 static bool cea_db_is_y420cmdb(const struct cea_db *db)
4878 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
4881 static bool cea_db_is_y420vdb(const struct cea_db *db)
4883 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
4886 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
4888 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
4889 cea_db_payload_len(db) >= 3;
4892 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4895 struct drm_display_info *info = &connector->display_info;
4896 struct drm_hdmi_info *hdmi = &info->hdmi;
4897 u8 map_len = cea_db_payload_len(db) - 1;
4902 /* All CEA modes support ycbcr420 sampling also.*/
4903 hdmi->y420_cmdb_map = U64_MAX;
4904 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4909 * This map indicates which of the existing CEA block modes
4910 * from VDB can support YCBCR420 output too. So if bit=0 is
4911 * set, first mode from VDB can support YCBCR420 output too.
4912 * We will parse and keep this map, before parsing VDB itself
4913 * to avoid going through the same block again and again.
4915 * Spec is not clear about max possible size of this block.
4916 * Clamping max bitmap block size at 8 bytes. Every byte can
4917 * address 8 CEA modes, in this way this map can address
4918 * 8*8 = first 64 SVDs.
4920 if (WARN_ON_ONCE(map_len > 8))
4923 for (count = 0; count < map_len; count++)
4924 map |= (u64)db[2 + count] << (8 * count);
4927 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4929 hdmi->y420_cmdb_map = map;
4932 static int add_cea_modes(struct drm_connector *connector,
4933 const struct drm_edid *drm_edid)
4935 const struct cea_db *db;
4936 struct cea_db_iter iter;
4939 cea_db_iter_edid_begin(drm_edid, &iter);
4940 cea_db_iter_for_each(db, &iter) {
4941 const u8 *hdmi = NULL, *video = NULL;
4942 u8 hdmi_len = 0, video_len = 0;
4944 if (cea_db_tag(db) == CTA_DB_VIDEO) {
4945 video = cea_db_data(db);
4946 video_len = cea_db_payload_len(db);
4947 modes += do_cea_modes(connector, video, video_len);
4948 } else if (cea_db_is_hdmi_vsdb(db)) {
4949 /* FIXME: Switch to use cea_db_data() */
4950 hdmi = (const u8 *)db;
4951 hdmi_len = cea_db_payload_len(db);
4952 } else if (cea_db_is_y420vdb(db)) {
4953 const u8 *vdb420 = cea_db_data(db) + 1;
4955 /* Add 4:2:0(only) modes present in EDID */
4956 modes += do_y420vdb_modes(connector, vdb420,
4957 cea_db_payload_len(db) - 1);
4961 * We parse the HDMI VSDB after having added the cea modes as we
4962 * will be patching their flags when the sink supports stereo
4966 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
4969 cea_db_iter_end(&iter);
4974 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4976 const struct drm_display_mode *cea_mode;
4977 int clock1, clock2, clock;
4982 * allow 5kHz clock difference either way to account for
4983 * the 10kHz clock resolution limit of detailed timings.
4985 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4986 if (drm_valid_cea_vic(vic)) {
4988 cea_mode = cea_mode_for_vic(vic);
4989 clock1 = cea_mode->clock;
4990 clock2 = cea_mode_alternate_clock(cea_mode);
4992 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4993 if (drm_valid_hdmi_vic(vic)) {
4995 cea_mode = &edid_4k_modes[vic];
4996 clock1 = cea_mode->clock;
4997 clock2 = hdmi_mode_alternate_clock(cea_mode);
5003 /* pick whichever is closest */
5004 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5009 if (mode->clock == clock)
5012 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5013 type, vic, mode->clock, clock);
5014 mode->clock = clock;
5017 static uint8_t eotf_supported(const u8 *edid_ext)
5019 return edid_ext[2] &
5020 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5021 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5022 BIT(HDMI_EOTF_SMPTE_ST2084) |
5023 BIT(HDMI_EOTF_BT_2100_HLG));
5026 static uint8_t hdr_metadata_type(const u8 *edid_ext)
5028 return edid_ext[3] &
5029 BIT(HDMI_STATIC_METADATA_TYPE1);
5033 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5037 len = cea_db_payload_len(db);
5039 connector->hdr_sink_metadata.hdmi_type1.eotf =
5041 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5042 hdr_metadata_type(db);
5045 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5047 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5049 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5053 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5055 u8 len = cea_db_payload_len(db);
5057 if (len >= 6 && (db[6] & (1 << 7)))
5058 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5060 connector->latency_present[0] = db[8] >> 7;
5061 connector->latency_present[1] = (db[8] >> 6) & 1;
5064 connector->video_latency[0] = db[9];
5066 connector->audio_latency[0] = db[10];
5068 connector->video_latency[1] = db[11];
5070 connector->audio_latency[1] = db[12];
5072 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
5073 "video latency %d %d, "
5074 "audio latency %d %d\n",
5075 connector->latency_present[0],
5076 connector->latency_present[1],
5077 connector->video_latency[0],
5078 connector->video_latency[1],
5079 connector->audio_latency[0],
5080 connector->audio_latency[1]);
5084 monitor_name(const struct detailed_timing *timing, void *data)
5086 const char **res = data;
5088 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5091 *res = timing->data.other_data.data.str.str;
5094 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5096 const char *edid_name = NULL;
5099 if (!drm_edid || !name)
5102 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5103 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5104 if (edid_name[mnl] == 0x0a)
5107 name[mnl] = edid_name[mnl];
5114 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5115 * @edid: monitor EDID information
5116 * @name: pointer to a character array to hold the name of the monitor
5117 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5120 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5122 int name_length = 0;
5129 struct drm_edid drm_edid = {
5131 .size = edid_size(edid),
5134 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5135 memcpy(name, buf, name_length);
5138 name[name_length] = '\0';
5140 EXPORT_SYMBOL(drm_edid_get_monitor_name);
5142 static void clear_eld(struct drm_connector *connector)
5144 memset(connector->eld, 0, sizeof(connector->eld));
5146 connector->latency_present[0] = false;
5147 connector->latency_present[1] = false;
5148 connector->video_latency[0] = 0;
5149 connector->audio_latency[0] = 0;
5150 connector->video_latency[1] = 0;
5151 connector->audio_latency[1] = 0;
5155 * drm_edid_to_eld - build ELD from EDID
5156 * @connector: connector corresponding to the HDMI/DP sink
5157 * @drm_edid: EDID to parse
5159 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5160 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5162 static void drm_edid_to_eld(struct drm_connector *connector,
5163 const struct drm_edid *drm_edid)
5165 const struct drm_display_info *info = &connector->display_info;
5166 const struct cea_db *db;
5167 struct cea_db_iter iter;
5168 uint8_t *eld = connector->eld;
5169 int total_sad_count = 0;
5172 clear_eld(connector);
5177 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5178 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
5180 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5181 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5183 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5185 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5186 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5187 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5188 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5190 cea_db_iter_edid_begin(drm_edid, &iter);
5191 cea_db_iter_for_each(db, &iter) {
5192 const u8 *data = cea_db_data(db);
5193 int len = cea_db_payload_len(db);
5196 switch (cea_db_tag(db)) {
5198 /* Audio Data Block, contains SADs */
5199 sad_count = min(len / 3, 15 - total_sad_count);
5201 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5202 data, sad_count * 3);
5203 total_sad_count += sad_count;
5205 case CTA_DB_SPEAKER:
5206 /* Speaker Allocation Data Block */
5208 eld[DRM_ELD_SPEAKER] = data[0];
5211 /* HDMI Vendor-Specific Data Block */
5212 if (cea_db_is_hdmi_vsdb(db))
5213 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5219 cea_db_iter_end(&iter);
5221 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5223 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5224 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5225 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5227 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5229 eld[DRM_ELD_BASELINE_ELD_LEN] =
5230 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5232 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
5233 drm_eld_size(eld), total_sad_count);
5236 static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5237 struct cea_sad **sads)
5239 const struct cea_db *db;
5240 struct cea_db_iter iter;
5243 cea_db_iter_edid_begin(drm_edid, &iter);
5244 cea_db_iter_for_each(db, &iter) {
5245 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5248 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5249 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
5252 for (j = 0; j < count; j++) {
5253 const u8 *sad = &db->data[j * 3];
5255 (*sads)[j].format = (sad[0] & 0x78) >> 3;
5256 (*sads)[j].channels = sad[0] & 0x7;
5257 (*sads)[j].freq = sad[1] & 0x7F;
5258 (*sads)[j].byte2 = sad[2];
5263 cea_db_iter_end(&iter);
5265 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5271 * drm_edid_to_sad - extracts SADs from EDID
5272 * @edid: EDID to parse
5273 * @sads: pointer that will be set to the extracted SADs
5275 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5277 * Note: The returned pointer needs to be freed using kfree().
5279 * Return: The number of found SADs or negative number on error.
5281 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5283 struct drm_edid drm_edid;
5285 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5287 EXPORT_SYMBOL(drm_edid_to_sad);
5289 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5292 const struct cea_db *db;
5293 struct cea_db_iter iter;
5296 cea_db_iter_edid_begin(drm_edid, &iter);
5297 cea_db_iter_for_each(db, &iter) {
5298 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5299 cea_db_payload_len(db) == 3) {
5300 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5304 count = cea_db_payload_len(db);
5308 cea_db_iter_end(&iter);
5310 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5316 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5317 * @edid: EDID to parse
5318 * @sadb: pointer to the speaker block
5320 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5322 * Note: The returned pointer needs to be freed using kfree().
5324 * Return: The number of found Speaker Allocation Blocks or negative number on
5327 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5329 struct drm_edid drm_edid;
5331 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5334 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5337 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5338 * @connector: connector associated with the HDMI/DP sink
5339 * @mode: the display mode
5341 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5342 * the sink doesn't support audio or video.
5344 int drm_av_sync_delay(struct drm_connector *connector,
5345 const struct drm_display_mode *mode)
5347 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5350 if (!connector->latency_present[0])
5352 if (!connector->latency_present[1])
5355 a = connector->audio_latency[i];
5356 v = connector->video_latency[i];
5359 * HDMI/DP sink doesn't support audio or video?
5361 if (a == 255 || v == 255)
5365 * Convert raw EDID values to millisecond.
5366 * Treat unknown latency as 0ms.
5369 a = min(2 * (a - 1), 500);
5371 v = min(2 * (v - 1), 500);
5373 return max(v - a, 0);
5375 EXPORT_SYMBOL(drm_av_sync_delay);
5377 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5379 const struct cea_db *db;
5380 struct cea_db_iter iter;
5384 * Because HDMI identifier is in Vendor Specific Block,
5385 * search it from all data blocks of CEA extension.
5387 cea_db_iter_edid_begin(drm_edid, &iter);
5388 cea_db_iter_for_each(db, &iter) {
5389 if (cea_db_is_hdmi_vsdb(db)) {
5394 cea_db_iter_end(&iter);
5400 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5401 * @edid: monitor EDID information
5403 * Parse the CEA extension according to CEA-861-B.
5405 * Drivers that have added the modes parsed from EDID to drm_display_info
5406 * should use &drm_display_info.is_hdmi instead of calling this function.
5408 * Return: True if the monitor is HDMI, false if not or unknown.
5410 bool drm_detect_hdmi_monitor(const struct edid *edid)
5412 struct drm_edid drm_edid;
5414 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5416 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5418 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5420 struct drm_edid_iter edid_iter;
5421 const struct cea_db *db;
5422 struct cea_db_iter iter;
5424 bool has_audio = false;
5426 drm_edid_iter_begin(drm_edid, &edid_iter);
5427 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5428 if (edid_ext[0] == CEA_EXT) {
5429 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5434 drm_edid_iter_end(&edid_iter);
5437 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5441 cea_db_iter_edid_begin(drm_edid, &iter);
5442 cea_db_iter_for_each(db, &iter) {
5443 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5444 const u8 *data = cea_db_data(db);
5447 for (i = 0; i < cea_db_payload_len(db); i += 3)
5448 DRM_DEBUG_KMS("CEA audio format %d\n",
5449 (data[i] >> 3) & 0xf);
5454 cea_db_iter_end(&iter);
5461 * drm_detect_monitor_audio - check monitor audio capability
5462 * @edid: EDID block to scan
5464 * Monitor should have CEA extension block.
5465 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5466 * audio' only. If there is any audio extension block and supported
5467 * audio format, assume at least 'basic audio' support, even if 'basic
5468 * audio' is not defined in EDID.
5470 * Return: True if the monitor supports audio, false otherwise.
5472 bool drm_detect_monitor_audio(const struct edid *edid)
5474 struct drm_edid drm_edid;
5476 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5478 EXPORT_SYMBOL(drm_detect_monitor_audio);
5482 * drm_default_rgb_quant_range - default RGB quantization range
5483 * @mode: display mode
5485 * Determine the default RGB quantization range for the mode,
5486 * as specified in CEA-861.
5488 * Return: The default RGB quantization range for the mode
5490 enum hdmi_quantization_range
5491 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5493 /* All CEA modes other than VIC 1 use limited quantization range. */
5494 return drm_match_cea_mode(mode) > 1 ?
5495 HDMI_QUANTIZATION_RANGE_LIMITED :
5496 HDMI_QUANTIZATION_RANGE_FULL;
5498 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5500 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5502 struct drm_display_info *info = &connector->display_info;
5504 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5506 if (db[2] & EDID_CEA_VCDB_QS)
5507 info->rgb_quant_range_selectable = true;
5511 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5513 switch (max_frl_rate) {
5516 *max_rate_per_lane = 3;
5520 *max_rate_per_lane = 6;
5524 *max_rate_per_lane = 6;
5528 *max_rate_per_lane = 8;
5532 *max_rate_per_lane = 10;
5536 *max_rate_per_lane = 12;
5541 *max_rate_per_lane = 0;
5545 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5549 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5551 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5552 hdmi->y420_dc_modes = dc_mask;
5555 /* Sink Capability Data Structure */
5556 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5559 struct drm_display_info *display = &connector->display_info;
5560 struct drm_hdmi_info *hdmi = &display->hdmi;
5562 display->has_hdmi_infoframe = true;
5564 if (hf_scds[6] & 0x80) {
5565 hdmi->scdc.supported = true;
5566 if (hf_scds[6] & 0x40)
5567 hdmi->scdc.read_request = true;
5571 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5572 * And as per the spec, three factors confirm this:
5573 * * Availability of a HF-VSDB block in EDID (check)
5574 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5575 * * SCDC support available (let's check)
5576 * Lets check it out.
5580 /* max clock is 5000 KHz times block value */
5581 u32 max_tmds_clock = hf_scds[5] * 5000;
5582 struct drm_scdc *scdc = &hdmi->scdc;
5584 if (max_tmds_clock > 340000) {
5585 display->max_tmds_clock = max_tmds_clock;
5586 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5587 display->max_tmds_clock);
5590 if (scdc->supported) {
5591 scdc->scrambling.supported = true;
5593 /* Few sinks support scrambling for clocks < 340M */
5594 if ((hf_scds[6] & 0x8))
5595 scdc->scrambling.low_rates = true;
5601 u8 dsc_max_frl_rate;
5603 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5605 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5606 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5607 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5608 &hdmi->max_frl_rate_per_lane);
5609 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5611 if (hdmi_dsc->v_1p2) {
5612 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5613 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5615 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5616 hdmi_dsc->bpc_supported = 16;
5617 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5618 hdmi_dsc->bpc_supported = 12;
5619 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5620 hdmi_dsc->bpc_supported = 10;
5622 hdmi_dsc->bpc_supported = 0;
5624 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5625 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5626 &hdmi_dsc->max_frl_rate_per_lane);
5627 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5629 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5630 switch (dsc_max_slices) {
5632 hdmi_dsc->max_slices = 1;
5633 hdmi_dsc->clk_per_slice = 340;
5636 hdmi_dsc->max_slices = 2;
5637 hdmi_dsc->clk_per_slice = 340;
5640 hdmi_dsc->max_slices = 4;
5641 hdmi_dsc->clk_per_slice = 340;
5644 hdmi_dsc->max_slices = 8;
5645 hdmi_dsc->clk_per_slice = 340;
5648 hdmi_dsc->max_slices = 8;
5649 hdmi_dsc->clk_per_slice = 400;
5652 hdmi_dsc->max_slices = 12;
5653 hdmi_dsc->clk_per_slice = 400;
5656 hdmi_dsc->max_slices = 16;
5657 hdmi_dsc->clk_per_slice = 400;
5661 hdmi_dsc->max_slices = 0;
5662 hdmi_dsc->clk_per_slice = 0;
5667 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
5670 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5673 struct drm_display_info *info = &connector->display_info;
5674 unsigned int dc_bpc = 0;
5676 /* HDMI supports at least 8 bpc */
5679 if (cea_db_payload_len(hdmi) < 6)
5682 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5684 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
5685 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5689 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5691 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
5692 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5696 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5698 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
5699 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5704 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5709 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5710 connector->name, dc_bpc);
5713 /* YCRCB444 is optional according to spec. */
5714 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5715 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
5716 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5721 * Spec says that if any deep color mode is supported at all,
5722 * then deep color 36 bit must be supported.
5724 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5725 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5731 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5733 struct drm_display_info *info = &connector->display_info;
5734 u8 len = cea_db_payload_len(db);
5736 info->is_hdmi = true;
5739 info->dvi_dual = db[6] & 1;
5741 info->max_tmds_clock = db[7] * 5000;
5743 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5744 "max TMDS clock %d kHz\n",
5746 info->max_tmds_clock);
5748 drm_parse_hdmi_deep_color_info(connector, db);
5752 * See EDID extension for head-mounted and specialized monitors, specified at:
5753 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5755 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5758 struct drm_display_info *info = &connector->display_info;
5760 bool desktop_usage = db[5] & BIT(6);
5762 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5763 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5764 info->non_desktop = true;
5766 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5770 static void drm_parse_cea_ext(struct drm_connector *connector,
5771 const struct drm_edid *drm_edid)
5773 struct drm_display_info *info = &connector->display_info;
5774 struct drm_edid_iter edid_iter;
5775 const struct cea_db *db;
5776 struct cea_db_iter iter;
5779 drm_edid_iter_begin(drm_edid, &edid_iter);
5780 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5781 if (edid_ext[0] != CEA_EXT)
5785 info->cea_rev = edid_ext[1];
5787 if (info->cea_rev != edid_ext[1])
5788 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",
5789 info->cea_rev, edid_ext[1]);
5791 /* The existence of a CTA extension should imply RGB support */
5792 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5793 if (edid_ext[3] & EDID_CEA_YCRCB444)
5794 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5795 if (edid_ext[3] & EDID_CEA_YCRCB422)
5796 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5798 drm_edid_iter_end(&edid_iter);
5800 cea_db_iter_edid_begin(drm_edid, &iter);
5801 cea_db_iter_for_each(db, &iter) {
5802 /* FIXME: convert parsers to use struct cea_db */
5803 const u8 *data = (const u8 *)db;
5805 if (cea_db_is_hdmi_vsdb(db))
5806 drm_parse_hdmi_vsdb_video(connector, data);
5807 else if (cea_db_is_hdmi_forum_vsdb(db) ||
5808 cea_db_is_hdmi_forum_scdb(db))
5809 drm_parse_hdmi_forum_scds(connector, data);
5810 else if (cea_db_is_microsoft_vsdb(db))
5811 drm_parse_microsoft_vsdb(connector, data);
5812 else if (cea_db_is_y420cmdb(db))
5813 drm_parse_y420cmdb_bitmap(connector, data);
5814 else if (cea_db_is_vcdb(db))
5815 drm_parse_vcdb(connector, data);
5816 else if (cea_db_is_hdmi_hdr_metadata_block(db))
5817 drm_parse_hdr_metadata_block(connector, data);
5819 cea_db_iter_end(&iter);
5823 void get_monitor_range(const struct detailed_timing *timing,
5824 void *info_monitor_range)
5826 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5827 const struct detailed_non_pixel *data = &timing->data.other_data;
5828 const struct detailed_data_monitor_range *range = &data->data.range;
5830 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
5834 * Check for flag range limits only. If flag == 1 then
5835 * no additional timing information provided.
5836 * Default GTF, GTF Secondary curve and CVT are not
5839 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5842 monitor_range->min_vfreq = range->min_vfreq;
5843 monitor_range->max_vfreq = range->max_vfreq;
5846 static void drm_get_monitor_range(struct drm_connector *connector,
5847 const struct drm_edid *drm_edid)
5849 struct drm_display_info *info = &connector->display_info;
5851 if (!version_greater(drm_edid, 1, 1))
5854 drm_for_each_detailed_block(drm_edid, get_monitor_range,
5855 &info->monitor_range);
5857 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5858 info->monitor_range.min_vfreq,
5859 info->monitor_range.max_vfreq);
5862 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5863 const struct displayid_block *block)
5865 struct displayid_vesa_vendor_specific_block *vesa =
5866 (struct displayid_vesa_vendor_specific_block *)block;
5867 struct drm_display_info *info = &connector->display_info;
5869 if (block->num_bytes < 3) {
5870 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5875 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5878 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5879 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5883 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5885 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5888 info->mso_stream_count = 0;
5891 info->mso_stream_count = 2; /* 2 or 4 links */
5894 info->mso_stream_count = 4; /* 4 links */
5898 if (!info->mso_stream_count) {
5899 info->mso_pixel_overlap = 0;
5903 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5904 if (info->mso_pixel_overlap > 8) {
5905 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5906 info->mso_pixel_overlap);
5907 info->mso_pixel_overlap = 8;
5910 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5911 info->mso_stream_count, info->mso_pixel_overlap);
5914 static void drm_update_mso(struct drm_connector *connector,
5915 const struct drm_edid *drm_edid)
5917 const struct displayid_block *block;
5918 struct displayid_iter iter;
5920 displayid_iter_edid_begin(drm_edid, &iter);
5921 displayid_iter_for_each(block, &iter) {
5922 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5923 drm_parse_vesa_mso_data(connector, block);
5925 displayid_iter_end(&iter);
5928 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5929 * all of the values which would have been set from EDID
5931 static void drm_reset_display_info(struct drm_connector *connector)
5933 struct drm_display_info *info = &connector->display_info;
5936 info->height_mm = 0;
5939 info->color_formats = 0;
5941 info->max_tmds_clock = 0;
5942 info->dvi_dual = false;
5943 info->is_hdmi = false;
5944 info->has_hdmi_infoframe = false;
5945 info->rgb_quant_range_selectable = false;
5946 memset(&info->hdmi, 0, sizeof(info->hdmi));
5948 info->edid_hdmi_rgb444_dc_modes = 0;
5949 info->edid_hdmi_ycbcr444_dc_modes = 0;
5951 info->non_desktop = 0;
5952 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5954 info->mso_stream_count = 0;
5955 info->mso_pixel_overlap = 0;
5958 static u32 update_display_info(struct drm_connector *connector,
5959 const struct drm_edid *drm_edid)
5961 struct drm_display_info *info = &connector->display_info;
5962 const struct edid *edid = drm_edid->edid;
5964 u32 quirks = edid_get_quirks(drm_edid);
5966 drm_reset_display_info(connector);
5968 info->width_mm = edid->width_cm * 10;
5969 info->height_mm = edid->height_cm * 10;
5971 drm_get_monitor_range(connector, drm_edid);
5973 if (edid->revision < 3)
5976 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5979 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5980 drm_parse_cea_ext(connector, drm_edid);
5983 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5985 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5986 * tells us to assume 8 bpc color depth if the EDID doesn't have
5987 * extensions which tell otherwise.
5989 if (info->bpc == 0 && edid->revision == 3 &&
5990 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5992 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5993 connector->name, info->bpc);
5996 /* Only defined for 1.4 with digital displays */
5997 if (edid->revision < 4)
6000 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6001 case DRM_EDID_DIGITAL_DEPTH_6:
6004 case DRM_EDID_DIGITAL_DEPTH_8:
6007 case DRM_EDID_DIGITAL_DEPTH_10:
6010 case DRM_EDID_DIGITAL_DEPTH_12:
6013 case DRM_EDID_DIGITAL_DEPTH_14:
6016 case DRM_EDID_DIGITAL_DEPTH_16:
6019 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6025 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6026 connector->name, info->bpc);
6028 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6029 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6030 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6031 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6033 drm_update_mso(connector, drm_edid);
6036 if (quirks & EDID_QUIRK_NON_DESKTOP) {
6037 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
6038 info->non_desktop ? " (redundant quirk)" : "");
6039 info->non_desktop = true;
6045 static u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
6047 struct drm_edid drm_edid;
6049 return update_display_info(connector,
6050 drm_edid_legacy_init(&drm_edid, edid));
6053 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6054 struct displayid_detailed_timings_1 *timings,
6057 struct drm_display_mode *mode;
6058 unsigned pixel_clock = (timings->pixel_clock[0] |
6059 (timings->pixel_clock[1] << 8) |
6060 (timings->pixel_clock[2] << 16)) + 1;
6061 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6062 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6063 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6064 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6065 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6066 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6067 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6068 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6069 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6070 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6072 mode = drm_mode_create(dev);
6076 /* resolution is kHz for type VII, and 10 kHz for type I */
6077 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6078 mode->hdisplay = hactive;
6079 mode->hsync_start = mode->hdisplay + hsync;
6080 mode->hsync_end = mode->hsync_start + hsync_width;
6081 mode->htotal = mode->hdisplay + hblank;
6083 mode->vdisplay = vactive;
6084 mode->vsync_start = mode->vdisplay + vsync;
6085 mode->vsync_end = mode->vsync_start + vsync_width;
6086 mode->vtotal = mode->vdisplay + vblank;
6089 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6090 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6091 mode->type = DRM_MODE_TYPE_DRIVER;
6093 if (timings->flags & 0x80)
6094 mode->type |= DRM_MODE_TYPE_PREFERRED;
6095 drm_mode_set_name(mode);
6100 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6101 const struct displayid_block *block)
6103 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6106 struct drm_display_mode *newmode;
6108 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6109 /* blocks must be multiple of 20 bytes length */
6110 if (block->num_bytes % 20)
6113 num_timings = block->num_bytes / 20;
6114 for (i = 0; i < num_timings; i++) {
6115 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6117 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6121 drm_mode_probed_add(connector, newmode);
6127 static int add_displayid_detailed_modes(struct drm_connector *connector,
6128 const struct drm_edid *drm_edid)
6130 const struct displayid_block *block;
6131 struct displayid_iter iter;
6134 displayid_iter_edid_begin(drm_edid, &iter);
6135 displayid_iter_for_each(block, &iter) {
6136 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6137 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6138 num_modes += add_displayid_detailed_1_modes(connector, block);
6140 displayid_iter_end(&iter);
6145 static int drm_edid_connector_update(struct drm_connector *connector,
6146 const struct drm_edid *drm_edid)
6152 drm_reset_display_info(connector);
6153 clear_eld(connector);
6158 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
6159 * To avoid multiple parsing of same block, lets parse that map
6160 * from sink info, before parsing CEA modes.
6162 quirks = update_display_info(connector, drm_edid);
6164 /* Depends on info->cea_rev set by update_display_info() above */
6165 drm_edid_to_eld(connector, drm_edid);
6168 * EDID spec says modes should be preferred in this order:
6169 * - preferred detailed mode
6170 * - other detailed modes from base block
6171 * - detailed modes from extension blocks
6172 * - CVT 3-byte code modes
6173 * - standard timing codes
6174 * - established timing codes
6175 * - modes inferred from GTF or CVT range information
6177 * We get this pretty much right.
6179 * XXX order for additional mode types in extension blocks?
6181 num_modes += add_detailed_modes(connector, drm_edid, quirks);
6182 num_modes += add_cvt_modes(connector, drm_edid);
6183 num_modes += add_standard_modes(connector, drm_edid);
6184 num_modes += add_established_modes(connector, drm_edid);
6185 num_modes += add_cea_modes(connector, drm_edid);
6186 num_modes += add_alternate_cea_modes(connector, drm_edid);
6187 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6188 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
6189 num_modes += add_inferred_modes(connector, drm_edid);
6191 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6192 edid_fixup_preferred(connector, quirks);
6194 if (quirks & EDID_QUIRK_FORCE_6BPC)
6195 connector->display_info.bpc = 6;
6197 if (quirks & EDID_QUIRK_FORCE_8BPC)
6198 connector->display_info.bpc = 8;
6200 if (quirks & EDID_QUIRK_FORCE_10BPC)
6201 connector->display_info.bpc = 10;
6203 if (quirks & EDID_QUIRK_FORCE_12BPC)
6204 connector->display_info.bpc = 12;
6209 static void drm_update_tile_info(struct drm_connector *connector,
6210 const struct edid *edid);
6213 * drm_connector_update_edid_property - update the edid property of a connector
6214 * @connector: drm connector
6215 * @edid: new value of the edid property
6217 * This function creates a new blob modeset object and assigns its id to the
6218 * connector's edid property.
6219 * Since we also parse tile information from EDID's displayID block, we also
6220 * set the connector's tile property here. See drm_connector_set_tile_property()
6224 * Zero on success, negative errno on failure.
6226 int drm_connector_update_edid_property(struct drm_connector *connector,
6227 const struct edid *edid)
6229 struct drm_device *dev = connector->dev;
6232 const struct edid *old_edid;
6234 /* ignore requests to set edid when overridden */
6235 if (connector->override_edid)
6239 size = EDID_LENGTH * (1 + edid->extensions);
6242 * Set the display info, using edid if available, otherwise resetting
6243 * the values to defaults. This duplicates the work done in
6244 * drm_add_edid_modes, but that function is not consistently called
6245 * before this one in all drivers and the computation is cheap enough
6246 * that it seems better to duplicate it rather than attempt to ensure
6247 * some arbitrary ordering of calls.
6250 drm_add_display_info(connector, edid);
6252 drm_reset_display_info(connector);
6254 drm_update_tile_info(connector, edid);
6256 if (connector->edid_blob_ptr) {
6257 old_edid = (const struct edid *)connector->edid_blob_ptr->data;
6259 if (!drm_edid_are_equal(edid, old_edid)) {
6260 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n",
6261 connector->base.id, connector->name);
6263 connector->epoch_counter += 1;
6264 DRM_DEBUG_KMS("Updating change counter to %llu\n",
6265 connector->epoch_counter);
6270 drm_object_property_set_value(&connector->base,
6271 dev->mode_config.non_desktop_property,
6272 connector->display_info.non_desktop);
6274 ret = drm_property_replace_global_blob(dev,
6275 &connector->edid_blob_ptr,
6279 dev->mode_config.edid_property);
6282 return drm_connector_set_tile_property(connector);
6284 EXPORT_SYMBOL(drm_connector_update_edid_property);
6287 * drm_add_edid_modes - add modes from EDID data, if available
6288 * @connector: connector we're probing
6291 * Add the specified modes to the connector's mode list. Also fills out the
6292 * &drm_display_info structure and ELD in @connector with any information which
6293 * can be derived from the edid.
6295 * Return: The number of modes added or 0 if we couldn't find any.
6297 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6299 struct drm_edid drm_edid;
6301 if (edid && !drm_edid_is_valid(edid)) {
6302 drm_warn(connector->dev, "%s: EDID invalid.\n",
6307 return drm_edid_connector_update(connector,
6308 drm_edid_legacy_init(&drm_edid, edid));
6310 EXPORT_SYMBOL(drm_add_edid_modes);
6313 * drm_add_modes_noedid - add modes for the connectors without EDID
6314 * @connector: connector we're probing
6315 * @hdisplay: the horizontal display limit
6316 * @vdisplay: the vertical display limit
6318 * Add the specified modes to the connector's mode list. Only when the
6319 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6321 * Return: The number of modes added or 0 if we couldn't find any.
6323 int drm_add_modes_noedid(struct drm_connector *connector,
6324 int hdisplay, int vdisplay)
6326 int i, count, num_modes = 0;
6327 struct drm_display_mode *mode;
6328 struct drm_device *dev = connector->dev;
6330 count = ARRAY_SIZE(drm_dmt_modes);
6336 for (i = 0; i < count; i++) {
6337 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6339 if (hdisplay && vdisplay) {
6341 * Only when two are valid, they will be used to check
6342 * whether the mode should be added to the mode list of
6345 if (ptr->hdisplay > hdisplay ||
6346 ptr->vdisplay > vdisplay)
6349 if (drm_mode_vrefresh(ptr) > 61)
6351 mode = drm_mode_duplicate(dev, ptr);
6353 drm_mode_probed_add(connector, mode);
6359 EXPORT_SYMBOL(drm_add_modes_noedid);
6362 * drm_set_preferred_mode - Sets the preferred mode of a connector
6363 * @connector: connector whose mode list should be processed
6364 * @hpref: horizontal resolution of preferred mode
6365 * @vpref: vertical resolution of preferred mode
6367 * Marks a mode as preferred if it matches the resolution specified by @hpref
6370 void drm_set_preferred_mode(struct drm_connector *connector,
6371 int hpref, int vpref)
6373 struct drm_display_mode *mode;
6375 list_for_each_entry(mode, &connector->probed_modes, head) {
6376 if (mode->hdisplay == hpref &&
6377 mode->vdisplay == vpref)
6378 mode->type |= DRM_MODE_TYPE_PREFERRED;
6381 EXPORT_SYMBOL(drm_set_preferred_mode);
6383 static bool is_hdmi2_sink(const struct drm_connector *connector)
6386 * FIXME: sil-sii8620 doesn't have a connector around when
6387 * we need one, so we have to be prepared for a NULL connector.
6392 return connector->display_info.hdmi.scdc.supported ||
6393 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6396 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6397 const struct drm_display_mode *mode)
6399 bool has_hdmi_infoframe = connector ?
6400 connector->display_info.has_hdmi_infoframe : false;
6402 if (!has_hdmi_infoframe)
6405 /* No HDMI VIC when signalling 3D video format */
6406 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6409 return drm_match_hdmi_mode(mode);
6412 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
6413 const struct drm_display_mode *mode)
6418 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6419 * we should send its VIC in vendor infoframes, else send the
6420 * VIC in AVI infoframes. Lets check if this mode is present in
6421 * HDMI 1.4b 4K modes
6423 if (drm_mode_hdmi_vic(connector, mode))
6426 vic = drm_match_cea_mode(mode);
6429 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6430 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6431 * have to make sure we dont break HDMI 1.4 sinks.
6433 if (!is_hdmi2_sink(connector) && vic > 64)
6440 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6441 * data from a DRM display mode
6442 * @frame: HDMI AVI infoframe
6443 * @connector: the connector
6444 * @mode: DRM display mode
6446 * Return: 0 on success or a negative error code on failure.
6449 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
6450 const struct drm_connector *connector,
6451 const struct drm_display_mode *mode)
6453 enum hdmi_picture_aspect picture_aspect;
6456 if (!frame || !mode)
6459 hdmi_avi_infoframe_init(frame);
6461 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6462 frame->pixel_repeat = 1;
6464 vic = drm_mode_cea_vic(connector, mode);
6465 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
6467 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6470 * As some drivers don't support atomic, we can't use connector state.
6471 * So just initialize the frame with default values, just the same way
6472 * as it's done with other properties here.
6474 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6478 * Populate picture aspect ratio from either
6479 * user input (if specified) or from the CEA/HDMI mode lists.
6481 picture_aspect = mode->picture_aspect_ratio;
6482 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6484 picture_aspect = drm_get_cea_aspect_ratio(vic);
6486 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6490 * The infoframe can't convey anything but none, 4:3
6491 * and 16:9, so if the user has asked for anything else
6492 * we can only satisfy it by specifying the right VIC.
6494 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
6496 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6498 } else if (hdmi_vic) {
6499 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6505 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6508 frame->video_code = vic;
6509 frame->picture_aspect = picture_aspect;
6510 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
6511 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
6515 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
6518 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6519 * quantization range information
6520 * @frame: HDMI AVI infoframe
6521 * @connector: the connector
6522 * @mode: DRM display mode
6523 * @rgb_quant_range: RGB quantization range (Q)
6526 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6527 const struct drm_connector *connector,
6528 const struct drm_display_mode *mode,
6529 enum hdmi_quantization_range rgb_quant_range)
6531 const struct drm_display_info *info = &connector->display_info;
6535 * "A Source shall not send a non-zero Q value that does not correspond
6536 * to the default RGB Quantization Range for the transmitted Picture
6537 * unless the Sink indicates support for the Q bit in a Video
6538 * Capabilities Data Block."
6540 * HDMI 2.0 recommends sending non-zero Q when it does match the
6541 * default RGB quantization range for the mode, even when QS=0.
6543 if (info->rgb_quant_range_selectable ||
6544 rgb_quant_range == drm_default_rgb_quant_range(mode))
6545 frame->quantization_range = rgb_quant_range;
6547 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
6551 * "When transmitting any RGB colorimetry, the Source should set the
6552 * YQ-field to match the RGB Quantization Range being transmitted
6553 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6554 * set YQ=1) and the Sink shall ignore the YQ-field."
6556 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6557 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6558 * good way to tell which version of CEA-861 the sink supports, so
6559 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6562 if (!is_hdmi2_sink(connector) ||
6563 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
6564 frame->ycc_quantization_range =
6565 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6567 frame->ycc_quantization_range =
6568 HDMI_YCC_QUANTIZATION_RANGE_FULL;
6570 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6572 static enum hdmi_3d_structure
6573 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6575 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6578 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6579 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6580 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6581 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6582 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6583 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6584 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6585 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6586 case DRM_MODE_FLAG_3D_L_DEPTH:
6587 return HDMI_3D_STRUCTURE_L_DEPTH;
6588 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6589 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6590 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6591 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6592 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6593 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6595 return HDMI_3D_STRUCTURE_INVALID;
6600 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6601 * data from a DRM display mode
6602 * @frame: HDMI vendor infoframe
6603 * @connector: the connector
6604 * @mode: DRM display mode
6606 * Note that there's is a need to send HDMI vendor infoframes only when using a
6607 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6608 * function will return -EINVAL, error that can be safely ignored.
6610 * Return: 0 on success or a negative error code on failure.
6613 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6614 const struct drm_connector *connector,
6615 const struct drm_display_mode *mode)
6618 * FIXME: sil-sii8620 doesn't have a connector around when
6619 * we need one, so we have to be prepared for a NULL connector.
6621 bool has_hdmi_infoframe = connector ?
6622 connector->display_info.has_hdmi_infoframe : false;
6625 if (!frame || !mode)
6628 if (!has_hdmi_infoframe)
6631 err = hdmi_vendor_infoframe_init(frame);
6636 * Even if it's not absolutely necessary to send the infoframe
6637 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6638 * know that the sink can handle it. This is based on a
6639 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6640 * have trouble realizing that they should switch from 3D to 2D
6641 * mode if the source simply stops sending the infoframe when
6642 * it wants to switch from 3D to 2D.
6644 frame->vic = drm_mode_hdmi_vic(connector, mode);
6645 frame->s3d_struct = s3d_structure_from_display_mode(mode);
6649 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6651 static void drm_parse_tiled_block(struct drm_connector *connector,
6652 const struct displayid_block *block)
6654 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6656 u8 tile_v_loc, tile_h_loc;
6657 u8 num_v_tile, num_h_tile;
6658 struct drm_tile_group *tg;
6660 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6661 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6663 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6664 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6665 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6666 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6668 connector->has_tile = true;
6669 if (tile->tile_cap & 0x80)
6670 connector->tile_is_single_monitor = true;
6672 connector->num_h_tile = num_h_tile + 1;
6673 connector->num_v_tile = num_v_tile + 1;
6674 connector->tile_h_loc = tile_h_loc;
6675 connector->tile_v_loc = tile_v_loc;
6676 connector->tile_h_size = w + 1;
6677 connector->tile_v_size = h + 1;
6679 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6680 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6681 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6682 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6683 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6685 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6687 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6691 if (connector->tile_group != tg) {
6692 /* if we haven't got a pointer,
6693 take the reference, drop ref to old tile group */
6694 if (connector->tile_group)
6695 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6696 connector->tile_group = tg;
6698 /* if same tile group, then release the ref we just took. */
6699 drm_mode_put_tile_group(connector->dev, tg);
6703 static void _drm_update_tile_info(struct drm_connector *connector,
6704 const struct drm_edid *drm_edid)
6706 const struct displayid_block *block;
6707 struct displayid_iter iter;
6709 connector->has_tile = false;
6711 displayid_iter_edid_begin(drm_edid, &iter);
6712 displayid_iter_for_each(block, &iter) {
6713 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6714 drm_parse_tiled_block(connector, block);
6716 displayid_iter_end(&iter);
6718 if (!connector->has_tile && connector->tile_group) {
6719 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6720 connector->tile_group = NULL;
6724 static void drm_update_tile_info(struct drm_connector *connector,
6725 const struct edid *edid)
6727 struct drm_edid drm_edid;
6729 _drm_update_tile_info(connector, drm_edid_legacy_init(&drm_edid, edid));
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