drivers/gpu/drm/bridge/tc358767.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * tc358767 eDP bridge driver
   4  *
   5  * Copyright (C) 2016 CogentEmbedded Inc
   6  * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
   7  *
   8  * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
   9  *
  10  * Copyright (C) 2016 Zodiac Inflight Innovations
  11  *
  12  * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
  13  *
  14  * Copyright (C) 2012 Texas Instruments
  15  * Author: Rob Clark <robdclark@gmail.com>
  16  */
  17
  18 #include <linux/bitfield.h>
  19 #include <linux/clk.h>
  20 #include <linux/device.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/i2c.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/regmap.h>
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_bridge.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_edid.h>
  32 #include <drm/drm_of.h>
  33 #include <drm/drm_panel.h>
  34 #include <drm/drm_probe_helper.h>
  35
  36 /* Registers */
  37
  38 /* Display Parallel Interface */
  39 #define DPIPXLFMT               0x0440
  40 #define VS_POL_ACTIVE_LOW               (1 << 10)
  41 #define HS_POL_ACTIVE_LOW               (1 << 9)
  42 #define DE_POL_ACTIVE_HIGH              (0 << 8)
  43 #define SUB_CFG_TYPE_CONFIG1            (0 << 2) /* LSB aligned */
  44 #define SUB_CFG_TYPE_CONFIG2            (1 << 2) /* Loosely Packed */
  45 #define SUB_CFG_TYPE_CONFIG3            (2 << 2) /* LSB aligned 8-bit */
  46 #define DPI_BPP_RGB888                  (0 << 0)
  47 #define DPI_BPP_RGB666                  (1 << 0)
  48 #define DPI_BPP_RGB565                  (2 << 0)
  49
  50 /* Video Path */
  51 #define VPCTRL0                 0x0450
  52 #define VSDELAY                 GENMASK(31, 20)
  53 #define OPXLFMT_RGB666                  (0 << 8)
  54 #define OPXLFMT_RGB888                  (1 << 8)
  55 #define FRMSYNC_DISABLED                (0 << 4) /* Video Timing Gen Disabled */
  56 #define FRMSYNC_ENABLED                 (1 << 4) /* Video Timing Gen Enabled */
  57 #define MSF_DISABLED                    (0 << 0) /* Magic Square FRC disabled */
  58 #define MSF_ENABLED                     (1 << 0) /* Magic Square FRC enabled */
  59 #define HTIM01                  0x0454
  60 #define HPW                     GENMASK(8, 0)
  61 #define HBPR                    GENMASK(24, 16)
  62 #define HTIM02                  0x0458
  63 #define HDISPR                  GENMASK(10, 0)
  64 #define HFPR                    GENMASK(24, 16)
  65 #define VTIM01                  0x045c
  66 #define VSPR                    GENMASK(7, 0)
  67 #define VBPR                    GENMASK(23, 16)
  68 #define VTIM02                  0x0460
  69 #define VFPR                    GENMASK(23, 16)
  70 #define VDISPR                  GENMASK(10, 0)
  71 #define VFUEN0                  0x0464
  72 #define VFUEN                           BIT(0)   /* Video Frame Timing Upload */
  73
  74 /* System */
  75 #define TC_IDREG                0x0500
  76 #define SYSSTAT                 0x0508
  77 #define SYSCTRL                 0x0510
  78 #define DP0_AUDSRC_NO_INPUT             (0 << 3)
  79 #define DP0_AUDSRC_I2S_RX               (1 << 3)
  80 #define DP0_VIDSRC_NO_INPUT             (0 << 0)
  81 #define DP0_VIDSRC_DSI_RX               (1 << 0)
  82 #define DP0_VIDSRC_DPI_RX               (2 << 0)
  83 #define DP0_VIDSRC_COLOR_BAR            (3 << 0)
  84 #define SYSRSTENB               0x050c
  85 #define ENBI2C                          (1 << 0)
  86 #define ENBLCD0                         (1 << 2)
  87 #define ENBBM                           (1 << 3)
  88 #define ENBDSIRX                        (1 << 4)
  89 #define ENBREG                          (1 << 5)
  90 #define ENBHDCP                         (1 << 8)
  91 #define GPIOM                   0x0540
  92 #define GPIOC                   0x0544
  93 #define GPIOO                   0x0548
  94 #define GPIOI                   0x054c
  95 #define INTCTL_G                0x0560
  96 #define INTSTS_G                0x0564
  97
  98 #define INT_SYSERR              BIT(16)
  99 #define INT_GPIO_H(x)           (1 << (x == 0 ? 2 : 10))
 100 #define INT_GPIO_LC(x)          (1 << (x == 0 ? 3 : 11))
 101
 102 #define INT_GP0_LCNT            0x0584
 103 #define INT_GP1_LCNT            0x0588
 104
 105 /* Control */
 106 #define DP0CTL                  0x0600
 107 #define VID_MN_GEN                      BIT(6)   /* Auto-generate M/N values */
 108 #define EF_EN                           BIT(5)   /* Enable Enhanced Framing */
 109 #define VID_EN                          BIT(1)   /* Video transmission enable */
 110 #define DP_EN                           BIT(0)   /* Enable DPTX function */
 111
 112 /* Clocks */
 113 #define DP0_VIDMNGEN0           0x0610
 114 #define DP0_VIDMNGEN1           0x0614
 115 #define DP0_VMNGENSTATUS        0x0618
 116
 117 /* Main Channel */
 118 #define DP0_SECSAMPLE           0x0640
 119 #define DP0_VIDSYNCDELAY        0x0644
 120 #define VID_SYNC_DLY            GENMASK(15, 0)
 121 #define THRESH_DLY              GENMASK(31, 16)
 122
 123 #define DP0_TOTALVAL            0x0648
 124 #define H_TOTAL                 GENMASK(15, 0)
 125 #define V_TOTAL                 GENMASK(31, 16)
 126 #define DP0_STARTVAL            0x064c
 127 #define H_START                 GENMASK(15, 0)
 128 #define V_START                 GENMASK(31, 16)
 129 #define DP0_ACTIVEVAL           0x0650
 130 #define H_ACT                   GENMASK(15, 0)
 131 #define V_ACT                   GENMASK(31, 16)
 132
 133 #define DP0_SYNCVAL             0x0654
 134 #define VS_WIDTH                GENMASK(30, 16)
 135 #define HS_WIDTH                GENMASK(14, 0)
 136 #define SYNCVAL_HS_POL_ACTIVE_LOW       (1 << 15)
 137 #define SYNCVAL_VS_POL_ACTIVE_LOW       (1 << 31)
 138 #define DP0_MISC                0x0658
 139 #define TU_SIZE_RECOMMENDED             (63) /* LSCLK cycles per TU */
 140 #define MAX_TU_SYMBOL           GENMASK(28, 23)
 141 #define TU_SIZE                 GENMASK(21, 16)
 142 #define BPC_6                           (0 << 5)
 143 #define BPC_8                           (1 << 5)
 144
 145 /* AUX channel */
 146 #define DP0_AUXCFG0             0x0660
 147 #define DP0_AUXCFG0_BSIZE       GENMASK(11, 8)
 148 #define DP0_AUXCFG0_ADDR_ONLY   BIT(4)
 149 #define DP0_AUXCFG1             0x0664
 150 #define AUX_RX_FILTER_EN                BIT(16)
 151
 152 #define DP0_AUXADDR             0x0668
 153 #define DP0_AUXWDATA(i)         (0x066c + (i) * 4)
 154 #define DP0_AUXRDATA(i)         (0x067c + (i) * 4)
 155 #define DP0_AUXSTATUS           0x068c
 156 #define AUX_BYTES               GENMASK(15, 8)
 157 #define AUX_STATUS              GENMASK(7, 4)
 158 #define AUX_TIMEOUT             BIT(1)
 159 #define AUX_BUSY                BIT(0)
 160 #define DP0_AUXI2CADR           0x0698
 161
 162 /* Link Training */
 163 #define DP0_SRCCTRL             0x06a0
 164 #define DP0_SRCCTRL_SCRMBLDIS           BIT(13)
 165 #define DP0_SRCCTRL_EN810B              BIT(12)
 166 #define DP0_SRCCTRL_NOTP                (0 << 8)
 167 #define DP0_SRCCTRL_TP1                 (1 << 8)
 168 #define DP0_SRCCTRL_TP2                 (2 << 8)
 169 #define DP0_SRCCTRL_LANESKEW            BIT(7)
 170 #define DP0_SRCCTRL_SSCG                BIT(3)
 171 #define DP0_SRCCTRL_LANES_1             (0 << 2)
 172 #define DP0_SRCCTRL_LANES_2             (1 << 2)
 173 #define DP0_SRCCTRL_BW27                (1 << 1)
 174 #define DP0_SRCCTRL_BW162               (0 << 1)
 175 #define DP0_SRCCTRL_AUTOCORRECT         BIT(0)
 176 #define DP0_LTSTAT              0x06d0
 177 #define LT_LOOPDONE                     BIT(13)
 178 #define LT_STATUS_MASK                  (0x1f << 8)
 179 #define LT_CHANNEL1_EQ_BITS             (DP_CHANNEL_EQ_BITS << 4)
 180 #define LT_INTERLANE_ALIGN_DONE         BIT(3)
 181 #define LT_CHANNEL0_EQ_BITS             (DP_CHANNEL_EQ_BITS)
 182 #define DP0_SNKLTCHGREQ         0x06d4
 183 #define DP0_LTLOOPCTRL          0x06d8
 184 #define DP0_SNKLTCTRL           0x06e4
 185
 186 #define DP1_SRCCTRL             0x07a0
 187
 188 /* PHY */
 189 #define DP_PHY_CTRL             0x0800
 190 #define DP_PHY_RST                      BIT(28)  /* DP PHY Global Soft Reset */
 191 #define BGREN                           BIT(25)  /* AUX PHY BGR Enable */
 192 #define PWR_SW_EN                       BIT(24)  /* PHY Power Switch Enable */
 193 #define PHY_M1_RST                      BIT(12)  /* Reset PHY1 Main Channel */
 194 #define PHY_RDY                         BIT(16)  /* PHY Main Channels Ready */
 195 #define PHY_M0_RST                      BIT(8)   /* Reset PHY0 Main Channel */
 196 #define PHY_2LANE                       BIT(2)   /* PHY Enable 2 lanes */
 197 #define PHY_A0_EN                       BIT(1)   /* PHY Aux Channel0 Enable */
 198 #define PHY_M0_EN                       BIT(0)   /* PHY Main Channel0 Enable */
 199
 200 /* PLL */
 201 #define DP0_PLLCTRL             0x0900
 202 #define DP1_PLLCTRL             0x0904  /* not defined in DS */
 203 #define PXL_PLLCTRL             0x0908
 204 #define PLLUPDATE                       BIT(2)
 205 #define PLLBYP                          BIT(1)
 206 #define PLLEN                           BIT(0)
 207 #define PXL_PLLPARAM            0x0914
 208 #define IN_SEL_REFCLK                   (0 << 14)
 209 #define SYS_PLLPARAM            0x0918
 210 #define REF_FREQ_38M4                   (0 << 8) /* 38.4 MHz */
 211 #define REF_FREQ_19M2                   (1 << 8) /* 19.2 MHz */
 212 #define REF_FREQ_26M                    (2 << 8) /* 26 MHz */
 213 #define REF_FREQ_13M                    (3 << 8) /* 13 MHz */
 214 #define SYSCLK_SEL_LSCLK                (0 << 4)
 215 #define LSCLK_DIV_1                     (0 << 0)
 216 #define LSCLK_DIV_2                     (1 << 0)
 217
 218 /* Test & Debug */
 219 #define TSTCTL                  0x0a00
 220 #define COLOR_R                 GENMASK(31, 24)
 221 #define COLOR_G                 GENMASK(23, 16)
 222 #define COLOR_B                 GENMASK(15, 8)
 223 #define ENI2CFILTER             BIT(4)
 224 #define COLOR_BAR_MODE          GENMASK(1, 0)
 225 #define COLOR_BAR_MODE_BARS     2
 226 #define PLL_DBG                 0x0a04
 227
 228 static bool tc_test_pattern;
 229 module_param_named(test, tc_test_pattern, bool, 0644);
 230
 231 struct tc_edp_link {
 232         u8                      dpcd[DP_RECEIVER_CAP_SIZE];
 233         unsigned int            rate;
 234         u8                      num_lanes;
 235         u8                      assr;
 236         bool                    scrambler_dis;
 237         bool                    spread;
 238 };
 239
 240 struct tc_data {
 241         struct device           *dev;
 242         struct regmap           *regmap;
 243         struct drm_dp_aux       aux;
 244
 245         struct drm_bridge       bridge;
 246         struct drm_connector    connector;
 247         struct drm_panel        *panel;
 248
 249         /* link settings */
 250         struct tc_edp_link      link;
 251
 252         /* display edid */
 253         struct edid             *edid;
 254         /* current mode */
 255         struct drm_display_mode mode;
 256
 257         u32                     rev;
 258         u8                      assr;
 259
 260         struct gpio_desc        *sd_gpio;
 261         struct gpio_desc        *reset_gpio;
 262         struct clk              *refclk;
 263
 264         /* do we have IRQ */
 265         bool                    have_irq;
 266
 267         /* HPD pin number (0 or 1) or -ENODEV */
 268         int                     hpd_pin;
 269 };
 270
 271 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
 272 {
 273         return container_of(a, struct tc_data, aux);
 274 }
 275
 276 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
 277 {
 278         return container_of(b, struct tc_data, bridge);
 279 }
 280
 281 static inline struct tc_data *connector_to_tc(struct drm_connector *c)
 282 {
 283         return container_of(c, struct tc_data, connector);
 284 }
 285
 286 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
 287                                   unsigned int cond_mask,
 288                                   unsigned int cond_value,
 289                                   unsigned long sleep_us, u64 timeout_us)
 290 {
 291         unsigned int val;
 292
 293         return regmap_read_poll_timeout(tc->regmap, addr, val,
 294                                         (val & cond_mask) == cond_value,
 295                                         sleep_us, timeout_us);
 296 }
 297
 298 static int tc_aux_wait_busy(struct tc_data *tc)
 299 {
 300         return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 1000, 100000);
 301 }
 302
 303 static int tc_aux_write_data(struct tc_data *tc, const void *data,
 304                              size_t size)
 305 {
 306         u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
 307         int ret, count = ALIGN(size, sizeof(u32));
 308
 309         memcpy(auxwdata, data, size);
 310
 311         ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
 312         if (ret)
 313                 return ret;
 314
 315         return size;
 316 }
 317
 318 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
 319 {
 320         u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
 321         int ret, count = ALIGN(size, sizeof(u32));
 322
 323         ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
 324         if (ret)
 325                 return ret;
 326
 327         memcpy(data, auxrdata, size);
 328
 329         return size;
 330 }
 331
 332 static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
 333 {
 334         u32 auxcfg0 = msg->request;
 335
 336         if (size)
 337                 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
 338         else
 339                 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
 340
 341         return auxcfg0;
 342 }
 343
 344 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
 345                                struct drm_dp_aux_msg *msg)
 346 {
 347         struct tc_data *tc = aux_to_tc(aux);
 348         size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
 349         u8 request = msg->request & ~DP_AUX_I2C_MOT;
 350         u32 auxstatus;
 351         int ret;
 352
 353         ret = tc_aux_wait_busy(tc);
 354         if (ret)
 355                 return ret;
 356
 357         switch (request) {
 358         case DP_AUX_NATIVE_READ:
 359         case DP_AUX_I2C_READ:
 360                 break;
 361         case DP_AUX_NATIVE_WRITE:
 362         case DP_AUX_I2C_WRITE:
 363                 if (size) {
 364                         ret = tc_aux_write_data(tc, msg->buffer, size);
 365                         if (ret < 0)
 366                                 return ret;
 367                 }
 368                 break;
 369         default:
 370                 return -EINVAL;
 371         }
 372
 373         /* Store address */
 374         ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
 375         if (ret)
 376                 return ret;
 377         /* Start transfer */
 378         ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
 379         if (ret)
 380                 return ret;
 381
 382         ret = tc_aux_wait_busy(tc);
 383         if (ret)
 384                 return ret;
 385
 386         ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
 387         if (ret)
 388                 return ret;
 389
 390         if (auxstatus & AUX_TIMEOUT)
 391                 return -ETIMEDOUT;
 392         /*
 393          * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
 394          * reports 1 byte transferred in its status. To deal we that
 395          * we ignore aux_bytes field if we know that this was an
 396          * address-only transfer
 397          */
 398         if (size)
 399                 size = FIELD_GET(AUX_BYTES, auxstatus);
 400         msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
 401
 402         switch (request) {
 403         case DP_AUX_NATIVE_READ:
 404         case DP_AUX_I2C_READ:
 405                 if (size)
 406                         return tc_aux_read_data(tc, msg->buffer, size);
 407                 break;
 408         }
 409
 410         return size;
 411 }
 412
 413 static const char * const training_pattern1_errors[] = {
 414         "No errors",
 415         "Aux write error",
 416         "Aux read error",
 417         "Max voltage reached error",
 418         "Loop counter expired error",
 419         "res", "res", "res"
 420 };
 421
 422 static const char * const training_pattern2_errors[] = {
 423         "No errors",
 424         "Aux write error",
 425         "Aux read error",
 426         "Clock recovery failed error",
 427         "Loop counter expired error",
 428         "res", "res", "res"
 429 };
 430
 431 static u32 tc_srcctrl(struct tc_data *tc)
 432 {
 433         /*
 434          * No training pattern, skew lane 1 data by two LSCLK cycles with
 435          * respect to lane 0 data, AutoCorrect Mode = 0
 436          */
 437         u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
 438
 439         if (tc->link.scrambler_dis)
 440                 reg |= DP0_SRCCTRL_SCRMBLDIS;   /* Scrambler Disabled */
 441         if (tc->link.spread)
 442                 reg |= DP0_SRCCTRL_SSCG;        /* Spread Spectrum Enable */
 443         if (tc->link.num_lanes == 2)
 444                 reg |= DP0_SRCCTRL_LANES_2;     /* Two Main Channel Lanes */
 445         if (tc->link.rate != 162000)
 446                 reg |= DP0_SRCCTRL_BW27;        /* 2.7 Gbps link */
 447         return reg;
 448 }
 449
 450 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
 451 {
 452         int ret;
 453
 454         ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
 455         if (ret)
 456                 return ret;
 457
 458         /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
 459         usleep_range(3000, 6000);
 460
 461         return 0;
 462 }
 463
 464 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
 465 {
 466         int ret;
 467         int i_pre, best_pre = 1;
 468         int i_post, best_post = 1;
 469         int div, best_div = 1;
 470         int mul, best_mul = 1;
 471         int delta, best_delta;
 472         int ext_div[] = {1, 2, 3, 5, 7};
 473         int best_pixelclock = 0;
 474         int vco_hi = 0;
 475         u32 pxl_pllparam;
 476
 477         dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
 478                 refclk);
 479         best_delta = pixelclock;
 480         /* Loop over all possible ext_divs, skipping invalid configurations */
 481         for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
 482                 /*
 483                  * refclk / ext_pre_div should be in the 1 to 200 MHz range.
 484                  * We don't allow any refclk > 200 MHz, only check lower bounds.
 485                  */
 486                 if (refclk / ext_div[i_pre] < 1000000)
 487                         continue;
 488                 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
 489                         for (div = 1; div <= 16; div++) {
 490                                 u32 clk;
 491                                 u64 tmp;
 492
 493                                 tmp = pixelclock * ext_div[i_pre] *
 494                                       ext_div[i_post] * div;
 495                                 do_div(tmp, refclk);
 496                                 mul = tmp;
 497
 498                                 /* Check limits */
 499                                 if ((mul < 1) || (mul > 128))
 500                                         continue;
 501
 502                                 clk = (refclk / ext_div[i_pre] / div) * mul;
 503                                 /*
 504                                  * refclk * mul / (ext_pre_div * pre_div)
 505                                  * should be in the 150 to 650 MHz range
 506                                  */
 507                                 if ((clk > 650000000) || (clk < 150000000))
 508                                         continue;
 509
 510                                 clk = clk / ext_div[i_post];
 511                                 delta = clk - pixelclock;
 512
 513                                 if (abs(delta) < abs(best_delta)) {
 514                                         best_pre = i_pre;
 515                                         best_post = i_post;
 516                                         best_div = div;
 517                                         best_mul = mul;
 518                                         best_delta = delta;
 519                                         best_pixelclock = clk;
 520                                 }
 521                         }
 522                 }
 523         }
 524         if (best_pixelclock == 0) {
 525                 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
 526                         pixelclock);
 527                 return -EINVAL;
 528         }
 529
 530         dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
 531                 best_delta);
 532         dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
 533                 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
 534
 535         /* if VCO >= 300 MHz */
 536         if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
 537                 vco_hi = 1;
 538         /* see DS */
 539         if (best_div == 16)
 540                 best_div = 0;
 541         if (best_mul == 128)
 542                 best_mul = 0;
 543
 544         /* Power up PLL and switch to bypass */
 545         ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
 546         if (ret)
 547                 return ret;
 548
 549         pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
 550         pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
 551         pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
 552         pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
 553         pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
 554         pxl_pllparam |= best_mul; /* Multiplier for PLL */
 555
 556         ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
 557         if (ret)
 558                 return ret;
 559
 560         /* Force PLL parameter update and disable bypass */
 561         return tc_pllupdate(tc, PXL_PLLCTRL);
 562 }
 563
 564 static int tc_pxl_pll_dis(struct tc_data *tc)
 565 {
 566         /* Enable PLL bypass, power down PLL */
 567         return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
 568 }
 569
 570 static int tc_stream_clock_calc(struct tc_data *tc)
 571 {
 572         /*
 573          * If the Stream clock and Link Symbol clock are
 574          * asynchronous with each other, the value of M changes over
 575          * time. This way of generating link clock and stream
 576          * clock is called Asynchronous Clock mode. The value M
 577          * must change while the value N stays constant. The
 578          * value of N in this Asynchronous Clock mode must be set
 579          * to 2^15 or 32,768.
 580          *
 581          * LSCLK = 1/10 of high speed link clock
 582          *
 583          * f_STRMCLK = M/N * f_LSCLK
 584          * M/N = f_STRMCLK / f_LSCLK
 585          *
 586          */
 587         return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
 588 }
 589
 590 static int tc_set_syspllparam(struct tc_data *tc)
 591 {
 592         unsigned long rate;
 593         u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
 594
 595         rate = clk_get_rate(tc->refclk);
 596         switch (rate) {
 597         case 38400000:
 598                 pllparam |= REF_FREQ_38M4;
 599                 break;
 600         case 26000000:
 601                 pllparam |= REF_FREQ_26M;
 602                 break;
 603         case 19200000:
 604                 pllparam |= REF_FREQ_19M2;
 605                 break;
 606         case 13000000:
 607                 pllparam |= REF_FREQ_13M;
 608                 break;
 609         default:
 610                 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
 611                 return -EINVAL;
 612         }
 613
 614         return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
 615 }
 616
 617 static int tc_aux_link_setup(struct tc_data *tc)
 618 {
 619         int ret;
 620         u32 dp0_auxcfg1;
 621
 622         /* Setup DP-PHY / PLL */
 623         ret = tc_set_syspllparam(tc);
 624         if (ret)
 625                 goto err;
 626
 627         ret = regmap_write(tc->regmap, DP_PHY_CTRL,
 628                            BGREN | PWR_SW_EN | PHY_A0_EN);
 629         if (ret)
 630                 goto err;
 631         /*
 632          * Initially PLLs are in bypass. Force PLL parameter update,
 633          * disable PLL bypass, enable PLL
 634          */
 635         ret = tc_pllupdate(tc, DP0_PLLCTRL);
 636         if (ret)
 637                 goto err;
 638
 639         ret = tc_pllupdate(tc, DP1_PLLCTRL);
 640         if (ret)
 641                 goto err;
 642
 643         ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
 644         if (ret == -ETIMEDOUT) {
 645                 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
 646                 return ret;
 647         } else if (ret) {
 648                 goto err;
 649         }
 650
 651         /* Setup AUX link */
 652         dp0_auxcfg1  = AUX_RX_FILTER_EN;
 653         dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
 654         dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
 655
 656         ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
 657         if (ret)
 658                 goto err;
 659
 660         return 0;
 661 err:
 662         dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
 663         return ret;
 664 }
 665
 666 static int tc_get_display_props(struct tc_data *tc)
 667 {
 668         u8 revision, num_lanes;
 669         unsigned int rate;
 670         int ret;
 671         u8 reg;
 672
 673         /* Read DP Rx Link Capability */
 674         ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
 675                                DP_RECEIVER_CAP_SIZE);
 676         if (ret < 0)
 677                 goto err_dpcd_read;
 678
 679         revision = tc->link.dpcd[DP_DPCD_REV];
 680         rate = drm_dp_max_link_rate(tc->link.dpcd);
 681         num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
 682
 683         if (rate != 162000 && rate != 270000) {
 684                 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
 685                 rate = 270000;
 686         }
 687
 688         tc->link.rate = rate;
 689
 690         if (num_lanes > 2) {
 691                 dev_dbg(tc->dev, "Falling to 2 lanes\n");
 692                 num_lanes = 2;
 693         }
 694
 695         tc->link.num_lanes = num_lanes;
 696
 697         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
 698         if (ret < 0)
 699                 goto err_dpcd_read;
 700         tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
 701
 702         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
 703         if (ret < 0)
 704                 goto err_dpcd_read;
 705
 706         tc->link.scrambler_dis = false;
 707         /* read assr */
 708         ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
 709         if (ret < 0)
 710                 goto err_dpcd_read;
 711         tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
 712
 713         dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
 714                 revision >> 4, revision & 0x0f,
 715                 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
 716                 tc->link.num_lanes,
 717                 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
 718                 "enhanced" : "default");
 719         dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
 720                 tc->link.spread ? "0.5%" : "0.0%",
 721                 tc->link.scrambler_dis ? "disabled" : "enabled");
 722         dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
 723                 tc->link.assr, tc->assr);
 724
 725         return 0;
 726
 727 err_dpcd_read:
 728         dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
 729         return ret;
 730 }
 731
 732 static int tc_set_video_mode(struct tc_data *tc,
 733                              const struct drm_display_mode *mode)
 734 {
 735         int ret;
 736         int vid_sync_dly;
 737         int max_tu_symbol;
 738
 739         int left_margin = mode->htotal - mode->hsync_end;
 740         int right_margin = mode->hsync_start - mode->hdisplay;
 741         int hsync_len = mode->hsync_end - mode->hsync_start;
 742         int upper_margin = mode->vtotal - mode->vsync_end;
 743         int lower_margin = mode->vsync_start - mode->vdisplay;
 744         int vsync_len = mode->vsync_end - mode->vsync_start;
 745         u32 dp0_syncval;
 746         u32 bits_per_pixel = 24;
 747         u32 in_bw, out_bw;
 748
 749         /*
 750          * Recommended maximum number of symbols transferred in a transfer unit:
 751          * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
 752          *              (output active video bandwidth in bytes))
 753          * Must be less than tu_size.
 754          */
 755
 756         in_bw = mode->clock * bits_per_pixel / 8;
 757         out_bw = tc->link.num_lanes * tc->link.rate;
 758         max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
 759
 760         dev_dbg(tc->dev, "set mode %dx%d\n",
 761                 mode->hdisplay, mode->vdisplay);
 762         dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
 763                 left_margin, right_margin, hsync_len);
 764         dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
 765                 upper_margin, lower_margin, vsync_len);
 766         dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
 767
 768
 769         /*
 770          * LCD Ctl Frame Size
 771          * datasheet is not clear of vsdelay in case of DPI
 772          * assume we do not need any delay when DPI is a source of
 773          * sync signals
 774          */
 775         ret = regmap_write(tc->regmap, VPCTRL0,
 776                            FIELD_PREP(VSDELAY, 0) |
 777                            OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
 778         if (ret)
 779                 return ret;
 780
 781         ret = regmap_write(tc->regmap, HTIM01,
 782                            FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
 783                            FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
 784         if (ret)
 785                 return ret;
 786
 787         ret = regmap_write(tc->regmap, HTIM02,
 788                            FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
 789                            FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
 790         if (ret)
 791                 return ret;
 792
 793         ret = regmap_write(tc->regmap, VTIM01,
 794                            FIELD_PREP(VBPR, upper_margin) |
 795                            FIELD_PREP(VSPR, vsync_len));
 796         if (ret)
 797                 return ret;
 798
 799         ret = regmap_write(tc->regmap, VTIM02,
 800                            FIELD_PREP(VFPR, lower_margin) |
 801                            FIELD_PREP(VDISPR, mode->vdisplay));
 802         if (ret)
 803                 return ret;
 804
 805         ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
 806         if (ret)
 807                 return ret;
 808
 809         /* Test pattern settings */
 810         ret = regmap_write(tc->regmap, TSTCTL,
 811                            FIELD_PREP(COLOR_R, 120) |
 812                            FIELD_PREP(COLOR_G, 20) |
 813                            FIELD_PREP(COLOR_B, 99) |
 814                            ENI2CFILTER |
 815                            FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
 816         if (ret)
 817                 return ret;
 818
 819         /* DP Main Stream Attributes */
 820         vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
 821         ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
 822                  FIELD_PREP(THRESH_DLY, max_tu_symbol) |
 823                  FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
 824
 825         ret = regmap_write(tc->regmap, DP0_TOTALVAL,
 826                            FIELD_PREP(H_TOTAL, mode->htotal) |
 827                            FIELD_PREP(V_TOTAL, mode->vtotal));
 828         if (ret)
 829                 return ret;
 830
 831         ret = regmap_write(tc->regmap, DP0_STARTVAL,
 832                            FIELD_PREP(H_START, left_margin + hsync_len) |
 833                            FIELD_PREP(V_START, upper_margin + vsync_len));
 834         if (ret)
 835                 return ret;
 836
 837         ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
 838                            FIELD_PREP(V_ACT, mode->vdisplay) |
 839                            FIELD_PREP(H_ACT, mode->hdisplay));
 840         if (ret)
 841                 return ret;
 842
 843         dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
 844                       FIELD_PREP(HS_WIDTH, hsync_len);
 845
 846         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 847                 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
 848
 849         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 850                 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
 851
 852         ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
 853         if (ret)
 854                 return ret;
 855
 856         ret = regmap_write(tc->regmap, DPIPXLFMT,
 857                            VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
 858                            DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
 859                            DPI_BPP_RGB888);
 860         if (ret)
 861                 return ret;
 862
 863         ret = regmap_write(tc->regmap, DP0_MISC,
 864                            FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
 865                            FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
 866                            BPC_8);
 867         if (ret)
 868                 return ret;
 869
 870         return 0;
 871 }
 872
 873 static int tc_wait_link_training(struct tc_data *tc)
 874 {
 875         u32 value;
 876         int ret;
 877
 878         ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
 879                               LT_LOOPDONE, 1, 1000);
 880         if (ret) {
 881                 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
 882                 return ret;
 883         }
 884
 885         ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
 886         if (ret)
 887                 return ret;
 888
 889         return (value >> 8) & 0x7;
 890 }
 891
 892 static int tc_main_link_enable(struct tc_data *tc)
 893 {
 894         struct drm_dp_aux *aux = &tc->aux;
 895         struct device *dev = tc->dev;
 896         u32 dp_phy_ctrl;
 897         u32 value;
 898         int ret;
 899         u8 tmp[DP_LINK_STATUS_SIZE];
 900
 901         dev_dbg(tc->dev, "link enable\n");
 902
 903         ret = regmap_read(tc->regmap, DP0CTL, &value);
 904         if (ret)
 905                 return ret;
 906
 907         if (WARN_ON(value & DP_EN)) {
 908                 ret = regmap_write(tc->regmap, DP0CTL, 0);
 909                 if (ret)
 910                         return ret;
 911         }
 912
 913         ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
 914         if (ret)
 915                 return ret;
 916         /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
 917         ret = regmap_write(tc->regmap, DP1_SRCCTRL,
 918                  (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
 919                  ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
 920         if (ret)
 921                 return ret;
 922
 923         ret = tc_set_syspllparam(tc);
 924         if (ret)
 925                 return ret;
 926
 927         /* Setup Main Link */
 928         dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
 929         if (tc->link.num_lanes == 2)
 930                 dp_phy_ctrl |= PHY_2LANE;
 931
 932         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 933         if (ret)
 934                 return ret;
 935
 936         /* PLL setup */
 937         ret = tc_pllupdate(tc, DP0_PLLCTRL);
 938         if (ret)
 939                 return ret;
 940
 941         ret = tc_pllupdate(tc, DP1_PLLCTRL);
 942         if (ret)
 943                 return ret;
 944
 945         /* Reset/Enable Main Links */
 946         dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
 947         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 948         usleep_range(100, 200);
 949         dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
 950         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 951
 952         ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
 953         if (ret) {
 954                 dev_err(dev, "timeout waiting for phy become ready");
 955                 return ret;
 956         }
 957
 958         /* Set misc: 8 bits per color */
 959         ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
 960         if (ret)
 961                 return ret;
 962
 963         /*
 964          * ASSR mode
 965          * on TC358767 side ASSR configured through strap pin
 966          * seems there is no way to change this setting from SW
 967          *
 968          * check is tc configured for same mode
 969          */
 970         if (tc->assr != tc->link.assr) {
 971                 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
 972                         tc->assr);
 973                 /* try to set ASSR on display side */
 974                 tmp[0] = tc->assr;
 975                 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
 976                 if (ret < 0)
 977                         goto err_dpcd_read;
 978                 /* read back */
 979                 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
 980                 if (ret < 0)
 981                         goto err_dpcd_read;
 982
 983                 if (tmp[0] != tc->assr) {
 984                         dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
 985                                 tc->assr);
 986                         /* trying with disabled scrambler */
 987                         tc->link.scrambler_dis = true;
 988                 }
 989         }
 990
 991         /* Setup Link & DPRx Config for Training */
 992         tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
 993         tmp[1] = tc->link.num_lanes;
 994
 995         if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
 996                 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 997
 998         ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
 999         if (ret < 0)
1000                 goto err_dpcd_write;
1001
1002         /* DOWNSPREAD_CTRL */
1003         tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1004         /* MAIN_LINK_CHANNEL_CODING_SET */
1005         tmp[1] =  DP_SET_ANSI_8B10B;
1006         ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1007         if (ret < 0)
1008                 goto err_dpcd_write;
1009
1010         /* Reset voltage-swing & pre-emphasis */
1011         tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1012                           DP_TRAIN_PRE_EMPH_LEVEL_0;
1013         ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1014         if (ret < 0)
1015                 goto err_dpcd_write;
1016
1017         /* Clock-Recovery */
1018
1019         /* Set DPCD 0x102 for Training Pattern 1 */
1020         ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1021                            DP_LINK_SCRAMBLING_DISABLE |
1022                            DP_TRAINING_PATTERN_1);
1023         if (ret)
1024                 return ret;
1025
1026         ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1027                            (15 << 28) | /* Defer Iteration Count */
1028                            (15 << 24) | /* Loop Iteration Count */
1029                            (0xd << 0)); /* Loop Timer Delay */
1030         if (ret)
1031                 return ret;
1032
1033         ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1034                            tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1035                            DP0_SRCCTRL_AUTOCORRECT |
1036                            DP0_SRCCTRL_TP1);
1037         if (ret)
1038                 return ret;
1039
1040         /* Enable DP0 to start Link Training */
1041         ret = regmap_write(tc->regmap, DP0CTL,
1042                            (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1043                                 EF_EN : 0) | DP_EN);
1044         if (ret)
1045                 return ret;
1046
1047         /* wait */
1048
1049         ret = tc_wait_link_training(tc);
1050         if (ret < 0)
1051                 return ret;
1052
1053         if (ret) {
1054                 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1055                         training_pattern1_errors[ret]);
1056                 return -ENODEV;
1057         }
1058
1059         /* Channel Equalization */
1060
1061         /* Set DPCD 0x102 for Training Pattern 2 */
1062         ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1063                            DP_LINK_SCRAMBLING_DISABLE |
1064                            DP_TRAINING_PATTERN_2);
1065         if (ret)
1066                 return ret;
1067
1068         ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1069                            tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1070                            DP0_SRCCTRL_AUTOCORRECT |
1071                            DP0_SRCCTRL_TP2);
1072         if (ret)
1073                 return ret;
1074
1075         /* wait */
1076         ret = tc_wait_link_training(tc);
1077         if (ret < 0)
1078                 return ret;
1079
1080         if (ret) {
1081                 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1082                         training_pattern2_errors[ret]);
1083                 return -ENODEV;
1084         }
1085
1086         /*
1087          * Toshiba's documentation suggests to first clear DPCD 0x102, then
1088          * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1089          * that the link sometimes drops if those steps are done in that order,
1090          * but if the steps are done in reverse order, the link stays up.
1091          *
1092          * So we do the steps differently than documented here.
1093          */
1094
1095         /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1096         ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1097                            DP0_SRCCTRL_AUTOCORRECT);
1098         if (ret)
1099                 return ret;
1100
1101         /* Clear DPCD 0x102 */
1102         /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1103         tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1104         ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1105         if (ret < 0)
1106                 goto err_dpcd_write;
1107
1108         /* Check link status */
1109         ret = drm_dp_dpcd_read_link_status(aux, tmp);
1110         if (ret < 0)
1111                 goto err_dpcd_read;
1112
1113         ret = 0;
1114
1115         value = tmp[0] & DP_CHANNEL_EQ_BITS;
1116
1117         if (value != DP_CHANNEL_EQ_BITS) {
1118                 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1119                 ret = -ENODEV;
1120         }
1121
1122         if (tc->link.num_lanes == 2) {
1123                 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1124
1125                 if (value != DP_CHANNEL_EQ_BITS) {
1126                         dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1127                         ret = -ENODEV;
1128                 }
1129
1130                 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1131                         dev_err(tc->dev, "Interlane align failed\n");
1132                         ret = -ENODEV;
1133                 }
1134         }
1135
1136         if (ret) {
1137                 dev_err(dev, "0x0202 LANE0_1_STATUS:            0x%02x\n", tmp[0]);
1138                 dev_err(dev, "0x0203 LANE2_3_STATUS             0x%02x\n", tmp[1]);
1139                 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1140                 dev_err(dev, "0x0205 SINK_STATUS:               0x%02x\n", tmp[3]);
1141                 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1:    0x%02x\n", tmp[4]);
1142                 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3:    0x%02x\n", tmp[5]);
1143                 return ret;
1144         }
1145
1146         return 0;
1147 err_dpcd_read:
1148         dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1149         return ret;
1150 err_dpcd_write:
1151         dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1152         return ret;
1153 }
1154
1155 static int tc_main_link_disable(struct tc_data *tc)
1156 {
1157         int ret;
1158
1159         dev_dbg(tc->dev, "link disable\n");
1160
1161         ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1162         if (ret)
1163                 return ret;
1164
1165         return regmap_write(tc->regmap, DP0CTL, 0);
1166 }
1167
1168 static int tc_stream_enable(struct tc_data *tc)
1169 {
1170         int ret;
1171         u32 value;
1172
1173         dev_dbg(tc->dev, "enable video stream\n");
1174
1175         /* PXL PLL setup */
1176         if (tc_test_pattern) {
1177                 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1178                                     1000 * tc->mode.clock);
1179                 if (ret)
1180                         return ret;
1181         }
1182
1183         ret = tc_set_video_mode(tc, &tc->mode);
1184         if (ret)
1185                 return ret;
1186
1187         /* Set M/N */
1188         ret = tc_stream_clock_calc(tc);
1189         if (ret)
1190                 return ret;
1191
1192         value = VID_MN_GEN | DP_EN;
1193         if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1194                 value |= EF_EN;
1195         ret = regmap_write(tc->regmap, DP0CTL, value);
1196         if (ret)
1197                 return ret;
1198         /*
1199          * VID_EN assertion should be delayed by at least N * LSCLK
1200          * cycles from the time VID_MN_GEN is enabled in order to
1201          * generate stable values for VID_M. LSCLK is 270 MHz or
1202          * 162 MHz, VID_N is set to 32768 in  tc_stream_clock_calc(),
1203          * so a delay of at least 203 us should suffice.
1204          */
1205         usleep_range(500, 1000);
1206         value |= VID_EN;
1207         ret = regmap_write(tc->regmap, DP0CTL, value);
1208         if (ret)
1209                 return ret;
1210         /* Set input interface */
1211         value = DP0_AUDSRC_NO_INPUT;
1212         if (tc_test_pattern)
1213                 value |= DP0_VIDSRC_COLOR_BAR;
1214         else
1215                 value |= DP0_VIDSRC_DPI_RX;
1216         ret = regmap_write(tc->regmap, SYSCTRL, value);
1217         if (ret)
1218                 return ret;
1219
1220         return 0;
1221 }
1222
1223 static int tc_stream_disable(struct tc_data *tc)
1224 {
1225         int ret;
1226
1227         dev_dbg(tc->dev, "disable video stream\n");
1228
1229         ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1230         if (ret)
1231                 return ret;
1232
1233         tc_pxl_pll_dis(tc);
1234
1235         return 0;
1236 }
1237
1238 static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1239 {
1240         struct tc_data *tc = bridge_to_tc(bridge);
1241
1242         drm_panel_prepare(tc->panel);
1243 }
1244
1245 static void tc_bridge_enable(struct drm_bridge *bridge)
1246 {
1247         struct tc_data *tc = bridge_to_tc(bridge);
1248         int ret;
1249
1250         ret = tc_get_display_props(tc);
1251         if (ret < 0) {
1252                 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1253                 return;
1254         }
1255
1256         ret = tc_main_link_enable(tc);
1257         if (ret < 0) {
1258                 dev_err(tc->dev, "main link enable error: %d\n", ret);
1259                 return;
1260         }
1261
1262         ret = tc_stream_enable(tc);
1263         if (ret < 0) {
1264                 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1265                 tc_main_link_disable(tc);
1266                 return;
1267         }
1268
1269         drm_panel_enable(tc->panel);
1270 }
1271
1272 static void tc_bridge_disable(struct drm_bridge *bridge)
1273 {
1274         struct tc_data *tc = bridge_to_tc(bridge);
1275         int ret;
1276
1277         drm_panel_disable(tc->panel);
1278
1279         ret = tc_stream_disable(tc);
1280         if (ret < 0)
1281                 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1282
1283         ret = tc_main_link_disable(tc);
1284         if (ret < 0)
1285                 dev_err(tc->dev, "main link disable error: %d\n", ret);
1286 }
1287
1288 static void tc_bridge_post_disable(struct drm_bridge *bridge)
1289 {
1290         struct tc_data *tc = bridge_to_tc(bridge);
1291
1292         drm_panel_unprepare(tc->panel);
1293 }
1294
1295 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1296                                  const struct drm_display_mode *mode,
1297                                  struct drm_display_mode *adj)
1298 {
1299         /* Fixup sync polarities, both hsync and vsync are active low */
1300         adj->flags = mode->flags;
1301         adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1302         adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1303
1304         return true;
1305 }
1306
1307 static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
1308                                           const struct drm_display_mode *mode)
1309 {
1310         struct tc_data *tc = bridge_to_tc(bridge);
1311         u32 req, avail;
1312         u32 bits_per_pixel = 24;
1313
1314         /* DPI interface clock limitation: upto 154 MHz */
1315         if (mode->clock > 154000)
1316                 return MODE_CLOCK_HIGH;
1317
1318         req = mode->clock * bits_per_pixel / 8;
1319         avail = tc->link.num_lanes * tc->link.rate;
1320
1321         if (req > avail)
1322                 return MODE_BAD;
1323
1324         return MODE_OK;
1325 }
1326
1327 static void tc_bridge_mode_set(struct drm_bridge *bridge,
1328                                const struct drm_display_mode *mode,
1329                                const struct drm_display_mode *adj)
1330 {
1331         struct tc_data *tc = bridge_to_tc(bridge);
1332
1333         tc->mode = *mode;
1334 }
1335
1336 static int tc_connector_get_modes(struct drm_connector *connector)
1337 {
1338         struct tc_data *tc = connector_to_tc(connector);
1339         struct edid *edid;
1340         int count;
1341         int ret;
1342
1343         ret = tc_get_display_props(tc);
1344         if (ret < 0) {
1345                 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1346                 return 0;
1347         }
1348
1349         count = drm_panel_get_modes(tc->panel, connector);
1350         if (count > 0)
1351                 return count;
1352
1353         edid = drm_get_edid(connector, &tc->aux.ddc);
1354
1355         kfree(tc->edid);
1356         tc->edid = edid;
1357         if (!edid)
1358                 return 0;
1359
1360         drm_connector_update_edid_property(connector, edid);
1361         count = drm_add_edid_modes(connector, edid);
1362
1363         return count;
1364 }
1365
1366 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1367         .get_modes = tc_connector_get_modes,
1368 };
1369
1370 static enum drm_connector_status tc_connector_detect(struct drm_connector *connector,
1371                                                      bool force)
1372 {
1373         struct tc_data *tc = connector_to_tc(connector);
1374         bool conn;
1375         u32 val;
1376         int ret;
1377
1378         if (tc->hpd_pin < 0) {
1379                 if (tc->panel)
1380                         return connector_status_connected;
1381                 else
1382                         return connector_status_unknown;
1383         }
1384
1385         ret = regmap_read(tc->regmap, GPIOI, &val);
1386         if (ret)
1387                 return connector_status_unknown;
1388
1389         conn = val & BIT(tc->hpd_pin);
1390
1391         if (conn)
1392                 return connector_status_connected;
1393         else
1394                 return connector_status_disconnected;
1395 }
1396
1397 static const struct drm_connector_funcs tc_connector_funcs = {
1398         .detect = tc_connector_detect,
1399         .fill_modes = drm_helper_probe_single_connector_modes,
1400         .destroy = drm_connector_cleanup,
1401         .reset = drm_atomic_helper_connector_reset,
1402         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1403         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1404 };
1405
1406 static int tc_bridge_attach(struct drm_bridge *bridge)
1407 {
1408         u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1409         struct tc_data *tc = bridge_to_tc(bridge);
1410         struct drm_device *drm = bridge->dev;
1411         int ret;
1412
1413         /* Create DP/eDP connector */
1414         drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1415         ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1416                                  tc->panel ? DRM_MODE_CONNECTOR_eDP :
1417                                  DRM_MODE_CONNECTOR_DisplayPort);
1418         if (ret)
1419                 return ret;
1420
1421         /* Don't poll if don't have HPD connected */
1422         if (tc->hpd_pin >= 0) {
1423                 if (tc->have_irq)
1424                         tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1425                 else
1426                         tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1427                                                DRM_CONNECTOR_POLL_DISCONNECT;
1428         }
1429
1430         if (tc->panel)
1431                 drm_panel_attach(tc->panel, &tc->connector);
1432
1433         drm_display_info_set_bus_formats(&tc->connector.display_info,
1434                                          &bus_format, 1);
1435         tc->connector.display_info.bus_flags =
1436                 DRM_BUS_FLAG_DE_HIGH |
1437                 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1438                 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1439         drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1440
1441         return 0;
1442 }
1443
1444 static const struct drm_bridge_funcs tc_bridge_funcs = {
1445         .attach = tc_bridge_attach,
1446         .mode_valid = tc_mode_valid,
1447         .mode_set = tc_bridge_mode_set,
1448         .pre_enable = tc_bridge_pre_enable,
1449         .enable = tc_bridge_enable,
1450         .disable = tc_bridge_disable,
1451         .post_disable = tc_bridge_post_disable,
1452         .mode_fixup = tc_bridge_mode_fixup,
1453 };
1454
1455 static bool tc_readable_reg(struct device *dev, unsigned int reg)
1456 {
1457         return reg != SYSCTRL;
1458 }
1459
1460 static const struct regmap_range tc_volatile_ranges[] = {
1461         regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1462         regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1463         regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1464         regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1465         regmap_reg_range(VFUEN0, VFUEN0),
1466         regmap_reg_range(INTSTS_G, INTSTS_G),
1467         regmap_reg_range(GPIOI, GPIOI),
1468 };
1469
1470 static const struct regmap_access_table tc_volatile_table = {
1471         .yes_ranges = tc_volatile_ranges,
1472         .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1473 };
1474
1475 static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1476 {
1477         return (reg != TC_IDREG) &&
1478                (reg != DP0_LTSTAT) &&
1479                (reg != DP0_SNKLTCHGREQ);
1480 }
1481
1482 static const struct regmap_config tc_regmap_config = {
1483         .name = "tc358767",
1484         .reg_bits = 16,
1485         .val_bits = 32,
1486         .reg_stride = 4,
1487         .max_register = PLL_DBG,
1488         .cache_type = REGCACHE_RBTREE,
1489         .readable_reg = tc_readable_reg,
1490         .volatile_table = &tc_volatile_table,
1491         .writeable_reg = tc_writeable_reg,
1492         .reg_format_endian = REGMAP_ENDIAN_BIG,
1493         .val_format_endian = REGMAP_ENDIAN_LITTLE,
1494 };
1495
1496 static irqreturn_t tc_irq_handler(int irq, void *arg)
1497 {
1498         struct tc_data *tc = arg;
1499         u32 val;
1500         int r;
1501
1502         r = regmap_read(tc->regmap, INTSTS_G, &val);
1503         if (r)
1504                 return IRQ_NONE;
1505
1506         if (!val)
1507                 return IRQ_NONE;
1508
1509         if (val & INT_SYSERR) {
1510                 u32 stat = 0;
1511
1512                 regmap_read(tc->regmap, SYSSTAT, &stat);
1513
1514                 dev_err(tc->dev, "syserr %x\n", stat);
1515         }
1516
1517         if (tc->hpd_pin >= 0 && tc->bridge.dev) {
1518                 /*
1519                  * H is triggered when the GPIO goes high.
1520                  *
1521                  * LC is triggered when the GPIO goes low and stays low for
1522                  * the duration of LCNT
1523                  */
1524                 bool h = val & INT_GPIO_H(tc->hpd_pin);
1525                 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
1526
1527                 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
1528                         h ? "H" : "", lc ? "LC" : "");
1529
1530                 if (h || lc)
1531                         drm_kms_helper_hotplug_event(tc->bridge.dev);
1532         }
1533
1534         regmap_write(tc->regmap, INTSTS_G, val);
1535
1536         return IRQ_HANDLED;
1537 }
1538
1539 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1540 {
1541         struct device *dev = &client->dev;
1542         struct tc_data *tc;
1543         int ret;
1544
1545         tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1546         if (!tc)
1547                 return -ENOMEM;
1548
1549         tc->dev = dev;
1550
1551         /* port@2 is the output port */
1552         ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1553         if (ret && ret != -ENODEV)
1554                 return ret;
1555
1556         /* Shut down GPIO is optional */
1557         tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1558         if (IS_ERR(tc->sd_gpio))
1559                 return PTR_ERR(tc->sd_gpio);
1560
1561         if (tc->sd_gpio) {
1562                 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1563                 usleep_range(5000, 10000);
1564         }
1565
1566         /* Reset GPIO is optional */
1567         tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1568         if (IS_ERR(tc->reset_gpio))
1569                 return PTR_ERR(tc->reset_gpio);
1570
1571         if (tc->reset_gpio) {
1572                 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1573                 usleep_range(5000, 10000);
1574         }
1575
1576         tc->refclk = devm_clk_get(dev, "ref");
1577         if (IS_ERR(tc->refclk)) {
1578                 ret = PTR_ERR(tc->refclk);
1579                 dev_err(dev, "Failed to get refclk: %d\n", ret);
1580                 return ret;
1581         }
1582
1583         tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1584         if (IS_ERR(tc->regmap)) {
1585                 ret = PTR_ERR(tc->regmap);
1586                 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1587                 return ret;
1588         }
1589
1590         ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
1591                                    &tc->hpd_pin);
1592         if (ret) {
1593                 tc->hpd_pin = -ENODEV;
1594         } else {
1595                 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
1596                         dev_err(dev, "failed to parse HPD number\n");
1597                         return ret;
1598                 }
1599         }
1600
1601         if (client->irq > 0) {
1602                 /* enable SysErr */
1603                 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
1604
1605                 ret = devm_request_threaded_irq(dev, client->irq,
1606                                                 NULL, tc_irq_handler,
1607                                                 IRQF_ONESHOT,
1608                                                 "tc358767-irq", tc);
1609                 if (ret) {
1610                         dev_err(dev, "failed to register dp interrupt\n");
1611                         return ret;
1612                 }
1613
1614                 tc->have_irq = true;
1615         }
1616
1617         ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1618         if (ret) {
1619                 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1620                 return ret;
1621         }
1622
1623         if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1624                 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1625                 return -EINVAL;
1626         }
1627
1628         tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1629
1630         if (!tc->reset_gpio) {
1631                 /*
1632                  * If the reset pin isn't present, do a software reset. It isn't
1633                  * as thorough as the hardware reset, as we can't reset the I2C
1634                  * communication block for obvious reasons, but it's getting the
1635                  * chip into a defined state.
1636                  */
1637                 regmap_update_bits(tc->regmap, SYSRSTENB,
1638                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1639                                 0);
1640                 regmap_update_bits(tc->regmap, SYSRSTENB,
1641                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1642                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
1643                 usleep_range(5000, 10000);
1644         }
1645
1646         if (tc->hpd_pin >= 0) {
1647                 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
1648                 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
1649
1650                 /* Set LCNT to 2ms */
1651                 regmap_write(tc->regmap, lcnt_reg,
1652                              clk_get_rate(tc->refclk) * 2 / 1000);
1653                 /* We need the "alternate" mode for HPD */
1654                 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
1655
1656                 if (tc->have_irq) {
1657                         /* enable H & LC */
1658                         regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
1659                 }
1660         }
1661
1662         ret = tc_aux_link_setup(tc);
1663         if (ret)
1664                 return ret;
1665
1666         /* Register DP AUX channel */
1667         tc->aux.name = "TC358767 AUX i2c adapter";
1668         tc->aux.dev = tc->dev;
1669         tc->aux.transfer = tc_aux_transfer;
1670         ret = drm_dp_aux_register(&tc->aux);
1671         if (ret)
1672                 return ret;
1673
1674         tc->bridge.funcs = &tc_bridge_funcs;
1675         tc->bridge.of_node = dev->of_node;
1676         drm_bridge_add(&tc->bridge);
1677
1678         i2c_set_clientdata(client, tc);
1679
1680         return 0;
1681 }
1682
1683 static int tc_remove(struct i2c_client *client)
1684 {
1685         struct tc_data *tc = i2c_get_clientdata(client);
1686
1687         drm_bridge_remove(&tc->bridge);
1688         drm_dp_aux_unregister(&tc->aux);
1689
1690         return 0;
1691 }
1692
1693 static const struct i2c_device_id tc358767_i2c_ids[] = {
1694         { "tc358767", 0 },
1695         { }
1696 };
1697 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1698
1699 static const struct of_device_id tc358767_of_ids[] = {
1700         { .compatible = "toshiba,tc358767", },
1701         { }
1702 };
1703 MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1704
1705 static struct i2c_driver tc358767_driver = {
1706         .driver = {
1707                 .name = "tc358767",
1708                 .of_match_table = tc358767_of_ids,
1709         },
1710         .id_table = tc358767_i2c_ids,
1711         .probe = tc_probe,
1712         .remove = tc_remove,
1713 };
1714 module_i2c_driver(tc358767_driver);
1715
1716 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1717 MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1718 MODULE_LICENSE("GPL");