drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   4  * Copyright (C) STMicroelectronics SA 2017
   5  *
   6  * Modified by Philippe Cornu <philippe.cornu@st.com>
   7  * This generic Synopsys DesignWare MIPI DSI host driver is based on the
   8  * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/debugfs.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/reset.h>
  19
  20 #include <video/mipi_display.h>
  21
  22 #include <drm/bridge/dw_mipi_dsi.h>
  23 #include <drm/drm_atomic_helper.h>
  24 #include <drm/drm_bridge.h>
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_mipi_dsi.h>
  27 #include <drm/drm_modes.h>
  28 #include <drm/drm_of.h>
  29 #include <drm/drm_print.h>
  30 #include <drm/drm_probe_helper.h>
  31
  32 #define HWVER_131                       0x31333100      /* IP version 1.31 */
  33
  34 #define DSI_VERSION                     0x00
  35 #define VERSION                         GENMASK(31, 8)
  36
  37 #define DSI_PWR_UP                      0x04
  38 #define RESET                           0
  39 #define POWERUP                         BIT(0)
  40
  41 #define DSI_CLKMGR_CFG                  0x08
  42 #define TO_CLK_DIVISION(div)            (((div) & 0xff) << 8)
  43 #define TX_ESC_CLK_DIVISION(div)        ((div) & 0xff)
  44
  45 #define DSI_DPI_VCID                    0x0c
  46 #define DPI_VCID(vcid)                  ((vcid) & 0x3)
  47
  48 #define DSI_DPI_COLOR_CODING            0x10
  49 #define LOOSELY18_EN                    BIT(8)
  50 #define DPI_COLOR_CODING_16BIT_1        0x0
  51 #define DPI_COLOR_CODING_16BIT_2        0x1
  52 #define DPI_COLOR_CODING_16BIT_3        0x2
  53 #define DPI_COLOR_CODING_18BIT_1        0x3
  54 #define DPI_COLOR_CODING_18BIT_2        0x4
  55 #define DPI_COLOR_CODING_24BIT          0x5
  56
  57 #define DSI_DPI_CFG_POL                 0x14
  58 #define COLORM_ACTIVE_LOW               BIT(4)
  59 #define SHUTD_ACTIVE_LOW                BIT(3)
  60 #define HSYNC_ACTIVE_LOW                BIT(2)
  61 #define VSYNC_ACTIVE_LOW                BIT(1)
  62 #define DATAEN_ACTIVE_LOW               BIT(0)
  63
  64 #define DSI_DPI_LP_CMD_TIM              0x18
  65 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  66 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  67
  68 #define DSI_DBI_VCID                    0x1c
  69 #define DSI_DBI_CFG                     0x20
  70 #define DSI_DBI_PARTITIONING_EN         0x24
  71 #define DSI_DBI_CMDSIZE                 0x28
  72
  73 #define DSI_PCKHDL_CFG                  0x2c
  74 #define CRC_RX_EN                       BIT(4)
  75 #define ECC_RX_EN                       BIT(3)
  76 #define BTA_EN                          BIT(2)
  77 #define EOTP_RX_EN                      BIT(1)
  78 #define EOTP_TX_EN                      BIT(0)
  79
  80 #define DSI_GEN_VCID                    0x30
  81
  82 #define DSI_MODE_CFG                    0x34
  83 #define ENABLE_VIDEO_MODE               0
  84 #define ENABLE_CMD_MODE                 BIT(0)
  85
  86 #define DSI_VID_MODE_CFG                0x38
  87 #define ENABLE_LOW_POWER                (0x3f << 8)
  88 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  89 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES     0x0
  90 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS     0x1
  91 #define VID_MODE_TYPE_BURST                     0x2
  92 #define VID_MODE_TYPE_MASK                      0x3
  93 #define VID_MODE_VPG_ENABLE             BIT(16)
  94 #define VID_MODE_VPG_HORIZONTAL         BIT(24)
  95
  96 #define DSI_VID_PKT_SIZE                0x3c
  97 #define VID_PKT_SIZE(p)                 ((p) & 0x3fff)
  98
  99 #define DSI_VID_NUM_CHUNKS              0x40
 100 #define VID_NUM_CHUNKS(c)               ((c) & 0x1fff)
 101
 102 #define DSI_VID_NULL_SIZE               0x44
 103 #define VID_NULL_SIZE(b)                ((b) & 0x1fff)
 104
 105 #define DSI_VID_HSA_TIME                0x48
 106 #define DSI_VID_HBP_TIME                0x4c
 107 #define DSI_VID_HLINE_TIME              0x50
 108 #define DSI_VID_VSA_LINES               0x54
 109 #define DSI_VID_VBP_LINES               0x58
 110 #define DSI_VID_VFP_LINES               0x5c
 111 #define DSI_VID_VACTIVE_LINES           0x60
 112 #define DSI_EDPI_CMD_SIZE               0x64
 113
 114 #define DSI_CMD_MODE_CFG                0x68
 115 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 116 #define DCS_LW_TX_LP                    BIT(19)
 117 #define DCS_SR_0P_TX_LP                 BIT(18)
 118 #define DCS_SW_1P_TX_LP                 BIT(17)
 119 #define DCS_SW_0P_TX_LP                 BIT(16)
 120 #define GEN_LW_TX_LP                    BIT(14)
 121 #define GEN_SR_2P_TX_LP                 BIT(13)
 122 #define GEN_SR_1P_TX_LP                 BIT(12)
 123 #define GEN_SR_0P_TX_LP                 BIT(11)
 124 #define GEN_SW_2P_TX_LP                 BIT(10)
 125 #define GEN_SW_1P_TX_LP                 BIT(9)
 126 #define GEN_SW_0P_TX_LP                 BIT(8)
 127 #define ACK_RQST_EN                     BIT(1)
 128 #define TEAR_FX_EN                      BIT(0)
 129
 130 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 131                                          DCS_LW_TX_LP | \
 132                                          DCS_SR_0P_TX_LP | \
 133                                          DCS_SW_1P_TX_LP | \
 134                                          DCS_SW_0P_TX_LP | \
 135                                          GEN_LW_TX_LP | \
 136                                          GEN_SR_2P_TX_LP | \
 137                                          GEN_SR_1P_TX_LP | \
 138                                          GEN_SR_0P_TX_LP | \
 139                                          GEN_SW_2P_TX_LP | \
 140                                          GEN_SW_1P_TX_LP | \
 141                                          GEN_SW_0P_TX_LP)
 142
 143 #define DSI_GEN_HDR                     0x6c
 144 #define DSI_GEN_PLD_DATA                0x70
 145
 146 #define DSI_CMD_PKT_STATUS              0x74
 147 #define GEN_RD_CMD_BUSY                 BIT(6)
 148 #define GEN_PLD_R_FULL                  BIT(5)
 149 #define GEN_PLD_R_EMPTY                 BIT(4)
 150 #define GEN_PLD_W_FULL                  BIT(3)
 151 #define GEN_PLD_W_EMPTY                 BIT(2)
 152 #define GEN_CMD_FULL                    BIT(1)
 153 #define GEN_CMD_EMPTY                   BIT(0)
 154
 155 #define DSI_TO_CNT_CFG                  0x78
 156 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 157 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 158
 159 #define DSI_HS_RD_TO_CNT                0x7c
 160 #define DSI_LP_RD_TO_CNT                0x80
 161 #define DSI_HS_WR_TO_CNT                0x84
 162 #define DSI_LP_WR_TO_CNT                0x88
 163 #define DSI_BTA_TO_CNT                  0x8c
 164
 165 #define DSI_LPCLK_CTRL                  0x94
 166 #define AUTO_CLKLANE_CTRL               BIT(1)
 167 #define PHY_TXREQUESTCLKHS              BIT(0)
 168
 169 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 170 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 171 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 172
 173 #define DSI_PHY_TMR_CFG                 0x9c
 174 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 175 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 176 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 177 #define PHY_HS2LP_TIME_V131(lbcc)       (((lbcc) & 0x3ff) << 16)
 178 #define PHY_LP2HS_TIME_V131(lbcc)       ((lbcc) & 0x3ff)
 179
 180 #define DSI_PHY_RSTZ                    0xa0
 181 #define PHY_DISFORCEPLL                 0
 182 #define PHY_ENFORCEPLL                  BIT(3)
 183 #define PHY_DISABLECLK                  0
 184 #define PHY_ENABLECLK                   BIT(2)
 185 #define PHY_RSTZ                        0
 186 #define PHY_UNRSTZ                      BIT(1)
 187 #define PHY_SHUTDOWNZ                   0
 188 #define PHY_UNSHUTDOWNZ                 BIT(0)
 189
 190 #define DSI_PHY_IF_CFG                  0xa4
 191 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 192 #define N_LANES(n)                      (((n) - 1) & 0x3)
 193
 194 #define DSI_PHY_ULPS_CTRL               0xa8
 195 #define DSI_PHY_TX_TRIGGERS             0xac
 196
 197 #define DSI_PHY_STATUS                  0xb0
 198 #define PHY_STOP_STATE_CLK_LANE         BIT(2)
 199 #define PHY_LOCK                        BIT(0)
 200
 201 #define DSI_PHY_TST_CTRL0               0xb4
 202 #define PHY_TESTCLK                     BIT(1)
 203 #define PHY_UNTESTCLK                   0
 204 #define PHY_TESTCLR                     BIT(0)
 205 #define PHY_UNTESTCLR                   0
 206
 207 #define DSI_PHY_TST_CTRL1               0xb8
 208 #define PHY_TESTEN                      BIT(16)
 209 #define PHY_UNTESTEN                    0
 210 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 211 #define PHY_TESTDIN(n)                  ((n) & 0xff)
 212
 213 #define DSI_INT_ST0                     0xbc
 214 #define DSI_INT_ST1                     0xc0
 215 #define DSI_INT_MSK0                    0xc4
 216 #define DSI_INT_MSK1                    0xc8
 217
 218 #define DSI_PHY_TMR_RD_CFG              0xf4
 219 #define MAX_RD_TIME_V131(lbcc)          ((lbcc) & 0x7fff)
 220
 221 #define PHY_STATUS_TIMEOUT_US           10000
 222 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 223
 224 struct dw_mipi_dsi {
 225         struct drm_bridge bridge;
 226         struct mipi_dsi_host dsi_host;
 227         struct drm_bridge *panel_bridge;
 228         struct device *dev;
 229         void __iomem *base;
 230
 231         struct clk *pclk;
 232
 233         unsigned int lane_mbps; /* per lane */
 234         u32 channel;
 235         u32 lanes;
 236         u32 format;
 237         unsigned long mode_flags;
 238
 239 #ifdef CONFIG_DEBUG_FS
 240         struct dentry *debugfs;
 241
 242         bool vpg;
 243         bool vpg_horizontal;
 244 #endif /* CONFIG_DEBUG_FS */
 245
 246         struct dw_mipi_dsi *master; /* dual-dsi master ptr */
 247         struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
 248
 249         const struct dw_mipi_dsi_plat_data *plat_data;
 250 };
 251
 252 /*
 253  * Check if either a link to a master or slave is present
 254  */
 255 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
 256 {
 257         return dsi->slave || dsi->master;
 258 }
 259
 260 /*
 261  * The controller should generate 2 frames before
 262  * preparing the peripheral.
 263  */
 264 static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode)
 265 {
 266         int refresh, two_frames;
 267
 268         refresh = drm_mode_vrefresh(mode);
 269         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 270         msleep(two_frames);
 271 }
 272
 273 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 274 {
 275         return container_of(host, struct dw_mipi_dsi, dsi_host);
 276 }
 277
 278 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
 279 {
 280         return container_of(bridge, struct dw_mipi_dsi, bridge);
 281 }
 282
 283 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 284 {
 285         writel(val, dsi->base + reg);
 286 }
 287
 288 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 289 {
 290         return readl(dsi->base + reg);
 291 }
 292
 293 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 294                                    struct mipi_dsi_device *device)
 295 {
 296         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 297         const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
 298         struct drm_bridge *bridge;
 299         struct drm_panel *panel;
 300         int ret;
 301
 302         if (device->lanes > dsi->plat_data->max_data_lanes) {
 303                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 304                         device->lanes);
 305                 return -EINVAL;
 306         }
 307
 308         dsi->lanes = device->lanes;
 309         dsi->channel = device->channel;
 310         dsi->format = device->format;
 311         dsi->mode_flags = device->mode_flags;
 312
 313         ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
 314                                           &panel, &bridge);
 315         if (ret)
 316                 return ret;
 317
 318         if (panel) {
 319                 bridge = drm_panel_bridge_add_typed(panel,
 320                                                     DRM_MODE_CONNECTOR_DSI);
 321                 if (IS_ERR(bridge))
 322                         return PTR_ERR(bridge);
 323         }
 324
 325         dsi->panel_bridge = bridge;
 326
 327         drm_bridge_add(&dsi->bridge);
 328
 329         if (pdata->host_ops && pdata->host_ops->attach) {
 330                 ret = pdata->host_ops->attach(pdata->priv_data, device);
 331                 if (ret < 0)
 332                         return ret;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 339                                    struct mipi_dsi_device *device)
 340 {
 341         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 342         const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
 343         int ret;
 344
 345         if (pdata->host_ops && pdata->host_ops->detach) {
 346                 ret = pdata->host_ops->detach(pdata->priv_data, device);
 347                 if (ret < 0)
 348                         return ret;
 349         }
 350
 351         drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
 352
 353         drm_bridge_remove(&dsi->bridge);
 354
 355         return 0;
 356 }
 357
 358 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 359                                    const struct mipi_dsi_msg *msg)
 360 {
 361         bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
 362         u32 val = 0;
 363
 364         if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
 365                 val |= ACK_RQST_EN;
 366         if (lpm)
 367                 val |= CMD_MODE_ALL_LP;
 368
 369         dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
 370         dsi_write(dsi, DSI_CMD_MODE_CFG, val);
 371 }
 372
 373 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 374 {
 375         int ret;
 376         u32 val, mask;
 377
 378         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 379                                  val, !(val & GEN_CMD_FULL), 1000,
 380                                  CMD_PKT_STATUS_TIMEOUT_US);
 381         if (ret) {
 382                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 383                 return ret;
 384         }
 385
 386         dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 387
 388         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 389         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 390                                  val, (val & mask) == mask,
 391                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 392         if (ret) {
 393                 dev_err(dsi->dev, "failed to write command FIFO\n");
 394                 return ret;
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
 401                              const struct mipi_dsi_packet *packet)
 402 {
 403         const u8 *tx_buf = packet->payload;
 404         int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
 405         __le32 word;
 406         u32 val;
 407
 408         while (len) {
 409                 if (len < pld_data_bytes) {
 410                         word = 0;
 411                         memcpy(&word, tx_buf, len);
 412                         dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 413                         len = 0;
 414                 } else {
 415                         memcpy(&word, tx_buf, pld_data_bytes);
 416                         dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 417                         tx_buf += pld_data_bytes;
 418                         len -= pld_data_bytes;
 419                 }
 420
 421                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 422                                          val, !(val & GEN_PLD_W_FULL), 1000,
 423                                          CMD_PKT_STATUS_TIMEOUT_US);
 424                 if (ret) {
 425                         dev_err(dsi->dev,
 426                                 "failed to get available write payload FIFO\n");
 427                         return ret;
 428                 }
 429         }
 430
 431         word = 0;
 432         memcpy(&word, packet->header, sizeof(packet->header));
 433         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
 434 }
 435
 436 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 437                             const struct mipi_dsi_msg *msg)
 438 {
 439         int i, j, ret, len = msg->rx_len;
 440         u8 *buf = msg->rx_buf;
 441         u32 val;
 442
 443         /* Wait end of the read operation */
 444         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 445                                  val, !(val & GEN_RD_CMD_BUSY),
 446                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 447         if (ret) {
 448                 dev_err(dsi->dev, "Timeout during read operation\n");
 449                 return ret;
 450         }
 451
 452         for (i = 0; i < len; i += 4) {
 453                 /* Read fifo must not be empty before all bytes are read */
 454                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 455                                          val, !(val & GEN_PLD_R_EMPTY),
 456                                          1000, CMD_PKT_STATUS_TIMEOUT_US);
 457                 if (ret) {
 458                         dev_err(dsi->dev, "Read payload FIFO is empty\n");
 459                         return ret;
 460                 }
 461
 462                 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
 463                 for (j = 0; j < 4 && j + i < len; j++)
 464                         buf[i + j] = val >> (8 * j);
 465         }
 466
 467         return ret;
 468 }
 469
 470 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 471                                          const struct mipi_dsi_msg *msg)
 472 {
 473         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 474         struct mipi_dsi_packet packet;
 475         int ret, nb_bytes;
 476
 477         ret = mipi_dsi_create_packet(&packet, msg);
 478         if (ret) {
 479                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 480                 return ret;
 481         }
 482
 483         dw_mipi_message_config(dsi, msg);
 484         if (dsi->slave)
 485                 dw_mipi_message_config(dsi->slave, msg);
 486
 487         ret = dw_mipi_dsi_write(dsi, &packet);
 488         if (ret)
 489                 return ret;
 490         if (dsi->slave) {
 491                 ret = dw_mipi_dsi_write(dsi->slave, &packet);
 492                 if (ret)
 493                         return ret;
 494         }
 495
 496         if (msg->rx_buf && msg->rx_len) {
 497                 ret = dw_mipi_dsi_read(dsi, msg);
 498                 if (ret)
 499                         return ret;
 500                 nb_bytes = msg->rx_len;
 501         } else {
 502                 nb_bytes = packet.size;
 503         }
 504
 505         return nb_bytes;
 506 }
 507
 508 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 509         .attach = dw_mipi_dsi_host_attach,
 510         .detach = dw_mipi_dsi_host_detach,
 511         .transfer = dw_mipi_dsi_host_transfer,
 512 };
 513
 514 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 515 {
 516         u32 val;
 517
 518         /*
 519          * TODO dw drv improvements
 520          * enabling low power is panel-dependent, we should use the
 521          * panel configuration here...
 522          */
 523         val = ENABLE_LOW_POWER;
 524
 525         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 526                 val |= VID_MODE_TYPE_BURST;
 527         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 528                 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
 529         else
 530                 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
 531
 532 #ifdef CONFIG_DEBUG_FS
 533         if (dsi->vpg) {
 534                 val |= VID_MODE_VPG_ENABLE;
 535                 val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
 536         }
 537 #endif /* CONFIG_DEBUG_FS */
 538
 539         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 540 }
 541
 542 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 543                                  unsigned long mode_flags)
 544 {
 545         dsi_write(dsi, DSI_PWR_UP, RESET);
 546
 547         if (mode_flags & MIPI_DSI_MODE_VIDEO) {
 548                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 549                 dw_mipi_dsi_video_mode_config(dsi);
 550                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 551         } else {
 552                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 553         }
 554
 555         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 556 }
 557
 558 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 559 {
 560         dsi_write(dsi, DSI_PWR_UP, RESET);
 561         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 562 }
 563
 564 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 565 {
 566         /*
 567          * The maximum permitted escape clock is 20MHz and it is derived from
 568          * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
 569          *
 570          *     (lane_mbps >> 3) / esc_clk_division < 20
 571          * which is:
 572          *     (lane_mbps >> 3) / 20 > esc_clk_division
 573          */
 574         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
 575
 576         dsi_write(dsi, DSI_PWR_UP, RESET);
 577
 578         /*
 579          * TODO dw drv improvements
 580          * timeout clock division should be computed with the
 581          * high speed transmission counter timeout and byte lane...
 582          */
 583         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
 584                   TX_ESC_CLK_DIVISION(esc_clk_division));
 585 }
 586
 587 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 588                                    const struct drm_display_mode *mode)
 589 {
 590         u32 val = 0, color = 0;
 591
 592         switch (dsi->format) {
 593         case MIPI_DSI_FMT_RGB888:
 594                 color = DPI_COLOR_CODING_24BIT;
 595                 break;
 596         case MIPI_DSI_FMT_RGB666:
 597                 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
 598                 break;
 599         case MIPI_DSI_FMT_RGB666_PACKED:
 600                 color = DPI_COLOR_CODING_18BIT_1;
 601                 break;
 602         case MIPI_DSI_FMT_RGB565:
 603                 color = DPI_COLOR_CODING_16BIT_1;
 604                 break;
 605         }
 606
 607         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 608                 val |= VSYNC_ACTIVE_LOW;
 609         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 610                 val |= HSYNC_ACTIVE_LOW;
 611
 612         dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
 613         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 614         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 615         /*
 616          * TODO dw drv improvements
 617          * largest packet sizes during hfp or during vsa/vpb/vfp
 618          * should be computed according to byte lane, lane number and only
 619          * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
 620          */
 621         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 622                   | INVACT_LPCMD_TIME(4));
 623 }
 624
 625 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 626 {
 627         dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
 628 }
 629
 630 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 631                                             const struct drm_display_mode *mode)
 632 {
 633         /*
 634          * TODO dw drv improvements
 635          * only burst mode is supported here. For non-burst video modes,
 636          * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
 637          * DSI_VNPCR.NPSIZE... especially because this driver supports
 638          * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
 639          */
 640
 641         dsi_write(dsi, DSI_VID_PKT_SIZE,
 642                        dw_mipi_is_dual_mode(dsi) ?
 643                                 VID_PKT_SIZE(mode->hdisplay / 2) :
 644                                 VID_PKT_SIZE(mode->hdisplay));
 645 }
 646
 647 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 648 {
 649         /*
 650          * TODO dw drv improvements
 651          * compute high speed transmission counter timeout according
 652          * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
 653          */
 654         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 655         /*
 656          * TODO dw drv improvements
 657          * the Bus-Turn-Around Timeout Counter should be computed
 658          * according to byte lane...
 659          */
 660         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 661         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 662 }
 663
 664 /* Get lane byte clock cycles. */
 665 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 666                                            const struct drm_display_mode *mode,
 667                                            u32 hcomponent)
 668 {
 669         u32 frac, lbcc;
 670
 671         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 672
 673         frac = lbcc % mode->clock;
 674         lbcc = lbcc / mode->clock;
 675         if (frac)
 676                 lbcc++;
 677
 678         return lbcc;
 679 }
 680
 681 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 682                                           const struct drm_display_mode *mode)
 683 {
 684         u32 htotal, hsa, hbp, lbcc;
 685
 686         htotal = mode->htotal;
 687         hsa = mode->hsync_end - mode->hsync_start;
 688         hbp = mode->htotal - mode->hsync_end;
 689
 690         /*
 691          * TODO dw drv improvements
 692          * computations below may be improved...
 693          */
 694         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
 695         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 696
 697         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
 698         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 699
 700         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
 701         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 702 }
 703
 704 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 705                                         const struct drm_display_mode *mode)
 706 {
 707         u32 vactive, vsa, vfp, vbp;
 708
 709         vactive = mode->vdisplay;
 710         vsa = mode->vsync_end - mode->vsync_start;
 711         vfp = mode->vsync_start - mode->vdisplay;
 712         vbp = mode->vtotal - mode->vsync_end;
 713
 714         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 715         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 716         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 717         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 718 }
 719
 720 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 721 {
 722         u32 hw_version;
 723
 724         /*
 725          * TODO dw drv improvements
 726          * data & clock lane timers should be computed according to panel
 727          * blankings and to the automatic clock lane control mode...
 728          * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
 729          * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
 730          */
 731
 732         hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
 733
 734         if (hw_version >= HWVER_131) {
 735                 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
 736                           PHY_LP2HS_TIME_V131(0x40));
 737                 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
 738         } else {
 739                 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
 740                           PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 741         }
 742
 743         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 744                   | PHY_CLKLP2HS_TIME(0x40));
 745 }
 746
 747 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 748 {
 749         /*
 750          * TODO dw drv improvements
 751          * stop wait time should be the maximum between host dsi
 752          * and panel stop wait times
 753          */
 754         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 755                   N_LANES(dsi->lanes));
 756 }
 757
 758 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
 759 {
 760         /* Clear PHY state */
 761         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 762                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 763         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 764         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
 765         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 766 }
 767
 768 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 769 {
 770         u32 val;
 771         int ret;
 772
 773         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 774                   PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 775
 776         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
 777                                  val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 778         if (ret)
 779                 DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
 780
 781         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 782                                  val, val & PHY_STOP_STATE_CLK_LANE, 1000,
 783                                  PHY_STATUS_TIMEOUT_US);
 784         if (ret)
 785                 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
 786 }
 787
 788 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 789 {
 790         dsi_read(dsi, DSI_INT_ST0);
 791         dsi_read(dsi, DSI_INT_ST1);
 792         dsi_write(dsi, DSI_INT_MSK0, 0);
 793         dsi_write(dsi, DSI_INT_MSK1, 0);
 794 }
 795
 796 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
 797 {
 798         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 799         const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 800
 801         if (phy_ops->power_off)
 802                 phy_ops->power_off(dsi->plat_data->priv_data);
 803
 804         /*
 805          * Switch to command mode before panel-bridge post_disable &
 806          * panel unprepare.
 807          * Note: panel-bridge disable & panel disable has been called
 808          * before by the drm framework.
 809          */
 810         dw_mipi_dsi_set_mode(dsi, 0);
 811
 812         /*
 813          * TODO Only way found to call panel-bridge post_disable &
 814          * panel unprepare before the dsi "final" disable...
 815          * This needs to be fixed in the drm_bridge framework and the API
 816          * needs to be updated to manage our own call chains...
 817          */
 818         dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
 819
 820         if (dsi->slave) {
 821                 dw_mipi_dsi_disable(dsi->slave);
 822                 clk_disable_unprepare(dsi->slave->pclk);
 823                 pm_runtime_put(dsi->slave->dev);
 824         }
 825         dw_mipi_dsi_disable(dsi);
 826
 827         clk_disable_unprepare(dsi->pclk);
 828         pm_runtime_put(dsi->dev);
 829 }
 830
 831 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
 832 {
 833         /* this instance is the slave, so add the master's lanes */
 834         if (dsi->master)
 835                 return dsi->master->lanes + dsi->lanes;
 836
 837         /* this instance is the master, so add the slave's lanes */
 838         if (dsi->slave)
 839                 return dsi->lanes + dsi->slave->lanes;
 840
 841         /* single-dsi, so no other instance to consider */
 842         return dsi->lanes;
 843 }
 844
 845 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
 846                                  const struct drm_display_mode *adjusted_mode)
 847 {
 848         const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 849         void *priv_data = dsi->plat_data->priv_data;
 850         int ret;
 851         u32 lanes = dw_mipi_dsi_get_lanes(dsi);
 852
 853         clk_prepare_enable(dsi->pclk);
 854
 855         ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
 856                                      lanes, dsi->format, &dsi->lane_mbps);
 857         if (ret)
 858                 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
 859
 860         pm_runtime_get_sync(dsi->dev);
 861         dw_mipi_dsi_init(dsi);
 862         dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
 863         dw_mipi_dsi_packet_handler_config(dsi);
 864         dw_mipi_dsi_video_mode_config(dsi);
 865         dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
 866         dw_mipi_dsi_command_mode_config(dsi);
 867         dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
 868         dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
 869
 870         dw_mipi_dsi_dphy_init(dsi);
 871         dw_mipi_dsi_dphy_timing_config(dsi);
 872         dw_mipi_dsi_dphy_interface_config(dsi);
 873
 874         dw_mipi_dsi_clear_err(dsi);
 875
 876         ret = phy_ops->init(priv_data);
 877         if (ret)
 878                 DRM_DEBUG_DRIVER("Phy init() failed\n");
 879
 880         dw_mipi_dsi_dphy_enable(dsi);
 881
 882         dw_mipi_dsi_wait_for_two_frames(adjusted_mode);
 883
 884         /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
 885         dw_mipi_dsi_set_mode(dsi, 0);
 886 }
 887
 888 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
 889                                         const struct drm_display_mode *mode,
 890                                         const struct drm_display_mode *adjusted_mode)
 891 {
 892         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 893
 894         dw_mipi_dsi_mode_set(dsi, adjusted_mode);
 895         if (dsi->slave)
 896                 dw_mipi_dsi_mode_set(dsi->slave, adjusted_mode);
 897 }
 898
 899 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
 900 {
 901         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 902         const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 903
 904         /* Switch to video mode for panel-bridge enable & panel enable */
 905         dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
 906         if (dsi->slave)
 907                 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);
 908
 909         if (phy_ops->power_on)
 910                 phy_ops->power_on(dsi->plat_data->priv_data);
 911 }
 912
 913 static enum drm_mode_status
 914 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
 915                               const struct drm_display_mode *mode)
 916 {
 917         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 918         const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
 919         enum drm_mode_status mode_status = MODE_OK;
 920
 921         if (pdata->mode_valid)
 922                 mode_status = pdata->mode_valid(pdata->priv_data, mode);
 923
 924         return mode_status;
 925 }
 926
 927 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
 928 {
 929         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 930
 931         if (!bridge->encoder) {
 932                 DRM_ERROR("Parent encoder object not found\n");
 933                 return -ENODEV;
 934         }
 935
 936         /* Set the encoder type as caller does not know it */
 937         bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
 938
 939         /* Attach the panel-bridge to the dsi bridge */
 940         return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
 941 }
 942
 943 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
 944         .mode_set     = dw_mipi_dsi_bridge_mode_set,
 945         .enable       = dw_mipi_dsi_bridge_enable,
 946         .post_disable = dw_mipi_dsi_bridge_post_disable,
 947         .mode_valid   = dw_mipi_dsi_bridge_mode_valid,
 948         .attach       = dw_mipi_dsi_bridge_attach,
 949 };
 950
 951 #ifdef CONFIG_DEBUG_FS
 952
 953 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
 954 {
 955         dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
 956         if (IS_ERR(dsi->debugfs)) {
 957                 dev_err(dsi->dev, "failed to create debugfs root\n");
 958                 return;
 959         }
 960
 961         debugfs_create_bool("vpg", 0660, dsi->debugfs, &dsi->vpg);
 962         debugfs_create_bool("vpg_horizontal", 0660, dsi->debugfs,
 963                             &dsi->vpg_horizontal);
 964 }
 965
 966 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
 967 {
 968         debugfs_remove_recursive(dsi->debugfs);
 969 }
 970
 971 #else
 972
 973 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
 974 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
 975
 976 #endif /* CONFIG_DEBUG_FS */
 977
 978 static struct dw_mipi_dsi *
 979 __dw_mipi_dsi_probe(struct platform_device *pdev,
 980                     const struct dw_mipi_dsi_plat_data *plat_data)
 981 {
 982         struct device *dev = &pdev->dev;
 983         struct reset_control *apb_rst;
 984         struct dw_mipi_dsi *dsi;
 985         int ret;
 986
 987         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
 988         if (!dsi)
 989                 return ERR_PTR(-ENOMEM);
 990
 991         dsi->dev = dev;
 992         dsi->plat_data = plat_data;
 993
 994         if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
 995                 DRM_ERROR("Phy not properly configured\n");
 996                 return ERR_PTR(-ENODEV);
 997         }
 998
 999         if (!plat_data->base) {
1000                 dsi->base = devm_platform_ioremap_resource(pdev, 0);
1001                 if (IS_ERR(dsi->base))
1002                         return ERR_PTR(-ENODEV);
1003
1004         } else {
1005                 dsi->base = plat_data->base;
1006         }
1007
1008         dsi->pclk = devm_clk_get(dev, "pclk");
1009         if (IS_ERR(dsi->pclk)) {
1010                 ret = PTR_ERR(dsi->pclk);
1011                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1012                 return ERR_PTR(ret);
1013         }
1014
1015         /*
1016          * Note that the reset was not defined in the initial device tree, so
1017          * we have to be prepared for it not being found.
1018          */
1019         apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
1020         if (IS_ERR(apb_rst)) {
1021                 ret = PTR_ERR(apb_rst);
1022
1023                 if (ret != -EPROBE_DEFER)
1024                         dev_err(dev, "Unable to get reset control: %d\n", ret);
1025
1026                 return ERR_PTR(ret);
1027         }
1028
1029         if (apb_rst) {
1030                 ret = clk_prepare_enable(dsi->pclk);
1031                 if (ret) {
1032                         dev_err(dev, "%s: Failed to enable pclk\n", __func__);
1033                         return ERR_PTR(ret);
1034                 }
1035
1036                 reset_control_assert(apb_rst);
1037                 usleep_range(10, 20);
1038                 reset_control_deassert(apb_rst);
1039
1040                 clk_disable_unprepare(dsi->pclk);
1041         }
1042
1043         dw_mipi_dsi_debugfs_init(dsi);
1044         pm_runtime_enable(dev);
1045
1046         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1047         dsi->dsi_host.dev = dev;
1048         ret = mipi_dsi_host_register(&dsi->dsi_host);
1049         if (ret) {
1050                 dev_err(dev, "Failed to register MIPI host: %d\n", ret);
1051                 dw_mipi_dsi_debugfs_remove(dsi);
1052                 return ERR_PTR(ret);
1053         }
1054
1055         dsi->bridge.driver_private = dsi;
1056         dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
1057 #ifdef CONFIG_OF
1058         dsi->bridge.of_node = pdev->dev.of_node;
1059 #endif
1060
1061         return dsi;
1062 }
1063
1064 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1065 {
1066         mipi_dsi_host_unregister(&dsi->dsi_host);
1067
1068         pm_runtime_disable(dsi->dev);
1069         dw_mipi_dsi_debugfs_remove(dsi);
1070 }
1071
1072 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave)
1073 {
1074         /* introduce controllers to each other */
1075         dsi->slave = slave;
1076         dsi->slave->master = dsi;
1077
1078         /* migrate settings for already attached displays */
1079         dsi->slave->lanes = dsi->lanes;
1080         dsi->slave->channel = dsi->channel;
1081         dsi->slave->format = dsi->format;
1082         dsi->slave->mode_flags = dsi->mode_flags;
1083 }
1084 EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave);
1085
1086 /*
1087  * Probe/remove API, used from platforms based on the DRM bridge API.
1088  */
1089 struct dw_mipi_dsi *
1090 dw_mipi_dsi_probe(struct platform_device *pdev,
1091                   const struct dw_mipi_dsi_plat_data *plat_data)
1092 {
1093         return __dw_mipi_dsi_probe(pdev, plat_data);
1094 }
1095 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
1096
1097 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1098 {
1099         __dw_mipi_dsi_remove(dsi);
1100 }
1101 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
1102
1103 /*
1104  * Bind/unbind API, used from platforms based on the component framework.
1105  */
1106 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
1107 {
1108         int ret;
1109
1110         ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
1111         if (ret) {
1112                 DRM_ERROR("Failed to initialize bridge with drm\n");
1113                 return ret;
1114         }
1115
1116         return ret;
1117 }
1118 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
1119
1120 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
1121 {
1122 }
1123 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
1124
1125 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1126 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1127 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
1128 MODULE_LICENSE("GPL");
1129 MODULE_ALIAS("platform:dw-mipi-dsi");