drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   4  *
   5  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   6  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   7  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/hdmi.h>
  13 #include <linux/irq.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pinctrl/consumer.h>
  18 #include <linux/regmap.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/spinlock.h>
  21
  22 #include <media/cec-notifier.h>
  23
  24 #include <uapi/linux/media-bus-format.h>
  25 #include <uapi/linux/videodev2.h>
  26
  27 #include <drm/bridge/dw_hdmi.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_bridge.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/drm_of.h>
  33 #include <drm/drm_print.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/drm_scdc_helper.h>
  36
  37 #include "dw-hdmi-audio.h"
  38 #include "dw-hdmi-cec.h"
  39 #include "dw-hdmi.h"
  40
  41 #define DDC_SEGMENT_ADDR        0x30
  42
  43 #define HDMI_EDID_LEN           512
  44
  45 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
  46 #define SCDC_MIN_SOURCE_VERSION 0x1
  47
  48 #define HDMI14_MAX_TMDSCLK      340000000
  49
  50 enum hdmi_datamap {
  51         RGB444_8B = 0x01,
  52         RGB444_10B = 0x03,
  53         RGB444_12B = 0x05,
  54         RGB444_16B = 0x07,
  55         YCbCr444_8B = 0x09,
  56         YCbCr444_10B = 0x0B,
  57         YCbCr444_12B = 0x0D,
  58         YCbCr444_16B = 0x0F,
  59         YCbCr422_8B = 0x16,
  60         YCbCr422_10B = 0x14,
  61         YCbCr422_12B = 0x12,
  62 };
  63
  64 static const u16 csc_coeff_default[3][4] = {
  65         { 0x2000, 0x0000, 0x0000, 0x0000 },
  66         { 0x0000, 0x2000, 0x0000, 0x0000 },
  67         { 0x0000, 0x0000, 0x2000, 0x0000 }
  68 };
  69
  70 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  71         { 0x2000, 0x6926, 0x74fd, 0x010e },
  72         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  73         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  74 };
  75
  76 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  77         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  78         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  79         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  80 };
  81
  82 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  83         { 0x2591, 0x1322, 0x074b, 0x0000 },
  84         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  85         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  86 };
  87
  88 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  89         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  90         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  91         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  92 };
  93
  94 struct hdmi_vmode {
  95         bool mdataenablepolarity;
  96
  97         unsigned int mpixelclock;
  98         unsigned int mpixelrepetitioninput;
  99         unsigned int mpixelrepetitionoutput;
 100         unsigned int mtmdsclock;
 101 };
 102
 103 struct hdmi_data_info {
 104         unsigned int enc_in_bus_format;
 105         unsigned int enc_out_bus_format;
 106         unsigned int enc_in_encoding;
 107         unsigned int enc_out_encoding;
 108         unsigned int pix_repet_factor;
 109         unsigned int hdcp_enable;
 110         struct hdmi_vmode video_mode;
 111 };
 112
 113 struct dw_hdmi_i2c {
 114         struct i2c_adapter      adap;
 115
 116         struct mutex            lock;   /* used to serialize data transfers */
 117         struct completion       cmp;
 118         u8                      stat;
 119
 120         u8                      slave_reg;
 121         bool                    is_regaddr;
 122         bool                    is_segment;
 123 };
 124
 125 struct dw_hdmi_phy_data {
 126         enum dw_hdmi_phy_type type;
 127         const char *name;
 128         unsigned int gen;
 129         bool has_svsret;
 130         int (*configure)(struct dw_hdmi *hdmi,
 131                          const struct dw_hdmi_plat_data *pdata,
 132                          unsigned long mpixelclock);
 133 };
 134
 135 struct dw_hdmi {
 136         struct drm_connector connector;
 137         struct drm_bridge bridge;
 138
 139         unsigned int version;
 140
 141         struct platform_device *audio;
 142         struct platform_device *cec;
 143         struct device *dev;
 144         struct clk *isfr_clk;
 145         struct clk *iahb_clk;
 146         struct clk *cec_clk;
 147         struct dw_hdmi_i2c *i2c;
 148
 149         struct hdmi_data_info hdmi_data;
 150         const struct dw_hdmi_plat_data *plat_data;
 151
 152         int vic;
 153
 154         u8 edid[HDMI_EDID_LEN];
 155
 156         struct {
 157                 const struct dw_hdmi_phy_ops *ops;
 158                 const char *name;
 159                 void *data;
 160                 bool enabled;
 161         } phy;
 162
 163         struct drm_display_mode previous_mode;
 164
 165         struct i2c_adapter *ddc;
 166         void __iomem *regs;
 167         bool sink_is_hdmi;
 168         bool sink_has_audio;
 169
 170         struct pinctrl *pinctrl;
 171         struct pinctrl_state *default_state;
 172         struct pinctrl_state *unwedge_state;
 173
 174         struct mutex mutex;             /* for state below and previous_mode */
 175         enum drm_connector_force force; /* mutex-protected force state */
 176         bool disabled;                  /* DRM has disabled our bridge */
 177         bool bridge_is_on;              /* indicates the bridge is on */
 178         bool rxsense;                   /* rxsense state */
 179         u8 phy_mask;                    /* desired phy int mask settings */
 180         u8 mc_clkdis;                   /* clock disable register */
 181
 182         spinlock_t audio_lock;
 183         struct mutex audio_mutex;
 184         unsigned int sample_rate;
 185         unsigned int audio_cts;
 186         unsigned int audio_n;
 187         bool audio_enable;
 188
 189         unsigned int reg_shift;
 190         struct regmap *regm;
 191         void (*enable_audio)(struct dw_hdmi *hdmi);
 192         void (*disable_audio)(struct dw_hdmi *hdmi);
 193
 194         struct mutex cec_notifier_mutex;
 195         struct cec_notifier *cec_notifier;
 196 };
 197
 198 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 199         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 200          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 201
 202 #define HDMI_PHY_RX_SENSE \
 203         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 204          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 205
 206 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 207 {
 208         regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
 209 }
 210
 211 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 212 {
 213         unsigned int val = 0;
 214
 215         regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
 216
 217         return val;
 218 }
 219
 220 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 221 {
 222         regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
 223 }
 224
 225 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 226                              u8 shift, u8 mask)
 227 {
 228         hdmi_modb(hdmi, data << shift, mask, reg);
 229 }
 230
 231 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 232 {
 233         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
 234                     HDMI_PHY_I2CM_INT_ADDR);
 235
 236         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
 237                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
 238                     HDMI_PHY_I2CM_CTLINT_ADDR);
 239
 240         /* Software reset */
 241         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 242
 243         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
 244         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
 245
 246         /* Set done, not acknowledged and arbitration interrupt polarities */
 247         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 248         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 249                     HDMI_I2CM_CTLINT);
 250
 251         /* Clear DONE and ERROR interrupts */
 252         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 253                     HDMI_IH_I2CM_STAT0);
 254
 255         /* Mute DONE and ERROR interrupts */
 256         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 257                     HDMI_IH_MUTE_I2CM_STAT0);
 258 }
 259
 260 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
 261 {
 262         /* If no unwedge state then give up */
 263         if (!hdmi->unwedge_state)
 264                 return false;
 265
 266         dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
 267
 268         /*
 269          * This is a huge hack to workaround a problem where the dw_hdmi i2c
 270          * bus could sometimes get wedged.  Once wedged there doesn't appear
 271          * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
 272          * other than pulsing the SDA line.
 273          *
 274          * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
 275          * by:
 276          * 1. Remux the pin as a GPIO output, driven low.
 277          * 2. Wait a little while.  1 ms seems to work, but we'll do 10.
 278          * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
 279          *
 280          * At the moment of remuxing, the line will still be low due to its
 281          * recent stint as an output, but then it will be pulled high by the
 282          * (presumed) external pullup.  dw_hdmi seems to see this as a rising
 283          * edge and that seems to get it out of its jam.
 284          *
 285          * This wedging was only ever seen on one TV, and only on one of
 286          * its HDMI ports.  It happened when the TV was powered on while the
 287          * device was plugged in.  A scope trace shows the TV bringing both SDA
 288          * and SCL low, then bringing them both back up at roughly the same
 289          * time.  Presumably this confuses dw_hdmi because it saw activity but
 290          * no real STOP (maybe it thinks there's another master on the bus?).
 291          * Giving it a clean rising edge of SDA while SCL is already high
 292          * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
 293          * of its stupor.
 294          *
 295          * Note that after coming back alive, transfers seem to immediately
 296          * resume, so if we unwedge due to a timeout we should wait a little
 297          * longer for our transfer to finish, since it might have just started
 298          * now.
 299          */
 300         pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
 301         msleep(10);
 302         pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
 303
 304         return true;
 305 }
 306
 307 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
 308 {
 309         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 310         int stat;
 311
 312         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 313         if (!stat) {
 314                 /* If we can't unwedge, return timeout */
 315                 if (!dw_hdmi_i2c_unwedge(hdmi))
 316                         return -EAGAIN;
 317
 318                 /* We tried to unwedge; give it another chance */
 319                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 320                 if (!stat)
 321                         return -EAGAIN;
 322         }
 323
 324         /* Check for error condition on the bus */
 325         if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 326                 return -EIO;
 327
 328         return 0;
 329 }
 330
 331 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 332                             unsigned char *buf, unsigned int length)
 333 {
 334         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 335         int ret;
 336
 337         if (!i2c->is_regaddr) {
 338                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 339                 i2c->slave_reg = 0x00;
 340                 i2c->is_regaddr = true;
 341         }
 342
 343         while (length--) {
 344                 reinit_completion(&i2c->cmp);
 345
 346                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 347                 if (i2c->is_segment)
 348                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 349                                     HDMI_I2CM_OPERATION);
 350                 else
 351                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 352                                     HDMI_I2CM_OPERATION);
 353
 354                 ret = dw_hdmi_i2c_wait(hdmi);
 355                 if (ret)
 356                         return ret;
 357
 358                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 359         }
 360         i2c->is_segment = false;
 361
 362         return 0;
 363 }
 364
 365 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 366                              unsigned char *buf, unsigned int length)
 367 {
 368         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 369         int ret;
 370
 371         if (!i2c->is_regaddr) {
 372                 /* Use the first write byte as register address */
 373                 i2c->slave_reg = buf[0];
 374                 length--;
 375                 buf++;
 376                 i2c->is_regaddr = true;
 377         }
 378
 379         while (length--) {
 380                 reinit_completion(&i2c->cmp);
 381
 382                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 383                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 384                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 385                             HDMI_I2CM_OPERATION);
 386
 387                 ret = dw_hdmi_i2c_wait(hdmi);
 388                 if (ret)
 389                         return ret;
 390         }
 391
 392         return 0;
 393 }
 394
 395 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 396                             struct i2c_msg *msgs, int num)
 397 {
 398         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 399         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 400         u8 addr = msgs[0].addr;
 401         int i, ret = 0;
 402
 403         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 404
 405         for (i = 0; i < num; i++) {
 406                 if (msgs[i].len == 0) {
 407                         dev_dbg(hdmi->dev,
 408                                 "unsupported transfer %d/%d, no data\n",
 409                                 i + 1, num);
 410                         return -EOPNOTSUPP;
 411                 }
 412         }
 413
 414         mutex_lock(&i2c->lock);
 415
 416         /* Unmute DONE and ERROR interrupts */
 417         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 418
 419         /* Set slave device address taken from the first I2C message */
 420         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 421
 422         /* Set slave device register address on transfer */
 423         i2c->is_regaddr = false;
 424
 425         /* Set segment pointer for I2C extended read mode operation */
 426         i2c->is_segment = false;
 427
 428         for (i = 0; i < num; i++) {
 429                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 430                         i + 1, num, msgs[i].len, msgs[i].flags);
 431                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 432                         i2c->is_segment = true;
 433                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 434                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 435                 } else {
 436                         if (msgs[i].flags & I2C_M_RD)
 437                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 438                                                        msgs[i].len);
 439                         else
 440                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 441                                                         msgs[i].len);
 442                 }
 443                 if (ret < 0)
 444                         break;
 445         }
 446
 447         if (!ret)
 448                 ret = num;
 449
 450         /* Mute DONE and ERROR interrupts */
 451         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 452                     HDMI_IH_MUTE_I2CM_STAT0);
 453
 454         mutex_unlock(&i2c->lock);
 455
 456         return ret;
 457 }
 458
 459 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 460 {
 461         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 462 }
 463
 464 static const struct i2c_algorithm dw_hdmi_algorithm = {
 465         .master_xfer    = dw_hdmi_i2c_xfer,
 466         .functionality  = dw_hdmi_i2c_func,
 467 };
 468
 469 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 470 {
 471         struct i2c_adapter *adap;
 472         struct dw_hdmi_i2c *i2c;
 473         int ret;
 474
 475         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 476         if (!i2c)
 477                 return ERR_PTR(-ENOMEM);
 478
 479         mutex_init(&i2c->lock);
 480         init_completion(&i2c->cmp);
 481
 482         adap = &i2c->adap;
 483         adap->class = I2C_CLASS_DDC;
 484         adap->owner = THIS_MODULE;
 485         adap->dev.parent = hdmi->dev;
 486         adap->algo = &dw_hdmi_algorithm;
 487         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 488         i2c_set_adapdata(adap, hdmi);
 489
 490         ret = i2c_add_adapter(adap);
 491         if (ret) {
 492                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 493                 devm_kfree(hdmi->dev, i2c);
 494                 return ERR_PTR(ret);
 495         }
 496
 497         hdmi->i2c = i2c;
 498
 499         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 500
 501         return adap;
 502 }
 503
 504 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 505                            unsigned int n)
 506 {
 507         /* Must be set/cleared first */
 508         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 509
 510         /* nshift factor = 0 */
 511         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 512
 513         /* Use automatic CTS generation mode when CTS is not set */
 514         if (cts)
 515                 hdmi_writeb(hdmi, ((cts >> 16) &
 516                                    HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 517                                   HDMI_AUD_CTS3_CTS_MANUAL,
 518                             HDMI_AUD_CTS3);
 519         else
 520                 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
 521         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 522         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 523
 524         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 525         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 526         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 527 }
 528
 529 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 530 {
 531         unsigned int n = (128 * freq) / 1000;
 532         unsigned int mult = 1;
 533
 534         while (freq > 48000) {
 535                 mult *= 2;
 536                 freq /= 2;
 537         }
 538
 539         switch (freq) {
 540         case 32000:
 541                 if (pixel_clk == 25175000)
 542                         n = 4576;
 543                 else if (pixel_clk == 27027000)
 544                         n = 4096;
 545                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 546                         n = 11648;
 547                 else
 548                         n = 4096;
 549                 n *= mult;
 550                 break;
 551
 552         case 44100:
 553                 if (pixel_clk == 25175000)
 554                         n = 7007;
 555                 else if (pixel_clk == 74176000)
 556                         n = 17836;
 557                 else if (pixel_clk == 148352000)
 558                         n = 8918;
 559                 else
 560                         n = 6272;
 561                 n *= mult;
 562                 break;
 563
 564         case 48000:
 565                 if (pixel_clk == 25175000)
 566                         n = 6864;
 567                 else if (pixel_clk == 27027000)
 568                         n = 6144;
 569                 else if (pixel_clk == 74176000)
 570                         n = 11648;
 571                 else if (pixel_clk == 148352000)
 572                         n = 5824;
 573                 else
 574                         n = 6144;
 575                 n *= mult;
 576                 break;
 577
 578         default:
 579                 break;
 580         }
 581
 582         return n;
 583 }
 584
 585 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 586         unsigned long pixel_clk, unsigned int sample_rate)
 587 {
 588         unsigned long ftdms = pixel_clk;
 589         unsigned int n, cts;
 590         u8 config3;
 591         u64 tmp;
 592
 593         n = hdmi_compute_n(sample_rate, pixel_clk);
 594
 595         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
 596
 597         /* Only compute CTS when using internal AHB audio */
 598         if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
 599                 /*
 600                  * Compute the CTS value from the N value.  Note that CTS and N
 601                  * can be up to 20 bits in total, so we need 64-bit math.  Also
 602                  * note that our TDMS clock is not fully accurate; it is
 603                  * accurate to kHz.  This can introduce an unnecessary remainder
 604                  * in the calculation below, so we don't try to warn about that.
 605                  */
 606                 tmp = (u64)ftdms * n;
 607                 do_div(tmp, 128 * sample_rate);
 608                 cts = tmp;
 609
 610                 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 611                         __func__, sample_rate,
 612                         ftdms / 1000000, (ftdms / 1000) % 1000,
 613                         n, cts);
 614         } else {
 615                 cts = 0;
 616         }
 617
 618         spin_lock_irq(&hdmi->audio_lock);
 619         hdmi->audio_n = n;
 620         hdmi->audio_cts = cts;
 621         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 622         spin_unlock_irq(&hdmi->audio_lock);
 623 }
 624
 625 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 626 {
 627         mutex_lock(&hdmi->audio_mutex);
 628         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 629         mutex_unlock(&hdmi->audio_mutex);
 630 }
 631
 632 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 633 {
 634         mutex_lock(&hdmi->audio_mutex);
 635         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
 636                                  hdmi->sample_rate);
 637         mutex_unlock(&hdmi->audio_mutex);
 638 }
 639
 640 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 641 {
 642         mutex_lock(&hdmi->audio_mutex);
 643         hdmi->sample_rate = rate;
 644         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
 645                                  hdmi->sample_rate);
 646         mutex_unlock(&hdmi->audio_mutex);
 647 }
 648 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 649
 650 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
 651 {
 652         u8 layout;
 653
 654         mutex_lock(&hdmi->audio_mutex);
 655
 656         /*
 657          * For >2 channel PCM audio, we need to select layout 1
 658          * and set an appropriate channel map.
 659          */
 660         if (cnt > 2)
 661                 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
 662         else
 663                 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
 664
 665         hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
 666                   HDMI_FC_AUDSCONF);
 667
 668         /* Set the audio infoframes channel count */
 669         hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
 670                   HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
 671
 672         mutex_unlock(&hdmi->audio_mutex);
 673 }
 674 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
 675
 676 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
 677 {
 678         mutex_lock(&hdmi->audio_mutex);
 679
 680         hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
 681
 682         mutex_unlock(&hdmi->audio_mutex);
 683 }
 684 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
 685
 686 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
 687 {
 688         if (enable)
 689                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 690         else
 691                 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 692         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
 693 }
 694
 695 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
 696 {
 697         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 698 }
 699
 700 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
 701 {
 702         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 703 }
 704
 705 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
 706 {
 707         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 708         hdmi_enable_audio_clk(hdmi, true);
 709 }
 710
 711 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
 712 {
 713         hdmi_enable_audio_clk(hdmi, false);
 714 }
 715
 716 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 717 {
 718         unsigned long flags;
 719
 720         spin_lock_irqsave(&hdmi->audio_lock, flags);
 721         hdmi->audio_enable = true;
 722         if (hdmi->enable_audio)
 723                 hdmi->enable_audio(hdmi);
 724         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 725 }
 726 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 727
 728 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 729 {
 730         unsigned long flags;
 731
 732         spin_lock_irqsave(&hdmi->audio_lock, flags);
 733         hdmi->audio_enable = false;
 734         if (hdmi->disable_audio)
 735                 hdmi->disable_audio(hdmi);
 736         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 737 }
 738 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 739
 740 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
 741 {
 742         switch (bus_format) {
 743         case MEDIA_BUS_FMT_RGB888_1X24:
 744         case MEDIA_BUS_FMT_RGB101010_1X30:
 745         case MEDIA_BUS_FMT_RGB121212_1X36:
 746         case MEDIA_BUS_FMT_RGB161616_1X48:
 747                 return true;
 748
 749         default:
 750                 return false;
 751         }
 752 }
 753
 754 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
 755 {
 756         switch (bus_format) {
 757         case MEDIA_BUS_FMT_YUV8_1X24:
 758         case MEDIA_BUS_FMT_YUV10_1X30:
 759         case MEDIA_BUS_FMT_YUV12_1X36:
 760         case MEDIA_BUS_FMT_YUV16_1X48:
 761                 return true;
 762
 763         default:
 764                 return false;
 765         }
 766 }
 767
 768 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
 769 {
 770         switch (bus_format) {
 771         case MEDIA_BUS_FMT_UYVY8_1X16:
 772         case MEDIA_BUS_FMT_UYVY10_1X20:
 773         case MEDIA_BUS_FMT_UYVY12_1X24:
 774                 return true;
 775
 776         default:
 777                 return false;
 778         }
 779 }
 780
 781 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
 782 {
 783         switch (bus_format) {
 784         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 785         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 786         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 787         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 788                 return true;
 789
 790         default:
 791                 return false;
 792         }
 793 }
 794
 795 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
 796 {
 797         switch (bus_format) {
 798         case MEDIA_BUS_FMT_RGB888_1X24:
 799         case MEDIA_BUS_FMT_YUV8_1X24:
 800         case MEDIA_BUS_FMT_UYVY8_1X16:
 801         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 802                 return 8;
 803
 804         case MEDIA_BUS_FMT_RGB101010_1X30:
 805         case MEDIA_BUS_FMT_YUV10_1X30:
 806         case MEDIA_BUS_FMT_UYVY10_1X20:
 807         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 808                 return 10;
 809
 810         case MEDIA_BUS_FMT_RGB121212_1X36:
 811         case MEDIA_BUS_FMT_YUV12_1X36:
 812         case MEDIA_BUS_FMT_UYVY12_1X24:
 813         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 814                 return 12;
 815
 816         case MEDIA_BUS_FMT_RGB161616_1X48:
 817         case MEDIA_BUS_FMT_YUV16_1X48:
 818         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 819                 return 16;
 820
 821         default:
 822                 return 0;
 823         }
 824 }
 825
 826 /*
 827  * this submodule is responsible for the video data synchronization.
 828  * for example, for RGB 4:4:4 input, the data map is defined as
 829  *                      pin{47~40} <==> R[7:0]
 830  *                      pin{31~24} <==> G[7:0]
 831  *                      pin{15~8}  <==> B[7:0]
 832  */
 833 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 834 {
 835         int color_format = 0;
 836         u8 val;
 837
 838         switch (hdmi->hdmi_data.enc_in_bus_format) {
 839         case MEDIA_BUS_FMT_RGB888_1X24:
 840                 color_format = 0x01;
 841                 break;
 842         case MEDIA_BUS_FMT_RGB101010_1X30:
 843                 color_format = 0x03;
 844                 break;
 845         case MEDIA_BUS_FMT_RGB121212_1X36:
 846                 color_format = 0x05;
 847                 break;
 848         case MEDIA_BUS_FMT_RGB161616_1X48:
 849                 color_format = 0x07;
 850                 break;
 851
 852         case MEDIA_BUS_FMT_YUV8_1X24:
 853         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 854                 color_format = 0x09;
 855                 break;
 856         case MEDIA_BUS_FMT_YUV10_1X30:
 857         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 858                 color_format = 0x0B;
 859                 break;
 860         case MEDIA_BUS_FMT_YUV12_1X36:
 861         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 862                 color_format = 0x0D;
 863                 break;
 864         case MEDIA_BUS_FMT_YUV16_1X48:
 865         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 866                 color_format = 0x0F;
 867                 break;
 868
 869         case MEDIA_BUS_FMT_UYVY8_1X16:
 870                 color_format = 0x16;
 871                 break;
 872         case MEDIA_BUS_FMT_UYVY10_1X20:
 873                 color_format = 0x14;
 874                 break;
 875         case MEDIA_BUS_FMT_UYVY12_1X24:
 876                 color_format = 0x12;
 877                 break;
 878
 879         default:
 880                 return;
 881         }
 882
 883         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 884                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 885                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 886         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 887
 888         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 889         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 890                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 891                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 892         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 893         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 894         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 895         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 896         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 897         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 898         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 899 }
 900
 901 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 902 {
 903         return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
 904 }
 905
 906 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 907 {
 908         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
 909                 return 0;
 910
 911         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
 912             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
 913                 return 1;
 914
 915         return 0;
 916 }
 917
 918 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 919 {
 920         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
 921                 return 0;
 922
 923         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 924             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
 925                 return 1;
 926
 927         return 0;
 928 }
 929
 930 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 931 {
 932         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 933         unsigned i;
 934         u32 csc_scale = 1;
 935
 936         if (is_color_space_conversion(hdmi)) {
 937                 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
 938                         if (hdmi->hdmi_data.enc_out_encoding ==
 939                                                 V4L2_YCBCR_ENC_601)
 940                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 941                         else
 942                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 943                 } else if (hdmi_bus_fmt_is_rgb(
 944                                         hdmi->hdmi_data.enc_in_bus_format)) {
 945                         if (hdmi->hdmi_data.enc_out_encoding ==
 946                                                 V4L2_YCBCR_ENC_601)
 947                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 948                         else
 949                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 950                         csc_scale = 0;
 951                 }
 952         }
 953
 954         /* The CSC registers are sequential, alternating MSB then LSB */
 955         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 956                 u16 coeff_a = (*csc_coeff)[0][i];
 957                 u16 coeff_b = (*csc_coeff)[1][i];
 958                 u16 coeff_c = (*csc_coeff)[2][i];
 959
 960                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 961                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 962                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 963                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 964                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 965                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 966         }
 967
 968         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 969                   HDMI_CSC_SCALE);
 970 }
 971
 972 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 973 {
 974         int color_depth = 0;
 975         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 976         int decimation = 0;
 977
 978         /* YCC422 interpolation to 444 mode */
 979         if (is_color_space_interpolation(hdmi))
 980                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 981         else if (is_color_space_decimation(hdmi))
 982                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 983
 984         switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
 985         case 8:
 986                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 987                 break;
 988         case 10:
 989                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 990                 break;
 991         case 12:
 992                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 993                 break;
 994         case 16:
 995                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 996                 break;
 997
 998         default:
 999                 return;
1000         }
1001
1002         /* Configure the CSC registers */
1003         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1004         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1005                   HDMI_CSC_SCALE);
1006
1007         dw_hdmi_update_csc_coeffs(hdmi);
1008 }
1009
1010 /*
1011  * HDMI video packetizer is used to packetize the data.
1012  * for example, if input is YCC422 mode or repeater is used,
1013  * data should be repacked this module can be bypassed.
1014  */
1015 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1016 {
1017         unsigned int color_depth = 0;
1018         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1019         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1020         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1021         u8 val, vp_conf;
1022
1023         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1024             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1025             hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1026                 switch (hdmi_bus_fmt_color_depth(
1027                                         hdmi->hdmi_data.enc_out_bus_format)) {
1028                 case 8:
1029                         color_depth = 4;
1030                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1031                         break;
1032                 case 10:
1033                         color_depth = 5;
1034                         break;
1035                 case 12:
1036                         color_depth = 6;
1037                         break;
1038                 case 16:
1039                         color_depth = 7;
1040                         break;
1041                 default:
1042                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1043                 }
1044         } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1045                 switch (hdmi_bus_fmt_color_depth(
1046                                         hdmi->hdmi_data.enc_out_bus_format)) {
1047                 case 0:
1048                 case 8:
1049                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
1050                         break;
1051                 case 10:
1052                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
1053                         break;
1054                 case 12:
1055                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
1056                         break;
1057
1058                 default:
1059                         return;
1060                 }
1061                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1062         } else {
1063                 return;
1064         }
1065
1066         /* set the packetizer registers */
1067         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1068                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1069                 ((hdmi_data->pix_repet_factor <<
1070                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1071                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1072         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1073
1074         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1075                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1076
1077         /* Data from pixel repeater block */
1078         if (hdmi_data->pix_repet_factor > 1) {
1079                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1080                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1081         } else { /* data from packetizer block */
1082                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1083                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1084         }
1085
1086         hdmi_modb(hdmi, vp_conf,
1087                   HDMI_VP_CONF_PR_EN_MASK |
1088                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1089
1090         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1091                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1092
1093         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1094
1095         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1096                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1097                           HDMI_VP_CONF_PP_EN_ENABLE |
1098                           HDMI_VP_CONF_YCC422_EN_DISABLE;
1099         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1100                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1101                           HDMI_VP_CONF_PP_EN_DISABLE |
1102                           HDMI_VP_CONF_YCC422_EN_ENABLE;
1103         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1104                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1105                           HDMI_VP_CONF_PP_EN_DISABLE |
1106                           HDMI_VP_CONF_YCC422_EN_DISABLE;
1107         } else {
1108                 return;
1109         }
1110
1111         hdmi_modb(hdmi, vp_conf,
1112                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1113                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1114
1115         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1116                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1117                   HDMI_VP_STUFF_PP_STUFFING_MASK |
1118                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1119
1120         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1121                   HDMI_VP_CONF);
1122 }
1123
1124 /* -----------------------------------------------------------------------------
1125  * Synopsys PHY Handling
1126  */
1127
1128 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1129                                        unsigned char bit)
1130 {
1131         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1132                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1133 }
1134
1135 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1136 {
1137         u32 val;
1138
1139         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1140                 if (msec-- == 0)
1141                         return false;
1142                 udelay(1000);
1143         }
1144         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1145
1146         return true;
1147 }
1148
1149 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1150                            unsigned char addr)
1151 {
1152         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1153         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1154         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1155                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1156         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1157                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1158         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1159                     HDMI_PHY_I2CM_OPERATION_ADDR);
1160         hdmi_phy_wait_i2c_done(hdmi, 1000);
1161 }
1162 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1163
1164 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
1165 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
1166 {
1167         struct drm_display_info *display = &hdmi->connector.display_info;
1168
1169         /* Completely disable SCDC support for older controllers */
1170         if (hdmi->version < 0x200a)
1171                 return false;
1172
1173         /* Disable if no DDC bus */
1174         if (!hdmi->ddc)
1175                 return false;
1176
1177         /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1178         if (!display->hdmi.scdc.supported ||
1179             !display->hdmi.scdc.scrambling.supported)
1180                 return false;
1181
1182         /*
1183          * Disable if display only support low TMDS rates and scrambling
1184          * for low rates is not supported either
1185          */
1186         if (!display->hdmi.scdc.scrambling.low_rates &&
1187             display->max_tmds_clock <= 340000)
1188                 return false;
1189
1190         return true;
1191 }
1192
1193 /*
1194  * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1195  * - The Source shall suspend transmission of the TMDS clock and data
1196  * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1197  * from a 0 to a 1 or from a 1 to a 0
1198  * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1199  * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1200  * transmission of TMDS clock and data
1201  *
1202  * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1203  * helper should called right before enabling the TMDS Clock and Data in
1204  * the PHY configuration callback.
1205  */
1206 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1207 {
1208         unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1209
1210         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1211         if (dw_hdmi_support_scdc(hdmi)) {
1212                 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1213                         drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1214                 else
1215                         drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1216         }
1217 }
1218 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1219
1220 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1221 {
1222         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1223                          HDMI_PHY_CONF0_PDZ_OFFSET,
1224                          HDMI_PHY_CONF0_PDZ_MASK);
1225 }
1226
1227 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1228 {
1229         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1230                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1231                          HDMI_PHY_CONF0_ENTMDS_MASK);
1232 }
1233
1234 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1235 {
1236         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1237                          HDMI_PHY_CONF0_SVSRET_OFFSET,
1238                          HDMI_PHY_CONF0_SVSRET_MASK);
1239 }
1240
1241 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1242 {
1243         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1244                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1245                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1246 }
1247 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1248
1249 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1250 {
1251         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1252                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1253                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1254 }
1255 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1256
1257 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1258 {
1259         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1260                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1261                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1262 }
1263
1264 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1265 {
1266         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1267                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1268                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1269 }
1270
1271 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1272 {
1273         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1274         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1275         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1276 }
1277 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1278
1279 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1280 {
1281         hdmi_phy_test_clear(hdmi, 1);
1282         hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1283         hdmi_phy_test_clear(hdmi, 0);
1284 }
1285 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1286
1287 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1288 {
1289         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1290         unsigned int i;
1291         u16 val;
1292
1293         if (phy->gen == 1) {
1294                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1295                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1296                 return;
1297         }
1298
1299         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1300
1301         /*
1302          * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1303          * to low power mode.
1304          */
1305         for (i = 0; i < 5; ++i) {
1306                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1307                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1308                         break;
1309
1310                 usleep_range(1000, 2000);
1311         }
1312
1313         if (val & HDMI_PHY_TX_PHY_LOCK)
1314                 dev_warn(hdmi->dev, "PHY failed to power down\n");
1315         else
1316                 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1317
1318         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1319 }
1320
1321 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1322 {
1323         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1324         unsigned int i;
1325         u8 val;
1326
1327         if (phy->gen == 1) {
1328                 dw_hdmi_phy_enable_powerdown(hdmi, false);
1329
1330                 /* Toggle TMDS enable. */
1331                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1332                 dw_hdmi_phy_enable_tmds(hdmi, 1);
1333                 return 0;
1334         }
1335
1336         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1337         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1338
1339         /* Wait for PHY PLL lock */
1340         for (i = 0; i < 5; ++i) {
1341                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1342                 if (val)
1343                         break;
1344
1345                 usleep_range(1000, 2000);
1346         }
1347
1348         if (!val) {
1349                 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1350                 return -ETIMEDOUT;
1351         }
1352
1353         dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1354         return 0;
1355 }
1356
1357 /*
1358  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1359  * information the DWC MHL PHY has the same register layout and is thus also
1360  * supported by this function.
1361  */
1362 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1363                 const struct dw_hdmi_plat_data *pdata,
1364                 unsigned long mpixelclock)
1365 {
1366         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1367         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1368         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1369
1370         /* TOFIX Will need 420 specific PHY configuration tables */
1371
1372         /* PLL/MPLL Cfg - always match on final entry */
1373         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1374                 if (mpixelclock <= mpll_config->mpixelclock)
1375                         break;
1376
1377         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1378                 if (mpixelclock <= curr_ctrl->mpixelclock)
1379                         break;
1380
1381         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1382                 if (mpixelclock <= phy_config->mpixelclock)
1383                         break;
1384
1385         if (mpll_config->mpixelclock == ~0UL ||
1386             curr_ctrl->mpixelclock == ~0UL ||
1387             phy_config->mpixelclock == ~0UL)
1388                 return -EINVAL;
1389
1390         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1391                               HDMI_3D_TX_PHY_CPCE_CTRL);
1392         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1393                               HDMI_3D_TX_PHY_GMPCTRL);
1394         dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1395                               HDMI_3D_TX_PHY_CURRCTRL);
1396
1397         dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1398         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1399                               HDMI_3D_TX_PHY_MSM_CTRL);
1400
1401         dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1402         dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1403                               HDMI_3D_TX_PHY_CKSYMTXCTRL);
1404         dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1405                               HDMI_3D_TX_PHY_VLEVCTRL);
1406
1407         /* Override and disable clock termination. */
1408         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1409                               HDMI_3D_TX_PHY_CKCALCTRL);
1410
1411         return 0;
1412 }
1413
1414 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1415 {
1416         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1417         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1418         unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1419         unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1420         int ret;
1421
1422         dw_hdmi_phy_power_off(hdmi);
1423
1424         dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1425
1426         /* Leave low power consumption mode by asserting SVSRET. */
1427         if (phy->has_svsret)
1428                 dw_hdmi_phy_enable_svsret(hdmi, 1);
1429
1430         dw_hdmi_phy_reset(hdmi);
1431
1432         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1433
1434         dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1435
1436         /* Write to the PHY as configured by the platform */
1437         if (pdata->configure_phy)
1438                 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1439         else
1440                 ret = phy->configure(hdmi, pdata, mpixelclock);
1441         if (ret) {
1442                 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1443                         mpixelclock);
1444                 return ret;
1445         }
1446
1447         /* Wait for resuming transmission of TMDS clock and data */
1448         if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1449                 msleep(100);
1450
1451         return dw_hdmi_phy_power_on(hdmi);
1452 }
1453
1454 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1455                             struct drm_display_mode *mode)
1456 {
1457         int i, ret;
1458
1459         /* HDMI Phy spec says to do the phy initialization sequence twice */
1460         for (i = 0; i < 2; i++) {
1461                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1462                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1463
1464                 ret = hdmi_phy_configure(hdmi);
1465                 if (ret)
1466                         return ret;
1467         }
1468
1469         return 0;
1470 }
1471
1472 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1473 {
1474         dw_hdmi_phy_power_off(hdmi);
1475 }
1476
1477 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1478                                                void *data)
1479 {
1480         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1481                 connector_status_connected : connector_status_disconnected;
1482 }
1483 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1484
1485 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1486                             bool force, bool disabled, bool rxsense)
1487 {
1488         u8 old_mask = hdmi->phy_mask;
1489
1490         if (force || disabled || !rxsense)
1491                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1492         else
1493                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1494
1495         if (old_mask != hdmi->phy_mask)
1496                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1497 }
1498 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1499
1500 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1501 {
1502         /*
1503          * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1504          * any pending interrupt.
1505          */
1506         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1507         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1508                     HDMI_IH_PHY_STAT0);
1509
1510         /* Enable cable hot plug irq. */
1511         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1512
1513         /* Clear and unmute interrupts. */
1514         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1515                     HDMI_IH_PHY_STAT0);
1516         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1517                     HDMI_IH_MUTE_PHY_STAT0);
1518 }
1519 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1520
1521 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1522         .init = dw_hdmi_phy_init,
1523         .disable = dw_hdmi_phy_disable,
1524         .read_hpd = dw_hdmi_phy_read_hpd,
1525         .update_hpd = dw_hdmi_phy_update_hpd,
1526         .setup_hpd = dw_hdmi_phy_setup_hpd,
1527 };
1528
1529 /* -----------------------------------------------------------------------------
1530  * HDMI TX Setup
1531  */
1532
1533 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1534 {
1535         u8 de;
1536
1537         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1538                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1539         else
1540                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1541
1542         /* disable rx detect */
1543         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1544                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1545
1546         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1547
1548         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1549                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1550 }
1551
1552 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1553 {
1554         struct hdmi_avi_infoframe frame;
1555         u8 val;
1556
1557         /* Initialise info frame from DRM mode */
1558         drm_hdmi_avi_infoframe_from_display_mode(&frame,
1559                                                  &hdmi->connector, mode);
1560
1561         if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1562                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1563         else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1564                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1565         else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1566                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1567         else
1568                 frame.colorspace = HDMI_COLORSPACE_RGB;
1569
1570         /* Set up colorimetry */
1571         switch (hdmi->hdmi_data.enc_out_encoding) {
1572         case V4L2_YCBCR_ENC_601:
1573                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1574                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1575                 else
1576                         frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1577                 frame.extended_colorimetry =
1578                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1579                 break;
1580         case V4L2_YCBCR_ENC_709:
1581                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1582                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1583                 else
1584                         frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1585                 frame.extended_colorimetry =
1586                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1587                 break;
1588         default: /* Carries no data */
1589                 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1590                 frame.extended_colorimetry =
1591                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1592                 break;
1593         }
1594
1595         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1596
1597         /*
1598          * The Designware IP uses a different byte format from standard
1599          * AVI info frames, though generally the bits are in the correct
1600          * bytes.
1601          */
1602
1603         /*
1604          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1605          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1606          * bit 6 rather than 4.
1607          */
1608         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1609         if (frame.active_aspect & 15)
1610                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1611         if (frame.top_bar || frame.bottom_bar)
1612                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1613         if (frame.left_bar || frame.right_bar)
1614                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1615         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1616
1617         /* AVI data byte 2 differences: none */
1618         val = ((frame.colorimetry & 0x3) << 6) |
1619               ((frame.picture_aspect & 0x3) << 4) |
1620               (frame.active_aspect & 0xf);
1621         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1622
1623         /* AVI data byte 3 differences: none */
1624         val = ((frame.extended_colorimetry & 0x7) << 4) |
1625               ((frame.quantization_range & 0x3) << 2) |
1626               (frame.nups & 0x3);
1627         if (frame.itc)
1628                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1629         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1630
1631         /* AVI data byte 4 differences: none */
1632         val = frame.video_code & 0x7f;
1633         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1634
1635         /* AVI Data Byte 5- set up input and output pixel repetition */
1636         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1637                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1638                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1639                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1640                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1641                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1642         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1643
1644         /*
1645          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1646          * ycc range in bits 2,3 rather than 6,7
1647          */
1648         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1649               (frame.content_type & 0x3);
1650         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1651
1652         /* AVI Data Bytes 6-13 */
1653         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1654         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1655         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1656         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1657         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1658         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1659         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1660         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1661 }
1662
1663 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1664                                                  struct drm_display_mode *mode)
1665 {
1666         struct hdmi_vendor_infoframe frame;
1667         u8 buffer[10];
1668         ssize_t err;
1669
1670         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1671                                                           &hdmi->connector,
1672                                                           mode);
1673         if (err < 0)
1674                 /*
1675                  * Going into that statement does not means vendor infoframe
1676                  * fails. It just informed us that vendor infoframe is not
1677                  * needed for the selected mode. Only 4k or stereoscopic 3D
1678                  * mode requires vendor infoframe. So just simply return.
1679                  */
1680                 return;
1681
1682         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1683         if (err < 0) {
1684                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1685                         err);
1686                 return;
1687         }
1688         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1689                         HDMI_FC_DATAUTO0_VSD_MASK);
1690
1691         /* Set the length of HDMI vendor specific InfoFrame payload */
1692         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1693
1694         /* Set 24bit IEEE Registration Identifier */
1695         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1696         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1697         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1698
1699         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1700         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1701         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1702
1703         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1704                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1705
1706         /* Packet frame interpolation */
1707         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1708
1709         /* Auto packets per frame and line spacing */
1710         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1711
1712         /* Configures the Frame Composer On RDRB mode */
1713         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1714                         HDMI_FC_DATAUTO0_VSD_MASK);
1715 }
1716
1717 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1718                              const struct drm_display_mode *mode)
1719 {
1720         u8 inv_val, bytes;
1721         struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
1722         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1723         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1724         unsigned int vdisplay, hdisplay;
1725
1726         vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000;
1727
1728         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1729
1730         if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1731                 vmode->mtmdsclock /= 2;
1732
1733         /* Set up HDMI_FC_INVIDCONF */
1734         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1735                    (dw_hdmi_support_scdc(hdmi) &&
1736                     (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1737                      hdmi_info->scdc.scrambling.low_rates)) ?
1738                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1739                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1740
1741         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1742                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1743                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1744
1745         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1746                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1747                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1748
1749         inv_val |= (vmode->mdataenablepolarity ?
1750                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1751                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1752
1753         if (hdmi->vic == 39)
1754                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1755         else
1756                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1757                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1758                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1759
1760         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1761                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1762                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1763
1764         inv_val |= hdmi->sink_is_hdmi ?
1765                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1766                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1767
1768         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1769
1770         hdisplay = mode->hdisplay;
1771         hblank = mode->htotal - mode->hdisplay;
1772         h_de_hs = mode->hsync_start - mode->hdisplay;
1773         hsync_len = mode->hsync_end - mode->hsync_start;
1774
1775         /*
1776          * When we're setting a YCbCr420 mode, we need
1777          * to adjust the horizontal timing to suit.
1778          */
1779         if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1780                 hdisplay /= 2;
1781                 hblank /= 2;
1782                 h_de_hs /= 2;
1783                 hsync_len /= 2;
1784         }
1785
1786         vdisplay = mode->vdisplay;
1787         vblank = mode->vtotal - mode->vdisplay;
1788         v_de_vs = mode->vsync_start - mode->vdisplay;
1789         vsync_len = mode->vsync_end - mode->vsync_start;
1790
1791         /*
1792          * When we're setting an interlaced mode, we need
1793          * to adjust the vertical timing to suit.
1794          */
1795         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1796                 vdisplay /= 2;
1797                 vblank /= 2;
1798                 v_de_vs /= 2;
1799                 vsync_len /= 2;
1800         }
1801
1802         /* Scrambling Control */
1803         if (dw_hdmi_support_scdc(hdmi)) {
1804                 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1805                     hdmi_info->scdc.scrambling.low_rates) {
1806                         /*
1807                          * HDMI2.0 Specifies the following procedure:
1808                          * After the Source Device has determined that
1809                          * SCDC_Present is set (=1), the Source Device should
1810                          * write the accurate Version of the Source Device
1811                          * to the Source Version field in the SCDCS.
1812                          * Source Devices compliant shall set the
1813                          * Source Version = 1.
1814                          */
1815                         drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
1816                                        &bytes);
1817                         drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1818                                 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1819
1820                         /* Enabled Scrambling in the Sink */
1821                         drm_scdc_set_scrambling(hdmi->ddc, 1);
1822
1823                         /*
1824                          * To activate the scrambler feature, you must ensure
1825                          * that the quasi-static configuration bit
1826                          * fc_invidconf.HDCP_keepout is set at configuration
1827                          * time, before the required mc_swrstzreq.tmdsswrst_req
1828                          * reset request is issued.
1829                          */
1830                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1831                                     HDMI_MC_SWRSTZ);
1832                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1833                 } else {
1834                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1835                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1836                                     HDMI_MC_SWRSTZ);
1837                         drm_scdc_set_scrambling(hdmi->ddc, 0);
1838                 }
1839         }
1840
1841         /* Set up horizontal active pixel width */
1842         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1843         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1844
1845         /* Set up vertical active lines */
1846         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1847         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1848
1849         /* Set up horizontal blanking pixel region width */
1850         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1851         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1852
1853         /* Set up vertical blanking pixel region width */
1854         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1855
1856         /* Set up HSYNC active edge delay width (in pixel clks) */
1857         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1858         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1859
1860         /* Set up VSYNC active edge delay (in lines) */
1861         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1862
1863         /* Set up HSYNC active pulse width (in pixel clks) */
1864         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1865         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1866
1867         /* Set up VSYNC active edge delay (in lines) */
1868         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1869 }
1870
1871 /* HDMI Initialization Step B.4 */
1872 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1873 {
1874         /* control period minimum duration */
1875         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1876         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1877         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1878
1879         /* Set to fill TMDS data channels */
1880         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1881         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1882         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1883
1884         /* Enable pixel clock and tmds data path */
1885         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1886                            HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1887                            HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1888                            HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1889                            HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1890         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1891         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1892
1893         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1894         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1895
1896         /* Enable csc path */
1897         if (is_color_space_conversion(hdmi)) {
1898                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1899                 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1900         }
1901
1902         /* Enable color space conversion if needed */
1903         if (is_color_space_conversion(hdmi))
1904                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1905                             HDMI_MC_FLOWCTRL);
1906         else
1907                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1908                             HDMI_MC_FLOWCTRL);
1909 }
1910
1911 /* Workaround to clear the overflow condition */
1912 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1913 {
1914         unsigned int count;
1915         unsigned int i;
1916         u8 val;
1917
1918         /*
1919          * Under some circumstances the Frame Composer arithmetic unit can miss
1920          * an FC register write due to being busy processing the previous one.
1921          * The issue can be worked around by issuing a TMDS software reset and
1922          * then write one of the FC registers several times.
1923          *
1924          * The number of iterations matters and depends on the HDMI TX revision
1925          * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
1926          * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
1927          * as needing the workaround, with 4 iterations for v1.30a and 1
1928          * iteration for others.
1929          * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
1930          * the workaround with a single iteration.
1931          * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
1932          * been identified as needing the workaround with a single iteration.
1933          */
1934
1935         switch (hdmi->version) {
1936         case 0x130a:
1937                 count = 4;
1938                 break;
1939         case 0x131a:
1940         case 0x132a:
1941         case 0x200a:
1942         case 0x201a:
1943         case 0x211a:
1944         case 0x212a:
1945                 count = 1;
1946                 break;
1947         default:
1948                 return;
1949         }
1950
1951         /* TMDS software reset */
1952         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1953
1954         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1955         for (i = 0; i < count; i++)
1956                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1957 }
1958
1959 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1960 {
1961         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1962                     HDMI_IH_MUTE_FC_STAT2);
1963 }
1964
1965 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1966 {
1967         int ret;
1968
1969         hdmi_disable_overflow_interrupts(hdmi);
1970
1971         hdmi->vic = drm_match_cea_mode(mode);
1972
1973         if (!hdmi->vic) {
1974                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1975         } else {
1976                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1977         }
1978
1979         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1980             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1981             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1982             (hdmi->vic == 17) || (hdmi->vic == 18))
1983                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1984         else
1985                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1986
1987         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1988         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1989
1990         /* TOFIX: Get input format from plat data or fallback to RGB888 */
1991         if (hdmi->plat_data->input_bus_format)
1992                 hdmi->hdmi_data.enc_in_bus_format =
1993                         hdmi->plat_data->input_bus_format;
1994         else
1995                 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1996
1997         /* TOFIX: Get input encoding from plat data or fallback to none */
1998         if (hdmi->plat_data->input_bus_encoding)
1999                 hdmi->hdmi_data.enc_in_encoding =
2000                         hdmi->plat_data->input_bus_encoding;
2001         else
2002                 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2003
2004         /* TOFIX: Default to RGB888 output format */
2005         hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2006
2007         hdmi->hdmi_data.pix_repet_factor = 0;
2008         hdmi->hdmi_data.hdcp_enable = 0;
2009         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2010
2011         /* HDMI Initialization Step B.1 */
2012         hdmi_av_composer(hdmi, mode);
2013
2014         /* HDMI Initializateion Step B.2 */
2015         ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
2016         if (ret)
2017                 return ret;
2018         hdmi->phy.enabled = true;
2019
2020         /* HDMI Initialization Step B.3 */
2021         dw_hdmi_enable_video_path(hdmi);
2022
2023         if (hdmi->sink_has_audio) {
2024                 dev_dbg(hdmi->dev, "sink has audio support\n");
2025
2026                 /* HDMI Initialization Step E - Configure audio */
2027                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2028                 hdmi_enable_audio_clk(hdmi, true);
2029         }
2030
2031         /* not for DVI mode */
2032         if (hdmi->sink_is_hdmi) {
2033                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2034
2035                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2036                 hdmi_config_AVI(hdmi, mode);
2037                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
2038         } else {
2039                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2040         }
2041
2042         hdmi_video_packetize(hdmi);
2043         hdmi_video_csc(hdmi);
2044         hdmi_video_sample(hdmi);
2045         hdmi_tx_hdcp_config(hdmi);
2046
2047         dw_hdmi_clear_overflow(hdmi);
2048
2049         return 0;
2050 }
2051
2052 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2053 {
2054         u8 ih_mute;
2055
2056         /*
2057          * Boot up defaults are:
2058          * HDMI_IH_MUTE   = 0x03 (disabled)
2059          * HDMI_IH_MUTE_* = 0x00 (enabled)
2060          *
2061          * Disable top level interrupt bits in HDMI block
2062          */
2063         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2064                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2065                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2066
2067         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2068
2069         /* by default mask all interrupts */
2070         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2071         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2072         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2073         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2074         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2075         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2076         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2077         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2078         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2079         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2080         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2081         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2082         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2083         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2084
2085         /* Disable interrupts in the IH_MUTE_* registers */
2086         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2087         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2088         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2089         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2090         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2091         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2092         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2093         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2094         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2095         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2096
2097         /* Enable top level interrupt bits in HDMI block */
2098         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2099                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2100         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2101 }
2102
2103 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2104 {
2105         hdmi->bridge_is_on = true;
2106         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
2107 }
2108
2109 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2110 {
2111         if (hdmi->phy.enabled) {
2112                 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2113                 hdmi->phy.enabled = false;
2114         }
2115
2116         hdmi->bridge_is_on = false;
2117 }
2118
2119 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2120 {
2121         int force = hdmi->force;
2122
2123         if (hdmi->disabled) {
2124                 force = DRM_FORCE_OFF;
2125         } else if (force == DRM_FORCE_UNSPECIFIED) {
2126                 if (hdmi->rxsense)
2127                         force = DRM_FORCE_ON;
2128                 else
2129                         force = DRM_FORCE_OFF;
2130         }
2131
2132         if (force == DRM_FORCE_OFF) {
2133                 if (hdmi->bridge_is_on)
2134                         dw_hdmi_poweroff(hdmi);
2135         } else {
2136                 if (!hdmi->bridge_is_on)
2137                         dw_hdmi_poweron(hdmi);
2138         }
2139 }
2140
2141 /*
2142  * Adjust the detection of RXSENSE according to whether we have a forced
2143  * connection mode enabled, or whether we have been disabled.  There is
2144  * no point processing RXSENSE interrupts if we have a forced connection
2145  * state, or DRM has us disabled.
2146  *
2147  * We also disable rxsense interrupts when we think we're disconnected
2148  * to avoid floating TDMS signals giving false rxsense interrupts.
2149  *
2150  * Note: we still need to listen for HPD interrupts even when DRM has us
2151  * disabled so that we can detect a connect event.
2152  */
2153 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2154 {
2155         if (hdmi->phy.ops->update_hpd)
2156                 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2157                                           hdmi->force, hdmi->disabled,
2158                                           hdmi->rxsense);
2159 }
2160
2161 static enum drm_connector_status
2162 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2163 {
2164         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2165                                              connector);
2166
2167         mutex_lock(&hdmi->mutex);
2168         hdmi->force = DRM_FORCE_UNSPECIFIED;
2169         dw_hdmi_update_power(hdmi);
2170         dw_hdmi_update_phy_mask(hdmi);
2171         mutex_unlock(&hdmi->mutex);
2172
2173         return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2174 }
2175
2176 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2177 {
2178         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2179                                              connector);
2180         struct edid *edid;
2181         int ret = 0;
2182
2183         if (!hdmi->ddc)
2184                 return 0;
2185
2186         edid = drm_get_edid(connector, hdmi->ddc);
2187         if (edid) {
2188                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2189                         edid->width_cm, edid->height_cm);
2190
2191                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2192                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2193                 drm_connector_update_edid_property(connector, edid);
2194                 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2195                 ret = drm_add_edid_modes(connector, edid);
2196                 kfree(edid);
2197         } else {
2198                 dev_dbg(hdmi->dev, "failed to get edid\n");
2199         }
2200
2201         return ret;
2202 }
2203
2204 static void dw_hdmi_connector_force(struct drm_connector *connector)
2205 {
2206         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2207                                              connector);
2208
2209         mutex_lock(&hdmi->mutex);
2210         hdmi->force = connector->force;
2211         dw_hdmi_update_power(hdmi);
2212         dw_hdmi_update_phy_mask(hdmi);
2213         mutex_unlock(&hdmi->mutex);
2214 }
2215
2216 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2217         .fill_modes = drm_helper_probe_single_connector_modes,
2218         .detect = dw_hdmi_connector_detect,
2219         .destroy = drm_connector_cleanup,
2220         .force = dw_hdmi_connector_force,
2221         .reset = drm_atomic_helper_connector_reset,
2222         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2223         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2224 };
2225
2226 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2227         .get_modes = dw_hdmi_connector_get_modes,
2228 };
2229
2230 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
2231 {
2232         struct dw_hdmi *hdmi = bridge->driver_private;
2233         struct drm_encoder *encoder = bridge->encoder;
2234         struct drm_connector *connector = &hdmi->connector;
2235         struct cec_connector_info conn_info;
2236         struct cec_notifier *notifier;
2237
2238         connector->interlace_allowed = 1;
2239         connector->polled = DRM_CONNECTOR_POLL_HPD;
2240
2241         drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2242
2243         drm_connector_init_with_ddc(bridge->dev, connector,
2244                                     &dw_hdmi_connector_funcs,
2245                                     DRM_MODE_CONNECTOR_HDMIA,
2246                                     hdmi->ddc);
2247
2248         drm_connector_attach_encoder(connector, encoder);
2249
2250         cec_fill_conn_info_from_drm(&conn_info, connector);
2251
2252         notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2253         if (!notifier)
2254                 return -ENOMEM;
2255
2256         mutex_lock(&hdmi->cec_notifier_mutex);
2257         hdmi->cec_notifier = notifier;
2258         mutex_unlock(&hdmi->cec_notifier_mutex);
2259
2260         return 0;
2261 }
2262
2263 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2264 {
2265         struct dw_hdmi *hdmi = bridge->driver_private;
2266
2267         mutex_lock(&hdmi->cec_notifier_mutex);
2268         cec_notifier_conn_unregister(hdmi->cec_notifier);
2269         hdmi->cec_notifier = NULL;
2270         mutex_unlock(&hdmi->cec_notifier_mutex);
2271 }
2272
2273 static enum drm_mode_status
2274 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2275                           const struct drm_display_mode *mode)
2276 {
2277         struct dw_hdmi *hdmi = bridge->driver_private;
2278         struct drm_connector *connector = &hdmi->connector;
2279         enum drm_mode_status mode_status = MODE_OK;
2280
2281         /* We don't support double-clocked modes */
2282         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2283                 return MODE_BAD;
2284
2285         if (hdmi->plat_data->mode_valid)
2286                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2287
2288         return mode_status;
2289 }
2290
2291 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2292                                     const struct drm_display_mode *orig_mode,
2293                                     const struct drm_display_mode *mode)
2294 {
2295         struct dw_hdmi *hdmi = bridge->driver_private;
2296
2297         mutex_lock(&hdmi->mutex);
2298
2299         /* Store the display mode for plugin/DKMS poweron events */
2300         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2301
2302         mutex_unlock(&hdmi->mutex);
2303 }
2304
2305 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2306 {
2307         struct dw_hdmi *hdmi = bridge->driver_private;
2308
2309         mutex_lock(&hdmi->mutex);
2310         hdmi->disabled = true;
2311         dw_hdmi_update_power(hdmi);
2312         dw_hdmi_update_phy_mask(hdmi);
2313         mutex_unlock(&hdmi->mutex);
2314 }
2315
2316 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2317 {
2318         struct dw_hdmi *hdmi = bridge->driver_private;
2319
2320         mutex_lock(&hdmi->mutex);
2321         hdmi->disabled = false;
2322         dw_hdmi_update_power(hdmi);
2323         dw_hdmi_update_phy_mask(hdmi);
2324         mutex_unlock(&hdmi->mutex);
2325 }
2326
2327 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2328         .attach = dw_hdmi_bridge_attach,
2329         .detach = dw_hdmi_bridge_detach,
2330         .enable = dw_hdmi_bridge_enable,
2331         .disable = dw_hdmi_bridge_disable,
2332         .mode_set = dw_hdmi_bridge_mode_set,
2333         .mode_valid = dw_hdmi_bridge_mode_valid,
2334 };
2335
2336 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2337 {
2338         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2339         unsigned int stat;
2340
2341         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2342         if (!stat)
2343                 return IRQ_NONE;
2344
2345         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2346
2347         i2c->stat = stat;
2348
2349         complete(&i2c->cmp);
2350
2351         return IRQ_HANDLED;
2352 }
2353
2354 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2355 {
2356         struct dw_hdmi *hdmi = dev_id;
2357         u8 intr_stat;
2358         irqreturn_t ret = IRQ_NONE;
2359
2360         if (hdmi->i2c)
2361                 ret = dw_hdmi_i2c_irq(hdmi);
2362
2363         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2364         if (intr_stat) {
2365                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2366                 return IRQ_WAKE_THREAD;
2367         }
2368
2369         return ret;
2370 }
2371
2372 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2373 {
2374         mutex_lock(&hdmi->mutex);
2375
2376         if (!hdmi->force) {
2377                 /*
2378                  * If the RX sense status indicates we're disconnected,
2379                  * clear the software rxsense status.
2380                  */
2381                 if (!rx_sense)
2382                         hdmi->rxsense = false;
2383
2384                 /*
2385                  * Only set the software rxsense status when both
2386                  * rxsense and hpd indicates we're connected.
2387                  * This avoids what seems to be bad behaviour in
2388                  * at least iMX6S versions of the phy.
2389                  */
2390                 if (hpd)
2391                         hdmi->rxsense = true;
2392
2393                 dw_hdmi_update_power(hdmi);
2394                 dw_hdmi_update_phy_mask(hdmi);
2395         }
2396         mutex_unlock(&hdmi->mutex);
2397 }
2398 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2399
2400 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2401 {
2402         struct dw_hdmi *hdmi = dev_id;
2403         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2404
2405         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2406         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2407         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2408
2409         phy_pol_mask = 0;
2410         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2411                 phy_pol_mask |= HDMI_PHY_HPD;
2412         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2413                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2414         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2415                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2416         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2417                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2418         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2419                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2420
2421         if (phy_pol_mask)
2422                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2423
2424         /*
2425          * RX sense tells us whether the TDMS transmitters are detecting
2426          * load - in other words, there's something listening on the
2427          * other end of the link.  Use this to decide whether we should
2428          * power on the phy as HPD may be toggled by the sink to merely
2429          * ask the source to re-read the EDID.
2430          */
2431         if (intr_stat &
2432             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2433                 dw_hdmi_setup_rx_sense(hdmi,
2434                                        phy_stat & HDMI_PHY_HPD,
2435                                        phy_stat & HDMI_PHY_RX_SENSE);
2436
2437                 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
2438                         mutex_lock(&hdmi->cec_notifier_mutex);
2439                         cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
2440                         mutex_unlock(&hdmi->cec_notifier_mutex);
2441                 }
2442         }
2443
2444         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2445                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2446                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2447                 if (hdmi->bridge.dev)
2448                         drm_helper_hpd_irq_event(hdmi->bridge.dev);
2449         }
2450
2451         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2452         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2453                     HDMI_IH_MUTE_PHY_STAT0);
2454
2455         return IRQ_HANDLED;
2456 }
2457
2458 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2459         {
2460                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2461                 .name = "DWC HDMI TX PHY",
2462                 .gen = 1,
2463         }, {
2464                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2465                 .name = "DWC MHL PHY + HEAC PHY",
2466                 .gen = 2,
2467                 .has_svsret = true,
2468                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2469         }, {
2470                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2471                 .name = "DWC MHL PHY",
2472                 .gen = 2,
2473                 .has_svsret = true,
2474                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2475         }, {
2476                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2477                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2478                 .gen = 2,
2479                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2480         }, {
2481                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2482                 .name = "DWC HDMI 3D TX PHY",
2483                 .gen = 2,
2484                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2485         }, {
2486                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2487                 .name = "DWC HDMI 2.0 TX PHY",
2488                 .gen = 2,
2489                 .has_svsret = true,
2490                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2491         }, {
2492                 .type = DW_HDMI_PHY_VENDOR_PHY,
2493                 .name = "Vendor PHY",
2494         }
2495 };
2496
2497 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2498 {
2499         unsigned int i;
2500         u8 phy_type;
2501
2502         phy_type = hdmi->plat_data->phy_force_vendor ?
2503                                 DW_HDMI_PHY_VENDOR_PHY :
2504                                 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2505
2506         if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2507                 /* Vendor PHYs require support from the glue layer. */
2508                 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2509                         dev_err(hdmi->dev,
2510                                 "Vendor HDMI PHY not supported by glue layer\n");
2511                         return -ENODEV;
2512                 }
2513
2514                 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2515                 hdmi->phy.data = hdmi->plat_data->phy_data;
2516                 hdmi->phy.name = hdmi->plat_data->phy_name;
2517                 return 0;
2518         }
2519
2520         /* Synopsys PHYs are handled internally. */
2521         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2522                 if (dw_hdmi_phys[i].type == phy_type) {
2523                         hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2524                         hdmi->phy.name = dw_hdmi_phys[i].name;
2525                         hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2526
2527                         if (!dw_hdmi_phys[i].configure &&
2528                             !hdmi->plat_data->configure_phy) {
2529                                 dev_err(hdmi->dev, "%s requires platform support\n",
2530                                         hdmi->phy.name);
2531                                 return -ENODEV;
2532                         }
2533
2534                         return 0;
2535                 }
2536         }
2537
2538         dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2539         return -ENODEV;
2540 }
2541
2542 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2543 {
2544         mutex_lock(&hdmi->mutex);
2545         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2546         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2547         mutex_unlock(&hdmi->mutex);
2548 }
2549
2550 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2551 {
2552         mutex_lock(&hdmi->mutex);
2553         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2554         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2555         mutex_unlock(&hdmi->mutex);
2556 }
2557
2558 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2559         .write = hdmi_writeb,
2560         .read = hdmi_readb,
2561         .enable = dw_hdmi_cec_enable,
2562         .disable = dw_hdmi_cec_disable,
2563 };
2564
2565 static const struct regmap_config hdmi_regmap_8bit_config = {
2566         .reg_bits       = 32,
2567         .val_bits       = 8,
2568         .reg_stride     = 1,
2569         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2570 };
2571
2572 static const struct regmap_config hdmi_regmap_32bit_config = {
2573         .reg_bits       = 32,
2574         .val_bits       = 32,
2575         .reg_stride     = 4,
2576         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2577 };
2578
2579 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
2580 {
2581         initialize_hdmi_ih_mutes(hdmi);
2582
2583         /*
2584          * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
2585          * Even if we are using a separate i2c adapter doing this doesn't
2586          * hurt.
2587          */
2588         dw_hdmi_i2c_init(hdmi);
2589
2590         if (hdmi->phy.ops->setup_hpd)
2591                 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2592 }
2593
2594 static struct dw_hdmi *
2595 __dw_hdmi_probe(struct platform_device *pdev,
2596                 const struct dw_hdmi_plat_data *plat_data)
2597 {
2598         struct device *dev = &pdev->dev;
2599         struct device_node *np = dev->of_node;
2600         struct platform_device_info pdevinfo;
2601         struct device_node *ddc_node;
2602         struct dw_hdmi_cec_data cec;
2603         struct dw_hdmi *hdmi;
2604         struct resource *iores = NULL;
2605         int irq;
2606         int ret;
2607         u32 val = 1;
2608         u8 prod_id0;
2609         u8 prod_id1;
2610         u8 config0;
2611         u8 config3;
2612
2613         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2614         if (!hdmi)
2615                 return ERR_PTR(-ENOMEM);
2616
2617         hdmi->plat_data = plat_data;
2618         hdmi->dev = dev;
2619         hdmi->sample_rate = 48000;
2620         hdmi->disabled = true;
2621         hdmi->rxsense = true;
2622         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2623         hdmi->mc_clkdis = 0x7f;
2624
2625         mutex_init(&hdmi->mutex);
2626         mutex_init(&hdmi->audio_mutex);
2627         mutex_init(&hdmi->cec_notifier_mutex);
2628         spin_lock_init(&hdmi->audio_lock);
2629
2630         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2631         if (ddc_node) {
2632                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2633                 of_node_put(ddc_node);
2634                 if (!hdmi->ddc) {
2635                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2636                         return ERR_PTR(-EPROBE_DEFER);
2637                 }
2638
2639         } else {
2640                 dev_dbg(hdmi->dev, "no ddc property found\n");
2641         }
2642
2643         if (!plat_data->regm) {
2644                 const struct regmap_config *reg_config;
2645
2646                 of_property_read_u32(np, "reg-io-width", &val);
2647                 switch (val) {
2648                 case 4:
2649                         reg_config = &hdmi_regmap_32bit_config;
2650                         hdmi->reg_shift = 2;
2651                         break;
2652                 case 1:
2653                         reg_config = &hdmi_regmap_8bit_config;
2654                         break;
2655                 default:
2656                         dev_err(dev, "reg-io-width must be 1 or 4\n");
2657                         return ERR_PTR(-EINVAL);
2658                 }
2659
2660                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2661                 hdmi->regs = devm_ioremap_resource(dev, iores);
2662                 if (IS_ERR(hdmi->regs)) {
2663                         ret = PTR_ERR(hdmi->regs);
2664                         goto err_res;
2665                 }
2666
2667                 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2668                 if (IS_ERR(hdmi->regm)) {
2669                         dev_err(dev, "Failed to configure regmap\n");
2670                         ret = PTR_ERR(hdmi->regm);
2671                         goto err_res;
2672                 }
2673         } else {
2674                 hdmi->regm = plat_data->regm;
2675         }
2676
2677         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2678         if (IS_ERR(hdmi->isfr_clk)) {
2679                 ret = PTR_ERR(hdmi->isfr_clk);
2680                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2681                 goto err_res;
2682         }
2683
2684         ret = clk_prepare_enable(hdmi->isfr_clk);
2685         if (ret) {
2686                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2687                 goto err_res;
2688         }
2689
2690         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2691         if (IS_ERR(hdmi->iahb_clk)) {
2692                 ret = PTR_ERR(hdmi->iahb_clk);
2693                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2694                 goto err_isfr;
2695         }
2696
2697         ret = clk_prepare_enable(hdmi->iahb_clk);
2698         if (ret) {
2699                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2700                 goto err_isfr;
2701         }
2702
2703         hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2704         if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2705                 hdmi->cec_clk = NULL;
2706         } else if (IS_ERR(hdmi->cec_clk)) {
2707                 ret = PTR_ERR(hdmi->cec_clk);
2708                 if (ret != -EPROBE_DEFER)
2709                         dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2710                                 ret);
2711
2712                 hdmi->cec_clk = NULL;
2713                 goto err_iahb;
2714         } else {
2715                 ret = clk_prepare_enable(hdmi->cec_clk);
2716                 if (ret) {
2717                         dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2718                                 ret);
2719                         goto err_iahb;
2720                 }
2721         }
2722
2723         /* Product and revision IDs */
2724         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2725                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2726         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2727         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2728
2729         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2730             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2731                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2732                         hdmi->version, prod_id0, prod_id1);
2733                 ret = -ENODEV;
2734                 goto err_iahb;
2735         }
2736
2737         ret = dw_hdmi_detect_phy(hdmi);
2738         if (ret < 0)
2739                 goto err_iahb;
2740
2741         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2742                  hdmi->version >> 12, hdmi->version & 0xfff,
2743                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2744                  hdmi->phy.name);
2745
2746         dw_hdmi_init_hw(hdmi);
2747
2748         irq = platform_get_irq(pdev, 0);
2749         if (irq < 0) {
2750                 ret = irq;
2751                 goto err_iahb;
2752         }
2753
2754         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2755                                         dw_hdmi_irq, IRQF_SHARED,
2756                                         dev_name(dev), hdmi);
2757         if (ret)
2758                 goto err_iahb;
2759
2760         /*
2761          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2762          * N and cts values before enabling phy
2763          */
2764         hdmi_init_clk_regenerator(hdmi);
2765
2766         /* If DDC bus is not specified, try to register HDMI I2C bus */
2767         if (!hdmi->ddc) {
2768                 /* Look for (optional) stuff related to unwedging */
2769                 hdmi->pinctrl = devm_pinctrl_get(dev);
2770                 if (!IS_ERR(hdmi->pinctrl)) {
2771                         hdmi->unwedge_state =
2772                                 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
2773                         hdmi->default_state =
2774                                 pinctrl_lookup_state(hdmi->pinctrl, "default");
2775
2776                         if (IS_ERR(hdmi->default_state) ||
2777                             IS_ERR(hdmi->unwedge_state)) {
2778                                 if (!IS_ERR(hdmi->unwedge_state))
2779                                         dev_warn(dev,
2780                                                  "Unwedge requires default pinctrl\n");
2781                                 hdmi->default_state = NULL;
2782                                 hdmi->unwedge_state = NULL;
2783                         }
2784                 }
2785
2786                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2787                 if (IS_ERR(hdmi->ddc))
2788                         hdmi->ddc = NULL;
2789         }
2790
2791         hdmi->bridge.driver_private = hdmi;
2792         hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2793 #ifdef CONFIG_OF
2794         hdmi->bridge.of_node = pdev->dev.of_node;
2795 #endif
2796
2797         memset(&pdevinfo, 0, sizeof(pdevinfo));
2798         pdevinfo.parent = dev;
2799         pdevinfo.id = PLATFORM_DEVID_AUTO;
2800
2801         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2802         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2803
2804         if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2805                 struct dw_hdmi_audio_data audio;
2806
2807                 audio.phys = iores->start;
2808                 audio.base = hdmi->regs;
2809                 audio.irq = irq;
2810                 audio.hdmi = hdmi;
2811                 audio.eld = hdmi->connector.eld;
2812                 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2813                 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2814
2815                 pdevinfo.name = "dw-hdmi-ahb-audio";
2816                 pdevinfo.data = &audio;
2817                 pdevinfo.size_data = sizeof(audio);
2818                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2819                 hdmi->audio = platform_device_register_full(&pdevinfo);
2820         } else if (config0 & HDMI_CONFIG0_I2S) {
2821                 struct dw_hdmi_i2s_audio_data audio;
2822
2823                 audio.hdmi      = hdmi;
2824                 audio.eld       = hdmi->connector.eld;
2825                 audio.write     = hdmi_writeb;
2826                 audio.read      = hdmi_readb;
2827                 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2828                 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2829
2830                 pdevinfo.name = "dw-hdmi-i2s-audio";
2831                 pdevinfo.data = &audio;
2832                 pdevinfo.size_data = sizeof(audio);
2833                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2834                 hdmi->audio = platform_device_register_full(&pdevinfo);
2835         }
2836
2837         if (config0 & HDMI_CONFIG0_CEC) {
2838                 cec.hdmi = hdmi;
2839                 cec.ops = &dw_hdmi_cec_ops;
2840                 cec.irq = irq;
2841
2842                 pdevinfo.name = "dw-hdmi-cec";
2843                 pdevinfo.data = &cec;
2844                 pdevinfo.size_data = sizeof(cec);
2845                 pdevinfo.dma_mask = 0;
2846
2847                 hdmi->cec = platform_device_register_full(&pdevinfo);
2848         }
2849
2850         return hdmi;
2851
2852 err_iahb:
2853         if (hdmi->i2c) {
2854                 i2c_del_adapter(&hdmi->i2c->adap);
2855                 hdmi->ddc = NULL;
2856         }
2857
2858         clk_disable_unprepare(hdmi->iahb_clk);
2859         if (hdmi->cec_clk)
2860                 clk_disable_unprepare(hdmi->cec_clk);
2861 err_isfr:
2862         clk_disable_unprepare(hdmi->isfr_clk);
2863 err_res:
2864         i2c_put_adapter(hdmi->ddc);
2865
2866         return ERR_PTR(ret);
2867 }
2868
2869 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2870 {
2871         if (hdmi->audio && !IS_ERR(hdmi->audio))
2872                 platform_device_unregister(hdmi->audio);
2873         if (!IS_ERR(hdmi->cec))
2874                 platform_device_unregister(hdmi->cec);
2875
2876         /* Disable all interrupts */
2877         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2878
2879         clk_disable_unprepare(hdmi->iahb_clk);
2880         clk_disable_unprepare(hdmi->isfr_clk);
2881         if (hdmi->cec_clk)
2882                 clk_disable_unprepare(hdmi->cec_clk);
2883
2884         if (hdmi->i2c)
2885                 i2c_del_adapter(&hdmi->i2c->adap);
2886         else
2887                 i2c_put_adapter(hdmi->ddc);
2888 }
2889
2890 /* -----------------------------------------------------------------------------
2891  * Probe/remove API, used from platforms based on the DRM bridge API.
2892  */
2893 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
2894                               const struct dw_hdmi_plat_data *plat_data)
2895 {
2896         struct dw_hdmi *hdmi;
2897
2898         hdmi = __dw_hdmi_probe(pdev, plat_data);
2899         if (IS_ERR(hdmi))
2900                 return hdmi;
2901
2902         drm_bridge_add(&hdmi->bridge);
2903
2904         return hdmi;
2905 }
2906 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2907
2908 void dw_hdmi_remove(struct dw_hdmi *hdmi)
2909 {
2910         drm_bridge_remove(&hdmi->bridge);
2911
2912         __dw_hdmi_remove(hdmi);
2913 }
2914 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2915
2916 /* -----------------------------------------------------------------------------
2917  * Bind/unbind API, used from platforms based on the component framework.
2918  */
2919 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
2920                              struct drm_encoder *encoder,
2921                              const struct dw_hdmi_plat_data *plat_data)
2922 {
2923         struct dw_hdmi *hdmi;
2924         int ret;
2925
2926         hdmi = __dw_hdmi_probe(pdev, plat_data);
2927         if (IS_ERR(hdmi))
2928                 return hdmi;
2929
2930         ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2931         if (ret) {
2932                 dw_hdmi_remove(hdmi);
2933                 DRM_ERROR("Failed to initialize bridge with drm\n");
2934                 return ERR_PTR(ret);
2935         }
2936
2937         return hdmi;
2938 }
2939 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2940
2941 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
2942 {
2943         __dw_hdmi_remove(hdmi);
2944 }
2945 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2946
2947 void dw_hdmi_resume(struct dw_hdmi *hdmi)
2948 {
2949         dw_hdmi_init_hw(hdmi);
2950 }
2951 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2952
2953 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2954 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2955 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2956 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2957 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2958 MODULE_LICENSE("GPL");
2959 MODULE_ALIAS("platform:dw-hdmi");