1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung MIPI DSIM bridge driver.
5 * Copyright (C) 2021 Amarula Solutions(India)
6 * Copyright (c) 2014 Samsung Electronics Co., Ltd
7 * Author: Jagan Teki <jagan@amarulasolutions.com>
9 * Based on exynos_drm_dsi from
10 * Tomasz Figa <t.figa@samsung.com>
13 #include <asm/unaligned.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/irq.h>
18 #include <linux/media-bus-format.h>
19 #include <linux/of_device.h>
20 #include <linux/phy/phy.h>
22 #include <video/mipi_display.h>
24 #include <drm/bridge/samsung-dsim.h>
25 #include <drm/drm_panel.h>
26 #include <drm/drm_print.h>
28 /* returns true iff both arguments logically differs */
29 #define NEQV(a, b) (!(a) ^ !(b))
32 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
33 #define DSIM_STOP_STATE_CLK BIT(8)
34 #define DSIM_TX_READY_HS_CLK BIT(10)
35 #define DSIM_PLL_STABLE BIT(31)
38 #define DSIM_FUNCRST BIT(16)
39 #define DSIM_SWRST BIT(0)
42 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
43 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
46 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
47 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
48 #define DSIM_LANE_ESC_CLK_EN_CLK BIT(19)
49 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
50 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
51 #define DSIM_BYTE_CLKEN BIT(24)
52 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
53 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
54 #define DSIM_PLL_BYPASS BIT(27)
55 #define DSIM_ESC_CLKEN BIT(28)
56 #define DSIM_TX_REQUEST_HSCLK BIT(31)
59 #define DSIM_LANE_EN_CLK BIT(0)
60 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
61 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
62 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
63 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
64 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
65 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
66 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
67 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
68 #define DSIM_SUB_VC (((x) & 0x3) << 16)
69 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
70 #define DSIM_HSA_DISABLE_MODE BIT(20)
71 #define DSIM_HBP_DISABLE_MODE BIT(21)
72 #define DSIM_HFP_DISABLE_MODE BIT(22)
74 * The i.MX 8M Mini Applications Processor Reference Manual,
75 * Rev. 3, 11/2020 Page 4091
76 * The i.MX 8M Nano Applications Processor Reference Manual,
77 * Rev. 2, 07/2022 Page 3058
78 * The i.MX 8M Plus Applications Processor Reference Manual,
79 * Rev. 1, 06/2021 Page 5436
80 * all claims this bit is 'HseDisableMode' with the definition
81 * 0 = Disables transfer
82 * 1 = Enables transfer
84 * This clearly states that HSE is not a disabled bit.
86 * The naming convention follows as per the manual and the
87 * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag.
89 #define DSIM_HSE_DISABLE_MODE BIT(23)
90 #define DSIM_AUTO_MODE BIT(24)
91 #define DSIM_VIDEO_MODE BIT(25)
92 #define DSIM_BURST_MODE BIT(26)
93 #define DSIM_SYNC_INFORM BIT(27)
94 #define DSIM_EOT_DISABLE BIT(28)
95 #define DSIM_MFLUSH_VS BIT(29)
96 /* This flag is valid only for exynos3250/3472/5260/5430 */
97 #define DSIM_CLKLANE_STOP BIT(30)
100 #define DSIM_TX_TRIGGER_RST BIT(4)
101 #define DSIM_TX_LPDT_LP BIT(6)
102 #define DSIM_CMD_LPDT_LP BIT(7)
103 #define DSIM_FORCE_BTA BIT(16)
104 #define DSIM_FORCE_STOP_STATE BIT(20)
105 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
106 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
109 #define DSIM_MAIN_STAND_BY BIT(31)
110 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
111 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
114 #define DSIM_CMD_ALLOW(x) ((x) << 28)
115 #define DSIM_STABLE_VFP(x) ((x) << 16)
116 #define DSIM_MAIN_VBP(x) ((x) << 0)
117 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
118 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
119 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
122 #define DSIM_MAIN_HFP(x) ((x) << 16)
123 #define DSIM_MAIN_HBP(x) ((x) << 0)
124 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
125 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
128 #define DSIM_MAIN_VSA(x) ((x) << 22)
129 #define DSIM_MAIN_HSA(x) ((x) << 0)
130 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
131 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
134 #define DSIM_SUB_STANDY(x) ((x) << 31)
135 #define DSIM_SUB_VRESOL(x) ((x) << 16)
136 #define DSIM_SUB_HRESOL(x) ((x) << 0)
137 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
138 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
139 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
142 #define DSIM_INT_PLL_STABLE BIT(31)
143 #define DSIM_INT_SW_RST_RELEASE BIT(30)
144 #define DSIM_INT_SFR_FIFO_EMPTY BIT(29)
145 #define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28)
146 #define DSIM_INT_BTA BIT(25)
147 #define DSIM_INT_FRAME_DONE BIT(24)
148 #define DSIM_INT_RX_TIMEOUT BIT(21)
149 #define DSIM_INT_BTA_TIMEOUT BIT(20)
150 #define DSIM_INT_RX_DONE BIT(18)
151 #define DSIM_INT_RX_TE BIT(17)
152 #define DSIM_INT_RX_ACK BIT(16)
153 #define DSIM_INT_RX_ECC_ERR BIT(15)
154 #define DSIM_INT_RX_CRC_ERR BIT(14)
157 #define DSIM_RX_DATA_FULL BIT(25)
158 #define DSIM_RX_DATA_EMPTY BIT(24)
159 #define DSIM_SFR_HEADER_FULL BIT(23)
160 #define DSIM_SFR_HEADER_EMPTY BIT(22)
161 #define DSIM_SFR_PAYLOAD_FULL BIT(21)
162 #define DSIM_SFR_PAYLOAD_EMPTY BIT(20)
163 #define DSIM_I80_HEADER_FULL BIT(19)
164 #define DSIM_I80_HEADER_EMPTY BIT(18)
165 #define DSIM_I80_PAYLOAD_FULL BIT(17)
166 #define DSIM_I80_PAYLOAD_EMPTY BIT(16)
167 #define DSIM_SD_HEADER_FULL BIT(15)
168 #define DSIM_SD_HEADER_EMPTY BIT(14)
169 #define DSIM_SD_PAYLOAD_FULL BIT(13)
170 #define DSIM_SD_PAYLOAD_EMPTY BIT(12)
171 #define DSIM_MD_HEADER_FULL BIT(11)
172 #define DSIM_MD_HEADER_EMPTY BIT(10)
173 #define DSIM_MD_PAYLOAD_FULL BIT(9)
174 #define DSIM_MD_PAYLOAD_EMPTY BIT(8)
175 #define DSIM_RX_FIFO BIT(4)
176 #define DSIM_SFR_FIFO BIT(3)
177 #define DSIM_I80_FIFO BIT(2)
178 #define DSIM_SD_FIFO BIT(1)
179 #define DSIM_MD_FIFO BIT(0)
182 #define DSIM_AFC_EN BIT(14)
183 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
186 #define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
187 #define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
188 #define DSIM_FREQ_BAND(x) ((x) << 24)
189 #define DSIM_PLL_EN BIT(23)
190 #define DSIM_PLL_P(x, offset) ((x) << (offset))
191 #define DSIM_PLL_M(x) ((x) << 4)
192 #define DSIM_PLL_S(x) ((x) << 1)
195 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
196 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30)
197 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14)
200 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
201 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
203 /* DSIM_PHYTIMING1 */
204 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
205 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
206 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
207 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
209 /* DSIM_PHYTIMING2 */
210 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
211 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
212 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
214 #define DSI_MAX_BUS_WIDTH 4
215 #define DSI_NUM_VIRTUAL_CHANNELS 4
216 #define DSI_TX_FIFO_SIZE 2048
217 #define DSI_RX_FIFO_SIZE 256
218 #define DSI_XFER_TIMEOUT_MS 100
219 #define DSI_RX_FIFO_EMPTY 0x30800002
221 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
223 #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL)
225 static const char *const clk_names[5] = {
228 "phyclk_mipidphy0_bitclkdiv8",
229 "phyclk_mipidphy0_rxclkesc0",
230 "sclk_rgb_vclk_to_dsim0"
233 enum samsung_dsim_transfer_type {
239 DSIM_STATUS_REG, /* Status register */
240 DSIM_SWRST_REG, /* Software reset register */
241 DSIM_CLKCTRL_REG, /* Clock control register */
242 DSIM_TIMEOUT_REG, /* Time out register */
243 DSIM_CONFIG_REG, /* Configuration register */
244 DSIM_ESCMODE_REG, /* Escape mode register */
246 DSIM_MVPORCH_REG, /* Main display Vporch register */
247 DSIM_MHPORCH_REG, /* Main display Hporch register */
248 DSIM_MSYNC_REG, /* Main display sync area register */
249 DSIM_INTSRC_REG, /* Interrupt source register */
250 DSIM_INTMSK_REG, /* Interrupt mask register */
251 DSIM_PKTHDR_REG, /* Packet Header FIFO register */
252 DSIM_PAYLOAD_REG, /* Payload FIFO register */
253 DSIM_RXFIFO_REG, /* Read FIFO register */
254 DSIM_FIFOCTRL_REG, /* FIFO status and control register */
255 DSIM_PLLCTRL_REG, /* PLL control register */
263 static const unsigned int exynos_reg_ofs[] = {
264 [DSIM_STATUS_REG] = 0x00,
265 [DSIM_SWRST_REG] = 0x04,
266 [DSIM_CLKCTRL_REG] = 0x08,
267 [DSIM_TIMEOUT_REG] = 0x0c,
268 [DSIM_CONFIG_REG] = 0x10,
269 [DSIM_ESCMODE_REG] = 0x14,
270 [DSIM_MDRESOL_REG] = 0x18,
271 [DSIM_MVPORCH_REG] = 0x1c,
272 [DSIM_MHPORCH_REG] = 0x20,
273 [DSIM_MSYNC_REG] = 0x24,
274 [DSIM_INTSRC_REG] = 0x2c,
275 [DSIM_INTMSK_REG] = 0x30,
276 [DSIM_PKTHDR_REG] = 0x34,
277 [DSIM_PAYLOAD_REG] = 0x38,
278 [DSIM_RXFIFO_REG] = 0x3c,
279 [DSIM_FIFOCTRL_REG] = 0x44,
280 [DSIM_PLLCTRL_REG] = 0x4c,
281 [DSIM_PHYCTRL_REG] = 0x5c,
282 [DSIM_PHYTIMING_REG] = 0x64,
283 [DSIM_PHYTIMING1_REG] = 0x68,
284 [DSIM_PHYTIMING2_REG] = 0x6c,
287 static const unsigned int exynos5433_reg_ofs[] = {
288 [DSIM_STATUS_REG] = 0x04,
289 [DSIM_SWRST_REG] = 0x0C,
290 [DSIM_CLKCTRL_REG] = 0x10,
291 [DSIM_TIMEOUT_REG] = 0x14,
292 [DSIM_CONFIG_REG] = 0x18,
293 [DSIM_ESCMODE_REG] = 0x1C,
294 [DSIM_MDRESOL_REG] = 0x20,
295 [DSIM_MVPORCH_REG] = 0x24,
296 [DSIM_MHPORCH_REG] = 0x28,
297 [DSIM_MSYNC_REG] = 0x2C,
298 [DSIM_INTSRC_REG] = 0x34,
299 [DSIM_INTMSK_REG] = 0x38,
300 [DSIM_PKTHDR_REG] = 0x3C,
301 [DSIM_PAYLOAD_REG] = 0x40,
302 [DSIM_RXFIFO_REG] = 0x44,
303 [DSIM_FIFOCTRL_REG] = 0x4C,
304 [DSIM_PLLCTRL_REG] = 0x94,
305 [DSIM_PHYCTRL_REG] = 0xA4,
306 [DSIM_PHYTIMING_REG] = 0xB4,
307 [DSIM_PHYTIMING1_REG] = 0xB8,
308 [DSIM_PHYTIMING2_REG] = 0xBC,
320 PHYTIMING_CLK_PREPARE,
324 PHYTIMING_HS_PREPARE,
329 static const unsigned int reg_values[] = {
330 [RESET_TYPE] = DSIM_SWRST,
332 [STOP_STATE_CNT] = 0xf,
333 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
334 [PHYCTRL_VREG_LP] = 0,
335 [PHYCTRL_SLEW_UP] = 0,
336 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
337 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
338 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
339 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
340 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
341 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
342 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
343 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
344 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
347 static const unsigned int exynos5422_reg_values[] = {
348 [RESET_TYPE] = DSIM_SWRST,
350 [STOP_STATE_CNT] = 0xf,
351 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
352 [PHYCTRL_VREG_LP] = 0,
353 [PHYCTRL_SLEW_UP] = 0,
354 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
355 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
356 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
357 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
358 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
359 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
360 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
361 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
362 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
365 static const unsigned int exynos5433_reg_values[] = {
366 [RESET_TYPE] = DSIM_FUNCRST,
368 [STOP_STATE_CNT] = 0xa,
369 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
370 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
371 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
372 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
373 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
374 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
375 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
376 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
377 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
378 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
379 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
380 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
383 static const unsigned int imx8mm_dsim_reg_values[] = {
384 [RESET_TYPE] = DSIM_SWRST,
386 [STOP_STATE_CNT] = 0xf,
387 [PHYCTRL_ULPS_EXIT] = 0,
388 [PHYCTRL_VREG_LP] = 0,
389 [PHYCTRL_SLEW_UP] = 0,
390 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
391 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
392 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
393 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
394 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
395 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
396 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
397 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
398 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
401 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
402 .reg_ofs = exynos_reg_ofs,
405 .has_clklane_stop = 1,
409 .num_bits_resol = 11,
411 .reg_values = reg_values,
417 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
418 .reg_ofs = exynos_reg_ofs,
421 .has_clklane_stop = 1,
425 .num_bits_resol = 11,
427 .reg_values = reg_values,
433 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
434 .reg_ofs = exynos_reg_ofs,
439 .num_bits_resol = 11,
441 .reg_values = reg_values,
447 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
448 .reg_ofs = exynos5433_reg_ofs,
450 .has_clklane_stop = 1,
454 .num_bits_resol = 12,
456 .reg_values = exynos5433_reg_values,
462 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
463 .reg_ofs = exynos5433_reg_ofs,
465 .has_clklane_stop = 1,
469 .num_bits_resol = 12,
471 .reg_values = exynos5422_reg_values,
477 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
478 .reg_ofs = exynos5433_reg_ofs,
480 .has_clklane_stop = 1,
484 .num_bits_resol = 12,
486 * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus
487 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
490 .reg_values = imx8mm_dsim_reg_values,
496 static const struct samsung_dsim_driver_data *
497 samsung_dsim_types[DSIM_TYPE_COUNT] = {
498 [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data,
499 [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data,
500 [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
501 [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
502 [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
503 [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
504 [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
507 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
509 return container_of(h, struct samsung_dsim, dsi_host);
512 static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b)
514 return container_of(b, struct samsung_dsim, bridge);
517 static inline void samsung_dsim_write(struct samsung_dsim *dsi,
518 enum reg_idx idx, u32 val)
520 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
523 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx)
525 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
528 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi)
530 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
533 dev_err(dsi->dev, "timeout waiting for reset\n");
536 static void samsung_dsim_reset(struct samsung_dsim *dsi)
538 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
540 reinit_completion(&dsi->completed);
541 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
545 #define MHZ (1000 * 1000)
548 static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
551 u8 *p, u16 *m, u8 *s)
553 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
554 unsigned long best_freq = 0;
555 u32 min_delta = 0xffffffff;
561 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
562 p_max = fin / (6 * MHZ);
564 for (_p = p_min; _p <= p_max; ++_p) {
565 for (_s = 0; _s <= 5; ++_s) {
569 tmp = (u64)fout * (_p << _s);
572 if (_m < driver_data->m_min || _m > driver_data->m_max)
577 if (tmp < driver_data->min_freq * MHZ ||
578 tmp > driver_data->max_freq * MHZ)
582 do_div(tmp, _p << _s);
584 delta = abs(fout - tmp);
585 if (delta < min_delta) {
604 static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
607 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
608 unsigned long fin, fout;
614 fin = dsi->pll_clk_rate;
615 fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
618 "failed to find PLL PMS for requested frequency\n");
621 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
623 writel(driver_data->reg_values[PLL_TIMER],
624 dsi->reg_base + driver_data->plltmr_reg);
626 reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
627 DSIM_PLL_M(m) | DSIM_PLL_S(s);
629 if (driver_data->has_freqband) {
630 static const unsigned long freq_bands[] = {
631 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
632 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
633 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
634 770 * MHZ, 870 * MHZ, 950 * MHZ,
638 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
639 if (fout < freq_bands[band])
642 dev_dbg(dsi->dev, "band %d\n", band);
644 reg |= DSIM_FREQ_BAND(band);
647 if (dsi->swap_dn_dp_clk)
648 reg |= DSIM_PLL_DPDNSWAP_CLK;
649 if (dsi->swap_dn_dp_data)
650 reg |= DSIM_PLL_DPDNSWAP_DAT;
652 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
656 if (timeout-- == 0) {
657 dev_err(dsi->dev, "PLL failed to stabilize\n");
660 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
661 } while ((reg & DSIM_PLL_STABLE) == 0);
663 dsi->hs_clock = fout;
668 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
670 unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
671 unsigned long esc_div;
673 struct drm_display_mode *m = &dsi->mode;
674 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
676 /* m->clock is in KHz */
677 pix_clk = m->clock * 1000;
679 /* Use burst_clk_rate if available, otherwise use the pix_clk */
680 if (dsi->burst_clk_rate)
681 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
683 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes));
686 dev_err(dsi->dev, "failed to configure DSI PLL\n");
690 byte_clk = hs_clk / 8;
691 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
692 esc_clk = byte_clk / esc_div;
694 if (esc_clk > 20 * MHZ) {
696 esc_clk = byte_clk / esc_div;
699 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
700 hs_clk, byte_clk, esc_clk);
702 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
703 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
704 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
705 | DSIM_BYTE_CLK_SRC_MASK);
706 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
707 | DSIM_ESC_PRESCALER(esc_div)
708 | DSIM_LANE_ESC_CLK_EN_CLK
709 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
710 | DSIM_BYTE_CLK_SRC(0)
711 | DSIM_TX_REQUEST_HSCLK;
712 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
717 static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
719 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
720 const unsigned int *reg_values = driver_data->reg_values;
722 struct phy_configure_opts_mipi_dphy cfg;
723 int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
724 int hs_exit, hs_prepare, hs_zero, hs_trail;
725 unsigned long long byte_clock = dsi->hs_clock / 8;
727 if (driver_data->has_freqband)
730 phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
735 * The tech Applications Processor manuals for i.MX8M Mini, Nano,
736 * and Plus don't state what the definition of the PHYTIMING
737 * bits are beyond their address and bit position.
738 * After reviewing NXP's downstream code, it appears
739 * that the various PHYTIMING registers take the number
740 * of cycles and use various dividers on them. This
741 * calculation does not result in an exact match to the
742 * downstream code, but it is very close to the values
743 * generated by their lookup table, and it appears
744 * to sync at a variety of resolutions. If someone
745 * can get a more accurate mathematical equation needed
746 * for these registers, this should be updated.
749 lpx = PS_TO_CYCLE(cfg.lpx, byte_clock);
750 hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock);
751 clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
752 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
753 clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock);
754 clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock);
755 hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock);
756 hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock);
757 hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock);
759 /* B D-PHY: D-PHY Master & Slave Analog Block control */
760 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
761 reg_values[PHYCTRL_SLEW_UP];
763 samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);
766 * T LPX: Transmitted length of any Low-Power state period
767 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
771 reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit);
773 samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);
776 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
777 * Line state immediately before the HS-0 Line state starting the
779 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
780 * transmitting the Clock.
781 * T CLK_POST: Time that the transmitter continues to send HS clock
782 * after the last associated Data Lane has transitioned to LP Mode
783 * Interval is defined as the period from the end of T HS-TRAIL to
784 * the beginning of T CLK-TRAIL
785 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
786 * the last payload clock bit of a HS transmission burst
789 reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) |
790 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) |
791 DSIM_PHYTIMING1_CLK_POST(clk_post) |
792 DSIM_PHYTIMING1_CLK_TRAIL(clk_trail);
794 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);
797 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
798 * Line state immediately before the HS-0 Line state starting the
800 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
801 * transmitting the Sync sequence.
802 * T HS-TRAIL: Time that the transmitter drives the flipped differential
803 * state after last payload data bit of a HS transmission burst
806 reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) |
807 DSIM_PHYTIMING2_HS_ZERO(hs_zero) |
808 DSIM_PHYTIMING2_HS_TRAIL(hs_trail);
810 samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg);
813 static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
817 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
818 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
819 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
820 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
822 reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);
824 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
827 static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane)
829 u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG);
831 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
833 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
836 static int samsung_dsim_init_link(struct samsung_dsim *dsi)
838 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
843 /* Initialize FIFO pointers */
844 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
846 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
848 usleep_range(9000, 11000);
851 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
852 usleep_range(9000, 11000);
854 /* DSI configuration */
858 * The first bit of mode_flags specifies display configuration.
859 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
860 * mode, otherwise it will support command mode.
862 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
863 reg |= DSIM_VIDEO_MODE;
866 * The user manual describes that following bits are ignored in
869 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
870 reg |= DSIM_MFLUSH_VS;
871 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
872 reg |= DSIM_SYNC_INFORM;
873 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
874 reg |= DSIM_BURST_MODE;
875 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
876 reg |= DSIM_AUTO_MODE;
877 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
878 reg |= DSIM_HSE_DISABLE_MODE;
879 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
880 reg |= DSIM_HFP_DISABLE_MODE;
881 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
882 reg |= DSIM_HBP_DISABLE_MODE;
883 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
884 reg |= DSIM_HSA_DISABLE_MODE;
887 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
888 reg |= DSIM_EOT_DISABLE;
890 switch (dsi->format) {
891 case MIPI_DSI_FMT_RGB888:
892 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
894 case MIPI_DSI_FMT_RGB666:
895 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
897 case MIPI_DSI_FMT_RGB666_PACKED:
898 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
900 case MIPI_DSI_FMT_RGB565:
901 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
904 dev_err(dsi->dev, "invalid pixel format\n");
909 * Use non-continuous clock mode if the periparal wants and
910 * host controller supports
912 * In non-continous clock mode, host controller will turn off
913 * the HS clock between high-speed transmissions to reduce
916 if (driver_data->has_clklane_stop &&
917 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
918 reg |= DSIM_CLKLANE_STOP;
919 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
921 lanes_mask = BIT(dsi->lanes) - 1;
922 samsung_dsim_enable_lane(dsi, lanes_mask);
924 /* Check clock and data lane state are stop state */
927 if (timeout-- == 0) {
928 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
932 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
933 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
934 != DSIM_STOP_STATE_DAT(lanes_mask))
936 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
938 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
939 reg &= ~DSIM_STOP_STATE_CNT_MASK;
940 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
942 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type))
943 reg |= DSIM_FORCE_STOP_STATE;
945 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
947 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
948 samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg);
953 static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
955 struct drm_display_mode *m = &dsi->mode;
956 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
959 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
960 int byte_clk_khz = dsi->hs_clock / 1000 / 8;
961 int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock;
962 int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock;
963 int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock;
965 /* remove packet overhead when possible */
966 hfp = max(hfp - 6, 0);
967 hbp = max(hbp - 6, 0);
968 hsa = max(hsa - 6, 0);
970 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
973 reg = DSIM_CMD_ALLOW(0xf)
974 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
975 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
976 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
978 reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
979 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
981 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
982 | DSIM_MAIN_HSA(hsa);
983 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
985 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
986 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
988 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
990 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
993 static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable)
997 reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG);
999 reg |= DSIM_MAIN_STAND_BY;
1001 reg &= ~DSIM_MAIN_STAND_BY;
1002 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
1005 static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi)
1010 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
1012 if (!(reg & DSIM_SFR_HEADER_FULL))
1015 if (!cond_resched())
1016 usleep_range(950, 1050);
1017 } while (--timeout);
1022 static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm)
1024 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1027 v |= DSIM_CMD_LPDT_LP;
1029 v &= ~DSIM_CMD_LPDT_LP;
1031 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1034 static void samsung_dsim_force_bta(struct samsung_dsim *dsi)
1036 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1038 v |= DSIM_FORCE_BTA;
1039 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1042 static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi,
1043 struct samsung_dsim_transfer *xfer)
1045 struct device *dev = dsi->dev;
1046 struct mipi_dsi_packet *pkt = &xfer->packet;
1047 const u8 *payload = pkt->payload + xfer->tx_done;
1048 u16 length = pkt->payload_length - xfer->tx_done;
1049 bool first = !xfer->tx_done;
1052 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
1053 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1055 if (length > DSI_TX_FIFO_SIZE)
1056 length = DSI_TX_FIFO_SIZE;
1058 xfer->tx_done += length;
1061 while (length >= 4) {
1062 reg = get_unaligned_le32(payload);
1063 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1071 reg |= payload[2] << 16;
1074 reg |= payload[1] << 8;
1078 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1082 /* Send packet header */
1086 reg = get_unaligned_le32(pkt->header);
1087 if (samsung_dsim_wait_for_hdr_fifo(dsi)) {
1088 dev_err(dev, "waiting for header FIFO timed out\n");
1092 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1093 dsi->state & DSIM_STATE_CMD_LPM)) {
1094 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1095 dsi->state ^= DSIM_STATE_CMD_LPM;
1098 samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg);
1100 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1101 samsung_dsim_force_bta(dsi);
1104 static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi,
1105 struct samsung_dsim_transfer *xfer)
1107 u8 *payload = xfer->rx_payload + xfer->rx_done;
1108 bool first = !xfer->rx_done;
1109 struct device *dev = dsi->dev;
1114 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1116 switch (reg & 0x3f) {
1117 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1118 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1119 if (xfer->rx_len >= 2) {
1120 payload[1] = reg >> 16;
1124 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1125 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1126 payload[0] = reg >> 8;
1128 xfer->rx_len = xfer->rx_done;
1131 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1132 dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff);
1137 length = (reg >> 8) & 0xffff;
1138 if (length > xfer->rx_len) {
1140 "response too long (%u > %u bytes), stripping\n",
1141 xfer->rx_len, length);
1142 length = xfer->rx_len;
1143 } else if (length < xfer->rx_len) {
1144 xfer->rx_len = length;
1148 length = xfer->rx_len - xfer->rx_done;
1149 xfer->rx_done += length;
1151 /* Receive payload */
1152 while (length >= 4) {
1153 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1154 payload[0] = (reg >> 0) & 0xff;
1155 payload[1] = (reg >> 8) & 0xff;
1156 payload[2] = (reg >> 16) & 0xff;
1157 payload[3] = (reg >> 24) & 0xff;
1163 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1166 payload[2] = (reg >> 16) & 0xff;
1169 payload[1] = (reg >> 8) & 0xff;
1172 payload[0] = reg & 0xff;
1176 if (xfer->rx_done == xfer->rx_len)
1180 length = DSI_RX_FIFO_SIZE / 4;
1182 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1183 if (reg == DSI_RX_FIFO_EMPTY)
1188 static void samsung_dsim_transfer_start(struct samsung_dsim *dsi)
1190 unsigned long flags;
1191 struct samsung_dsim_transfer *xfer;
1195 spin_lock_irqsave(&dsi->transfer_lock, flags);
1197 if (list_empty(&dsi->transfer_list)) {
1198 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1202 xfer = list_first_entry(&dsi->transfer_list,
1203 struct samsung_dsim_transfer, list);
1205 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1207 if (xfer->packet.payload_length &&
1208 xfer->tx_done == xfer->packet.payload_length)
1209 /* waiting for RX */
1212 samsung_dsim_send_to_fifo(dsi, xfer);
1214 if (xfer->packet.payload_length || xfer->rx_len)
1218 complete(&xfer->completed);
1220 spin_lock_irqsave(&dsi->transfer_lock, flags);
1222 list_del_init(&xfer->list);
1223 start = !list_empty(&dsi->transfer_list);
1225 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1231 static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi)
1233 struct samsung_dsim_transfer *xfer;
1234 unsigned long flags;
1237 spin_lock_irqsave(&dsi->transfer_lock, flags);
1239 if (list_empty(&dsi->transfer_list)) {
1240 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1244 xfer = list_first_entry(&dsi->transfer_list,
1245 struct samsung_dsim_transfer, list);
1247 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1250 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1251 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1254 if (xfer->tx_done != xfer->packet.payload_length)
1257 if (xfer->rx_done != xfer->rx_len)
1258 samsung_dsim_read_from_fifo(dsi, xfer);
1260 if (xfer->rx_done != xfer->rx_len)
1263 spin_lock_irqsave(&dsi->transfer_lock, flags);
1265 list_del_init(&xfer->list);
1266 start = !list_empty(&dsi->transfer_list);
1268 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1272 complete(&xfer->completed);
1277 static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi,
1278 struct samsung_dsim_transfer *xfer)
1280 unsigned long flags;
1283 spin_lock_irqsave(&dsi->transfer_lock, flags);
1285 if (!list_empty(&dsi->transfer_list) &&
1286 xfer == list_first_entry(&dsi->transfer_list,
1287 struct samsung_dsim_transfer, list)) {
1288 list_del_init(&xfer->list);
1289 start = !list_empty(&dsi->transfer_list);
1290 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1292 samsung_dsim_transfer_start(dsi);
1296 list_del_init(&xfer->list);
1298 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1301 static int samsung_dsim_transfer(struct samsung_dsim *dsi,
1302 struct samsung_dsim_transfer *xfer)
1304 unsigned long flags;
1309 xfer->result = -ETIMEDOUT;
1310 init_completion(&xfer->completed);
1312 spin_lock_irqsave(&dsi->transfer_lock, flags);
1314 stopped = list_empty(&dsi->transfer_list);
1315 list_add_tail(&xfer->list, &dsi->transfer_list);
1317 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1320 samsung_dsim_transfer_start(dsi);
1322 wait_for_completion_timeout(&xfer->completed,
1323 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1324 if (xfer->result == -ETIMEDOUT) {
1325 struct mipi_dsi_packet *pkt = &xfer->packet;
1327 samsung_dsim_remove_transfer(dsi, xfer);
1328 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1329 (int)pkt->payload_length, pkt->payload);
1333 /* Also covers hardware timeout condition */
1334 return xfer->result;
1337 static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
1339 struct samsung_dsim *dsi = dev_id;
1342 status = samsung_dsim_read(dsi, DSIM_INTSRC_REG);
1344 static unsigned long j;
1346 if (printk_timed_ratelimit(&j, 500))
1347 dev_warn(dsi->dev, "spurious interrupt\n");
1350 samsung_dsim_write(dsi, DSIM_INTSRC_REG, status);
1352 if (status & DSIM_INT_SW_RST_RELEASE) {
1353 unsigned long mask = ~(DSIM_INT_RX_DONE |
1354 DSIM_INT_SFR_FIFO_EMPTY |
1355 DSIM_INT_SFR_HDR_FIFO_EMPTY |
1356 DSIM_INT_RX_ECC_ERR |
1357 DSIM_INT_SW_RST_RELEASE);
1358 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask);
1359 complete(&dsi->completed);
1363 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1364 DSIM_INT_PLL_STABLE)))
1367 if (samsung_dsim_transfer_finish(dsi))
1368 samsung_dsim_transfer_start(dsi);
1373 static void samsung_dsim_enable_irq(struct samsung_dsim *dsi)
1375 enable_irq(dsi->irq);
1378 enable_irq(gpiod_to_irq(dsi->te_gpio));
1381 static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
1384 disable_irq(gpiod_to_irq(dsi->te_gpio));
1386 disable_irq(dsi->irq);
1389 static void samsung_dsim_set_stop_state(struct samsung_dsim *dsi, bool enable)
1391 u32 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1394 reg |= DSIM_FORCE_STOP_STATE;
1396 reg &= ~DSIM_FORCE_STOP_STATE;
1398 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
1401 static int samsung_dsim_init(struct samsung_dsim *dsi)
1403 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1405 if (dsi->state & DSIM_STATE_INITIALIZED)
1408 samsung_dsim_reset(dsi);
1409 samsung_dsim_enable_irq(dsi);
1411 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1412 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
1414 samsung_dsim_enable_clock(dsi);
1415 if (driver_data->wait_for_reset)
1416 samsung_dsim_wait_for_reset(dsi);
1417 samsung_dsim_set_phy_ctrl(dsi);
1418 samsung_dsim_init_link(dsi);
1420 dsi->state |= DSIM_STATE_INITIALIZED;
1425 static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
1426 struct drm_bridge_state *old_bridge_state)
1428 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1431 if (dsi->state & DSIM_STATE_ENABLED)
1434 ret = pm_runtime_resume_and_get(dsi->dev);
1436 dev_err(dsi->dev, "failed to enable DSI device.\n");
1440 dsi->state |= DSIM_STATE_ENABLED;
1443 * For Exynos-DSIM the downstream bridge, or panel are expecting
1444 * the host initialization during DSI transfer.
1446 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1447 ret = samsung_dsim_init(dsi);
1451 samsung_dsim_set_display_mode(dsi);
1452 samsung_dsim_set_display_enable(dsi, true);
1456 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
1457 struct drm_bridge_state *old_bridge_state)
1459 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1461 if (samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1462 samsung_dsim_set_display_mode(dsi);
1463 samsung_dsim_set_display_enable(dsi, true);
1465 samsung_dsim_set_stop_state(dsi, false);
1468 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1471 static void samsung_dsim_atomic_disable(struct drm_bridge *bridge,
1472 struct drm_bridge_state *old_bridge_state)
1474 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1476 if (!(dsi->state & DSIM_STATE_ENABLED))
1479 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type))
1480 samsung_dsim_set_stop_state(dsi, true);
1482 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1485 static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
1486 struct drm_bridge_state *old_bridge_state)
1488 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1490 samsung_dsim_set_display_enable(dsi, false);
1492 dsi->state &= ~DSIM_STATE_ENABLED;
1493 pm_runtime_put_sync(dsi->dev);
1497 * This pixel output formats list referenced from,
1498 * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
1499 * 3.7.4 Pixel formats
1500 * Table 14. DSI pixel packing formats
1502 static const u32 samsung_dsim_pixel_output_fmts[] = {
1503 MEDIA_BUS_FMT_YUYV10_1X20,
1504 MEDIA_BUS_FMT_YUYV12_1X24,
1505 MEDIA_BUS_FMT_UYVY8_1X16,
1506 MEDIA_BUS_FMT_RGB101010_1X30,
1507 MEDIA_BUS_FMT_RGB121212_1X36,
1508 MEDIA_BUS_FMT_RGB565_1X16,
1509 MEDIA_BUS_FMT_RGB666_1X18,
1510 MEDIA_BUS_FMT_RGB888_1X24,
1513 static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt)
1517 if (fmt == MEDIA_BUS_FMT_FIXED)
1520 for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) {
1521 if (samsung_dsim_pixel_output_fmts[i] == fmt)
1529 samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1530 struct drm_bridge_state *bridge_state,
1531 struct drm_crtc_state *crtc_state,
1532 struct drm_connector_state *conn_state,
1534 unsigned int *num_input_fmts)
1538 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
1542 if (!samsung_dsim_pixel_output_fmt_supported(output_fmt))
1544 * Some bridge/display drivers are still not able to pass the
1545 * correct format, so handle those pipelines by falling back
1546 * to the default format till the supported formats finalized.
1548 output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
1550 input_fmts[0] = output_fmt;
1551 *num_input_fmts = 1;
1556 static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
1557 struct drm_bridge_state *bridge_state,
1558 struct drm_crtc_state *crtc_state,
1559 struct drm_connector_state *conn_state)
1561 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1562 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1565 * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM
1566 * inverts HS/VS/DE sync signals polarity, therefore, while
1567 * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
1568 * 13.6.3.5.2 RGB interface
1569 * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
1570 * 13.6.2.7.2 RGB interface
1571 * both claim "Vsync, Hsync, and VDEN are active high signals.", the
1572 * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
1574 * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not
1575 * implement the same behavior, therefore LCDIFv3 must generate
1576 * HS/VS/DE signals active HIGH.
1578 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
1579 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1580 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1581 } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) {
1582 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1583 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1589 static void samsung_dsim_mode_set(struct drm_bridge *bridge,
1590 const struct drm_display_mode *mode,
1591 const struct drm_display_mode *adjusted_mode)
1593 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1595 drm_mode_copy(&dsi->mode, adjusted_mode);
1598 static int samsung_dsim_attach(struct drm_bridge *bridge,
1599 enum drm_bridge_attach_flags flags)
1601 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1603 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge,
1607 static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
1608 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1609 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1610 .atomic_reset = drm_atomic_helper_bridge_reset,
1611 .atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts,
1612 .atomic_check = samsung_dsim_atomic_check,
1613 .atomic_pre_enable = samsung_dsim_atomic_pre_enable,
1614 .atomic_enable = samsung_dsim_atomic_enable,
1615 .atomic_disable = samsung_dsim_atomic_disable,
1616 .atomic_post_disable = samsung_dsim_atomic_post_disable,
1617 .mode_set = samsung_dsim_mode_set,
1618 .attach = samsung_dsim_attach,
1621 static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id)
1623 struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id;
1624 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1626 if (pdata->host_ops && pdata->host_ops->te_irq_handler)
1627 return pdata->host_ops->te_irq_handler(dsi);
1632 static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev)
1637 dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN);
1640 else if (IS_ERR(dsi->te_gpio))
1641 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n");
1643 te_gpio_irq = gpiod_to_irq(dsi->te_gpio);
1645 ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL,
1646 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
1648 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1649 gpiod_put(dsi->te_gpio);
1656 static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
1657 struct mipi_dsi_device *device)
1659 struct samsung_dsim *dsi = host_to_dsi(host);
1660 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1661 struct device *dev = dsi->dev;
1662 struct device_node *np = dev->of_node;
1663 struct device_node *remote;
1664 struct drm_panel *panel;
1668 * Devices can also be child nodes when we also control that device
1669 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
1671 * Lookup for a child node of the given parent that isn't either port
1674 for_each_available_child_of_node(np, remote) {
1675 if (of_node_name_eq(remote, "port") ||
1676 of_node_name_eq(remote, "ports"))
1679 goto of_find_panel_or_bridge;
1683 * of_graph_get_remote_node() produces a noisy error message if port
1684 * node isn't found and the absence of the port is a legit case here,
1685 * so at first we silently check whether graph presents in the
1688 if (!of_graph_is_present(np))
1691 remote = of_graph_get_remote_node(np, 1, 0);
1693 of_find_panel_or_bridge:
1697 panel = of_drm_find_panel(remote);
1698 if (!IS_ERR(panel)) {
1699 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
1701 dsi->out_bridge = of_drm_find_bridge(remote);
1702 if (!dsi->out_bridge)
1703 dsi->out_bridge = ERR_PTR(-EINVAL);
1706 of_node_put(remote);
1708 if (IS_ERR(dsi->out_bridge)) {
1709 ret = PTR_ERR(dsi->out_bridge);
1710 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
1714 DRM_DEV_INFO(dev, "Attached %s device\n", device->name);
1716 drm_bridge_add(&dsi->bridge);
1719 * This is a temporary solution and should be made by more generic way.
1721 * If attached panel device is for command mode one, dsi should register
1722 * TE interrupt handler.
1724 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1725 ret = samsung_dsim_register_te_irq(dsi, &device->dev);
1730 if (pdata->host_ops && pdata->host_ops->attach) {
1731 ret = pdata->host_ops->attach(dsi, device);
1736 dsi->lanes = device->lanes;
1737 dsi->format = device->format;
1738 dsi->mode_flags = device->mode_flags;
1743 static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi)
1746 free_irq(gpiod_to_irq(dsi->te_gpio), dsi);
1747 gpiod_put(dsi->te_gpio);
1751 static int samsung_dsim_host_detach(struct mipi_dsi_host *host,
1752 struct mipi_dsi_device *device)
1754 struct samsung_dsim *dsi = host_to_dsi(host);
1755 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1757 dsi->out_bridge = NULL;
1759 if (pdata->host_ops && pdata->host_ops->detach)
1760 pdata->host_ops->detach(dsi, device);
1762 samsung_dsim_unregister_te_irq(dsi);
1764 drm_bridge_remove(&dsi->bridge);
1769 static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
1770 const struct mipi_dsi_msg *msg)
1772 struct samsung_dsim *dsi = host_to_dsi(host);
1773 struct samsung_dsim_transfer xfer;
1776 if (!(dsi->state & DSIM_STATE_ENABLED))
1779 ret = samsung_dsim_init(dsi);
1783 samsung_dsim_set_stop_state(dsi, false);
1785 ret = mipi_dsi_create_packet(&xfer.packet, msg);
1789 xfer.rx_len = msg->rx_len;
1790 xfer.rx_payload = msg->rx_buf;
1791 xfer.flags = msg->flags;
1793 ret = samsung_dsim_transfer(dsi, &xfer);
1794 return (ret < 0) ? ret : xfer.rx_done;
1797 static const struct mipi_dsi_host_ops samsung_dsim_ops = {
1798 .attach = samsung_dsim_host_attach,
1799 .detach = samsung_dsim_host_detach,
1800 .transfer = samsung_dsim_host_transfer,
1803 static int samsung_dsim_of_read_u32(const struct device_node *np,
1804 const char *propname, u32 *out_value, bool optional)
1806 int ret = of_property_read_u32(np, propname, out_value);
1808 if (ret < 0 && !optional)
1809 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1814 static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
1816 struct device *dev = dsi->dev;
1817 struct device_node *node = dev->of_node;
1818 u32 lane_polarities[5] = { 0 };
1819 struct device_node *endpoint;
1820 int i, nr_lanes, ret;
1821 struct clk *pll_clk;
1823 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
1824 &dsi->pll_clk_rate, 1);
1825 /* If it doesn't exist, read it from the clock instead of failing */
1827 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n");
1828 pll_clk = devm_clk_get(dev, "sclk_mipi");
1829 if (!IS_ERR(pll_clk))
1830 dsi->pll_clk_rate = clk_get_rate(pll_clk);
1832 return PTR_ERR(pll_clk);
1835 /* If it doesn't exist, use pixel clock instead of failing */
1836 ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
1837 &dsi->burst_clk_rate, 1);
1839 dev_dbg(dev, "Using pixel clock for HS clock frequency\n");
1840 dsi->burst_clk_rate = 0;
1843 ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
1844 &dsi->esc_clk_rate, 0);
1848 endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
1849 nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1850 if (nr_lanes > 0 && nr_lanes <= 4) {
1851 /* Polarity 0 is clock lane, 1..4 are data lanes. */
1852 of_property_read_u32_array(endpoint, "lane-polarities",
1853 lane_polarities, nr_lanes + 1);
1854 for (i = 1; i <= nr_lanes; i++) {
1855 if (lane_polarities[1] != lane_polarities[i])
1856 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
1858 if (lane_polarities[0])
1859 dsi->swap_dn_dp_clk = true;
1860 if (lane_polarities[1])
1861 dsi->swap_dn_dp_data = true;
1867 static int generic_dsim_register_host(struct samsung_dsim *dsi)
1869 return mipi_dsi_host_register(&dsi->dsi_host);
1872 static void generic_dsim_unregister_host(struct samsung_dsim *dsi)
1874 mipi_dsi_host_unregister(&dsi->dsi_host);
1877 static const struct samsung_dsim_host_ops generic_dsim_host_ops = {
1878 .register_host = generic_dsim_register_host,
1879 .unregister_host = generic_dsim_unregister_host,
1882 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = {
1883 .input_bus_flags = DRM_BUS_FLAG_DE_HIGH,
1886 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = {
1887 .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1890 int samsung_dsim_probe(struct platform_device *pdev)
1892 struct device *dev = &pdev->dev;
1893 struct samsung_dsim *dsi;
1896 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1900 init_completion(&dsi->completed);
1901 spin_lock_init(&dsi->transfer_lock);
1902 INIT_LIST_HEAD(&dsi->transfer_list);
1904 dsi->dsi_host.ops = &samsung_dsim_ops;
1905 dsi->dsi_host.dev = dev;
1908 dsi->plat_data = of_device_get_match_data(dev);
1909 dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type];
1911 dsi->supplies[0].supply = "vddcore";
1912 dsi->supplies[1].supply = "vddio";
1913 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1916 return dev_err_probe(dev, ret, "failed to get regulators\n");
1918 dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
1919 sizeof(*dsi->clks), GFP_KERNEL);
1923 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1924 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1925 if (IS_ERR(dsi->clks[i])) {
1926 if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1927 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1928 if (!IS_ERR(dsi->clks[i]))
1932 dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
1933 return PTR_ERR(dsi->clks[i]);
1937 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
1938 if (IS_ERR(dsi->reg_base))
1939 return PTR_ERR(dsi->reg_base);
1941 dsi->phy = devm_phy_optional_get(dev, "dsim");
1942 if (IS_ERR(dsi->phy)) {
1943 dev_info(dev, "failed to get dsim phy\n");
1944 return PTR_ERR(dsi->phy);
1947 dsi->irq = platform_get_irq(pdev, 0);
1951 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1953 IRQF_ONESHOT | IRQF_NO_AUTOEN,
1954 dev_name(dev), dsi);
1956 dev_err(dev, "failed to request dsi irq\n");
1960 ret = samsung_dsim_parse_dt(dsi);
1964 platform_set_drvdata(pdev, dsi);
1966 pm_runtime_enable(dev);
1968 dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
1969 dsi->bridge.of_node = dev->of_node;
1970 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1972 /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */
1973 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM)
1974 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low;
1976 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high;
1978 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host)
1979 ret = dsi->plat_data->host_ops->register_host(dsi);
1982 goto err_disable_runtime;
1986 err_disable_runtime:
1987 pm_runtime_disable(dev);
1991 EXPORT_SYMBOL_GPL(samsung_dsim_probe);
1993 int samsung_dsim_remove(struct platform_device *pdev)
1995 struct samsung_dsim *dsi = platform_get_drvdata(pdev);
1997 pm_runtime_disable(&pdev->dev);
1999 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host)
2000 dsi->plat_data->host_ops->unregister_host(dsi);
2004 EXPORT_SYMBOL_GPL(samsung_dsim_remove);
2006 static int __maybe_unused samsung_dsim_suspend(struct device *dev)
2008 struct samsung_dsim *dsi = dev_get_drvdata(dev);
2009 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2012 usleep_range(10000, 20000);
2014 if (dsi->state & DSIM_STATE_INITIALIZED) {
2015 dsi->state &= ~DSIM_STATE_INITIALIZED;
2017 samsung_dsim_disable_clock(dsi);
2019 samsung_dsim_disable_irq(dsi);
2022 dsi->state &= ~DSIM_STATE_CMD_LPM;
2024 phy_power_off(dsi->phy);
2026 for (i = driver_data->num_clks - 1; i > -1; i--)
2027 clk_disable_unprepare(dsi->clks[i]);
2029 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2031 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
2036 static int __maybe_unused samsung_dsim_resume(struct device *dev)
2038 struct samsung_dsim *dsi = dev_get_drvdata(dev);
2039 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2042 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2044 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
2048 for (i = 0; i < driver_data->num_clks; i++) {
2049 ret = clk_prepare_enable(dsi->clks[i]);
2054 ret = phy_power_on(dsi->phy);
2056 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
2064 clk_disable_unprepare(dsi->clks[i]);
2065 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2070 const struct dev_pm_ops samsung_dsim_pm_ops = {
2071 SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
2072 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2073 pm_runtime_force_resume)
2075 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops);
2077 static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = {
2078 .hw_type = DSIM_TYPE_IMX8MM,
2079 .host_ops = &generic_dsim_host_ops,
2082 static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = {
2083 .hw_type = DSIM_TYPE_IMX8MP,
2084 .host_ops = &generic_dsim_host_ops,
2087 static const struct of_device_id samsung_dsim_of_match[] = {
2089 .compatible = "fsl,imx8mm-mipi-dsim",
2090 .data = &samsung_dsim_imx8mm_pdata,
2093 .compatible = "fsl,imx8mp-mipi-dsim",
2094 .data = &samsung_dsim_imx8mp_pdata,
2098 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);
2100 static struct platform_driver samsung_dsim_driver = {
2101 .probe = samsung_dsim_probe,
2102 .remove = samsung_dsim_remove,
2104 .name = "samsung-dsim",
2105 .pm = &samsung_dsim_pm_ops,
2106 .of_match_table = samsung_dsim_of_match,
2110 module_platform_driver(samsung_dsim_driver);
2112 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
2113 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
2114 MODULE_LICENSE("GPL");