drivers/gpu/drm/bridge/parade-ps8640.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016 MediaTek Inc.
   4  */
   5
   6 #include <linux/delay.h>
   7 #include <linux/err.h>
   8 #include <linux/gpio/consumer.h>
   9 #include <linux/i2c.h>
  10 #include <linux/module.h>
  11 #include <linux/of_graph.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/regmap.h>
  14 #include <linux/regulator/consumer.h>
  15
  16 #include <drm/display/drm_dp_aux_bus.h>
  17 #include <drm/display/drm_dp_helper.h>
  18 #include <drm/drm_atomic_state_helper.h>
  19 #include <drm/drm_bridge.h>
  20 #include <drm/drm_edid.h>
  21 #include <drm/drm_mipi_dsi.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drm_print.h>
  25
  26 #define PAGE0_AUXCH_CFG3        0x76
  27 #define  AUXCH_CFG3_RESET       0xff
  28 #define PAGE0_SWAUX_ADDR_7_0    0x7d
  29 #define PAGE0_SWAUX_ADDR_15_8   0x7e
  30 #define PAGE0_SWAUX_ADDR_23_16  0x7f
  31 #define  SWAUX_ADDR_MASK        GENMASK(19, 0)
  32 #define PAGE0_SWAUX_LENGTH      0x80
  33 #define  SWAUX_LENGTH_MASK      GENMASK(3, 0)
  34 #define  SWAUX_NO_PAYLOAD       BIT(7)
  35 #define PAGE0_SWAUX_WDATA       0x81
  36 #define PAGE0_SWAUX_RDATA       0x82
  37 #define PAGE0_SWAUX_CTRL        0x83
  38 #define  SWAUX_SEND             BIT(0)
  39 #define PAGE0_SWAUX_STATUS      0x84
  40 #define  SWAUX_M_MASK           GENMASK(4, 0)
  41 #define  SWAUX_STATUS_MASK      GENMASK(7, 5)
  42 #define  SWAUX_STATUS_NACK      (0x1 << 5)
  43 #define  SWAUX_STATUS_DEFER     (0x2 << 5)
  44 #define  SWAUX_STATUS_ACKM      (0x3 << 5)
  45 #define  SWAUX_STATUS_INVALID   (0x4 << 5)
  46 #define  SWAUX_STATUS_I2C_NACK  (0x5 << 5)
  47 #define  SWAUX_STATUS_I2C_DEFER (0x6 << 5)
  48 #define  SWAUX_STATUS_TIMEOUT   (0x7 << 5)
  49
  50 #define PAGE2_GPIO_H            0xa7
  51 #define  PS_GPIO9               BIT(1)
  52 #define PAGE2_I2C_BYPASS        0xea
  53 #define  I2C_BYPASS_EN          0xd0
  54 #define PAGE2_MCS_EN            0xf3
  55 #define  MCS_EN                 BIT(0)
  56
  57 #define PAGE3_SET_ADD           0xfe
  58 #define  VDO_CTL_ADD            0x13
  59 #define  VDO_DIS                0x18
  60 #define  VDO_EN                 0x1c
  61
  62 #define NUM_MIPI_LANES          4
  63
  64 #define COMMON_PS8640_REGMAP_CONFIG \
  65         .reg_bits = 8, \
  66         .val_bits = 8, \
  67         .cache_type = REGCACHE_NONE
  68
  69 /*
  70  * PS8640 uses multiple addresses:
  71  * page[0]: for DP control
  72  * page[1]: for VIDEO Bridge
  73  * page[2]: for control top
  74  * page[3]: for DSI Link Control1
  75  * page[4]: for MIPI Phy
  76  * page[5]: for VPLL
  77  * page[6]: for DSI Link Control2
  78  * page[7]: for SPI ROM mapping
  79  */
  80 enum page_addr_offset {
  81         PAGE0_DP_CNTL = 0,
  82         PAGE1_VDO_BDG,
  83         PAGE2_TOP_CNTL,
  84         PAGE3_DSI_CNTL1,
  85         PAGE4_MIPI_PHY,
  86         PAGE5_VPLL,
  87         PAGE6_DSI_CNTL2,
  88         PAGE7_SPI_CNTL,
  89         MAX_DEVS
  90 };
  91
  92 enum ps8640_vdo_control {
  93         DISABLE = VDO_DIS,
  94         ENABLE = VDO_EN,
  95 };
  96
  97 struct ps8640 {
  98         struct drm_bridge bridge;
  99         struct drm_bridge *panel_bridge;
 100         struct drm_dp_aux aux;
 101         struct mipi_dsi_device *dsi;
 102         struct i2c_client *page[MAX_DEVS];
 103         struct regmap   *regmap[MAX_DEVS];
 104         struct regulator_bulk_data supplies[2];
 105         struct gpio_desc *gpio_reset;
 106         struct gpio_desc *gpio_powerdown;
 107         struct device_link *link;
 108         bool pre_enabled;
 109         bool need_post_hpd_delay;
 110         struct mutex aux_lock;
 111 };
 112
 113 static const struct regmap_config ps8640_regmap_config[] = {
 114         [PAGE0_DP_CNTL] = {
 115                 COMMON_PS8640_REGMAP_CONFIG,
 116                 .max_register = 0xbf,
 117         },
 118         [PAGE1_VDO_BDG] = {
 119                 COMMON_PS8640_REGMAP_CONFIG,
 120                 .max_register = 0xff,
 121         },
 122         [PAGE2_TOP_CNTL] = {
 123                 COMMON_PS8640_REGMAP_CONFIG,
 124                 .max_register = 0xff,
 125         },
 126         [PAGE3_DSI_CNTL1] = {
 127                 COMMON_PS8640_REGMAP_CONFIG,
 128                 .max_register = 0xff,
 129         },
 130         [PAGE4_MIPI_PHY] = {
 131                 COMMON_PS8640_REGMAP_CONFIG,
 132                 .max_register = 0xff,
 133         },
 134         [PAGE5_VPLL] = {
 135                 COMMON_PS8640_REGMAP_CONFIG,
 136                 .max_register = 0x7f,
 137         },
 138         [PAGE6_DSI_CNTL2] = {
 139                 COMMON_PS8640_REGMAP_CONFIG,
 140                 .max_register = 0xff,
 141         },
 142         [PAGE7_SPI_CNTL] = {
 143                 COMMON_PS8640_REGMAP_CONFIG,
 144                 .max_register = 0xff,
 145         },
 146 };
 147
 148 static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
 149 {
 150         return container_of(e, struct ps8640, bridge);
 151 }
 152
 153 static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
 154 {
 155         return container_of(aux, struct ps8640, aux);
 156 }
 157
 158 static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us)
 159 {
 160         struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
 161         int status;
 162         int ret;
 163
 164         /*
 165          * Apparently something about the firmware in the chip signals that
 166          * HPD goes high by reporting GPIO9 as high (even though HPD isn't
 167          * actually connected to GPIO9).
 168          */
 169         ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
 170                                        status & PS_GPIO9, 20000, wait_us);
 171
 172         /*
 173          * The first time we see HPD go high after a reset we delay an extra
 174          * 50 ms. The best guess is that the MCU is doing "stuff" during this
 175          * time (maybe talking to the panel) and we don't want to interrupt it.
 176          *
 177          * No locking is done around "need_post_hpd_delay". If we're here we
 178          * know we're holding a PM Runtime reference and the only other place
 179          * that touches this is PM Runtime resume.
 180          */
 181         if (!ret && ps_bridge->need_post_hpd_delay) {
 182                 ps_bridge->need_post_hpd_delay = false;
 183                 msleep(50);
 184         }
 185
 186         return ret;
 187 }
 188
 189 static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
 190 {
 191         struct ps8640 *ps_bridge = aux_to_ps8640(aux);
 192         struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
 193         int ret;
 194
 195         /*
 196          * Note that this function is called by code that has already powered
 197          * the panel. We have to power ourselves up but we don't need to worry
 198          * about powering the panel.
 199          */
 200         pm_runtime_get_sync(dev);
 201         ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us);
 202         pm_runtime_mark_last_busy(dev);
 203         pm_runtime_put_autosuspend(dev);
 204
 205         return ret;
 206 }
 207
 208 static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
 209                                        struct drm_dp_aux_msg *msg)
 210 {
 211         struct ps8640 *ps_bridge = aux_to_ps8640(aux);
 212         struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
 213         struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
 214         size_t len = msg->size;
 215         unsigned int data;
 216         unsigned int base;
 217         int ret;
 218         u8 request = msg->request &
 219                      ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
 220         u8 *buf = msg->buffer;
 221         u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
 222         u8 i;
 223         bool is_native_aux = false;
 224
 225         if (len > DP_AUX_MAX_PAYLOAD_BYTES)
 226                 return -EINVAL;
 227
 228         if (msg->address & ~SWAUX_ADDR_MASK)
 229                 return -EINVAL;
 230
 231         switch (request) {
 232         case DP_AUX_NATIVE_WRITE:
 233         case DP_AUX_NATIVE_READ:
 234                 is_native_aux = true;
 235                 fallthrough;
 236         case DP_AUX_I2C_WRITE:
 237         case DP_AUX_I2C_READ:
 238                 break;
 239         default:
 240                 return -EINVAL;
 241         }
 242
 243         ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
 244         if (ret) {
 245                 DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
 246                               ret);
 247                 return ret;
 248         }
 249
 250         /* Assume it's good */
 251         msg->reply = 0;
 252
 253         base = PAGE0_SWAUX_ADDR_7_0;
 254         addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
 255         addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
 256         addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
 257                                                   (msg->request << 4);
 258         addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
 259                                               ((len - 1) & SWAUX_LENGTH_MASK);
 260
 261         regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len,
 262                           ARRAY_SIZE(addr_len));
 263
 264         if (len && (request == DP_AUX_NATIVE_WRITE ||
 265                     request == DP_AUX_I2C_WRITE)) {
 266                 /* Write to the internal FIFO buffer */
 267                 for (i = 0; i < len; i++) {
 268                         ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]);
 269                         if (ret) {
 270                                 DRM_DEV_ERROR(dev,
 271                                               "failed to write WDATA: %d\n",
 272                                               ret);
 273                                 return ret;
 274                         }
 275                 }
 276         }
 277
 278         regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
 279
 280         /* Zero delay loop because i2c transactions are slow already */
 281         regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
 282                                  !(data & SWAUX_SEND), 0, 50 * 1000);
 283
 284         regmap_read(map, PAGE0_SWAUX_STATUS, &data);
 285         if (ret) {
 286                 DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
 287                               ret);
 288                 return ret;
 289         }
 290
 291         switch (data & SWAUX_STATUS_MASK) {
 292         case SWAUX_STATUS_NACK:
 293         case SWAUX_STATUS_I2C_NACK:
 294                 /*
 295                  * The programming guide is not clear about whether a I2C NACK
 296                  * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
 297                  * we handle both cases together.
 298                  */
 299                 if (is_native_aux)
 300                         msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
 301                 else
 302                         msg->reply |= DP_AUX_I2C_REPLY_NACK;
 303
 304                 fallthrough;
 305         case SWAUX_STATUS_ACKM:
 306                 len = data & SWAUX_M_MASK;
 307                 break;
 308         case SWAUX_STATUS_DEFER:
 309         case SWAUX_STATUS_I2C_DEFER:
 310                 if (is_native_aux)
 311                         msg->reply |= DP_AUX_NATIVE_REPLY_DEFER;
 312                 else
 313                         msg->reply |= DP_AUX_I2C_REPLY_DEFER;
 314                 len = data & SWAUX_M_MASK;
 315                 break;
 316         case SWAUX_STATUS_INVALID:
 317                 return -EOPNOTSUPP;
 318         case SWAUX_STATUS_TIMEOUT:
 319                 return -ETIMEDOUT;
 320         }
 321
 322         if (len && (request == DP_AUX_NATIVE_READ ||
 323                     request == DP_AUX_I2C_READ)) {
 324                 /* Read from the internal FIFO buffer */
 325                 for (i = 0; i < len; i++) {
 326                         ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data);
 327                         if (ret) {
 328                                 DRM_DEV_ERROR(dev,
 329                                               "failed to read RDATA: %d\n",
 330                                               ret);
 331                                 return ret;
 332                         }
 333
 334                         if (i < msg->size)
 335                                 buf[i] = data;
 336                 }
 337         }
 338
 339         return min(len, msg->size);
 340 }
 341
 342 static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
 343                                    struct drm_dp_aux_msg *msg)
 344 {
 345         struct ps8640 *ps_bridge = aux_to_ps8640(aux);
 346         struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
 347         int ret;
 348
 349         mutex_lock(&ps_bridge->aux_lock);
 350         pm_runtime_get_sync(dev);
 351         ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000);
 352         if (ret) {
 353                 pm_runtime_put_sync_suspend(dev);
 354                 return ret;
 355         }
 356         ret = ps8640_aux_transfer_msg(aux, msg);
 357         pm_runtime_mark_last_busy(dev);
 358         pm_runtime_put_autosuspend(dev);
 359         mutex_unlock(&ps_bridge->aux_lock);
 360
 361         return ret;
 362 }
 363
 364 static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
 365                                       const enum ps8640_vdo_control ctrl)
 366 {
 367         struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
 368         struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
 369         u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
 370         int ret;
 371
 372         ret = regmap_bulk_write(map, PAGE3_SET_ADD,
 373                                 vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
 374
 375         if (ret < 0)
 376                 dev_err(dev, "failed to %sable VDO: %d\n",
 377                         ctrl == ENABLE ? "en" : "dis", ret);
 378 }
 379
 380 static int __maybe_unused ps8640_resume(struct device *dev)
 381 {
 382         struct ps8640 *ps_bridge = dev_get_drvdata(dev);
 383         int ret;
 384
 385         ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
 386                                     ps_bridge->supplies);
 387         if (ret < 0) {
 388                 dev_err(dev, "cannot enable regulators %d\n", ret);
 389                 return ret;
 390         }
 391
 392         gpiod_set_value(ps_bridge->gpio_powerdown, 0);
 393         gpiod_set_value(ps_bridge->gpio_reset, 1);
 394         usleep_range(2000, 2500);
 395         gpiod_set_value(ps_bridge->gpio_reset, 0);
 396         /* Double reset for T4 and T5 */
 397         msleep(50);
 398         gpiod_set_value(ps_bridge->gpio_reset, 1);
 399         msleep(50);
 400         gpiod_set_value(ps_bridge->gpio_reset, 0);
 401
 402         /* We just reset things, so we need a delay after the first HPD */
 403         ps_bridge->need_post_hpd_delay = true;
 404
 405         /*
 406          * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
 407          * this is truly necessary since the MCU will already signal that
 408          * things are "good to go" by signaling HPD on "gpio 9". See
 409          * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
 410          * just in case.
 411          */
 412         msleep(200);
 413
 414         return 0;
 415 }
 416
 417 static int __maybe_unused ps8640_suspend(struct device *dev)
 418 {
 419         struct ps8640 *ps_bridge = dev_get_drvdata(dev);
 420         int ret;
 421
 422         gpiod_set_value(ps_bridge->gpio_reset, 1);
 423         gpiod_set_value(ps_bridge->gpio_powerdown, 1);
 424         ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
 425                                      ps_bridge->supplies);
 426         if (ret < 0)
 427                 dev_err(dev, "cannot disable regulators %d\n", ret);
 428
 429         return ret;
 430 }
 431
 432 static const struct dev_pm_ops ps8640_pm_ops = {
 433         SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
 434         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 435                                 pm_runtime_force_resume)
 436 };
 437
 438 static void ps8640_atomic_pre_enable(struct drm_bridge *bridge,
 439                                      struct drm_bridge_state *old_bridge_state)
 440 {
 441         struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
 442         struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
 443         struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
 444         int ret;
 445
 446         pm_runtime_get_sync(dev);
 447         ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000);
 448         if (ret < 0)
 449                 dev_warn(dev, "HPD didn't go high: %d\n", ret);
 450
 451         /*
 452          * The Manufacturer Command Set (MCS) is a device dependent interface
 453          * intended for factory programming of the display module default
 454          * parameters. Once the display module is configured, the MCS shall be
 455          * disabled by the manufacturer. Once disabled, all MCS commands are
 456          * ignored by the display interface.
 457          */
 458
 459         ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
 460         if (ret < 0)
 461                 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
 462
 463         /* Switch access edp panel's edid through i2c */
 464         ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
 465         if (ret < 0)
 466                 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
 467
 468         ps8640_bridge_vdo_control(ps_bridge, ENABLE);
 469
 470         ps_bridge->pre_enabled = true;
 471 }
 472
 473 static void ps8640_atomic_post_disable(struct drm_bridge *bridge,
 474                                        struct drm_bridge_state *old_bridge_state)
 475 {
 476         struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
 477
 478         ps_bridge->pre_enabled = false;
 479
 480         ps8640_bridge_vdo_control(ps_bridge, DISABLE);
 481
 482         /*
 483          * The bridge seems to expect everything to be power cycled at the
 484          * disable process, so grab a lock here to make sure
 485          * ps8640_aux_transfer() is not holding a runtime PM reference and
 486          * preventing the bridge from suspend.
 487          */
 488         mutex_lock(&ps_bridge->aux_lock);
 489
 490         pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev);
 491
 492         mutex_unlock(&ps_bridge->aux_lock);
 493 }
 494
 495 static int ps8640_bridge_attach(struct drm_bridge *bridge,
 496                                 enum drm_bridge_attach_flags flags)
 497 {
 498         struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
 499         struct device *dev = &ps_bridge->page[0]->dev;
 500         int ret;
 501
 502         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
 503                 return -EINVAL;
 504
 505         ps_bridge->aux.drm_dev = bridge->dev;
 506         ret = drm_dp_aux_register(&ps_bridge->aux);
 507         if (ret) {
 508                 dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
 509                 return ret;
 510         }
 511
 512         ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
 513         if (!ps_bridge->link) {
 514                 dev_err(dev, "failed to create device link");
 515                 ret = -EINVAL;
 516                 goto err_devlink;
 517         }
 518
 519         /* Attach the panel-bridge to the dsi bridge */
 520         ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
 521                                 &ps_bridge->bridge, flags);
 522         if (ret)
 523                 goto err_bridge_attach;
 524
 525         return 0;
 526
 527 err_bridge_attach:
 528         device_link_del(ps_bridge->link);
 529 err_devlink:
 530         drm_dp_aux_unregister(&ps_bridge->aux);
 531
 532         return ret;
 533 }
 534
 535 static void ps8640_bridge_detach(struct drm_bridge *bridge)
 536 {
 537         struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
 538
 539         drm_dp_aux_unregister(&ps_bridge->aux);
 540         if (ps_bridge->link)
 541                 device_link_del(ps_bridge->link);
 542 }
 543
 544 static void ps8640_runtime_disable(void *data)
 545 {
 546         pm_runtime_dont_use_autosuspend(data);
 547         pm_runtime_disable(data);
 548 }
 549
 550 static const struct drm_bridge_funcs ps8640_bridge_funcs = {
 551         .attach = ps8640_bridge_attach,
 552         .detach = ps8640_bridge_detach,
 553         .atomic_post_disable = ps8640_atomic_post_disable,
 554         .atomic_pre_enable = ps8640_atomic_pre_enable,
 555         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 556         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 557         .atomic_reset = drm_atomic_helper_bridge_reset,
 558 };
 559
 560 static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge)
 561 {
 562         struct device_node *in_ep, *dsi_node;
 563         struct mipi_dsi_device *dsi;
 564         struct mipi_dsi_host *host;
 565         const struct mipi_dsi_device_info info = { .type = "ps8640",
 566                                                    .channel = 0,
 567                                                    .node = NULL,
 568                                                  };
 569
 570         /* port@0 is ps8640 dsi input port */
 571         in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
 572         if (!in_ep)
 573                 return -ENODEV;
 574
 575         dsi_node = of_graph_get_remote_port_parent(in_ep);
 576         of_node_put(in_ep);
 577         if (!dsi_node)
 578                 return -ENODEV;
 579
 580         host = of_find_mipi_dsi_host_by_node(dsi_node);
 581         of_node_put(dsi_node);
 582         if (!host)
 583                 return -EPROBE_DEFER;
 584
 585         dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
 586         if (IS_ERR(dsi)) {
 587                 dev_err(dev, "failed to create dsi device\n");
 588                 return PTR_ERR(dsi);
 589         }
 590
 591         ps_bridge->dsi = dsi;
 592
 593         dsi->host = host;
 594         dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
 595                           MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
 596         dsi->format = MIPI_DSI_FMT_RGB888;
 597         dsi->lanes = NUM_MIPI_LANES;
 598
 599         return 0;
 600 }
 601
 602 static int ps8640_bridge_link_panel(struct drm_dp_aux *aux)
 603 {
 604         struct ps8640 *ps_bridge = aux_to_ps8640(aux);
 605         struct device *dev = aux->dev;
 606         struct device_node *np = dev->of_node;
 607         int ret;
 608
 609         /*
 610          * NOTE about returning -EPROBE_DEFER from this function: if we
 611          * return an error (most relevant to -EPROBE_DEFER) it will only
 612          * be passed out to ps8640_probe() if it called this directly (AKA the
 613          * panel isn't under the "aux-bus" node). That should be fine because
 614          * if the panel is under "aux-bus" it's guaranteed to have probed by
 615          * the time this function has been called.
 616          */
 617
 618         /* port@1 is ps8640 output port */
 619         ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
 620         if (IS_ERR(ps_bridge->panel_bridge))
 621                 return PTR_ERR(ps_bridge->panel_bridge);
 622
 623         ret = devm_drm_bridge_add(dev, &ps_bridge->bridge);
 624         if (ret)
 625                 return ret;
 626
 627         return devm_mipi_dsi_attach(dev, ps_bridge->dsi);
 628 }
 629
 630 static int ps8640_probe(struct i2c_client *client)
 631 {
 632         struct device *dev = &client->dev;
 633         struct ps8640 *ps_bridge;
 634         int ret;
 635         u32 i;
 636
 637         ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
 638         if (!ps_bridge)
 639                 return -ENOMEM;
 640
 641         mutex_init(&ps_bridge->aux_lock);
 642
 643         ps_bridge->supplies[0].supply = "vdd12";
 644         ps_bridge->supplies[1].supply = "vdd33";
 645         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
 646                                       ps_bridge->supplies);
 647         if (ret)
 648                 return ret;
 649
 650         ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
 651                                                    GPIOD_OUT_HIGH);
 652         if (IS_ERR(ps_bridge->gpio_powerdown))
 653                 return PTR_ERR(ps_bridge->gpio_powerdown);
 654
 655         /*
 656          * Assert the reset to avoid the bridge being initialized prematurely
 657          */
 658         ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
 659                                                GPIOD_OUT_HIGH);
 660         if (IS_ERR(ps_bridge->gpio_reset))
 661                 return PTR_ERR(ps_bridge->gpio_reset);
 662
 663         ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
 664         ps_bridge->bridge.of_node = dev->of_node;
 665         ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
 666
 667         /*
 668          * Get MIPI DSI resources early. These can return -EPROBE_DEFER so
 669          * we want to get them out of the way sooner.
 670          */
 671         ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge);
 672         if (ret)
 673                 return ret;
 674
 675         ps_bridge->page[PAGE0_DP_CNTL] = client;
 676
 677         ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
 678         if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]))
 679                 return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]);
 680
 681         for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
 682                 ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
 683                                                              client->adapter,
 684                                                              client->addr + i);
 685                 if (IS_ERR(ps_bridge->page[i]))
 686                         return PTR_ERR(ps_bridge->page[i]);
 687
 688                 ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
 689                                                             ps8640_regmap_config + i);
 690                 if (IS_ERR(ps_bridge->regmap[i]))
 691                         return PTR_ERR(ps_bridge->regmap[i]);
 692         }
 693
 694         i2c_set_clientdata(client, ps_bridge);
 695
 696         ps_bridge->aux.name = "parade-ps8640-aux";
 697         ps_bridge->aux.dev = dev;
 698         ps_bridge->aux.transfer = ps8640_aux_transfer;
 699         ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted;
 700         drm_dp_aux_init(&ps_bridge->aux);
 701
 702         pm_runtime_enable(dev);
 703         /*
 704          * Powering on ps8640 takes ~300ms. To avoid wasting time on power
 705          * cycling ps8640 too often, set autosuspend_delay to 2000ms to ensure
 706          * the bridge wouldn't suspend in between each _aux_transfer_msg() call
 707          * during EDID read (~20ms in my experiment) and in between the last
 708          * _aux_transfer_msg() call during EDID read and the _pre_enable() call
 709          * (~100ms in my experiment).
 710          */
 711         pm_runtime_set_autosuspend_delay(dev, 2000);
 712         pm_runtime_use_autosuspend(dev);
 713         pm_suspend_ignore_children(dev, true);
 714         ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
 715         if (ret)
 716                 return ret;
 717
 718         ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel);
 719
 720         /*
 721          * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to
 722          * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case
 723          * the function is allowed to -EPROBE_DEFER.
 724          */
 725         if (ret == -ENODEV)
 726                 return ps8640_bridge_link_panel(&ps_bridge->aux);
 727
 728         return ret;
 729 }
 730
 731 static const struct of_device_id ps8640_match[] = {
 732         { .compatible = "parade,ps8640" },
 733         { }
 734 };
 735 MODULE_DEVICE_TABLE(of, ps8640_match);
 736
 737 static struct i2c_driver ps8640_driver = {
 738         .probe = ps8640_probe,
 739         .driver = {
 740                 .name = "ps8640",
 741                 .of_match_table = ps8640_match,
 742                 .pm = &ps8640_pm_ops,
 743         },
 744 };
 745 module_i2c_driver(ps8640_driver);
 746
 747 MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
 748 MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
 749 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
 750 MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
 751 MODULE_LICENSE("GPL v2");