1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved.
7 #include <linux/gpio/consumer.h>
9 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/types.h>
18 #include <linux/workqueue.h>
20 #include <linux/of_graph.h>
21 #include <linux/of_platform.h>
23 #include <drm/display/drm_dp_aux_bus.h>
24 #include <drm/display/drm_dp_helper.h>
25 #include <drm/display/drm_hdcp_helper.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_bridge.h>
28 #include <drm/drm_edid.h>
29 #include <drm/drm_mipi_dsi.h>
30 #include <drm/drm_of.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_print.h>
33 #include <drm/drm_probe_helper.h>
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
37 #include <video/display_timing.h>
42 * There is a sync issue while access I2C register between AP(CPU) and
43 * internal firmware(OCM), to avoid the race condition, AP should access
44 * the reserved slave address before slave address occurs changes.
46 static int i2c_access_workaround(struct anx7625_data *ctx,
47 struct i2c_client *client)
50 struct device *dev = &client->dev;
53 if (client == ctx->last_client)
56 ctx->last_client = client;
58 if (client == ctx->i2c.tcpc_client)
59 offset = RSVD_00_ADDR;
60 else if (client == ctx->i2c.tx_p0_client)
61 offset = RSVD_D1_ADDR;
62 else if (client == ctx->i2c.tx_p1_client)
63 offset = RSVD_60_ADDR;
64 else if (client == ctx->i2c.rx_p0_client)
65 offset = RSVD_39_ADDR;
66 else if (client == ctx->i2c.rx_p1_client)
67 offset = RSVD_7F_ADDR;
69 offset = RSVD_00_ADDR;
71 ret = i2c_smbus_write_byte_data(client, offset, 0x00);
74 "fail to access i2c id=%x\n:%x",
75 client->addr, offset);
80 static int anx7625_reg_read(struct anx7625_data *ctx,
81 struct i2c_client *client, u8 reg_addr)
84 struct device *dev = &client->dev;
86 i2c_access_workaround(ctx, client);
88 ret = i2c_smbus_read_byte_data(client, reg_addr);
90 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n",
91 client->addr, reg_addr);
96 static int anx7625_reg_block_read(struct anx7625_data *ctx,
97 struct i2c_client *client,
98 u8 reg_addr, u8 len, u8 *buf)
101 struct device *dev = &client->dev;
103 i2c_access_workaround(ctx, client);
105 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf);
107 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n",
108 client->addr, reg_addr);
113 static int anx7625_reg_write(struct anx7625_data *ctx,
114 struct i2c_client *client,
115 u8 reg_addr, u8 reg_val)
118 struct device *dev = &client->dev;
120 i2c_access_workaround(ctx, client);
122 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val);
125 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x",
126 client->addr, reg_addr);
131 static int anx7625_reg_block_write(struct anx7625_data *ctx,
132 struct i2c_client *client,
133 u8 reg_addr, u8 len, u8 *buf)
136 struct device *dev = &client->dev;
138 i2c_access_workaround(ctx, client);
140 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf);
142 dev_err(dev, "write i2c block failed id=%x\n:%x",
143 client->addr, reg_addr);
148 static int anx7625_write_or(struct anx7625_data *ctx,
149 struct i2c_client *client,
154 val = anx7625_reg_read(ctx, client, offset);
158 return anx7625_reg_write(ctx, client, offset, (val | (mask)));
161 static int anx7625_write_and(struct anx7625_data *ctx,
162 struct i2c_client *client,
167 val = anx7625_reg_read(ctx, client, offset);
171 return anx7625_reg_write(ctx, client, offset, (val & (mask)));
174 static int anx7625_write_and_or(struct anx7625_data *ctx,
175 struct i2c_client *client,
176 u8 offset, u8 and_mask, u8 or_mask)
180 val = anx7625_reg_read(ctx, client, offset);
184 return anx7625_reg_write(ctx, client,
185 offset, (val & and_mask) | (or_mask));
188 static int anx7625_config_bit_matrix(struct anx7625_data *ctx)
192 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
193 AUDIO_CONTROL_REGISTER, 0x80);
194 for (i = 0; i < 13; i++)
195 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
196 VIDEO_BIT_MATRIX_12 + i,
202 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
204 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
207 static int wait_aux_op_finish(struct anx7625_data *ctx)
209 struct device *dev = ctx->dev;
213 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0,
215 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)),
219 DRM_DEV_ERROR(dev, "aux operation fail!\n");
223 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
225 if (val < 0 || (val & 0x0F)) {
226 DRM_DEV_ERROR(dev, "aux status %02x\n", val);
233 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address,
236 struct device *dev = ctx->dev;
238 u8 addrh, addrm, addrl;
240 bool is_write = !(op & DP_AUX_I2C_READ);
242 if (len > DP_AUX_MAX_PAYLOAD_BYTES) {
243 dev_err(dev, "exceed aux buffer len.\n");
250 addrl = address & 0xFF;
251 addrm = (address >> 8) & 0xFF;
252 addrh = (address >> 16) & 0xFF;
255 op &= ~DP_AUX_I2C_MOT;
256 cmd = DPCD_CMD(len, op);
258 /* Set command and length */
259 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
260 AP_AUX_COMMAND, cmd);
262 /* Set aux access address */
263 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
264 AP_AUX_ADDR_7_0, addrl);
265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
266 AP_AUX_ADDR_15_8, addrm);
267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
268 AP_AUX_ADDR_19_16, addrh);
271 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client,
272 AP_AUX_BUFF_START, len, buf);
273 /* Enable aux access */
274 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
275 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
278 dev_err(dev, "cannot access aux related register.\n");
282 ret = wait_aux_op_finish(ctx);
284 dev_err(dev, "aux IO error: wait aux op finish.\n");
292 /* Read done, read out dpcd data */
293 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
294 AP_AUX_BUFF_START, len, buf);
296 dev_err(dev, "read dpcd register failed\n");
303 static int anx7625_video_mute_control(struct anx7625_data *ctx,
309 /* Set mute on flag */
310 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
311 AP_AV_STATUS, AP_MIPI_MUTE);
312 /* Clear mipi RX en */
313 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
314 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN);
317 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
318 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
320 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
321 AP_AV_STATUS, AP_MIPI_RX_EN);
327 /* Reduction of fraction a/b */
328 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b)
330 unsigned long gcd_num;
331 unsigned long tmp_a, tmp_b;
334 gcd_num = gcd(*a, *b);
341 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) {
348 * In the end, make a, b larger to have higher ODFC PLL
349 * output frequency accuracy
351 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) {
360 static int anx7625_calculate_m_n(u32 pixelclock,
365 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
366 /* Pixel clock frequency is too high */
367 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n",
369 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
373 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
374 /* Pixel clock frequency is too low */
375 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n",
377 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
381 for (*post_divider = 1;
382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));)
385 if (*post_divider > POST_DIVIDER_MAX) {
386 for (*post_divider = 1;
388 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));)
391 if (*post_divider > POST_DIVIDER_MAX) {
392 DRM_ERROR("cannot find property post_divider(%d)\n",
398 /* Patch to improve the accuracy */
399 if (*post_divider == 7) {
400 /* 27,000,000 is not divisible by 7 */
402 } else if (*post_divider == 11) {
403 /* 27,000,000 is not divisible by 11 */
405 } else if ((*post_divider == 13) || (*post_divider == 14)) {
406 /* 27,000,000 is not divisible by 13 or 14 */
410 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) {
411 DRM_ERROR("act clock(%u) large than maximum(%lu)\n",
412 pixelclock * (*post_divider),
413 PLL_OUT_FREQ_ABS_MAX);
418 *n = XTAL_FRQ / (*post_divider);
420 anx7625_reduction_of_a_fraction(m, n);
425 static int anx7625_odfc_config(struct anx7625_data *ctx,
429 struct device *dev = ctx->dev;
431 /* Config input reference clock frequency 27MHz/19.2MHz */
432 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
433 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND));
434 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
435 (REF_CLK_27000KHZ << MIPI_FREF_D_IND));
437 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
438 MIPI_DIGITAL_PLL_8, 0x0f);
439 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
442 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */
443 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
444 ~MIPI_PLL_VCO_TUNE_REG_VAL);
447 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
449 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
453 DRM_DEV_ERROR(dev, "IO error.\n");
459 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz),
460 * anx7625 defined K ratio for matching MIPI input video clock and
461 * DP output video clock. Increase K value can match bigger video data
462 * variation. IVO panel has small variation than DP CTS spec, need
463 * decrease the K value.
465 static int anx7625_set_k_value(struct anx7625_data *ctx)
467 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;
469 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)
470 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
471 MIPI_DIGITAL_ADJ_1, 0x3B);
473 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
474 MIPI_DIGITAL_ADJ_1, 0x3D);
477 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
479 struct device *dev = ctx->dev;
485 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000,
486 &m, &n, &post_divider);
489 DRM_DEV_ERROR(dev, "cannot get property m n value.\n");
493 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n",
496 /* Configure pixel clock */
497 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
498 (ctx->dt.pixelclock.min / 1000) & 0xFF);
499 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
500 (ctx->dt.pixelclock.min / 1000) >> 8);
502 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
503 MIPI_LANE_CTRL_0, 0xfc);
504 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client,
505 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1);
508 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
509 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
510 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
511 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF);
512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
513 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8);
515 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
516 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF);
517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
518 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8);
520 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
521 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min);
522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
523 HORIZONTAL_FRONT_PORCH_H,
524 ctx->dt.hfront_porch.min >> 8);
526 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
527 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min);
528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
529 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8);
531 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
532 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min);
533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
534 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8);
536 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
537 ctx->dt.vactive.min);
538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
539 ctx->dt.vactive.min >> 8);
541 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
542 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min);
544 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
545 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min);
547 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
548 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min);
550 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
551 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff);
552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
553 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff);
554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
555 MIPI_PLL_M_NUM_7_0, (m & 0xff));
557 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
558 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff);
559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
560 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
564 anx7625_set_k_value(ctx);
566 ret |= anx7625_odfc_config(ctx, post_divider - 1);
569 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n");
574 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx)
577 struct device *dev = ctx->dev;
579 /* Swap MIPI-DSI data lane 3 P and N */
580 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP);
582 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n");
586 val |= (1 << MIPI_SWAP_CH3);
587 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val);
590 static int anx7625_api_dsi_config(struct anx7625_data *ctx)
594 struct device *dev = ctx->dev;
596 /* Swap MIPI-DSI data lane 3 P and N */
597 ret = anx7625_swap_dsi_lane3(ctx);
599 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n");
603 /* DSI clock settings */
604 val = (0 << MIPI_HS_PWD_CLK) |
605 (0 << MIPI_HS_RT_CLK) |
607 (1 << MIPI_CLK_RT_MANUAL_PD_EN) |
608 (1 << MIPI_CLK_HS_MANUAL_PD_EN) |
609 (0 << MIPI_CLK_DET_DET_BYPASS) |
610 (0 << MIPI_CLK_MISS_CTRL) |
611 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN);
612 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
613 MIPI_PHY_CONTROL_3, val);
616 * Decreased HS prepare timing delay from 160ns to 80ns work with
617 * a) Dragon board 810 series (Qualcomm AP)
618 * b) Moving Pixel DSI source (PG3A pattern generator +
619 * P332 D-PHY Probe) default D-PHY timing
622 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
623 MIPI_TIME_HS_PRPR, 0x10);
626 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
627 SELECT_DSI << MIPI_DPI_SELECT);
629 ret |= anx7625_dsi_video_timing_config(ctx);
631 DRM_DEV_ERROR(dev, "dsi video timing config fail\n");
635 /* Toggle m, n ready */
636 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
637 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY));
638 usleep_range(1000, 1100);
639 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
640 MIPI_M_NUM_READY | MIPI_N_NUM_READY);
642 /* Configure integer stable register */
643 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
644 MIPI_VIDEO_STABLE_CNT, 0x02);
645 /* Power on MIPI RX */
646 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
647 MIPI_LANE_CTRL_10, 0x00);
648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
649 MIPI_LANE_CTRL_10, 0x80);
652 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n");
657 static int anx7625_dsi_config(struct anx7625_data *ctx)
659 struct device *dev = ctx->dev;
662 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n");
665 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
666 R_DSC_CTRL_0, ~DSC_EN);
668 ret |= anx7625_api_dsi_config(ctx);
671 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n");
676 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
677 AP_AV_STATUS, AP_MIPI_RX_EN);
678 /* Clear mute flag */
679 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
680 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
682 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n");
684 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n");
689 static int anx7625_api_dpi_config(struct anx7625_data *ctx)
691 struct device *dev = ctx->dev;
692 u16 freq = ctx->dt.pixelclock.min / 1000;
695 /* configure pixel clock */
696 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
697 PIXEL_CLOCK_L, freq & 0xFF);
698 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
699 PIXEL_CLOCK_H, (freq >> 8));
702 /* set to DPI PLL module sel */
703 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
704 MIPI_DIGITAL_PLL_9, 0x20);
705 /* power down MIPI */
706 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
707 MIPI_LANE_CTRL_10, 0x08);
708 /* enable DPI mode */
709 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
710 MIPI_DIGITAL_PLL_18, 0x1C);
712 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
713 VIDEO_CONTROL_0, 0x06);
715 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n");
720 static int anx7625_dpi_config(struct anx7625_data *ctx)
722 struct device *dev = ctx->dev;
725 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n");
728 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
729 R_DSC_CTRL_0, ~DSC_EN);
731 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n");
735 ret = anx7625_config_bit_matrix(ctx);
737 DRM_DEV_ERROR(dev, "config bit matrix failed.\n");
741 ret = anx7625_api_dpi_config(ctx);
743 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n");
748 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
749 AP_AV_STATUS, AP_MIPI_RX_EN);
750 /* clear mute flag */
751 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
752 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
754 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n");
759 static int anx7625_read_flash_status(struct anx7625_data *ctx)
761 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
764 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
767 struct device *dev = ctx->dev;
768 u8 ident[FLASH_BUF_LEN];
770 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
771 FLASH_ADDR_HIGH, 0x91);
772 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
773 FLASH_ADDR_LOW, 0xA0);
775 dev_err(dev, "IO error : set key flash address.\n");
779 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
780 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
781 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
782 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
784 dev_err(dev, "IO error : set key flash len.\n");
788 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
789 R_FLASH_RW_CTRL, FLASH_READ);
790 ret |= readx_poll_timeout(anx7625_read_flash_status,
792 ((val & FLASH_DONE) || (val < 0)),
796 dev_err(dev, "flash read access fail!\n");
800 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
802 FLASH_BUF_LEN, ident);
804 dev_err(dev, "read flash data fail!\n");
808 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
814 static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
817 struct device *dev = ctx->dev;
819 /* Select HDCP 1.4 KEY */
820 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
822 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
823 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8);
824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
825 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF);
826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
827 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12);
828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
829 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4);
831 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
835 /* Enable HDCP 1.4 KEY load */
836 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
837 R_RAM_CTRL, DECRYPT_EN | LOAD_START);
838 dev_dbg(dev, "load HDCP 1.4 key done\n");
842 static int anx7625_hdcp_disable(struct anx7625_data *ctx)
845 struct device *dev = ctx->dev;
847 dev_dbg(dev, "disable HDCP 1.4\n");
850 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
852 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
853 /* Interrupt for DRM */
854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
856 dev_err(dev, "fail to disable HDCP\n");
858 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
859 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF);
862 static int anx7625_hdcp_enable(struct anx7625_data *ctx)
866 struct device *dev = ctx->dev;
868 ret = anx7625_hdcp_key_probe(ctx);
870 dev_dbg(dev, "no key found, not to do hdcp\n");
874 /* Read downstream capability */
875 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, DP_AUX_HDCP_BCAPS, 1, &bcap);
879 if (!(bcap & DP_BCAPS_HDCP_CAPABLE)) {
880 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap);
884 dev_dbg(dev, "enable HDCP 1.4\n");
886 /* First clear HDCP state */
887 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
889 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
890 usleep_range(1000, 1100);
891 /* Second clear HDCP state */
892 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
894 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
896 /* Set time for waiting KSVR */
897 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
898 SP_TX_WAIT_KSVR_TIME, 0xc8);
899 /* Set time for waiting R0 */
900 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
901 SP_TX_WAIT_R0_TIME, 0xb0);
902 ret |= anx7625_hdcp_key_load(ctx);
904 pr_warn("prepare HDCP key failed.\n");
908 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
911 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
912 /* Interrupt for DRM */
913 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
915 dev_err(dev, "fail to enable HDCP\n");
917 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
918 TX_HDCP_CTRL0, HARD_AUTH_EN);
921 static void anx7625_dp_start(struct anx7625_data *ctx)
924 struct device *dev = ctx->dev;
927 if (!ctx->display_timing_valid) {
928 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n");
932 dev_dbg(dev, "set downstream sink into normal\n");
933 /* Downstream sink enter into normal mode */
934 data = DP_SET_POWER_D0;
935 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data);
937 dev_err(dev, "IO error : set sink into normal mode fail\n");
940 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
942 if (ctx->pdata.is_dpi)
943 ret = anx7625_dpi_config(ctx);
945 ret = anx7625_dsi_config(ctx);
948 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
950 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
955 static void anx7625_dp_stop(struct anx7625_data *ctx)
957 struct device *dev = ctx->dev;
961 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
964 * Video disable: 0x72:08 bit 7 = 0;
965 * Audio disable: 0x70:87 bit 0 = 0;
967 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe);
968 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
970 ret |= anx7625_video_mute_control(ctx, 1);
972 dev_dbg(dev, "notify downstream enter into standby\n");
973 /* Downstream monitor enter into standby mode */
974 data = DP_SET_POWER_D3;
975 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data);
977 DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
979 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
984 static int sp_tx_rst_aux(struct anx7625_data *ctx)
988 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
990 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
995 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset)
999 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1000 AP_AUX_BUFF_START, offset);
1001 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1002 AP_AUX_COMMAND, 0x04);
1003 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1004 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1005 return (ret | wait_aux_op_finish(ctx));
1008 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd)
1012 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1013 AP_AUX_COMMAND, len_cmd);
1014 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1015 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1016 return (ret | wait_aux_op_finish(ctx));
1019 static int sp_tx_get_edid_block(struct anx7625_data *ctx)
1022 struct device *dev = ctx->dev;
1024 sp_tx_aux_wr(ctx, 0x7e);
1025 sp_tx_aux_rd(ctx, 0x01);
1026 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
1028 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n");
1032 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1);
1034 if (c > MAX_EDID_BLOCK)
1040 static int edid_read(struct anx7625_data *ctx,
1041 u8 offset, u8 *pblock_buf)
1044 struct device *dev = ctx->dev;
1046 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1047 sp_tx_aux_wr(ctx, offset);
1048 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1049 ret = sp_tx_aux_rd(ctx, 0xf1);
1052 ret = sp_tx_rst_aux(ctx);
1053 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n");
1055 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1057 MAX_DPCD_BUFFER_SIZE,
1064 if (cnt > EDID_TRY_CNT)
1070 static int segments_edid_read(struct anx7625_data *ctx,
1071 u8 segment, u8 *buf, u8 offset)
1075 struct device *dev = ctx->dev;
1077 /* Write address only */
1078 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1079 AP_AUX_ADDR_7_0, 0x30);
1080 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1081 AP_AUX_COMMAND, 0x04);
1082 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1084 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN);
1086 ret |= wait_aux_op_finish(ctx);
1087 /* Write segment address */
1088 ret |= sp_tx_aux_wr(ctx, segment);
1090 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1091 AP_AUX_ADDR_7_0, 0x50);
1093 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n");
1097 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1098 sp_tx_aux_wr(ctx, offset);
1099 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1100 ret = sp_tx_aux_rd(ctx, 0xf1);
1103 ret = sp_tx_rst_aux(ctx);
1104 DRM_DEV_ERROR(dev, "segment read fail, reset!\n");
1106 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1108 MAX_DPCD_BUFFER_SIZE, buf);
1114 if (cnt > EDID_TRY_CNT)
1120 static int sp_tx_edid_read(struct anx7625_data *ctx,
1121 u8 *pedid_blocks_buf)
1125 int count, blocks_num;
1126 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE];
1128 int g_edid_break = 0;
1130 struct device *dev = ctx->dev;
1132 /* Address initial */
1133 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1134 AP_AUX_ADDR_7_0, 0x50);
1135 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1136 AP_AUX_ADDR_15_8, 0);
1137 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
1138 AP_AUX_ADDR_19_16, 0xf0);
1140 DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
1144 blocks_num = sp_tx_get_edid_block(ctx);
1154 for (i = 0; i < 8; i++) {
1155 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE;
1156 g_edid_break = edid_read(ctx, offset,
1159 if (g_edid_break < 0)
1162 memcpy(&pedid_blocks_buf[offset],
1164 MAX_DPCD_BUFFER_SIZE);
1171 for (j = 0; j < 8; j++) {
1172 edid_pos = (j + count * 8) *
1173 MAX_DPCD_BUFFER_SIZE;
1175 if (g_edid_break == 1)
1178 ret = segments_edid_read(ctx, count / 2,
1179 pblock_buf, offset);
1183 memcpy(&pedid_blocks_buf[edid_pos],
1185 MAX_DPCD_BUFFER_SIZE);
1186 offset = offset + 0x10;
1193 for (j = 0; j < 8; j++) {
1194 edid_pos = (j + count * 8) *
1195 MAX_DPCD_BUFFER_SIZE;
1196 if (g_edid_break == 1)
1199 ret = segments_edid_read(ctx, count / 2,
1200 pblock_buf, offset);
1204 memcpy(&pedid_blocks_buf[edid_pos],
1206 MAX_DPCD_BUFFER_SIZE);
1207 offset = offset + 0x10;
1217 } while (blocks_num >= count);
1219 /* Check edid data */
1220 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) {
1221 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n");
1225 /* Reset aux channel */
1226 ret = sp_tx_rst_aux(ctx);
1228 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n");
1232 return (blocks_num + 1);
1235 static void anx7625_power_on(struct anx7625_data *ctx)
1237 struct device *dev = ctx->dev;
1240 if (!ctx->pdata.low_power_mode) {
1241 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1245 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) {
1246 ret = regulator_enable(ctx->pdata.supplies[i].consumer);
1248 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n",
1252 usleep_range(2000, 2100);
1255 usleep_range(11000, 12000);
1257 /* Power on pin enable */
1258 gpiod_set_value(ctx->pdata.gpio_p_on, 1);
1259 usleep_range(10000, 11000);
1260 /* Power reset pin enable */
1261 gpiod_set_value(ctx->pdata.gpio_reset, 1);
1262 usleep_range(10000, 11000);
1264 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n");
1267 for (--i; i >= 0; i--)
1268 regulator_disable(ctx->pdata.supplies[i].consumer);
1271 static void anx7625_power_standby(struct anx7625_data *ctx)
1273 struct device *dev = ctx->dev;
1276 if (!ctx->pdata.low_power_mode) {
1277 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1281 gpiod_set_value(ctx->pdata.gpio_reset, 0);
1282 usleep_range(1000, 1100);
1283 gpiod_set_value(ctx->pdata.gpio_p_on, 0);
1284 usleep_range(1000, 1100);
1286 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies),
1287 ctx->pdata.supplies);
1289 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret);
1291 DRM_DEV_DEBUG_DRIVER(dev, "power down\n");
1294 /* Basic configurations of ANX7625 */
1295 static void anx7625_config(struct anx7625_data *ctx)
1297 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1298 XTAL_FRQ_SEL, XTAL_FRQ_27M);
1301 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
1303 struct device *dev = ctx->dev;
1306 /* Reset main ocm */
1307 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40);
1309 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1310 AP_AV_STATUS, AP_DISABLE_PD);
1311 /* Release main ocm */
1312 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00);
1315 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n");
1317 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n");
1320 static int anx7625_ocm_loading_check(struct anx7625_data *ctx)
1323 struct device *dev = ctx->dev;
1325 /* Check interface workable */
1326 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1329 DRM_DEV_ERROR(dev, "IO error : access flash load.\n");
1332 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK)
1335 anx7625_disable_pd_protocol(ctx);
1337 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,",
1338 anx7625_reg_read(ctx,
1339 ctx->i2c.rx_p0_client,
1341 anx7625_reg_read(ctx,
1342 ctx->i2c.rx_p0_client,
1344 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n",
1345 ANX7625_DRV_VERSION);
1350 static void anx7625_power_on_init(struct anx7625_data *ctx)
1354 for (retry_count = 0; retry_count < 3; retry_count++) {
1355 anx7625_power_on(ctx);
1356 anx7625_config(ctx);
1358 for (i = 0; i < OCM_LOADING_TIME; i++) {
1359 if (!anx7625_ocm_loading_check(ctx))
1361 usleep_range(1000, 1100);
1363 anx7625_power_standby(ctx);
1367 static void anx7625_init_gpio(struct anx7625_data *platform)
1369 struct device *dev = platform->dev;
1371 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n");
1373 /* Gpio for chip power enable */
1374 platform->pdata.gpio_p_on =
1375 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);
1376 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) {
1377 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n");
1378 platform->pdata.gpio_p_on = NULL;
1381 /* Gpio for chip reset */
1382 platform->pdata.gpio_reset =
1383 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1384 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) {
1385 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n");
1386 platform->pdata.gpio_reset = NULL;
1389 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) {
1390 platform->pdata.low_power_mode = 1;
1391 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n",
1392 desc_to_gpio(platform->pdata.gpio_p_on),
1393 desc_to_gpio(platform->pdata.gpio_reset));
1395 platform->pdata.low_power_mode = 0;
1396 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n");
1400 static void anx7625_stop_dp_work(struct anx7625_data *ctx)
1402 ctx->hpd_status = 0;
1403 ctx->hpd_high_cnt = 0;
1406 static void anx7625_start_dp_work(struct anx7625_data *ctx)
1409 struct device *dev = ctx->dev;
1411 if (ctx->hpd_high_cnt >= 2) {
1412 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n");
1416 ctx->hpd_status = 1;
1417 ctx->hpd_high_cnt++;
1419 /* Not support HDCP */
1420 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
1423 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
1424 /* Interrupt for DRM */
1425 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
1427 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n");
1431 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86);
1435 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret);
1438 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
1442 /* Set irq detect window to 2ms */
1443 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1444 HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF);
1445 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1446 HPD_DET_TIMER_BIT8_15,
1447 (HPD_TIME >> 8) & 0xFF);
1448 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1449 HPD_DET_TIMER_BIT16_23,
1450 (HPD_TIME >> 16) & 0xFF);
1454 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
1457 static int _anx7625_hpd_polling(struct anx7625_data *ctx,
1458 unsigned long wait_us)
1461 struct device *dev = ctx->dev;
1463 /* Interrupt mode, no need poll HPD status, just return */
1464 if (ctx->pdata.intp_irq)
1467 ret = readx_poll_timeout(anx7625_read_hpd_status_p0,
1469 ((val & HPD_STATUS) || (val < 0)),
1473 DRM_DEV_ERROR(dev, "no hpd.\n");
1477 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val);
1478 anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1479 INTR_ALERT_1, 0xFF);
1480 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1481 INTERFACE_CHANGE_INT, 0);
1483 anx7625_start_dp_work(ctx);
1485 if (!ctx->pdata.panel_bridge && ctx->bridge_attached)
1486 drm_helper_hpd_irq_event(ctx->bridge.dev);
1491 static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux,
1492 unsigned long wait_us)
1494 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1495 struct device *dev = ctx->dev;
1498 pm_runtime_get_sync(dev);
1499 ret = _anx7625_hpd_polling(ctx, wait_us);
1500 pm_runtime_mark_last_busy(dev);
1501 pm_runtime_put_autosuspend(dev);
1506 static void anx7625_remove_edid(struct anx7625_data *ctx)
1508 ctx->slimport_edid_p.edid_block_num = -1;
1511 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)
1515 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++)
1516 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1517 DP_TX_LANE0_SWING_REG0 + i,
1518 ctx->pdata.lane0_reg_data[i]);
1520 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++)
1521 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1522 DP_TX_LANE1_SWING_REG0 + i,
1523 ctx->pdata.lane1_reg_data[i]);
1526 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
1528 struct device *dev = ctx->dev;
1531 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n",
1535 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n");
1536 anx7625_remove_edid(ctx);
1537 anx7625_stop_dp_work(ctx);
1539 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n");
1540 anx7625_start_dp_work(ctx);
1541 anx7625_dp_adjust_swing(ctx);
1545 static int anx7625_hpd_change_detect(struct anx7625_data *ctx)
1547 int intr_vector, status;
1548 struct device *dev = ctx->dev;
1550 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1551 INTR_ALERT_1, 0xFF);
1553 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n");
1557 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1558 INTERFACE_CHANGE_INT);
1559 if (intr_vector < 0) {
1560 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n");
1563 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector);
1564 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1565 INTERFACE_CHANGE_INT,
1566 intr_vector & (~intr_vector));
1568 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n");
1572 if (!(intr_vector & HPD_STATUS_CHANGE))
1575 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1578 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n");
1582 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status);
1583 dp_hpd_change_handler(ctx, status & HPD_STATUS);
1588 static void anx7625_work_func(struct work_struct *work)
1591 struct anx7625_data *ctx = container_of(work,
1592 struct anx7625_data, work);
1594 mutex_lock(&ctx->lock);
1596 if (pm_runtime_suspended(ctx->dev)) {
1597 mutex_unlock(&ctx->lock);
1601 event = anx7625_hpd_change_detect(ctx);
1603 mutex_unlock(&ctx->lock);
1608 if (ctx->bridge_attached)
1609 drm_helper_hpd_irq_event(ctx->bridge.dev);
1612 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data)
1614 struct anx7625_data *ctx = (struct anx7625_data *)data;
1616 queue_work(ctx->workqueue, &ctx->work);
1621 static int anx7625_get_swing_setting(struct device *dev,
1622 struct anx7625_platform_data *pdata)
1626 if (of_get_property(dev->of_node,
1627 "analogix,lane0-swing", &num_regs)) {
1628 if (num_regs > DP_TX_SWING_REG_CNT)
1629 num_regs = DP_TX_SWING_REG_CNT;
1631 pdata->dp_lane0_swing_reg_cnt = num_regs;
1632 of_property_read_u8_array(dev->of_node, "analogix,lane0-swing",
1633 pdata->lane0_reg_data, num_regs);
1636 if (of_get_property(dev->of_node,
1637 "analogix,lane1-swing", &num_regs)) {
1638 if (num_regs > DP_TX_SWING_REG_CNT)
1639 num_regs = DP_TX_SWING_REG_CNT;
1641 pdata->dp_lane1_swing_reg_cnt = num_regs;
1642 of_property_read_u8_array(dev->of_node, "analogix,lane1-swing",
1643 pdata->lane1_reg_data, num_regs);
1649 static int anx7625_parse_dt(struct device *dev,
1650 struct anx7625_platform_data *pdata)
1652 struct device_node *np = dev->of_node, *ep0;
1653 int bus_type, mipi_lanes;
1655 anx7625_get_swing_setting(dev, pdata);
1657 pdata->is_dpi = 0; /* default dsi mode */
1658 of_node_put(pdata->mipi_host_node);
1659 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0);
1660 if (!pdata->mipi_host_node) {
1661 DRM_DEV_ERROR(dev, "fail to get internal panel.\n");
1666 mipi_lanes = MAX_LANES_SUPPORT;
1667 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0);
1669 if (of_property_read_u32(ep0, "bus-type", &bus_type))
1672 mipi_lanes = drm_of_get_data_lanes_count(ep0, 1, MAX_LANES_SUPPORT);
1676 if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */
1679 pdata->mipi_lanes = MAX_LANES_SUPPORT;
1681 pdata->mipi_lanes = mipi_lanes;
1684 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n");
1686 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n");
1688 if (of_property_read_bool(np, "analogix,audio-enable"))
1689 pdata->audio_en = 1;
1694 static int anx7625_parse_dt_panel(struct device *dev,
1695 struct anx7625_platform_data *pdata)
1697 struct device_node *np = dev->of_node;
1699 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
1700 if (IS_ERR(pdata->panel_bridge)) {
1701 if (PTR_ERR(pdata->panel_bridge) == -ENODEV) {
1702 pdata->panel_bridge = NULL;
1706 return PTR_ERR(pdata->panel_bridge);
1709 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n");
1714 static bool anx7625_of_panel_on_aux_bus(struct device *dev)
1716 struct device_node *bus, *panel;
1718 bus = of_get_child_by_name(dev->of_node, "aux-bus");
1722 panel = of_get_child_by_name(bus, "panel");
1731 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge)
1733 return container_of(bridge, struct anx7625_data, bridge);
1736 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux,
1737 struct drm_dp_aux_msg *msg)
1739 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1740 struct device *dev = ctx->dev;
1741 u8 request = msg->request & ~DP_AUX_I2C_MOT;
1744 pm_runtime_get_sync(dev);
1747 case DP_AUX_NATIVE_WRITE:
1748 case DP_AUX_I2C_WRITE:
1749 case DP_AUX_NATIVE_READ:
1750 case DP_AUX_I2C_READ:
1756 ret = anx7625_aux_trans(ctx, msg->request, msg->address,
1757 msg->size, msg->buffer);
1758 pm_runtime_mark_last_busy(dev);
1759 pm_runtime_put_autosuspend(dev);
1764 static struct edid *anx7625_get_edid(struct anx7625_data *ctx)
1766 struct device *dev = ctx->dev;
1767 struct s_edid_data *p_edid = &ctx->slimport_edid_p;
1771 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL);
1773 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n");
1777 if (ctx->slimport_edid_p.edid_block_num > 0) {
1778 memcpy(edid, ctx->slimport_edid_p.edid_raw_data,
1780 return (struct edid *)edid;
1783 pm_runtime_get_sync(dev);
1784 _anx7625_hpd_polling(ctx, 5000 * 100);
1785 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data);
1786 pm_runtime_put_sync(dev);
1789 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num);
1794 p_edid->edid_block_num = edid_num;
1796 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE);
1797 return (struct edid *)edid;
1800 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)
1802 struct device *dev = ctx->dev;
1804 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n");
1806 if (ctx->pdata.panel_bridge)
1807 return connector_status_connected;
1809 return ctx->hpd_status ? connector_status_connected :
1810 connector_status_disconnected;
1813 static int anx7625_audio_hw_params(struct device *dev, void *data,
1814 struct hdmi_codec_daifmt *fmt,
1815 struct hdmi_codec_params *params)
1817 struct anx7625_data *ctx = dev_get_drvdata(dev);
1821 if (anx7625_sink_detect(ctx) == connector_status_disconnected) {
1822 DRM_DEV_DEBUG_DRIVER(dev, "DP not connected\n");
1826 if (fmt->fmt != HDMI_DSP_A && fmt->fmt != HDMI_I2S) {
1827 DRM_DEV_ERROR(dev, "only supports DSP_A & I2S\n");
1831 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n",
1832 params->sample_rate, params->sample_width,
1833 params->cea.channels);
1835 if (fmt->fmt == HDMI_DSP_A)
1836 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1837 AUDIO_CHANNEL_STATUS_6,
1841 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1842 AUDIO_CHANNEL_STATUS_6,
1847 switch (params->sample_width) {
1849 wl = AUDIO_W_LEN_16_20MAX;
1852 wl = AUDIO_W_LEN_18_20MAX;
1855 wl = AUDIO_W_LEN_20_20MAX;
1858 wl = AUDIO_W_LEN_24_24MAX;
1861 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
1862 params->sample_width);
1865 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1866 AUDIO_CHANNEL_STATUS_5,
1870 switch (params->cea.channels) {
1884 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
1885 params->cea.channels);
1888 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1889 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5);
1891 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
1892 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT);
1894 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client,
1895 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT);
1898 switch (params->sample_rate) {
1900 rate = AUDIO_FS_32K;
1903 rate = AUDIO_FS_441K;
1906 rate = AUDIO_FS_48K;
1909 rate = AUDIO_FS_882K;
1912 rate = AUDIO_FS_96K;
1915 rate = AUDIO_FS_1764K;
1918 rate = AUDIO_FS_192K;
1921 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support",
1922 params->sample_rate);
1925 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1926 AUDIO_CHANNEL_STATUS_4,
1928 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1929 AP_AV_STATUS, AP_AUDIO_CHG);
1931 DRM_DEV_ERROR(dev, "IO error : config audio.\n");
1938 static void anx7625_audio_shutdown(struct device *dev, void *data)
1940 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n");
1943 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component,
1944 struct device_node *endpoint)
1946 struct of_endpoint of_ep;
1949 ret = of_graph_parse_endpoint(endpoint, &of_ep);
1954 * HDMI sound should be located at external DPI port
1955 * Didn't have good way to check where is internal(DSI)
1956 * or external(DPI) bridge
1962 anx7625_audio_update_connector_status(struct anx7625_data *ctx,
1963 enum drm_connector_status status)
1965 if (ctx->plugged_cb && ctx->codec_dev) {
1966 ctx->plugged_cb(ctx->codec_dev,
1967 status == connector_status_connected);
1971 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data,
1972 hdmi_codec_plugged_cb fn,
1973 struct device *codec_dev)
1975 struct anx7625_data *ctx = data;
1977 ctx->plugged_cb = fn;
1978 ctx->codec_dev = codec_dev;
1979 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx));
1984 static int anx7625_audio_get_eld(struct device *dev, void *data,
1985 u8 *buf, size_t len)
1987 struct anx7625_data *ctx = dev_get_drvdata(dev);
1989 if (!ctx->connector) {
1990 /* Pass en empty ELD if connector not available */
1991 memset(buf, 0, len);
1993 dev_dbg(dev, "audio copy eld\n");
1994 memcpy(buf, ctx->connector->eld,
1995 min(sizeof(ctx->connector->eld), len));
2001 static const struct hdmi_codec_ops anx7625_codec_ops = {
2002 .hw_params = anx7625_audio_hw_params,
2003 .audio_shutdown = anx7625_audio_shutdown,
2004 .get_eld = anx7625_audio_get_eld,
2005 .get_dai_id = anx7625_hdmi_i2s_get_dai_id,
2006 .hook_plugged_cb = anx7625_audio_hook_plugged_cb,
2009 static void anx7625_unregister_audio(struct anx7625_data *ctx)
2011 struct device *dev = ctx->dev;
2013 if (ctx->audio_pdev) {
2014 platform_device_unregister(ctx->audio_pdev);
2015 ctx->audio_pdev = NULL;
2018 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME);
2021 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx)
2023 struct hdmi_codec_pdata codec_data = {
2024 .ops = &anx7625_codec_ops,
2025 .max_i2s_channels = 8,
2030 ctx->audio_pdev = platform_device_register_data(dev,
2031 HDMI_CODEC_DRV_NAME,
2032 PLATFORM_DEVID_AUTO,
2034 sizeof(codec_data));
2036 if (IS_ERR(ctx->audio_pdev))
2037 return PTR_ERR(ctx->audio_pdev);
2039 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME);
2044 static int anx7625_setup_dsi_device(struct anx7625_data *ctx)
2046 struct mipi_dsi_device *dsi;
2047 struct device *dev = ctx->dev;
2048 struct mipi_dsi_host *host;
2049 const struct mipi_dsi_device_info info = {
2055 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
2057 DRM_DEV_ERROR(dev, "fail to find dsi host.\n");
2058 return -EPROBE_DEFER;
2061 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
2063 DRM_DEV_ERROR(dev, "fail to create dsi device.\n");
2067 dsi->lanes = ctx->pdata.mipi_lanes;
2068 dsi->format = MIPI_DSI_FMT_RGB888;
2069 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
2070 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2071 MIPI_DSI_MODE_VIDEO_HSE |
2072 MIPI_DSI_HS_PKT_END_ALIGNED;
2079 static int anx7625_attach_dsi(struct anx7625_data *ctx)
2081 struct device *dev = ctx->dev;
2084 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
2086 ret = devm_mipi_dsi_attach(dev, ctx->dsi);
2088 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
2092 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");
2097 static void hdcp_check_work_func(struct work_struct *work)
2100 struct delayed_work *dwork;
2101 struct anx7625_data *ctx;
2103 struct drm_device *drm_dev;
2105 dwork = to_delayed_work(work);
2106 ctx = container_of(dwork, struct anx7625_data, hdcp_work);
2109 if (!ctx->connector) {
2110 dev_err(dev, "HDCP connector is null!");
2114 drm_dev = ctx->connector->dev;
2115 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2116 mutex_lock(&ctx->hdcp_wq_lock);
2118 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
2119 dev_dbg(dev, "sink HDCP status check: %.02x\n", status);
2120 if (status & BIT(1)) {
2121 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
2122 drm_hdcp_update_content_protection(ctx->connector,
2124 dev_dbg(dev, "update CP to ENABLE\n");
2127 mutex_unlock(&ctx->hdcp_wq_lock);
2128 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2131 static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
2132 struct drm_connector_state *state)
2134 struct device *dev = ctx->dev;
2137 dev_dbg(dev, "hdcp state check\n");
2138 cp = state->content_protection;
2140 if (cp == ctx->hdcp_cp)
2143 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
2145 dev_dbg(dev, "enable HDCP\n");
2146 anx7625_hdcp_enable(ctx);
2148 queue_delayed_work(ctx->hdcp_workqueue,
2150 msecs_to_jiffies(2000));
2154 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
2155 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2156 dev_err(dev, "current CP is not ENABLED\n");
2159 anx7625_hdcp_disable(ctx);
2160 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
2161 drm_hdcp_update_content_protection(ctx->connector,
2163 dev_dbg(dev, "update CP to UNDESIRE\n");
2166 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2167 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n");
2174 static int anx7625_bridge_attach(struct drm_bridge *bridge,
2175 enum drm_bridge_attach_flags flags)
2177 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2179 struct device *dev = ctx->dev;
2181 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n");
2182 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
2185 if (!bridge->encoder) {
2186 DRM_DEV_ERROR(dev, "Parent encoder object not found");
2190 ctx->aux.drm_dev = bridge->dev;
2191 err = drm_dp_aux_register(&ctx->aux);
2193 dev_err(dev, "failed to register aux channel: %d\n", err);
2197 if (ctx->pdata.panel_bridge) {
2198 err = drm_bridge_attach(bridge->encoder,
2199 ctx->pdata.panel_bridge,
2200 &ctx->bridge, flags);
2205 ctx->bridge_attached = 1;
2210 static void anx7625_bridge_detach(struct drm_bridge *bridge)
2212 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2214 drm_dp_aux_unregister(&ctx->aux);
2217 static enum drm_mode_status
2218 anx7625_bridge_mode_valid(struct drm_bridge *bridge,
2219 const struct drm_display_info *info,
2220 const struct drm_display_mode *mode)
2222 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2223 struct device *dev = ctx->dev;
2225 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n");
2227 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */
2228 if (mode->clock > SUPPORT_PIXEL_CLOCK) {
2229 DRM_DEV_DEBUG_DRIVER(dev,
2230 "drm mode invalid, pixelclock too high.\n");
2231 return MODE_CLOCK_HIGH;
2234 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n");
2239 static void anx7625_bridge_mode_set(struct drm_bridge *bridge,
2240 const struct drm_display_mode *old_mode,
2241 const struct drm_display_mode *mode)
2243 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2244 struct device *dev = ctx->dev;
2246 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n");
2248 ctx->dt.pixelclock.min = mode->clock;
2249 ctx->dt.hactive.min = mode->hdisplay;
2250 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start;
2251 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay;
2252 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end;
2253 ctx->dt.vactive.min = mode->vdisplay;
2254 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start;
2255 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay;
2256 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end;
2258 ctx->display_timing_valid = 1;
2260 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min);
2261 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n",
2262 ctx->dt.hactive.min,
2263 ctx->dt.hsync_len.min,
2264 ctx->dt.hfront_porch.min,
2265 ctx->dt.hback_porch.min);
2266 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n",
2267 ctx->dt.vactive.min,
2268 ctx->dt.vsync_len.min,
2269 ctx->dt.vfront_porch.min,
2270 ctx->dt.vback_porch.min);
2271 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n",
2274 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n",
2277 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n",
2280 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n",
2285 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
2286 const struct drm_display_mode *mode,
2287 struct drm_display_mode *adj)
2289 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2290 struct device *dev = ctx->dev;
2291 u32 hsync, hfp, hbp, hblanking;
2292 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj;
2293 u32 vref, adj_clock;
2295 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n");
2297 /* No need fixup for external monitor */
2298 if (!ctx->pdata.panel_bridge)
2301 hsync = mode->hsync_end - mode->hsync_start;
2302 hfp = mode->hsync_start - mode->hdisplay;
2303 hbp = mode->htotal - mode->hsync_end;
2304 hblanking = mode->htotal - mode->hdisplay;
2306 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n");
2307 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2308 hsync, hfp, hbp, adj->clock);
2309 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2310 adj->hsync_start, adj->hsync_end, adj->htotal);
2315 adj_hblanking = hblanking;
2317 /* HFP needs to be even */
2323 /* HBP needs to be even */
2329 /* HSYNC needs to be even */
2331 if (adj_hblanking < hblanking)
2338 * Once illegal timing detected, use default HFP, HSYNC, HBP
2339 * This adjusting made for built-in eDP panel, for the externel
2340 * DP monitor, may need return false.
2342 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) {
2343 adj_hsync = SYNC_LEN_DEF;
2344 adj_hfp = HFP_HBP_DEF;
2345 adj_hbp = HFP_HBP_DEF;
2346 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal);
2347 if (hblanking < HBLANKING_MIN) {
2348 delta_adj = HBLANKING_MIN - hblanking;
2349 adj_clock = vref * delta_adj * adj->vtotal;
2350 adj->clock += DIV_ROUND_UP(adj_clock, 1000);
2352 delta_adj = hblanking - HBLANKING_MIN;
2353 adj_clock = vref * delta_adj * adj->vtotal;
2354 adj->clock -= DIV_ROUND_UP(adj_clock, 1000);
2357 DRM_WARN("illegal hblanking timing, use default.\n");
2358 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync);
2359 } else if (adj_hfp < HP_MIN) {
2360 /* Adjust hfp if hfp less than HP_MIN */
2361 delta_adj = HP_MIN - adj_hfp;
2365 * Balance total HBlanking pixel, if HBP does not have enough
2366 * space, adjust HSYNC length, otherwise adjust HBP
2368 if ((adj_hbp - delta_adj) < HP_MIN)
2369 /* HBP not enough space */
2370 adj_hsync -= delta_adj;
2372 adj_hbp -= delta_adj;
2373 } else if (adj_hbp < HP_MIN) {
2374 delta_adj = HP_MIN - adj_hbp;
2378 * Balance total HBlanking pixel, if HBP hasn't enough space,
2379 * adjust HSYNC length, otherwize adjust HBP
2381 if ((adj_hfp - delta_adj) < HP_MIN)
2382 /* HFP not enough space */
2383 adj_hsync -= delta_adj;
2385 adj_hfp -= delta_adj;
2388 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n");
2389 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2390 adj_hsync, adj_hfp, adj_hbp, adj->clock);
2392 /* Reconstruct timing */
2393 adj->hsync_start = adj->hdisplay + adj_hfp;
2394 adj->hsync_end = adj->hsync_start + adj_hsync;
2395 adj->htotal = adj->hsync_end + adj_hbp;
2396 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2397 adj->hsync_start, adj->hsync_end, adj->htotal);
2402 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge,
2403 struct drm_bridge_state *bridge_state,
2404 struct drm_crtc_state *crtc_state,
2405 struct drm_connector_state *conn_state)
2407 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2408 struct device *dev = ctx->dev;
2410 dev_dbg(dev, "drm bridge atomic check\n");
2412 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
2413 &crtc_state->adjusted_mode);
2415 return anx7625_connector_atomic_check(ctx, conn_state);
2418 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge,
2419 struct drm_bridge_state *state)
2421 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2422 struct device *dev = ctx->dev;
2423 struct drm_connector *connector;
2425 dev_dbg(dev, "drm atomic enable\n");
2427 if (!bridge->encoder) {
2428 dev_err(dev, "Parent encoder object not found");
2432 connector = drm_atomic_get_new_connector_for_encoder(state->base.state,
2437 ctx->connector = connector;
2439 pm_runtime_get_sync(dev);
2440 _anx7625_hpd_polling(ctx, 5000 * 100);
2442 anx7625_dp_start(ctx);
2445 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge,
2446 struct drm_bridge_state *old)
2448 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2449 struct device *dev = ctx->dev;
2451 dev_dbg(dev, "drm atomic disable\n");
2453 ctx->connector = NULL;
2454 anx7625_dp_stop(ctx);
2456 pm_runtime_put_sync(dev);
2459 static enum drm_connector_status
2460 anx7625_bridge_detect(struct drm_bridge *bridge)
2462 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2463 struct device *dev = ctx->dev;
2465 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n");
2467 return anx7625_sink_detect(ctx);
2470 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge,
2471 struct drm_connector *connector)
2473 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2474 struct device *dev = ctx->dev;
2476 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n");
2478 return anx7625_get_edid(ctx);
2481 static const struct drm_bridge_funcs anx7625_bridge_funcs = {
2482 .attach = anx7625_bridge_attach,
2483 .detach = anx7625_bridge_detach,
2484 .mode_valid = anx7625_bridge_mode_valid,
2485 .mode_set = anx7625_bridge_mode_set,
2486 .atomic_check = anx7625_bridge_atomic_check,
2487 .atomic_enable = anx7625_bridge_atomic_enable,
2488 .atomic_disable = anx7625_bridge_atomic_disable,
2489 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2490 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2491 .atomic_reset = drm_atomic_helper_bridge_reset,
2492 .detect = anx7625_bridge_detect,
2493 .get_edid = anx7625_bridge_get_edid,
2496 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx,
2497 struct i2c_client *client)
2499 struct device *dev = ctx->dev;
2501 ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2503 if (IS_ERR(ctx->i2c.tx_p0_client))
2504 return PTR_ERR(ctx->i2c.tx_p0_client);
2506 ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2508 if (IS_ERR(ctx->i2c.tx_p1_client))
2509 return PTR_ERR(ctx->i2c.tx_p1_client);
2511 ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2513 if (IS_ERR(ctx->i2c.tx_p2_client))
2514 return PTR_ERR(ctx->i2c.tx_p2_client);
2516 ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2518 if (IS_ERR(ctx->i2c.rx_p0_client))
2519 return PTR_ERR(ctx->i2c.rx_p0_client);
2521 ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2523 if (IS_ERR(ctx->i2c.rx_p1_client))
2524 return PTR_ERR(ctx->i2c.rx_p1_client);
2526 ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2528 if (IS_ERR(ctx->i2c.rx_p2_client))
2529 return PTR_ERR(ctx->i2c.rx_p2_client);
2531 ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter,
2532 TCPC_INTERFACE_ADDR >> 1);
2533 if (IS_ERR(ctx->i2c.tcpc_client))
2534 return PTR_ERR(ctx->i2c.tcpc_client);
2539 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev)
2541 struct anx7625_data *ctx = dev_get_drvdata(dev);
2543 mutex_lock(&ctx->lock);
2545 anx7625_stop_dp_work(ctx);
2546 anx7625_power_standby(ctx);
2548 mutex_unlock(&ctx->lock);
2553 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev)
2555 struct anx7625_data *ctx = dev_get_drvdata(dev);
2557 mutex_lock(&ctx->lock);
2559 anx7625_power_on_init(ctx);
2561 mutex_unlock(&ctx->lock);
2566 static const struct dev_pm_ops anx7625_pm_ops = {
2567 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2568 pm_runtime_force_resume)
2569 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend,
2570 anx7625_runtime_pm_resume, NULL)
2573 static void anx7625_runtime_disable(void *data)
2575 pm_runtime_dont_use_autosuspend(data);
2576 pm_runtime_disable(data);
2579 static int anx7625_link_bridge(struct drm_dp_aux *aux)
2581 struct anx7625_data *platform = container_of(aux, struct anx7625_data, aux);
2582 struct device *dev = aux->dev;
2585 ret = anx7625_parse_dt_panel(dev, &platform->pdata);
2587 DRM_DEV_ERROR(dev, "fail to parse DT for panel : %d\n", ret);
2591 platform->bridge.funcs = &anx7625_bridge_funcs;
2592 platform->bridge.of_node = dev->of_node;
2593 if (!anx7625_of_panel_on_aux_bus(dev))
2594 platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
2595 if (!platform->pdata.panel_bridge)
2596 platform->bridge.ops |= DRM_BRIDGE_OP_HPD |
2597 DRM_BRIDGE_OP_DETECT;
2598 platform->bridge.type = platform->pdata.panel_bridge ?
2599 DRM_MODE_CONNECTOR_eDP :
2600 DRM_MODE_CONNECTOR_DisplayPort;
2602 drm_bridge_add(&platform->bridge);
2604 if (!platform->pdata.is_dpi) {
2605 ret = anx7625_attach_dsi(platform);
2607 drm_bridge_remove(&platform->bridge);
2613 static int anx7625_i2c_probe(struct i2c_client *client)
2615 struct anx7625_data *platform;
2616 struct anx7625_platform_data *pdata;
2618 struct device *dev = &client->dev;
2620 if (!i2c_check_functionality(client->adapter,
2621 I2C_FUNC_SMBUS_I2C_BLOCK)) {
2622 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n");
2626 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL);
2628 DRM_DEV_ERROR(dev, "fail to allocate driver data\n");
2632 pdata = &platform->pdata;
2634 platform->dev = &client->dev;
2635 i2c_set_clientdata(client, platform);
2637 pdata->supplies[0].supply = "vdd10";
2638 pdata->supplies[1].supply = "vdd18";
2639 pdata->supplies[2].supply = "vdd33";
2640 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies),
2643 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret);
2646 anx7625_init_gpio(platform);
2648 mutex_init(&platform->lock);
2649 mutex_init(&platform->hdcp_wq_lock);
2651 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
2652 platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
2653 if (!platform->hdcp_workqueue) {
2654 dev_err(dev, "fail to create work queue\n");
2659 platform->pdata.intp_irq = client->irq;
2660 if (platform->pdata.intp_irq) {
2661 INIT_WORK(&platform->work, anx7625_work_func);
2662 platform->workqueue = alloc_workqueue("anx7625_work",
2663 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1);
2664 if (!platform->workqueue) {
2665 DRM_DEV_ERROR(dev, "fail to create work queue\n");
2670 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
2671 NULL, anx7625_intr_hpd_isr,
2672 IRQF_TRIGGER_FALLING |
2674 "anx7625-intp", platform);
2676 DRM_DEV_ERROR(dev, "fail to request irq\n");
2681 platform->aux.name = "anx7625-aux";
2682 platform->aux.dev = dev;
2683 platform->aux.transfer = anx7625_aux_transfer;
2684 platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted;
2685 drm_dp_aux_init(&platform->aux);
2687 ret = anx7625_parse_dt(dev, pdata);
2689 if (ret != -EPROBE_DEFER)
2690 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
2694 if (!platform->pdata.is_dpi) {
2695 ret = anx7625_setup_dsi_device(platform);
2701 * Registering the i2c devices will retrigger deferred probe, so it
2702 * needs to be done after calls that might return EPROBE_DEFER,
2703 * otherwise we can get an infinite loop.
2705 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) {
2707 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");
2711 pm_runtime_enable(dev);
2712 pm_runtime_set_autosuspend_delay(dev, 1000);
2713 pm_runtime_use_autosuspend(dev);
2714 pm_suspend_ignore_children(dev, true);
2715 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev);
2720 * Populating the aux bus will retrigger deferred probe, so it needs to
2721 * be done after calls that might return EPROBE_DEFER, otherwise we can
2722 * get an infinite loop.
2724 ret = devm_of_dp_aux_populate_bus(&platform->aux, anx7625_link_bridge);
2726 if (ret != -ENODEV) {
2727 DRM_DEV_ERROR(dev, "failed to populate aux bus : %d\n", ret);
2731 ret = anx7625_link_bridge(&platform->aux);
2736 if (!platform->pdata.low_power_mode) {
2737 anx7625_disable_pd_protocol(platform);
2738 pm_runtime_get_sync(dev);
2739 _anx7625_hpd_polling(platform, 5000 * 100);
2742 /* Add work function */
2743 if (platform->pdata.intp_irq)
2744 queue_work(platform->workqueue, &platform->work);
2746 if (platform->pdata.audio_en)
2747 anx7625_register_audio(dev, platform);
2749 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n");
2754 if (platform->workqueue)
2755 destroy_workqueue(platform->workqueue);
2758 if (platform->hdcp_workqueue)
2759 destroy_workqueue(platform->hdcp_workqueue);
2764 static void anx7625_i2c_remove(struct i2c_client *client)
2766 struct anx7625_data *platform = i2c_get_clientdata(client);
2768 drm_bridge_remove(&platform->bridge);
2770 if (platform->pdata.intp_irq)
2771 destroy_workqueue(platform->workqueue);
2773 if (platform->hdcp_workqueue) {
2774 cancel_delayed_work(&platform->hdcp_work);
2775 flush_workqueue(platform->hdcp_workqueue);
2776 destroy_workqueue(platform->hdcp_workqueue);
2779 if (!platform->pdata.low_power_mode)
2780 pm_runtime_put_sync_suspend(&client->dev);
2782 if (platform->pdata.audio_en)
2783 anx7625_unregister_audio(platform);
2786 static const struct i2c_device_id anx7625_id[] = {
2791 MODULE_DEVICE_TABLE(i2c, anx7625_id);
2793 static const struct of_device_id anx_match_table[] = {
2794 {.compatible = "analogix,anx7625",},
2797 MODULE_DEVICE_TABLE(of, anx_match_table);
2799 static struct i2c_driver anx7625_driver = {
2802 .of_match_table = anx_match_table,
2803 .pm = &anx7625_pm_ops,
2805 .probe = anx7625_i2c_probe,
2806 .remove = anx7625_i2c_remove,
2808 .id_table = anx7625_id,
2811 module_i2c_driver(anx7625_driver);
2813 MODULE_DESCRIPTION("MIPI2DP anx7625 driver");
2814 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>");
2815 MODULE_LICENSE("GPL v2");
2816 MODULE_VERSION(ANX7625_DRV_VERSION);