1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2021, ASPEED Technology Inc.
3 // Authors: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com>
5 #include <linux/firmware.h>
6 #include <linux/delay.h>
7 #include <drm/drm_print.h>
10 int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata)
12 struct ast_private *ast = to_ast_private(dev);
16 * CRD1[b5]: DP MCU FW is executing
17 * CRDC[b0]: DP link success
19 * CRE5[b0]: Host reading EDID process is done
21 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING) &&
22 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS) &&
23 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD) &&
24 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5,
25 ASTDP_HOST_EDID_READ_DONE_MASK))) {
26 goto err_astdp_edid_not_ready;
29 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK,
32 for (i = 0; i < 32; i++) {
34 * CRE4[7:0]: Read-Pointer for EDID (Unit: 4bytes); valid range: 0~64
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE4,
37 (u8) ~ASTDP_EDID_READ_POINTER_MASK, (u8) i);
41 * CRD7[b0]: valid flag for EDID
42 * CRD6[b0]: mirror read pointer for EDID
44 while ((ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD7,
45 ASTDP_EDID_VALID_FLAG_MASK) != 0x01) ||
46 (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD6,
47 ASTDP_EDID_READ_POINTER_MASK) != i)) {
49 * Delay are getting longer with each retry.
50 * 1. The Delays are often 2 loops when users request "Display Settings"
51 * of right-click of mouse.
52 * 2. The Delays are often longer a lot when system resume from S3/S4.
56 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1,
57 ASTDP_MCU_FW_EXECUTING) &&
58 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC,
59 ASTDP_LINK_SUCCESS) &&
60 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD))) {
61 goto err_astdp_jump_out_loop_of_edid;
66 goto err_astdp_jump_out_loop_of_edid;
69 *(ediddata) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT,
70 0xD8, ASTDP_EDID_READ_DATA_MASK);
71 *(ediddata + 1) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD9,
72 ASTDP_EDID_READ_DATA_MASK);
73 *(ediddata + 2) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDA,
74 ASTDP_EDID_READ_DATA_MASK);
75 *(ediddata + 3) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDB,
76 ASTDP_EDID_READ_DATA_MASK);
80 * For 128-bytes EDID_1.3,
81 * 1. Add the value of Bytes-126 to Bytes-127.
82 * The Bytes-127 is Checksum. Sum of all 128bytes should
84 * 2. Modify Bytes-126 to be 0.
85 * The Bytes-126 indicates the Number of extensions to
86 * follow. 0 represents noextensions.
88 *(ediddata + 3) = *(ediddata + 3) + *(ediddata + 2);
95 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK,
96 ASTDP_HOST_EDID_READ_DONE);
100 err_astdp_jump_out_loop_of_edid:
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5,
102 (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK,
103 ASTDP_HOST_EDID_READ_DONE);
104 return (~(j+256) + 1);
106 err_astdp_edid_not_ready:
107 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING)))
109 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS)))
111 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD)))
113 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, ASTDP_HOST_EDID_READ_DONE_MASK)))
122 void ast_dp_launch(struct drm_device *dev, u8 bPower)
124 u32 i = 0, j = 0, WaitCount = 1;
128 struct ast_private *ast = to_ast_private(dev);
129 // S3 come back, need more time to wait BMC ready.
134 // Wait total count by different condition.
135 for (j = 0; j < WaitCount; j++) {
136 bDPTX = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, TX_TYPE_MASK);
144 // 0xE : ASTDP with DPMCU FW handling
145 if (bDPTX == ASTDP_DPMCU_TX) {
146 // Wait one second then timeout.
149 while (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, COPROCESSOR_LAUNCH) !=
150 COPROCESSOR_LAUNCH) {
156 // DP would not be ready.
163 ast->tx_chip_type = AST_TX_ASTDP;
165 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5,
166 (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK,
167 ASTDP_HOST_EDID_READ_DONE);
169 ast->tx_chip_type = AST_TX_NONE;
174 void ast_dp_power_on_off(struct drm_device *dev, bool on)
176 struct ast_private *ast = to_ast_private(dev);
177 // Read and Turn off DP PHY sleep
178 u8 bE3 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, AST_DP_VIDEO_ENABLE);
180 // Turn on DP PHY sleep
182 bE3 |= AST_DP_PHY_SLEEP;
185 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_PHY_SLEEP, bE3);
190 void ast_dp_set_on_off(struct drm_device *dev, bool on)
192 struct ast_private *ast = to_ast_private(dev);
193 u8 video_on_off = on;
196 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_VIDEO_ENABLE, on);
198 // If DP plug in and link successful then check video on / off status
199 if (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS) &&
200 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD)) {
202 while (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF,
203 ASTDP_MIRROR_VIDEO_ENABLE) != video_on_off) {
210 void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode)
212 struct ast_private *ast = to_ast_private(crtc->dev);
214 u32 ulRefreshRateIndex;
217 ulRefreshRateIndex = vbios_mode->enh_table->refresh_rate_index - 1;
219 switch (crtc->mode.crtc_hdisplay) {
221 ModeIdx = ASTDP_320x240_60;
224 ModeIdx = ASTDP_400x300_60;
227 ModeIdx = ASTDP_512x384_60;
230 ModeIdx = (ASTDP_640x480_60 + (u8) ulRefreshRateIndex);
233 ModeIdx = (ASTDP_800x600_56 + (u8) ulRefreshRateIndex);
236 ModeIdx = (ASTDP_1024x768_60 + (u8) ulRefreshRateIndex);
239 ModeIdx = ASTDP_1152x864_75;
242 if (crtc->mode.crtc_vdisplay == 800)
243 ModeIdx = (ASTDP_1280x800_60_RB - (u8) ulRefreshRateIndex);
245 ModeIdx = (ASTDP_1280x1024_60 + (u8) ulRefreshRateIndex);
249 ModeIdx = ASTDP_1366x768_60;
252 ModeIdx = (ASTDP_1440x900_60_RB - (u8) ulRefreshRateIndex);
255 if (crtc->mode.crtc_vdisplay == 900)
256 ModeIdx = (ASTDP_1600x900_60_RB - (u8) ulRefreshRateIndex);
258 ModeIdx = ASTDP_1600x1200_60;
261 ModeIdx = (ASTDP_1680x1050_60_RB - (u8) ulRefreshRateIndex);
264 if (crtc->mode.crtc_vdisplay == 1080)
265 ModeIdx = ASTDP_1920x1080_60;
267 ModeIdx = ASTDP_1920x1200_60;
274 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
275 * CRE1[7:0]: MISC1 (default: 0x00)
276 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
278 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE0, (u8) ~ASTDP_CLEAR_MASK,
280 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE1, (u8) ~ASTDP_CLEAR_MASK, ASTDP_MISC1);
281 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE2, (u8) ~ASTDP_CLEAR_MASK, ModeIdx);