drivers/gpu/drm/arm/malidp_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   4  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   5  *
   6  * ARM Mali DP500/DP550/DP650 driver (crtc operations)
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/pm_runtime.h>
  11
  12 #include <video/videomode.h>
  13
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_print.h>
  18 #include <drm/drm_probe_helper.h>
  19 #include <drm/drm_vblank.h>
  20
  21 #include "malidp_drv.h"
  22 #include "malidp_hw.h"
  23
  24 static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc,
  25                                                    const struct drm_display_mode *mode)
  26 {
  27         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  28         struct malidp_hw_device *hwdev = malidp->dev;
  29
  30         /*
  31          * check that the hardware can drive the required clock rate,
  32          * but skip the check if the clock is meant to be disabled (req_rate = 0)
  33          */
  34         long rate, req_rate = mode->crtc_clock * 1000;
  35
  36         if (req_rate) {
  37                 rate = clk_round_rate(hwdev->pxlclk, req_rate);
  38                 if (rate != req_rate) {
  39                         DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
  40                                          req_rate);
  41                         return MODE_NOCLOCK;
  42                 }
  43         }
  44
  45         return MODE_OK;
  46 }
  47
  48 static void malidp_crtc_atomic_enable(struct drm_crtc *crtc,
  49                                       struct drm_atomic_state *state)
  50 {
  51         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  52         struct malidp_hw_device *hwdev = malidp->dev;
  53         struct videomode vm;
  54         int err = pm_runtime_get_sync(crtc->dev->dev);
  55
  56         if (err < 0) {
  57                 DRM_DEBUG_DRIVER("Failed to enable runtime power management: %d\n", err);
  58                 return;
  59         }
  60
  61         drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm);
  62         clk_prepare_enable(hwdev->pxlclk);
  63
  64         /* We rely on firmware to set mclk to a sensible level. */
  65         clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
  66
  67         hwdev->hw->modeset(hwdev, &vm);
  68         hwdev->hw->leave_config_mode(hwdev);
  69         drm_crtc_vblank_on(crtc);
  70 }
  71
  72 static void malidp_crtc_atomic_disable(struct drm_crtc *crtc,
  73                                        struct drm_atomic_state *state)
  74 {
  75         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
  76                                                                          crtc);
  77         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  78         struct malidp_hw_device *hwdev = malidp->dev;
  79         int err;
  80
  81         /* always disable planes on the CRTC that is being turned off */
  82         drm_atomic_helper_disable_planes_on_crtc(old_state, false);
  83
  84         drm_crtc_vblank_off(crtc);
  85         hwdev->hw->enter_config_mode(hwdev);
  86
  87         clk_disable_unprepare(hwdev->pxlclk);
  88
  89         err = pm_runtime_put(crtc->dev->dev);
  90         if (err < 0) {
  91                 DRM_DEBUG_DRIVER("Failed to disable runtime power management: %d\n", err);
  92         }
  93 }
  94
  95 static const struct gamma_curve_segment {
  96         u16 start;
  97         u16 end;
  98 } segments[MALIDP_COEFFTAB_NUM_COEFFS] = {
  99         /* sector 0 */
 100         {    0,    0 }, {    1,    1 }, {    2,    2 }, {    3,    3 },
 101         {    4,    4 }, {    5,    5 }, {    6,    6 }, {    7,    7 },
 102         {    8,    8 }, {    9,    9 }, {   10,   10 }, {   11,   11 },
 103         {   12,   12 }, {   13,   13 }, {   14,   14 }, {   15,   15 },
 104         /* sector 1 */
 105         {   16,   19 }, {   20,   23 }, {   24,   27 }, {   28,   31 },
 106         /* sector 2 */
 107         {   32,   39 }, {   40,   47 }, {   48,   55 }, {   56,   63 },
 108         /* sector 3 */
 109         {   64,   79 }, {   80,   95 }, {   96,  111 }, {  112,  127 },
 110         /* sector 4 */
 111         {  128,  159 }, {  160,  191 }, {  192,  223 }, {  224,  255 },
 112         /* sector 5 */
 113         {  256,  319 }, {  320,  383 }, {  384,  447 }, {  448,  511 },
 114         /* sector 6 */
 115         {  512,  639 }, {  640,  767 }, {  768,  895 }, {  896, 1023 },
 116         { 1024, 1151 }, { 1152, 1279 }, { 1280, 1407 }, { 1408, 1535 },
 117         { 1536, 1663 }, { 1664, 1791 }, { 1792, 1919 }, { 1920, 2047 },
 118         { 2048, 2175 }, { 2176, 2303 }, { 2304, 2431 }, { 2432, 2559 },
 119         { 2560, 2687 }, { 2688, 2815 }, { 2816, 2943 }, { 2944, 3071 },
 120         { 3072, 3199 }, { 3200, 3327 }, { 3328, 3455 }, { 3456, 3583 },
 121         { 3584, 3711 }, { 3712, 3839 }, { 3840, 3967 }, { 3968, 4095 },
 122 };
 123
 124 #define DE_COEFTAB_DATA(a, b) ((((a) & 0xfff) << 16) | (((b) & 0xfff)))
 125
 126 static void malidp_generate_gamma_table(struct drm_property_blob *lut_blob,
 127                                         u32 coeffs[MALIDP_COEFFTAB_NUM_COEFFS])
 128 {
 129         struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data;
 130         int i;
 131
 132         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) {
 133                 u32 a, b, delta_in, out_start, out_end;
 134
 135                 delta_in = segments[i].end - segments[i].start;
 136                 /* DP has 12-bit internal precision for its LUTs. */
 137                 out_start = drm_color_lut_extract(lut[segments[i].start].green,
 138                                                   12);
 139                 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12);
 140                 a = (delta_in == 0) ? 0 : ((out_end - out_start) * 256) / delta_in;
 141                 b = out_start;
 142                 coeffs[i] = DE_COEFTAB_DATA(a, b);
 143         }
 144 }
 145
 146 /*
 147  * Check if there is a new gamma LUT and if it is of an acceptable size. Also,
 148  * reject any LUTs that use distinct red, green, and blue curves.
 149  */
 150 static int malidp_crtc_atomic_check_gamma(struct drm_crtc *crtc,
 151                                           struct drm_crtc_state *state)
 152 {
 153         struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
 154         struct drm_color_lut *lut;
 155         size_t lut_size;
 156         int i;
 157
 158         if (!state->color_mgmt_changed || !state->gamma_lut)
 159                 return 0;
 160
 161         if (crtc->state->gamma_lut &&
 162             (crtc->state->gamma_lut->base.id == state->gamma_lut->base.id))
 163                 return 0;
 164
 165         if (state->gamma_lut->length % sizeof(struct drm_color_lut))
 166                 return -EINVAL;
 167
 168         lut_size = state->gamma_lut->length / sizeof(struct drm_color_lut);
 169         if (lut_size != MALIDP_GAMMA_LUT_SIZE)
 170                 return -EINVAL;
 171
 172         lut = (struct drm_color_lut *)state->gamma_lut->data;
 173         for (i = 0; i < lut_size; ++i)
 174                 if (!((lut[i].red == lut[i].green) &&
 175                       (lut[i].red == lut[i].blue)))
 176                         return -EINVAL;
 177
 178         if (!state->mode_changed) {
 179                 int ret;
 180
 181                 state->mode_changed = true;
 182                 /*
 183                  * Kerneldoc for drm_atomic_helper_check_modeset mandates that
 184                  * it be invoked when the driver sets ->mode_changed. Since
 185                  * changing the gamma LUT doesn't depend on any external
 186                  * resources, it is safe to call it only once.
 187                  */
 188                 ret = drm_atomic_helper_check_modeset(crtc->dev, state->state);
 189                 if (ret)
 190                         return ret;
 191         }
 192
 193         malidp_generate_gamma_table(state->gamma_lut, mc->gamma_coeffs);
 194         return 0;
 195 }
 196
 197 /*
 198  * Check if there is a new CTM and if it contains valid input. Valid here means
 199  * that the number is inside the representable range for a Q3.12 number,
 200  * excluding truncating the fractional part of the input data.
 201  *
 202  * The COLORADJ registers can be changed atomically.
 203  */
 204 static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc,
 205                                         struct drm_crtc_state *state)
 206 {
 207         struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
 208         struct drm_color_ctm *ctm;
 209         int i;
 210
 211         if (!state->color_mgmt_changed)
 212                 return 0;
 213
 214         if (!state->ctm)
 215                 return 0;
 216
 217         if (crtc->state->ctm && (crtc->state->ctm->base.id ==
 218                                  state->ctm->base.id))
 219                 return 0;
 220
 221         /*
 222          * The size of the ctm is checked in
 223          * drm_atomic_replace_property_blob_from_id.
 224          */
 225         ctm = (struct drm_color_ctm *)state->ctm->data;
 226         for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) {
 227                 /* Convert from S31.32 to Q3.12. */
 228                 s64 val = ctm->matrix[i];
 229                 u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) &
 230                           GENMASK_ULL(14, 0);
 231
 232                 /*
 233                  * Convert to 2s complement and check the destination's top bit
 234                  * for overflow. NB: Can't check before converting or it'd
 235                  * incorrectly reject the case:
 236                  * sign == 1
 237                  * mag == 0x2000
 238                  */
 239                 if (val & BIT_ULL(63))
 240                         mag = ~mag + 1;
 241                 if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14)))
 242                         return -EINVAL;
 243                 mc->coloradj_coeffs[i] = mag;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
 250                                             struct drm_crtc_state *state)
 251 {
 252         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 253         struct malidp_hw_device *hwdev = malidp->dev;
 254         struct malidp_crtc_state *cs = to_malidp_crtc_state(state);
 255         struct malidp_se_config *s = &cs->scaler_config;
 256         struct drm_plane *plane;
 257         struct videomode vm;
 258         const struct drm_plane_state *pstate;
 259         u32 h_upscale_factor = 0; /* U16.16 */
 260         u32 v_upscale_factor = 0; /* U16.16 */
 261         u8 scaling = cs->scaled_planes_mask;
 262         int ret;
 263
 264         if (!scaling) {
 265                 s->scale_enable = false;
 266                 goto mclk_calc;
 267         }
 268
 269         /* The scaling engine can only handle one plane at a time. */
 270         if (scaling & (scaling - 1))
 271                 return -EINVAL;
 272
 273         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 274                 struct malidp_plane *mp = to_malidp_plane(plane);
 275                 u32 phase;
 276
 277                 if (!(mp->layer->id & scaling))
 278                         continue;
 279
 280                 /*
 281                  * Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h]
 282                  * to get the U16.16 result.
 283                  */
 284                 h_upscale_factor = div_u64((u64)pstate->crtc_w << 32,
 285                                            pstate->src_w);
 286                 v_upscale_factor = div_u64((u64)pstate->crtc_h << 32,
 287                                            pstate->src_h);
 288
 289                 s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||
 290                                       (v_upscale_factor >> 16) >= 2);
 291
 292                 if (pstate->rotation & MALIDP_ROTATED_MASK) {
 293                         s->input_w = pstate->src_h >> 16;
 294                         s->input_h = pstate->src_w >> 16;
 295                 } else {
 296                         s->input_w = pstate->src_w >> 16;
 297                         s->input_h = pstate->src_h >> 16;
 298                 }
 299
 300                 s->output_w = pstate->crtc_w;
 301                 s->output_h = pstate->crtc_h;
 302
 303 #define SE_N_PHASE 4
 304 #define SE_SHIFT_N_PHASE 12
 305                 /* Calculate initial_phase and delta_phase for horizontal. */
 306                 phase = s->input_w;
 307                 s->h_init_phase =
 308                                 ((phase << SE_N_PHASE) / s->output_w + 1) / 2;
 309
 310                 phase = s->input_w;
 311                 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
 312                 s->h_delta_phase = phase / s->output_w;
 313
 314                 /* Same for vertical. */
 315                 phase = s->input_h;
 316                 s->v_init_phase =
 317                                 ((phase << SE_N_PHASE) / s->output_h + 1) / 2;
 318
 319                 phase = s->input_h;
 320                 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
 321                 s->v_delta_phase = phase / s->output_h;
 322 #undef SE_N_PHASE
 323 #undef SE_SHIFT_N_PHASE
 324                 s->plane_src_id = mp->layer->id;
 325         }
 326
 327         s->scale_enable = true;
 328         s->hcoeff = malidp_se_select_coeffs(h_upscale_factor);
 329         s->vcoeff = malidp_se_select_coeffs(v_upscale_factor);
 330
 331 mclk_calc:
 332         drm_display_mode_to_videomode(&state->adjusted_mode, &vm);
 333         ret = hwdev->hw->se_calc_mclk(hwdev, s, &vm);
 334         if (ret < 0)
 335                 return -EINVAL;
 336         return 0;
 337 }
 338
 339 static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
 340                                     struct drm_atomic_state *state)
 341 {
 342         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 343                                                                           crtc);
 344         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 345         struct malidp_hw_device *hwdev = malidp->dev;
 346         struct drm_plane *plane;
 347         const struct drm_plane_state *pstate;
 348         u32 rot_mem_free, rot_mem_usable;
 349         int rotated_planes = 0;
 350         int ret;
 351
 352         /*
 353          * check if there is enough rotation memory available for planes
 354          * that need 90° and 270° rotion or planes that are compressed.
 355          * Each plane has set its required memory size in the ->plane_check()
 356          * callback, here we only make sure that the sums are less that the
 357          * total usable memory.
 358          *
 359          * The rotation memory allocation algorithm (for each plane):
 360          *  a. If no more rotated or compressed planes exist, all remaining
 361          *     rotate memory in the bank is available for use by the plane.
 362          *  b. If other rotated or compressed planes exist, and plane's
 363          *     layer ID is DE_VIDEO1, it can use all the memory from first bank
 364          *     if secondary rotation memory bank is available, otherwise it can
 365          *     use up to half the bank's memory.
 366          *  c. If other rotated or compressed planes exist, and plane's layer ID
 367          *     is not DE_VIDEO1, it can use half of the available memory.
 368          *
 369          * Note: this algorithm assumes that the order in which the planes are
 370          * checked always has DE_VIDEO1 plane first in the list if it is
 371          * rotated. Because that is how we create the planes in the first
 372          * place, under current DRM version things work, but if ever the order
 373          * in which drm_atomic_crtc_state_for_each_plane() iterates over planes
 374          * changes, we need to pre-sort the planes before validation.
 375          */
 376
 377         /* first count the number of rotated planes */
 378         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
 379                 struct drm_framebuffer *fb = pstate->fb;
 380
 381                 if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier)
 382                         rotated_planes++;
 383         }
 384
 385         rot_mem_free = hwdev->rotation_memory[0];
 386         /*
 387          * if we have more than 1 plane using rotation memory, use the second
 388          * block of rotation memory as well
 389          */
 390         if (rotated_planes > 1)
 391                 rot_mem_free += hwdev->rotation_memory[1];
 392
 393         /* now validate the rotation memory requirements */
 394         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
 395                 struct malidp_plane *mp = to_malidp_plane(plane);
 396                 struct malidp_plane_state *ms = to_malidp_plane_state(pstate);
 397                 struct drm_framebuffer *fb = pstate->fb;
 398
 399                 if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier) {
 400                         /* process current plane */
 401                         rotated_planes--;
 402
 403                         if (!rotated_planes) {
 404                                 /* no more rotated planes, we can use what's left */
 405                                 rot_mem_usable = rot_mem_free;
 406                         } else {
 407                                 if ((mp->layer->id != DE_VIDEO1) ||
 408                                     (hwdev->rotation_memory[1] == 0))
 409                                         rot_mem_usable = rot_mem_free / 2;
 410                                 else
 411                                         rot_mem_usable = hwdev->rotation_memory[0];
 412                         }
 413
 414                         rot_mem_free -= rot_mem_usable;
 415
 416                         if (ms->rotmem_size > rot_mem_usable)
 417                                 return -EINVAL;
 418                 }
 419         }
 420
 421         /* If only the writeback routing has changed, we don't need a modeset */
 422         if (crtc_state->connectors_changed) {
 423                 u32 old_mask = crtc->state->connector_mask;
 424                 u32 new_mask = crtc_state->connector_mask;
 425
 426                 if ((old_mask ^ new_mask) ==
 427                     (1 << drm_connector_index(&malidp->mw_connector.base)))
 428                         crtc_state->connectors_changed = false;
 429         }
 430
 431         ret = malidp_crtc_atomic_check_gamma(crtc, crtc_state);
 432         ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, crtc_state);
 433         ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, crtc_state);
 434
 435         return ret;
 436 }
 437
 438 static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
 439         .mode_valid = malidp_crtc_mode_valid,
 440         .atomic_check = malidp_crtc_atomic_check,
 441         .atomic_enable = malidp_crtc_atomic_enable,
 442         .atomic_disable = malidp_crtc_atomic_disable,
 443 };
 444
 445 static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc *crtc)
 446 {
 447         struct malidp_crtc_state *state, *old_state;
 448
 449         if (WARN_ON(!crtc->state))
 450                 return NULL;
 451
 452         old_state = to_malidp_crtc_state(crtc->state);
 453         state = kmalloc(sizeof(*state), GFP_KERNEL);
 454         if (!state)
 455                 return NULL;
 456
 457         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 458         memcpy(state->gamma_coeffs, old_state->gamma_coeffs,
 459                sizeof(state->gamma_coeffs));
 460         memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs,
 461                sizeof(state->coloradj_coeffs));
 462         memcpy(&state->scaler_config, &old_state->scaler_config,
 463                sizeof(state->scaler_config));
 464         state->scaled_planes_mask = 0;
 465
 466         return &state->base;
 467 }
 468
 469 static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
 470                                       struct drm_crtc_state *state)
 471 {
 472         struct malidp_crtc_state *mali_state = NULL;
 473
 474         if (state) {
 475                 mali_state = to_malidp_crtc_state(state);
 476                 __drm_atomic_helper_crtc_destroy_state(state);
 477         }
 478
 479         kfree(mali_state);
 480 }
 481
 482 static void malidp_crtc_reset(struct drm_crtc *crtc)
 483 {
 484         struct malidp_crtc_state *state =
 485                 kzalloc(sizeof(*state), GFP_KERNEL);
 486
 487         if (crtc->state)
 488                 malidp_crtc_destroy_state(crtc, crtc->state);
 489
 490         __drm_atomic_helper_crtc_reset(crtc, &state->base);
 491 }
 492
 493 static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
 494 {
 495         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 496         struct malidp_hw_device *hwdev = malidp->dev;
 497
 498         malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
 499                              hwdev->hw->map.de_irq_map.vsync_irq);
 500         return 0;
 501 }
 502
 503 static void malidp_crtc_disable_vblank(struct drm_crtc *crtc)
 504 {
 505         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 506         struct malidp_hw_device *hwdev = malidp->dev;
 507
 508         malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
 509                               hwdev->hw->map.de_irq_map.vsync_irq);
 510 }
 511
 512 static const struct drm_crtc_funcs malidp_crtc_funcs = {
 513         .destroy = drm_crtc_cleanup,
 514         .set_config = drm_atomic_helper_set_config,
 515         .page_flip = drm_atomic_helper_page_flip,
 516         .reset = malidp_crtc_reset,
 517         .atomic_duplicate_state = malidp_crtc_duplicate_state,
 518         .atomic_destroy_state = malidp_crtc_destroy_state,
 519         .enable_vblank = malidp_crtc_enable_vblank,
 520         .disable_vblank = malidp_crtc_disable_vblank,
 521 };
 522
 523 int malidp_crtc_init(struct drm_device *drm)
 524 {
 525         struct malidp_drm *malidp = drm->dev_private;
 526         struct drm_plane *primary = NULL, *plane;
 527         int ret;
 528
 529         ret = malidp_de_planes_init(drm);
 530         if (ret < 0) {
 531                 DRM_ERROR("Failed to initialise planes\n");
 532                 return ret;
 533         }
 534
 535         drm_for_each_plane(plane, drm) {
 536                 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 537                         primary = plane;
 538                         break;
 539                 }
 540         }
 541
 542         if (!primary) {
 543                 DRM_ERROR("no primary plane found\n");
 544                 return -EINVAL;
 545         }
 546
 547         ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
 548                                         &malidp_crtc_funcs, NULL);
 549         if (ret)
 550                 return ret;
 551
 552         drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
 553         drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
 554         /* No inverse-gamma: it is per-plane. */
 555         drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE);
 556
 557         malidp_se_set_enh_coeffs(malidp->dev);
 558
 559         return 0;
 560 }