1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
4 * Author: James.Qian.Wang <james.qian.wang@arm.com>
10 /* Common block registers offset */
11 #define BLK_BLOCK_INFO 0x000
12 #define BLK_PIPELINE_INFO 0x004
13 #define BLK_MAX_LINE_SIZE 0x008
14 #define BLK_VALID_INPUT_ID0 0x020
15 #define BLK_OUTPUT_ID0 0x060
16 #define BLK_INPUT_ID0 0x080
17 #define BLK_IRQ_RAW_STATUS 0x0A0
18 #define BLK_IRQ_CLEAR 0x0A4
19 #define BLK_IRQ_MASK 0x0A8
20 #define BLK_IRQ_STATUS 0x0AC
21 #define BLK_STATUS 0x0B0
22 #define BLK_INFO 0x0C0
23 #define BLK_CONTROL 0x0D0
24 #define BLK_SIZE 0x0D4
25 #define BLK_IN_SIZE 0x0E0
27 #define BLK_P0_PTR_LOW 0x100
28 #define BLK_P0_PTR_HIGH 0x104
29 #define BLK_P0_STRIDE 0x108
30 #define BLK_P1_PTR_LOW 0x110
31 #define BLK_P1_PTR_HIGH 0x114
32 #define BLK_P1_STRIDE 0x118
33 #define BLK_P2_PTR_LOW 0x120
34 #define BLK_P2_PTR_HIGH 0x124
36 #define BLOCK_INFO_N_SUBBLKS(x) ((x) & 0x000F)
37 #define BLOCK_INFO_BLK_ID(x) (((x) & 0x00F0) >> 4)
38 #define BLOCK_INFO_BLK_TYPE(x) (((x) & 0xFF00) >> 8)
39 #define BLOCK_INFO_INPUT_ID(x) ((x) & 0xFFF0)
40 #define BLOCK_INFO_TYPE_ID(x) (((x) & 0x0FF0) >> 4)
42 #define PIPELINE_INFO_N_OUTPUTS(x) ((x) & 0x000F)
43 #define PIPELINE_INFO_N_VALID_INPUTS(x) (((x) & 0x0F00) >> 8)
45 /* Common block control register bits */
46 #define BLK_CTRL_EN BIT(0)
47 /* Common size macro */
48 #define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))
49 #define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
50 #define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
52 /* AD_CONTROL register */
53 #define AD_CONTROL 0x160
55 /* AD_CONTROL register bits */
62 /* Global Control Unit */
63 #define GLB_ARCH_ID 0x000
64 #define GLB_CORE_ID 0x004
65 #define GLB_CORE_INFO 0x008
66 #define GLB_IRQ_STATUS 0x010
68 #define GCU_CONFIG_VALID0 0x0D4
69 #define GCU_CONFIG_VALID1 0x0D8
71 /* GCU_CONTROL_BITS */
72 #define GCU_CONTROL_MODE(x) ((x) & 0x7)
73 #define GCU_CONTROL_SRST BIT(16)
75 /* GCU_CONFIGURATION registers */
76 #define GCU_CONFIGURATION_ID0 0x100
77 #define GCU_CONFIGURATION_ID1 0x104
79 /* GCU configuration */
80 #define GCU_MAX_LINE_SIZE(x) ((x) & 0xFFFF)
81 #define GCU_MAX_NUM_LINES(x) ((x) >> 16)
82 #define GCU_NUM_RICH_LAYERS(x) ((x) & 0x7)
83 #define GCU_NUM_PIPELINES(x) (((x) >> 3) & 0x7)
84 #define GCU_NUM_SCALERS(x) (((x) >> 6) & 0x7)
85 #define GCU_DISPLAY_SPLIT_EN(x) (((x) >> 16) & 0x1)
86 #define GCU_DISPLAY_TBU_EN(x) (((x) >> 17) & 0x1)
89 #define INACTIVE_MODE 0
90 #define TBU_CONNECT_MODE 1
91 #define TBU_DISCONNECT_MODE 2
92 #define DO0_ACTIVE_MODE 3
93 #define DO1_ACTIVE_MODE 4
94 #define DO01_ACTIVE_MODE 5
96 /* GLB_IRQ_STATUS bits */
97 #define GLB_IRQ_STATUS_GCU BIT(0)
98 #define GLB_IRQ_STATUS_LPU0 BIT(8)
99 #define GLB_IRQ_STATUS_LPU1 BIT(9)
100 #define GLB_IRQ_STATUS_ATU0 BIT(10)
101 #define GLB_IRQ_STATUS_ATU1 BIT(11)
102 #define GLB_IRQ_STATUS_ATU2 BIT(12)
103 #define GLB_IRQ_STATUS_ATU3 BIT(13)
104 #define GLB_IRQ_STATUS_CU0 BIT(16)
105 #define GLB_IRQ_STATUS_CU1 BIT(17)
106 #define GLB_IRQ_STATUS_DOU0 BIT(24)
107 #define GLB_IRQ_STATUS_DOU1 BIT(25)
109 #define GLB_IRQ_STATUS_PIPE0 (GLB_IRQ_STATUS_LPU0 |\
110 GLB_IRQ_STATUS_ATU0 |\
111 GLB_IRQ_STATUS_ATU1 |\
112 GLB_IRQ_STATUS_CU0 |\
115 #define GLB_IRQ_STATUS_PIPE1 (GLB_IRQ_STATUS_LPU1 |\
116 GLB_IRQ_STATUS_ATU2 |\
117 GLB_IRQ_STATUS_ATU3 |\
118 GLB_IRQ_STATUS_CU1 |\
121 #define GLB_IRQ_STATUS_ATU (GLB_IRQ_STATUS_ATU0 |\
122 GLB_IRQ_STATUS_ATU1 |\
123 GLB_IRQ_STATUS_ATU2 |\
127 #define GCU_IRQ_CVAL0 BIT(0)
128 #define GCU_IRQ_CVAL1 BIT(1)
129 #define GCU_IRQ_MODE BIT(4)
130 #define GCU_IRQ_ERR BIT(11)
132 /* GCU_STATUS_BITS */
133 #define GCU_STATUS_MODE(x) ((x) & 0x7)
134 #define GCU_STATUS_MERR BIT(4)
135 #define GCU_STATUS_TCS0 BIT(8)
136 #define GCU_STATUS_TCS1 BIT(9)
137 #define GCU_STATUS_ACTIVE BIT(31)
139 /* GCU_CONFIG_VALIDx BITS */
140 #define GCU_CONFIG_CVAL BIT(0)
142 /* PERIPHERAL registers */
143 #define PERIPH_MAX_LINE_SIZE BIT(0)
144 #define PERIPH_NUM_RICH_LAYERS BIT(4)
145 #define PERIPH_SPLIT_EN BIT(8)
146 #define PERIPH_TBU_EN BIT(12)
147 #define PERIPH_AFBC_DMA_EN BIT(16)
148 #define PERIPH_CONFIGURATION_ID 0x1D4
151 #define LPU_TBU_STATUS 0x0B4
152 #define LPU_RAXI_CONTROL 0x0D0
153 #define LPU_WAXI_CONTROL 0x0D4
154 #define LPU_TBU_CONTROL 0x0D8
156 /* LPU_xAXI_CONTROL_BITS */
157 #define TO_RAXI_AOUTSTDCAPB(x) (x)
158 #define TO_RAXI_BOUTSTDCAPB(x) ((x) << 8)
159 #define TO_RAXI_BEN(x) ((x) << 15)
160 #define TO_xAXI_BURSTLEN(x) ((x) << 16)
161 #define TO_xAXI_AxQOS(x) ((x) << 24)
162 #define TO_xAXI_ORD(x) ((x) << 31)
163 #define TO_WAXI_OUTSTDCAPB(x) (x)
165 #define RAXI_AOUTSTDCAPB_MASK 0x7F
166 #define RAXI_BOUTSTDCAPB_MASK 0x7F00
167 #define RAXI_BEN_MASK BIT(15)
168 #define xAXI_BURSTLEN_MASK 0x3F0000
169 #define xAXI_AxQOS_MASK 0xF000000
170 #define xAXI_ORD_MASK BIT(31)
171 #define WAXI_OUTSTDCAPB_MASK 0x3F
173 /* LPU_TBU_CONTROL BITS */
174 #define TO_TBU_DOUTSTDCAPB(x) (x)
175 #define TBU_DOUTSTDCAPB_MASK 0x3F
178 #define LPU_IRQ_IBSY BIT(10)
179 #define LPU_IRQ_ERR BIT(11)
180 #define LPU_IRQ_EOW BIT(12)
181 #define LPU_IRQ_PL0 BIT(13)
183 /* LPU_STATUS_BITS */
184 #define LPU_STATUS_AXIED(x) ((x) & 0xF)
185 #define LPU_STATUS_AXIE BIT(4)
186 #define LPU_STATUS_AXIRP BIT(5)
187 #define LPU_STATUS_AXIWP BIT(6)
188 #define LPU_STATUS_ACE0 BIT(16)
189 #define LPU_STATUS_ACE1 BIT(17)
190 #define LPU_STATUS_ACE2 BIT(18)
191 #define LPU_STATUS_ACE3 BIT(19)
192 #define LPU_STATUS_ACTIVE BIT(31)
194 #define AXIEID_MASK 0xF
195 #define AXIE_MASK LPU_STATUS_AXIE
196 #define AXIRP_MASK LPU_STATUS_AXIRP
197 #define AXIWP_MASK LPU_STATUS_AXIWP
199 #define FROM_AXIEID(reg) ((reg) & AXIEID_MASK)
200 #define TO_AXIE(x) ((x) << 4)
201 #define FROM_AXIRP(reg) (((reg) & AXIRP_MASK) >> 5)
202 #define FROM_AXIWP(reg) (((reg) & AXIWP_MASK) >> 6)
204 /* LPU_TBU_STATUS_BITS */
205 #define LPU_TBU_STATUS_TCF BIT(1)
206 #define LPU_TBU_STATUS_TTNG BIT(2)
207 #define LPU_TBU_STATUS_TITR BIT(8)
208 #define LPU_TBU_STATUS_TEMR BIT(16)
209 #define LPU_TBU_STATUS_TTF BIT(31)
211 /* LPU_TBU_CONTROL BITS */
212 #define LPU_TBU_CTRL_TLBPEN BIT(16)
214 /* CROSSBAR CONTROL BITS */
215 #define CBU_INPUT_CTRL_EN BIT(0)
216 #define CBU_NUM_INPUT_IDS 5
217 #define CBU_NUM_OUTPUT_IDS 5
220 #define CU_BG_COLOR 0x0DC
221 #define CU_INPUT0_SIZE 0x0E0
222 #define CU_INPUT0_OFFSET 0x0E4
223 #define CU_INPUT0_CONTROL 0x0E8
224 #define CU_INPUT1_SIZE 0x0F0
225 #define CU_INPUT1_OFFSET 0x0F4
226 #define CU_INPUT1_CONTROL 0x0F8
227 #define CU_INPUT2_SIZE 0x100
228 #define CU_INPUT2_OFFSET 0x104
229 #define CU_INPUT2_CONTROL 0x108
230 #define CU_INPUT3_SIZE 0x110
231 #define CU_INPUT3_OFFSET 0x114
232 #define CU_INPUT3_CONTROL 0x118
233 #define CU_INPUT4_SIZE 0x120
234 #define CU_INPUT4_OFFSET 0x124
235 #define CU_INPUT4_CONTROL 0x128
237 #define CU_PER_INPUT_REGS 4
239 #define CU_NUM_INPUT_IDS 5
240 #define CU_NUM_OUTPUT_IDS 1
242 /* CU control register bits */
243 #define CU_CTRL_COPROC BIT(0)
246 #define CU_IRQ_OVR BIT(9)
247 #define CU_IRQ_ERR BIT(11)
250 #define CU_STATUS_CPE BIT(0)
251 #define CU_STATUS_ZME BIT(1)
252 #define CU_STATUS_CFGE BIT(2)
253 #define CU_STATUS_ACTIVE BIT(31)
255 /* CU input control register bits */
256 #define CU_INPUT_CTRL_EN BIT(0)
257 #define CU_INPUT_CTRL_PAD BIT(1)
258 #define CU_INPUT_CTRL_PMUL BIT(2)
259 #define CU_INPUT_CTRL_ALPHA(x) (((x) & 0xFF) << 8)
264 #define DOU_IRQ_UND BIT(8)
265 #define DOU_IRQ_ERR BIT(11)
266 #define DOU_IRQ_PL0 BIT(13)
267 #define DOU_IRQ_PL1 BIT(14)
269 /* DOU_STATUS_BITS */
270 #define DOU_STATUS_DRIFTTO BIT(0)
271 #define DOU_STATUS_FRAMETO BIT(1)
272 #define DOU_STATUS_TETO BIT(2)
273 #define DOU_STATUS_CSCE BIT(8)
274 #define DOU_STATUS_ACTIVE BIT(31)
276 /* Layer registers */
277 #define LAYER_INFO 0x0C0
278 #define LAYER_R_CONTROL 0x0D4
279 #define LAYER_FMT 0x0D8
280 #define LAYER_LT_COEFFTAB 0x0DC
281 #define LAYER_PALPHA 0x0E4
283 #define LAYER_YUV_RGB_COEFF0 0x130
285 #define LAYER_AD_H_CROP 0x164
286 #define LAYER_AD_V_CROP 0x168
288 #define LAYER_RGB_RGB_COEFF0 0x170
295 #define L_ROT(x) (((x) & 3) << 8)
296 #define L_HFLIP BIT(10)
297 #define L_VFLIP BIT(11)
298 #define L_TBU_EN BIT(16)
299 #define L_A_RCACHE(x) (((x) & 0xF) << 28)
305 /* LAYER_R_CONTROL BITS */
306 #define LR_CHI422_BILINEAR 0
307 #define LR_CHI422_REPLICATION 1
308 #define LR_CHI420_JPEG (0 << 2)
309 #define LR_CHI420_MPEG (1 << 2)
311 #define L_ITSEL(x) ((x) & 0xFFF)
312 #define L_FTSEL(x) (((x) & 0xFFF) << 16)
314 #define LAYER_PER_PLANE_REGS 4
316 /* Layer_WR registers */
317 #define LAYER_WR_PROG_LINE 0x0D4
318 #define LAYER_WR_FORMAT 0x0D8
320 /* Layer_WR control bits */
321 #define LW_OFM BIT(4)
322 #define LW_LALPHA(x) (((x) & 0xFF) << 8)
323 #define LW_A_WCACHE(x) (((x) & 0xF) << 28)
324 #define LW_TBU_EN BIT(16)
326 #define AxCACHE_MASK 0xF0000000
328 /* Layer AXI R/W cache setting */
329 #define AxCACHE_B BIT(0) /* Bufferable */
330 #define AxCACHE_M BIT(1) /* Modifiable */
331 #define AxCACHE_RA BIT(2) /* Read-Allocate */
332 #define AxCACHE_WA BIT(3) /* Write-Allocate */
334 /* Layer info bits */
335 #define L_INFO_RF BIT(0)
336 #define L_INFO_CM BIT(1)
337 #define L_INFO_ABUF_SIZE(x) (((x) >> 4) & 0x7)
338 #define L_INFO_YUV_MAX_LINESZ(x) (((x) >> 16) & 0xFFFF)
340 /* Scaler registers */
341 #define SC_COEFFTAB 0x0DC
342 #define SC_OUT_SIZE 0x0E4
343 #define SC_H_CROP 0x0E8
344 #define SC_V_CROP 0x0EC
345 #define SC_H_INIT_PH 0x0F0
346 #define SC_H_DELTA_PH 0x0F4
347 #define SC_V_INIT_PH 0x0F8
348 #define SC_V_DELTA_PH 0x0FC
349 #define SC_ENH_LIMITS 0x130
350 #define SC_ENH_COEFF0 0x134
352 #define SC_MAX_ENH_COEFF 9
355 #define SC_CTRL_SCL BIT(0)
356 #define SC_CTRL_LS BIT(1)
357 #define SC_CTRL_AP BIT(4)
358 #define SC_CTRL_IENH BIT(8)
359 #define SC_CTRL_RGBSM BIT(16)
360 #define SC_CTRL_ASM BIT(17)
362 #define SC_VTSEL(vtal) ((vtal) << 16)
364 #define SC_NUM_INPUTS_IDS 1
365 #define SC_NUM_OUTPUTS_IDS 1
367 #define MG_NUM_INPUTS_IDS 2
368 #define MG_NUM_OUTPUTS_IDS 1
370 /* Merger registers */
371 #define MG_INPUT_ID0 BLK_INPUT_ID0
372 #define MG_INPUT_ID1 (MG_INPUT_ID0 + 4)
373 #define MG_SIZE BLK_SIZE
375 /* Splitter registers */
376 #define SP_OVERLAP_SIZE 0xD8
378 /* Backend registers */
379 #define BS_INFO 0x0C0
380 #define BS_PROG_LINE 0x0D4
381 #define BS_PREFETCH_LINE 0x0D8
382 #define BS_BG_COLOR 0x0DC
383 #define BS_ACTIVESIZE 0x0E0
384 #define BS_HINTERVALS 0x0E4
385 #define BS_VINTERVALS 0x0E8
386 #define BS_SYNC 0x0EC
387 #define BS_DRIFT_TO 0x100
388 #define BS_FRAME_TO 0x104
389 #define BS_TE_TO 0x108
390 #define BS_T0_INTERVAL 0x110
391 #define BS_T1_INTERVAL 0x114
392 #define BS_T2_INTERVAL 0x118
393 #define BS_CRC0_LOW 0x120
394 #define BS_CRC0_HIGH 0x124
395 #define BS_CRC1_LOW 0x128
396 #define BS_CRC1_HIGH 0x12C
397 #define BS_USER 0x130
399 /* BS control register bits */
400 #define BS_CTRL_EN BIT(0)
401 #define BS_CTRL_VM BIT(1)
402 #define BS_CTRL_BM BIT(2)
403 #define BS_CTRL_HMASK BIT(4)
404 #define BS_CTRL_VD BIT(5)
405 #define BS_CTRL_TE BIT(8)
406 #define BS_CTRL_TS BIT(9)
407 #define BS_CTRL_TM BIT(12)
408 #define BS_CTRL_DL BIT(16)
409 #define BS_CTRL_SBS BIT(17)
410 #define BS_CTRL_CRC BIT(18)
411 #define BS_CTRL_PM BIT(20)
413 /* BS active size/intervals */
414 #define BS_H_INTVALS(hfp, hbp) (((hfp) & 0xFFF) + (((hbp) & 0x3FF) << 16))
415 #define BS_V_INTVALS(vfp, vbp) (((vfp) & 0x3FFF) + (((vbp) & 0xFF) << 16))
418 #define BS_SYNC_HSW(x) ((x) & 0x3FF)
419 #define BS_SYNC_HSP BIT(12)
420 #define BS_SYNC_VSW(x) (((x) & 0xFF) << 16)
421 #define BS_SYNC_VSP BIT(28)
423 #define BS_NUM_INPUT_IDS 0
424 #define BS_NUM_OUTPUT_IDS 0
426 /* Image process registers */
427 #define IPS_DEPTH 0x0D8
428 #define IPS_RGB_RGB_COEFF0 0x130
429 #define IPS_RGB_YUV_COEFF0 0x170
431 #define IPS_DEPTH_MARK 0xF
433 /* IPS control register bits */
434 #define IPS_CTRL_RGB BIT(0)
435 #define IPS_CTRL_FT BIT(4)
436 #define IPS_CTRL_YUV BIT(8)
437 #define IPS_CTRL_CHD422 BIT(9)
438 #define IPS_CTRL_CHD420 BIT(10)
439 #define IPS_CTRL_LPF BIT(11)
440 #define IPS_CTRL_DITH BIT(12)
441 #define IPS_CTRL_CLAMP BIT(16)
442 #define IPS_CTRL_SBS BIT(17)
444 /* IPS info register bits */
445 #define IPS_INFO_CHD420 BIT(10)
447 #define IPS_NUM_INPUT_IDS 2
448 #define IPS_NUM_OUTPUT_IDS 1
450 /* FT_COEFF block registers */
451 #define FT_COEFF0 0x80
452 #define GLB_IT_COEFF 0x80
454 /* GLB_SC_COEFF registers */
455 #define GLB_SC_COEFF_ADDR 0x0080
456 #define GLB_SC_COEFF_DATA 0x0084
457 #define GLB_LT_COEFF_DATA 0x0080
459 #define GLB_SC_COEFF_MAX_NUM 1024
460 #define GLB_LT_COEFF_NUM 65
462 #define SC_COEFF_R_ADDR BIT(18)
463 #define SC_COEFF_G_ADDR BIT(17)
464 #define SC_COEFF_B_ADDR BIT(16)
466 #define SC_COEFF_DATA(x, y) (((y) & 0xFFFF) | (((x) & 0xFFFF) << 16))
469 D71_BLK_TYPE_GCU = 0x00,
470 D71_BLK_TYPE_LPU = 0x01,
471 D71_BLK_TYPE_CU = 0x02,
472 D71_BLK_TYPE_DOU = 0x03,
473 D71_BLK_TYPE_AEU = 0x04,
474 D71_BLK_TYPE_GLB_LT_COEFF = 0x05,
475 D71_BLK_TYPE_GLB_SCL_COEFF = 0x06, /* SH/SV scaler coeff */
476 D71_BLK_TYPE_GLB_SC_COEFF = 0x07,
477 D71_BLK_TYPE_PERIPH = 0x08,
478 D71_BLK_TYPE_LPU_TRUSTED = 0x09,
479 D71_BLK_TYPE_AEU_TRUSTED = 0x0A,
480 D71_BLK_TYPE_LPU_LAYER = 0x10,
481 D71_BLK_TYPE_LPU_WB_LAYER = 0x11,
482 D71_BLK_TYPE_CU_SPLITTER = 0x20,
483 D71_BLK_TYPE_CU_SCALER = 0x21,
484 D71_BLK_TYPE_CU_MERGER = 0x22,
485 D71_BLK_TYPE_DOU_IPS = 0x30,
486 D71_BLK_TYPE_DOU_BS = 0x31,
487 D71_BLK_TYPE_DOU_FT_COEFF = 0x32,
488 D71_BLK_TYPE_AEU_DS = 0x40,
489 D71_BLK_TYPE_AEU_AES = 0x41,
490 D71_BLK_TYPE_RESERVED = 0xFF
493 /* Constant of components */
494 #define D71_MAX_PIPELINE 2
495 #define D71_PIPELINE_MAX_SCALERS 2
496 #define D71_PIPELINE_MAX_LAYERS 4
498 #define D71_MAX_GLB_IT_COEFF 3
499 #define D71_MAX_GLB_SCL_COEFF 4
501 #define D71_MAX_LAYERS_PER_LPU 4
502 #define D71_BLOCK_MAX_INPUT 9
503 #define D71_BLOCK_MAX_OUTPUT 5
504 #define D71_MAX_SC_PER_CU 2
506 #define D71_BLOCK_OFFSET_PERIPH 0xFE00
507 #define D71_BLOCK_SIZE 0x0200
509 #define D71_DEFAULT_PREPRETCH_LINE 5
510 #define D71_BUS_WIDTH_16_BYTES 16
512 #define D71_SC_MAX_UPSCALING 64
513 #define D71_SC_MAX_DOWNSCALING 6
514 #define D71_SC_SPLIT_OVERLAP 8
515 #define D71_SC_ENH_SPLIT_OVERLAP 1
517 #define D71_MG_MIN_MERGED_SIZE 4
518 #define D71_MG_MAX_MERGED_HSIZE 4032
519 #define D71_MG_MAX_MERGED_VSIZE 4096
521 #define D71_PALPHA_DEF_MAP 0xFFAA5500
522 #define D71_LAYER_CONTROL_DEFAULT 0x30000000
523 #define D71_WB_LAYER_CONTROL_DEFAULT 0x3000FF00
524 #define D71_BS_CONTROL_DEFAULT 0x00000002
526 struct block_header {
529 u32 input_ids[D71_BLOCK_MAX_INPUT];
530 u32 output_ids[D71_BLOCK_MAX_OUTPUT];
533 static inline u32 get_block_type(struct block_header *blk)
535 return BLOCK_INFO_BLK_TYPE(blk->block_info);
538 #endif /* !_D71_REG_H_ */