drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HWMGR_H_
  24 #define _HWMGR_H_
  25
  26 #include <linux/seq_file.h>
  27 #include "amd_powerplay.h"
  28 #include "hardwaremanager.h"
  29 #include "pp_power_source.h"
  30 #include "hwmgr_ppt.h"
  31 #include "ppatomctrl.h"
  32 #include "hwmgr_ppt.h"
  33 #include "power_state.h"
  34 #include "smu_helper.h"
  35
  36 struct pp_hwmgr;
  37 struct phm_fan_speed_info;
  38 struct pp_atomctrl_voltage_table;
  39
  40 #define VOLTAGE_SCALE 4
  41
  42 uint8_t convert_to_vid(uint16_t vddc);
  43 uint16_t convert_to_vddc(uint8_t vid);
  44
  45 enum DISPLAY_GAP {
  46         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
  47         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
  48         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
  49         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
  50 };
  51 typedef enum DISPLAY_GAP DISPLAY_GAP;
  52
  53 struct vi_dpm_level {
  54         bool enabled;
  55         uint32_t value;
  56         uint32_t param1;
  57 };
  58
  59 struct vi_dpm_table {
  60         uint32_t count;
  61         struct vi_dpm_level dpm_level[1];
  62 };
  63
  64 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
  65 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
  66 #define PCIE_PERF_REQ_GEN1         2
  67 #define PCIE_PERF_REQ_GEN2         3
  68 #define PCIE_PERF_REQ_GEN3         4
  69
  70 enum PP_FEATURE_MASK {
  71         PP_SCLK_DPM_MASK = 0x1,
  72         PP_MCLK_DPM_MASK = 0x2,
  73         PP_PCIE_DPM_MASK = 0x4,
  74         PP_SCLK_DEEP_SLEEP_MASK = 0x8,
  75         PP_POWER_CONTAINMENT_MASK = 0x10,
  76         PP_UVD_HANDSHAKE_MASK = 0x20,
  77         PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
  78         PP_VBI_TIME_SUPPORT_MASK = 0x80,
  79         PP_ULV_MASK = 0x100,
  80         PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
  81         PP_CLOCK_STRETCH_MASK = 0x400,
  82         PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
  83         PP_SOCCLK_DPM_MASK = 0x1000,
  84         PP_DCEFCLK_DPM_MASK = 0x2000,
  85         PP_OVERDRIVE_MASK = 0x4000,
  86 };
  87
  88 enum PHM_BackEnd_Magic {
  89         PHM_Dummy_Magic       = 0xAA5555AA,
  90         PHM_RV770_Magic       = 0xDCBAABCD,
  91         PHM_Kong_Magic        = 0x239478DF,
  92         PHM_NIslands_Magic    = 0x736C494E,
  93         PHM_Sumo_Magic        = 0x8339FA11,
  94         PHM_SIslands_Magic    = 0x369431AC,
  95         PHM_Trinity_Magic     = 0x96751873,
  96         PHM_CIslands_Magic    = 0x38AC78B0,
  97         PHM_Kv_Magic          = 0xDCBBABC0,
  98         PHM_VIslands_Magic    = 0x20130307,
  99         PHM_Cz_Magic          = 0x67DCBA25,
 100         PHM_Rv_Magic          = 0x20161121
 101 };
 102
 103 struct phm_set_power_state_input {
 104         const struct pp_hw_power_state *pcurrent_state;
 105         const struct pp_hw_power_state *pnew_state;
 106 };
 107
 108 struct phm_clock_array {
 109         uint32_t count;
 110         uint32_t values[1];
 111 };
 112
 113 struct phm_clock_voltage_dependency_record {
 114         uint32_t clk;
 115         uint32_t v;
 116 };
 117
 118 struct phm_vceclock_voltage_dependency_record {
 119         uint32_t ecclk;
 120         uint32_t evclk;
 121         uint32_t v;
 122 };
 123
 124 struct phm_uvdclock_voltage_dependency_record {
 125         uint32_t vclk;
 126         uint32_t dclk;
 127         uint32_t v;
 128 };
 129
 130 struct phm_samuclock_voltage_dependency_record {
 131         uint32_t samclk;
 132         uint32_t v;
 133 };
 134
 135 struct phm_acpclock_voltage_dependency_record {
 136         uint32_t acpclk;
 137         uint32_t v;
 138 };
 139
 140 struct phm_clock_voltage_dependency_table {
 141         uint32_t count;                                                                         /* Number of entries. */
 142         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
 143 };
 144
 145 struct phm_phase_shedding_limits_record {
 146         uint32_t  Voltage;
 147         uint32_t    Sclk;
 148         uint32_t    Mclk;
 149 };
 150
 151 struct phm_uvd_clock_voltage_dependency_record {
 152         uint32_t vclk;
 153         uint32_t dclk;
 154         uint32_t v;
 155 };
 156
 157 struct phm_uvd_clock_voltage_dependency_table {
 158         uint8_t count;
 159         struct phm_uvd_clock_voltage_dependency_record entries[1];
 160 };
 161
 162 struct phm_acp_clock_voltage_dependency_record {
 163         uint32_t acpclk;
 164         uint32_t v;
 165 };
 166
 167 struct phm_acp_clock_voltage_dependency_table {
 168         uint32_t count;
 169         struct phm_acp_clock_voltage_dependency_record entries[1];
 170 };
 171
 172 struct phm_vce_clock_voltage_dependency_record {
 173         uint32_t ecclk;
 174         uint32_t evclk;
 175         uint32_t v;
 176 };
 177
 178 struct phm_phase_shedding_limits_table {
 179         uint32_t                           count;
 180         struct phm_phase_shedding_limits_record  entries[1];
 181 };
 182
 183 struct phm_vceclock_voltage_dependency_table {
 184         uint8_t count;                                    /* Number of entries. */
 185         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 186 };
 187
 188 struct phm_uvdclock_voltage_dependency_table {
 189         uint8_t count;                                    /* Number of entries. */
 190         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 191 };
 192
 193 struct phm_samuclock_voltage_dependency_table {
 194         uint8_t count;                                    /* Number of entries. */
 195         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 196 };
 197
 198 struct phm_acpclock_voltage_dependency_table {
 199         uint32_t count;                                    /* Number of entries. */
 200         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 201 };
 202
 203 struct phm_vce_clock_voltage_dependency_table {
 204         uint8_t count;
 205         struct phm_vce_clock_voltage_dependency_record entries[1];
 206 };
 207
 208 struct pp_smumgr_func {
 209         int (*smu_init)(struct pp_hwmgr  *hwmgr);
 210         int (*smu_fini)(struct pp_hwmgr  *hwmgr);
 211         int (*start_smu)(struct pp_hwmgr  *hwmgr);
 212         int (*check_fw_load_finish)(struct pp_hwmgr  *hwmgr,
 213                                     uint32_t firmware);
 214         int (*request_smu_load_fw)(struct pp_hwmgr  *hwmgr);
 215         int (*request_smu_load_specific_fw)(struct pp_hwmgr  *hwmgr,
 216                                             uint32_t firmware);
 217         int (*get_argument)(struct pp_hwmgr  *hwmgr);
 218         int (*send_msg_to_smc)(struct pp_hwmgr  *hwmgr, uint16_t msg);
 219         int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr  *hwmgr,
 220                                           uint16_t msg, uint32_t parameter);
 221         int (*download_pptable_settings)(struct pp_hwmgr  *hwmgr,
 222                                          void **table);
 223         int (*upload_pptable_settings)(struct pp_hwmgr  *hwmgr);
 224         int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
 225         int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
 226         int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
 227         int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
 228         int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
 229         int (*init_smc_table)(struct pp_hwmgr *hwmgr);
 230         int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
 231         int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
 232         int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
 233         uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
 234         uint32_t (*get_mac_definition)(uint32_t value);
 235         bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
 236         bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
 237         int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
 238         int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
 239 };
 240
 241 struct pp_hwmgr_func {
 242         int (*backend_init)(struct pp_hwmgr *hw_mgr);
 243         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
 244         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
 245         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
 246
 247         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
 248                                 struct pp_power_state  *prequest_ps,
 249                         const struct pp_power_state *pcurrent_ps);
 250
 251         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
 252                                         enum amd_dpm_forced_level level);
 253
 254         int (*dynamic_state_management_enable)(
 255                                                 struct pp_hwmgr *hw_mgr);
 256         int (*dynamic_state_management_disable)(
 257                                                 struct pp_hwmgr *hw_mgr);
 258
 259         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
 260                                      struct pp_hw_power_state *hw_ps);
 261
 262         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
 263                             unsigned long, struct pp_power_state *);
 264         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
 265         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
 266         void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
 267         void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
 268         uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
 269         uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
 270         int (*power_state_set)(struct pp_hwmgr *hwmgr,
 271                                                 const void *state);
 272         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 273         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
 274         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
 275         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 276         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
 277                                                 const uint32_t *msg_id);
 278         int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 279         int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 280         int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
 281         int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
 282         void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
 283         uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
 284         int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
 285         int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 286         int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
 287         int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 288         int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
 289         int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
 290         int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
 291                                         const void *thermal_interrupt_info);
 292         bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
 293         int (*check_states_equal)(struct pp_hwmgr *hwmgr,
 294                                         const struct pp_hw_power_state *pstate1,
 295                                         const struct pp_hw_power_state *pstate2,
 296                                         bool *equal);
 297         int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
 298         int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 299                                 bool cc6_disable, bool pstate_disable,
 300                                 bool pstate_switch_disable);
 301         int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
 302                         struct amd_pp_simple_clock_info *info);
 303         int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
 304                         PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
 305         int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
 306                                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
 307         int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
 308         int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
 309                         enum amd_pp_clock_type type,
 310                         struct pp_clock_levels_with_latency *clocks);
 311         int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
 312                         enum amd_pp_clock_type type,
 313                         struct pp_clock_levels_with_voltage *clocks);
 314         int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
 315                         struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
 316         int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
 317                         struct pp_display_clock_request *clock);
 318         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
 319         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
 320         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
 321         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
 322         int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
 323         int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
 324         int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 325         int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
 326         int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 327         int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
 328         int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
 329         int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
 330         int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
 331         int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
 332         int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
 333         int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
 334                                         uint32_t virtual_addr_low,
 335                                         uint32_t virtual_addr_hi,
 336                                         uint32_t mc_addr_low,
 337                                         uint32_t mc_addr_hi,
 338                                         uint32_t size);
 339         int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
 340                                         struct PP_TemperatureRange *range);
 341         int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
 342         int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
 343         int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
 344                                         enum PP_OD_DPM_TABLE_COMMAND type,
 345                                         long *input, uint32_t size);
 346         int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
 347         int (*set_mmhub_powergating_by_smu)(struct pp_hwmgr *hwmgr);
 348 };
 349
 350 struct pp_table_func {
 351         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
 352         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
 353         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
 354         int (*pptable_get_vce_state_table_entry)(
 355                                                 struct pp_hwmgr *hwmgr,
 356                                                 unsigned long i,
 357                                                 struct amd_vce_state *vce_state,
 358                                                 void **clock_info,
 359                                                 unsigned long *flag);
 360 };
 361
 362 union phm_cac_leakage_record {
 363         struct {
 364                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
 365                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
 366         };
 367         struct {
 368                 uint16_t Vddc1;
 369                 uint16_t Vddc2;
 370                 uint16_t Vddc3;
 371         };
 372 };
 373
 374 struct phm_cac_leakage_table {
 375         uint32_t count;
 376         union phm_cac_leakage_record entries[1];
 377 };
 378
 379 struct phm_samu_clock_voltage_dependency_record {
 380         uint32_t samclk;
 381         uint32_t v;
 382 };
 383
 384
 385 struct phm_samu_clock_voltage_dependency_table {
 386         uint8_t count;
 387         struct phm_samu_clock_voltage_dependency_record entries[1];
 388 };
 389
 390 struct phm_cac_tdp_table {
 391         uint16_t usTDP;
 392         uint16_t usConfigurableTDP;
 393         uint16_t usTDC;
 394         uint16_t usBatteryPowerLimit;
 395         uint16_t usSmallPowerLimit;
 396         uint16_t usLowCACLeakage;
 397         uint16_t usHighCACLeakage;
 398         uint16_t usMaximumPowerDeliveryLimit;
 399         uint16_t usEDCLimit;
 400         uint16_t usOperatingTempMinLimit;
 401         uint16_t usOperatingTempMaxLimit;
 402         uint16_t usOperatingTempStep;
 403         uint16_t usOperatingTempHyst;
 404         uint16_t usDefaultTargetOperatingTemp;
 405         uint16_t usTargetOperatingTemp;
 406         uint16_t usPowerTuneDataSetID;
 407         uint16_t usSoftwareShutdownTemp;
 408         uint16_t usClockStretchAmount;
 409         uint16_t usTemperatureLimitHotspot;
 410         uint16_t usTemperatureLimitLiquid1;
 411         uint16_t usTemperatureLimitLiquid2;
 412         uint16_t usTemperatureLimitVrVddc;
 413         uint16_t usTemperatureLimitVrMvdd;
 414         uint16_t usTemperatureLimitPlx;
 415         uint8_t  ucLiquid1_I2C_address;
 416         uint8_t  ucLiquid2_I2C_address;
 417         uint8_t  ucLiquid_I2C_Line;
 418         uint8_t  ucVr_I2C_address;
 419         uint8_t  ucVr_I2C_Line;
 420         uint8_t  ucPlx_I2C_address;
 421         uint8_t  ucPlx_I2C_Line;
 422         uint32_t usBoostPowerLimit;
 423         uint8_t  ucCKS_LDO_REFSEL;
 424 };
 425
 426 struct phm_tdp_table {
 427         uint16_t usTDP;
 428         uint16_t usConfigurableTDP;
 429         uint16_t usTDC;
 430         uint16_t usBatteryPowerLimit;
 431         uint16_t usSmallPowerLimit;
 432         uint16_t usLowCACLeakage;
 433         uint16_t usHighCACLeakage;
 434         uint16_t usMaximumPowerDeliveryLimit;
 435         uint16_t usEDCLimit;
 436         uint16_t usOperatingTempMinLimit;
 437         uint16_t usOperatingTempMaxLimit;
 438         uint16_t usOperatingTempStep;
 439         uint16_t usOperatingTempHyst;
 440         uint16_t usDefaultTargetOperatingTemp;
 441         uint16_t usTargetOperatingTemp;
 442         uint16_t usPowerTuneDataSetID;
 443         uint16_t usSoftwareShutdownTemp;
 444         uint16_t usClockStretchAmount;
 445         uint16_t usTemperatureLimitTedge;
 446         uint16_t usTemperatureLimitHotspot;
 447         uint16_t usTemperatureLimitLiquid1;
 448         uint16_t usTemperatureLimitLiquid2;
 449         uint16_t usTemperatureLimitHBM;
 450         uint16_t usTemperatureLimitVrVddc;
 451         uint16_t usTemperatureLimitVrMvdd;
 452         uint16_t usTemperatureLimitPlx;
 453         uint8_t  ucLiquid1_I2C_address;
 454         uint8_t  ucLiquid2_I2C_address;
 455         uint8_t  ucLiquid_I2C_Line;
 456         uint8_t  ucVr_I2C_address;
 457         uint8_t  ucVr_I2C_Line;
 458         uint8_t  ucPlx_I2C_address;
 459         uint8_t  ucPlx_I2C_Line;
 460         uint8_t  ucLiquid_I2C_LineSDA;
 461         uint8_t  ucVr_I2C_LineSDA;
 462         uint8_t  ucPlx_I2C_LineSDA;
 463         uint32_t usBoostPowerLimit;
 464         uint16_t usBoostStartTemperature;
 465         uint16_t usBoostStopTemperature;
 466         uint32_t  ulBoostClock;
 467 };
 468
 469 struct phm_ppm_table {
 470         uint8_t   ppm_design;
 471         uint16_t  cpu_core_number;
 472         uint32_t  platform_tdp;
 473         uint32_t  small_ac_platform_tdp;
 474         uint32_t  platform_tdc;
 475         uint32_t  small_ac_platform_tdc;
 476         uint32_t  apu_tdp;
 477         uint32_t  dgpu_tdp;
 478         uint32_t  dgpu_ulv_power;
 479         uint32_t  tj_max;
 480 };
 481
 482 struct phm_vq_budgeting_record {
 483         uint32_t ulCUs;
 484         uint32_t ulSustainableSOCPowerLimitLow;
 485         uint32_t ulSustainableSOCPowerLimitHigh;
 486         uint32_t ulMinSclkLow;
 487         uint32_t ulMinSclkHigh;
 488         uint8_t  ucDispConfig;
 489         uint32_t ulDClk;
 490         uint32_t ulEClk;
 491         uint32_t ulSustainableSclk;
 492         uint32_t ulSustainableCUs;
 493 };
 494
 495 struct phm_vq_budgeting_table {
 496         uint8_t numEntries;
 497         struct phm_vq_budgeting_record entries[1];
 498 };
 499
 500 struct phm_clock_and_voltage_limits {
 501         uint32_t sclk;
 502         uint32_t mclk;
 503         uint32_t gfxclk;
 504         uint16_t vddc;
 505         uint16_t vddci;
 506         uint16_t vddgfx;
 507         uint16_t vddmem;
 508 };
 509
 510 /* Structure to hold PPTable information */
 511
 512 struct phm_ppt_v1_information {
 513         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 514         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 515         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
 516         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
 517         struct phm_clock_array *valid_sclk_values;
 518         struct phm_clock_array *valid_mclk_values;
 519         struct phm_clock_array *valid_socclk_values;
 520         struct phm_clock_array *valid_dcefclk_values;
 521         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 522         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 523         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 524         struct phm_ppm_table *ppm_parameter_table;
 525         struct phm_cac_tdp_table *cac_dtp_table;
 526         struct phm_tdp_table *tdp_table;
 527         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 528         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 529         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 530         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
 531         struct phm_ppt_v1_pcie_table *pcie_table;
 532         struct phm_ppt_v1_gpio_table *gpio_table;
 533         uint16_t us_ulv_voltage_offset;
 534         uint16_t us_ulv_smnclk_did;
 535         uint16_t us_ulv_mp1clk_did;
 536         uint16_t us_ulv_gfxclk_bypass;
 537         uint16_t us_gfxclk_slew_rate;
 538         uint16_t us_min_gfxclk_freq_limit;
 539 };
 540
 541 struct phm_ppt_v2_information {
 542         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 543         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 544         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
 545         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
 546         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
 547         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
 548         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
 549         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 550
 551         struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
 552
 553         struct phm_clock_array *valid_sclk_values;
 554         struct phm_clock_array *valid_mclk_values;
 555         struct phm_clock_array *valid_socclk_values;
 556         struct phm_clock_array *valid_dcefclk_values;
 557
 558         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 559         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 560
 561         struct phm_ppm_table *ppm_parameter_table;
 562         struct phm_cac_tdp_table *cac_dtp_table;
 563         struct phm_tdp_table *tdp_table;
 564
 565         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 566         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 567         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
 568         struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
 569
 570         struct phm_ppt_v1_pcie_table *pcie_table;
 571
 572         uint16_t us_ulv_voltage_offset;
 573         uint16_t us_ulv_smnclk_did;
 574         uint16_t us_ulv_mp1clk_did;
 575         uint16_t us_ulv_gfxclk_bypass;
 576         uint16_t us_gfxclk_slew_rate;
 577         uint16_t us_min_gfxclk_freq_limit;
 578
 579         uint8_t  uc_gfx_dpm_voltage_mode;
 580         uint8_t  uc_soc_dpm_voltage_mode;
 581         uint8_t  uc_uclk_dpm_voltage_mode;
 582         uint8_t  uc_uvd_dpm_voltage_mode;
 583         uint8_t  uc_vce_dpm_voltage_mode;
 584         uint8_t  uc_mp0_dpm_voltage_mode;
 585         uint8_t  uc_dcef_dpm_voltage_mode;
 586 };
 587
 588 struct phm_ppt_v3_information
 589 {
 590         uint8_t uc_thermal_controller_type;
 591
 592         uint16_t us_small_power_limit1;
 593         uint16_t us_small_power_limit2;
 594         uint16_t us_boost_power_limit;
 595
 596         uint16_t us_od_turbo_power_limit;
 597         uint16_t us_od_powersave_power_limit;
 598         uint16_t us_software_shutdown_temp;
 599
 600         uint32_t *power_saving_clock_max;
 601         uint32_t *power_saving_clock_min;
 602
 603         uint32_t *od_settings_max;
 604         uint32_t *od_settings_min;
 605
 606         void *smc_pptable;
 607 };
 608
 609 struct phm_dynamic_state_info {
 610         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
 611         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
 612         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 613         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 614         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 615         struct phm_clock_array                    *valid_sclk_values;
 616         struct phm_clock_array                    *valid_mclk_values;
 617         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
 618         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
 619         uint32_t                                  mclk_sclk_ratio;
 620         uint32_t                                  sclk_mclk_delta;
 621         uint32_t                                  vddc_vddci_delta;
 622         uint32_t                                  min_vddc_for_pcie_gen2;
 623         struct phm_cac_leakage_table              *cac_leakage_table;
 624         struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
 625
 626         struct phm_vce_clock_voltage_dependency_table
 627                                             *vce_clock_voltage_dependency_table;
 628         struct phm_uvd_clock_voltage_dependency_table
 629                                             *uvd_clock_voltage_dependency_table;
 630         struct phm_acp_clock_voltage_dependency_table
 631                                             *acp_clock_voltage_dependency_table;
 632         struct phm_samu_clock_voltage_dependency_table
 633                                            *samu_clock_voltage_dependency_table;
 634
 635         struct phm_ppm_table                          *ppm_parameter_table;
 636         struct phm_cac_tdp_table                      *cac_dtp_table;
 637         struct phm_clock_voltage_dependency_table       *vdd_gfx_dependency_on_sclk;
 638 };
 639
 640 struct pp_fan_info {
 641         bool bNoFan;
 642         uint8_t   ucTachometerPulsesPerRevolution;
 643         uint32_t   ulMinRPM;
 644         uint32_t   ulMaxRPM;
 645 };
 646
 647 struct pp_advance_fan_control_parameters {
 648         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
 649         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
 650         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
 651         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
 652         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
 653         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
 654         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
 655         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
 656         uint16_t  usTMax;                          /* The max temperature */
 657         uint8_t   ucFanControlMode;
 658         uint16_t  usFanPWMMinLimit;
 659         uint16_t  usFanPWMMaxLimit;
 660         uint16_t  usFanPWMStep;
 661         uint16_t  usDefaultMaxFanPWM;
 662         uint16_t  usFanOutputSensitivity;
 663         uint16_t  usDefaultFanOutputSensitivity;
 664         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
 665         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
 666         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
 667         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
 668         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
 669         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
 670         uint16_t  usFanCurrentLow;                 /* Low current */
 671         uint16_t  usFanCurrentHigh;                /* High current */
 672         uint16_t  usFanRPMLow;                     /* Low RPM */
 673         uint16_t  usFanRPMHigh;                    /* High RPM */
 674         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
 675         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
 676         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
 677         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
 678         uint16_t  usFanGainHotspot;
 679         uint16_t  usFanGainLiquid;
 680         uint16_t  usFanGainVrVddc;
 681         uint16_t  usFanGainVrMvdd;
 682         uint16_t  usFanGainPlx;
 683         uint16_t  usFanGainHbm;
 684         uint8_t   ucEnableZeroRPM;
 685         uint8_t   ucFanStopTemperature;
 686         uint8_t   ucFanStartTemperature;
 687         uint32_t  ulMaxFanSCLKAcousticLimit;       /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
 688         uint32_t  ulTargetGfxClk;
 689         uint16_t  usZeroRPMStartTemperature;
 690         uint16_t  usZeroRPMStopTemperature;
 691 };
 692
 693 struct pp_thermal_controller_info {
 694         uint8_t ucType;
 695         uint8_t ucI2cLine;
 696         uint8_t ucI2cAddress;
 697         struct pp_fan_info fanInfo;
 698         struct pp_advance_fan_control_parameters advanceFanControlParameters;
 699 };
 700
 701 struct phm_microcode_version_info {
 702         uint32_t SMC;
 703         uint32_t DMCU;
 704         uint32_t MC;
 705         uint32_t NB;
 706 };
 707
 708 enum PP_TABLE_VERSION {
 709         PP_TABLE_V0 = 0,
 710         PP_TABLE_V1,
 711         PP_TABLE_V2,
 712         PP_TABLE_MAX
 713 };
 714
 715 /**
 716  * The main hardware manager structure.
 717  */
 718 #define Workload_Policy_Max 5
 719
 720 struct pp_hwmgr {
 721         void *adev;
 722         uint32_t chip_family;
 723         uint32_t chip_id;
 724         uint32_t smu_version;
 725         bool pm_en;
 726         struct mutex smu_lock;
 727
 728         uint32_t pp_table_version;
 729         void *device;
 730         struct pp_smumgr *smumgr;
 731         const void *soft_pp_table;
 732         uint32_t soft_pp_table_size;
 733         void *hardcode_pp_table;
 734         bool need_pp_table_upload;
 735
 736         struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
 737         uint32_t num_vce_state_tables;
 738
 739         enum amd_dpm_forced_level dpm_level;
 740         enum amd_dpm_forced_level saved_dpm_level;
 741         enum amd_dpm_forced_level request_dpm_level;
 742         uint32_t usec_timeout;
 743         void *pptable;
 744         struct phm_platform_descriptor platform_descriptor;
 745         void *backend;
 746
 747         void *smu_backend;
 748         const struct pp_smumgr_func *smumgr_funcs;
 749         bool is_kicker;
 750         bool reload_fw;
 751
 752         enum PP_DAL_POWERLEVEL dal_power_level;
 753         struct phm_dynamic_state_info dyn_state;
 754         const struct pp_hwmgr_func *hwmgr_func;
 755         const struct pp_table_func *pptable_func;
 756
 757         struct pp_power_state    *ps;
 758         enum pp_power_source  power_source;
 759         uint32_t num_ps;
 760         struct pp_thermal_controller_info thermal_controller;
 761         bool fan_ctrl_is_in_default_mode;
 762         uint32_t fan_ctrl_default_mode;
 763         bool fan_ctrl_enabled;
 764         uint32_t tmin;
 765         struct phm_microcode_version_info microcode_version_info;
 766         uint32_t ps_size;
 767         struct pp_power_state    *current_ps;
 768         struct pp_power_state    *request_ps;
 769         struct pp_power_state    *boot_ps;
 770         struct pp_power_state    *uvd_ps;
 771         struct amd_pp_display_configuration display_config;
 772         uint32_t feature_mask;
 773         bool avfs_supported;
 774         /* UMD Pstate */
 775         bool en_umd_pstate;
 776         uint32_t power_profile_mode;
 777         uint32_t default_power_profile_mode;
 778         uint32_t pstate_sclk;
 779         uint32_t pstate_mclk;
 780         bool od_enabled;
 781         uint32_t power_limit;
 782         uint32_t default_power_limit;
 783         uint32_t workload_mask;
 784         uint32_t workload_prority[Workload_Policy_Max];
 785         uint32_t workload_setting[Workload_Policy_Max];
 786 };
 787
 788 struct cgs_irq_src_funcs {
 789         cgs_irq_source_set_func_t set;
 790         cgs_irq_handler_func_t handler;
 791 };
 792
 793 extern int hwmgr_early_init(struct pp_hwmgr *hwmgr);
 794 extern int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
 795 extern int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
 796 extern int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr);
 797 extern int hwmgr_hw_resume(struct pp_hwmgr *hwmgr);
 798 extern int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
 799                                 enum amd_pp_task task_id,
 800                                 enum amd_pm_state_type *user_state);
 801
 802
 803 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 804
 805
 806 #endif /* _HWMGR_H_ */