2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "amd_powerplay.h"
31 #include "vega20_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega20_powertune.h"
37 #include "vega20_inc.h"
38 #include "pppcielanes.h"
39 #include "vega20_hwmgr.h"
40 #include "vega20_processpptables.h"
41 #include "vega20_pptable.h"
42 #include "vega20_thermal.h"
43 #include "vega20_ppsmc.h"
45 #include "amd_pcie_helpers.h"
46 #include "ppinterrupt.h"
47 #include "pp_overdriver.h"
48 #include "pp_thermal.h"
49 #include "soc15_common.h"
50 #include "smuio/smuio_9_0_offset.h"
51 #include "smuio/smuio_9_0_sh_mask.h"
52 #include "nbio/nbio_7_4_sh_mask.h"
54 #define smnPCIE_LC_SPEED_CNTL 0x11140290
55 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
57 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
59 struct vega20_hwmgr *data =
60 (struct vega20_hwmgr *)(hwmgr->backend);
62 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
63 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
64 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
65 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
66 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
68 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
69 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
70 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
71 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
72 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
73 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
74 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
77 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
78 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
79 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
80 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
83 * Disable the following features for now:
92 data->registry_data.disallowed_features = 0xE0041C00;
93 data->registry_data.od_state_in_dc_support = 0;
94 data->registry_data.thermal_support = 1;
95 data->registry_data.skip_baco_hardware = 0;
97 data->registry_data.log_avfs_param = 0;
98 data->registry_data.sclk_throttle_low_notification = 1;
99 data->registry_data.force_dpm_high = 0;
100 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
102 data->registry_data.didt_support = 0;
103 if (data->registry_data.didt_support) {
104 data->registry_data.didt_mode = 6;
105 data->registry_data.sq_ramping_support = 1;
106 data->registry_data.db_ramping_support = 0;
107 data->registry_data.td_ramping_support = 0;
108 data->registry_data.tcp_ramping_support = 0;
109 data->registry_data.dbr_ramping_support = 0;
110 data->registry_data.edc_didt_support = 1;
111 data->registry_data.gc_didt_support = 0;
112 data->registry_data.psm_didt_support = 0;
115 data->registry_data.pcie_lane_override = 0xff;
116 data->registry_data.pcie_speed_override = 0xff;
117 data->registry_data.pcie_clock_override = 0xffffffff;
118 data->registry_data.regulator_hot_gpio_support = 1;
119 data->registry_data.ac_dc_switch_gpio_support = 0;
120 data->registry_data.quick_transition_support = 0;
121 data->registry_data.zrpm_start_temp = 0xffff;
122 data->registry_data.zrpm_stop_temp = 0xffff;
123 data->registry_data.od8_feature_enable = 1;
124 data->registry_data.disable_water_mark = 0;
125 data->registry_data.disable_pp_tuning = 0;
126 data->registry_data.disable_xlpp_tuning = 0;
127 data->registry_data.disable_workload_policy = 0;
128 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
129 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
130 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
131 data->registry_data.force_workload_policy_mask = 0;
132 data->registry_data.disable_3d_fs_detection = 0;
133 data->registry_data.fps_support = 1;
134 data->registry_data.disable_auto_wattman = 1;
135 data->registry_data.auto_wattman_debug = 0;
136 data->registry_data.auto_wattman_sample_period = 100;
137 data->registry_data.fclk_gfxclk_ratio = 0;
138 data->registry_data.auto_wattman_threshold = 50;
139 data->registry_data.gfxoff_controlled_by_driver = 1;
140 data->gfxoff_allowed = false;
141 data->counter_gfxoff = 0;
144 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
146 struct vega20_hwmgr *data =
147 (struct vega20_hwmgr *)(hwmgr->backend);
148 struct amdgpu_device *adev = hwmgr->adev;
150 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
151 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
152 PHM_PlatformCaps_ControlVDDCI);
154 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
155 PHM_PlatformCaps_TablelessHardwareInterface);
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 PHM_PlatformCaps_EnableSMU7ThermalManagement);
160 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
161 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
162 PHM_PlatformCaps_UVDPowerGating);
164 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
165 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
166 PHM_PlatformCaps_VCEPowerGating);
168 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
169 PHM_PlatformCaps_UnTabledHardwareInterface);
171 if (data->registry_data.od8_feature_enable)
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_OD8inACSupport);
175 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
176 PHM_PlatformCaps_ActivityReporting);
177 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
178 PHM_PlatformCaps_FanSpeedInTableIsRPM);
180 if (data->registry_data.od_state_in_dc_support) {
181 if (data->registry_data.od8_feature_enable)
182 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
183 PHM_PlatformCaps_OD8inDCSupport);
186 if (data->registry_data.thermal_support &&
187 data->registry_data.fuzzy_fan_control_support &&
188 hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
189 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
190 PHM_PlatformCaps_ODFuzzyFanControlSupport);
192 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193 PHM_PlatformCaps_DynamicPowerManagement);
194 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
195 PHM_PlatformCaps_SMC);
196 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
197 PHM_PlatformCaps_ThermalPolicyDelay);
199 if (data->registry_data.force_dpm_high)
200 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
201 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_DynamicUVDState);
206 if (data->registry_data.sclk_throttle_low_notification)
207 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
208 PHM_PlatformCaps_SclkThrottleLowNotification);
210 /* power tune caps */
211 /* assume disabled */
212 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_PowerContainment);
214 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
215 PHM_PlatformCaps_DiDtSupport);
216 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_SQRamping);
218 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
219 PHM_PlatformCaps_DBRamping);
220 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
221 PHM_PlatformCaps_TDRamping);
222 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_TCPRamping);
224 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
225 PHM_PlatformCaps_DBRRamping);
226 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
227 PHM_PlatformCaps_DiDtEDCEnable);
228 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
229 PHM_PlatformCaps_GCEDC);
230 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
231 PHM_PlatformCaps_PSM);
233 if (data->registry_data.didt_support) {
234 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
235 PHM_PlatformCaps_DiDtSupport);
236 if (data->registry_data.sq_ramping_support)
237 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
238 PHM_PlatformCaps_SQRamping);
239 if (data->registry_data.db_ramping_support)
240 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
241 PHM_PlatformCaps_DBRamping);
242 if (data->registry_data.td_ramping_support)
243 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
244 PHM_PlatformCaps_TDRamping);
245 if (data->registry_data.tcp_ramping_support)
246 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
247 PHM_PlatformCaps_TCPRamping);
248 if (data->registry_data.dbr_ramping_support)
249 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
250 PHM_PlatformCaps_DBRRamping);
251 if (data->registry_data.edc_didt_support)
252 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
253 PHM_PlatformCaps_DiDtEDCEnable);
254 if (data->registry_data.gc_didt_support)
255 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
256 PHM_PlatformCaps_GCEDC);
257 if (data->registry_data.psm_didt_support)
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
259 PHM_PlatformCaps_PSM);
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
263 PHM_PlatformCaps_RegulatorHot);
265 if (data->registry_data.ac_dc_switch_gpio_support) {
266 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
267 PHM_PlatformCaps_AutomaticDCTransition);
268 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
269 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
272 if (data->registry_data.quick_transition_support) {
273 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
274 PHM_PlatformCaps_AutomaticDCTransition);
275 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
276 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
277 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
278 PHM_PlatformCaps_Falcon_QuickTransition);
281 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
282 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
283 PHM_PlatformCaps_LowestUclkReservedForUlv);
284 if (data->lowest_uclk_reserved_for_ulv == 1)
285 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
286 PHM_PlatformCaps_LowestUclkReservedForUlv);
289 if (data->registry_data.custom_fan_support)
290 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_CustomFanControlSupport);
296 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
298 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
301 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
302 FEATURE_DPM_PREFETCHER_BIT;
303 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
304 FEATURE_DPM_GFXCLK_BIT;
305 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
306 FEATURE_DPM_UCLK_BIT;
307 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
308 FEATURE_DPM_SOCCLK_BIT;
309 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
311 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
313 data->smu_features[GNLD_ULV].smu_feature_id =
315 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
316 FEATURE_DPM_MP0CLK_BIT;
317 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
318 FEATURE_DPM_LINK_BIT;
319 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
320 FEATURE_DPM_DCEFCLK_BIT;
321 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
322 FEATURE_DS_GFXCLK_BIT;
323 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
324 FEATURE_DS_SOCCLK_BIT;
325 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
327 data->smu_features[GNLD_PPT].smu_feature_id =
329 data->smu_features[GNLD_TDC].smu_feature_id =
331 data->smu_features[GNLD_THERMAL].smu_feature_id =
333 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
334 FEATURE_GFX_PER_CU_CG_BIT;
335 data->smu_features[GNLD_RM].smu_feature_id =
337 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
338 FEATURE_DS_DCEFCLK_BIT;
339 data->smu_features[GNLD_ACDC].smu_feature_id =
341 data->smu_features[GNLD_VR0HOT].smu_feature_id =
343 data->smu_features[GNLD_VR1HOT].smu_feature_id =
345 data->smu_features[GNLD_FW_CTF].smu_feature_id =
347 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
348 FEATURE_LED_DISPLAY_BIT;
349 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
350 FEATURE_FAN_CONTROL_BIT;
351 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
352 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
353 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
354 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
355 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
356 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
357 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
358 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
360 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
361 data->smu_features[i].smu_feature_bitmap =
362 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
363 data->smu_features[i].allowed =
364 ((data->registry_data.disallowed_features >> i) & 1) ?
369 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
374 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
376 kfree(hwmgr->backend);
377 hwmgr->backend = NULL;
382 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
384 struct vega20_hwmgr *data;
385 struct amdgpu_device *adev = hwmgr->adev;
387 data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
391 hwmgr->backend = data;
393 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
394 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
395 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
397 vega20_set_default_registry_data(hwmgr);
399 data->disable_dpm_mask = 0xff;
401 /* need to set voltage control types before EVV patching */
402 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
403 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
404 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
406 data->water_marks_bitmap = 0;
407 data->avfs_exist = false;
409 vega20_set_features_platform_caps(hwmgr);
411 vega20_init_dpm_defaults(hwmgr);
413 /* Parse pptable data read from VBIOS */
414 vega20_set_private_data_based_on_pptable(hwmgr);
416 data->is_tlu_enabled = false;
418 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
419 VEGA20_MAX_HARDWARE_POWERLEVELS;
420 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
421 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
423 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
424 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
425 hwmgr->platform_descriptor.clockStep.engineClock = 500;
426 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
428 data->total_active_cus = adev->gfx.cu_info.number;
433 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
435 struct vega20_hwmgr *data =
436 (struct vega20_hwmgr *)(hwmgr->backend);
438 data->low_sclk_interrupt_threshold = 0;
443 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
447 ret = vega20_init_sclk_threshold(hwmgr);
448 PP_ASSERT_WITH_CODE(!ret,
449 "Failed to init sclk threshold!",
456 * @fn vega20_init_dpm_state
457 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
459 * @param dpm_state - the address of the DPM Table to initiailize.
462 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
464 dpm_state->soft_min_level = 0x0;
465 dpm_state->soft_max_level = 0xffff;
466 dpm_state->hard_min_level = 0x0;
467 dpm_state->hard_max_level = 0xffff;
470 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
471 PPCLK_e clk_id, uint32_t *num_of_levels)
475 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
476 PPSMC_MSG_GetDpmFreqByIndex,
477 (clk_id << 16 | 0xFF));
478 PP_ASSERT_WITH_CODE(!ret,
479 "[GetNumOfDpmLevel] failed to get dpm levels!",
482 *num_of_levels = smum_get_argument(hwmgr);
483 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
484 "[GetNumOfDpmLevel] number of clk levels is invalid!",
490 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
491 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
495 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
496 PPSMC_MSG_GetDpmFreqByIndex,
497 (clk_id << 16 | index));
498 PP_ASSERT_WITH_CODE(!ret,
499 "[GetDpmFreqByIndex] failed to get dpm freq by index!",
502 *clk = smum_get_argument(hwmgr);
503 PP_ASSERT_WITH_CODE(*clk,
504 "[GetDpmFreqByIndex] clk value is invalid!",
510 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
511 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
514 uint32_t i, num_of_levels, clk;
516 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
517 PP_ASSERT_WITH_CODE(!ret,
518 "[SetupSingleDpmTable] failed to get clk levels!",
521 dpm_table->count = num_of_levels;
523 for (i = 0; i < num_of_levels; i++) {
524 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
525 PP_ASSERT_WITH_CODE(!ret,
526 "[SetupSingleDpmTable] failed to get clk of specific level!",
528 dpm_table->dpm_levels[i].value = clk;
529 dpm_table->dpm_levels[i].enabled = true;
535 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
537 struct vega20_hwmgr *data =
538 (struct vega20_hwmgr *)(hwmgr->backend);
539 struct vega20_single_dpm_table *dpm_table;
542 dpm_table = &(data->dpm_table.gfx_table);
543 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
544 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
545 PP_ASSERT_WITH_CODE(!ret,
546 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
549 dpm_table->count = 1;
550 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
556 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
558 struct vega20_hwmgr *data =
559 (struct vega20_hwmgr *)(hwmgr->backend);
560 struct vega20_single_dpm_table *dpm_table;
563 dpm_table = &(data->dpm_table.mem_table);
564 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
565 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
566 PP_ASSERT_WITH_CODE(!ret,
567 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
570 dpm_table->count = 1;
571 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
578 * This function is to initialize all DPM state tables
579 * for SMU based on the dependency table.
580 * Dynamic state patching function will then trim these
581 * state tables to the allowed range based
582 * on the power policy or external client requests,
583 * such as UVD request, etc.
585 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
587 struct vega20_hwmgr *data =
588 (struct vega20_hwmgr *)(hwmgr->backend);
589 struct vega20_single_dpm_table *dpm_table;
592 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
595 dpm_table = &(data->dpm_table.soc_table);
596 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
597 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
598 PP_ASSERT_WITH_CODE(!ret,
599 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
602 dpm_table->count = 1;
603 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
605 vega20_init_dpm_state(&(dpm_table->dpm_state));
608 dpm_table = &(data->dpm_table.gfx_table);
609 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
612 vega20_init_dpm_state(&(dpm_table->dpm_state));
615 dpm_table = &(data->dpm_table.mem_table);
616 ret = vega20_setup_memclk_dpm_table(hwmgr);
619 vega20_init_dpm_state(&(dpm_table->dpm_state));
622 dpm_table = &(data->dpm_table.eclk_table);
623 if (data->smu_features[GNLD_DPM_VCE].enabled) {
624 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
625 PP_ASSERT_WITH_CODE(!ret,
626 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
629 dpm_table->count = 1;
630 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
632 vega20_init_dpm_state(&(dpm_table->dpm_state));
635 dpm_table = &(data->dpm_table.vclk_table);
636 if (data->smu_features[GNLD_DPM_UVD].enabled) {
637 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
638 PP_ASSERT_WITH_CODE(!ret,
639 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
642 dpm_table->count = 1;
643 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
645 vega20_init_dpm_state(&(dpm_table->dpm_state));
648 dpm_table = &(data->dpm_table.dclk_table);
649 if (data->smu_features[GNLD_DPM_UVD].enabled) {
650 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
651 PP_ASSERT_WITH_CODE(!ret,
652 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
655 dpm_table->count = 1;
656 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
658 vega20_init_dpm_state(&(dpm_table->dpm_state));
661 dpm_table = &(data->dpm_table.dcef_table);
662 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
663 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
664 PP_ASSERT_WITH_CODE(!ret,
665 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
668 dpm_table->count = 1;
669 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
671 vega20_init_dpm_state(&(dpm_table->dpm_state));
674 dpm_table = &(data->dpm_table.pixel_table);
675 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
676 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
677 PP_ASSERT_WITH_CODE(!ret,
678 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
681 dpm_table->count = 0;
682 vega20_init_dpm_state(&(dpm_table->dpm_state));
685 dpm_table = &(data->dpm_table.display_table);
686 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
687 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
688 PP_ASSERT_WITH_CODE(!ret,
689 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
692 dpm_table->count = 0;
693 vega20_init_dpm_state(&(dpm_table->dpm_state));
696 dpm_table = &(data->dpm_table.phy_table);
697 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
698 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
699 PP_ASSERT_WITH_CODE(!ret,
700 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
703 dpm_table->count = 0;
704 vega20_init_dpm_state(&(dpm_table->dpm_state));
707 dpm_table = &(data->dpm_table.fclk_table);
708 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
709 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
710 PP_ASSERT_WITH_CODE(!ret,
711 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
714 dpm_table->count = 0;
715 vega20_init_dpm_state(&(dpm_table->dpm_state));
717 /* save a copy of the default DPM table */
718 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
719 sizeof(struct vega20_dpm_table));
725 * Initializes the SMC table and uploads it
727 * @param hwmgr the address of the powerplay hardware manager.
728 * @param pInput the pointer to input data (PowerState)
731 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
734 struct vega20_hwmgr *data =
735 (struct vega20_hwmgr *)(hwmgr->backend);
736 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
737 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
738 struct phm_ppt_v3_information *pptable_information =
739 (struct phm_ppt_v3_information *)hwmgr->pptable;
741 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
742 PP_ASSERT_WITH_CODE(!result,
743 "[InitSMCTable] Failed to get vbios bootup values!",
746 data->vbios_boot_state.vddc = boot_up_values.usVddc;
747 data->vbios_boot_state.vddci = boot_up_values.usVddci;
748 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
749 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
750 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
751 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
752 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
753 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
754 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
755 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
756 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
758 smum_send_msg_to_smc_with_parameter(hwmgr,
759 PPSMC_MSG_SetMinDeepSleepDcefclk,
760 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
762 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
764 result = smum_smc_table_manager(hwmgr,
765 (uint8_t *)pp_table, TABLE_PPTABLE, false);
766 PP_ASSERT_WITH_CODE(!result,
767 "[InitSMCTable] Failed to upload PPtable!",
773 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
775 struct vega20_hwmgr *data =
776 (struct vega20_hwmgr *)(hwmgr->backend);
777 uint32_t allowed_features_low = 0, allowed_features_high = 0;
781 for (i = 0; i < GNLD_FEATURES_MAX; i++)
782 if (data->smu_features[i].allowed)
783 data->smu_features[i].smu_feature_id > 31 ?
784 (allowed_features_high |=
785 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
787 (allowed_features_low |=
788 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
791 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
792 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
793 PP_ASSERT_WITH_CODE(!ret,
794 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
797 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
798 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
799 PP_ASSERT_WITH_CODE(!ret,
800 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
806 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
808 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
811 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
813 struct vega20_hwmgr *data =
814 (struct vega20_hwmgr *)(hwmgr->backend);
815 uint64_t features_enabled;
820 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
821 PPSMC_MSG_EnableAllSmuFeatures)) == 0,
822 "[EnableAllSMUFeatures] Failed to enable all smu features!",
825 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
826 PP_ASSERT_WITH_CODE(!ret,
827 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
830 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
831 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
833 data->smu_features[i].enabled = enabled;
834 data->smu_features[i].supported = enabled;
837 if (data->smu_features[i].allowed && !enabled)
838 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
839 else if (!data->smu_features[i].allowed && enabled)
840 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
847 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
849 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
851 if (data->smu_features[GNLD_DPM_UCLK].enabled)
852 return smum_send_msg_to_smc_with_parameter(hwmgr,
853 PPSMC_MSG_SetUclkFastSwitch,
859 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
861 struct vega20_hwmgr *data =
862 (struct vega20_hwmgr *)(hwmgr->backend);
864 return smum_send_msg_to_smc_with_parameter(hwmgr,
865 PPSMC_MSG_SetFclkGfxClkRatio,
866 data->registry_data.fclk_gfxclk_ratio);
869 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
871 struct vega20_hwmgr *data =
872 (struct vega20_hwmgr *)(hwmgr->backend);
873 uint64_t features_enabled;
878 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
879 PPSMC_MSG_DisableAllSmuFeatures)) == 0,
880 "[DisableAllSMUFeatures] Failed to disable all smu features!",
883 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
884 PP_ASSERT_WITH_CODE(!ret,
885 "[DisableAllSMUFeatures] Failed to get enabled smc features!",
888 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
889 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
891 data->smu_features[i].enabled = enabled;
892 data->smu_features[i].supported = enabled;
898 static int vega20_od8_set_feature_capabilities(
899 struct pp_hwmgr *hwmgr)
901 struct phm_ppt_v3_information *pptable_information =
902 (struct phm_ppt_v3_information *)hwmgr->pptable;
903 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
904 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
905 struct vega20_od8_settings *od_settings = &(data->od8_settings);
907 od_settings->overdrive8_capabilities = 0;
909 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
910 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
911 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
912 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
913 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
914 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
915 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
917 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
918 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
919 pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
920 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
921 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
922 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
923 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
924 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
927 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
928 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
929 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
930 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
931 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
932 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
933 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
936 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
937 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
938 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
939 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
940 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
941 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
943 if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
944 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
945 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
946 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
947 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
948 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
949 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
951 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
952 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
953 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
954 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
955 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
956 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
957 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
960 if (data->smu_features[GNLD_THERMAL].enabled) {
961 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
962 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
963 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
964 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
965 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
966 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
968 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
969 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
970 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
971 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
972 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
973 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
976 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
977 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
979 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
980 pp_table->FanZeroRpmEnable)
981 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
986 static int vega20_od8_set_feature_id(
987 struct pp_hwmgr *hwmgr)
989 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
990 struct vega20_od8_settings *od_settings = &(data->od8_settings);
992 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
993 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
995 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
998 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1000 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1004 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1005 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1007 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1009 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1011 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1013 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1015 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1018 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1020 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1022 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1024 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1026 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1028 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1032 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1033 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1035 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1037 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1038 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1040 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1042 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1043 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1044 OD8_ACOUSTIC_LIMIT_SCLK;
1046 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1049 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1050 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1053 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1056 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1057 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1058 OD8_TEMPERATURE_FAN;
1060 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1063 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1064 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1065 OD8_TEMPERATURE_SYSTEM;
1067 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1073 static int vega20_od8_get_gfx_clock_base_voltage(
1074 struct pp_hwmgr *hwmgr,
1080 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1081 PPSMC_MSG_GetAVFSVoltageByDpm,
1082 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1083 PP_ASSERT_WITH_CODE(!ret,
1084 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1087 *voltage = smum_get_argument(hwmgr);
1088 *voltage = *voltage / VOLTAGE_SCALE;
1093 static int vega20_od8_initialize_default_settings(
1094 struct pp_hwmgr *hwmgr)
1096 struct phm_ppt_v3_information *pptable_information =
1097 (struct phm_ppt_v3_information *)hwmgr->pptable;
1098 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1099 struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1100 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1103 /* Set Feature Capabilities */
1104 vega20_od8_set_feature_capabilities(hwmgr);
1106 /* Map FeatureID to individual settings */
1107 vega20_od8_set_feature_id(hwmgr);
1109 /* Set default values */
1110 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1111 PP_ASSERT_WITH_CODE(!ret,
1112 "Failed to export over drive table!",
1115 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1116 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1117 od_table->GfxclkFmin;
1118 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1119 od_table->GfxclkFmax;
1121 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1123 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1127 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1128 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1129 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1130 od_table->GfxclkFreq1;
1132 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1133 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1134 od_table->GfxclkFreq3;
1136 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1137 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1138 od_table->GfxclkFreq2;
1140 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1141 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1142 od_table->GfxclkFreq1),
1143 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1144 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1145 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1148 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1149 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1150 od_table->GfxclkFreq2),
1151 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1152 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1153 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1156 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1157 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1158 od_table->GfxclkFreq3),
1159 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1160 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1161 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1164 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1166 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1168 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1170 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1172 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1174 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1178 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1179 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1182 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1185 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1186 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1187 od_table->OverDrivePct;
1189 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1192 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1193 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1194 od_table->FanMaximumRpm;
1196 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1199 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1200 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1201 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1203 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1206 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1207 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1208 od_table->FanTargetTemperature;
1210 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1213 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1214 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1215 od_table->MaxOpTemp;
1217 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1220 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1221 if (od8_settings->od8_settings_array[i].feature_id) {
1222 od8_settings->od8_settings_array[i].min_value =
1223 pptable_information->od_settings_min[i];
1224 od8_settings->od8_settings_array[i].max_value =
1225 pptable_information->od_settings_max[i];
1226 od8_settings->od8_settings_array[i].current_value =
1227 od8_settings->od8_settings_array[i].default_value;
1229 od8_settings->od8_settings_array[i].min_value =
1231 od8_settings->od8_settings_array[i].max_value =
1233 od8_settings->od8_settings_array[i].current_value =
1238 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1239 PP_ASSERT_WITH_CODE(!ret,
1240 "Failed to import over drive table!",
1246 static int vega20_od8_set_settings(
1247 struct pp_hwmgr *hwmgr,
1251 OverDriveTable_t od_table;
1253 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1254 struct vega20_od8_single_setting *od8_settings =
1255 data->od8_settings.od8_settings_array;
1257 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1258 PP_ASSERT_WITH_CODE(!ret,
1259 "Failed to export over drive table!",
1263 case OD8_SETTING_GFXCLK_FMIN:
1264 od_table.GfxclkFmin = (uint16_t)value;
1266 case OD8_SETTING_GFXCLK_FMAX:
1267 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1268 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1271 od_table.GfxclkFmax = (uint16_t)value;
1273 case OD8_SETTING_GFXCLK_FREQ1:
1274 od_table.GfxclkFreq1 = (uint16_t)value;
1276 case OD8_SETTING_GFXCLK_VOLTAGE1:
1277 od_table.GfxclkVolt1 = (uint16_t)value;
1279 case OD8_SETTING_GFXCLK_FREQ2:
1280 od_table.GfxclkFreq2 = (uint16_t)value;
1282 case OD8_SETTING_GFXCLK_VOLTAGE2:
1283 od_table.GfxclkVolt2 = (uint16_t)value;
1285 case OD8_SETTING_GFXCLK_FREQ3:
1286 od_table.GfxclkFreq3 = (uint16_t)value;
1288 case OD8_SETTING_GFXCLK_VOLTAGE3:
1289 od_table.GfxclkVolt3 = (uint16_t)value;
1291 case OD8_SETTING_UCLK_FMAX:
1292 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1293 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1295 od_table.UclkFmax = (uint16_t)value;
1297 case OD8_SETTING_POWER_PERCENTAGE:
1298 od_table.OverDrivePct = (int16_t)value;
1300 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1301 od_table.FanMaximumRpm = (uint16_t)value;
1303 case OD8_SETTING_FAN_MIN_SPEED:
1304 od_table.FanMinimumPwm = (uint16_t)value;
1306 case OD8_SETTING_FAN_TARGET_TEMP:
1307 od_table.FanTargetTemperature = (uint16_t)value;
1309 case OD8_SETTING_OPERATING_TEMP_MAX:
1310 od_table.MaxOpTemp = (uint16_t)value;
1314 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1315 PP_ASSERT_WITH_CODE(!ret,
1316 "Failed to import over drive table!",
1322 static int vega20_get_sclk_od(
1323 struct pp_hwmgr *hwmgr)
1325 struct vega20_hwmgr *data = hwmgr->backend;
1326 struct vega20_single_dpm_table *sclk_table =
1327 &(data->dpm_table.gfx_table);
1328 struct vega20_single_dpm_table *golden_sclk_table =
1329 &(data->golden_dpm_table.gfx_table);
1330 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1331 int golden_value = golden_sclk_table->dpm_levels
1332 [golden_sclk_table->count - 1].value;
1335 value -= golden_value;
1336 value = DIV_ROUND_UP(value * 100, golden_value);
1341 static int vega20_set_sclk_od(
1342 struct pp_hwmgr *hwmgr, uint32_t value)
1344 struct vega20_hwmgr *data = hwmgr->backend;
1345 struct vega20_single_dpm_table *golden_sclk_table =
1346 &(data->golden_dpm_table.gfx_table);
1350 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1352 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1354 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1355 PP_ASSERT_WITH_CODE(!ret,
1356 "[SetSclkOD] failed to set od gfxclk!",
1359 /* retrieve updated gfxclk table */
1360 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1361 PP_ASSERT_WITH_CODE(!ret,
1362 "[SetSclkOD] failed to refresh gfxclk table!",
1368 static int vega20_get_mclk_od(
1369 struct pp_hwmgr *hwmgr)
1371 struct vega20_hwmgr *data = hwmgr->backend;
1372 struct vega20_single_dpm_table *mclk_table =
1373 &(data->dpm_table.mem_table);
1374 struct vega20_single_dpm_table *golden_mclk_table =
1375 &(data->golden_dpm_table.mem_table);
1376 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1377 int golden_value = golden_mclk_table->dpm_levels
1378 [golden_mclk_table->count - 1].value;
1381 value -= golden_value;
1382 value = DIV_ROUND_UP(value * 100, golden_value);
1387 static int vega20_set_mclk_od(
1388 struct pp_hwmgr *hwmgr, uint32_t value)
1390 struct vega20_hwmgr *data = hwmgr->backend;
1391 struct vega20_single_dpm_table *golden_mclk_table =
1392 &(data->golden_dpm_table.mem_table);
1396 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1398 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1400 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1401 PP_ASSERT_WITH_CODE(!ret,
1402 "[SetMclkOD] failed to set od memclk!",
1405 /* retrieve updated memclk table */
1406 ret = vega20_setup_memclk_dpm_table(hwmgr);
1407 PP_ASSERT_WITH_CODE(!ret,
1408 "[SetMclkOD] failed to refresh memclk table!",
1414 static int vega20_populate_umdpstate_clocks(
1415 struct pp_hwmgr *hwmgr)
1417 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1418 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1419 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1421 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1422 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1424 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1425 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1426 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1427 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1430 hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1431 hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1436 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1437 PP_Clock *clock, PPCLK_e clock_select)
1441 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1442 PPSMC_MSG_GetDcModeMaxDpmFreq,
1443 (clock_select << 16))) == 0,
1444 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1446 *clock = smum_get_argument(hwmgr);
1448 /* if DC limit is zero, return AC limit */
1450 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1451 PPSMC_MSG_GetMaxDpmFreq,
1452 (clock_select << 16))) == 0,
1453 "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1455 *clock = smum_get_argument(hwmgr);
1461 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1463 struct vega20_hwmgr *data =
1464 (struct vega20_hwmgr *)(hwmgr->backend);
1465 struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1466 &(data->max_sustainable_clocks);
1469 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1470 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1471 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1472 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1473 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1474 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1476 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1477 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1478 &(max_sustainable_clocks->uclock),
1480 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1483 if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1484 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1485 &(max_sustainable_clocks->soc_clock),
1486 PPCLK_SOCCLK)) == 0,
1487 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1490 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1491 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1492 &(max_sustainable_clocks->dcef_clock),
1493 PPCLK_DCEFCLK)) == 0,
1494 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1496 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1497 &(max_sustainable_clocks->display_clock),
1498 PPCLK_DISPCLK)) == 0,
1499 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1501 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1502 &(max_sustainable_clocks->phy_clock),
1503 PPCLK_PHYCLK)) == 0,
1504 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1506 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1507 &(max_sustainable_clocks->pixel_clock),
1508 PPCLK_PIXCLK)) == 0,
1509 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1513 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1514 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1519 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1523 result = smum_send_msg_to_smc(hwmgr,
1524 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1525 PP_ASSERT_WITH_CODE(!result,
1526 "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1532 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1534 struct vega20_hwmgr *data =
1535 (struct vega20_hwmgr *)(hwmgr->backend);
1537 data->uvd_power_gated = true;
1538 data->vce_power_gated = true;
1540 if (data->smu_features[GNLD_DPM_UVD].enabled)
1541 data->uvd_power_gated = false;
1543 if (data->smu_features[GNLD_DPM_VCE].enabled)
1544 data->vce_power_gated = false;
1547 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1551 smum_send_msg_to_smc_with_parameter(hwmgr,
1552 PPSMC_MSG_NumOfDisplays, 0);
1554 result = vega20_set_allowed_featuresmask(hwmgr);
1555 PP_ASSERT_WITH_CODE(!result,
1556 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1559 result = vega20_init_smc_table(hwmgr);
1560 PP_ASSERT_WITH_CODE(!result,
1561 "[EnableDPMTasks] Failed to initialize SMC table!",
1564 result = vega20_run_btc_afll(hwmgr);
1565 PP_ASSERT_WITH_CODE(!result,
1566 "[EnableDPMTasks] Failed to run btc afll!",
1569 result = vega20_enable_all_smu_features(hwmgr);
1570 PP_ASSERT_WITH_CODE(!result,
1571 "[EnableDPMTasks] Failed to enable all smu features!",
1574 result = vega20_notify_smc_display_change(hwmgr);
1575 PP_ASSERT_WITH_CODE(!result,
1576 "[EnableDPMTasks] Failed to notify smc display change!",
1579 result = vega20_send_clock_ratio(hwmgr);
1580 PP_ASSERT_WITH_CODE(!result,
1581 "[EnableDPMTasks] Failed to send clock ratio!",
1584 /* Initialize UVD/VCE powergating state */
1585 vega20_init_powergate_state(hwmgr);
1587 result = vega20_setup_default_dpm_tables(hwmgr);
1588 PP_ASSERT_WITH_CODE(!result,
1589 "[EnableDPMTasks] Failed to setup default DPM tables!",
1592 result = vega20_init_max_sustainable_clocks(hwmgr);
1593 PP_ASSERT_WITH_CODE(!result,
1594 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1597 result = vega20_power_control_set_level(hwmgr);
1598 PP_ASSERT_WITH_CODE(!result,
1599 "[EnableDPMTasks] Failed to power control set level!",
1602 result = vega20_od8_initialize_default_settings(hwmgr);
1603 PP_ASSERT_WITH_CODE(!result,
1604 "[EnableDPMTasks] Failed to initialize odn settings!",
1607 result = vega20_populate_umdpstate_clocks(hwmgr);
1608 PP_ASSERT_WITH_CODE(!result,
1609 "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1612 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1613 POWER_SOURCE_AC << 16);
1614 PP_ASSERT_WITH_CODE(!result,
1615 "[GetPptLimit] get default PPT limit failed!",
1617 hwmgr->power_limit =
1618 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1623 static uint32_t vega20_find_lowest_dpm_level(
1624 struct vega20_single_dpm_table *table)
1628 for (i = 0; i < table->count; i++) {
1629 if (table->dpm_levels[i].enabled)
1632 if (i >= table->count) {
1634 table->dpm_levels[i].enabled = true;
1640 static uint32_t vega20_find_highest_dpm_level(
1641 struct vega20_single_dpm_table *table)
1645 PP_ASSERT_WITH_CODE(table != NULL,
1646 "[FindHighestDPMLevel] DPM Table does not exist!",
1648 PP_ASSERT_WITH_CODE(table->count > 0,
1649 "[FindHighestDPMLevel] DPM Table has no entry!",
1651 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1652 "[FindHighestDPMLevel] DPM Table has too many entries!",
1653 return MAX_REGULAR_DPM_NUMBER - 1);
1655 for (i = table->count - 1; i >= 0; i--) {
1656 if (table->dpm_levels[i].enabled)
1661 table->dpm_levels[i].enabled = true;
1667 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1669 struct vega20_hwmgr *data =
1670 (struct vega20_hwmgr *)(hwmgr->backend);
1674 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1675 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1676 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1677 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1678 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1679 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1680 "Failed to set soft min gfxclk !",
1684 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1685 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1686 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1687 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1688 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1689 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1690 "Failed to set soft min memclk !",
1693 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1694 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1695 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1696 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1697 "Failed to set hard min memclk !",
1701 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1702 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1703 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1705 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1706 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1707 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1708 "Failed to set soft min vclk!",
1711 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1713 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1714 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1715 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1716 "Failed to set soft min dclk!",
1720 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1721 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1722 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1724 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1725 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1726 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1727 "Failed to set soft min eclk!",
1731 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1732 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1733 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1735 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1736 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1737 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1738 "Failed to set soft min socclk!",
1745 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1747 struct vega20_hwmgr *data =
1748 (struct vega20_hwmgr *)(hwmgr->backend);
1752 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1753 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1754 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1756 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1757 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1758 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1759 "Failed to set soft max gfxclk!",
1763 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1764 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1765 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1767 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1768 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1769 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1770 "Failed to set soft max memclk!",
1774 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1775 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1776 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1778 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1779 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1780 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1781 "Failed to set soft max vclk!",
1784 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1785 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1786 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1787 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1788 "Failed to set soft max dclk!",
1792 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1793 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1794 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1796 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1797 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1798 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1799 "Failed to set soft max eclk!",
1803 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1804 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1805 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1807 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1808 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1809 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1810 "Failed to set soft max socclk!",
1817 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1819 struct vega20_hwmgr *data =
1820 (struct vega20_hwmgr *)(hwmgr->backend);
1823 if (data->smu_features[GNLD_DPM_VCE].supported) {
1824 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1826 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1828 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1831 ret = vega20_enable_smc_features(hwmgr,
1833 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1834 PP_ASSERT_WITH_CODE(!ret,
1835 "Attempt to Enable/Disable DPM VCE Failed!",
1837 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1843 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1845 PPCLK_e clock_select,
1852 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1853 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1854 "[GetClockRanges] Failed to get max clock from SMC!",
1856 *clock = smum_get_argument(hwmgr);
1858 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1859 PPSMC_MSG_GetMinDpmFreq,
1860 (clock_select << 16))) == 0,
1861 "[GetClockRanges] Failed to get min clock from SMC!",
1863 *clock = smum_get_argument(hwmgr);
1869 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1871 struct vega20_hwmgr *data =
1872 (struct vega20_hwmgr *)(hwmgr->backend);
1876 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1877 "[GetSclks]: gfxclk dpm not enabled!\n",
1881 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1882 PP_ASSERT_WITH_CODE(!ret,
1883 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1886 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1887 PP_ASSERT_WITH_CODE(!ret,
1888 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1892 return (gfx_clk * 100);
1895 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1897 struct vega20_hwmgr *data =
1898 (struct vega20_hwmgr *)(hwmgr->backend);
1902 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1903 "[MemMclks]: memclk dpm not enabled!\n",
1907 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
1908 PP_ASSERT_WITH_CODE(!ret,
1909 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1912 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
1913 PP_ASSERT_WITH_CODE(!ret,
1914 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1918 return (mem_clk * 100);
1921 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1925 SmuMetrics_t metrics_table;
1927 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1928 PP_ASSERT_WITH_CODE(!ret,
1929 "Failed to export SMU METRICS table!",
1932 *query = metrics_table.CurrSocketPower << 8;
1937 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1938 PPCLK_e clk_id, uint32_t *clk_freq)
1944 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1945 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1946 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1948 *clk_freq = smum_get_argument(hwmgr);
1950 *clk_freq = *clk_freq * 100;
1955 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1956 uint32_t *activity_percent)
1959 SmuMetrics_t metrics_table;
1961 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1962 PP_ASSERT_WITH_CODE(!ret,
1963 "Failed to export SMU METRICS table!",
1966 *activity_percent = metrics_table.AverageGfxActivity;
1971 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1972 void *value, int *size)
1974 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1975 struct amdgpu_device *adev = hwmgr->adev;
1980 case AMDGPU_PP_SENSOR_GFX_SCLK:
1981 ret = vega20_get_current_clk_freq(hwmgr,
1987 case AMDGPU_PP_SENSOR_GFX_MCLK:
1988 ret = vega20_get_current_clk_freq(hwmgr,
1994 case AMDGPU_PP_SENSOR_GPU_LOAD:
1995 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
1999 case AMDGPU_PP_SENSOR_GPU_TEMP:
2000 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
2003 case AMDGPU_PP_SENSOR_UVD_POWER:
2004 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2007 case AMDGPU_PP_SENSOR_VCE_POWER:
2008 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2011 case AMDGPU_PP_SENSOR_GPU_POWER:
2013 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2015 case AMDGPU_PP_SENSOR_VDDGFX:
2016 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2017 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2018 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2019 *((uint32_t *)value) =
2020 (uint32_t)convert_to_vddc((uint8_t)val_vid);
2022 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2023 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2034 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2035 struct pp_display_clock_request *clock_req)
2038 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2039 enum amd_pp_clock_type clk_type = clock_req->clock_type;
2040 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2041 PPCLK_e clk_select = 0;
2042 uint32_t clk_request = 0;
2044 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2046 case amd_pp_dcef_clock:
2047 clk_select = PPCLK_DCEFCLK;
2049 case amd_pp_disp_clock:
2050 clk_select = PPCLK_DISPCLK;
2052 case amd_pp_pixel_clock:
2053 clk_select = PPCLK_PIXCLK;
2055 case amd_pp_phy_clock:
2056 clk_select = PPCLK_PHYCLK;
2059 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2065 clk_request = (clk_select << 16) | clk_freq;
2066 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2067 PPSMC_MSG_SetHardMinByFreq,
2075 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2076 PHM_PerformanceLevelDesignation designation, uint32_t index,
2077 PHM_PerformanceLevel *level)
2082 static int vega20_notify_smc_display_config_after_ps_adjustment(
2083 struct pp_hwmgr *hwmgr)
2085 struct vega20_hwmgr *data =
2086 (struct vega20_hwmgr *)(hwmgr->backend);
2087 struct vega20_single_dpm_table *dpm_table =
2088 &data->dpm_table.mem_table;
2089 struct PP_Clocks min_clocks = {0};
2090 struct pp_display_clock_request clock_req;
2093 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2094 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2095 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2097 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2098 clock_req.clock_type = amd_pp_dcef_clock;
2099 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2100 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2101 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2102 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2103 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2104 min_clocks.dcefClockInSR / 100)) == 0,
2105 "Attempt to set divider for DCEFCLK Failed!",
2108 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2112 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2113 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2114 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2115 PPSMC_MSG_SetHardMinByFreq,
2116 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2117 "[SetHardMinFreq] Set hard min uclk failed!",
2124 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2126 struct vega20_hwmgr *data =
2127 (struct vega20_hwmgr *)(hwmgr->backend);
2128 uint32_t soft_level;
2131 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2133 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2134 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2135 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2137 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2139 data->dpm_table.mem_table.dpm_state.soft_min_level =
2140 data->dpm_table.mem_table.dpm_state.soft_max_level =
2141 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2143 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2144 PP_ASSERT_WITH_CODE(!ret,
2145 "Failed to upload boot level to highest!",
2148 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2149 PP_ASSERT_WITH_CODE(!ret,
2150 "Failed to upload dpm max level to highest!",
2156 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2158 struct vega20_hwmgr *data =
2159 (struct vega20_hwmgr *)(hwmgr->backend);
2160 uint32_t soft_level;
2163 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2165 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2166 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2167 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2169 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2171 data->dpm_table.mem_table.dpm_state.soft_min_level =
2172 data->dpm_table.mem_table.dpm_state.soft_max_level =
2173 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2175 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2176 PP_ASSERT_WITH_CODE(!ret,
2177 "Failed to upload boot level to highest!",
2180 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2181 PP_ASSERT_WITH_CODE(!ret,
2182 "Failed to upload dpm max level to highest!",
2189 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2193 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2194 PP_ASSERT_WITH_CODE(!ret,
2195 "Failed to upload DPM Bootup Levels!",
2198 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2199 PP_ASSERT_WITH_CODE(!ret,
2200 "Failed to upload DPM Max Levels!",
2206 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2207 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2209 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2210 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2211 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2212 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2218 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2219 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2220 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2221 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2222 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2223 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2226 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2228 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2230 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2231 *sclk_mask = gfx_dpm_table->count - 1;
2232 *mclk_mask = mem_dpm_table->count - 1;
2233 *soc_mask = soc_dpm_table->count - 1;
2239 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2240 enum pp_clock_type type, uint32_t mask)
2242 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2243 uint32_t soft_min_level, soft_max_level;
2248 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2249 soft_max_level = mask ? (fls(mask) - 1) : 0;
2251 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2252 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2253 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2254 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2256 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2257 PP_ASSERT_WITH_CODE(!ret,
2258 "Failed to upload boot level to lowest!",
2261 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2262 PP_ASSERT_WITH_CODE(!ret,
2263 "Failed to upload dpm max level to highest!",
2268 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2269 soft_max_level = mask ? (fls(mask) - 1) : 0;
2271 data->dpm_table.mem_table.dpm_state.soft_min_level =
2272 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2273 data->dpm_table.mem_table.dpm_state.soft_max_level =
2274 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2276 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2277 PP_ASSERT_WITH_CODE(!ret,
2278 "Failed to upload boot level to lowest!",
2281 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2282 PP_ASSERT_WITH_CODE(!ret,
2283 "Failed to upload dpm max level to highest!",
2289 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2290 soft_max_level = mask ? (fls(mask) - 1) : 0;
2291 if (soft_min_level >= NUM_LINK_LEVELS ||
2292 soft_max_level >= NUM_LINK_LEVELS)
2295 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2296 PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level);
2297 PP_ASSERT_WITH_CODE(!ret,
2298 "Failed to set min link dpm level!",
2310 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2311 enum amd_dpm_forced_level level)
2314 uint32_t sclk_mask, mclk_mask, soc_mask;
2317 case AMD_DPM_FORCED_LEVEL_HIGH:
2318 ret = vega20_force_dpm_highest(hwmgr);
2321 case AMD_DPM_FORCED_LEVEL_LOW:
2322 ret = vega20_force_dpm_lowest(hwmgr);
2325 case AMD_DPM_FORCED_LEVEL_AUTO:
2326 ret = vega20_unforce_dpm_levels(hwmgr);
2329 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2330 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2331 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2332 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2333 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2336 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2337 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2340 case AMD_DPM_FORCED_LEVEL_MANUAL:
2341 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2349 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2351 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2353 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2354 return AMD_FAN_CTRL_MANUAL;
2356 return AMD_FAN_CTRL_AUTO;
2359 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2362 case AMD_FAN_CTRL_NONE:
2363 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2365 case AMD_FAN_CTRL_MANUAL:
2366 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2367 vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2369 case AMD_FAN_CTRL_AUTO:
2370 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2371 vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2378 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2379 struct amd_pp_simple_clock_info *info)
2382 struct phm_ppt_v2_information *table_info =
2383 (struct phm_ppt_v2_information *)hwmgr->pptable;
2384 struct phm_clock_and_voltage_limits *max_limits =
2385 &table_info->max_clock_voltage_on_ac;
2387 info->engine_max_clock = max_limits->sclk;
2388 info->memory_max_clock = max_limits->mclk;
2394 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2395 struct pp_clock_levels_with_latency *clocks)
2397 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2398 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2401 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2402 "[GetSclks]: gfxclk dpm not enabled!\n",
2405 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2406 clocks->num_levels = count;
2408 for (i = 0; i < count; i++) {
2409 clocks->data[i].clocks_in_khz =
2410 dpm_table->dpm_levels[i].value * 1000;
2411 clocks->data[i].latency_in_us = 0;
2417 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2423 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2424 struct pp_clock_levels_with_latency *clocks)
2426 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2427 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2430 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2431 "[GetMclks]: uclk dpm not enabled!\n",
2434 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2435 clocks->num_levels = data->mclk_latency_table.count = count;
2437 for (i = 0; i < count; i++) {
2438 clocks->data[i].clocks_in_khz =
2439 data->mclk_latency_table.entries[i].frequency =
2440 dpm_table->dpm_levels[i].value * 1000;
2441 clocks->data[i].latency_in_us =
2442 data->mclk_latency_table.entries[i].latency =
2443 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2449 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2450 struct pp_clock_levels_with_latency *clocks)
2452 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2453 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2456 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2457 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2460 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2461 clocks->num_levels = count;
2463 for (i = 0; i < count; i++) {
2464 clocks->data[i].clocks_in_khz =
2465 dpm_table->dpm_levels[i].value * 1000;
2466 clocks->data[i].latency_in_us = 0;
2472 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2473 struct pp_clock_levels_with_latency *clocks)
2475 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2476 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2479 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2480 "[GetSocclks]: socclk dpm not enabled!\n",
2483 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2484 clocks->num_levels = count;
2486 for (i = 0; i < count; i++) {
2487 clocks->data[i].clocks_in_khz =
2488 dpm_table->dpm_levels[i].value * 1000;
2489 clocks->data[i].latency_in_us = 0;
2496 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2497 enum amd_pp_clock_type type,
2498 struct pp_clock_levels_with_latency *clocks)
2503 case amd_pp_sys_clock:
2504 ret = vega20_get_sclks(hwmgr, clocks);
2506 case amd_pp_mem_clock:
2507 ret = vega20_get_memclocks(hwmgr, clocks);
2509 case amd_pp_dcef_clock:
2510 ret = vega20_get_dcefclocks(hwmgr, clocks);
2512 case amd_pp_soc_clock:
2513 ret = vega20_get_socclocks(hwmgr, clocks);
2522 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2523 enum amd_pp_clock_type type,
2524 struct pp_clock_levels_with_voltage *clocks)
2526 clocks->num_levels = 0;
2531 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2534 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2535 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2536 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2538 if (!data->registry_data.disable_water_mark &&
2539 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2540 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2541 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2542 data->water_marks_bitmap |= WaterMarksExist;
2543 data->water_marks_bitmap &= ~WaterMarksLoaded;
2549 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2550 enum PP_OD_DPM_TABLE_COMMAND type,
2551 long *input, uint32_t size)
2553 struct vega20_hwmgr *data =
2554 (struct vega20_hwmgr *)(hwmgr->backend);
2555 struct vega20_od8_single_setting *od8_settings =
2556 data->od8_settings.od8_settings_array;
2557 OverDriveTable_t *od_table =
2558 &(data->smc_state_table.overdrive_table);
2559 struct pp_clock_levels_with_latency clocks;
2560 int32_t input_index, input_clk, input_vol, i;
2564 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2568 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2569 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2570 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2571 pr_info("Sclk min/max frequency overdrive not supported\n");
2575 for (i = 0; i < size; i += 2) {
2577 pr_info("invalid number of input parameters %d\n",
2582 input_index = input[i];
2583 input_clk = input[i + 1];
2585 if (input_index != 0 && input_index != 1) {
2586 pr_info("Invalid index %d\n", input_index);
2587 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2591 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2592 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2593 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2595 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2596 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2600 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2601 (input_index == 1 && od_table->GfxclkFmax != input_clk))
2602 data->gfxclk_overdrive = true;
2604 if (input_index == 0)
2605 od_table->GfxclkFmin = input_clk;
2607 od_table->GfxclkFmax = input_clk;
2612 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2613 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2614 pr_info("Mclk max frequency overdrive not supported\n");
2618 ret = vega20_get_memclocks(hwmgr, &clocks);
2619 PP_ASSERT_WITH_CODE(!ret,
2620 "Attempt to get memory clk levels failed!",
2623 for (i = 0; i < size; i += 2) {
2625 pr_info("invalid number of input parameters %d\n",
2630 input_index = input[i];
2631 input_clk = input[i + 1];
2633 if (input_index != 1) {
2634 pr_info("Invalid index %d\n", input_index);
2635 pr_info("Support max Mclk frequency setting only which index by 1\n");
2639 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2640 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2641 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2643 clocks.data[0].clocks_in_khz / 1000,
2644 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2648 if (input_index == 1 && od_table->UclkFmax != input_clk)
2649 data->memclk_overdrive = true;
2651 od_table->UclkFmax = input_clk;
2656 case PP_OD_EDIT_VDDC_CURVE:
2657 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2658 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2659 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2660 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2661 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2662 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2663 pr_info("Voltage curve calibrate not supported\n");
2667 for (i = 0; i < size; i += 3) {
2669 pr_info("invalid number of input parameters %d\n",
2674 input_index = input[i];
2675 input_clk = input[i + 1];
2676 input_vol = input[i + 2];
2678 if (input_index > 2) {
2679 pr_info("Setting for point %d is not supported\n",
2681 pr_info("Three supported points index by 0, 1, 2\n");
2685 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2686 if (input_clk < od8_settings[od8_id].min_value ||
2687 input_clk > od8_settings[od8_id].max_value) {
2688 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2690 od8_settings[od8_id].min_value,
2691 od8_settings[od8_id].max_value);
2695 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2696 if (input_vol < od8_settings[od8_id].min_value ||
2697 input_vol > od8_settings[od8_id].max_value) {
2698 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2700 od8_settings[od8_id].min_value,
2701 od8_settings[od8_id].max_value);
2705 switch (input_index) {
2707 od_table->GfxclkFreq1 = input_clk;
2708 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2711 od_table->GfxclkFreq2 = input_clk;
2712 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2715 od_table->GfxclkFreq3 = input_clk;
2716 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2722 case PP_OD_RESTORE_DEFAULT_TABLE:
2723 data->gfxclk_overdrive = false;
2724 data->memclk_overdrive = false;
2726 ret = smum_smc_table_manager(hwmgr,
2727 (uint8_t *)od_table,
2728 TABLE_OVERDRIVE, true);
2729 PP_ASSERT_WITH_CODE(!ret,
2730 "Failed to export overdrive table!",
2734 case PP_OD_COMMIT_DPM_TABLE:
2735 ret = smum_smc_table_manager(hwmgr,
2736 (uint8_t *)od_table,
2737 TABLE_OVERDRIVE, false);
2738 PP_ASSERT_WITH_CODE(!ret,
2739 "Failed to import overdrive table!",
2742 /* retrieve updated gfxclk table */
2743 if (data->gfxclk_overdrive) {
2744 data->gfxclk_overdrive = false;
2746 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2751 /* retrieve updated memclk table */
2752 if (data->memclk_overdrive) {
2753 data->memclk_overdrive = false;
2755 ret = vega20_setup_memclk_dpm_table(hwmgr);
2768 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
2769 enum pp_clock_type type, char *buf)
2771 struct vega20_hwmgr *data =
2772 (struct vega20_hwmgr *)(hwmgr->backend);
2773 struct vega20_od8_single_setting *od8_settings =
2774 data->od8_settings.od8_settings_array;
2775 OverDriveTable_t *od_table =
2776 &(data->smc_state_table.overdrive_table);
2777 struct phm_ppt_v3_information *pptable_information =
2778 (struct phm_ppt_v3_information *)hwmgr->pptable;
2779 PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
2780 struct amdgpu_device *adev = hwmgr->adev;
2781 struct pp_clock_levels_with_latency clocks;
2782 int i, now, size = 0;
2784 uint32_t gen_speed, lane_width;
2788 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2789 PP_ASSERT_WITH_CODE(!ret,
2790 "Attempt to get current gfx clk Failed!",
2793 ret = vega20_get_sclks(hwmgr, &clocks);
2794 PP_ASSERT_WITH_CODE(!ret,
2795 "Attempt to get gfx clk levels Failed!",
2798 for (i = 0; i < clocks.num_levels; i++)
2799 size += sprintf(buf + size, "%d: %uMhz %s\n",
2800 i, clocks.data[i].clocks_in_khz / 1000,
2801 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
2805 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2806 PP_ASSERT_WITH_CODE(!ret,
2807 "Attempt to get current mclk freq Failed!",
2810 ret = vega20_get_memclocks(hwmgr, &clocks);
2811 PP_ASSERT_WITH_CODE(!ret,
2812 "Attempt to get memory clk levels Failed!",
2815 for (i = 0; i < clocks.num_levels; i++)
2816 size += sprintf(buf + size, "%d: %uMhz %s\n",
2817 i, clocks.data[i].clocks_in_khz / 1000,
2818 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
2822 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2823 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2824 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2825 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2826 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2827 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2828 for (i = 0; i < NUM_LINK_LEVELS; i++)
2829 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
2830 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," :
2831 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," :
2832 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," :
2833 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "",
2834 (pptable->PcieLaneCount[i] == 1) ? "x1" :
2835 (pptable->PcieLaneCount[i] == 2) ? "x2" :
2836 (pptable->PcieLaneCount[i] == 3) ? "x4" :
2837 (pptable->PcieLaneCount[i] == 4) ? "x8" :
2838 (pptable->PcieLaneCount[i] == 5) ? "x12" :
2839 (pptable->PcieLaneCount[i] == 6) ? "x16" : "",
2840 pptable->LclkFreq[i],
2841 (gen_speed == pptable->PcieGenSpeed[i]) &&
2842 (lane_width == pptable->PcieLaneCount[i]) ?
2847 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2848 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2849 size = sprintf(buf, "%s:\n", "OD_SCLK");
2850 size += sprintf(buf + size, "0: %10uMhz\n",
2851 od_table->GfxclkFmin);
2852 size += sprintf(buf + size, "1: %10uMhz\n",
2853 od_table->GfxclkFmax);
2858 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2859 size = sprintf(buf, "%s:\n", "OD_MCLK");
2860 size += sprintf(buf + size, "1: %10uMhz\n",
2861 od_table->UclkFmax);
2867 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2868 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2869 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2870 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2871 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2872 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2873 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
2874 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
2875 od_table->GfxclkFreq1,
2876 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
2877 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
2878 od_table->GfxclkFreq2,
2879 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
2880 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
2881 od_table->GfxclkFreq3,
2882 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
2888 size = sprintf(buf, "%s:\n", "OD_RANGE");
2890 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2891 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2892 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
2893 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2894 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2897 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2898 ret = vega20_get_memclocks(hwmgr, &clocks);
2899 PP_ASSERT_WITH_CODE(!ret,
2900 "Fail to get memory clk levels!",
2903 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2904 clocks.data[0].clocks_in_khz / 1000,
2905 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2908 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2909 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2910 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2911 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2912 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2913 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2914 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
2915 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
2916 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
2917 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
2918 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
2919 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
2920 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
2921 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
2922 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
2923 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
2924 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
2925 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
2926 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
2927 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
2928 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
2929 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
2930 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
2931 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
2941 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2942 struct vega20_single_dpm_table *dpm_table)
2944 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2947 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2948 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2949 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2951 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2952 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2955 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2956 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2957 PPSMC_MSG_SetHardMinByFreq,
2958 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2959 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2966 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2968 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2971 smum_send_msg_to_smc_with_parameter(hwmgr,
2972 PPSMC_MSG_NumOfDisplays, 0);
2974 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
2975 &data->dpm_table.mem_table);
2980 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2982 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2984 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2986 if ((data->water_marks_bitmap & WaterMarksExist) &&
2987 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2988 result = smum_smc_table_manager(hwmgr,
2989 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2990 PP_ASSERT_WITH_CODE(!result,
2991 "Failed to update WMTABLE!",
2993 data->water_marks_bitmap |= WaterMarksLoaded;
2996 if ((data->water_marks_bitmap & WaterMarksExist) &&
2997 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2998 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2999 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3000 PPSMC_MSG_NumOfDisplays,
3001 hwmgr->display_config->num_display);
3007 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3009 struct vega20_hwmgr *data =
3010 (struct vega20_hwmgr *)(hwmgr->backend);
3013 if (data->smu_features[GNLD_DPM_UVD].supported) {
3014 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3016 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3018 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3021 ret = vega20_enable_smc_features(hwmgr,
3023 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3024 PP_ASSERT_WITH_CODE(!ret,
3025 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3027 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3033 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3035 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3037 if (data->vce_power_gated == bgate)
3040 data->vce_power_gated = bgate;
3041 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3044 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3046 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3048 if (data->uvd_power_gated == bgate)
3051 data->uvd_power_gated = bgate;
3052 vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3055 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3057 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3058 struct vega20_single_dpm_table *dpm_table;
3059 bool vblank_too_short = false;
3060 bool disable_mclk_switching;
3061 uint32_t i, latency;
3063 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3064 !hwmgr->display_config->multi_monitor_in_sync) ||
3066 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3069 dpm_table = &(data->dpm_table.gfx_table);
3070 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3071 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3072 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3073 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3075 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3076 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3077 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3078 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3081 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3082 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3083 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3086 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3087 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3088 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3093 dpm_table = &(data->dpm_table.mem_table);
3094 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3095 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3096 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3097 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3099 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3100 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3101 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3102 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3105 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3106 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3107 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3110 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3111 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3112 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3116 /* honour DAL's UCLK Hardmin */
3117 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3118 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3120 /* Hardmin is dependent on displayconfig */
3121 if (disable_mclk_switching) {
3122 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3123 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3124 if (data->mclk_latency_table.entries[i].latency <= latency) {
3125 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3126 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3133 if (hwmgr->display_config->nb_pstate_switch_disable)
3134 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3137 dpm_table = &(data->dpm_table.vclk_table);
3138 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3139 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3140 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3141 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3143 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3144 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3145 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3146 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3149 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3150 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3151 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3156 dpm_table = &(data->dpm_table.dclk_table);
3157 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3158 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3159 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3160 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3162 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3163 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3164 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3165 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3168 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3169 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3170 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3175 dpm_table = &(data->dpm_table.soc_table);
3176 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3177 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3178 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3179 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3181 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3182 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3183 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3184 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3187 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3188 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3189 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3194 dpm_table = &(data->dpm_table.eclk_table);
3195 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3196 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3197 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3198 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3200 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3201 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3202 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3203 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3206 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3207 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3208 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3216 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3218 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3219 bool is_update_required = false;
3221 if (data->display_timing.num_existing_displays !=
3222 hwmgr->display_config->num_display)
3223 is_update_required = true;
3225 if (data->registry_data.gfx_clk_deep_sleep_support &&
3226 (data->display_timing.min_clock_in_sr !=
3227 hwmgr->display_config->min_core_set_clock_in_sr))
3228 is_update_required = true;
3230 return is_update_required;
3233 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3237 ret = vega20_disable_all_smu_features(hwmgr);
3238 PP_ASSERT_WITH_CODE(!ret,
3239 "[DisableDpmTasks] Failed to disable all smu features!",
3245 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3247 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3250 result = vega20_disable_dpm_tasks(hwmgr);
3251 PP_ASSERT_WITH_CODE((0 == result),
3252 "[PowerOffAsic] Failed to disable DPM!",
3254 data->water_marks_bitmap &= ~(WaterMarksLoaded);
3259 static int conv_power_profile_to_pplib_workload(int power_profile)
3261 int pplib_workload = 0;
3263 switch (power_profile) {
3264 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3265 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3267 case PP_SMC_POWER_PROFILE_POWERSAVING:
3268 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3270 case PP_SMC_POWER_PROFILE_VIDEO:
3271 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3273 case PP_SMC_POWER_PROFILE_VR:
3274 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3276 case PP_SMC_POWER_PROFILE_COMPUTE:
3277 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3279 case PP_SMC_POWER_PROFILE_CUSTOM:
3280 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3284 return pplib_workload;
3287 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3289 DpmActivityMonitorCoeffInt_t activity_monitor;
3290 uint32_t i, size = 0;
3291 uint16_t workload_type = 0;
3292 static const char *profile_name[] = {
3299 static const char *title[] = {
3300 "PROFILE_INDEX(NAME)",
3304 "MinActiveFreqType",
3309 "PD_Data_error_coeff",
3310 "PD_Data_error_rate_coeff"};
3316 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3317 title[0], title[1], title[2], title[3], title[4], title[5],
3318 title[6], title[7], title[8], title[9], title[10]);
3320 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3321 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3322 workload_type = conv_power_profile_to_pplib_workload(i);
3323 result = vega20_get_activity_monitor_coeff(hwmgr,
3324 (uint8_t *)(&activity_monitor), workload_type);
3325 PP_ASSERT_WITH_CODE(!result,
3326 "[GetPowerProfile] Failed to get activity monitor!",
3329 size += sprintf(buf + size, "%2d %14s%s:\n",
3330 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3332 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3336 activity_monitor.Gfx_FPS,
3337 activity_monitor.Gfx_UseRlcBusy,
3338 activity_monitor.Gfx_MinActiveFreqType,
3339 activity_monitor.Gfx_MinActiveFreq,
3340 activity_monitor.Gfx_BoosterFreqType,
3341 activity_monitor.Gfx_BoosterFreq,
3342 activity_monitor.Gfx_PD_Data_limit_c,
3343 activity_monitor.Gfx_PD_Data_error_coeff,
3344 activity_monitor.Gfx_PD_Data_error_rate_coeff);
3346 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3350 activity_monitor.Soc_FPS,
3351 activity_monitor.Soc_UseRlcBusy,
3352 activity_monitor.Soc_MinActiveFreqType,
3353 activity_monitor.Soc_MinActiveFreq,
3354 activity_monitor.Soc_BoosterFreqType,
3355 activity_monitor.Soc_BoosterFreq,
3356 activity_monitor.Soc_PD_Data_limit_c,
3357 activity_monitor.Soc_PD_Data_error_coeff,
3358 activity_monitor.Soc_PD_Data_error_rate_coeff);
3360 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3364 activity_monitor.Mem_FPS,
3365 activity_monitor.Mem_UseRlcBusy,
3366 activity_monitor.Mem_MinActiveFreqType,
3367 activity_monitor.Mem_MinActiveFreq,
3368 activity_monitor.Mem_BoosterFreqType,
3369 activity_monitor.Mem_BoosterFreq,
3370 activity_monitor.Mem_PD_Data_limit_c,
3371 activity_monitor.Mem_PD_Data_error_coeff,
3372 activity_monitor.Mem_PD_Data_error_rate_coeff);
3374 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3378 activity_monitor.Fclk_FPS,
3379 activity_monitor.Fclk_UseRlcBusy,
3380 activity_monitor.Fclk_MinActiveFreqType,
3381 activity_monitor.Fclk_MinActiveFreq,
3382 activity_monitor.Fclk_BoosterFreqType,
3383 activity_monitor.Fclk_BoosterFreq,
3384 activity_monitor.Fclk_PD_Data_limit_c,
3385 activity_monitor.Fclk_PD_Data_error_coeff,
3386 activity_monitor.Fclk_PD_Data_error_rate_coeff);
3392 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3394 DpmActivityMonitorCoeffInt_t activity_monitor;
3395 int workload_type, result = 0;
3397 hwmgr->power_profile_mode = input[size];
3399 if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3400 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3404 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3408 result = vega20_get_activity_monitor_coeff(hwmgr,
3409 (uint8_t *)(&activity_monitor),
3410 WORKLOAD_PPLIB_CUSTOM_BIT);
3411 PP_ASSERT_WITH_CODE(!result,
3412 "[SetPowerProfile] Failed to get activity monitor!",
3416 case 0: /* Gfxclk */
3417 activity_monitor.Gfx_FPS = input[1];
3418 activity_monitor.Gfx_UseRlcBusy = input[2];
3419 activity_monitor.Gfx_MinActiveFreqType = input[3];
3420 activity_monitor.Gfx_MinActiveFreq = input[4];
3421 activity_monitor.Gfx_BoosterFreqType = input[5];
3422 activity_monitor.Gfx_BoosterFreq = input[6];
3423 activity_monitor.Gfx_PD_Data_limit_c = input[7];
3424 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3425 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3427 case 1: /* Socclk */
3428 activity_monitor.Soc_FPS = input[1];
3429 activity_monitor.Soc_UseRlcBusy = input[2];
3430 activity_monitor.Soc_MinActiveFreqType = input[3];
3431 activity_monitor.Soc_MinActiveFreq = input[4];
3432 activity_monitor.Soc_BoosterFreqType = input[5];
3433 activity_monitor.Soc_BoosterFreq = input[6];
3434 activity_monitor.Soc_PD_Data_limit_c = input[7];
3435 activity_monitor.Soc_PD_Data_error_coeff = input[8];
3436 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3439 activity_monitor.Mem_FPS = input[1];
3440 activity_monitor.Mem_UseRlcBusy = input[2];
3441 activity_monitor.Mem_MinActiveFreqType = input[3];
3442 activity_monitor.Mem_MinActiveFreq = input[4];
3443 activity_monitor.Mem_BoosterFreqType = input[5];
3444 activity_monitor.Mem_BoosterFreq = input[6];
3445 activity_monitor.Mem_PD_Data_limit_c = input[7];
3446 activity_monitor.Mem_PD_Data_error_coeff = input[8];
3447 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3450 activity_monitor.Fclk_FPS = input[1];
3451 activity_monitor.Fclk_UseRlcBusy = input[2];
3452 activity_monitor.Fclk_MinActiveFreqType = input[3];
3453 activity_monitor.Fclk_MinActiveFreq = input[4];
3454 activity_monitor.Fclk_BoosterFreqType = input[5];
3455 activity_monitor.Fclk_BoosterFreq = input[6];
3456 activity_monitor.Fclk_PD_Data_limit_c = input[7];
3457 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3458 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3462 result = vega20_set_activity_monitor_coeff(hwmgr,
3463 (uint8_t *)(&activity_monitor),
3464 WORKLOAD_PPLIB_CUSTOM_BIT);
3465 PP_ASSERT_WITH_CODE(!result,
3466 "[SetPowerProfile] Failed to set activity monitor!",
3470 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3472 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3473 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3474 1 << workload_type);
3479 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3480 uint32_t virtual_addr_low,
3481 uint32_t virtual_addr_hi,
3482 uint32_t mc_addr_low,
3483 uint32_t mc_addr_hi,
3486 smum_send_msg_to_smc_with_parameter(hwmgr,
3487 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3489 smum_send_msg_to_smc_with_parameter(hwmgr,
3490 PPSMC_MSG_SetSystemVirtualDramAddrLow,
3492 smum_send_msg_to_smc_with_parameter(hwmgr,
3493 PPSMC_MSG_DramLogSetDramAddrHigh,
3496 smum_send_msg_to_smc_with_parameter(hwmgr,
3497 PPSMC_MSG_DramLogSetDramAddrLow,
3500 smum_send_msg_to_smc_with_parameter(hwmgr,
3501 PPSMC_MSG_DramLogSetDramSize,
3506 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3507 struct PP_TemperatureRange *thermal_data)
3509 struct phm_ppt_v3_information *pptable_information =
3510 (struct phm_ppt_v3_information *)hwmgr->pptable;
3512 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3514 thermal_data->max = pptable_information->us_software_shutdown_temp *
3515 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3520 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3521 /* init/fini related */
3522 .backend_init = vega20_hwmgr_backend_init,
3523 .backend_fini = vega20_hwmgr_backend_fini,
3524 .asic_setup = vega20_setup_asic_task,
3525 .power_off_asic = vega20_power_off_asic,
3526 .dynamic_state_management_enable = vega20_enable_dpm_tasks,
3527 .dynamic_state_management_disable = vega20_disable_dpm_tasks,
3528 /* power state related */
3529 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
3530 .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
3531 .display_config_changed = vega20_display_configuration_changed_task,
3532 .check_smc_update_required_for_display_configuration =
3533 vega20_check_smc_update_required_for_display_configuration,
3534 .notify_smc_display_config_after_ps_adjustment =
3535 vega20_notify_smc_display_config_after_ps_adjustment,
3537 .get_sclk = vega20_dpm_get_sclk,
3538 .get_mclk = vega20_dpm_get_mclk,
3539 .get_dal_power_level = vega20_get_dal_power_level,
3540 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
3541 .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
3542 .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
3543 .display_clock_voltage_request = vega20_display_clock_voltage_request,
3544 .get_performance_level = vega20_get_performance_level,
3545 /* UMD pstate, profile related */
3546 .force_dpm_level = vega20_dpm_force_dpm_level,
3547 .get_power_profile_mode = vega20_get_power_profile_mode,
3548 .set_power_profile_mode = vega20_set_power_profile_mode,
3550 .set_power_limit = vega20_set_power_limit,
3551 .get_sclk_od = vega20_get_sclk_od,
3552 .set_sclk_od = vega20_set_sclk_od,
3553 .get_mclk_od = vega20_get_mclk_od,
3554 .set_mclk_od = vega20_set_mclk_od,
3555 .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
3556 /* for sysfs to retrive/set gfxclk/memclk */
3557 .force_clock_level = vega20_force_clock_level,
3558 .print_clock_levels = vega20_print_clock_levels,
3559 .read_sensor = vega20_read_sensor,
3560 /* powergate related */
3561 .powergate_uvd = vega20_power_gate_uvd,
3562 .powergate_vce = vega20_power_gate_vce,
3563 /* thermal related */
3564 .start_thermal_controller = vega20_start_thermal_controller,
3565 .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
3566 .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
3567 .register_irq_handlers = smu9_register_irq_handlers,
3568 .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
3569 /* fan control related */
3570 .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
3571 .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
3572 .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
3573 .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
3574 .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
3575 .get_fan_control_mode = vega20_get_fan_control_mode,
3576 .set_fan_control_mode = vega20_set_fan_control_mode,
3577 /* smu memory related */
3578 .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
3579 .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
3582 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3584 hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3585 hwmgr->pptable_func = &vega20_pptable_funcs;