drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include "linux/delay.h"
  27 #include "pp_acpi.h"
  28 #include "hwmgr.h"
  29 #include <atombios.h>
  30 #include "tonga_hwmgr.h"
  31 #include "pptable.h"
  32 #include "processpptables.h"
  33 #include "tonga_processpptables.h"
  34 #include "tonga_pptable.h"
  35 #include "pp_debug.h"
  36 #include "tonga_ppsmc.h"
  37 #include "cgs_common.h"
  38 #include "pppcielanes.h"
  39 #include "tonga_dyn_defaults.h"
  40 #include "smumgr.h"
  41 #include "tonga_smumgr.h"
  42 #include "tonga_clockpowergating.h"
  43 #include "tonga_thermal.h"
  44
  45 #include "smu/smu_7_1_2_d.h"
  46 #include "smu/smu_7_1_2_sh_mask.h"
  47
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50
  51 #include "bif/bif_5_0_d.h"
  52 #include "bif/bif_5_0_sh_mask.h"
  53
  54 #include "dce/dce_10_0_d.h"
  55 #include "dce/dce_10_0_sh_mask.h"
  56
  57 #include "cgs_linux.h"
  58 #include "eventmgr.h"
  59 #include "amd_pcie_helpers.h"
  60
  61 #define MC_CG_ARB_FREQ_F0           0x0a
  62 #define MC_CG_ARB_FREQ_F1           0x0b
  63 #define MC_CG_ARB_FREQ_F2           0x0c
  64 #define MC_CG_ARB_FREQ_F3           0x0d
  65
  66 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  67 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  68 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  69 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  70
  71 #define PCIE_BUS_CLK                10000
  72 #define TCLK                        (PCIE_BUS_CLK / 10)
  73
  74 #define SMC_RAM_END 0x40000
  75 #define SMC_CG_IND_START            0xc0030000
  76 #define SMC_CG_IND_END              0xc0040000  /* First byte after SMC_CG_IND*/
  77
  78 #define VOLTAGE_SCALE               4
  79 #define VOLTAGE_VID_OFFSET_SCALE1   625
  80 #define VOLTAGE_VID_OFFSET_SCALE2   100
  81
  82 #define VDDC_VDDCI_DELTA            200
  83 #define VDDC_VDDGFX_DELTA           300
  84
  85 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  86 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  87 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  88
  89 typedef uint32_t PECI_RegistryValue;
  90
  91 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
  92 static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
  93         {600, 1050, 3, 0},
  94         {600, 1050, 6, 1} };
  95
  96 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
  97 static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
  98         { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
  99         { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 100
 101 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 102 static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
 103         {0, 1, 3, 2, 4, 5},
 104         {0, 2, 4, 5, 6, 5} };
 105
 106 /* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 107 enum DPM_EVENT_SRC {
 108         DPM_EVENT_SRC_ANALOG = 0,               /* Internal analog trip point */
 109         DPM_EVENT_SRC_EXTERNAL = 1,             /* External (GPIO 17) signal */
 110         DPM_EVENT_SRC_DIGITAL = 2,              /* Internal digital trip point (DIG_THERM_DPM) */
 111         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,   /* Internal analog or external */
 112         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4   /* Internal digital or external */
 113 };
 114 typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
 115
 116 static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
 117
 118 struct tonga_power_state *cast_phw_tonga_power_state(
 119                                   struct pp_hw_power_state *hw_ps)
 120 {
 121         if (hw_ps == NULL)
 122                 return NULL;
 123
 124         PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
 125                                 "Invalid Powerstate Type!",
 126                                  return NULL);
 127
 128         return (struct tonga_power_state *)hw_ps;
 129 }
 130
 131 const struct tonga_power_state *cast_const_phw_tonga_power_state(
 132                                  const struct pp_hw_power_state *hw_ps)
 133 {
 134         if (hw_ps == NULL)
 135                 return NULL;
 136
 137         PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
 138                                 "Invalid Powerstate Type!",
 139                                  return NULL);
 140
 141         return (const struct tonga_power_state *)hw_ps;
 142 }
 143
 144 int tonga_add_voltage(struct pp_hwmgr *hwmgr,
 145         phm_ppt_v1_voltage_lookup_table *look_up_table,
 146         phm_ppt_v1_voltage_lookup_record *record)
 147 {
 148         uint32_t i;
 149         PP_ASSERT_WITH_CODE((NULL != look_up_table),
 150                 "Lookup Table empty.", return -1;);
 151         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
 152                 "Lookup Table empty.", return -1;);
 153         PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
 154                 "Lookup Table is full.", return -1;);
 155
 156         /* This is to avoid entering duplicate calculated records. */
 157         for (i = 0; i < look_up_table->count; i++) {
 158                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
 159                         if (look_up_table->entries[i].us_calculated == 1)
 160                                 return 0;
 161                         else
 162                                 break;
 163                 }
 164         }
 165
 166         look_up_table->entries[i].us_calculated = 1;
 167         look_up_table->entries[i].us_vdd = record->us_vdd;
 168         look_up_table->entries[i].us_cac_low = record->us_cac_low;
 169         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
 170         look_up_table->entries[i].us_cac_high = record->us_cac_high;
 171         /* Only increment the count when we're appending, not replacing duplicate entry. */
 172         if (i == look_up_table->count)
 173                 look_up_table->count++;
 174
 175         return 0;
 176 }
 177
 178 int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
 179 {
 180         PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
 181
 182         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
 183 }
 184
 185 uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
 186                 uint32_t voltage)
 187 {
 188         uint8_t count = (uint8_t) (voltage_table->count);
 189         uint8_t i = 0;
 190
 191         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 192                 "Voltage Table empty.", return 0;);
 193         PP_ASSERT_WITH_CODE((0 != count),
 194                 "Voltage Table empty.", return 0;);
 195
 196         for (i = 0; i < count; i++) {
 197                 /* find first voltage bigger than requested */
 198                 if (voltage_table->entries[i].value >= voltage)
 199                         return i;
 200         }
 201
 202         /* voltage is bigger than max voltage in the table */
 203         return i - 1;
 204 }
 205
 206 /**
 207  * @brief PhwTonga_GetVoltageOrder
 208  *  Returns index of requested voltage record in lookup(table)
 209  * @param hwmgr - pointer to hardware manager
 210  * @param lookupTable - lookup list to search in
 211  * @param voltage - voltage to look for
 212  * @return 0 on success
 213  */
 214 uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
 215                 uint16_t voltage)
 216 {
 217         uint8_t count = (uint8_t) (look_up_table->count);
 218         uint8_t i;
 219
 220         PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
 221         PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
 222
 223         for (i = 0; i < count; i++) {
 224                 /* find first voltage equal or bigger than requested */
 225                 if (look_up_table->entries[i].us_vdd >= voltage)
 226                         return i;
 227         }
 228
 229         /* voltage is bigger than max voltage in the table */
 230         return i-1;
 231 }
 232
 233 bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
 234 {
 235         /*
 236          * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
 237          * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
 238          * whereas voltage control is a fundemental change that will not be disabled
 239          */
 240
 241         return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 242                                         FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
 243 }
 244
 245 /**
 246  * Re-generate the DPM level mask value
 247  * @param    hwmgr      the address of the hardware manager
 248  */
 249 static uint32_t tonga_get_dpm_level_enable_mask_value(
 250                         struct tonga_single_dpm_table * dpm_table)
 251 {
 252         uint32_t i;
 253         uint32_t mask_value = 0;
 254
 255         for (i = dpm_table->count; i > 0; i--) {
 256                 mask_value = mask_value << 1;
 257
 258                 if (dpm_table->dpm_levels[i-1].enabled)
 259                         mask_value |= 0x1;
 260                 else
 261                         mask_value &= 0xFFFFFFFE;
 262         }
 263         return mask_value;
 264 }
 265
 266 /**
 267  * Retrieve DPM default values from registry (if available)
 268  *
 269  * @param    hwmgr  the address of the powerplay hardware manager.
 270  */
 271 void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 272 {
 273         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 274         phw_tonga_ulv_parm *ulv = &(data->ulv);
 275         uint32_t tmp;
 276
 277         ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
 278         data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
 279         data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
 280         data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
 281         data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
 282         data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
 283         data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
 284         data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
 285         data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
 286
 287         data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
 288         data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
 289
 290         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 291                 PHM_PlatformCaps_ABM);
 292         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 293                 PHM_PlatformCaps_NonABMSupportInPPLib);
 294
 295         tmp = 0;
 296         if (tmp == 0)
 297                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 298                         PHM_PlatformCaps_DynamicACTiming);
 299
 300         tmp = 0;
 301         if (0 != tmp)
 302                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 303                         PHM_PlatformCaps_DisableMemoryTransition);
 304
 305         data->mclk_strobe_mode_threshold = 40000;
 306         data->mclk_stutter_mode_threshold = 30000;
 307         data->mclk_edc_enable_threshold = 40000;
 308         data->mclk_edc_wr_enable_threshold = 40000;
 309
 310         tmp = 0;
 311         if (tmp != 0)
 312                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 313                         PHM_PlatformCaps_DisableMCLS);
 314
 315         data->pcie_gen_performance.max = PP_PCIEGen1;
 316         data->pcie_gen_performance.min = PP_PCIEGen3;
 317         data->pcie_gen_power_saving.max = PP_PCIEGen1;
 318         data->pcie_gen_power_saving.min = PP_PCIEGen3;
 319
 320         data->pcie_lane_performance.max = 0;
 321         data->pcie_lane_performance.min = 16;
 322         data->pcie_lane_power_saving.max = 0;
 323         data->pcie_lane_power_saving.min = 16;
 324
 325         tmp = 0;
 326
 327         if (tmp)
 328                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 329                         PHM_PlatformCaps_SclkThrottleLowNotification);
 330
 331         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 332                 PHM_PlatformCaps_DynamicUVDState);
 333
 334 }
 335
 336 int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
 337 {
 338         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 339
 340         int result = 0;
 341         uint32_t low_sclk_interrupt_threshold = 0;
 342
 343         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 344                         PHM_PlatformCaps_SclkThrottleLowNotification)
 345                 && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
 346                 data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
 347                 low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
 348
 349                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
 350
 351                 result = tonga_copy_bytes_to_smc(
 352                                 hwmgr->smumgr,
 353                                 data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
 354                                 LowSclkInterruptThreshold),
 355                                 (uint8_t *)&low_sclk_interrupt_threshold,
 356                                 sizeof(uint32_t),
 357                                 data->sram_end
 358                                 );
 359         }
 360
 361         return result;
 362 }
 363
 364 /**
 365  * Find SCLK value that is associated with specified virtual_voltage_Id.
 366  *
 367  * @param    hwmgr  the address of the powerplay hardware manager.
 368  * @param    virtual_voltage_Id  voltageId to look for.
 369  * @param    sclk output value .
 370  * @return   always 0 if success and 2 if association not found
 371  */
 372 static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 373         phm_ppt_v1_voltage_lookup_table *lookup_table,
 374         uint16_t virtual_voltage_id, uint32_t *sclk)
 375 {
 376         uint8_t entryId;
 377         uint8_t voltageId;
 378         struct phm_ppt_v1_information *pptable_info =
 379                                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 380
 381         PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
 382
 383         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
 384         for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
 385                 voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
 386                 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
 387                         break;
 388         }
 389
 390         PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
 391                         "Can't find requested voltage id in vdd_dep_on_sclk table!",
 392                         return -1;
 393                         );
 394
 395         *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
 396
 397         return 0;
 398 }
 399
 400 /**
 401  * Get Leakage VDDC based on leakage ID.
 402  *
 403  * @param    hwmgr  the address of the powerplay hardware manager.
 404  * @return   2 if vddgfx returned is greater than 2V or if BIOS
 405  */
 406 int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
 407 {
 408         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 409         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
 410         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
 411         uint16_t    virtual_voltage_id;
 412         uint16_t    vddc = 0;
 413         uint16_t    vddgfx = 0;
 414         uint16_t    i, j;
 415         uint32_t  sclk = 0;
 416
 417         /* retrieve voltage for leakage ID (0xff01 + i) */
 418         for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
 419                 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 420
 421                 /* in split mode we should have only vddgfx EVV leakages */
 422                 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
 423                         if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
 424                                                 pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
 425                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 426                                                         PHM_PlatformCaps_ClockStretcher)) {
 427                                         for (j = 1; j < sclk_table->count; j++) {
 428                                                 if (sclk_table->entries[j].clk == sclk &&
 429                                                                 sclk_table->entries[j].cks_enable == 0) {
 430                                                         sclk += 5000;
 431                                                         break;
 432                                                 }
 433                                         }
 434                                 }
 435                                 if (0 == atomctrl_get_voltage_evv_on_sclk
 436                                     (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
 437                                      virtual_voltage_id, &vddgfx)) {
 438                                         /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
 439                                         PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
 440
 441                                         /* the voltage should not be zero nor equal to leakage ID */
 442                                         if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
 443                                                 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
 444                                                 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
 445                                                 data->vddcgfx_leakage.count++;
 446                                         }
 447                                 } else {
 448                                         printk("Error retrieving EVV voltage value!\n");
 449                                 }
 450                         }
 451                 } else {
 452                         /*  in merged mode we have only vddc EVV leakages */
 453                         if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
 454                                                 pptable_info->vddc_lookup_table,
 455                                                 virtual_voltage_id, &sclk)) {
 456                                 if (0 == atomctrl_get_voltage_evv_on_sclk
 457                                     (hwmgr, VOLTAGE_TYPE_VDDC, sclk,
 458                                      virtual_voltage_id, &vddc)) {
 459                                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
 460                                         PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1);
 461
 462                                         /* the voltage should not be zero nor equal to leakage ID */
 463                                         if (vddc != 0 && vddc != virtual_voltage_id) {
 464                                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
 465                                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
 466                                                 data->vddc_leakage.count++;
 467                                         }
 468                                 } else {
 469                                         printk("Error retrieving EVV voltage value!\n");
 470                                 }
 471                         }
 472                 }
 473         }
 474
 475         return 0;
 476 }
 477
 478 int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 479 {
 480         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 481
 482         /* enable SCLK dpm */
 483         if (0 == data->sclk_dpm_key_disabled) {
 484                 PP_ASSERT_WITH_CODE(
 485                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 486                                                    PPSMC_MSG_DPM_Enable)),
 487                                 "Failed to enable SCLK DPM during DPM Start Function!",
 488                                 return -1);
 489         }
 490
 491         /* enable MCLK dpm */
 492         if (0 == data->mclk_dpm_key_disabled) {
 493                 PP_ASSERT_WITH_CODE(
 494                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 495                                              PPSMC_MSG_MCLKDPM_Enable)),
 496                                 "Failed to enable MCLK DPM during DPM Start Function!",
 497                                 return -1);
 498
 499                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
 500
 501                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 502                         ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
 503                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 504                         ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
 505                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 506                         ixLCAC_CPL_CNTL, 0x100005);/*Read */
 507
 508                 udelay(10);
 509
 510                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 511                         ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
 512                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 513                         ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
 514                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 515                         ixLCAC_CPL_CNTL, 0x500005);/* write */
 516
 517         }
 518
 519         return 0;
 520 }
 521
 522 int tonga_start_dpm(struct pp_hwmgr *hwmgr)
 523 {
 524         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 525
 526         /* enable general power management */
 527         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
 528         /* enable sclk deep sleep */
 529         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
 530
 531         /* prepare for PCIE DPM */
 532         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
 533                         offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
 534
 535         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
 536
 537         PP_ASSERT_WITH_CODE(
 538                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 539                                         PPSMC_MSG_Voltage_Cntl_Enable)),
 540                         "Failed to enable voltage DPM during DPM Start Function!",
 541                         return -1);
 542
 543         if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
 544                 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
 545         }
 546
 547         /* enable PCIE dpm */
 548         if (0 == data->pcie_dpm_key_disabled) {
 549                 PP_ASSERT_WITH_CODE(
 550                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 551                                                 PPSMC_MSG_PCIeDPM_Enable)),
 552                                 "Failed to enable pcie DPM during DPM Start Function!",
 553                                 return -1
 554                                 );
 555         }
 556
 557         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 558                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
 559                                    smum_send_msg_to_smc(hwmgr->smumgr,
 560                                     PPSMC_MSG_EnableACDCGPIOInterrupt);
 561         }
 562
 563         return 0;
 564 }
 565
 566 int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 567 {
 568         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 569
 570         /* disable SCLK dpm */
 571         if (0 == data->sclk_dpm_key_disabled) {
 572                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
 573                 PP_ASSERT_WITH_CODE(
 574                                 (0 == tonga_is_dpm_running(hwmgr)),
 575                                 "Trying to Disable SCLK DPM when DPM is disabled",
 576                                 return -1
 577                                 );
 578
 579                 PP_ASSERT_WITH_CODE(
 580                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 581                                                   PPSMC_MSG_DPM_Disable)),
 582                                 "Failed to disable SCLK DPM during DPM stop Function!",
 583                                 return -1);
 584         }
 585
 586         /* disable MCLK dpm */
 587         if (0 == data->mclk_dpm_key_disabled) {
 588                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
 589                 PP_ASSERT_WITH_CODE(
 590                                 (0 == tonga_is_dpm_running(hwmgr)),
 591                                 "Trying to Disable MCLK DPM when DPM is disabled",
 592                                 return -1
 593                                 );
 594
 595                 PP_ASSERT_WITH_CODE(
 596                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 597                                             PPSMC_MSG_MCLKDPM_Disable)),
 598                                 "Failed to Disable MCLK DPM during DPM stop Function!",
 599                                 return -1);
 600         }
 601
 602         return 0;
 603 }
 604
 605 int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
 606 {
 607         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 608
 609         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
 610         /* disable sclk deep sleep*/
 611         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
 612
 613         /* disable PCIE dpm */
 614         if (0 == data->pcie_dpm_key_disabled) {
 615                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
 616                 PP_ASSERT_WITH_CODE(
 617                                 (0 == tonga_is_dpm_running(hwmgr)),
 618                                 "Trying to Disable PCIE DPM when DPM is disabled",
 619                                 return -1
 620                                 );
 621                 PP_ASSERT_WITH_CODE(
 622                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 623                                                 PPSMC_MSG_PCIeDPM_Disable)),
 624                                 "Failed to disable pcie DPM during DPM stop Function!",
 625                                 return -1);
 626         }
 627
 628         if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
 629                 PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
 630
 631         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
 632         PP_ASSERT_WITH_CODE(
 633                         (0 == tonga_is_dpm_running(hwmgr)),
 634                         "Trying to Disable Voltage CNTL when DPM is disabled",
 635                         return -1
 636                         );
 637
 638         PP_ASSERT_WITH_CODE(
 639                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
 640                                         PPSMC_MSG_Voltage_Cntl_Disable)),
 641                         "Failed to disable voltage DPM during DPM stop Function!",
 642                         return -1);
 643
 644         return 0;
 645 }
 646
 647 int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
 648 {
 649         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
 650
 651         return 0;
 652 }
 653
 654 /**
 655  * Send a message to the SMC and return a parameter
 656  *
 657  * @param    hwmgr:  the address of the powerplay hardware manager.
 658  * @param    msg: the message to send.
 659  * @param    parameter: pointer to the received parameter
 660  * @return   The response that came from the SMC.
 661  */
 662 PPSMC_Result tonga_send_msg_to_smc_return_parameter(
 663                 struct pp_hwmgr *hwmgr,
 664                 PPSMC_Msg msg,
 665                 uint32_t *parameter)
 666 {
 667         int result;
 668
 669         result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
 670
 671         if ((0 == result) && parameter) {
 672                 *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
 673         }
 674
 675         return result;
 676 }
 677
 678 /**
 679  * force DPM power State
 680  *
 681  * @param    hwmgr:  the address of the powerplay hardware manager.
 682  * @param    n     :  DPM level
 683  * @return   The response that came from the SMC.
 684  */
 685 int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
 686 {
 687         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 688         uint32_t level_mask = 1 << n;
 689
 690         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
 691         PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
 692                         "Trying to force SCLK when DPM is disabled", return -1;);
 693         if (0 == data->sclk_dpm_key_disabled)
 694                 return (0 == smum_send_msg_to_smc_with_parameter(
 695                                                              hwmgr->smumgr,
 696                      (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
 697                                                     level_mask) ? 0 : 1);
 698
 699         return 0;
 700 }
 701
 702 /**
 703  * force DPM power State
 704  *
 705  * @param    hwmgr:  the address of the powerplay hardware manager.
 706  * @param    n     :  DPM level
 707  * @return   The response that came from the SMC.
 708  */
 709 int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
 710 {
 711         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 712         uint32_t level_mask = 1 << n;
 713
 714         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message. */
 715         PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
 716                         "Trying to Force MCLK when DPM is disabled", return -1;);
 717         if (0 == data->mclk_dpm_key_disabled)
 718                 return (0 == smum_send_msg_to_smc_with_parameter(
 719                                                                 hwmgr->smumgr,
 720                                                                 (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
 721                                                                 level_mask) ? 0 : 1);
 722
 723         return 0;
 724 }
 725
 726 /**
 727  * force DPM power State
 728  *
 729  * @param    hwmgr:  the address of the powerplay hardware manager.
 730  * @param    n     :  DPM level
 731  * @return   The response that came from the SMC.
 732  */
 733 int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
 734 {
 735         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 736
 737         /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
 738         PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
 739                         "Trying to Force PCIE level when DPM is disabled", return -1;);
 740         if (0 == data->pcie_dpm_key_disabled)
 741                 return (0 == smum_send_msg_to_smc_with_parameter(
 742                                                              hwmgr->smumgr,
 743                            (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
 744                                                                 n) ? 0 : 1);
 745
 746         return 0;
 747 }
 748
 749 /**
 750  * Set the initial state by calling SMC to switch to this state directly
 751  *
 752  * @param    hwmgr  the address of the powerplay hardware manager.
 753  * @return   always 0
 754  */
 755 int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
 756 {
 757         /*
 758         * SMC only stores one state that SW will ask to switch too,
 759         * so we switch the the just uploaded one
 760         */
 761         return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
 762 }
 763
 764 /**
 765  * Get the location of various tables inside the FW image.
 766  *
 767  * @param    hwmgr  the address of the powerplay hardware manager.
 768  * @return   always 0
 769  */
 770 int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
 771 {
 772         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 773         struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
 774
 775         uint32_t tmp;
 776         int result;
 777         bool error = 0;
 778
 779         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 780                                 SMU72_FIRMWARE_HEADER_LOCATION +
 781                                 offsetof(SMU72_Firmware_Header, DpmTable),
 782                                 &tmp, data->sram_end);
 783
 784         if (0 == result) {
 785                 data->dpm_table_start = tmp;
 786         }
 787
 788         error |= (0 != result);
 789
 790         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 791                                 SMU72_FIRMWARE_HEADER_LOCATION +
 792                                 offsetof(SMU72_Firmware_Header, SoftRegisters),
 793                                 &tmp, data->sram_end);
 794
 795         if (0 == result) {
 796                 data->soft_regs_start = tmp;
 797                 tonga_smu->ulSoftRegsStart = tmp;
 798         }
 799
 800         error |= (0 != result);
 801
 802
 803         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 804                                 SMU72_FIRMWARE_HEADER_LOCATION +
 805                                 offsetof(SMU72_Firmware_Header, mcRegisterTable),
 806                                 &tmp, data->sram_end);
 807
 808         if (0 == result) {
 809                 data->mc_reg_table_start = tmp;
 810         }
 811
 812         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 813                                 SMU72_FIRMWARE_HEADER_LOCATION +
 814                                 offsetof(SMU72_Firmware_Header, FanTable),
 815                                 &tmp, data->sram_end);
 816
 817         if (0 == result) {
 818                 data->fan_table_start = tmp;
 819         }
 820
 821         error |= (0 != result);
 822
 823         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 824                                 SMU72_FIRMWARE_HEADER_LOCATION +
 825                                 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
 826                                 &tmp, data->sram_end);
 827
 828         if (0 == result) {
 829                 data->arb_table_start = tmp;
 830         }
 831
 832         error |= (0 != result);
 833
 834
 835         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
 836                                 SMU72_FIRMWARE_HEADER_LOCATION +
 837                                 offsetof(SMU72_Firmware_Header, Version),
 838                                 &tmp, data->sram_end);
 839
 840         if (0 == result) {
 841                 hwmgr->microcode_version_info.SMC = tmp;
 842         }
 843
 844         error |= (0 != result);
 845
 846         return error ? 1 : 0;
 847 }
 848
 849 /**
 850  * Read clock related registers.
 851  *
 852  * @param    hwmgr  the address of the powerplay hardware manager.
 853  * @return   always 0
 854  */
 855 int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
 856 {
 857         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 858
 859         data->clock_registers.vCG_SPLL_FUNC_CNTL         =
 860                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
 861         data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
 862                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
 863         data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
 864                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
 865         data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
 866                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
 867         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
 868                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
 869         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
 870                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
 871         data->clock_registers.vDLL_CNTL                  =
 872                 cgs_read_register(hwmgr->device, mmDLL_CNTL);
 873         data->clock_registers.vMCLK_PWRMGT_CNTL          =
 874                 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
 875         data->clock_registers.vMPLL_AD_FUNC_CNTL         =
 876                 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
 877         data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
 878                 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
 879         data->clock_registers.vMPLL_FUNC_CNTL            =
 880                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
 881         data->clock_registers.vMPLL_FUNC_CNTL_1          =
 882                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
 883         data->clock_registers.vMPLL_FUNC_CNTL_2          =
 884                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
 885         data->clock_registers.vMPLL_SS1                  =
 886                 cgs_read_register(hwmgr->device, mmMPLL_SS1);
 887         data->clock_registers.vMPLL_SS2                  =
 888                 cgs_read_register(hwmgr->device, mmMPLL_SS2);
 889
 890         return 0;
 891 }
 892
 893 /**
 894  * Find out if memory is GDDR5.
 895  *
 896  * @param    hwmgr  the address of the powerplay hardware manager.
 897  * @return   always 0
 898  */
 899 int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
 900 {
 901         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 902         uint32_t temp;
 903
 904         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
 905
 906         data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
 907                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
 908                          MC_SEQ_MISC0_GDDR5_SHIFT));
 909
 910         return 0;
 911 }
 912
 913 /**
 914  * Enables Dynamic Power Management by SMC
 915  *
 916  * @param    hwmgr  the address of the powerplay hardware manager.
 917  * @return   always 0
 918  */
 919 int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
 920 {
 921         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
 922
 923         return 0;
 924 }
 925
 926 /**
 927  * Initialize PowerGating States for different engines
 928  *
 929  * @param    hwmgr  the address of the powerplay hardware manager.
 930  * @return   always 0
 931  */
 932 int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
 933 {
 934         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 935
 936         data->uvd_power_gated = 0;
 937         data->vce_power_gated = 0;
 938         data->samu_power_gated = 0;
 939         data->acp_power_gated = 0;
 940         data->pg_acp_init = 1;
 941
 942         return 0;
 943 }
 944
 945 /**
 946  * Checks if DPM is enabled
 947  *
 948  * @param    hwmgr  the address of the powerplay hardware manager.
 949  * @return   always 0
 950  */
 951 int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
 952 {
 953         /*
 954          * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
 955          * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
 956          * whereas voltage control is a fundemental change that will not be disabled
 957          */
 958         return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1);
 959 }
 960
 961 /**
 962  * Checks if DPM is stopped
 963  *
 964  * @param    hwmgr  the address of the powerplay hardware manager.
 965  * @return   always 0
 966  */
 967 int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
 968 {
 969         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
 970
 971         if (0 != tonga_is_dpm_running(hwmgr)) {
 972                 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
 973                 if (!data->dpm_table_start) {
 974                         return 1;
 975                 }
 976         }
 977
 978         return 0;
 979 }
 980
 981 /**
 982  * Remove repeated voltage values and create table with unique values.
 983  *
 984  * @param    hwmgr  the address of the powerplay hardware manager.
 985  * @param    voltage_table  the pointer to changing voltage table
 986  * @return    1 in success
 987  */
 988
 989 static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
 990                         pp_atomctrl_voltage_table *voltage_table)
 991 {
 992         uint32_t table_size, i, j;
 993         uint16_t vvalue;
 994         bool bVoltageFound = 0;
 995         pp_atomctrl_voltage_table *table;
 996
 997         PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
 998         table_size = sizeof(pp_atomctrl_voltage_table);
 999         table = kzalloc(table_size, GFP_KERNEL);
1000
1001         if (NULL == table)
1002                 return -ENOMEM;
1003
1004         memset(table, 0x00, table_size);
1005         table->mask_low = voltage_table->mask_low;
1006         table->phase_delay = voltage_table->phase_delay;
1007
1008         for (i = 0; i < voltage_table->count; i++) {
1009                 vvalue = voltage_table->entries[i].value;
1010                 bVoltageFound = 0;
1011
1012                 for (j = 0; j < table->count; j++) {
1013                         if (vvalue == table->entries[j].value) {
1014                                 bVoltageFound = 1;
1015                                 break;
1016                         }
1017                 }
1018
1019                 if (!bVoltageFound) {
1020                         table->entries[table->count].value = vvalue;
1021                         table->entries[table->count].smio_low =
1022                                 voltage_table->entries[i].smio_low;
1023                         table->count++;
1024                 }
1025         }
1026
1027         memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
1028
1029         kfree(table);
1030
1031         return 0;
1032 }
1033
1034 static int tonga_get_svi2_vdd_ci_voltage_table(
1035                 struct pp_hwmgr *hwmgr,
1036                 phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
1037 {
1038         uint32_t i;
1039         int result;
1040         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1041         pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
1042
1043         PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
1044                         "Voltage Dependency Table empty.", return -1;);
1045
1046         vddci_voltage_table->mask_low = 0;
1047         vddci_voltage_table->phase_delay = 0;
1048         vddci_voltage_table->count = voltage_dependency_table->count;
1049
1050         for (i = 0; i < voltage_dependency_table->count; i++) {
1051                 vddci_voltage_table->entries[i].value =
1052                         voltage_dependency_table->entries[i].vddci;
1053                 vddci_voltage_table->entries[i].smio_low = 0;
1054         }
1055
1056         result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
1057         PP_ASSERT_WITH_CODE((0 == result),
1058                         "Failed to trim VDDCI table.", return result;);
1059
1060         return 0;
1061 }
1062
1063
1064
1065 static int tonga_get_svi2_vdd_voltage_table(
1066                 struct pp_hwmgr *hwmgr,
1067                 phm_ppt_v1_voltage_lookup_table *look_up_table,
1068                 pp_atomctrl_voltage_table *voltage_table)
1069 {
1070         uint8_t i = 0;
1071
1072         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1073                         "Voltage Lookup Table empty.", return -1;);
1074
1075         voltage_table->mask_low = 0;
1076         voltage_table->phase_delay = 0;
1077
1078         voltage_table->count = look_up_table->count;
1079
1080         for (i = 0; i < voltage_table->count; i++) {
1081                 voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
1082                 voltage_table->entries[i].smio_low = 0;
1083         }
1084
1085         return 0;
1086 }
1087
1088 /*
1089  * -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
1090  * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
1091  */
1092
1093 static void tonga_trim_voltage_table_to_fit_state_table(
1094                 struct pp_hwmgr *hwmgr,
1095                 uint32_t max_voltage_steps,
1096                 pp_atomctrl_voltage_table *voltage_table)
1097 {
1098         unsigned int i, diff;
1099
1100         if (voltage_table->count <= max_voltage_steps) {
1101                 return;
1102         }
1103
1104         diff = voltage_table->count - max_voltage_steps;
1105
1106         for (i = 0; i < max_voltage_steps; i++) {
1107                 voltage_table->entries[i] = voltage_table->entries[i + diff];
1108         }
1109
1110         voltage_table->count = max_voltage_steps;
1111
1112         return;
1113 }
1114
1115 /**
1116  * Create Voltage Tables.
1117  *
1118  * @param    hwmgr  the address of the powerplay hardware manager.
1119  * @return   always 0
1120  */
1121 int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1122 {
1123         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1124         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1125         int result;
1126
1127         /* MVDD has only GPIO voltage control */
1128         if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1129                 result = atomctrl_get_voltage_table_v3(hwmgr,
1130                                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
1131                 PP_ASSERT_WITH_CODE((0 == result),
1132                         "Failed to retrieve MVDD table.", return result;);
1133         }
1134
1135         if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1136                 /* GPIO voltage */
1137                 result = atomctrl_get_voltage_table_v3(hwmgr,
1138                                         VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
1139                 PP_ASSERT_WITH_CODE((0 == result),
1140                         "Failed to retrieve VDDCI table.", return result;);
1141         } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1142                 /* SVI2 voltage */
1143                 result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
1144                                         pptable_info->vdd_dep_on_mclk);
1145                 PP_ASSERT_WITH_CODE((0 == result),
1146                         "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
1147         }
1148
1149         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1150                 /* VDDGFX has only SVI2 voltage control */
1151                 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1152                                         pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
1153                 PP_ASSERT_WITH_CODE((0 == result),
1154                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
1155         }
1156
1157         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1158                 /* VDDC has only SVI2 voltage control */
1159                 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1160                                         pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
1161                 PP_ASSERT_WITH_CODE((0 == result),
1162                         "Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
1163         }
1164
1165         PP_ASSERT_WITH_CODE(
1166                         (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
1167                         "Too many voltage values for VDDC. Trimming to fit state table.",
1168                         tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1169                         SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
1170                         );
1171
1172         PP_ASSERT_WITH_CODE(
1173                         (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
1174                         "Too many voltage values for VDDGFX. Trimming to fit state table.",
1175                         tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1176                         SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
1177                         );
1178
1179         PP_ASSERT_WITH_CODE(
1180                         (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
1181                         "Too many voltage values for VDDCI. Trimming to fit state table.",
1182                         tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1183                         SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
1184                         );
1185
1186         PP_ASSERT_WITH_CODE(
1187                         (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
1188                         "Too many voltage values for MVDD. Trimming to fit state table.",
1189                         tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1190                         SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
1191                         );
1192
1193         return 0;
1194 }
1195
1196 /**
1197  * Vddc table preparation for SMC.
1198  *
1199  * @param    hwmgr      the address of the hardware manager
1200  * @param    table     the SMC DPM table structure to be populated
1201  * @return   always 0
1202  */
1203 static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
1204                         SMU72_Discrete_DpmTable *table)
1205 {
1206         unsigned int count;
1207         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1208
1209         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1210                 table->VddcLevelCount = data->vddc_voltage_table.count;
1211                 for (count = 0; count < table->VddcLevelCount; count++) {
1212                         table->VddcTable[count] =
1213                                 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
1214                 }
1215                 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1216         }
1217         return 0;
1218 }
1219
1220 /**
1221  * VddGfx table preparation for SMC.
1222  *
1223  * @param    hwmgr      the address of the hardware manager
1224  * @param    table     the SMC DPM table structure to be populated
1225  * @return   always 0
1226  */
1227 static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
1228                         SMU72_Discrete_DpmTable *table)
1229 {
1230         unsigned int count;
1231         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1232
1233         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1234                 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
1235                 for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
1236                         table->VddGfxTable[count] =
1237                                 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
1238                 }
1239                 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
1240         }
1241         return 0;
1242 }
1243
1244 /**
1245  * Vddci table preparation for SMC.
1246  *
1247  * @param    *hwmgr The address of the hardware manager.
1248  * @param    *table The SMC DPM table structure to be populated.
1249  * @return   0
1250  */
1251 static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
1252                         SMU72_Discrete_DpmTable *table)
1253 {
1254         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1255         uint32_t count;
1256
1257         table->VddciLevelCount = data->vddci_voltage_table.count;
1258         for (count = 0; count < table->VddciLevelCount; count++) {
1259                 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1260                         table->VddciTable[count] =
1261                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1262                 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1263                         table->SmioTable1.Pattern[count].Voltage =
1264                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1265                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
1266                         table->SmioTable1.Pattern[count].Smio =
1267                                 (uint8_t) count;
1268                         table->Smio[count] |=
1269                                 data->vddci_voltage_table.entries[count].smio_low;
1270                         table->VddciTable[count] =
1271                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1272                 }
1273         }
1274
1275         table->SmioMask1 = data->vddci_voltage_table.mask_low;
1276         CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
1277
1278         return 0;
1279 }
1280
1281 /**
1282  * Mvdd table preparation for SMC.
1283  *
1284  * @param    *hwmgr The address of the hardware manager.
1285  * @param    *table The SMC DPM table structure to be populated.
1286  * @return   0
1287  */
1288 static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
1289                         SMU72_Discrete_DpmTable *table)
1290 {
1291         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1292         uint32_t count;
1293
1294         if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1295                 table->MvddLevelCount = data->mvdd_voltage_table.count;
1296                 for (count = 0; count < table->MvddLevelCount; count++) {
1297                         table->SmioTable2.Pattern[count].Voltage =
1298                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
1299                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
1300                         table->SmioTable2.Pattern[count].Smio =
1301                                 (uint8_t) count;
1302                         table->Smio[count] |=
1303                                 data->mvdd_voltage_table.entries[count].smio_low;
1304                 }
1305                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
1306
1307                 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1308         }
1309
1310         return 0;
1311 }
1312
1313 /**
1314  * Convert a voltage value in mv unit to VID number required by SMU firmware
1315  */
1316 static uint8_t convert_to_vid(uint16_t vddc)
1317 {
1318         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
1319 }
1320
1321
1322 /**
1323  * Preparation of vddc and vddgfx CAC tables for SMC.
1324  *
1325  * @param    hwmgr      the address of the hardware manager
1326  * @param    table     the SMC DPM table structure to be populated
1327  * @return   always 0
1328  */
1329 static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
1330                         SMU72_Discrete_DpmTable *table)
1331 {
1332         uint32_t count;
1333         uint8_t index;
1334         int result = 0;
1335         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1336         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1337         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
1338         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
1339
1340         /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
1341         uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
1342         uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
1343
1344         for (count = 0; count < vddcLevelCount; count++) {
1345                 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
1346                 index = tonga_get_voltage_index(vddc_lookup_table,
1347                         data->vddc_voltage_table.entries[count].value);
1348                 table->BapmVddcVidLoSidd[count] =
1349                         convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1350                 table->BapmVddcVidHiSidd[count] =
1351                         convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1352                 table->BapmVddcVidHiSidd2[count] =
1353                         convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1354         }
1355
1356         if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
1357                 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
1358                 for (count = 0; count < vddgfxLevelCount; count++) {
1359                         index = tonga_get_voltage_index(vddgfx_lookup_table,
1360                                 data->vddgfx_voltage_table.entries[count].value);
1361                         table->BapmVddGfxVidLoSidd[count] =
1362                                 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
1363                         table->BapmVddGfxVidHiSidd[count] =
1364                                 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
1365                         table->BapmVddGfxVidHiSidd2[count] =
1366                                 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
1367                 }
1368         } else {
1369                 for (count = 0; count < vddcLevelCount; count++) {
1370                         index = tonga_get_voltage_index(vddc_lookup_table,
1371                                 data->vddc_voltage_table.entries[count].value);
1372                         table->BapmVddGfxVidLoSidd[count] =
1373                                 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1374                         table->BapmVddGfxVidHiSidd[count] =
1375                                 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1376                         table->BapmVddGfxVidHiSidd2[count] =
1377                                 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1378                 }
1379         }
1380
1381         return result;
1382 }
1383
1384
1385 /**
1386  * Preparation of voltage tables for SMC.
1387  *
1388  * @param    hwmgr      the address of the hardware manager
1389  * @param    table     the SMC DPM table structure to be populated
1390  * @return   always 0
1391  */
1392
1393 int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1394         SMU72_Discrete_DpmTable *table)
1395 {
1396         int result;
1397
1398         result = tonga_populate_smc_vddc_table(hwmgr, table);
1399         PP_ASSERT_WITH_CODE(0 == result,
1400                         "can not populate VDDC voltage table to SMC", return -1);
1401
1402         result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
1403         PP_ASSERT_WITH_CODE(0 == result,
1404                         "can not populate VDDCI voltage table to SMC", return -1);
1405
1406         result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
1407         PP_ASSERT_WITH_CODE(0 == result,
1408                         "can not populate VDDGFX voltage table to SMC", return -1);
1409
1410         result = tonga_populate_smc_mvdd_table(hwmgr, table);
1411         PP_ASSERT_WITH_CODE(0 == result,
1412                         "can not populate MVDD voltage table to SMC", return -1);
1413
1414         result = tonga_populate_cac_tables(hwmgr, table);
1415         PP_ASSERT_WITH_CODE(0 == result,
1416                         "can not populate CAC voltage tables to SMC", return -1);
1417
1418         return 0;
1419 }
1420
1421 /**
1422  * Populates the SMC VRConfig field in DPM table.
1423  *
1424  * @param    hwmgr      the address of the hardware manager
1425  * @param    table     the SMC DPM table structure to be populated
1426  * @return   always 0
1427  */
1428 static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1429                         SMU72_Discrete_DpmTable *table)
1430 {
1431         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1432         uint16_t config;
1433
1434         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1435                 /*  Splitted mode */
1436                 config = VR_SVI2_PLANE_1;
1437                 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1438
1439                 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1440                         config = VR_SVI2_PLANE_2;
1441                         table->VRConfig |= config;
1442                 } else {
1443                         printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
1444                 }
1445         } else {
1446                 /* Merged mode  */
1447                 config = VR_MERGED_WITH_VDDC;
1448                 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1449
1450                 /* Set Vddc Voltage Controller  */
1451                 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1452                         config = VR_SVI2_PLANE_1;
1453                         table->VRConfig |= config;
1454                 } else {
1455                         printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
1456                 }
1457         }
1458
1459         /* Set Vddci Voltage Controller  */
1460         if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1461                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1462                 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1463         } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1464                 config = VR_SMIO_PATTERN_1;
1465                 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1466         }
1467
1468         /* Set Mvdd Voltage Controller */
1469         if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1470                 config = VR_SMIO_PATTERN_2;
1471                 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
1478         phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
1479         uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1480 {
1481         uint32_t i = 0;
1482         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1483         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1484
1485         /* clock - voltage dependency table is empty table */
1486         if (allowed_clock_voltage_table->count == 0)
1487                 return -1;
1488
1489         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1490                 /* find first sclk bigger than request */
1491                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1492                         voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1493                                                                 allowed_clock_voltage_table->entries[i].vddgfx);
1494
1495                         voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1496                                                                 allowed_clock_voltage_table->entries[i].vddc);
1497
1498                         if (allowed_clock_voltage_table->entries[i].vddci) {
1499                                 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1500                                                                         allowed_clock_voltage_table->entries[i].vddci);
1501                         } else {
1502                                 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1503                                                                         allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
1504                         }
1505
1506                         if (allowed_clock_voltage_table->entries[i].mvdd) {
1507                                 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
1508                         }
1509
1510                         voltage->Phases = 1;
1511                         return 0;
1512                 }
1513         }
1514
1515         /* sclk is bigger than max sclk in the dependence table */
1516         voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1517                 allowed_clock_voltage_table->entries[i-1].vddgfx);
1518         voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1519                 allowed_clock_voltage_table->entries[i-1].vddc);
1520
1521         if (allowed_clock_voltage_table->entries[i-1].vddci) {
1522                 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1523                         allowed_clock_voltage_table->entries[i-1].vddci);
1524         }
1525         if (allowed_clock_voltage_table->entries[i-1].mvdd) {
1526                 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
1527         }
1528
1529         return 0;
1530 }
1531
1532 /**
1533  * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
1534  *
1535  * @param    hwmgr  the address of the powerplay hardware manager.
1536  * @return   always 0
1537  */
1538 int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
1539 {
1540         return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
1541 }
1542
1543 int tonga_populate_memory_timing_parameters(
1544                 struct pp_hwmgr *hwmgr,
1545                 uint32_t engine_clock,
1546                 uint32_t memory_clock,
1547                 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1548                 )
1549 {
1550         uint32_t dramTiming;
1551         uint32_t dramTiming2;
1552         uint32_t burstTime;
1553         int result;
1554
1555         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1556                                 engine_clock, memory_clock);
1557
1558         PP_ASSERT_WITH_CODE(result == 0,
1559                 "Error calling VBIOS to set DRAM_TIMING.", return result);
1560
1561         dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1562         dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1563         burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1564
1565         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dramTiming);
1566         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1567         arb_regs->McArbBurstTime = (uint8_t)burstTime;
1568
1569         return 0;
1570 }
1571
1572 /**
1573  * Setup parameters for the MC ARB.
1574  *
1575  * @param    hwmgr  the address of the powerplay hardware manager.
1576  * @return   always 0
1577  * This function is to be called from the SetPowerState table.
1578  */
1579 int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1580 {
1581         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1582         int result = 0;
1583         SMU72_Discrete_MCArbDramTimingTable  arb_regs;
1584         uint32_t i, j;
1585
1586         memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1587
1588         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1589                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1590                         result = tonga_populate_memory_timing_parameters
1591                                 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1592                                  data->dpm_table.mclk_table.dpm_levels[j].value,
1593                                  &arb_regs.entries[i][j]);
1594
1595                         if (0 != result) {
1596                                 break;
1597                         }
1598                 }
1599         }
1600
1601         if (0 == result) {
1602                 result = tonga_copy_bytes_to_smc(
1603                                 hwmgr->smumgr,
1604                                 data->arb_table_start,
1605                                 (uint8_t *)&arb_regs,
1606                                 sizeof(SMU72_Discrete_MCArbDramTimingTable),
1607                                 data->sram_end
1608                                 );
1609         }
1610
1611         return result;
1612 }
1613
1614 static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
1615 {
1616         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1617         struct tonga_dpm_table *dpm_table = &data->dpm_table;
1618         uint32_t i;
1619
1620         /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1621         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1622                 table->LinkLevel[i].PcieGenSpeed  =
1623                         (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1624                 table->LinkLevel[i].PcieLaneCount =
1625                         (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1626                 table->LinkLevel[i].EnabledForActivity =
1627                         1;
1628                 table->LinkLevel[i].SPC =
1629                         (uint8_t)(data->pcie_spc_cap & 0xff);
1630                 table->LinkLevel[i].DownThreshold =
1631                         PP_HOST_TO_SMC_UL(5);
1632                 table->LinkLevel[i].UpThreshold =
1633                         PP_HOST_TO_SMC_UL(30);
1634         }
1635
1636         data->smc_state_table.LinkLevelCount =
1637                 (uint8_t)dpm_table->pcie_speed_table.count;
1638         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1639                 tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1640
1641         return 0;
1642 }
1643
1644 static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1645                                         SMU72_Discrete_DpmTable *table)
1646 {
1647         int result = 0;
1648
1649         uint8_t count;
1650         pp_atomctrl_clock_dividers_vi dividers;
1651         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1652         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1653         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1654
1655         table->UvdLevelCount = (uint8_t) (mm_table->count);
1656         table->UvdBootLevel = 0;
1657
1658         for (count = 0; count < table->UvdLevelCount; count++) {
1659                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1660                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1661                 table->UvdLevel[count].MinVoltage.Vddc =
1662                         tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1663                                                 mm_table->entries[count].vddc);
1664                 table->UvdLevel[count].MinVoltage.VddGfx =
1665                         (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1666                         tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1667                                                 mm_table->entries[count].vddgfx) : 0;
1668                 table->UvdLevel[count].MinVoltage.Vddci =
1669                         tonga_get_voltage_id(&data->vddci_voltage_table,
1670                                              mm_table->entries[count].vddc - data->vddc_vddci_delta);
1671                 table->UvdLevel[count].MinVoltage.Phases = 1;
1672
1673                 /* retrieve divider value for VBIOS */
1674                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1675                                                           table->UvdLevel[count].VclkFrequency, &dividers);
1676                 PP_ASSERT_WITH_CODE((0 == result),
1677                                     "can not find divide id for Vclk clock", return result);
1678
1679                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1680
1681                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1682                                                           table->UvdLevel[count].DclkFrequency, &dividers);
1683                 PP_ASSERT_WITH_CODE((0 == result),
1684                                     "can not find divide id for Dclk clock", return result);
1685
1686                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1687
1688                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1689                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1690                 //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage);
1691         }
1692
1693         return result;
1694
1695 }
1696
1697 static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1698                 SMU72_Discrete_DpmTable *table)
1699 {
1700         int result = 0;
1701
1702         uint8_t count;
1703         pp_atomctrl_clock_dividers_vi dividers;
1704         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1705         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1706         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1707
1708         table->VceLevelCount = (uint8_t) (mm_table->count);
1709         table->VceBootLevel = 0;
1710
1711         for (count = 0; count < table->VceLevelCount; count++) {
1712                 table->VceLevel[count].Frequency =
1713                         mm_table->entries[count].eclk;
1714                 table->VceLevel[count].MinVoltage.Vddc =
1715                         tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1716                                 mm_table->entries[count].vddc);
1717                 table->VceLevel[count].MinVoltage.VddGfx =
1718                         (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1719                         tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1720                                 mm_table->entries[count].vddgfx) : 0;
1721                 table->VceLevel[count].MinVoltage.Vddci =
1722                         tonga_get_voltage_id(&data->vddci_voltage_table,
1723                                 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1724                 table->VceLevel[count].MinVoltage.Phases = 1;
1725
1726                 /* retrieve divider value for VBIOS */
1727                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1728                                         table->VceLevel[count].Frequency, &dividers);
1729                 PP_ASSERT_WITH_CODE((0 == result),
1730                                 "can not find divide id for VCE engine clock", return result);
1731
1732                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1733
1734                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1735         }
1736
1737         return result;
1738 }
1739
1740 static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1741                 SMU72_Discrete_DpmTable *table)
1742 {
1743         int result = 0;
1744         uint8_t count;
1745         pp_atomctrl_clock_dividers_vi dividers;
1746         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1747         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1748         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1749
1750         table->AcpLevelCount = (uint8_t) (mm_table->count);
1751         table->AcpBootLevel = 0;
1752
1753         for (count = 0; count < table->AcpLevelCount; count++) {
1754                 table->AcpLevel[count].Frequency =
1755                         pptable_info->mm_dep_table->entries[count].aclk;
1756                 table->AcpLevel[count].MinVoltage.Vddc =
1757                         tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1758                         mm_table->entries[count].vddc);
1759                 table->AcpLevel[count].MinVoltage.VddGfx =
1760                         (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1761                         tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1762                                 mm_table->entries[count].vddgfx) : 0;
1763                 table->AcpLevel[count].MinVoltage.Vddci =
1764                         tonga_get_voltage_id(&data->vddci_voltage_table,
1765                                 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1766                 table->AcpLevel[count].MinVoltage.Phases = 1;
1767
1768                 /* retrieve divider value for VBIOS */
1769                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1770                         table->AcpLevel[count].Frequency, &dividers);
1771                 PP_ASSERT_WITH_CODE((0 == result),
1772                         "can not find divide id for engine clock", return result);
1773
1774                 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1775
1776                 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1777         }
1778
1779         return result;
1780 }
1781
1782 static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1783         SMU72_Discrete_DpmTable *table)
1784 {
1785         int result = 0;
1786         uint8_t count;
1787         pp_atomctrl_clock_dividers_vi dividers;
1788         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1789         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1790         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1791
1792         table->SamuBootLevel = 0;
1793         table->SamuLevelCount = (uint8_t) (mm_table->count);
1794
1795         for (count = 0; count < table->SamuLevelCount; count++) {
1796                 /* not sure whether we need evclk or not */
1797                 table->SamuLevel[count].Frequency =
1798                         pptable_info->mm_dep_table->entries[count].samclock;
1799                 table->SamuLevel[count].MinVoltage.Vddc =
1800                         tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1801                                 mm_table->entries[count].vddc);
1802                 table->SamuLevel[count].MinVoltage.VddGfx =
1803                         (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1804                         tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1805                                 mm_table->entries[count].vddgfx) : 0;
1806                 table->SamuLevel[count].MinVoltage.Vddci =
1807                         tonga_get_voltage_id(&data->vddci_voltage_table,
1808                                 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1809                 table->SamuLevel[count].MinVoltage.Phases = 1;
1810
1811                 /* retrieve divider value for VBIOS */
1812                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1813                                         table->SamuLevel[count].Frequency, &dividers);
1814                 PP_ASSERT_WITH_CODE((0 == result),
1815                         "can not find divide id for samu clock", return result);
1816
1817                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1818
1819                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1820         }
1821
1822         return result;
1823 }
1824
1825 /**
1826  * Populates the SMC MCLK structure using the provided memory clock
1827  *
1828  * @param    hwmgr      the address of the hardware manager
1829  * @param    memory_clock the memory clock to use to populate the structure
1830  * @param    sclk        the SMC SCLK structure to be populated
1831  */
1832 static int tonga_calculate_mclk_params(
1833                 struct pp_hwmgr *hwmgr,
1834                 uint32_t memory_clock,
1835                 SMU72_Discrete_MemoryLevel *mclk,
1836                 bool strobe_mode,
1837                 bool dllStateOn
1838                 )
1839 {
1840         const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1841         uint32_t  dll_cntl = data->clock_registers.vDLL_CNTL;
1842         uint32_t  mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1843         uint32_t  mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1844         uint32_t  mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1845         uint32_t  mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1846         uint32_t  mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1847         uint32_t  mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1848         uint32_t  mpll_ss1 = data->clock_registers.vMPLL_SS1;
1849         uint32_t  mpll_ss2 = data->clock_registers.vMPLL_SS2;
1850
1851         pp_atomctrl_memory_clock_param mpll_param;
1852         int result;
1853
1854         result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1855                                 memory_clock, &mpll_param, strobe_mode);
1856         PP_ASSERT_WITH_CODE(0 == result,
1857                 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1858
1859         /* MPLL_FUNC_CNTL setup*/
1860         mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1861
1862         /* MPLL_FUNC_CNTL_1 setup*/
1863         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1864                                                         MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1865         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1866                                                         MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1867         mpll_func_cntl_1  = PHM_SET_FIELD(mpll_func_cntl_1,
1868                                                         MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1869
1870         /* MPLL_AD_FUNC_CNTL setup*/
1871         mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1872                                                         MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1873
1874         if (data->is_memory_GDDR5) {
1875                 /* MPLL_DQ_FUNC_CNTL setup*/
1876                 mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1877                                                                 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1878                 mpll_dq_func_cntl  = PHM_SET_FIELD(mpll_dq_func_cntl,
1879                                                                 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1880         }
1881
1882         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1883                         PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1884                 /*
1885                  ************************************
1886                  Fref = Reference Frequency
1887                  NF = Feedback divider ratio
1888                  NR = Reference divider ratio
1889                  Fnom = Nominal VCO output frequency = Fref * NF / NR
1890                  Fs = Spreading Rate
1891                  D = Percentage down-spread / 2
1892                  Fint = Reference input frequency to PFD = Fref / NR
1893                  NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1894                  CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1895                  NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1896                  CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1897                  *************************************
1898                  */
1899                 pp_atomctrl_internal_ss_info ss_info;
1900                 uint32_t freq_nom;
1901                 uint32_t tmp;
1902                 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1903
1904                 /* for GDDR5 for all modes and DDR3 */
1905                 if (1 == mpll_param.qdr)
1906                         freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1907                 else
1908                         freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1909
1910                 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2  Note: S.I. reference_divider = 1*/
1911                 tmp = (freq_nom / reference_clock);
1912                 tmp = tmp * tmp;
1913
1914                 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1915                         /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1916                         /* ss.Info.speed_spectrum_rate -- in unit of khz */
1917                         /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1918                         /*     = reference_clock * 5 / speed_spectrum_rate */
1919                         uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1920
1921                         /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1922                         /*     = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1923                         uint32_t clkv =
1924                                 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1925                                                         ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1926
1927                         mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1928                         mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1929                 }
1930         }
1931
1932         /* MCLK_PWRMGT_CNTL setup */
1933         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1934                 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1935         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1936                 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1937         mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1938                 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1939
1940
1941         /* Save the result data to outpupt memory level structure */
1942         mclk->MclkFrequency   = memory_clock;
1943         mclk->MpllFuncCntl    = mpll_func_cntl;
1944         mclk->MpllFuncCntl_1  = mpll_func_cntl_1;
1945         mclk->MpllFuncCntl_2  = mpll_func_cntl_2;
1946         mclk->MpllAdFuncCntl  = mpll_ad_func_cntl;
1947         mclk->MpllDqFuncCntl  = mpll_dq_func_cntl;
1948         mclk->MclkPwrmgtCntl  = mclk_pwrmgt_cntl;
1949         mclk->DllCntl         = dll_cntl;
1950         mclk->MpllSs1         = mpll_ss1;
1951         mclk->MpllSs2         = mpll_ss2;
1952
1953         return 0;
1954 }
1955
1956 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
1957                 bool strobe_mode)
1958 {
1959         uint8_t mc_para_index;
1960
1961         if (strobe_mode) {
1962                 if (memory_clock < 12500) {
1963                         mc_para_index = 0x00;
1964                 } else if (memory_clock > 47500) {
1965                         mc_para_index = 0x0f;
1966                 } else {
1967                         mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1968                 }
1969         } else {
1970                 if (memory_clock < 65000) {
1971                         mc_para_index = 0x00;
1972                 } else if (memory_clock > 135000) {
1973                         mc_para_index = 0x0f;
1974                 } else {
1975                         mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1976                 }
1977         }
1978
1979         return mc_para_index;
1980 }
1981
1982 static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1983 {
1984         uint8_t mc_para_index;
1985
1986         if (memory_clock < 10000) {
1987                 mc_para_index = 0;
1988         } else if (memory_clock >= 80000) {
1989                 mc_para_index = 0x0f;
1990         } else {
1991                 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1992         }
1993
1994         return mc_para_index;
1995 }
1996
1997 static int tonga_populate_single_memory_level(
1998                 struct pp_hwmgr *hwmgr,
1999                 uint32_t memory_clock,
2000                 SMU72_Discrete_MemoryLevel *memory_level
2001                 )
2002 {
2003         uint32_t minMvdd = 0;
2004         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2005         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2006         int result = 0;
2007         bool dllStateOn;
2008         struct cgs_display_info info = {0};
2009
2010
2011         if (NULL != pptable_info->vdd_dep_on_mclk) {
2012                 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2013                         pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
2014                 PP_ASSERT_WITH_CODE((0 == result),
2015                         "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
2016         }
2017
2018         if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
2019                 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
2020         } else {
2021                 memory_level->MinMvdd = minMvdd;
2022         }
2023         memory_level->EnabledForThrottle = 1;
2024         memory_level->EnabledForActivity = 0;
2025         memory_level->UpHyst = 0;
2026         memory_level->DownHyst = 100;
2027         memory_level->VoltageDownHyst = 0;
2028
2029         /* Indicates maximum activity level for this performance level.*/
2030         memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2031         memory_level->StutterEnable = 0;
2032         memory_level->StrobeEnable = 0;
2033         memory_level->EdcReadEnable = 0;
2034         memory_level->EdcWriteEnable = 0;
2035         memory_level->RttEnable = 0;
2036
2037         /* default set to low watermark. Highest level will be set to high later.*/
2038         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2039
2040         cgs_get_active_displays_info(hwmgr->device, &info);
2041         data->display_timing.num_existing_displays = info.display_count;
2042
2043         if ((data->mclk_stutter_mode_threshold != 0) &&
2044             (memory_clock <= data->mclk_stutter_mode_threshold) &&
2045             (data->is_uvd_enabled == 0)
2046             && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
2047             && (data->display_timing.num_existing_displays <= 2)
2048             && (data->display_timing.num_existing_displays != 0))
2049                 memory_level->StutterEnable = 1;
2050
2051         /* decide strobe mode*/
2052         memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
2053                 (memory_clock <= data->mclk_strobe_mode_threshold);
2054
2055         /* decide EDC mode and memory clock ratio*/
2056         if (data->is_memory_GDDR5) {
2057                 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
2058                                         memory_level->StrobeEnable);
2059
2060                 if ((data->mclk_edc_enable_threshold != 0) &&
2061                                 (memory_clock > data->mclk_edc_enable_threshold)) {
2062                         memory_level->EdcReadEnable = 1;
2063                 }
2064
2065                 if ((data->mclk_edc_wr_enable_threshold != 0) &&
2066                                 (memory_clock > data->mclk_edc_wr_enable_threshold)) {
2067                         memory_level->EdcWriteEnable = 1;
2068                 }
2069
2070                 if (memory_level->StrobeEnable) {
2071                         if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
2072                                         ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
2073                                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2074                         } else {
2075                                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
2076                         }
2077
2078                 } else {
2079                         dllStateOn = data->dll_defaule_on;
2080                 }
2081         } else {
2082                 memory_level->StrobeRatio =
2083                         tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
2084                 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2085         }
2086
2087         result = tonga_calculate_mclk_params(hwmgr,
2088                 memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
2089
2090         if (0 == result) {
2091                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
2092                 /* MCLK frequency in units of 10KHz*/
2093                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
2094                 /* Indicates maximum activity level for this performance level.*/
2095                 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
2096                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
2097                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
2098                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
2099                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
2100                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
2101                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
2102                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
2103                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
2104                 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
2105         }
2106
2107         return result;
2108 }
2109
2110 /**
2111  * Populates the SMC MVDD structure using the provided memory clock.
2112  *
2113  * @param    hwmgr      the address of the hardware manager
2114  * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
2115  * @param    voltage     the SMC VOLTAGE structure to be populated
2116  */
2117 int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
2118 {
2119         const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2120         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2121         uint32_t i = 0;
2122
2123         if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2124                 /* find mvdd value which clock is more than request */
2125                 for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
2126                         if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
2127                                 /* Always round to higher voltage. */
2128                                 smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
2129                                 break;
2130                         }
2131                 }
2132
2133                 PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
2134                         "MVDD Voltage is outside the supported range.", return -1);
2135
2136         } else {
2137                 return -1;
2138         }
2139
2140         return 0;
2141 }
2142
2143
2144 static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
2145         SMU72_Discrete_DpmTable *table)
2146 {
2147         int result = 0;
2148         const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2149         pp_atomctrl_clock_dividers_vi dividers;
2150         SMIO_Pattern voltage_level;
2151         uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2152         uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2153         uint32_t dll_cntl          = data->clock_registers.vDLL_CNTL;
2154         uint32_t mclk_pwrmgt_cntl  = data->clock_registers.vMCLK_PWRMGT_CNTL;
2155
2156         /* The ACPI state should not do DPM on DC (or ever).*/
2157         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2158
2159         table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
2160
2161         /* assign zero for now*/
2162         table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
2163
2164         /* get the engine clock dividers for this clock value*/
2165         result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2166                 table->ACPILevel.SclkFrequency,  &dividers);
2167
2168         PP_ASSERT_WITH_CODE(result == 0,
2169                 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2170
2171         /* divider ID for required SCLK*/
2172         table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2173         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2174         table->ACPILevel.DeepSleepDivId = 0;
2175
2176         spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
2177                                                         CG_SPLL_FUNC_CNTL,   SPLL_PWRON,     0);
2178         spll_func_cntl      = PHM_SET_FIELD(spll_func_cntl,
2179                                                         CG_SPLL_FUNC_CNTL,   SPLL_RESET,     1);
2180         spll_func_cntl_2    = PHM_SET_FIELD(spll_func_cntl_2,
2181                                                         CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL,   4);
2182
2183         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2184         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2185         table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2186         table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2187         table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2188         table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2189         table->ACPILevel.CcPwrDynRm = 0;
2190         table->ACPILevel.CcPwrDynRm1 = 0;
2191
2192
2193         /* For various features to be enabled/disabled while this level is active.*/
2194         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2195         /* SCLK frequency in units of 10KHz*/
2196         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2197         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2198         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2199         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2200         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2201         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2202         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2203         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2204         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2205
2206         /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
2207         table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
2208
2209         /*  CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2210
2211         if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
2212                 table->MemoryACPILevel.MinMvdd =
2213                         PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
2214         else
2215                 table->MemoryACPILevel.MinMvdd = 0;
2216
2217         /* Force reset on DLL*/
2218         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2219                 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
2220         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2221                 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
2222
2223         /* Disable DLL in ACPIState*/
2224         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2225                 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
2226         mclk_pwrmgt_cntl    = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2227                 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
2228
2229         /* Enable DLL bypass signal*/
2230         dll_cntl            = PHM_SET_FIELD(dll_cntl,
2231                 DLL_CNTL, MRDCK0_BYPASS, 0);
2232         dll_cntl            = PHM_SET_FIELD(dll_cntl,
2233                 DLL_CNTL, MRDCK1_BYPASS, 0);
2234
2235         table->MemoryACPILevel.DllCntl            =
2236                 PP_HOST_TO_SMC_UL(dll_cntl);
2237         table->MemoryACPILevel.MclkPwrmgtCntl     =
2238                 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
2239         table->MemoryACPILevel.MpllAdFuncCntl     =
2240                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
2241         table->MemoryACPILevel.MpllDqFuncCntl     =
2242                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
2243         table->MemoryACPILevel.MpllFuncCntl       =
2244                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
2245         table->MemoryACPILevel.MpllFuncCntl_1     =
2246                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
2247         table->MemoryACPILevel.MpllFuncCntl_2     =
2248                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
2249         table->MemoryACPILevel.MpllSs1            =
2250                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
2251         table->MemoryACPILevel.MpllSs2            =
2252                 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
2253
2254         table->MemoryACPILevel.EnabledForThrottle = 0;
2255         table->MemoryACPILevel.EnabledForActivity = 0;
2256         table->MemoryACPILevel.UpHyst = 0;
2257         table->MemoryACPILevel.DownHyst = 100;
2258         table->MemoryACPILevel.VoltageDownHyst = 0;
2259         /* Indicates maximum activity level for this performance level.*/
2260         table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2261
2262         table->MemoryACPILevel.StutterEnable = 0;
2263         table->MemoryACPILevel.StrobeEnable = 0;
2264         table->MemoryACPILevel.EdcReadEnable = 0;
2265         table->MemoryACPILevel.EdcWriteEnable = 0;
2266         table->MemoryACPILevel.RttEnable = 0;
2267
2268         return result;
2269 }
2270
2271 static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
2272 {
2273         int result = 0;
2274         uint32_t i;
2275
2276         for (i = 0; i < table->count; i++) {
2277                 if (value == table->dpm_levels[i].value) {
2278                         *boot_level = i;
2279                         result = 0;
2280                 }
2281         }
2282         return result;
2283 }
2284
2285 static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2286                         SMU72_Discrete_DpmTable *table)
2287 {
2288         int result = 0;
2289         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2290
2291         table->GraphicsBootLevel  = 0;        /* 0 == DPM[0] (low), etc. */
2292         table->MemoryBootLevel    = 0;        /* 0 == DPM[0] (low), etc. */
2293
2294         /* find boot level from dpm table*/
2295         result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
2296         data->vbios_boot_state.sclk_bootup_value,
2297         (uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
2298
2299         if (0 != result) {
2300                 data->smc_state_table.GraphicsBootLevel = 0;
2301                 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2302                         in dependency table. Using Graphics DPM level 0!");
2303                 result = 0;
2304         }
2305
2306         result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
2307                 data->vbios_boot_state.mclk_bootup_value,
2308                 (uint32_t *)&(data->smc_state_table.MemoryBootLevel));
2309
2310         if (0 != result) {
2311                 data->smc_state_table.MemoryBootLevel = 0;
2312                 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2313                         in dependency table. Using Memory DPM level 0!");
2314                 result = 0;
2315         }
2316
2317         table->BootVoltage.Vddc =
2318                 tonga_get_voltage_id(&(data->vddc_voltage_table),
2319                         data->vbios_boot_state.vddc_bootup_value);
2320         table->BootVoltage.VddGfx =
2321                 tonga_get_voltage_id(&(data->vddgfx_voltage_table),
2322                         data->vbios_boot_state.vddgfx_bootup_value);
2323         table->BootVoltage.Vddci =
2324                 tonga_get_voltage_id(&(data->vddci_voltage_table),
2325                         data->vbios_boot_state.vddci_bootup_value);
2326         table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
2327
2328         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2329
2330         return result;
2331 }
2332
2333
2334 /**
2335  * Calculates the SCLK dividers using the provided engine clock
2336  *
2337  * @param    hwmgr      the address of the hardware manager
2338  * @param    engine_clock the engine clock to use to populate the structure
2339  * @param    sclk        the SMC SCLK structure to be populated
2340  */
2341 int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
2342                 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
2343 {
2344         const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2345         pp_atomctrl_clock_dividers_vi dividers;
2346         uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2347         uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2348         uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2349         uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2350         uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2351         uint32_t    reference_clock;
2352         uint32_t reference_divider;
2353         uint32_t fbdiv;
2354         int result;
2355
2356         /* get the engine clock dividers for this clock value*/
2357         result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
2358
2359         PP_ASSERT_WITH_CODE(result == 0,
2360                 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2361
2362         /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2363         reference_clock = atomctrl_get_reference_clock(hwmgr);
2364
2365         reference_divider = 1 + dividers.uc_pll_ref_div;
2366
2367         /* low 14 bits is fraction and high 12 bits is divider*/
2368         fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
2369
2370         /* SPLL_FUNC_CNTL setup*/
2371         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2372                 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
2373         spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2374                 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A,  dividers.uc_pll_post_div);
2375
2376         /* SPLL_FUNC_CNTL_3 setup*/
2377         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2378                 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
2379
2380         /* set to use fractional accumulation*/
2381         spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2382                 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
2383
2384         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2385                         PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
2386                 pp_atomctrl_internal_ss_info ss_info;
2387
2388                 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
2389                 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
2390                         /*
2391                         * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2392                         * ss_info.speed_spectrum_rate -- in unit of khz
2393                         */
2394                         /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2395                         uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
2396
2397                         /* clkv = 2 * D * fbdiv / NS */
2398                         uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
2399
2400                         cg_spll_spread_spectrum =
2401                                 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
2402                         cg_spll_spread_spectrum =
2403                                 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
2404                         cg_spll_spread_spectrum_2 =
2405                                 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
2406                 }
2407         }
2408
2409         sclk->SclkFrequency        = engine_clock;
2410         sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
2411         sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
2412         sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
2413         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2414         sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
2415
2416         return 0;
2417 }
2418
2419 static uint8_t tonga_get_sleep_divider_id_from_clock(uint32_t engine_clock,
2420                 uint32_t min_engine_clock_in_sr)
2421 {
2422         uint32_t i, temp;
2423         uint32_t min = max(min_engine_clock_in_sr, (uint32_t)TONGA_MINIMUM_ENGINE_CLOCK);
2424
2425         PP_ASSERT_WITH_CODE((engine_clock >= min),
2426                         "Engine clock can't satisfy stutter requirement!", return 0);
2427
2428         for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
2429                 temp = engine_clock >> i;
2430
2431                 if(temp >= min || i == 0)
2432                         break;
2433         }
2434         return (uint8_t)i;
2435 }
2436
2437 /**
2438  * Populates single SMC SCLK structure using the provided engine clock
2439  *
2440  * @param    hwmgr      the address of the hardware manager
2441  * @param    engine_clock the engine clock to use to populate the structure
2442  * @param    sclk        the SMC SCLK structure to be populated
2443  */
2444 static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
2445 {
2446         int result;
2447         uint32_t threshold;
2448         uint32_t mvdd;
2449         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2450         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2451
2452         result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
2453
2454
2455         /* populate graphics levels*/
2456         result = tonga_get_dependecy_volt_by_clk(hwmgr,
2457                 pptable_info->vdd_dep_on_sclk, engine_clock,
2458                 &graphic_level->MinVoltage, &mvdd);
2459         PP_ASSERT_WITH_CODE((0 == result),
2460                 "can not find VDDC voltage value for VDDC       \
2461                 engine clock dependency table", return result);
2462
2463         /* SCLK frequency in units of 10KHz*/
2464         graphic_level->SclkFrequency = engine_clock;
2465
2466         /* Indicates maximum activity level for this performance level. 50% for now*/
2467         graphic_level->ActivityLevel = sclk_activity_level_threshold;
2468
2469         graphic_level->CcPwrDynRm = 0;
2470         graphic_level->CcPwrDynRm1 = 0;
2471         /* this level can be used if activity is high enough.*/
2472         graphic_level->EnabledForActivity = 0;
2473         /* this level can be used for throttling.*/
2474         graphic_level->EnabledForThrottle = 1;
2475         graphic_level->UpHyst = 0;
2476         graphic_level->DownHyst = 0;
2477         graphic_level->VoltageDownHyst = 0;
2478         graphic_level->PowerThrottle = 0;
2479
2480         threshold = engine_clock * data->fast_watemark_threshold / 100;
2481 /*
2482         *get the DAL clock. do it in funture.
2483         PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
2484         data->display_timing.min_clock_insr = minClocks.engineClockInSR;
2485 */
2486         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2487                         PHM_PlatformCaps_SclkDeepSleep))
2488                 graphic_level->DeepSleepDivId =
2489                                 tonga_get_sleep_divider_id_from_clock(engine_clock,
2490                                                 data->display_timing.min_clock_insr);
2491
2492         /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2493         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2494
2495         if (0 == result) {
2496                 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2497                 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
2498                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
2499                 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
2500                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
2501                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
2502                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
2503                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
2504                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
2505                 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
2506         }
2507
2508         return result;
2509 }
2510
2511 /**
2512  * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2513  *
2514  * @param    hwmgr      the address of the hardware manager
2515  */
2516 static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2517 {
2518         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2519         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2520         struct tonga_dpm_table *dpm_table = &data->dpm_table;
2521         phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2522         uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2523         int result = 0;
2524         uint32_t level_array_adress = data->dpm_table_start +
2525                 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
2526         uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
2527                 SMU72_MAX_LEVELS_GRAPHICS;   /* 64 -> long; 32 -> int*/
2528         SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
2529         uint32_t i, maxEntry;
2530         uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
2531         PECI_RegistryValue reg_value;
2532         memset(levels, 0x00, level_array_size);
2533
2534         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2535                 result = tonga_populate_single_graphic_level(hwmgr,
2536                                         dpm_table->sclk_table.dpm_levels[i].value,
2537                                         (uint16_t)data->activity_target[i],
2538                                         &(data->smc_state_table.GraphicsLevel[i]));
2539
2540                 if (0 != result)
2541                         return result;
2542
2543                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2544                 if (i > 1)
2545                         data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2546
2547                 if (0 == i) {
2548                         reg_value = 0;
2549                         if (reg_value != 0)
2550                                 data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
2551                 }
2552
2553                 if (1 == i) {
2554                         reg_value = 0;
2555                         if (reg_value != 0)
2556                                 data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
2557                 }
2558         }
2559
2560         /* Only enable level 0 for now. */
2561         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2562
2563         /* set highest level watermark to high */
2564         if (dpm_table->sclk_table.count > 1)
2565                 data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
2566                         PPSMC_DISPLAY_WATERMARK_HIGH;
2567
2568         data->smc_state_table.GraphicsDpmLevelCount =
2569                 (uint8_t)dpm_table->sclk_table.count;
2570         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2571                 tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2572
2573         if (pcie_table != NULL) {
2574                 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
2575                         "There must be 1 or more PCIE levels defined in PPTable.", return -1);
2576                 maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
2577                 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2578                         data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
2579                                 (uint8_t) ((i < maxEntry) ? i : maxEntry);
2580                 }
2581         } else {
2582                 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
2583                         printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
2584
2585                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2586                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2587                                         (1<<(highest_pcie_level_enabled+1))) != 0)) {
2588                         highest_pcie_level_enabled++;
2589                 }
2590
2591                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2592                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2593                                         (1<<lowest_pcie_level_enabled)) == 0)) {
2594                         lowest_pcie_level_enabled++;
2595                 }
2596
2597                 while ((count < highest_pcie_level_enabled) &&
2598                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2599                                         (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
2600                         count++;
2601                 }
2602                 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
2603                         (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
2604
2605
2606                 /* set pcieDpmLevel to highest_pcie_level_enabled*/
2607                 for (i = 2; i < dpm_table->sclk_table.count; i++) {
2608                         data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
2609                 }
2610
2611                 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2612                 data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
2613
2614                 /* set pcieDpmLevel to mid_pcie_level_enabled*/
2615                 data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
2616         }
2617         /* level count will send to smc once at init smc table and never change*/
2618         result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2619
2620         if (0 != result)
2621                 return result;
2622
2623         return 0;
2624 }
2625
2626 /**
2627  * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2628  *
2629  * @param    hwmgr      the address of the hardware manager
2630  */
2631
2632 static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2633 {
2634         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2635         struct tonga_dpm_table *dpm_table = &data->dpm_table;
2636         int result;
2637         /* populate MCLK dpm table to SMU7 */
2638         uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
2639         uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
2640         SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
2641         uint32_t i;
2642
2643         memset(levels, 0x00, level_array_size);
2644
2645         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2646                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2647                         "can not populate memory level as memory clock is zero", return -1);
2648                 result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
2649                         &(data->smc_state_table.MemoryLevel[i]));
2650                 if (0 != result) {
2651                         return result;
2652                 }
2653         }
2654
2655         /* Only enable level 0 for now.*/
2656         data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2657
2658         /*
2659         * in order to prevent MC activity from stutter mode to push DPM up.
2660         * the UVD change complements this by putting the MCLK in a higher state
2661         * by default such that we are not effected by up threshold or and MCLK DPM latency.
2662         */
2663         data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
2664         CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
2665
2666         data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
2667         data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2668         /* set highest level watermark to high*/
2669         data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
2670
2671         /* level count will send to smc once at init smc table and never change*/
2672         result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
2673                 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2674
2675         if (0 != result) {
2676                 return result;
2677         }
2678
2679         return 0;
2680 }
2681
2682 struct TONGA_DLL_SPEED_SETTING {
2683         uint16_t            Min;                          /* Minimum Data Rate*/
2684         uint16_t            Max;                          /* Maximum Data Rate*/
2685         uint32_t                        dll_speed;                     /* The desired DLL_SPEED setting*/
2686 };
2687
2688 static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2689 {
2690         return 0;
2691 }
2692
2693 /* ---------------------------------------- ULV related functions ----------------------------------------------------*/
2694
2695
2696 static int tonga_reset_single_dpm_table(
2697         struct pp_hwmgr *hwmgr,
2698         struct tonga_single_dpm_table *dpm_table,
2699         uint32_t count)
2700 {
2701         uint32_t i;
2702         if (!(count <= MAX_REGULAR_DPM_NUMBER))
2703                 printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
2704                         table entries to exceed max number! \n");
2705
2706         dpm_table->count = count;
2707         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
2708                 dpm_table->dpm_levels[i].enabled = 0;
2709         }
2710
2711         return 0;
2712 }
2713
2714 static void tonga_setup_pcie_table_entry(
2715         struct tonga_single_dpm_table *dpm_table,
2716         uint32_t index, uint32_t pcie_gen,
2717         uint32_t pcie_lanes)
2718 {
2719         dpm_table->dpm_levels[index].value = pcie_gen;
2720         dpm_table->dpm_levels[index].param1 = pcie_lanes;
2721         dpm_table->dpm_levels[index].enabled = 1;
2722 }
2723
2724 static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
2725 {
2726         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2727         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2728         phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2729         uint32_t i, maxEntry;
2730
2731         if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
2732                 data->pcie_gen_power_saving = data->pcie_gen_performance;
2733                 data->pcie_lane_power_saving = data->pcie_lane_performance;
2734         } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
2735                 data->pcie_gen_performance = data->pcie_gen_power_saving;
2736                 data->pcie_lane_performance = data->pcie_lane_power_saving;
2737         }
2738
2739         tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK);
2740
2741         if (pcie_table != NULL) {
2742                 /*
2743                 * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue).
2744                 * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry.
2745                 */
2746                 maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ?
2747                                                 SMU72_MAX_LEVELS_LINK : pcie_table->count;
2748                 for (i = 1; i < maxEntry; i++) {
2749                         tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1,
2750                                 get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed),
2751                                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2752                 }
2753                 data->dpm_table.pcie_speed_table.count = maxEntry - 1;
2754         } else {
2755                 /* Hardcode Pcie Table */
2756                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
2757                         get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2758                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2759                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
2760                         get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2761                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2762                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
2763                         get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2764                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2765                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
2766                         get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2767                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2768                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
2769                         get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2770                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2771                 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
2772                         get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2773                         get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2774                 data->dpm_table.pcie_speed_table.count = 6;
2775         }
2776         /* Populate last level for boot PCIE level, but do not increment count. */
2777         tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
2778                 data->dpm_table.pcie_speed_table.count,
2779                 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2780                 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2781
2782         return 0;
2783
2784 }
2785
2786 /*
2787  * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
2788  * Dynamic state patching function will then trim these state tables to the allowed range based
2789  * on the power policy or external client requests, such as UVD request, etc.
2790  */
2791 static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
2792 {
2793         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2794         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2795         uint32_t i;
2796
2797         phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table =
2798                 pptable_info->vdd_dep_on_sclk;
2799         phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table =
2800                 pptable_info->vdd_dep_on_mclk;
2801
2802         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2803                 "SCLK dependency table is missing. This table is mandatory", return -1);
2804         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
2805                 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
2806
2807         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2808                 "MCLK dependency table is missing. This table is mandatory", return -1);
2809         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
2810                 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
2811
2812         /* clear the state table to reset everything to default */
2813         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
2814         tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS);
2815         tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY);
2816         /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */
2817         /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/
2818         /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/
2819         /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/
2820
2821         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2822                 "SCLK dependency table is missing. This table is mandatory", return -1);
2823         /* Initialize Sclk DPM table based on allow Sclk values*/
2824         data->dpm_table.sclk_table.count = 0;
2825
2826         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2827                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
2828                                 allowed_vdd_sclk_table->entries[i].clk) {
2829                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
2830                                 allowed_vdd_sclk_table->entries[i].clk;
2831                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
2832                         data->dpm_table.sclk_table.count++;
2833                 }
2834         }
2835
2836         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2837                 "MCLK dependency table is missing. This table is mandatory", return -1);
2838         /* Initialize Mclk DPM table based on allow Mclk values */
2839         data->dpm_table.mclk_table.count = 0;
2840         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2841                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
2842                         allowed_vdd_mclk_table->entries[i].clk) {
2843                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
2844                                 allowed_vdd_mclk_table->entries[i].clk;
2845                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
2846                         data->dpm_table.mclk_table.count++;
2847                 }
2848         }
2849
2850         /* setup PCIE gen speed levels*/
2851         tonga_setup_default_pcie_tables(hwmgr);
2852
2853         /* save a copy of the default DPM table*/
2854         memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table));
2855
2856         return 0;
2857 }
2858
2859 int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
2860                 const struct tonga_power_state *bootState)
2861 {
2862         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2863         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2864         uint8_t count, level;
2865
2866         count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count);
2867         for (level = 0; level < count; level++) {
2868                 if (pptable_info->vdd_dep_on_sclk->entries[level].clk >=
2869                         bootState->performance_levels[0].engine_clock) {
2870                         data->smc_state_table.GraphicsBootLevel = level;
2871                         break;
2872                 }
2873         }
2874
2875         count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count);
2876         for (level = 0; level < count; level++) {
2877                 if (pptable_info->vdd_dep_on_mclk->entries[level].clk >=
2878                         bootState->performance_levels[0].memory_clock) {
2879                         data->smc_state_table.MemoryBootLevel = level;
2880                         break;
2881                 }
2882         }
2883
2884         return 0;
2885 }
2886
2887 /**
2888  * Initializes the SMC table and uploads it
2889  *
2890  * @param    hwmgr  the address of the powerplay hardware manager.
2891  * @param    pInput  the pointer to input data (PowerState)
2892  * @return   always 0
2893  */
2894 int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2895 {
2896         int result;
2897         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2898         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2899         SMU72_Discrete_DpmTable  *table = &(data->smc_state_table);
2900         const phw_tonga_ulv_parm *ulv = &(data->ulv);
2901         uint8_t i;
2902         PECI_RegistryValue reg_value;
2903         pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2904
2905         result = tonga_setup_default_dpm_tables(hwmgr);
2906         PP_ASSERT_WITH_CODE(0 == result,
2907                 "Failed to setup default DPM tables!", return result;);
2908         memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
2909         if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) {
2910                 tonga_populate_smc_voltage_tables(hwmgr, table);
2911         }
2912
2913         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2914                         PHM_PlatformCaps_AutomaticDCTransition)) {
2915                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2916         }
2917
2918         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2919                         PHM_PlatformCaps_StepVddc)) {
2920                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2921         }
2922
2923         if (data->is_memory_GDDR5) {
2924                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2925         }
2926
2927         i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2928
2929         if (i == 1 || i == 0) {
2930                 table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL;
2931         }
2932
2933         if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) {
2934                 PP_ASSERT_WITH_CODE(0 == result,
2935                         "Failed to initialize ULV state!", return result;);
2936
2937                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2938                         ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
2939         }
2940
2941         result = tonga_populate_smc_link_level(hwmgr, table);
2942         PP_ASSERT_WITH_CODE(0 == result,
2943                 "Failed to initialize Link Level!", return result;);
2944
2945         result = tonga_populate_all_graphic_levels(hwmgr);
2946         PP_ASSERT_WITH_CODE(0 == result,
2947                 "Failed to initialize Graphics Level!", return result;);
2948
2949         result = tonga_populate_all_memory_levels(hwmgr);
2950         PP_ASSERT_WITH_CODE(0 == result,
2951                 "Failed to initialize Memory Level!", return result;);
2952
2953         result = tonga_populate_smv_acpi_level(hwmgr, table);
2954         PP_ASSERT_WITH_CODE(0 == result,
2955                 "Failed to initialize ACPI Level!", return result;);
2956
2957         result = tonga_populate_smc_vce_level(hwmgr, table);
2958         PP_ASSERT_WITH_CODE(0 == result,
2959                 "Failed to initialize VCE Level!", return result;);
2960
2961         result = tonga_populate_smc_acp_level(hwmgr, table);
2962         PP_ASSERT_WITH_CODE(0 == result,
2963                 "Failed to initialize ACP Level!", return result;);
2964
2965         result = tonga_populate_smc_samu_level(hwmgr, table);
2966         PP_ASSERT_WITH_CODE(0 == result,
2967                 "Failed to initialize SAMU Level!", return result;);
2968
2969         /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
2970         /* need to populate the  ARB settings for the initial state. */
2971         result = tonga_program_memory_timing_parameters(hwmgr);
2972         PP_ASSERT_WITH_CODE(0 == result,
2973                 "Failed to Write ARB settings for the initial state.", return result;);
2974
2975         result = tonga_populate_smc_uvd_level(hwmgr, table);
2976         PP_ASSERT_WITH_CODE(0 == result,
2977                 "Failed to initialize UVD Level!", return result;);
2978
2979         result = tonga_populate_smc_boot_level(hwmgr, table);
2980         PP_ASSERT_WITH_CODE(0 == result,
2981                 "Failed to initialize Boot Level!", return result;);
2982
2983         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2984                         PHM_PlatformCaps_ClockStretcher)) {
2985                 result = tonga_populate_clock_stretcher_data_table(hwmgr);
2986                 PP_ASSERT_WITH_CODE(0 == result,
2987                         "Failed to populate Clock Stretcher Data Table!", return result;);
2988         }
2989         table->GraphicsVoltageChangeEnable  = 1;
2990         table->GraphicsThermThrottleEnable  = 1;
2991         table->GraphicsInterval = 1;
2992         table->VoltageInterval  = 1;
2993         table->ThermalInterval  = 1;
2994         table->TemperatureLimitHigh =
2995                 pptable_info->cac_dtp_table->usTargetOperatingTemp *
2996                 TONGA_Q88_FORMAT_CONVERSION_UNIT;
2997         table->TemperatureLimitLow =
2998                 (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2999                 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3000         table->MemoryVoltageChangeEnable  = 1;
3001         table->MemoryInterval  = 1;
3002         table->VoltageResponseTime  = 0;
3003         table->PhaseResponseTime  = 0;
3004         table->MemoryThermThrottleEnable  = 1;
3005
3006         /*
3007         * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had)
3008         * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
3009         * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay
3010         * To avoid it, we set PCIeBootLinkLevel to highest dpm level
3011         */
3012         PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
3013                         "There must be 1 or more PCIE levels defined in PPTable.",
3014                         return -1);
3015
3016         table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
3017
3018         table->PCIeGenInterval  = 1;
3019
3020         result = tonga_populate_vr_config(hwmgr, table);
3021         PP_ASSERT_WITH_CODE(0 == result,
3022                 "Failed to populate VRConfig setting!", return result);
3023
3024         table->ThermGpio  = 17;
3025         table->SclkStepSize = 0x4000;
3026
3027         reg_value = 0;
3028         if ((0 == reg_value) &&
3029                 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3030                         VDDC_VRHOT_GPIO_PINID, &gpio_pin_assignment))) {
3031                 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3032                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3033                         PHM_PlatformCaps_RegulatorHot);
3034         } else {
3035                 table->VRHotGpio = TONGA_UNUSED_GPIO_PIN;
3036                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3037                         PHM_PlatformCaps_RegulatorHot);
3038         }
3039
3040         /* ACDC Switch GPIO */
3041         reg_value = 0;
3042         if ((0 == reg_value) &&
3043                 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3044                         PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin_assignment))) {
3045                 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3046                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3047                         PHM_PlatformCaps_AutomaticDCTransition);
3048         } else {
3049                 table->AcDcGpio = TONGA_UNUSED_GPIO_PIN;
3050                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3051                         PHM_PlatformCaps_AutomaticDCTransition);
3052         }
3053
3054         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3055                 PHM_PlatformCaps_Falcon_QuickTransition);
3056
3057         reg_value = 0;
3058         if (1 == reg_value) {
3059                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3060                         PHM_PlatformCaps_AutomaticDCTransition);
3061                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3062                         PHM_PlatformCaps_Falcon_QuickTransition);
3063         }
3064
3065         reg_value = 0;
3066         if ((0 == reg_value) &&
3067                 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3068                         THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) {
3069                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3070                         PHM_PlatformCaps_ThermalOutGPIO);
3071
3072                 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3073
3074                 table->ThermOutPolarity =
3075                         (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3076                         (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0;
3077
3078                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3079
3080                 /* if required, combine VRHot/PCC with thermal out GPIO*/
3081                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3082                         PHM_PlatformCaps_RegulatorHot) &&
3083                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3084                         PHM_PlatformCaps_CombinePCCWithThermalSignal)){
3085                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3086                 }
3087         } else {
3088                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3089                         PHM_PlatformCaps_ThermalOutGPIO);
3090
3091                 table->ThermOutGpio = 17;
3092                 table->ThermOutPolarity = 1;
3093                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3094         }
3095
3096         for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) {
3097                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3098         }
3099         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3100         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3101         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3102         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3103         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3104         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3105         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3106         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3107         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3108
3109         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3110         result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
3111                                                                                 offsetof(SMU72_Discrete_DpmTable, SystemFlags),
3112                                                                                 (uint8_t *)&(table->SystemFlags),
3113                                                                                 sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController),
3114                                                                                 data->sram_end);
3115
3116         PP_ASSERT_WITH_CODE(0 == result,
3117                 "Failed to upload dpm data to SMC memory!", return result;);
3118
3119         return result;
3120 }
3121
3122 /* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/
3123 static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
3124 {
3125         return;
3126 }
3127
3128 int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3129 {
3130         PPSMC_Result result;
3131         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3132
3133         /* Apply minimum voltage based on DAL's request level */
3134         tonga_apply_dal_minimum_voltage_request(hwmgr);
3135
3136         if (0 == data->sclk_dpm_key_disabled) {
3137                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
3138                 if (0 != tonga_is_dpm_running(hwmgr))
3139                         printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3140
3141                 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3142                         result = smum_send_msg_to_smc_with_parameter(
3143                                                                 hwmgr->smumgr,
3144                                 (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
3145                                 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3146                         PP_ASSERT_WITH_CODE((0 == result),
3147                                 "Set Sclk Dpm enable Mask failed", return -1);
3148                 }
3149         }
3150
3151         if (0 == data->mclk_dpm_key_disabled) {
3152                 /* Checking if DPM is running.  If we discover hang because of this, we should skip this message.*/
3153                 if (0 != tonga_is_dpm_running(hwmgr))
3154                         printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3155
3156                 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3157                         result = smum_send_msg_to_smc_with_parameter(
3158                                                                 hwmgr->smumgr,
3159                                 (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
3160                                 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3161                         PP_ASSERT_WITH_CODE((0 == result),
3162                                 "Set Mclk Dpm enable Mask failed", return -1);
3163                 }
3164         }
3165
3166         return 0;
3167 }
3168
3169
3170 int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
3171 {
3172         uint32_t level, tmp;
3173         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3174
3175         if (0 == data->pcie_dpm_key_disabled) {
3176                 /* PCIE */
3177                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3178                         level = 0;
3179                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3180                         while (tmp >>= 1)
3181                                 level++ ;
3182
3183                         if (0 != level) {
3184                                 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3185                                         "force highest pcie dpm state failed!", return -1);
3186                         }
3187                 }
3188         }
3189
3190         if (0 == data->sclk_dpm_key_disabled) {
3191                 /* SCLK */
3192                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
3193                         level = 0;
3194                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3195                         while (tmp >>= 1)
3196                                 level++ ;
3197
3198                         if (0 != level) {
3199                                 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3200                                         "force highest sclk dpm state failed!", return -1);
3201                                 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3202                                         CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3203                                         printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3204                                                 Curr_Sclk_Index does not match the level \n");
3205
3206                         }
3207                 }
3208         }
3209
3210         if (0 == data->mclk_dpm_key_disabled) {
3211                 /* MCLK */
3212                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3213                         level = 0;
3214                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3215                         while (tmp >>= 1)
3216                                 level++ ;
3217
3218                         if (0 != level) {
3219                                 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3220                                         "force highest mclk dpm state failed!", return -1);
3221                                 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3222                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3223                                         printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3224                                                 Curr_Mclk_Index does not match the level \n");
3225                         }
3226                 }
3227         }
3228
3229         return 0;
3230 }
3231
3232 /**
3233  * Find the MC microcode version and store it in the HwMgr struct
3234  *
3235  * @param    hwmgr  the address of the powerplay hardware manager.
3236  * @return   always 0
3237  */
3238 int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
3239 {
3240         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
3241
3242         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
3243
3244         return 0;
3245 }
3246
3247 /**
3248  * Initialize Dynamic State Adjustment Rule Settings
3249  *
3250  * @param    hwmgr  the address of the powerplay hardware manager.
3251  */
3252 int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
3253 {
3254         uint32_t table_size;
3255         struct phm_clock_voltage_dependency_table *table_clk_vlt;
3256         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3257
3258         hwmgr->dyn_state.mclk_sclk_ratio = 4;
3259         hwmgr->dyn_state.sclk_mclk_delta = 15000;      /* 150 MHz */
3260         hwmgr->dyn_state.vddc_vddci_delta = 200;       /* 200mV */
3261
3262         /* initialize vddc_dep_on_dal_pwrl table */
3263         table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
3264         table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
3265
3266         if (NULL == table_clk_vlt) {
3267                 printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3268                 return -ENOMEM;
3269         } else {
3270                 table_clk_vlt->count = 4;
3271                 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
3272                 table_clk_vlt->entries[0].v = 0;
3273                 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
3274                 table_clk_vlt->entries[1].v = 720;
3275                 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
3276                 table_clk_vlt->entries[2].v = 810;
3277                 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
3278                 table_clk_vlt->entries[3].v = 900;
3279                 pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
3280                 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
3281         }
3282
3283         return 0;
3284 }
3285
3286 static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
3287 {
3288         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3289         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3290
3291         phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3292                 pptable_info->vdd_dep_on_sclk;
3293         phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3294                 pptable_info->vdd_dep_on_mclk;
3295
3296         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3297                 "VDD dependency on SCLK table is missing.       \
3298                 This table is mandatory", return -1);
3299         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3300                 "VDD dependency on SCLK table has to have is missing.   \
3301                 This table is mandatory", return -1);
3302
3303         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3304                 "VDD dependency on MCLK table is missing.       \
3305                 This table is mandatory", return -1);
3306         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3307                 "VDD dependency on MCLK table has to have is missing.    \
3308                 This table is mandatory", return -1);
3309
3310         data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
3311         data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3312
3313         pptable_info->max_clock_voltage_on_ac.sclk =
3314                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3315         pptable_info->max_clock_voltage_on_ac.mclk =
3316                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3317         pptable_info->max_clock_voltage_on_ac.vddc =
3318                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3319         pptable_info->max_clock_voltage_on_ac.vddci =
3320                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3321
3322         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
3323                 pptable_info->max_clock_voltage_on_ac.sclk;
3324         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
3325                 pptable_info->max_clock_voltage_on_ac.mclk;
3326         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
3327                 pptable_info->max_clock_voltage_on_ac.vddc;
3328         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
3329                 pptable_info->max_clock_voltage_on_ac.vddci;
3330
3331         return 0;
3332 }
3333
3334 int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3335 {
3336         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3337         int result = 1;
3338
3339         PP_ASSERT_WITH_CODE (0 == tonga_is_dpm_running(hwmgr),
3340                 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
3341                                                         return result);
3342
3343         if (0 == data->pcie_dpm_key_disabled) {
3344                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
3345                                                              hwmgr->smumgr,
3346                                         PPSMC_MSG_PCIeDPM_UnForceLevel)),
3347                                            "unforce pcie level failed!",
3348                                                                 return -1);
3349         }
3350
3351         result = tonga_upload_dpm_level_enable_mask(hwmgr);
3352
3353         return result;
3354 }
3355
3356 static uint32_t tonga_get_lowest_enable_level(
3357                                 struct pp_hwmgr *hwmgr, uint32_t level_mask)
3358 {
3359         uint32_t level = 0;
3360
3361         while (0 == (level_mask & (1 << level)))
3362                 level++;
3363
3364         return level;
3365 }
3366
3367 static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3368 {
3369         uint32_t level;
3370         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3371
3372         if (0 == data->pcie_dpm_key_disabled) {
3373                 /* PCIE */
3374                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3375                         level = tonga_get_lowest_enable_level(hwmgr,
3376                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3377                         PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3378                                             "force lowest pcie dpm state failed!", return -1);
3379                 }
3380         }
3381
3382         if (0 == data->sclk_dpm_key_disabled) {
3383                 /* SCLK */
3384                 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3385                         level = tonga_get_lowest_enable_level(hwmgr,
3386                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3387
3388                         PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3389                                             "force sclk dpm state failed!", return -1);
3390
3391                         if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3392                                                          CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3393                                 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index.        \
3394                                 Curr_Sclk_Index does not match the level \n");
3395                 }
3396         }
3397
3398         if (0 == data->mclk_dpm_key_disabled) {
3399                 /* MCLK */
3400                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3401                         level = tonga_get_lowest_enable_level(hwmgr,
3402                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3403                         PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3404                                             "force lowest mclk dpm state failed!", return -1);
3405                         if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3406                                                          TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3407                                 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3408                                                 Curr_Mclk_Index does not match the level \n");
3409                 }
3410         }
3411
3412         return 0;
3413 }
3414
3415 static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr)
3416 {
3417         uint8_t entryId;
3418         uint8_t voltageId;
3419         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3420         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3421
3422         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3423         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3424         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3425
3426         if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3427                 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3428                         voltageId = sclk_table->entries[entryId].vddInd;
3429                         sclk_table->entries[entryId].vddgfx =
3430                                 pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd;
3431                 }
3432         } else {
3433                 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3434                         voltageId = sclk_table->entries[entryId].vddInd;
3435                         sclk_table->entries[entryId].vddc =
3436                                 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3437                 }
3438         }
3439
3440         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3441                 voltageId = mclk_table->entries[entryId].vddInd;
3442                 mclk_table->entries[entryId].vddc =
3443                         pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3444         }
3445
3446         for (entryId = 0; entryId < mm_table->count; ++entryId) {
3447                 voltageId = mm_table->entries[entryId].vddcInd;
3448                 mm_table->entries[entryId].vddc =
3449                         pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3450         }
3451
3452         return 0;
3453
3454 }
3455
3456 static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3457 {
3458         uint8_t entryId;
3459         phm_ppt_v1_voltage_lookup_record v_record;
3460         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3461         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3462
3463         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3464         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3465
3466         if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3467                 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3468                         if (sclk_table->entries[entryId].vdd_offset & (1 << 15))
3469                                 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3470                                         sclk_table->entries[entryId].vdd_offset - 0xFFFF;
3471                         else
3472                                 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3473                                         sclk_table->entries[entryId].vdd_offset;
3474
3475                         sclk_table->entries[entryId].vddc =
3476                                 v_record.us_cac_low = v_record.us_cac_mid =
3477                                 v_record.us_cac_high = v_record.us_vdd;
3478
3479                         tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
3480                 }
3481
3482                 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3483                         if (mclk_table->entries[entryId].vdd_offset & (1 << 15))
3484                                 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3485                                         mclk_table->entries[entryId].vdd_offset - 0xFFFF;
3486                         else
3487                                 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3488                                         mclk_table->entries[entryId].vdd_offset;
3489
3490                         mclk_table->entries[entryId].vddgfx = v_record.us_cac_low =
3491                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3492                         tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3493                 }
3494         }
3495
3496         return 0;
3497
3498 }
3499
3500 static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3501 {
3502         uint32_t entryId;
3503         phm_ppt_v1_voltage_lookup_record v_record;
3504         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3505         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3506         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3507
3508         if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3509                 for (entryId = 0; entryId < mm_table->count; entryId++) {
3510                         if (mm_table->entries[entryId].vddgfx_offset & (1 << 15))
3511                                 v_record.us_vdd = mm_table->entries[entryId].vddc +
3512                                         mm_table->entries[entryId].vddgfx_offset - 0xFFFF;
3513                         else
3514                                 v_record.us_vdd = mm_table->entries[entryId].vddc +
3515                                         mm_table->entries[entryId].vddgfx_offset;
3516
3517                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
3518                         mm_table->entries[entryId].vddgfx = v_record.us_cac_low =
3519                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3520                         tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3521                 }
3522         }
3523         return 0;
3524 }
3525
3526
3527 /**
3528  * Change virtual leakage voltage to actual value.
3529  *
3530  * @param     hwmgr  the address of the powerplay hardware manager.
3531  * @param     pointer to changing voltage
3532  * @param     pointer to leakage table
3533  */
3534 static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
3535                 uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable)
3536 {
3537         uint32_t leakage_index;
3538
3539         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3540         for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) {
3541                 /* if this voltage matches a leakage voltage ID */
3542                 /* patch with actual leakage voltage */
3543                 if (pLeakageTable->leakage_id[leakage_index] == *voltage) {
3544                         *voltage = pLeakageTable->actual_voltage[leakage_index];
3545                         break;
3546                 }
3547         }
3548
3549         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
3550                 printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n");
3551 }
3552
3553 /**
3554  * Patch voltage lookup table by EVV leakages.
3555  *
3556  * @param     hwmgr  the address of the powerplay hardware manager.
3557  * @param     pointer to voltage lookup table
3558  * @param     pointer to leakage table
3559  * @return     always 0
3560  */
3561 static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
3562                 phm_ppt_v1_voltage_lookup_table *lookup_table,
3563                 phw_tonga_leakage_voltage *pLeakageTable)
3564 {
3565         uint32_t i;
3566
3567         for (i = 0; i < lookup_table->count; i++) {
3568                 tonga_patch_with_vdd_leakage(hwmgr,
3569                         &lookup_table->entries[i].us_vdd, pLeakageTable);
3570         }
3571
3572         return 0;
3573 }
3574
3575 static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr,
3576                 phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc)
3577 {
3578         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3579
3580         tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable);
3581         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
3582                 pptable_info->max_clock_voltage_on_dc.vddc;
3583
3584         return 0;
3585 }
3586
3587 static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
3588                 struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable,
3589                 uint16_t *Vddgfx)
3590 {
3591         tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable);
3592         return 0;
3593 }
3594
3595 int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
3596                 phm_ppt_v1_voltage_lookup_table *lookup_table)
3597 {
3598         uint32_t table_size, i, j;
3599         phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3600         table_size = lookup_table->count;
3601
3602         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3603                 "Lookup table is empty", return -1);
3604
3605         /* Sorting voltages */
3606         for (i = 0; i < table_size - 1; i++) {
3607                 for (j = i + 1; j > 0; j--) {
3608                         if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) {
3609                                 tmp_voltage_lookup_record = lookup_table->entries[j-1];
3610                                 lookup_table->entries[j-1] = lookup_table->entries[j];
3611                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
3612                         }
3613                 }
3614         }
3615
3616         return 0;
3617 }
3618
3619 static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3620 {
3621         int result = 0;
3622         int tmp_result;
3623         tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3624         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3625
3626         if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3627                 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3628                         pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
3629                 if (tmp_result != 0)
3630                         result = tmp_result;
3631
3632                 tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr,
3633                         &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx);
3634                 if (tmp_result != 0)
3635                         result = tmp_result;
3636         } else {
3637                 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3638                         pptable_info->vddc_lookup_table, &(data->vddc_leakage));
3639                 if (tmp_result != 0)
3640                         result = tmp_result;
3641
3642                 tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr,
3643                         &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc);
3644                 if (tmp_result != 0)
3645                         result = tmp_result;
3646         }
3647
3648         tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3649         if (tmp_result != 0)
3650                 result = tmp_result;
3651
3652         tmp_result = tonga_calc_voltage_dependency_tables(hwmgr);
3653         if (tmp_result != 0)
3654                 result = tmp_result;
3655
3656         tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr);
3657         if (tmp_result != 0)
3658                 result = tmp_result;
3659
3660         tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table);
3661         if (tmp_result != 0)
3662                 result = tmp_result;
3663
3664         tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table);
3665         if (tmp_result != 0)
3666                 result = tmp_result;
3667
3668         return result;
3669 }
3670
3671 int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
3672 {
3673         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3674         data->low_sclk_interrupt_threshold = 0;
3675
3676         return 0;
3677 }
3678
3679 int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
3680 {
3681         int tmp_result, result = 0;
3682
3683         tmp_result = tonga_read_clock_registers(hwmgr);
3684         PP_ASSERT_WITH_CODE((0 == tmp_result),
3685                 "Failed to read clock registers!", result = tmp_result);
3686
3687         tmp_result = tonga_get_memory_type(hwmgr);
3688         PP_ASSERT_WITH_CODE((0 == tmp_result),
3689                 "Failed to get memory type!", result = tmp_result);
3690
3691         tmp_result = tonga_enable_acpi_power_management(hwmgr);
3692         PP_ASSERT_WITH_CODE((0 == tmp_result),
3693                 "Failed to enable ACPI power management!", result = tmp_result);
3694
3695         tmp_result = tonga_init_power_gate_state(hwmgr);
3696         PP_ASSERT_WITH_CODE((0 == tmp_result),
3697                 "Failed to init power gate state!", result = tmp_result);
3698
3699         tmp_result = tonga_get_mc_microcode_version(hwmgr);
3700         PP_ASSERT_WITH_CODE((0 == tmp_result),
3701                 "Failed to get MC microcode version!", result = tmp_result);
3702
3703         tmp_result = tonga_init_sclk_threshold(hwmgr);
3704         PP_ASSERT_WITH_CODE((0 == tmp_result),
3705                 "Failed to init sclk threshold!", result = tmp_result);
3706
3707         return result;
3708 }
3709
3710 /**
3711  * Enable voltage control
3712  *
3713  * @param    hwmgr  the address of the powerplay hardware manager.
3714  * @return   always 0
3715  */
3716 int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
3717 {
3718         /* enable voltage control */
3719         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
3720
3721         return 0;
3722 }
3723
3724 /**
3725  * Checks if we want to support voltage control
3726  *
3727  * @param    hwmgr  the address of the powerplay hardware manager.
3728  */
3729 bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
3730 {
3731         const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3732
3733         return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control);
3734 }
3735
3736 /*---------------------------MC----------------------------*/
3737
3738 uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
3739 {
3740         return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
3741 }
3742
3743 bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
3744 {
3745         bool result = 1;
3746
3747         switch (inReg) {
3748         case  mmMC_SEQ_RAS_TIMING:
3749                 *outReg = mmMC_SEQ_RAS_TIMING_LP;
3750                 break;
3751
3752         case  mmMC_SEQ_DLL_STBY:
3753                 *outReg = mmMC_SEQ_DLL_STBY_LP;
3754                 break;
3755
3756         case  mmMC_SEQ_G5PDX_CMD0:
3757                 *outReg = mmMC_SEQ_G5PDX_CMD0_LP;
3758                 break;
3759
3760         case  mmMC_SEQ_G5PDX_CMD1:
3761                 *outReg = mmMC_SEQ_G5PDX_CMD1_LP;
3762                 break;
3763
3764         case  mmMC_SEQ_G5PDX_CTRL:
3765                 *outReg = mmMC_SEQ_G5PDX_CTRL_LP;
3766                 break;
3767
3768         case mmMC_SEQ_CAS_TIMING:
3769                 *outReg = mmMC_SEQ_CAS_TIMING_LP;
3770                 break;
3771
3772         case mmMC_SEQ_MISC_TIMING:
3773                 *outReg = mmMC_SEQ_MISC_TIMING_LP;
3774                 break;
3775
3776         case mmMC_SEQ_MISC_TIMING2:
3777                 *outReg = mmMC_SEQ_MISC_TIMING2_LP;
3778                 break;
3779
3780         case mmMC_SEQ_PMG_DVS_CMD:
3781                 *outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
3782                 break;
3783
3784         case mmMC_SEQ_PMG_DVS_CTL:
3785                 *outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
3786                 break;
3787
3788         case mmMC_SEQ_RD_CTL_D0:
3789                 *outReg = mmMC_SEQ_RD_CTL_D0_LP;
3790                 break;
3791
3792         case mmMC_SEQ_RD_CTL_D1:
3793                 *outReg = mmMC_SEQ_RD_CTL_D1_LP;
3794                 break;
3795
3796         case mmMC_SEQ_WR_CTL_D0:
3797                 *outReg = mmMC_SEQ_WR_CTL_D0_LP;
3798                 break;
3799
3800         case mmMC_SEQ_WR_CTL_D1:
3801                 *outReg = mmMC_SEQ_WR_CTL_D1_LP;
3802                 break;
3803
3804         case mmMC_PMG_CMD_EMRS:
3805                 *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
3806                 break;
3807
3808         case mmMC_PMG_CMD_MRS:
3809                 *outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
3810                 break;
3811
3812         case mmMC_PMG_CMD_MRS1:
3813                 *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
3814                 break;
3815
3816         case mmMC_SEQ_PMG_TIMING:
3817                 *outReg = mmMC_SEQ_PMG_TIMING_LP;
3818                 break;
3819
3820         case mmMC_PMG_CMD_MRS2:
3821                 *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
3822                 break;
3823
3824         case mmMC_SEQ_WR_CTL_2:
3825                 *outReg = mmMC_SEQ_WR_CTL_2_LP;
3826                 break;
3827
3828         default:
3829                 result = 0;
3830                 break;
3831         }
3832
3833         return result;
3834 }
3835
3836 int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
3837 {
3838         uint32_t i;
3839         uint16_t address;
3840
3841         for (i = 0; i < table->last; i++) {
3842                 table->mc_reg_address[i].s0 =
3843                         tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
3844                         ? address : table->mc_reg_address[i].s1;
3845         }
3846         return 0;
3847 }
3848
3849 int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
3850 {
3851         uint8_t i, j;
3852
3853         PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3854                 "Invalid VramInfo table.", return -1);
3855         PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
3856                 "Invalid VramInfo table.", return -1);
3857
3858         for (i = 0; i < table->last; i++) {
3859                 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
3860         }
3861         ni_table->last = table->last;
3862
3863         for (i = 0; i < table->num_entries; i++) {
3864                 ni_table->mc_reg_table_entry[i].mclk_max =
3865                         table->mc_reg_table_entry[i].mclk_max;
3866                 for (j = 0; j < table->last; j++) {
3867                         ni_table->mc_reg_table_entry[i].mc_data[j] =
3868                                 table->mc_reg_table_entry[i].mc_data[j];
3869                 }
3870         }
3871
3872         ni_table->num_entries = table->num_entries;
3873
3874         return 0;
3875 }
3876
3877 /**
3878  * VBIOS omits some information to reduce size, we need to recover them here.
3879  * 1.   when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to  mmMC_PMG_CMD_EMRS /_LP[15:0].
3880  *      Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3881  * 2.   when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
3882  * 3.   need to set these data for each clock range
3883  *
3884  * @param    hwmgr the address of the powerplay hardware manager.
3885  * @param    table the address of MCRegTable
3886  * @return   always 0
3887  */
3888 int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
3889 {
3890         uint8_t i, j, k;
3891         uint32_t temp_reg;
3892         const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3893
3894         for (i = 0, j = table->last; i < table->last; i++) {
3895                 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3896                         "Invalid VramInfo table.", return -1);
3897                 switch (table->mc_reg_address[i].s1) {
3898                 /*
3899                 * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to  mmMC_PMG_CMD_EMRS /_LP[15:0].
3900                 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3901                 */
3902                 case mmMC_SEQ_MISC1:
3903                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
3904                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
3905                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
3906                         for (k = 0; k < table->num_entries; k++) {
3907                                 table->mc_reg_table_entry[k].mc_data[j] =
3908                                         ((temp_reg & 0xffff0000)) |
3909                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3910                         }
3911                         j++;
3912                         PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3913                                 "Invalid VramInfo table.", return -1);
3914
3915                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3916                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3917                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3918                         for (k = 0; k < table->num_entries; k++) {
3919                                 table->mc_reg_table_entry[k].mc_data[j] =
3920                                         (temp_reg & 0xffff0000) |
3921                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3922
3923                                 if (!data->is_memory_GDDR5) {
3924                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3925                                 }
3926                         }
3927                         j++;
3928                         PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3929                                 "Invalid VramInfo table.", return -1);
3930
3931                         if (!data->is_memory_GDDR5) {
3932                                 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3933                                 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3934                                 for (k = 0; k < table->num_entries; k++) {
3935                                         table->mc_reg_table_entry[k].mc_data[j] =
3936                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3937                                 }
3938                                 j++;
3939                                 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3940                                         "Invalid VramInfo table.", return -1);
3941                         }
3942
3943                         break;
3944
3945                 case mmMC_SEQ_RESERVE_M:
3946                         temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3947                         table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3948                         table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3949                         for (k = 0; k < table->num_entries; k++) {
3950                                 table->mc_reg_table_entry[k].mc_data[j] =
3951                                         (temp_reg & 0xffff0000) |
3952                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3953                         }
3954                         j++;
3955                         PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3956                                 "Invalid VramInfo table.", return -1);
3957                         break;
3958
3959                 default:
3960                         break;
3961                 }
3962
3963         }
3964
3965         table->last = j;
3966
3967         return 0;
3968 }
3969
3970 int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
3971 {
3972         uint8_t i, j;
3973         for (i = 0; i < table->last; i++) {
3974                 for (j = 1; j < table->num_entries; j++) {
3975                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3976                                 table->mc_reg_table_entry[j].mc_data[i]) {
3977                                 table->validflag |= (1<<i);
3978                                 break;
3979                         }
3980                 }
3981         }
3982
3983         return 0;
3984 }
3985
3986 int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
3987 {
3988         int result;
3989         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3990         pp_atomctrl_mc_reg_table *table;
3991         phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table;
3992         uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
3993
3994         table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
3995
3996         if (NULL == table)
3997                 return -ENOMEM;
3998
3999         /* Program additional LP registers that are no longer programmed by VBIOS */
4000         cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
4001         cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
4002         cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
4003         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
4004         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
4005         cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
4006         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
4007         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
4008         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
4009         cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
4010         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
4011         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
4012         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
4013         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
4014         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
4015         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
4016         cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
4017         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
4018         cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
4019         cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
4020
4021         memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
4022
4023         result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
4024
4025         if (0 == result)
4026                 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
4027
4028         if (0 == result) {
4029                 tonga_set_s0_mc_reg_index(ni_table);
4030                 result = tonga_set_mc_special_registers(hwmgr, ni_table);
4031         }
4032
4033         if (0 == result)
4034                 tonga_set_valid_flag(ni_table);
4035
4036         kfree(table);
4037         return result;
4038 }
4039
4040 /*
4041 * Copy one arb setting to another and then switch the active set.
4042 * arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
4043 */
4044 int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
4045                 uint32_t arbFreqSrc, uint32_t arbFreqDest)
4046 {
4047         uint32_t mc_arb_dram_timing;
4048         uint32_t mc_arb_dram_timing2;
4049         uint32_t burst_time;
4050         uint32_t mc_cg_config;
4051
4052         switch (arbFreqSrc) {
4053         case MC_CG_ARB_FREQ_F0:
4054                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
4055                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
4056                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
4057                 break;
4058
4059         case MC_CG_ARB_FREQ_F1:
4060                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
4061                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
4062                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
4063                 break;
4064
4065         default:
4066                 return -1;
4067         }
4068
4069         switch (arbFreqDest) {
4070         case MC_CG_ARB_FREQ_F0:
4071                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
4072                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
4073                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
4074                 break;
4075
4076         case MC_CG_ARB_FREQ_F1:
4077                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
4078                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
4079                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
4080                 break;
4081
4082         default:
4083                 return -1;
4084         }
4085
4086         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
4087         mc_cg_config |= 0x0000000F;
4088         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
4089         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
4090
4091         return 0;
4092 }
4093
4094 /**
4095  * Initial switch from ARB F0->F1
4096  *
4097  * @param    hwmgr  the address of the powerplay hardware manager.
4098  * @return   always 0
4099  * This function is to be called from the SetPowerState table.
4100  */
4101 int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
4102 {
4103         return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4104 }
4105
4106 /**
4107  * Initialize the ARB DRAM timing table's index field.
4108  *
4109  * @param    hwmgr  the address of the powerplay hardware manager.
4110  * @return   always 0
4111  */
4112 int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
4113 {
4114         const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4115         uint32_t tmp;
4116         int result;
4117
4118         /*
4119         * This is a read-modify-write on the first byte of the ARB table.
4120         * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'.
4121         * This solution is ugly, but we never write the whole table only individual fields in it.
4122         * In reality this field should not be in that structure but in a soft register.
4123         */
4124         result = tonga_read_smc_sram_dword(hwmgr->smumgr,
4125                                 data->arb_table_start, &tmp, data->sram_end);
4126
4127         if (0 != result)
4128                 return result;
4129
4130         tmp &= 0x00FFFFFF;
4131         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
4132
4133         return tonga_write_smc_sram_dword(hwmgr->smumgr,
4134                         data->arb_table_start,  tmp, data->sram_end);
4135 }
4136
4137 int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
4138 {
4139         const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4140
4141         uint32_t i, j;
4142
4143         for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) {
4144                 if (data->tonga_mc_reg_table.validflag & 1<<j) {
4145                         PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
4146                                 "Index of mc_reg_table->address[] array out of boundary", return -1);
4147                         mc_reg_table->address[i].s0 =
4148                                 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0);
4149                         mc_reg_table->address[i].s1 =
4150                                 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1);
4151                         i++;
4152                 }
4153         }
4154
4155         mc_reg_table->last = (uint8_t)i;
4156
4157         return 0;
4158 }
4159
4160 /*convert register values from driver to SMC format */
4161 void tonga_convert_mc_registers(
4162         const phw_tonga_mc_reg_entry * pEntry,
4163         SMU72_Discrete_MCRegisterSet *pData,
4164         uint32_t numEntries, uint32_t validflag)
4165 {
4166         uint32_t i, j;
4167
4168         for (i = 0, j = 0; j < numEntries; j++) {
4169                 if (validflag & 1<<j) {
4170                         pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
4171                         i++;
4172                 }
4173         }
4174 }
4175
4176 /* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
4177 int tonga_convert_mc_reg_table_entry_to_smc(
4178                 struct pp_hwmgr *hwmgr,
4179                 const uint32_t memory_clock,
4180                 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
4181                 )
4182 {
4183         const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4184         uint32_t i = 0;
4185
4186         for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) {
4187                 if (memory_clock <=
4188                         data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
4189                         break;
4190                 }
4191         }
4192
4193         if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0))
4194                 --i;
4195
4196         tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i],
4197                 mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag);
4198
4199         return 0;
4200 }
4201
4202 int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
4203                 SMU72_Discrete_MCRegisters *mc_reg_table)
4204 {
4205         int result = 0;
4206         tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4207         int res;
4208         uint32_t i;
4209
4210         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
4211                 res = tonga_convert_mc_reg_table_entry_to_smc(
4212                                 hwmgr,
4213                                 data->dpm_table.mclk_table.dpm_levels[i].value,
4214                                 &mc_reg_table->data[i]
4215                                 );
4216
4217                 if (0 != res)
4218                         result = res;
4219         }
4220
4221         return result;
4222 }
4223
4224 int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
4225 {
4226         int result;
4227         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4228
4229         memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters));
4230         result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
4231         PP_ASSERT_WITH_CODE(0 == result,
4232                 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
4233
4234         result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
4235         PP_ASSERT_WITH_CODE(0 == result,
4236                 "Failed to initialize MCRegTable for driver state!", return result;);
4237
4238         return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
4239                         (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end);
4240 }
4241
4242 /**
4243  * Programs static screed detection parameters
4244  *
4245  * @param   hwmgr  the address of the powerplay hardware manager.
4246  * @return   always 0
4247  */
4248 int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
4249 {
4250         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4251
4252         /* Set static screen threshold unit*/
4253         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4254                 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
4255                 data->static_screen_threshold_unit);
4256         /* Set static screen threshold*/
4257         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4258                 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
4259                 data->static_screen_threshold);
4260
4261         return 0;
4262 }
4263
4264 /**
4265  * Setup display gap for glitch free memory clock switching.
4266  *
4267  * @param    hwmgr  the address of the powerplay hardware manager.
4268  * @return   always 0
4269  */
4270 int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
4271 {
4272         uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4273                                                         CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4274
4275         display_gap = PHM_SET_FIELD(display_gap,
4276                                         CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
4277
4278         display_gap = PHM_SET_FIELD(display_gap,
4279                                         CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
4280
4281         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4282                 ixCG_DISPLAY_GAP_CNTL, display_gap);
4283
4284         return 0;
4285 }
4286
4287 /**
4288  * Programs activity state transition voting clients
4289  *
4290  * @param    hwmgr  the address of the powerplay hardware manager.
4291  * @return   always 0
4292  */
4293 int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
4294 {
4295         tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4296
4297         /* Clear reset for voting clients before enabling DPM */
4298         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4299                 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
4300         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4301                 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
4302
4303         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4304                 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
4305         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4306                 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
4307         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4308                 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
4309         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4310                 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
4311         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4312                 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
4313         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4314                 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
4315         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4316                 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
4317         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4318                 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
4319
4320         return 0;
4321 }
4322
4323
4324 int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
4325 {
4326         int tmp_result, result = 0;
4327
4328         tmp_result = tonga_check_for_dpm_stopped(hwmgr);
4329
4330         if (cf_tonga_voltage_control(hwmgr)) {
4331                 tmp_result = tonga_enable_voltage_control(hwmgr);
4332                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4333                         "Failed to enable voltage control!", result = tmp_result);
4334
4335                 tmp_result = tonga_construct_voltage_tables(hwmgr);
4336                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4337                         "Failed to contruct voltage tables!", result = tmp_result);
4338         }
4339
4340         tmp_result = tonga_initialize_mc_reg_table(hwmgr);
4341         PP_ASSERT_WITH_CODE((0 == tmp_result),
4342                 "Failed to initialize MC reg table!", result = tmp_result);
4343
4344         tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr);
4345         PP_ASSERT_WITH_CODE((0 == tmp_result),
4346                 "Failed to program static screen threshold parameters!", result = tmp_result);
4347
4348         tmp_result = tonga_enable_display_gap(hwmgr);
4349         PP_ASSERT_WITH_CODE((0 == tmp_result),
4350                 "Failed to enable display gap!", result = tmp_result);
4351
4352         tmp_result = tonga_program_voting_clients(hwmgr);
4353         PP_ASSERT_WITH_CODE((0 == tmp_result),
4354                 "Failed to program voting clients!", result = tmp_result);
4355
4356         tmp_result = tonga_process_firmware_header(hwmgr);
4357         PP_ASSERT_WITH_CODE((0 == tmp_result),
4358                 "Failed to process firmware header!", result = tmp_result);
4359
4360         tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr);
4361         PP_ASSERT_WITH_CODE((0 == tmp_result),
4362                 "Failed to initialize switch from ArbF0 to F1!", result = tmp_result);
4363
4364         tmp_result = tonga_init_smc_table(hwmgr);
4365         PP_ASSERT_WITH_CODE((0 == tmp_result),
4366                 "Failed to initialize SMC table!", result = tmp_result);
4367
4368         tmp_result = tonga_init_arb_table_index(hwmgr);
4369         PP_ASSERT_WITH_CODE((0 == tmp_result),
4370                 "Failed to initialize ARB table index!", result = tmp_result);
4371
4372         tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
4373         PP_ASSERT_WITH_CODE((0 == tmp_result),
4374                 "Failed to populate initialize MC Reg table!", result = tmp_result);
4375
4376         tmp_result = tonga_notify_smc_display_change(hwmgr, false);
4377         PP_ASSERT_WITH_CODE((0 == tmp_result),
4378                 "Failed to notify no display!", result = tmp_result);
4379
4380         /* enable SCLK control */
4381         tmp_result = tonga_enable_sclk_control(hwmgr);
4382         PP_ASSERT_WITH_CODE((0 == tmp_result),
4383                 "Failed to enable SCLK control!", result = tmp_result);
4384
4385         /* enable DPM */
4386         tmp_result = tonga_start_dpm(hwmgr);
4387         PP_ASSERT_WITH_CODE((0 == tmp_result),
4388                 "Failed to start DPM!", result = tmp_result);
4389
4390         return result;
4391 }
4392
4393 int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4394 {
4395         int tmp_result, result = 0;
4396
4397         tmp_result = tonga_check_for_dpm_running(hwmgr);
4398         PP_ASSERT_WITH_CODE((0 == tmp_result),
4399                 "SMC is still running!", return 0);
4400
4401         tmp_result = tonga_stop_dpm(hwmgr);
4402         PP_ASSERT_WITH_CODE((0 == tmp_result),
4403                 "Failed to stop DPM!", result = tmp_result);
4404
4405         tmp_result = tonga_reset_to_default(hwmgr);
4406         PP_ASSERT_WITH_CODE((0 == tmp_result),
4407                 "Failed to reset to default!", result = tmp_result);
4408
4409         return result;
4410 }
4411
4412 int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
4413 {
4414         int result;
4415
4416         result = tonga_set_boot_state(hwmgr);
4417         if (0 != result)
4418                 printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n");
4419
4420         return result;
4421 }
4422
4423 int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
4424 {
4425         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4426
4427         if (data->soft_pp_table) {
4428                 kfree(data->soft_pp_table);
4429                 data->soft_pp_table = NULL;
4430         }
4431
4432         return phm_hwmgr_backend_fini(hwmgr);
4433 }
4434
4435 /**
4436  * Initializes the Volcanic Islands Hardware Manager
4437  *
4438  * @param   hwmgr the address of the powerplay hardware manager.
4439  * @return   1 if success; otherwise appropriate error code.
4440  */
4441 int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4442 {
4443         int result = 0;
4444         SMU72_Discrete_DpmTable  *table = NULL;
4445         tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4446         pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4447         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4448         phw_tonga_ulv_parm *ulv;
4449         struct cgs_system_info sys_info = {0};
4450
4451         PP_ASSERT_WITH_CODE((NULL != hwmgr),
4452                 "Invalid Parameter!", return -1;);
4453
4454         data->dll_defaule_on = 0;
4455         data->sram_end = SMC_RAM_END;
4456
4457         data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
4458         data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT;
4459         data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT;
4460         data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT;
4461         data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT;
4462         data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT;
4463         data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT;
4464         data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT;
4465
4466         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
4467         data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA;
4468         data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT;
4469
4470         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4471                 PHM_PlatformCaps_DisableVoltageIsland);
4472
4473         data->sclk_dpm_key_disabled = 0;
4474         data->mclk_dpm_key_disabled = 0;
4475         data->pcie_dpm_key_disabled = 0;
4476         data->pcc_monitor_enabled = 0;
4477
4478         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4479                 PHM_PlatformCaps_UnTabledHardwareInterface);
4480
4481         data->gpio_debug = 0;
4482         data->engine_clock_data = 0;
4483         data->memory_clock_data = 0;
4484         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4485                 PHM_PlatformCaps_DynamicPatchPowerState);
4486
4487         /* need to set voltage control types before EVV patching*/
4488         data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE;
4489         data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
4490         data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
4491         data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
4492
4493         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4494                                 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
4495                 data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4496         }
4497
4498         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4499                         PHM_PlatformCaps_ControlVDDGFX)) {
4500                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4501                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
4502                         data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4503                 }
4504         }
4505
4506         if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
4507                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4508                         PHM_PlatformCaps_ControlVDDGFX);
4509         }
4510
4511         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4512                         PHM_PlatformCaps_EnableMVDDControl)) {
4513                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4514                                         VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
4515                         data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4516                 }
4517         }
4518
4519         if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) {
4520                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4521                         PHM_PlatformCaps_EnableMVDDControl);
4522         }
4523
4524         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4525                         PHM_PlatformCaps_ControlVDDCI)) {
4526                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4527                                         VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
4528                         data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4529                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
4530                                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
4531                         data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4532         }
4533
4534         if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control)
4535                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4536                 PHM_PlatformCaps_ControlVDDCI);
4537
4538         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4539                 PHM_PlatformCaps_TablelessHardwareInterface);
4540
4541         if (pptable_info->cac_dtp_table->usClockStretchAmount != 0)
4542                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4543                         PHM_PlatformCaps_ClockStretcher);
4544
4545         /* Initializes DPM default values*/
4546         tonga_initialize_dpm_defaults(hwmgr);
4547
4548         /* Get leakage voltage based on leakage ID.*/
4549         PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)),
4550                 "Get EVV Voltage Failed.  Abort Driver loading!", return -1);
4551
4552         tonga_complete_dependency_tables(hwmgr);
4553
4554         /* Parse pptable data read from VBIOS*/
4555         tonga_set_private_var_based_on_pptale(hwmgr);
4556
4557         /* ULV Support*/
4558         ulv = &(data->ulv);
4559         ulv->ulv_supported = 0;
4560
4561         /* Initalize Dynamic State Adjustment Rule Settings*/
4562         result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
4563         if (result)
4564                 printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n");
4565         data->uvd_enabled = 0;
4566
4567         table = &(data->smc_state_table);
4568
4569         /*
4570         * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable,
4571         * Peak Current Control feature is enabled and we should program PCC HW register
4572         */
4573         if (0 == atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
4574                 uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
4575                                                                                 CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
4576
4577                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
4578                 case 0:
4579                         temp_reg = PHM_SET_FIELD(temp_reg,
4580                                 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
4581                         break;
4582                 case 1:
4583                         temp_reg = PHM_SET_FIELD(temp_reg,
4584                                 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
4585                         break;
4586                 case 2:
4587                         temp_reg = PHM_SET_FIELD(temp_reg,
4588                                 CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
4589                         break;
4590                 case 3:
4591                         temp_reg = PHM_SET_FIELD(temp_reg,
4592                                 CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
4593                         break;
4594                 case 4:
4595                         temp_reg = PHM_SET_FIELD(temp_reg,
4596                                 CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
4597                         break;
4598                 default:
4599                         printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \
4600                                 Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n");
4601                         break;
4602                 }
4603                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4604                         ixCNB_PWRMGT_CNTL, temp_reg);
4605         }
4606
4607         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4608                 PHM_PlatformCaps_EnableSMU7ThermalManagement);
4609         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4610                 PHM_PlatformCaps_SMU7);
4611
4612         data->vddc_phase_shed_control = 0;
4613
4614         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4615                       PHM_PlatformCaps_UVDPowerGating);
4616         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4617                       PHM_PlatformCaps_VCEPowerGating);
4618         sys_info.size = sizeof(struct cgs_system_info);
4619         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
4620         result = cgs_query_system_info(hwmgr->device, &sys_info);
4621         if (!result) {
4622                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
4623                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4624                                       PHM_PlatformCaps_UVDPowerGating);
4625                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
4626                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4627                                       PHM_PlatformCaps_VCEPowerGating);
4628         }
4629
4630         if (0 == result) {
4631                 data->is_tlu_enabled = 0;
4632                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4633                         TONGA_MAX_HARDWARE_POWERLEVELS;
4634                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
4635                 hwmgr->platform_descriptor.minimumClocksReductionPercentage  = 50;
4636
4637                 sys_info.size = sizeof(struct cgs_system_info);
4638                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
4639                 result = cgs_query_system_info(hwmgr->device, &sys_info);
4640                 if (result)
4641                         data->pcie_gen_cap = 0x30007;
4642                 else
4643                         data->pcie_gen_cap = (uint32_t)sys_info.value;
4644                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
4645                         data->pcie_spc_cap = 20;
4646                 sys_info.size = sizeof(struct cgs_system_info);
4647                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
4648                 result = cgs_query_system_info(hwmgr->device, &sys_info);
4649                 if (result)
4650                         data->pcie_lane_cap = 0x2f0000;
4651                 else
4652                         data->pcie_lane_cap = (uint32_t)sys_info.value;
4653         } else {
4654                 /* Ignore return value in here, we are cleaning up a mess. */
4655                 tonga_hwmgr_backend_fini(hwmgr);
4656         }
4657
4658         return result;
4659 }
4660
4661 static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr,
4662                 enum amd_dpm_forced_level level)
4663 {
4664         int ret = 0;
4665
4666         switch (level) {
4667         case AMD_DPM_FORCED_LEVEL_HIGH:
4668                 ret = tonga_force_dpm_highest(hwmgr);
4669                 if (ret)
4670                         return ret;
4671                 break;
4672         case AMD_DPM_FORCED_LEVEL_LOW:
4673                 ret = tonga_force_dpm_lowest(hwmgr);
4674                 if (ret)
4675                         return ret;
4676                 break;
4677         case AMD_DPM_FORCED_LEVEL_AUTO:
4678                 ret = tonga_unforce_dpm_levels(hwmgr);
4679                 if (ret)
4680                         return ret;
4681                 break;
4682         default:
4683                 break;
4684         }
4685
4686         hwmgr->dpm_level = level;
4687         return ret;
4688 }
4689
4690 static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
4691                                 struct pp_power_state  *prequest_ps,
4692                         const struct pp_power_state *pcurrent_ps)
4693 {
4694         struct tonga_power_state *tonga_ps =
4695                                 cast_phw_tonga_power_state(&prequest_ps->hardware);
4696
4697         uint32_t sclk;
4698         uint32_t mclk;
4699         struct PP_Clocks minimum_clocks = {0};
4700         bool disable_mclk_switching;
4701         bool disable_mclk_switching_for_frame_lock;
4702         struct cgs_display_info info = {0};
4703         const struct phm_clock_and_voltage_limits *max_limits;
4704         uint32_t i;
4705         tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4706         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4707
4708         int32_t count;
4709         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
4710
4711         data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
4712
4713         PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2,
4714                                  "VI should always have 2 performance levels",
4715                                  );
4716
4717         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
4718                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
4719                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
4720
4721         if (PP_PowerSource_DC == hwmgr->power_source) {
4722                 for (i = 0; i < tonga_ps->performance_level_count; i++) {
4723                         if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk)
4724                                 tonga_ps->performance_levels[i].memory_clock = max_limits->mclk;
4725                         if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk)
4726                                 tonga_ps->performance_levels[i].engine_clock = max_limits->sclk;
4727                 }
4728         }
4729
4730         tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
4731         tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
4732
4733         tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
4734
4735         cgs_get_active_displays_info(hwmgr->device, &info);
4736
4737         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
4738
4739         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
4740
4741         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4742
4743                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
4744                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
4745
4746                 for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
4747                         if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) {
4748                                 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk;
4749                                 break;
4750                         }
4751                 }
4752
4753                 if (count < 0)
4754                         stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk;
4755
4756                 stable_pstate_mclk = max_limits->mclk;
4757
4758                 minimum_clocks.engineClock = stable_pstate_sclk;
4759                 minimum_clocks.memoryClock = stable_pstate_mclk;
4760         }
4761
4762         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
4763                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
4764
4765         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
4766                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
4767
4768         tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4769
4770         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
4771                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
4772                                         "Overdrive sclk exceeds limit",
4773                                         hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
4774
4775                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4776                         tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
4777         }
4778
4779         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4780                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4781                         "Overdrive mclk exceeds limit",
4782                         hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4783
4784                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4785                         tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
4786         }
4787
4788         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4789                                     hwmgr->platform_descriptor.platformCaps,
4790                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4791
4792         disable_mclk_switching = (1 < info.display_count) ||
4793                                     disable_mclk_switching_for_frame_lock;
4794
4795         sclk  = tonga_ps->performance_levels[0].engine_clock;
4796         mclk  = tonga_ps->performance_levels[0].memory_clock;
4797
4798         if (disable_mclk_switching)
4799                 mclk  = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock;
4800
4801         if (sclk < minimum_clocks.engineClock)
4802                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
4803
4804         if (mclk < minimum_clocks.memoryClock)
4805                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
4806
4807         tonga_ps->performance_levels[0].engine_clock = sclk;
4808         tonga_ps->performance_levels[0].memory_clock = mclk;
4809
4810         tonga_ps->performance_levels[1].engine_clock =
4811                 (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ?
4812                               tonga_ps->performance_levels[1].engine_clock :
4813                               tonga_ps->performance_levels[0].engine_clock;
4814
4815         if (disable_mclk_switching) {
4816                 if (mclk < tonga_ps->performance_levels[1].memory_clock)
4817                         mclk = tonga_ps->performance_levels[1].memory_clock;
4818
4819                 tonga_ps->performance_levels[0].memory_clock = mclk;
4820                 tonga_ps->performance_levels[1].memory_clock = mclk;
4821         } else {
4822                 if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock)
4823                         tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock;
4824         }
4825
4826         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4827                 for (i=0; i < tonga_ps->performance_level_count; i++) {
4828                         tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4829                         tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4830                         tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4831                         tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4832                 }
4833         }
4834
4835         return 0;
4836 }
4837
4838 int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
4839 {
4840         return sizeof(struct tonga_power_state);
4841 }
4842
4843 static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4844 {
4845         struct pp_power_state  *ps;
4846         struct tonga_power_state  *tonga_ps;
4847
4848         if (hwmgr == NULL)
4849                 return -EINVAL;
4850
4851         ps = hwmgr->request_ps;
4852
4853         if (ps == NULL)
4854                 return -EINVAL;
4855
4856         tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4857
4858         if (low)
4859                 return tonga_ps->performance_levels[0].memory_clock;
4860         else
4861                 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
4862 }
4863
4864 static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4865 {
4866         struct pp_power_state  *ps;
4867         struct tonga_power_state  *tonga_ps;
4868
4869         if (hwmgr == NULL)
4870                 return -EINVAL;
4871
4872         ps = hwmgr->request_ps;
4873
4874         if (ps == NULL)
4875                 return -EINVAL;
4876
4877         tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4878
4879         if (low)
4880                 return tonga_ps->performance_levels[0].engine_clock;
4881         else
4882                 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
4883 }
4884
4885 static uint16_t tonga_get_current_pcie_speed(
4886                                                    struct pp_hwmgr *hwmgr)
4887 {
4888         uint32_t speed_cntl = 0;
4889
4890         speed_cntl = cgs_read_ind_register(hwmgr->device,
4891                                                    CGS_IND_REG__PCIE,
4892                                                    ixPCIE_LC_SPEED_CNTL);
4893         return((uint16_t)PHM_GET_FIELD(speed_cntl,
4894                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4895 }
4896
4897 static int tonga_get_current_pcie_lane_number(
4898                                                    struct pp_hwmgr *hwmgr)
4899 {
4900         uint32_t link_width;
4901
4902         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4903                                                         CGS_IND_REG__PCIE,
4904                                                   PCIE_LC_LINK_WIDTH_CNTL,
4905                                                         LC_LINK_WIDTH_RD);
4906
4907         PP_ASSERT_WITH_CODE((7 >= link_width),
4908                         "Invalid PCIe lane width!", return 0);
4909
4910         return decode_pcie_lane_width(link_width);
4911 }
4912
4913 static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
4914                                         struct pp_hw_power_state *hw_ps)
4915 {
4916         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4917         struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps;
4918         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
4919         uint16_t size;
4920         uint8_t frev, crev;
4921         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
4922
4923         /* First retrieve the Boot clocks and VDDC from the firmware info table.
4924          * We assume here that fw_info is unchanged if this call fails.
4925          */
4926         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
4927                         hwmgr->device, index,
4928                         &size, &frev, &crev);
4929         if (!fw_info)
4930                 /* During a test, there is no firmware info table. */
4931                 return 0;
4932
4933         /* Patch the state. */
4934         data->vbios_boot_state.sclk_bootup_value  = le32_to_cpu(fw_info->ulDefaultEngineClock);
4935         data->vbios_boot_state.mclk_bootup_value  = le32_to_cpu(fw_info->ulDefaultMemoryClock);
4936         data->vbios_boot_state.mvdd_bootup_value  = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
4937         data->vbios_boot_state.vddc_bootup_value  = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
4938         data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
4939         data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr);
4940         data->vbios_boot_state.pcie_lane_bootup_value =
4941                         (uint16_t)tonga_get_current_pcie_lane_number(hwmgr);
4942
4943         /* set boot power state */
4944         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
4945         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
4946         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
4947         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
4948
4949         return 0;
4950 }
4951
4952 static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
4953                 void *state, struct pp_power_state *power_state,
4954                 void *pp_table, uint32_t classification_flag)
4955 {
4956         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4957
4958         struct tonga_power_state  *tonga_ps =
4959                         (struct tonga_power_state *)(&(power_state->hardware));
4960
4961         struct tonga_performance_level *performance_level;
4962
4963         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
4964
4965         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
4966                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
4967
4968         ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
4969                         (ATOM_Tonga_SCLK_Dependency_Table *)
4970                         (((unsigned long)powerplay_table) +
4971                         le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
4972
4973         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
4974                         (ATOM_Tonga_MCLK_Dependency_Table *)
4975                         (((unsigned long)powerplay_table) +
4976                         le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
4977
4978         /* The following fields are not initialized here: id orderedList allStatesList */
4979         power_state->classification.ui_label =
4980                         (le16_to_cpu(state_entry->usClassification) &
4981                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
4982                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
4983         power_state->classification.flags = classification_flag;
4984         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
4985
4986         power_state->classification.temporary_state = false;
4987         power_state->classification.to_be_deleted = false;
4988
4989         power_state->validation.disallowOnDC =
4990                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC));
4991
4992         power_state->pcie.lanes = 0;
4993
4994         power_state->display.disableFrameModulation = false;
4995         power_state->display.limitRefreshrate = false;
4996         power_state->display.enableVariBright =
4997                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT));
4998
4999         power_state->validation.supportedPowerLevels = 0;
5000         power_state->uvd_clocks.VCLK = 0;
5001         power_state->uvd_clocks.DCLK = 0;
5002         power_state->temperatures.min = 0;
5003         power_state->temperatures.max = 0;
5004
5005         performance_level = &(tonga_ps->performance_levels
5006                         [tonga_ps->performance_level_count++]);
5007
5008         PP_ASSERT_WITH_CODE(
5009                         (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS),
5010                         "Performance levels exceeds SMC limit!",
5011                         return -1);
5012
5013         PP_ASSERT_WITH_CODE(
5014                         (tonga_ps->performance_level_count <=
5015                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
5016                         "Performance levels exceeds Driver limit!",
5017                         return -1);
5018
5019         /* Performance levels are arranged from low to high. */
5020         performance_level->memory_clock =
5021                                 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk);
5022
5023         performance_level->engine_clock =
5024                                 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk);
5025
5026         performance_level->pcie_gen = get_pcie_gen_support(
5027                                                         data->pcie_gen_cap,
5028                                              state_entry->ucPCIEGenLow);
5029
5030         performance_level->pcie_lane = get_pcie_lane_support(
5031                                                     data->pcie_lane_cap,
5032                                            state_entry->ucPCIELaneHigh);
5033
5034         performance_level =
5035                         &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]);
5036
5037         performance_level->memory_clock =
5038                                 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk);
5039
5040         performance_level->engine_clock =
5041                                 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk);
5042
5043         performance_level->pcie_gen = get_pcie_gen_support(
5044                                                         data->pcie_gen_cap,
5045                                             state_entry->ucPCIEGenHigh);
5046
5047         performance_level->pcie_lane = get_pcie_lane_support(
5048                                                     data->pcie_lane_cap,
5049                                            state_entry->ucPCIELaneHigh);
5050
5051         return 0;
5052 }
5053
5054 static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
5055                     unsigned long entry_index, struct pp_power_state *ps)
5056 {
5057         int result;
5058         struct tonga_power_state *tonga_ps;
5059         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5060
5061         struct phm_ppt_v1_information *table_info =
5062                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
5063
5064         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5065                                            table_info->vdd_dep_on_mclk;
5066
5067         ps->hardware.magic = PhwTonga_Magic;
5068
5069         tonga_ps = cast_phw_tonga_power_state(&(ps->hardware));
5070
5071         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps,
5072                         tonga_get_pp_table_entry_callback_func);
5073
5074         /* This is the earliest time we have all the dependency table and the VBIOS boot state
5075          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
5076          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
5077          */
5078         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
5079                 if (dep_mclk_table->entries[0].clk !=
5080                                 data->vbios_boot_state.mclk_bootup_value)
5081                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
5082                                         "does not match VBIOS boot MCLK level");
5083                 if (dep_mclk_table->entries[0].vddci !=
5084                                 data->vbios_boot_state.vddci_bootup_value)
5085                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
5086                                         "does not match VBIOS boot VDDCI level");
5087         }
5088
5089         /* set DC compatible flag if this state supports DC */
5090         if (!ps->validation.disallowOnDC)
5091                 tonga_ps->dc_compatible = true;
5092
5093         if (ps->classification.flags & PP_StateClassificationFlag_ACPI)
5094                 data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen;
5095         else if (ps->classification.flags & PP_StateClassificationFlag_Boot) {
5096                 if (data->bacos.best_match == 0xffff) {
5097                         /* For V.I. use boot state as base BACO state */
5098                         data->bacos.best_match = PP_StateClassificationFlag_Boot;
5099                         data->bacos.performance_level = tonga_ps->performance_levels[0];
5100                 }
5101         }
5102
5103         tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK;
5104         tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK;
5105
5106         if (!result) {
5107                 uint32_t i;
5108
5109                 switch (ps->classification.ui_label) {
5110                 case PP_StateUILabel_Performance:
5111                         data->use_pcie_performance_levels = true;
5112
5113                         for (i = 0; i < tonga_ps->performance_level_count; i++) {
5114                                 if (data->pcie_gen_performance.max <
5115                                                 tonga_ps->performance_levels[i].pcie_gen)
5116                                         data->pcie_gen_performance.max =
5117                                                         tonga_ps->performance_levels[i].pcie_gen;
5118
5119                                 if (data->pcie_gen_performance.min >
5120                                                 tonga_ps->performance_levels[i].pcie_gen)
5121                                         data->pcie_gen_performance.min =
5122                                                         tonga_ps->performance_levels[i].pcie_gen;
5123
5124                                 if (data->pcie_lane_performance.max <
5125                                                 tonga_ps->performance_levels[i].pcie_lane)
5126                                         data->pcie_lane_performance.max =
5127                                                         tonga_ps->performance_levels[i].pcie_lane;
5128
5129                                 if (data->pcie_lane_performance.min >
5130                                                 tonga_ps->performance_levels[i].pcie_lane)
5131                                         data->pcie_lane_performance.min =
5132                                                         tonga_ps->performance_levels[i].pcie_lane;
5133                         }
5134                         break;
5135                 case PP_StateUILabel_Battery:
5136                         data->use_pcie_power_saving_levels = true;
5137
5138                         for (i = 0; i < tonga_ps->performance_level_count; i++) {
5139                                 if (data->pcie_gen_power_saving.max <
5140                                                 tonga_ps->performance_levels[i].pcie_gen)
5141                                         data->pcie_gen_power_saving.max =
5142                                                         tonga_ps->performance_levels[i].pcie_gen;
5143
5144                                 if (data->pcie_gen_power_saving.min >
5145                                                 tonga_ps->performance_levels[i].pcie_gen)
5146                                         data->pcie_gen_power_saving.min =
5147                                                         tonga_ps->performance_levels[i].pcie_gen;
5148
5149                                 if (data->pcie_lane_power_saving.max <
5150                                                 tonga_ps->performance_levels[i].pcie_lane)
5151                                         data->pcie_lane_power_saving.max =
5152                                                         tonga_ps->performance_levels[i].pcie_lane;
5153
5154                                 if (data->pcie_lane_power_saving.min >
5155                                                 tonga_ps->performance_levels[i].pcie_lane)
5156                                         data->pcie_lane_power_saving.min =
5157                                                         tonga_ps->performance_levels[i].pcie_lane;
5158                         }
5159                         break;
5160                 default:
5161                         break;
5162                 }
5163         }
5164         return 0;
5165 }
5166
5167 static void
5168 tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
5169 {
5170         uint32_t sclk, mclk, activity_percent;
5171         uint32_t offset;
5172         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5173
5174         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
5175
5176         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5177
5178         smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
5179
5180         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5181         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n", mclk/100, sclk/100);
5182
5183         offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
5184         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
5185         activity_percent += 0x80;
5186         activity_percent >>= 8;
5187
5188         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
5189
5190         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
5191
5192         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
5193 }
5194
5195 static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
5196 {
5197         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5198         const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5199         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5200         struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
5201         uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5202         struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
5203         uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5204         struct PP_Clocks min_clocks = {0};
5205         uint32_t i;
5206         struct cgs_display_info info = {0};
5207
5208         data->need_update_smu7_dpm_table = 0;
5209
5210         for (i = 0; i < psclk_table->count; i++) {
5211                 if (sclk == psclk_table->dpm_levels[i].value)
5212                         break;
5213         }
5214
5215         if (i >= psclk_table->count)
5216                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5217         else {
5218         /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/
5219                 if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
5220                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
5221         }
5222
5223         for (i=0; i < pmclk_table->count; i++) {
5224                 if (mclk == pmclk_table->dpm_levels[i].value)
5225                         break;
5226         }
5227
5228         if (i >= pmclk_table->count)
5229                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5230
5231         cgs_get_active_displays_info(hwmgr->device, &info);
5232
5233         if (data->display_timing.num_existing_displays != info.display_count)
5234                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
5235
5236         return 0;
5237 }
5238
5239 static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps)
5240 {
5241         uint32_t i;
5242         uint32_t sclk, max_sclk = 0;
5243         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5244         struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5245
5246         for (i = 0; i < hw_ps->performance_level_count; i++) {
5247                 sclk = hw_ps->performance_levels[i].engine_clock;
5248                 if (max_sclk < sclk)
5249                         max_sclk = sclk;
5250         }
5251
5252         for (i = 0; i < pdpm_table->sclk_table.count; i++) {
5253                 if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk)
5254                         return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ?
5255                                         pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value :
5256                                         pdpm_table->pcie_speed_table.dpm_levels[i].value);
5257         }
5258
5259         return 0;
5260 }
5261
5262 static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
5263 {
5264         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5265         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5266         const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5267         const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5268
5269         uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps);
5270         uint16_t current_link_speed;
5271
5272         if (data->force_pcie_gen == PP_PCIEGenInvalid)
5273                 current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps);
5274         else
5275                 current_link_speed = data->force_pcie_gen;
5276
5277         data->force_pcie_gen = PP_PCIEGenInvalid;
5278         data->pspp_notify_required = false;
5279         if (target_link_speed > current_link_speed) {
5280                 switch(target_link_speed) {
5281                 case PP_PCIEGen3:
5282                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
5283                                 break;
5284                         data->force_pcie_gen = PP_PCIEGen2;
5285                         if (current_link_speed == PP_PCIEGen2)
5286                                 break;
5287                 case PP_PCIEGen2:
5288                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
5289                                 break;
5290                 default:
5291                         data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr);
5292                         break;
5293                 }
5294         } else {
5295                 if (target_link_speed < current_link_speed)
5296                         data->pspp_notify_required = true;
5297         }
5298
5299         return 0;
5300 }
5301
5302 static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5303 {
5304         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5305
5306         if (0 == data->need_update_smu7_dpm_table)
5307                 return 0;
5308
5309         if ((0 == data->sclk_dpm_key_disabled) &&
5310                 (data->need_update_smu7_dpm_table &
5311                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5312                 PP_ASSERT_WITH_CODE(
5313                         0 == tonga_is_dpm_running(hwmgr),
5314                         "Trying to freeze SCLK DPM when DPM is disabled",
5315                         );
5316                 PP_ASSERT_WITH_CODE(
5317                         0 == smum_send_msg_to_smc(hwmgr->smumgr,
5318                                           PPSMC_MSG_SCLKDPM_FreezeLevel),
5319                         "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
5320                         return -1);
5321         }
5322
5323         if ((0 == data->mclk_dpm_key_disabled) &&
5324                 (data->need_update_smu7_dpm_table &
5325                  DPMTABLE_OD_UPDATE_MCLK)) {
5326                 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
5327                         "Trying to freeze MCLK DPM when DPM is disabled",
5328                         );
5329                 PP_ASSERT_WITH_CODE(
5330                         0 == smum_send_msg_to_smc(hwmgr->smumgr,
5331                                                         PPSMC_MSG_MCLKDPM_FreezeLevel),
5332                         "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
5333                         return -1);
5334         }
5335
5336         return 0;
5337 }
5338
5339 static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
5340 {
5341         int result = 0;
5342
5343         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5344         const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5345         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5346         uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5347         uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5348         struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5349
5350         struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
5351         uint32_t dpm_count, clock_percent;
5352         uint32_t i;
5353
5354         if (0 == data->need_update_smu7_dpm_table)
5355                 return 0;
5356
5357         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
5358                 pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
5359
5360                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5361                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5362                 /* Need to do calculation based on the golden DPM table
5363                  * as the Heatmap GPU Clock axis is also based on the default values
5364                  */
5365                         PP_ASSERT_WITH_CODE(
5366                                 (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
5367                                 "Divide by 0!",
5368                                 return -1);
5369                         dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
5370                         for (i = dpm_count; i > 1; i--) {
5371                                 if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
5372                                         clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
5373                                                         pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5374
5375                                         pdpm_table->sclk_table.dpm_levels[i].value =
5376                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value +
5377                                                         (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5378
5379                                 } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
5380                                         clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
5381                                                                 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5382
5383                                         pdpm_table->sclk_table.dpm_levels[i].value =
5384                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value -
5385                                                         (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5386                                 } else
5387                                         pdpm_table->sclk_table.dpm_levels[i].value =
5388                                                         pgolden_dpm_table->sclk_table.dpm_levels[i].value;
5389                         }
5390                 }
5391         }
5392
5393         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
5394                 pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
5395
5396                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5397                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5398
5399                         PP_ASSERT_WITH_CODE(
5400                                         (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
5401                                         "Divide by 0!",
5402                                         return -1);
5403                         dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
5404                         for (i = dpm_count; i > 1; i--) {
5405                                 if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
5406                                                 clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
5407                                                                     pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5408
5409                                                 pdpm_table->mclk_table.dpm_levels[i].value =
5410                                                                                 pgolden_dpm_table->mclk_table.dpm_levels[i].value +
5411                                                                                 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5412
5413                                 } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
5414                                                 clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
5415                                                                     pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5416
5417                                                 pdpm_table->mclk_table.dpm_levels[i].value =
5418                                                                         pgolden_dpm_table->mclk_table.dpm_levels[i].value -
5419                                                                         (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5420                                 } else
5421                                         pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
5422                         }
5423                 }
5424         }
5425
5426         if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
5427                 result = tonga_populate_all_graphic_levels(hwmgr);
5428                 PP_ASSERT_WITH_CODE((0 == result),
5429                         "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
5430                         return result);
5431         }
5432
5433         if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
5434                 /*populate MCLK dpm table to SMU7 */
5435                 result = tonga_populate_all_memory_levels(hwmgr);
5436                 PP_ASSERT_WITH_CODE((0 == result),
5437                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
5438                                 return result);
5439         }
5440
5441         return result;
5442 }
5443
5444 static  int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
5445                           struct tonga_single_dpm_table * pdpm_table,
5446                              uint32_t low_limit, uint32_t high_limit)
5447 {
5448         uint32_t i;
5449
5450         for (i = 0; i < pdpm_table->count; i++) {
5451                 if ((pdpm_table->dpm_levels[i].value < low_limit) ||
5452                     (pdpm_table->dpm_levels[i].value > high_limit))
5453                         pdpm_table->dpm_levels[i].enabled = false;
5454                 else
5455                         pdpm_table->dpm_levels[i].enabled = true;
5456         }
5457         return 0;
5458 }
5459
5460 static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state)
5461 {
5462         int result = 0;
5463         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5464         uint32_t high_limit_count;
5465
5466         PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
5467                                 "power state did not have any performance level",
5468                                  return -1);
5469
5470         high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
5471
5472         tonga_trim_single_dpm_states(hwmgr,
5473                                         &(data->dpm_table.sclk_table),
5474                                         hw_state->performance_levels[0].engine_clock,
5475                                         hw_state->performance_levels[high_limit_count].engine_clock);
5476
5477         tonga_trim_single_dpm_states(hwmgr,
5478                                                 &(data->dpm_table.mclk_table),
5479                                                 hw_state->performance_levels[0].memory_clock,
5480                                                 hw_state->performance_levels[high_limit_count].memory_clock);
5481
5482         return result;
5483 }
5484
5485 static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
5486 {
5487         int result;
5488         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5489         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5490         const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5491
5492         result = tonga_trim_dpm_states(hwmgr, tonga_ps);
5493         if (0 != result)
5494                 return result;
5495
5496         data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
5497         data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
5498         data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
5499         if (data->uvd_enabled)
5500                 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
5501
5502         data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
5503
5504         return 0;
5505 }
5506
5507 int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
5508 {
5509         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5510                                   (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
5511                                   (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
5512 }
5513
5514 int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
5515 {
5516         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5517                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
5518                                   (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
5519 }
5520
5521 int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
5522 {
5523         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5524         uint32_t mm_boot_level_offset, mm_boot_level_value;
5525         struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5526
5527         if (!bgate) {
5528                 data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1);
5529                 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
5530                 mm_boot_level_offset /= 4;
5531                 mm_boot_level_offset *= 4;
5532                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5533                 mm_boot_level_value &= 0x00FFFFFF;
5534                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
5535                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5536
5537                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) ||
5538                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5539                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5540                                                 PPSMC_MSG_UVDDPM_SetEnabledMask,
5541                                                 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
5542         }
5543
5544         return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
5545 }
5546
5547 int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
5548 {
5549         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5550         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5551         const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5552         const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5553
5554         uint32_t mm_boot_level_offset, mm_boot_level_value;
5555         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5556
5557         if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
5558                 data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
5559
5560                 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
5561                 mm_boot_level_offset /= 4;
5562                 mm_boot_level_offset *= 4;
5563                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5564                 mm_boot_level_value &= 0xFF00FFFF;
5565                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
5566                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5567
5568                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5569                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5570                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
5571                                 (uint32_t)(1 << data->smc_state_table.VceBootLevel));
5572
5573                 tonga_enable_disable_vce_dpm(hwmgr, true);
5574         } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
5575                 tonga_enable_disable_vce_dpm(hwmgr, false);
5576
5577         return 0;
5578 }
5579
5580 static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
5581 {
5582         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5583
5584         uint32_t address;
5585         int32_t result;
5586
5587         if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
5588                 return 0;
5589
5590
5591         memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters));
5592
5593         result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
5594
5595         if(result != 0)
5596                 return result;
5597
5598
5599         address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
5600
5601         return  tonga_copy_bytes_to_smc(hwmgr->smumgr, address,
5602                                  (uint8_t *)&data->mc_reg_table.data[0],
5603                                 sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
5604                                 data->sram_end);
5605 }
5606
5607 static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
5608 {
5609         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5610
5611         if (data->need_update_smu7_dpm_table &
5612                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
5613                 return tonga_program_memory_timing_parameters(hwmgr);
5614
5615         return 0;
5616 }
5617
5618 static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5619 {
5620         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5621
5622         if (0 == data->need_update_smu7_dpm_table)
5623                 return 0;
5624
5625         if ((0 == data->sclk_dpm_key_disabled) &&
5626                 (data->need_update_smu7_dpm_table &
5627                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5628
5629                 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
5630                         "Trying to Unfreeze SCLK DPM when DPM is disabled",
5631                         );
5632                 PP_ASSERT_WITH_CODE(
5633                          0 == smum_send_msg_to_smc(hwmgr->smumgr,
5634                                          PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5635                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
5636                         return -1);
5637         }
5638
5639         if ((0 == data->mclk_dpm_key_disabled) &&
5640                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
5641
5642                 PP_ASSERT_WITH_CODE(
5643                                 0 == tonga_is_dpm_running(hwmgr),
5644                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5645                                 );
5646                 PP_ASSERT_WITH_CODE(
5647                          0 == smum_send_msg_to_smc(hwmgr->smumgr,
5648                                          PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5649                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
5650                     return -1);
5651         }
5652
5653         data->need_update_smu7_dpm_table = 0;
5654
5655         return 0;
5656 }
5657
5658 static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
5659 {
5660         const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5661         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5662         const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5663         uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps);
5664         uint8_t  request;
5665
5666         if (data->pspp_notify_required  ||
5667             data->pcie_performance_request) {
5668                 if (target_link_speed == PP_PCIEGen3)
5669                         request = PCIE_PERF_REQ_GEN3;
5670                 else if (target_link_speed == PP_PCIEGen2)
5671                         request = PCIE_PERF_REQ_GEN2;
5672                 else
5673                         request = PCIE_PERF_REQ_GEN1;
5674
5675                 if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) {
5676                         data->pcie_performance_request = false;
5677                         return 0;
5678                 }
5679
5680                 if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
5681                         if (PP_PCIEGen2 == target_link_speed)
5682                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
5683                         else
5684                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
5685                 }
5686         }
5687
5688         data->pcie_performance_request = false;
5689         return 0;
5690 }
5691
5692 static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
5693 {
5694         int tmp_result, result = 0;
5695
5696         tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
5697         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
5698
5699         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5700                 tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input);
5701                 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
5702         }
5703
5704         tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr);
5705         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
5706
5707         tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
5708         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
5709
5710         tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input);
5711         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
5712
5713         tmp_result = tonga_update_vce_dpm(hwmgr, input);
5714         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
5715
5716         tmp_result = tonga_update_sclk_threshold(hwmgr);
5717         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
5718
5719         tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr);
5720         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
5721
5722         tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr);
5723         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
5724
5725         tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr);
5726         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
5727
5728         tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr);
5729         PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
5730
5731         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5732                 tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input);
5733                 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
5734         }
5735
5736         return result;
5737 }
5738
5739 /**
5740 *  Set maximum target operating fan output PWM
5741 *
5742 * @param    pHwMgr:  the address of the powerplay hardware manager.
5743 * @param    usMaxFanPwm:  max operating fan PWM in percents
5744 * @return   The response that came from the SMC.
5745 */
5746 static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5747 {
5748         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5749
5750         if (phm_is_hw_access_blocked(hwmgr))
5751                 return 0;
5752
5753         return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1);
5754 }
5755
5756 int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
5757 {
5758         uint32_t num_active_displays = 0;
5759         struct cgs_display_info info = {0};
5760         info.mode_info = NULL;
5761
5762         cgs_get_active_displays_info(hwmgr->device, &info);
5763
5764         num_active_displays = info.display_count;
5765
5766         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5767                 tonga_notify_smc_display_change(hwmgr, false);
5768         else
5769                 tonga_notify_smc_display_change(hwmgr, true);
5770
5771         return 0;
5772 }
5773
5774 /**
5775 * Programs the display gap
5776 *
5777 * @param    hwmgr  the address of the powerplay hardware manager.
5778 * @return   always OK
5779 */
5780 int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
5781 {
5782         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5783         uint32_t num_active_displays = 0;
5784         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5785         uint32_t display_gap2;
5786         uint32_t pre_vbi_time_in_us;
5787         uint32_t frame_time_in_us;
5788         uint32_t ref_clock;
5789         uint32_t refresh_rate = 0;
5790         struct cgs_display_info info = {0};
5791         struct cgs_mode_info mode_info;
5792
5793         info.mode_info = &mode_info;
5794
5795         cgs_get_active_displays_info(hwmgr->device, &info);
5796         num_active_displays = info.display_count;
5797
5798         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5799         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
5800
5801         ref_clock = mode_info.ref_clock;
5802         refresh_rate = mode_info.refresh_rate;
5803
5804         if(0 == refresh_rate)
5805                 refresh_rate = 60;
5806
5807         frame_time_in_us = 1000000 / refresh_rate;
5808
5809         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5810         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5811
5812         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5813
5814         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64);
5815
5816         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
5817
5818         if (num_active_displays == 1)
5819                 tonga_notify_smc_display_change(hwmgr, true);
5820
5821         return 0;
5822 }
5823
5824 int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5825 {
5826
5827         tonga_program_display_gap(hwmgr);
5828
5829         /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */
5830         return 0;
5831 }
5832
5833 /**
5834 *  Set maximum target operating fan output RPM
5835 *
5836 * @param    pHwMgr:  the address of the powerplay hardware manager.
5837 * @param    usMaxFanRpm:  max operating fan RPM value.
5838 * @return   The response that came from the SMC.
5839 */
5840 static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5841 {
5842         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
5843
5844         if (phm_is_hw_access_blocked(hwmgr))
5845                 return 0;
5846
5847         return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1);
5848 }
5849
5850 uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
5851 {
5852         uint32_t reference_clock;
5853         uint32_t tc;
5854         uint32_t divide;
5855
5856         ATOM_FIRMWARE_INFO *fw_info;
5857         uint16_t size;
5858         uint8_t frev, crev;
5859         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5860
5861         tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
5862
5863         if (tc)
5864                 return TCLK;
5865
5866         fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
5867                                                   &size, &frev, &crev);
5868
5869         if (!fw_info)
5870                 return 0;
5871
5872         reference_clock = le16_to_cpu(fw_info->usReferenceClock);
5873
5874         divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
5875
5876         if (0 != divide)
5877                 return reference_clock / 4;
5878
5879         return reference_clock;
5880 }
5881
5882 int tonga_dpm_set_interrupt_state(void *private_data,
5883                                          unsigned src_id, unsigned type,
5884                                          int enabled)
5885 {
5886         uint32_t cg_thermal_int;
5887         struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5888
5889         if (hwmgr == NULL)
5890                 return -EINVAL;
5891
5892         switch (type) {
5893         case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5894                 if (enabled) {
5895                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5896                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5897                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5898                 } else {
5899                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5900                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5901                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5902                 }
5903                 break;
5904
5905         case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5906                 if (enabled) {
5907                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5908                         cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5909                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5910                 } else {
5911                         cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5912                         cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5913                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5914                 }
5915                 break;
5916         default:
5917                 break;
5918         }
5919         return 0;
5920 }
5921
5922 int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5923                                         const void *thermal_interrupt_info)
5924 {
5925         int result;
5926         const struct pp_interrupt_registration_info *info =
5927                         (const struct pp_interrupt_registration_info *)thermal_interrupt_info;
5928
5929         if (info == NULL)
5930                 return -EINVAL;
5931
5932         result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5933                                 tonga_dpm_set_interrupt_state,
5934                                 info->call_back, info->context);
5935
5936         if (result)
5937                 return -EINVAL;
5938
5939         result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5940                                 tonga_dpm_set_interrupt_state,
5941                                 info->call_back, info->context);
5942
5943         if (result)
5944                 return -EINVAL;
5945
5946         return 0;
5947 }
5948
5949 bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5950 {
5951         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5952         bool is_update_required = false;
5953         struct cgs_display_info info = {0,0,NULL};
5954
5955         cgs_get_active_displays_info(hwmgr->device, &info);
5956
5957         if (data->display_timing.num_existing_displays != info.display_count)
5958                 is_update_required = true;
5959 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5960         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5961                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5962                 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5963                         is_update_required = true;
5964 */
5965         return is_update_required;
5966 }
5967
5968 static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1,
5969                                                            const struct tonga_performance_level *pl2)
5970 {
5971         return ((pl1->memory_clock == pl2->memory_clock) &&
5972                   (pl1->engine_clock == pl2->engine_clock) &&
5973                   (pl1->pcie_gen == pl2->pcie_gen) &&
5974                   (pl1->pcie_lane == pl2->pcie_lane));
5975 }
5976
5977 int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5978 {
5979         const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
5980         const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
5981         int i;
5982
5983         if (equal == NULL || psa == NULL || psb == NULL)
5984                 return -EINVAL;
5985
5986         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5987         if (psa->performance_level_count != psb->performance_level_count) {
5988                 *equal = false;
5989                 return 0;
5990         }
5991
5992         for (i = 0; i < psa->performance_level_count; i++) {
5993                 if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5994                         /* If we have found even one performance level pair that is different the states are different. */
5995                         *equal = false;
5996                         return 0;
5997                 }
5998         }
5999
6000         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6001         *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
6002         *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
6003         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
6004         *equal &= (psa->acp_clk == psb->acp_clk);
6005
6006         return 0;
6007 }
6008
6009 static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
6010 {
6011         if (mode) {
6012                 /* stop auto-manage */
6013                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
6014                                 PHM_PlatformCaps_MicrocodeFanControl))
6015                         tonga_fan_ctrl_stop_smc_fan_control(hwmgr);
6016                 tonga_fan_ctrl_set_static_mode(hwmgr, mode);
6017         } else
6018                 /* restart auto-manage */
6019                 tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr);
6020
6021         return 0;
6022 }
6023
6024 static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr)
6025 {
6026         if (hwmgr->fan_ctrl_is_in_default_mode)
6027                 return hwmgr->fan_ctrl_default_mode;
6028         else
6029                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
6030                                 CG_FDO_CTRL2, FDO_PWM_MODE);
6031 }
6032
6033 static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
6034 {
6035         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6036
6037         if (!data->soft_pp_table) {
6038                 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
6039                                               hwmgr->soft_pp_table_size,
6040                                               GFP_KERNEL);
6041                 if (!data->soft_pp_table)
6042                         return -ENOMEM;
6043         }
6044
6045         *table = (char *)&data->soft_pp_table;
6046
6047         return hwmgr->soft_pp_table_size;
6048 }
6049
6050 static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
6051 {
6052         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6053
6054         if (!data->soft_pp_table) {
6055                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
6056                 if (!data->soft_pp_table)
6057                         return -ENOMEM;
6058         }
6059
6060         memcpy(data->soft_pp_table, buf, size);
6061
6062         hwmgr->soft_pp_table = data->soft_pp_table;
6063
6064         /* TODO: re-init powerplay to implement modified pptable */
6065
6066         return 0;
6067 }
6068
6069 static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
6070                 enum pp_clock_type type, uint32_t mask)
6071 {
6072         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6073
6074         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
6075                 return -EINVAL;
6076
6077         switch (type) {
6078         case PP_SCLK:
6079                 if (!data->sclk_dpm_key_disabled)
6080                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6081                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
6082                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
6083                 break;
6084         case PP_MCLK:
6085                 if (!data->mclk_dpm_key_disabled)
6086                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6087                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
6088                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
6089                 break;
6090         case PP_PCIE:
6091         {
6092                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
6093                 uint32_t level = 0;
6094
6095                 while (tmp >>= 1)
6096                         level++;
6097
6098                 if (!data->pcie_dpm_key_disabled)
6099                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6100                                         PPSMC_MSG_PCIeDPM_ForceLevel,
6101                                         level);
6102                 break;
6103         }
6104         default:
6105                 break;
6106         }
6107
6108         return 0;
6109 }
6110
6111 static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr,
6112                 enum pp_clock_type type, char *buf)
6113 {
6114         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6115         struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
6116         struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
6117         struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
6118         int i, now, size = 0;
6119         uint32_t clock, pcie_speed;
6120
6121         switch (type) {
6122         case PP_SCLK:
6123                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
6124                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6125
6126                 for (i = 0; i < sclk_table->count; i++) {
6127                         if (clock > sclk_table->dpm_levels[i].value)
6128                                 continue;
6129                         break;
6130                 }
6131                 now = i;
6132
6133                 for (i = 0; i < sclk_table->count; i++)
6134                         size += sprintf(buf + size, "%d: %uMhz %s\n",
6135                                         i, sclk_table->dpm_levels[i].value / 100,
6136                                         (i == now) ? "*" : "");
6137                 break;
6138         case PP_MCLK:
6139                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
6140                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6141
6142                 for (i = 0; i < mclk_table->count; i++) {
6143                         if (clock > mclk_table->dpm_levels[i].value)
6144                                 continue;
6145                         break;
6146                 }
6147                 now = i;
6148
6149                 for (i = 0; i < mclk_table->count; i++)
6150                         size += sprintf(buf + size, "%d: %uMhz %s\n",
6151                                         i, mclk_table->dpm_levels[i].value / 100,
6152                                         (i == now) ? "*" : "");
6153                 break;
6154         case PP_PCIE:
6155                 pcie_speed = tonga_get_current_pcie_speed(hwmgr);
6156                 for (i = 0; i < pcie_table->count; i++) {
6157                         if (pcie_speed != pcie_table->dpm_levels[i].value)
6158                                 continue;
6159                         break;
6160                 }
6161                 now = i;
6162
6163                 for (i = 0; i < pcie_table->count; i++)
6164                         size += sprintf(buf + size, "%d: %s %s\n", i,
6165                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
6166                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6167                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6168                                         (i == now) ? "*" : "");
6169                 break;
6170         default:
6171                 break;
6172         }
6173         return size;
6174 }
6175
6176 static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
6177         .backend_init = &tonga_hwmgr_backend_init,
6178         .backend_fini = &tonga_hwmgr_backend_fini,
6179         .asic_setup = &tonga_setup_asic_task,
6180         .dynamic_state_management_enable = &tonga_enable_dpm_tasks,
6181         .apply_state_adjust_rules = tonga_apply_state_adjust_rules,
6182         .force_dpm_level = &tonga_force_dpm_level,
6183         .power_state_set = tonga_set_power_state_tasks,
6184         .get_power_state_size = tonga_get_power_state_size,
6185         .get_mclk = tonga_dpm_get_mclk,
6186         .get_sclk = tonga_dpm_get_sclk,
6187         .patch_boot_state = tonga_dpm_patch_boot_state,
6188         .get_pp_table_entry = tonga_get_pp_table_entry,
6189         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
6190         .print_current_perforce_level = tonga_print_current_perforce_level,
6191         .powerdown_uvd = tonga_phm_powerdown_uvd,
6192         .powergate_uvd = tonga_phm_powergate_uvd,
6193         .powergate_vce = tonga_phm_powergate_vce,
6194         .disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
6195         .update_clock_gatings = tonga_phm_update_clock_gatings,
6196         .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
6197         .display_config_changed = tonga_display_configuration_changed_task,
6198         .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
6199         .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output,
6200         .get_temperature = tonga_thermal_get_temperature,
6201         .stop_thermal_controller = tonga_thermal_stop_thermal_controller,
6202         .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info,
6203         .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent,
6204         .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent,
6205         .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default,
6206         .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm,
6207         .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
6208         .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
6209         .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
6210         .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
6211         .check_states_equal = tonga_check_states_equal,
6212         .set_fan_control_mode = tonga_set_fan_control_mode,
6213         .get_fan_control_mode = tonga_get_fan_control_mode,
6214         .get_pp_table = tonga_get_pp_table,
6215         .set_pp_table = tonga_set_pp_table,
6216         .force_clock_level = tonga_force_clock_level,
6217         .print_clock_levels = tonga_print_clock_levels,
6218 };
6219
6220 int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
6221 {
6222         tonga_hwmgr  *data;
6223
6224         data = kzalloc (sizeof(tonga_hwmgr), GFP_KERNEL);
6225         if (data == NULL)
6226                 return -ENOMEM;
6227         memset(data, 0x00, sizeof(tonga_hwmgr));
6228
6229         hwmgr->backend = data;
6230         hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
6231         hwmgr->pptable_func = &tonga_pptable_funcs;
6232         pp_tonga_thermal_initialize(hwmgr);
6233         return 0;
6234 }
6235